drivers/net/mvpp2/mrvl_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017-2021 Marvell International Ltd.
   3  * Copyright(c) 2017-2021 Semihalf.
   4  * All rights reserved.
   5  */
   6
   7 #include <rte_string_fns.h>
   8 #include <ethdev_driver.h>
   9 #include <rte_kvargs.h>
  10 #include <rte_log.h>
  11 #include <rte_malloc.h>
  12 #include <rte_bus_vdev.h>
  13
  14 #include <fcntl.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/sockios.h>
  17 #include <net/if.h>
  18 #include <net/if_arp.h>
  19 #include <sys/ioctl.h>
  20 #include <sys/socket.h>
  21 #include <sys/stat.h>
  22 #include <sys/types.h>
  23
  24 #include <rte_mvep_common.h>
  25 #include "mrvl_ethdev.h"
  26 #include "mrvl_qos.h"
  27 #include "mrvl_flow.h"
  28 #include "mrvl_mtr.h"
  29 #include "mrvl_tm.h"
  30
  31 /* bitmask with reserved hifs */
  32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  33 /* bitmask with reserved bpools */
  34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  35 /* bitmask with reserved kernel RSS tables */
  36 #define MRVL_MUSDK_RSS_RESERVED 0x0F
  37 /* maximum number of available hifs */
  38 #define MRVL_MUSDK_HIFS_MAX 9
  39
  40 /* prefetch shift */
  41 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  42
  43 /* TCAM has 25 entries reserved for uc/mc filter entries
  44  * + 1 for primary mac address
  45  */
  46 #define MRVL_MAC_ADDRS_MAX (1 + 25)
  47 #define MRVL_MATCH_LEN 16
  48 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  49 /* Maximum allowable packet size */
  50 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  51
  52 #define MRVL_IFACE_NAME_ARG "iface"
  53 #define MRVL_CFG_ARG "cfg"
  54
  55 #define MRVL_BURST_SIZE 64
  56
  57 #define MRVL_ARP_LENGTH 28
  58
  59 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  60 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
  61
  62 /** Port Rx offload capabilities */
  63 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
  64                           DEV_RX_OFFLOAD_JUMBO_FRAME | \
  65                           DEV_RX_OFFLOAD_CHECKSUM)
  66
  67 /** Port Tx offloads capabilities */
  68 #define MRVL_TX_OFFLOAD_CHECKSUM (DEV_TX_OFFLOAD_IPV4_CKSUM | \
  69                                   DEV_TX_OFFLOAD_UDP_CKSUM  | \
  70                                   DEV_TX_OFFLOAD_TCP_CKSUM)
  71 #define MRVL_TX_OFFLOADS (MRVL_TX_OFFLOAD_CHECKSUM | \
  72                           DEV_TX_OFFLOAD_MULTI_SEGS)
  73
  74 #define MRVL_TX_PKT_OFFLOADS (PKT_TX_IP_CKSUM | \
  75                               PKT_TX_TCP_CKSUM | \
  76                               PKT_TX_UDP_CKSUM)
  77
  78 static const char * const valid_args[] = {
  79         MRVL_IFACE_NAME_ARG,
  80         MRVL_CFG_ARG,
  81         NULL
  82 };
  83
  84 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
  85 static struct pp2_hif *hifs[RTE_MAX_LCORE];
  86 static int used_bpools[PP2_NUM_PKT_PROC] = {
  87         [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
  88 };
  89
  90 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
  91 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
  92 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
  93
  94 struct mrvl_ifnames {
  95         const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
  96         int idx;
  97 };
  98
  99 /*
 100  * To use buffer harvesting based on loopback port shadow queue structure
 101  * was introduced for buffers information bookkeeping.
 102  *
 103  * Before sending the packet, related buffer information (pp2_buff_inf) is
 104  * stored in shadow queue. After packet is transmitted no longer used
 105  * packet buffer is released back to it's original hardware pool,
 106  * on condition it originated from interface.
 107  * In case it  was generated by application itself i.e: mbuf->port field is
 108  * 0xff then its released to software mempool.
 109  */
 110 struct mrvl_shadow_txq {
 111         int head;           /* write index - used when sending buffers */
 112         int tail;           /* read index - used when releasing buffers */
 113         u16 size;           /* queue occupied size */
 114         u16 num_to_release; /* number of descriptors sent, that can be
 115                              * released
 116                              */
 117         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 118 };
 119
 120 struct mrvl_rxq {
 121         struct mrvl_priv *priv;
 122         struct rte_mempool *mp;
 123         int queue_id;
 124         int port_id;
 125         int cksum_enabled;
 126         uint64_t bytes_recv;
 127         uint64_t drop_mac;
 128 };
 129
 130 struct mrvl_txq {
 131         struct mrvl_priv *priv;
 132         int queue_id;
 133         int port_id;
 134         uint64_t bytes_sent;
 135         struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
 136         int tx_deferred_start;
 137 };
 138
 139 static int mrvl_lcore_first;
 140 static int mrvl_lcore_last;
 141 static int mrvl_dev_num;
 142
 143 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
 144 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
 145                         struct pp2_hif *hif, unsigned int core_id,
 146                         struct mrvl_shadow_txq *sq, int qid, int force);
 147
 148 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
 149                                   uint16_t nb_pkts);
 150 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
 151                                      uint16_t nb_pkts);
 152 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev);
 153 static void mrvl_deinit_pp2(void);
 154 static void mrvl_deinit_hifs(void);
 155
 156 static int
 157 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 158                   uint32_t index, uint32_t vmdq __rte_unused);
 159 static int
 160 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
 161 static int
 162 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
 163 static int mrvl_promiscuous_enable(struct rte_eth_dev *dev);
 164 static int mrvl_allmulticast_enable(struct rte_eth_dev *dev);
 165
 166 #define MRVL_XSTATS_TBL_ENTRY(name) { \
 167         #name, offsetof(struct pp2_ppio_statistics, name),      \
 168         sizeof(((struct pp2_ppio_statistics *)0)->name)         \
 169 }
 170
 171 /* Table with xstats data */
 172 static struct {
 173         const char *name;
 174         unsigned int offset;
 175         unsigned int size;
 176 } mrvl_xstats_tbl[] = {
 177         MRVL_XSTATS_TBL_ENTRY(rx_bytes),
 178         MRVL_XSTATS_TBL_ENTRY(rx_packets),
 179         MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
 180         MRVL_XSTATS_TBL_ENTRY(rx_errors),
 181         MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
 182         MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
 183         MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
 184         MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
 185         MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
 186         MRVL_XSTATS_TBL_ENTRY(tx_bytes),
 187         MRVL_XSTATS_TBL_ENTRY(tx_packets),
 188         MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
 189         MRVL_XSTATS_TBL_ENTRY(tx_errors)
 190 };
 191
 192 static inline void
 193 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
 194 {
 195         sq->ent[sq->head].buff.cookie = (uint64_t)buf;
 196         sq->ent[sq->head].buff.addr = buf ?
 197                 rte_mbuf_data_iova_default(buf) : 0;
 198
 199         sq->ent[sq->head].bpool =
 200                 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS ||
 201                  buf->refcnt > 1)) ? NULL :
 202                  mrvl_port_to_bpool_lookup[buf->port];
 203
 204         sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
 205         sq->size++;
 206 }
 207
 208 static inline void
 209 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
 210 {
 211         pp2_ppio_outq_desc_reset(desc);
 212         pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf));
 213         pp2_ppio_outq_desc_set_pkt_offset(desc, 0);
 214         pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf));
 215 }
 216
 217 static inline int
 218 mrvl_get_bpool_size(int pp2_id, int pool_id)
 219 {
 220         int i;
 221         int size = 0;
 222
 223         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 224                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 225
 226         return size;
 227 }
 228
 229 static inline int
 230 mrvl_reserve_bit(int *bitmap, int max)
 231 {
 232         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 233
 234         if (n >= max)
 235                 return -1;
 236
 237         *bitmap |= 1 << n;
 238
 239         return n;
 240 }
 241
 242 static int
 243 mrvl_init_hif(int core_id)
 244 {
 245         struct pp2_hif_params params;
 246         char match[MRVL_MATCH_LEN];
 247         int ret;
 248
 249         ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
 250         if (ret < 0) {
 251                 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
 252                 return ret;
 253         }
 254
 255         snprintf(match, sizeof(match), "hif-%d", ret);
 256         memset(&params, 0, sizeof(params));
 257         params.match = match;
 258         params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
 259         ret = pp2_hif_init(&params, &hifs[core_id]);
 260         if (ret) {
 261                 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
 262                 return ret;
 263         }
 264
 265         return 0;
 266 }
 267
 268 static inline struct pp2_hif*
 269 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
 270 {
 271         int ret;
 272
 273         if (likely(hifs[core_id] != NULL))
 274                 return hifs[core_id];
 275
 276         rte_spinlock_lock(&priv->lock);
 277
 278         ret = mrvl_init_hif(core_id);
 279         if (ret < 0) {
 280                 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
 281                 goto out;
 282         }
 283
 284         if (core_id < mrvl_lcore_first)
 285                 mrvl_lcore_first = core_id;
 286
 287         if (core_id > mrvl_lcore_last)
 288                 mrvl_lcore_last = core_id;
 289 out:
 290         rte_spinlock_unlock(&priv->lock);
 291
 292         return hifs[core_id];
 293 }
 294
 295 /**
 296  * Set tx burst function according to offload flag
 297  *
 298  * @param dev
 299  *   Pointer to Ethernet device structure.
 300  */
 301 static void
 302 mrvl_set_tx_function(struct rte_eth_dev *dev)
 303 {
 304         struct mrvl_priv *priv = dev->data->dev_private;
 305
 306         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 307         if (priv->multiseg) {
 308                 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n");
 309                 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst;
 310         } else {
 311                 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n");
 312                 dev->tx_pkt_burst = mrvl_tx_pkt_burst;
 313         }
 314 }
 315
 316 /**
 317  * Configure rss based on dpdk rss configuration.
 318  *
 319  * @param priv
 320  *   Pointer to private structure.
 321  * @param rss_conf
 322  *   Pointer to RSS configuration.
 323  *
 324  * @return
 325  *   0 on success, negative error value otherwise.
 326  */
 327 static int
 328 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 329 {
 330         if (rss_conf->rss_key)
 331                 MRVL_LOG(WARNING, "Changing hash key is not supported");
 332
 333         if (rss_conf->rss_hf == 0) {
 334                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 335         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 336                 priv->ppio_params.inqs_params.hash_type =
 337                         PP2_PPIO_HASH_T_2_TUPLE;
 338         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 339                 priv->ppio_params.inqs_params.hash_type =
 340                         PP2_PPIO_HASH_T_5_TUPLE;
 341                 priv->rss_hf_tcp = 1;
 342         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 343                 priv->ppio_params.inqs_params.hash_type =
 344                         PP2_PPIO_HASH_T_5_TUPLE;
 345                 priv->rss_hf_tcp = 0;
 346         } else {
 347                 return -EINVAL;
 348         }
 349
 350         return 0;
 351 }
 352
 353 /**
 354  * Ethernet device configuration.
 355  *
 356  * Prepare the driver for a given number of TX and RX queues and
 357  * configure RSS.
 358  *
 359  * @param dev
 360  *   Pointer to Ethernet device structure.
 361  *
 362  * @return
 363  *   0 on success, negative error value otherwise.
 364  */
 365 static int
 366 mrvl_dev_configure(struct rte_eth_dev *dev)
 367 {
 368         struct mrvl_priv *priv = dev->data->dev_private;
 369         int ret;
 370
 371         if (priv->ppio) {
 372                 MRVL_LOG(INFO, "Device reconfiguration is not supported");
 373                 return -EINVAL;
 374         }
 375
 376         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 377             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 378                 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
 379                         dev->data->dev_conf.rxmode.mq_mode);
 380                 return -EINVAL;
 381         }
 382
 383         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 384                 MRVL_LOG(INFO, "Split headers not supported");
 385                 return -EINVAL;
 386         }
 387
 388         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 389                 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
 390                                  MRVL_PP2_ETH_HDRS_LEN;
 391
 392         if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 393                 priv->multiseg = 1;
 394
 395         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 396                                   dev->data->nb_rx_queues);
 397         if (ret < 0)
 398                 return ret;
 399
 400         ret = mrvl_configure_txqs(priv, dev->data->port_id,
 401                                   dev->data->nb_tx_queues);
 402         if (ret < 0)
 403                 return ret;
 404
 405         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 406         priv->ppio_params.maintain_stats = 1;
 407         priv->nb_rx_queues = dev->data->nb_rx_queues;
 408
 409         ret = mrvl_tm_init(dev);
 410         if (ret < 0)
 411                 return ret;
 412
 413         if (dev->data->nb_rx_queues == 1 &&
 414             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 415                 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
 416                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 417
 418                 return 0;
 419         }
 420
 421         return mrvl_configure_rss(priv,
 422                         &dev->data->dev_conf.rx_adv_conf.rss_conf);
 423 }
 424
 425 /**
 426  * DPDK callback to change the MTU.
 427  *
 428  * Setting the MTU affects hardware MRU (packets larger than the MRU
 429  * will be dropped).
 430  *
 431  * @param dev
 432  *   Pointer to Ethernet device structure.
 433  * @param mtu
 434  *   New MTU.
 435  *
 436  * @return
 437  *   0 on success, negative error value otherwise.
 438  */
 439 static int
 440 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 441 {
 442         struct mrvl_priv *priv = dev->data->dev_private;
 443         uint16_t mru;
 444         uint16_t mbuf_data_size = 0; /* SW buffer size */
 445         int ret;
 446
 447         mru = MRVL_PP2_MTU_TO_MRU(mtu);
 448         /*
 449          * min_rx_buf_size is equal to mbuf data size
 450          * if pmd didn't set it differently
 451          */
 452         mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 453         /* Prevent PMD from:
 454          * - setting mru greater than the mbuf size resulting in
 455          * hw and sw buffer size mismatch
 456          * - setting mtu that requires the support of scattered packets
 457          * when this feature has not been enabled/supported so far
 458          * (TODO check scattered_rx flag here once scattered RX is supported).
 459          */
 460         if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) {
 461                 mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS;
 462                 mtu = MRVL_PP2_MRU_TO_MTU(mru);
 463                 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
 464                         "by current mbuf size: %u. Set MTU to %u, MRU to %u",
 465                         mbuf_data_size, mtu, mru);
 466         }
 467
 468         if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
 469                 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
 470                 return -EINVAL;
 471         }
 472
 473         dev->data->mtu = mtu;
 474         dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE;
 475
 476         if (!priv->ppio)
 477                 return 0;
 478
 479         ret = pp2_ppio_set_mru(priv->ppio, mru);
 480         if (ret) {
 481                 MRVL_LOG(ERR, "Failed to change MRU");
 482                 return ret;
 483         }
 484
 485         ret = pp2_ppio_set_mtu(priv->ppio, mtu);
 486         if (ret) {
 487                 MRVL_LOG(ERR, "Failed to change MTU");
 488                 return ret;
 489         }
 490
 491         return 0;
 492 }
 493
 494 /**
 495  * DPDK callback to bring the link up.
 496  *
 497  * @param dev
 498  *   Pointer to Ethernet device structure.
 499  *
 500  * @return
 501  *   0 on success, negative error value otherwise.
 502  */
 503 static int
 504 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 505 {
 506         struct mrvl_priv *priv = dev->data->dev_private;
 507         int ret;
 508
 509         if (!priv->ppio) {
 510                 dev->data->dev_link.link_status = ETH_LINK_UP;
 511                 return 0;
 512         }
 513
 514         ret = pp2_ppio_enable(priv->ppio);
 515         if (ret)
 516                 return ret;
 517
 518         /*
 519          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 520          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 521          * PP2_TRAFFIC_INGRESS_EGRESS.
 522          *
 523          * Set mtu to default DPDK value here.
 524          */
 525         ret = mrvl_mtu_set(dev, dev->data->mtu);
 526         if (ret) {
 527                 pp2_ppio_disable(priv->ppio);
 528                 return ret;
 529         }
 530
 531         dev->data->dev_link.link_status = ETH_LINK_UP;
 532         return 0;
 533 }
 534
 535 /**
 536  * DPDK callback to bring the link down.
 537  *
 538  * @param dev
 539  *   Pointer to Ethernet device structure.
 540  *
 541  * @return
 542  *   0 on success, negative error value otherwise.
 543  */
 544 static int
 545 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 546 {
 547         struct mrvl_priv *priv = dev->data->dev_private;
 548         int ret;
 549
 550         if (!priv->ppio) {
 551                 dev->data->dev_link.link_status = ETH_LINK_DOWN;
 552                 return 0;
 553         }
 554         ret = pp2_ppio_disable(priv->ppio);
 555         if (ret)
 556                 return ret;
 557
 558         dev->data->dev_link.link_status = ETH_LINK_DOWN;
 559         return 0;
 560 }
 561
 562 /**
 563  * DPDK callback to start tx queue.
 564  *
 565  * @param dev
 566  *   Pointer to Ethernet device structure.
 567  * @param queue_id
 568  *   Transmit queue index.
 569  *
 570  * @return
 571  *   0 on success, negative error value otherwise.
 572  */
 573 static int
 574 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
 575 {
 576         struct mrvl_priv *priv = dev->data->dev_private;
 577         int ret;
 578
 579         if (!priv)
 580                 return -EPERM;
 581
 582         /* passing 1 enables given tx queue */
 583         ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
 584         if (ret) {
 585                 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
 586                 return ret;
 587         }
 588
 589         dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 590
 591         return 0;
 592 }
 593
 594 /**
 595  * DPDK callback to stop tx queue.
 596  *
 597  * @param dev
 598  *   Pointer to Ethernet device structure.
 599  * @param queue_id
 600  *   Transmit queue index.
 601  *
 602  * @return
 603  *   0 on success, negative error value otherwise.
 604  */
 605 static int
 606 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
 607 {
 608         struct mrvl_priv *priv = dev->data->dev_private;
 609         int ret;
 610
 611         if (!priv->ppio)
 612                 return -EPERM;
 613
 614         /* passing 0 disables given tx queue */
 615         ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
 616         if (ret) {
 617                 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
 618                 return ret;
 619         }
 620
 621         dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 622
 623         return 0;
 624 }
 625
 626 /**
 627  * Populate VLAN Filter configuration.
 628  *
 629  * @param dev
 630  *   Pointer to Ethernet device structure.
 631  * @param on
 632  *   Toggle filter.
 633  *
 634  * @return
 635  *   0 on success, negative error value otherwise.
 636  */
 637 static int mrvl_populate_vlan_table(struct rte_eth_dev *dev, int on)
 638 {
 639         uint32_t j;
 640         int ret;
 641         struct rte_vlan_filter_conf *vfc;
 642
 643         vfc = &dev->data->vlan_filter_conf;
 644         for (j = 0; j < RTE_DIM(vfc->ids); j++) {
 645                 uint64_t vlan;
 646                 uint64_t vbit;
 647                 uint64_t ids = vfc->ids[j];
 648
 649                 if (ids == 0)
 650                         continue;
 651
 652                 while (ids) {
 653                         vlan = 64 * j;
 654                         /* count trailing zeroes */
 655                         vbit = ~ids & (ids - 1);
 656                         /* clear least significant bit set */
 657                         ids ^= (ids ^ (ids - 1)) ^ vbit;
 658                         for (; vbit; vlan++)
 659                                 vbit >>= 1;
 660                         ret = mrvl_vlan_filter_set(dev, vlan, on);
 661                         if (ret) {
 662                                 MRVL_LOG(ERR, "Failed to setup VLAN filter\n");
 663                                 return ret;
 664                         }
 665                 }
 666         }
 667
 668         return 0;
 669 }
 670
 671 /**
 672  * DPDK callback to start the device.
 673  *
 674  * @param dev
 675  *   Pointer to Ethernet device structure.
 676  *
 677  * @return
 678  *   0 on success, negative errno value on failure.
 679  */
 680 static int
 681 mrvl_dev_start(struct rte_eth_dev *dev)
 682 {
 683         struct mrvl_priv *priv = dev->data->dev_private;
 684         char match[MRVL_MATCH_LEN];
 685         int ret = 0, i, def_init_size;
 686         struct rte_ether_addr *mac_addr;
 687
 688         if (priv->ppio)
 689                 return mrvl_dev_set_link_up(dev);
 690
 691         snprintf(match, sizeof(match), "ppio-%d:%d",
 692                  priv->pp_id, priv->ppio_id);
 693         priv->ppio_params.match = match;
 694         priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH;
 695         if (mrvl_cfg)
 696                 priv->ppio_params.eth_start_hdr =
 697                         mrvl_cfg->port[dev->data->port_id].eth_start_hdr;
 698
 699         /*
 700          * Calculate the minimum bpool size for refill feature as follows:
 701          * 2 default burst sizes multiply by number of rx queues.
 702          * If the bpool size will be below this value, new buffers will
 703          * be added to the pool.
 704          */
 705         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 706
 707         /* In case initial bpool size configured in queues setup is
 708          * smaller than minimum size add more buffers
 709          */
 710         def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
 711         if (priv->bpool_init_size < def_init_size) {
 712                 int buffs_to_add = def_init_size - priv->bpool_init_size;
 713
 714                 priv->bpool_init_size += buffs_to_add;
 715                 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
 716                 if (ret)
 717                         MRVL_LOG(ERR, "Failed to add buffers to bpool");
 718         }
 719
 720         /*
 721          * Calculate the maximum bpool size for refill feature as follows:
 722          * maximum number of descriptors in rx queue multiply by number
 723          * of rx queues plus minimum bpool size.
 724          * In case the bpool size will exceed this value, superfluous buffers
 725          * will be removed
 726          */
 727         priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
 728                                 priv->bpool_min_size;
 729
 730         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 731         if (ret) {
 732                 MRVL_LOG(ERR, "Failed to init ppio");
 733                 return ret;
 734         }
 735
 736         /*
 737          * In case there are some some stale uc/mc mac addresses flush them
 738          * here. It cannot be done during mrvl_dev_close() as port information
 739          * is already gone at that point (due to pp2_ppio_deinit() in
 740          * mrvl_dev_stop()).
 741          */
 742         if (!priv->uc_mc_flushed) {
 743                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 744                 if (ret) {
 745                         MRVL_LOG(ERR,
 746                                 "Failed to flush uc/mc filter list");
 747                         goto out;
 748                 }
 749                 priv->uc_mc_flushed = 1;
 750         }
 751
 752         ret = mrvl_mtu_set(dev, dev->data->mtu);
 753         if (ret)
 754                 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
 755
 756         if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0]))
 757                 mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]);
 758
 759         for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) {
 760                 mac_addr = &dev->data->mac_addrs[i];
 761
 762                 /* skip zero address */
 763                 if (rte_is_zero_ether_addr(mac_addr))
 764                         continue;
 765
 766                 mrvl_mac_addr_add(dev, mac_addr, i, 0);
 767         }
 768
 769         if (dev->data->all_multicast == 1)
 770                 mrvl_allmulticast_enable(dev);
 771
 772         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 773                 ret = mrvl_populate_vlan_table(dev, 1);
 774                 if (ret) {
 775                         MRVL_LOG(ERR, "Failed to populate VLAN table");
 776                         goto out;
 777                 }
 778         }
 779
 780         /* For default QoS config, don't start classifier. */
 781         if (mrvl_cfg  &&
 782             mrvl_cfg->port[dev->data->port_id].use_global_defaults == 0) {
 783                 ret = mrvl_start_qos_mapping(priv);
 784                 if (ret) {
 785                         MRVL_LOG(ERR, "Failed to setup QoS mapping");
 786                         goto out;
 787                 }
 788         }
 789
 790         ret = pp2_ppio_set_loopback(priv->ppio, dev->data->dev_conf.lpbk_mode);
 791         if (ret) {
 792                 MRVL_LOG(ERR, "Failed to set loopback");
 793                 goto out;
 794         }
 795
 796         if (dev->data->promiscuous == 1)
 797                 mrvl_promiscuous_enable(dev);
 798
 799         if (dev->data->dev_link.link_status == ETH_LINK_UP) {
 800                 ret = mrvl_dev_set_link_up(dev);
 801                 if (ret) {
 802                         MRVL_LOG(ERR, "Failed to set link up");
 803                         dev->data->dev_link.link_status = ETH_LINK_DOWN;
 804                         goto out;
 805                 }
 806         }
 807
 808         /* start tx queues */
 809         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 810                 struct mrvl_txq *txq = dev->data->tx_queues[i];
 811
 812                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
 813
 814                 if (!txq->tx_deferred_start)
 815                         continue;
 816
 817                 /*
 818                  * All txqs are started by default. Stop them
 819                  * so that tx_deferred_start works as expected.
 820                  */
 821                 ret = mrvl_tx_queue_stop(dev, i);
 822                 if (ret)
 823                         goto out;
 824         }
 825
 826         mrvl_flow_init(dev);
 827         mrvl_mtr_init(dev);
 828         mrvl_set_tx_function(dev);
 829
 830         return 0;
 831 out:
 832         MRVL_LOG(ERR, "Failed to start device");
 833         pp2_ppio_deinit(priv->ppio);
 834         return ret;
 835 }
 836
 837 /**
 838  * Flush receive queues.
 839  *
 840  * @param dev
 841  *   Pointer to Ethernet device structure.
 842  */
 843 static void
 844 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 845 {
 846         int i;
 847
 848         MRVL_LOG(INFO, "Flushing rx queues");
 849         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 850                 int ret, num;
 851
 852                 do {
 853                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 854                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 855
 856                         num = MRVL_PP2_RXD_MAX;
 857                         ret = pp2_ppio_recv(q->priv->ppio,
 858                                             q->priv->rxq_map[q->queue_id].tc,
 859                                             q->priv->rxq_map[q->queue_id].inq,
 860                                             descs, (uint16_t *)&num);
 861                 } while (ret == 0 && num);
 862         }
 863 }
 864
 865 /**
 866  * Flush transmit shadow queues.
 867  *
 868  * @param dev
 869  *   Pointer to Ethernet device structure.
 870  */
 871 static void
 872 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
 873 {
 874         int i, j;
 875         struct mrvl_txq *txq;
 876
 877         MRVL_LOG(INFO, "Flushing tx shadow queues");
 878         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 879                 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
 880
 881                 for (j = 0; j < RTE_MAX_LCORE; j++) {
 882                         struct mrvl_shadow_txq *sq;
 883
 884                         if (!hifs[j])
 885                                 continue;
 886
 887                         sq = &txq->shadow_txqs[j];
 888                         mrvl_free_sent_buffers(txq->priv->ppio,
 889                                 hifs[j], j, sq, txq->queue_id, 1);
 890                         while (sq->tail != sq->head) {
 891                                 uint64_t addr = cookie_addr_high |
 892                                         sq->ent[sq->tail].buff.cookie;
 893                                 rte_pktmbuf_free(
 894                                         (struct rte_mbuf *)addr);
 895                                 sq->tail = (sq->tail + 1) &
 896                                             MRVL_PP2_TX_SHADOWQ_MASK;
 897                         }
 898                         memset(sq, 0, sizeof(*sq));
 899                 }
 900         }
 901 }
 902
 903 /**
 904  * Flush hardware bpool (buffer-pool).
 905  *
 906  * @param dev
 907  *   Pointer to Ethernet device structure.
 908  */
 909 static void
 910 mrvl_flush_bpool(struct rte_eth_dev *dev)
 911 {
 912         struct mrvl_priv *priv = dev->data->dev_private;
 913         struct pp2_hif *hif;
 914         uint32_t num;
 915         int ret;
 916         unsigned int core_id = rte_lcore_id();
 917
 918         if (core_id == LCORE_ID_ANY)
 919                 core_id = rte_get_main_lcore();
 920
 921         hif = mrvl_get_hif(priv, core_id);
 922
 923         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
 924         if (ret) {
 925                 MRVL_LOG(ERR, "Failed to get bpool buffers number");
 926                 return;
 927         }
 928
 929         while (num--) {
 930                 struct pp2_buff_inf inf;
 931                 uint64_t addr;
 932
 933                 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
 934                 if (ret)
 935                         break;
 936
 937                 addr = cookie_addr_high | inf.cookie;
 938                 rte_pktmbuf_free((struct rte_mbuf *)addr);
 939         }
 940 }
 941
 942 /**
 943  * DPDK callback to stop the device.
 944  *
 945  * @param dev
 946  *   Pointer to Ethernet device structure.
 947  */
 948 static int
 949 mrvl_dev_stop(struct rte_eth_dev *dev)
 950 {
 951         return mrvl_dev_set_link_down(dev);
 952 }
 953
 954 /**
 955  * DPDK callback to close the device.
 956  *
 957  * @param dev
 958  *   Pointer to Ethernet device structure.
 959  */
 960 static int
 961 mrvl_dev_close(struct rte_eth_dev *dev)
 962 {
 963         struct mrvl_priv *priv = dev->data->dev_private;
 964         size_t i;
 965
 966         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 967                 return 0;
 968
 969         mrvl_flush_rx_queues(dev);
 970         mrvl_flush_tx_shadow_queues(dev);
 971         mrvl_flow_deinit(dev);
 972         mrvl_mtr_deinit(dev);
 973
 974         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
 975                 struct pp2_ppio_tc_params *tc_params =
 976                         &priv->ppio_params.inqs_params.tcs_params[i];
 977
 978                 if (tc_params->inqs_params) {
 979                         rte_free(tc_params->inqs_params);
 980                         tc_params->inqs_params = NULL;
 981                 }
 982         }
 983
 984         if (priv->cls_tbl) {
 985                 pp2_cls_tbl_deinit(priv->cls_tbl);
 986                 priv->cls_tbl = NULL;
 987         }
 988
 989         if (priv->qos_tbl) {
 990                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
 991                 priv->qos_tbl = NULL;
 992         }
 993
 994         mrvl_flush_bpool(dev);
 995         mrvl_tm_deinit(dev);
 996
 997         if (priv->ppio) {
 998                 pp2_ppio_deinit(priv->ppio);
 999                 priv->ppio = NULL;
1000         }
1001
1002         /* policer must be released after ppio deinitialization */
1003         if (priv->default_policer) {
1004                 pp2_cls_plcr_deinit(priv->default_policer);
1005                 priv->default_policer = NULL;
1006         }
1007
1008
1009         if (priv->bpool) {
1010                 pp2_bpool_deinit(priv->bpool);
1011                 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
1012                 priv->bpool = NULL;
1013         }
1014
1015         mrvl_dev_num--;
1016
1017         if (mrvl_dev_num == 0) {
1018                 MRVL_LOG(INFO, "Perform MUSDK deinit");
1019                 mrvl_deinit_hifs();
1020                 mrvl_deinit_pp2();
1021                 rte_mvep_deinit(MVEP_MOD_T_PP2);
1022         }
1023
1024         return 0;
1025 }
1026
1027 /**
1028  * DPDK callback to retrieve physical link information.
1029  *
1030  * @param dev
1031  *   Pointer to Ethernet device structure.
1032  * @param wait_to_complete
1033  *   Wait for request completion (ignored).
1034  *
1035  * @return
1036  *   0 on success, negative error value otherwise.
1037  */
1038 static int
1039 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
1040 {
1041         /*
1042          * TODO
1043          * once MUSDK provides necessary API use it here
1044          */
1045         struct mrvl_priv *priv = dev->data->dev_private;
1046         struct ethtool_cmd edata;
1047         struct ifreq req;
1048         int ret, fd, link_up;
1049
1050         if (!priv->ppio)
1051                 return -EPERM;
1052
1053         edata.cmd = ETHTOOL_GSET;
1054
1055         strcpy(req.ifr_name, dev->data->name);
1056         req.ifr_data = (void *)&edata;
1057
1058         fd = socket(AF_INET, SOCK_DGRAM, 0);
1059         if (fd == -1)
1060                 return -EFAULT;
1061
1062         ret = ioctl(fd, SIOCETHTOOL, &req);
1063         if (ret == -1) {
1064                 close(fd);
1065                 return -EFAULT;
1066         }
1067
1068         close(fd);
1069
1070         switch (ethtool_cmd_speed(&edata)) {
1071         case SPEED_10:
1072                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
1073                 break;
1074         case SPEED_100:
1075                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
1076                 break;
1077         case SPEED_1000:
1078                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
1079                 break;
1080         case SPEED_10000:
1081                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
1082                 break;
1083         default:
1084                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
1085         }
1086
1087         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
1088                                                          ETH_LINK_HALF_DUPLEX;
1089         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
1090                                                            ETH_LINK_FIXED;
1091         pp2_ppio_get_link_state(priv->ppio, &link_up);
1092         dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1093
1094         return 0;
1095 }
1096
1097 /**
1098  * DPDK callback to enable promiscuous mode.
1099  *
1100  * @param dev
1101  *   Pointer to Ethernet device structure.
1102  *
1103  * @return
1104  *   0 on success, negative error value otherwise.
1105  */
1106 static int
1107 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
1108 {
1109         struct mrvl_priv *priv = dev->data->dev_private;
1110         int ret;
1111
1112         if (priv->isolated)
1113                 return -ENOTSUP;
1114
1115         if (!priv->ppio)
1116                 return 0;
1117
1118         ret = pp2_ppio_set_promisc(priv->ppio, 1);
1119         if (ret) {
1120                 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
1121                 return -EAGAIN;
1122         }
1123
1124         return 0;
1125 }
1126
1127 /**
1128  * DPDK callback to enable allmulti mode.
1129  *
1130  * @param dev
1131  *   Pointer to Ethernet device structure.
1132  *
1133  * @return
1134  *   0 on success, negative error value otherwise.
1135  */
1136 static int
1137 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
1138 {
1139         struct mrvl_priv *priv = dev->data->dev_private;
1140         int ret;
1141
1142         if (priv->isolated)
1143                 return -ENOTSUP;
1144
1145         if (!priv->ppio)
1146                 return 0;
1147
1148         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
1149         if (ret) {
1150                 MRVL_LOG(ERR, "Failed enable all-multicast mode");
1151                 return -EAGAIN;
1152         }
1153
1154         return 0;
1155 }
1156
1157 /**
1158  * DPDK callback to disable promiscuous mode.
1159  *
1160  * @param dev
1161  *   Pointer to Ethernet device structure.
1162  *
1163  * @return
1164  *   0 on success, negative error value otherwise.
1165  */
1166 static int
1167 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
1168 {
1169         struct mrvl_priv *priv = dev->data->dev_private;
1170         int ret;
1171
1172         if (priv->isolated)
1173                 return -ENOTSUP;
1174
1175         if (!priv->ppio)
1176                 return 0;
1177
1178         ret = pp2_ppio_set_promisc(priv->ppio, 0);
1179         if (ret) {
1180                 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
1181                 return -EAGAIN;
1182         }
1183
1184         return 0;
1185 }
1186
1187 /**
1188  * DPDK callback to disable allmulticast mode.
1189  *
1190  * @param dev
1191  *   Pointer to Ethernet device structure.
1192  *
1193  * @return
1194  *   0 on success, negative error value otherwise.
1195  */
1196 static int
1197 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
1198 {
1199         struct mrvl_priv *priv = dev->data->dev_private;
1200         int ret;
1201
1202         if (priv->isolated)
1203                 return -ENOTSUP;
1204
1205         if (!priv->ppio)
1206                 return 0;
1207
1208         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
1209         if (ret) {
1210                 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1211                 return -EAGAIN;
1212         }
1213
1214         return 0;
1215 }
1216
1217 /**
1218  * DPDK callback to remove a MAC address.
1219  *
1220  * @param dev
1221  *   Pointer to Ethernet device structure.
1222  * @param index
1223  *   MAC address index.
1224  */
1225 static void
1226 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1227 {
1228         struct mrvl_priv *priv = dev->data->dev_private;
1229         char buf[RTE_ETHER_ADDR_FMT_SIZE];
1230         int ret;
1231
1232         if (priv->isolated)
1233                 return;
1234
1235         if (!priv->ppio)
1236                 return;
1237
1238         ret = pp2_ppio_remove_mac_addr(priv->ppio,
1239                                        dev->data->mac_addrs[index].addr_bytes);
1240         if (ret) {
1241                 rte_ether_format_addr(buf, sizeof(buf),
1242                                   &dev->data->mac_addrs[index]);
1243                 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1244         }
1245 }
1246
1247 /**
1248  * DPDK callback to add a MAC address.
1249  *
1250  * @param dev
1251  *   Pointer to Ethernet device structure.
1252  * @param mac_addr
1253  *   MAC address to register.
1254  * @param index
1255  *   MAC address index.
1256  * @param vmdq
1257  *   VMDq pool index to associate address with (unused).
1258  *
1259  * @return
1260  *   0 on success, negative error value otherwise.
1261  */
1262 static int
1263 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1264                   uint32_t index, uint32_t vmdq __rte_unused)
1265 {
1266         struct mrvl_priv *priv = dev->data->dev_private;
1267         char buf[RTE_ETHER_ADDR_FMT_SIZE];
1268         int ret;
1269
1270         if (priv->isolated)
1271                 return -ENOTSUP;
1272
1273         if (!priv->ppio)
1274                 return 0;
1275
1276         if (index == 0)
1277                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1278                 return -1;
1279
1280         /*
1281          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1282          * parameter uc_filter_max. Maximum number of mc addresses is then
1283          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1284          * 21 respectively.
1285          *
1286          * If more than uc_filter_max uc addresses were added to filter list
1287          * then NIC will switch to promiscuous mode automatically.
1288          *
1289          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1290          * were added to filter list then NIC will switch to all-multicast mode
1291          * automatically.
1292          */
1293         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1294         if (ret) {
1295                 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1296                 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1297                 return -1;
1298         }
1299
1300         return 0;
1301 }
1302
1303 /**
1304  * DPDK callback to set the primary MAC address.
1305  *
1306  * @param dev
1307  *   Pointer to Ethernet device structure.
1308  * @param mac_addr
1309  *   MAC address to register.
1310  *
1311  * @return
1312  *   0 on success, negative error value otherwise.
1313  */
1314 static int
1315 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1316 {
1317         struct mrvl_priv *priv = dev->data->dev_private;
1318         int ret;
1319
1320         if (priv->isolated)
1321                 return -ENOTSUP;
1322
1323         if (!priv->ppio)
1324                 return 0;
1325
1326         ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1327         if (ret) {
1328                 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1329                 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1330                 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1331         }
1332
1333         return ret;
1334 }
1335
1336 /**
1337  * DPDK callback to get device statistics.
1338  *
1339  * @param dev
1340  *   Pointer to Ethernet device structure.
1341  * @param stats
1342  *   Stats structure output buffer.
1343  *
1344  * @return
1345  *   0 on success, negative error value otherwise.
1346  */
1347 static int
1348 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1349 {
1350         struct mrvl_priv *priv = dev->data->dev_private;
1351         struct pp2_ppio_statistics ppio_stats;
1352         uint64_t drop_mac = 0;
1353         unsigned int i, idx, ret;
1354
1355         if (!priv->ppio)
1356                 return -EPERM;
1357
1358         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1359                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1360                 struct pp2_ppio_inq_statistics rx_stats;
1361
1362                 if (!rxq)
1363                         continue;
1364
1365                 idx = rxq->queue_id;
1366                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1367                         MRVL_LOG(ERR,
1368                                 "rx queue %d stats out of range (0 - %d)",
1369                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1370                         continue;
1371                 }
1372
1373                 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1374                                                   priv->rxq_map[idx].tc,
1375                                                   priv->rxq_map[idx].inq,
1376                                                   &rx_stats, 0);
1377                 if (unlikely(ret)) {
1378                         MRVL_LOG(ERR,
1379                                 "Failed to update rx queue %d stats", idx);
1380                         break;
1381                 }
1382
1383                 stats->q_ibytes[idx] = rxq->bytes_recv;
1384                 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1385                 stats->q_errors[idx] = rx_stats.drop_early +
1386                                        rx_stats.drop_fullq +
1387                                        rx_stats.drop_bm +
1388                                        rxq->drop_mac;
1389                 stats->ibytes += rxq->bytes_recv;
1390                 drop_mac += rxq->drop_mac;
1391         }
1392
1393         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1394                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1395                 struct pp2_ppio_outq_statistics tx_stats;
1396
1397                 if (!txq)
1398                         continue;
1399
1400                 idx = txq->queue_id;
1401                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1402                         MRVL_LOG(ERR,
1403                                 "tx queue %d stats out of range (0 - %d)",
1404                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1405                 }
1406
1407                 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1408                                                    &tx_stats, 0);
1409                 if (unlikely(ret)) {
1410                         MRVL_LOG(ERR,
1411                                 "Failed to update tx queue %d stats", idx);
1412                         break;
1413                 }
1414
1415                 stats->q_opackets[idx] = tx_stats.deq_desc;
1416                 stats->q_obytes[idx] = txq->bytes_sent;
1417                 stats->obytes += txq->bytes_sent;
1418         }
1419
1420         ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1421         if (unlikely(ret)) {
1422                 MRVL_LOG(ERR, "Failed to update port statistics");
1423                 return ret;
1424         }
1425
1426         stats->ipackets += ppio_stats.rx_packets - drop_mac;
1427         stats->opackets += ppio_stats.tx_packets;
1428         stats->imissed += ppio_stats.rx_fullq_dropped +
1429                           ppio_stats.rx_bm_dropped +
1430                           ppio_stats.rx_early_dropped +
1431                           ppio_stats.rx_fifo_dropped +
1432                           ppio_stats.rx_cls_dropped;
1433         stats->ierrors = drop_mac;
1434
1435         return 0;
1436 }
1437
1438 /**
1439  * DPDK callback to clear device statistics.
1440  *
1441  * @param dev
1442  *   Pointer to Ethernet device structure.
1443  *
1444  * @return
1445  *   0 on success, negative error value otherwise.
1446  */
1447 static int
1448 mrvl_stats_reset(struct rte_eth_dev *dev)
1449 {
1450         struct mrvl_priv *priv = dev->data->dev_private;
1451         int i;
1452
1453         if (!priv->ppio)
1454                 return 0;
1455
1456         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1457                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1458
1459                 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1460                                             priv->rxq_map[i].inq, NULL, 1);
1461                 rxq->bytes_recv = 0;
1462                 rxq->drop_mac = 0;
1463         }
1464
1465         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1466                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1467
1468                 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1469                 txq->bytes_sent = 0;
1470         }
1471
1472         return pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1473 }
1474
1475 /**
1476  * DPDK callback to get extended statistics.
1477  *
1478  * @param dev
1479  *   Pointer to Ethernet device structure.
1480  * @param stats
1481  *   Pointer to xstats table.
1482  * @param n
1483  *   Number of entries in xstats table.
1484  * @return
1485  *   Negative value on error, number of read xstats otherwise.
1486  */
1487 static int
1488 mrvl_xstats_get(struct rte_eth_dev *dev,
1489                 struct rte_eth_xstat *stats, unsigned int n)
1490 {
1491         struct mrvl_priv *priv = dev->data->dev_private;
1492         struct pp2_ppio_statistics ppio_stats;
1493         unsigned int i;
1494
1495         if (!stats)
1496                 return 0;
1497
1498         pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1499         for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1500                 uint64_t val;
1501
1502                 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1503                         val = *(uint32_t *)((uint8_t *)&ppio_stats +
1504                                             mrvl_xstats_tbl[i].offset);
1505                 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1506                         val = *(uint64_t *)((uint8_t *)&ppio_stats +
1507                                             mrvl_xstats_tbl[i].offset);
1508                 else
1509                         return -EINVAL;
1510
1511                 stats[i].id = i;
1512                 stats[i].value = val;
1513         }
1514
1515         return n;
1516 }
1517
1518 /**
1519  * DPDK callback to reset extended statistics.
1520  *
1521  * @param dev
1522  *   Pointer to Ethernet device structure.
1523  *
1524  * @return
1525  *   0 on success, negative error value otherwise.
1526  */
1527 static int
1528 mrvl_xstats_reset(struct rte_eth_dev *dev)
1529 {
1530         return mrvl_stats_reset(dev);
1531 }
1532
1533 /**
1534  * DPDK callback to get extended statistics names.
1535  *
1536  * @param dev (unused)
1537  *   Pointer to Ethernet device structure.
1538  * @param xstats_names
1539  *   Pointer to xstats names table.
1540  * @param size
1541  *   Size of the xstats names table.
1542  * @return
1543  *   Number of read names.
1544  */
1545 static int
1546 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1547                       struct rte_eth_xstat_name *xstats_names,
1548                       unsigned int size)
1549 {
1550         unsigned int i;
1551
1552         if (!xstats_names)
1553                 return RTE_DIM(mrvl_xstats_tbl);
1554
1555         for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1556                 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name,
1557                         RTE_ETH_XSTATS_NAME_SIZE);
1558
1559         return size;
1560 }
1561
1562 /**
1563  * DPDK callback to get information about the device.
1564  *
1565  * @param dev
1566  *   Pointer to Ethernet device structure (unused).
1567  * @param info
1568  *   Info structure output buffer.
1569  */
1570 static int
1571 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1572                    struct rte_eth_dev_info *info)
1573 {
1574         info->speed_capa = ETH_LINK_SPEED_10M |
1575                            ETH_LINK_SPEED_100M |
1576                            ETH_LINK_SPEED_1G |
1577                            ETH_LINK_SPEED_10G;
1578
1579         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1580         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1581         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1582
1583         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1584         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1585         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1586
1587         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1588         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1589         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1590
1591         info->rx_offload_capa = MRVL_RX_OFFLOADS;
1592         info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1593
1594         info->tx_offload_capa = MRVL_TX_OFFLOADS;
1595         info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1596
1597         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1598                                        ETH_RSS_NONFRAG_IPV4_TCP |
1599                                        ETH_RSS_NONFRAG_IPV4_UDP;
1600
1601         /* By default packets are dropped if no descriptors are available */
1602         info->default_rxconf.rx_drop_en = 1;
1603
1604         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1605
1606         return 0;
1607 }
1608
1609 /**
1610  * Return supported packet types.
1611  *
1612  * @param dev
1613  *   Pointer to Ethernet device structure (unused).
1614  *
1615  * @return
1616  *   Const pointer to the table with supported packet types.
1617  */
1618 static const uint32_t *
1619 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1620 {
1621         static const uint32_t ptypes[] = {
1622                 RTE_PTYPE_L2_ETHER,
1623                 RTE_PTYPE_L2_ETHER_VLAN,
1624                 RTE_PTYPE_L2_ETHER_QINQ,
1625                 RTE_PTYPE_L3_IPV4,
1626                 RTE_PTYPE_L3_IPV4_EXT,
1627                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1628                 RTE_PTYPE_L3_IPV6,
1629                 RTE_PTYPE_L3_IPV6_EXT,
1630                 RTE_PTYPE_L2_ETHER_ARP,
1631                 RTE_PTYPE_L4_TCP,
1632                 RTE_PTYPE_L4_UDP
1633         };
1634
1635         return ptypes;
1636 }
1637
1638 /**
1639  * DPDK callback to get information about specific receive queue.
1640  *
1641  * @param dev
1642  *   Pointer to Ethernet device structure.
1643  * @param rx_queue_id
1644  *   Receive queue index.
1645  * @param qinfo
1646  *   Receive queue information structure.
1647  */
1648 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1649                               struct rte_eth_rxq_info *qinfo)
1650 {
1651         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1652         struct mrvl_priv *priv = dev->data->dev_private;
1653         int inq = priv->rxq_map[rx_queue_id].inq;
1654         int tc = priv->rxq_map[rx_queue_id].tc;
1655         struct pp2_ppio_tc_params *tc_params =
1656                 &priv->ppio_params.inqs_params.tcs_params[tc];
1657
1658         qinfo->mp = q->mp;
1659         qinfo->nb_desc = tc_params->inqs_params[inq].size;
1660 }
1661
1662 /**
1663  * DPDK callback to get information about specific transmit queue.
1664  *
1665  * @param dev
1666  *   Pointer to Ethernet device structure.
1667  * @param tx_queue_id
1668  *   Transmit queue index.
1669  * @param qinfo
1670  *   Transmit queue information structure.
1671  */
1672 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1673                               struct rte_eth_txq_info *qinfo)
1674 {
1675         struct mrvl_priv *priv = dev->data->dev_private;
1676         struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1677
1678         qinfo->nb_desc =
1679                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1680         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1681 }
1682
1683 /**
1684  * DPDK callback to Configure a VLAN filter.
1685  *
1686  * @param dev
1687  *   Pointer to Ethernet device structure.
1688  * @param vlan_id
1689  *   VLAN ID to filter.
1690  * @param on
1691  *   Toggle filter.
1692  *
1693  * @return
1694  *   0 on success, negative error value otherwise.
1695  */
1696 static int
1697 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1698 {
1699         struct mrvl_priv *priv = dev->data->dev_private;
1700
1701         if (priv->isolated)
1702                 return -ENOTSUP;
1703
1704         if (!priv->ppio)
1705                 return 0;
1706
1707         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1708                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1709 }
1710
1711 /**
1712  * DPDK callback to Configure VLAN offload.
1713  *
1714  * @param dev
1715  *   Pointer to Ethernet device structure.
1716  * @param mask
1717  *   VLAN offload mask.
1718  *
1719  * @return
1720  *   0 on success, negative error value otherwise.
1721  */
1722 static int mrvl_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1723 {
1724         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1725         int ret;
1726
1727         if (mask & ETH_VLAN_STRIP_MASK)
1728                 MRVL_LOG(ERR, "VLAN stripping is not supported\n");
1729
1730         if (mask & ETH_VLAN_FILTER_MASK) {
1731                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1732                         ret = mrvl_populate_vlan_table(dev, 1);
1733                 else
1734                         ret = mrvl_populate_vlan_table(dev, 0);
1735
1736                 if (ret)
1737                         return ret;
1738         }
1739
1740         if (mask & ETH_VLAN_EXTEND_MASK)
1741                 MRVL_LOG(ERR, "Extend VLAN not supported\n");
1742
1743         return 0;
1744 }
1745
1746 /**
1747  * Release buffers to hardware bpool (buffer-pool)
1748  *
1749  * @param rxq
1750  *   Receive queue pointer.
1751  * @param num
1752  *   Number of buffers to release to bpool.
1753  *
1754  * @return
1755  *   0 on success, negative error value otherwise.
1756  */
1757 static int
1758 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1759 {
1760         struct buff_release_entry entries[num];
1761         struct rte_mbuf *mbufs[num];
1762         int i, ret;
1763         unsigned int core_id;
1764         struct pp2_hif *hif;
1765         struct pp2_bpool *bpool;
1766
1767         core_id = rte_lcore_id();
1768         if (core_id == LCORE_ID_ANY)
1769                 core_id = rte_get_main_lcore();
1770
1771         hif = mrvl_get_hif(rxq->priv, core_id);
1772         if (!hif)
1773                 return -1;
1774
1775         bpool = rxq->priv->bpool;
1776
1777         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1778         if (ret)
1779                 return ret;
1780
1781         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1782                 cookie_addr_high =
1783                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1784
1785         for (i = 0; i < num; i++) {
1786                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1787                         != cookie_addr_high) {
1788                         MRVL_LOG(ERR,
1789                                 "mbuf virtual addr high is out of range "
1790                                 "0x%x instead of 0x%x\n",
1791                                 (uint32_t)((uint64_t)mbufs[i] >> 32),
1792                                 (uint32_t)(cookie_addr_high >> 32));
1793                         goto out;
1794                 }
1795
1796                 entries[i].buff.addr =
1797                         rte_mbuf_data_iova_default(mbufs[i]);
1798                 entries[i].buff.cookie = (uintptr_t)mbufs[i];
1799                 entries[i].bpool = bpool;
1800         }
1801
1802         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1803         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1804
1805         if (i != num)
1806                 goto out;
1807
1808         return 0;
1809 out:
1810         for (; i < num; i++)
1811                 rte_pktmbuf_free(mbufs[i]);
1812
1813         return -1;
1814 }
1815
1816 /**
1817  * DPDK callback to configure the receive queue.
1818  *
1819  * @param dev
1820  *   Pointer to Ethernet device structure.
1821  * @param idx
1822  *   RX queue index.
1823  * @param desc
1824  *   Number of descriptors to configure in queue.
1825  * @param socket
1826  *   NUMA socket on which memory must be allocated.
1827  * @param conf
1828  *   Thresholds parameters.
1829  * @param mp
1830  *   Memory pool for buffer allocations.
1831  *
1832  * @return
1833  *   0 on success, negative error value otherwise.
1834  */
1835 static int
1836 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1837                     unsigned int socket,
1838                     const struct rte_eth_rxconf *conf,
1839                     struct rte_mempool *mp)
1840 {
1841         struct mrvl_priv *priv = dev->data->dev_private;
1842         struct mrvl_rxq *rxq;
1843         uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1844         uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1845         int ret, tc, inq;
1846         uint64_t offloads;
1847
1848         offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1849
1850         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1851                 /*
1852                  * Unknown TC mapping, mapping will not have a correct queue.
1853                  */
1854                 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1855                         idx, priv->ppio_id);
1856                 return -EFAULT;
1857         }
1858
1859         frame_size = buf_size - RTE_PKTMBUF_HEADROOM -
1860                      MRVL_PKT_EFFEC_OFFS + RTE_ETHER_CRC_LEN;
1861         if (frame_size < max_rx_pkt_len) {
1862                 MRVL_LOG(WARNING,
1863                         "Mbuf size must be increased to %u bytes to hold up "
1864                         "to %u bytes of data.",
1865                         buf_size + max_rx_pkt_len - frame_size,
1866                         max_rx_pkt_len);
1867                 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1868                 MRVL_LOG(INFO, "Setting max rx pkt len to %u",
1869                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
1870         }
1871
1872         if (dev->data->rx_queues[idx]) {
1873                 rte_free(dev->data->rx_queues[idx]);
1874                 dev->data->rx_queues[idx] = NULL;
1875         }
1876
1877         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1878         if (!rxq)
1879                 return -ENOMEM;
1880
1881         rxq->priv = priv;
1882         rxq->mp = mp;
1883         rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1884         rxq->queue_id = idx;
1885         rxq->port_id = dev->data->port_id;
1886         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1887
1888         tc = priv->rxq_map[rxq->queue_id].tc,
1889         inq = priv->rxq_map[rxq->queue_id].inq;
1890         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1891                 desc;
1892
1893         ret = mrvl_fill_bpool(rxq, desc);
1894         if (ret) {
1895                 rte_free(rxq);
1896                 return ret;
1897         }
1898
1899         priv->bpool_init_size += desc;
1900
1901         dev->data->rx_queues[idx] = rxq;
1902
1903         return 0;
1904 }
1905
1906 /**
1907  * DPDK callback to release the receive queue.
1908  *
1909  * @param rxq
1910  *   Generic receive queue pointer.
1911  */
1912 static void
1913 mrvl_rx_queue_release(void *rxq)
1914 {
1915         struct mrvl_rxq *q = rxq;
1916         struct pp2_ppio_tc_params *tc_params;
1917         int i, num, tc, inq;
1918         struct pp2_hif *hif;
1919         unsigned int core_id = rte_lcore_id();
1920
1921         if (core_id == LCORE_ID_ANY)
1922                 core_id = rte_get_main_lcore();
1923
1924         if (!q)
1925                 return;
1926
1927         hif = mrvl_get_hif(q->priv, core_id);
1928
1929         if (!hif)
1930                 return;
1931
1932         tc = q->priv->rxq_map[q->queue_id].tc;
1933         inq = q->priv->rxq_map[q->queue_id].inq;
1934         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1935         num = tc_params->inqs_params[inq].size;
1936         for (i = 0; i < num; i++) {
1937                 struct pp2_buff_inf inf;
1938                 uint64_t addr;
1939
1940                 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1941                 addr = cookie_addr_high | inf.cookie;
1942                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1943         }
1944
1945         rte_free(q);
1946 }
1947
1948 /**
1949  * DPDK callback to configure the transmit queue.
1950  *
1951  * @param dev
1952  *   Pointer to Ethernet device structure.
1953  * @param idx
1954  *   Transmit queue index.
1955  * @param desc
1956  *   Number of descriptors to configure in the queue.
1957  * @param socket
1958  *   NUMA socket on which memory must be allocated.
1959  * @param conf
1960  *   Tx queue configuration parameters.
1961  *
1962  * @return
1963  *   0 on success, negative error value otherwise.
1964  */
1965 static int
1966 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1967                     unsigned int socket,
1968                     const struct rte_eth_txconf *conf)
1969 {
1970         struct mrvl_priv *priv = dev->data->dev_private;
1971         struct mrvl_txq *txq;
1972
1973         if (dev->data->tx_queues[idx]) {
1974                 rte_free(dev->data->tx_queues[idx]);
1975                 dev->data->tx_queues[idx] = NULL;
1976         }
1977
1978         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1979         if (!txq)
1980                 return -ENOMEM;
1981
1982         txq->priv = priv;
1983         txq->queue_id = idx;
1984         txq->port_id = dev->data->port_id;
1985         txq->tx_deferred_start = conf->tx_deferred_start;
1986         dev->data->tx_queues[idx] = txq;
1987
1988         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1989
1990         return 0;
1991 }
1992
1993 /**
1994  * DPDK callback to release the transmit queue.
1995  *
1996  * @param txq
1997  *   Generic transmit queue pointer.
1998  */
1999 static void
2000 mrvl_tx_queue_release(void *txq)
2001 {
2002         struct mrvl_txq *q = txq;
2003
2004         if (!q)
2005                 return;
2006
2007         rte_free(q);
2008 }
2009
2010 /**
2011  * DPDK callback to get flow control configuration.
2012  *
2013  * @param dev
2014  *  Pointer to Ethernet device structure.
2015  * @param fc_conf
2016  *  Pointer to the flow control configuration.
2017  *
2018  * @return
2019  *  0 on success, negative error value otherwise.
2020  */
2021 static int
2022 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2023 {
2024         struct mrvl_priv *priv = dev->data->dev_private;
2025         int ret, en;
2026
2027         if (!priv)
2028                 return -EPERM;
2029
2030         ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
2031         if (ret) {
2032                 MRVL_LOG(ERR, "Failed to read rx pause state");
2033                 return ret;
2034         }
2035
2036         fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
2037
2038         ret = pp2_ppio_get_tx_pause(priv->ppio, &en);
2039         if (ret) {
2040                 MRVL_LOG(ERR, "Failed to read tx pause state");
2041                 return ret;
2042         }
2043
2044         if (en) {
2045                 if (fc_conf->mode == RTE_FC_NONE)
2046                         fc_conf->mode = RTE_FC_TX_PAUSE;
2047                 else
2048                         fc_conf->mode = RTE_FC_FULL;
2049         }
2050
2051         return 0;
2052 }
2053
2054 /**
2055  * DPDK callback to set flow control configuration.
2056  *
2057  * @param dev
2058  *  Pointer to Ethernet device structure.
2059  * @param fc_conf
2060  *  Pointer to the flow control configuration.
2061  *
2062  * @return
2063  *  0 on success, negative error value otherwise.
2064  */
2065 static int
2066 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2067 {
2068         struct mrvl_priv *priv = dev->data->dev_private;
2069         struct pp2_ppio_tx_pause_params mrvl_pause_params;
2070         int ret;
2071         int rx_en, tx_en;
2072
2073         if (!priv)
2074                 return -EPERM;
2075
2076         if (fc_conf->high_water ||
2077             fc_conf->low_water ||
2078             fc_conf->pause_time ||
2079             fc_conf->mac_ctrl_frame_fwd ||
2080             fc_conf->autoneg) {
2081                 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
2082
2083                 return -EINVAL;
2084         }
2085
2086         switch (fc_conf->mode) {
2087         case RTE_FC_FULL:
2088                 rx_en = 1;
2089                 tx_en = 1;
2090                 break;
2091         case RTE_FC_TX_PAUSE:
2092                 rx_en = 0;
2093                 tx_en = 1;
2094                 break;
2095         case RTE_FC_RX_PAUSE:
2096                 rx_en = 1;
2097                 tx_en = 0;
2098                 break;
2099         case RTE_FC_NONE:
2100                 rx_en = 0;
2101                 tx_en = 0;
2102                 break;
2103         default:
2104                 MRVL_LOG(ERR, "Incorrect Flow control flag (%d)",
2105                          fc_conf->mode);
2106                 return -EINVAL;
2107         }
2108
2109         /* Set RX flow control */
2110         ret = pp2_ppio_set_rx_pause(priv->ppio, rx_en);
2111         if (ret) {
2112                 MRVL_LOG(ERR, "Failed to change RX flowctrl");
2113                 return ret;
2114         }
2115
2116         /* Set TX flow control */
2117         mrvl_pause_params.en = tx_en;
2118         /* all inqs participate in xon/xoff decision */
2119         mrvl_pause_params.use_tc_pause_inqs = 0;
2120         ret = pp2_ppio_set_tx_pause(priv->ppio, &mrvl_pause_params);
2121         if (ret) {
2122                 MRVL_LOG(ERR, "Failed to change TX flowctrl");
2123                 return ret;
2124         }
2125
2126         return 0;
2127 }
2128
2129 /**
2130  * Update RSS hash configuration
2131  *
2132  * @param dev
2133  *   Pointer to Ethernet device structure.
2134  * @param rss_conf
2135  *   Pointer to RSS configuration.
2136  *
2137  * @return
2138  *   0 on success, negative error value otherwise.
2139  */
2140 static int
2141 mrvl_rss_hash_update(struct rte_eth_dev *dev,
2142                      struct rte_eth_rss_conf *rss_conf)
2143 {
2144         struct mrvl_priv *priv = dev->data->dev_private;
2145
2146         if (priv->isolated)
2147                 return -ENOTSUP;
2148
2149         return mrvl_configure_rss(priv, rss_conf);
2150 }
2151
2152 /**
2153  * DPDK callback to get RSS hash configuration.
2154  *
2155  * @param dev
2156  *   Pointer to Ethernet device structure.
2157  * @rss_conf
2158  *   Pointer to RSS configuration.
2159  *
2160  * @return
2161  *   Always 0.
2162  */
2163 static int
2164 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
2165                        struct rte_eth_rss_conf *rss_conf)
2166 {
2167         struct mrvl_priv *priv = dev->data->dev_private;
2168         enum pp2_ppio_hash_type hash_type =
2169                 priv->ppio_params.inqs_params.hash_type;
2170
2171         rss_conf->rss_key = NULL;
2172
2173         if (hash_type == PP2_PPIO_HASH_T_NONE)
2174                 rss_conf->rss_hf = 0;
2175         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
2176                 rss_conf->rss_hf = ETH_RSS_IPV4;
2177         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
2178                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
2179         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
2180                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
2181
2182         return 0;
2183 }
2184
2185 /**
2186  * DPDK callback to get rte_flow callbacks.
2187  *
2188  * @param dev
2189  *   Pointer to the device structure.
2190  * @param filer_type
2191  *   Flow filter type.
2192  * @param filter_op
2193  *   Flow filter operation.
2194  * @param arg
2195  *   Pointer to pass the flow ops.
2196  *
2197  * @return
2198  *   0 on success, negative error value otherwise.
2199  */
2200 static int
2201 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
2202                      enum rte_filter_type filter_type,
2203                      enum rte_filter_op filter_op, void *arg)
2204 {
2205         switch (filter_type) {
2206         case RTE_ETH_FILTER_GENERIC:
2207                 if (filter_op != RTE_ETH_FILTER_GET)
2208                         return -EINVAL;
2209                 *(const void **)arg = &mrvl_flow_ops;
2210                 return 0;
2211         default:
2212                 MRVL_LOG(WARNING, "Filter type (%d) not supported",
2213                                 filter_type);
2214                 return -EINVAL;
2215         }
2216 }
2217
2218 /**
2219  * DPDK callback to get rte_mtr callbacks.
2220  *
2221  * @param dev
2222  *   Pointer to the device structure.
2223  * @param ops
2224  *   Pointer to pass the mtr ops.
2225  *
2226  * @return
2227  *   Always 0.
2228  */
2229 static int
2230 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2231 {
2232         *(const void **)ops = &mrvl_mtr_ops;
2233
2234         return 0;
2235 }
2236
2237 /**
2238  * DPDK callback to get rte_tm callbacks.
2239  *
2240  * @param dev
2241  *   Pointer to the device structure.
2242  * @param ops
2243  *   Pointer to pass the tm ops.
2244  *
2245  * @return
2246  *   Always 0.
2247  */
2248 static int
2249 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2250 {
2251         *(const void **)ops = &mrvl_tm_ops;
2252
2253         return 0;
2254 }
2255
2256 static const struct eth_dev_ops mrvl_ops = {
2257         .dev_configure = mrvl_dev_configure,
2258         .dev_start = mrvl_dev_start,
2259         .dev_stop = mrvl_dev_stop,
2260         .dev_set_link_up = mrvl_dev_set_link_up,
2261         .dev_set_link_down = mrvl_dev_set_link_down,
2262         .dev_close = mrvl_dev_close,
2263         .link_update = mrvl_link_update,
2264         .promiscuous_enable = mrvl_promiscuous_enable,
2265         .allmulticast_enable = mrvl_allmulticast_enable,
2266         .promiscuous_disable = mrvl_promiscuous_disable,
2267         .allmulticast_disable = mrvl_allmulticast_disable,
2268         .mac_addr_remove = mrvl_mac_addr_remove,
2269         .mac_addr_add = mrvl_mac_addr_add,
2270         .mac_addr_set = mrvl_mac_addr_set,
2271         .mtu_set = mrvl_mtu_set,
2272         .stats_get = mrvl_stats_get,
2273         .stats_reset = mrvl_stats_reset,
2274         .xstats_get = mrvl_xstats_get,
2275         .xstats_reset = mrvl_xstats_reset,
2276         .xstats_get_names = mrvl_xstats_get_names,
2277         .dev_infos_get = mrvl_dev_infos_get,
2278         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
2279         .rxq_info_get = mrvl_rxq_info_get,
2280         .txq_info_get = mrvl_txq_info_get,
2281         .vlan_filter_set = mrvl_vlan_filter_set,
2282         .vlan_offload_set = mrvl_vlan_offload_set,
2283         .tx_queue_start = mrvl_tx_queue_start,
2284         .tx_queue_stop = mrvl_tx_queue_stop,
2285         .rx_queue_setup = mrvl_rx_queue_setup,
2286         .rx_queue_release = mrvl_rx_queue_release,
2287         .tx_queue_setup = mrvl_tx_queue_setup,
2288         .tx_queue_release = mrvl_tx_queue_release,
2289         .flow_ctrl_get = mrvl_flow_ctrl_get,
2290         .flow_ctrl_set = mrvl_flow_ctrl_set,
2291         .rss_hash_update = mrvl_rss_hash_update,
2292         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
2293         .filter_ctrl = mrvl_eth_filter_ctrl,
2294         .mtr_ops_get = mrvl_mtr_ops_get,
2295         .tm_ops_get = mrvl_tm_ops_get,
2296 };
2297
2298 /**
2299  * Return packet type information and l3/l4 offsets.
2300  *
2301  * @param desc
2302  *   Pointer to the received packet descriptor.
2303  * @param l3_offset
2304  *   l3 packet offset.
2305  * @param l4_offset
2306  *   l4 packet offset.
2307  *
2308  * @return
2309  *   Packet type information.
2310  */
2311 static inline uint64_t
2312 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2313                                     uint8_t *l3_offset, uint8_t *l4_offset)
2314 {
2315         enum pp2_inq_l3_type l3_type;
2316         enum pp2_inq_l4_type l4_type;
2317         enum pp2_inq_vlan_tag vlan_tag;
2318         uint64_t packet_type;
2319
2320         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2321         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2322         pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2323
2324         packet_type = RTE_PTYPE_L2_ETHER;
2325
2326         switch (vlan_tag) {
2327         case PP2_INQ_VLAN_TAG_SINGLE:
2328                 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2329                 break;
2330         case PP2_INQ_VLAN_TAG_DOUBLE:
2331         case PP2_INQ_VLAN_TAG_TRIPLE:
2332                 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2333                 break;
2334         default:
2335                 break;
2336         }
2337
2338         switch (l3_type) {
2339         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2340                 packet_type |= RTE_PTYPE_L3_IPV4;
2341                 break;
2342         case PP2_INQ_L3_TYPE_IPV4_OK:
2343                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2344                 break;
2345         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2346                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2347                 break;
2348         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2349                 packet_type |= RTE_PTYPE_L3_IPV6;
2350                 break;
2351         case PP2_INQ_L3_TYPE_IPV6_EXT:
2352                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2353                 break;
2354         case PP2_INQ_L3_TYPE_ARP:
2355                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2356                 /*
2357                  * In case of ARP l4_offset is set to wrong value.
2358                  * Set it to proper one so that later on mbuf->l3_len can be
2359                  * calculated subtracting l4_offset and l3_offset.
2360                  */
2361                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2362                 break;
2363         default:
2364                 break;
2365         }
2366
2367         switch (l4_type) {
2368         case PP2_INQ_L4_TYPE_TCP:
2369                 packet_type |= RTE_PTYPE_L4_TCP;
2370                 break;
2371         case PP2_INQ_L4_TYPE_UDP:
2372                 packet_type |= RTE_PTYPE_L4_UDP;
2373                 break;
2374         default:
2375                 break;
2376         }
2377
2378         return packet_type;
2379 }
2380
2381 /**
2382  * Get offload information from the received packet descriptor.
2383  *
2384  * @param desc
2385  *   Pointer to the received packet descriptor.
2386  *
2387  * @return
2388  *   Mbuf offload flags.
2389  */
2390 static inline uint64_t
2391 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2392 {
2393         uint64_t flags;
2394         enum pp2_inq_desc_status status;
2395
2396         status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2397         if (unlikely(status != PP2_DESC_ERR_OK))
2398                 flags = PKT_RX_IP_CKSUM_BAD;
2399         else
2400                 flags = PKT_RX_IP_CKSUM_GOOD;
2401
2402         status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2403         if (unlikely(status != PP2_DESC_ERR_OK))
2404                 flags |= PKT_RX_L4_CKSUM_BAD;
2405         else
2406                 flags |= PKT_RX_L4_CKSUM_GOOD;
2407
2408         return flags;
2409 }
2410
2411 /**
2412  * DPDK callback for receive.
2413  *
2414  * @param rxq
2415  *   Generic pointer to the receive queue.
2416  * @param rx_pkts
2417  *   Array to store received packets.
2418  * @param nb_pkts
2419  *   Maximum number of packets in array.
2420  *
2421  * @return
2422  *   Number of packets successfully received.
2423  */
2424 static uint16_t
2425 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2426 {
2427         struct mrvl_rxq *q = rxq;
2428         struct pp2_ppio_desc descs[nb_pkts];
2429         struct pp2_bpool *bpool;
2430         int i, ret, rx_done = 0;
2431         int num;
2432         struct pp2_hif *hif;
2433         unsigned int core_id = rte_lcore_id();
2434
2435         hif = mrvl_get_hif(q->priv, core_id);
2436
2437         if (unlikely(!q->priv->ppio || !hif))
2438                 return 0;
2439
2440         bpool = q->priv->bpool;
2441
2442         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2443                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2444         if (unlikely(ret < 0))
2445                 return 0;
2446
2447         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2448
2449         for (i = 0; i < nb_pkts; i++) {
2450                 struct rte_mbuf *mbuf;
2451                 uint8_t l3_offset, l4_offset;
2452                 enum pp2_inq_desc_status status;
2453                 uint64_t addr;
2454
2455                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2456                         struct pp2_ppio_desc *pref_desc;
2457                         u64 pref_addr;
2458
2459                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2460                         pref_addr = cookie_addr_high |
2461                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
2462                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2463                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2464                 }
2465
2466                 addr = cookie_addr_high |
2467                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
2468                 mbuf = (struct rte_mbuf *)addr;
2469                 rte_pktmbuf_reset(mbuf);
2470
2471                 /* drop packet in case of mac, overrun or resource error */
2472                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2473                 if (unlikely(status != PP2_DESC_ERR_OK)) {
2474                         struct pp2_buff_inf binf = {
2475                                 .addr = rte_mbuf_data_iova_default(mbuf),
2476                                 .cookie = (uint64_t)mbuf,
2477                         };
2478
2479                         pp2_bpool_put_buff(hif, bpool, &binf);
2480                         mrvl_port_bpool_size
2481                                 [bpool->pp2_id][bpool->id][core_id]++;
2482                         q->drop_mac++;
2483                         continue;
2484                 }
2485
2486                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2487                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2488                 mbuf->data_len = mbuf->pkt_len;
2489                 mbuf->port = q->port_id;
2490                 mbuf->packet_type =
2491                         mrvl_desc_to_packet_type_and_offset(&descs[i],
2492                                                             &l3_offset,
2493                                                             &l4_offset);
2494                 mbuf->l2_len = l3_offset;
2495                 mbuf->l3_len = l4_offset - l3_offset;
2496
2497                 if (likely(q->cksum_enabled))
2498                         mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2499
2500                 rx_pkts[rx_done++] = mbuf;
2501                 q->bytes_recv += mbuf->pkt_len;
2502         }
2503
2504         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2505                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2506
2507                 if (unlikely(num <= q->priv->bpool_min_size ||
2508                              (!rx_done && num < q->priv->bpool_init_size))) {
2509                         mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2510                 } else if (unlikely(num > q->priv->bpool_max_size)) {
2511                         int i;
2512                         int pkt_to_remove = num - q->priv->bpool_init_size;
2513                         struct rte_mbuf *mbuf;
2514                         struct pp2_buff_inf buff;
2515
2516                         for (i = 0; i < pkt_to_remove; i++) {
2517                                 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2518                                 if (ret)
2519                                         break;
2520                                 mbuf = (struct rte_mbuf *)
2521                                         (cookie_addr_high | buff.cookie);
2522                                 rte_pktmbuf_free(mbuf);
2523                         }
2524                         mrvl_port_bpool_size
2525                                 [bpool->pp2_id][bpool->id][core_id] -= i;
2526                 }
2527                 rte_spinlock_unlock(&q->priv->lock);
2528         }
2529
2530         return rx_done;
2531 }
2532
2533 /**
2534  * Prepare offload information.
2535  *
2536  * @param ol_flags
2537  *   Offload flags.
2538  * @param l3_type
2539  *   Pointer to the pp2_ouq_l3_type structure.
2540  * @param l4_type
2541  *   Pointer to the pp2_outq_l4_type structure.
2542  * @param gen_l3_cksum
2543  *   Will be set to 1 in case l3 checksum is computed.
2544  * @param l4_cksum
2545  *   Will be set to 1 in case l4 checksum is computed.
2546  */
2547 static inline void
2548 mrvl_prepare_proto_info(uint64_t ol_flags,
2549                         enum pp2_outq_l3_type *l3_type,
2550                         enum pp2_outq_l4_type *l4_type,
2551                         int *gen_l3_cksum,
2552                         int *gen_l4_cksum)
2553 {
2554         /*
2555          * Based on ol_flags prepare information
2556          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2557          * for offloading.
2558          * in most of the checksum cases ipv4 must be set, so this is the
2559          * default value
2560          */
2561         *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2562         *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2563
2564         if (ol_flags & PKT_TX_IPV6) {
2565                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2566                 /* no checksum for ipv6 header */
2567                 *gen_l3_cksum = 0;
2568         }
2569
2570         if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) {
2571                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2572                 *gen_l4_cksum = 1;
2573         } else if ((ol_flags & PKT_TX_L4_MASK) ==  PKT_TX_UDP_CKSUM) {
2574                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2575                 *gen_l4_cksum = 1;
2576         } else {
2577                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2578                 /* no checksum for other type */
2579                 *gen_l4_cksum = 0;
2580         }
2581 }
2582
2583 /**
2584  * Release already sent buffers to bpool (buffer-pool).
2585  *
2586  * @param ppio
2587  *   Pointer to the port structure.
2588  * @param hif
2589  *   Pointer to the MUSDK hardware interface.
2590  * @param sq
2591  *   Pointer to the shadow queue.
2592  * @param qid
2593  *   Queue id number.
2594  * @param force
2595  *   Force releasing packets.
2596  */
2597 static inline void
2598 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2599                        unsigned int core_id, struct mrvl_shadow_txq *sq,
2600                        int qid, int force)
2601 {
2602         struct buff_release_entry *entry;
2603         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2604         int i;
2605
2606         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2607
2608         sq->num_to_release += nb_done;
2609
2610         if (likely(!force &&
2611                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2612                 return;
2613
2614         nb_done = sq->num_to_release;
2615         sq->num_to_release = 0;
2616
2617         for (i = 0; i < nb_done; i++) {
2618                 entry = &sq->ent[sq->tail + num];
2619                 if (unlikely(!entry->buff.addr)) {
2620                         MRVL_LOG(ERR,
2621                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2622                                 sq->tail, (u64)entry->buff.cookie,
2623                                 (u64)entry->buff.addr);
2624                         skip_bufs = 1;
2625                         goto skip;
2626                 }
2627
2628                 if (unlikely(!entry->bpool)) {
2629                         struct rte_mbuf *mbuf;
2630
2631                         mbuf = (struct rte_mbuf *)entry->buff.cookie;
2632                         rte_pktmbuf_free(mbuf);
2633                         skip_bufs = 1;
2634                         goto skip;
2635                 }
2636
2637                 mrvl_port_bpool_size
2638                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2639                 num++;
2640                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2641                         goto skip;
2642                 continue;
2643 skip:
2644                 if (likely(num))
2645                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2646                 num += skip_bufs;
2647                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2648                 sq->size -= num;
2649                 num = 0;
2650                 skip_bufs = 0;
2651         }
2652
2653         if (likely(num)) {
2654                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2655                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2656                 sq->size -= num;
2657         }
2658 }
2659
2660 /**
2661  * DPDK callback for transmit.
2662  *
2663  * @param txq
2664  *   Generic pointer transmit queue.
2665  * @param tx_pkts
2666  *   Packets to transmit.
2667  * @param nb_pkts
2668  *   Number of packets in array.
2669  *
2670  * @return
2671  *   Number of packets successfully transmitted.
2672  */
2673 static uint16_t
2674 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2675 {
2676         struct mrvl_txq *q = txq;
2677         struct mrvl_shadow_txq *sq;
2678         struct pp2_hif *hif;
2679         struct pp2_ppio_desc descs[nb_pkts];
2680         unsigned int core_id = rte_lcore_id();
2681         int i, bytes_sent = 0;
2682         uint16_t num, sq_free_size;
2683         uint64_t addr;
2684
2685         hif = mrvl_get_hif(q->priv, core_id);
2686         sq = &q->shadow_txqs[core_id];
2687
2688         if (unlikely(!q->priv->ppio || !hif))
2689                 return 0;
2690
2691         if (sq->size)
2692                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2693                                        sq, q->queue_id, 0);
2694
2695         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2696         if (unlikely(nb_pkts > sq_free_size))
2697                 nb_pkts = sq_free_size;
2698
2699         for (i = 0; i < nb_pkts; i++) {
2700                 struct rte_mbuf *mbuf = tx_pkts[i];
2701                 int gen_l3_cksum, gen_l4_cksum;
2702                 enum pp2_outq_l3_type l3_type;
2703                 enum pp2_outq_l4_type l4_type;
2704
2705                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2706                         struct rte_mbuf *pref_pkt_hdr;
2707
2708                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2709                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
2710                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
2711                 }
2712
2713                 mrvl_fill_shadowq(sq, mbuf);
2714                 mrvl_fill_desc(&descs[i], mbuf);
2715
2716                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2717                 /*
2718                  * in case unsupported ol_flags were passed
2719                  * do not update descriptor offload information
2720                  */
2721                 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS))
2722                         continue;
2723                 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type,
2724                                         &gen_l3_cksum, &gen_l4_cksum);
2725
2726                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2727                                                   mbuf->l2_len,
2728                                                   mbuf->l2_len + mbuf->l3_len,
2729                                                   gen_l3_cksum, gen_l4_cksum);
2730         }
2731
2732         num = nb_pkts;
2733         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2734         /* number of packets that were not sent */
2735         if (unlikely(num > nb_pkts)) {
2736                 for (i = nb_pkts; i < num; i++) {
2737                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2738                                 MRVL_PP2_TX_SHADOWQ_MASK;
2739                         addr = sq->ent[sq->head].buff.cookie;
2740                         bytes_sent -=
2741                                 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2742                 }
2743                 sq->size -= num - nb_pkts;
2744         }
2745
2746         q->bytes_sent += bytes_sent;
2747
2748         return nb_pkts;
2749 }
2750
2751 /** DPDK callback for S/G transmit.
2752  *
2753  * @param txq
2754  *   Generic pointer transmit queue.
2755  * @param tx_pkts
2756  *   Packets to transmit.
2757  * @param nb_pkts
2758  *   Number of packets in array.
2759  *
2760  * @return
2761  *   Number of packets successfully transmitted.
2762  */
2763 static uint16_t
2764 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
2765                      uint16_t nb_pkts)
2766 {
2767         struct mrvl_txq *q = txq;
2768         struct mrvl_shadow_txq *sq;
2769         struct pp2_hif *hif;
2770         struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS];
2771         struct pp2_ppio_sg_pkts pkts;
2772         uint8_t frags[nb_pkts];
2773         unsigned int core_id = rte_lcore_id();
2774         int i, j, bytes_sent = 0;
2775         int tail, tail_first;
2776         uint16_t num, sq_free_size;
2777         uint16_t nb_segs, total_descs = 0;
2778         uint64_t addr;
2779
2780         hif = mrvl_get_hif(q->priv, core_id);
2781         sq = &q->shadow_txqs[core_id];
2782         pkts.frags = frags;
2783         pkts.num = 0;
2784
2785         if (unlikely(!q->priv->ppio || !hif))
2786                 return 0;
2787
2788         if (sq->size)
2789                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2790                                        sq, q->queue_id, 0);
2791
2792         /* Save shadow queue free size */
2793         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2794
2795         tail = 0;
2796         for (i = 0; i < nb_pkts; i++) {
2797                 struct rte_mbuf *mbuf = tx_pkts[i];
2798                 struct rte_mbuf *seg = NULL;
2799                 int gen_l3_cksum, gen_l4_cksum;
2800                 enum pp2_outq_l3_type l3_type;
2801                 enum pp2_outq_l4_type l4_type;
2802
2803                 nb_segs = mbuf->nb_segs;
2804                 tail_first = tail;
2805                 total_descs += nb_segs;
2806
2807                 /*
2808                  * Check if total_descs does not exceed
2809                  * shadow queue free size
2810                  */
2811                 if (unlikely(total_descs > sq_free_size)) {
2812                         total_descs -= nb_segs;
2813                         break;
2814                 }
2815
2816                 /* Check if nb_segs does not exceed the max nb of desc per
2817                  * fragmented packet
2818                  */
2819                 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) {
2820                         total_descs -= nb_segs;
2821                         RTE_LOG(ERR, PMD,
2822                                 "Too many segments. Packet won't be sent.\n");
2823                         break;
2824                 }
2825
2826                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2827                         struct rte_mbuf *pref_pkt_hdr;
2828
2829                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2830                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
2831                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
2832                 }
2833
2834                 pkts.frags[pkts.num] = nb_segs;
2835                 pkts.num++;
2836
2837                 seg = mbuf;
2838                 for (j = 0; j < nb_segs - 1; j++) {
2839                         /* For the subsequent segments, set shadow queue
2840                          * buffer to NULL
2841                          */
2842                         mrvl_fill_shadowq(sq, NULL);
2843                         mrvl_fill_desc(&descs[tail], seg);
2844
2845                         tail++;
2846                         seg = seg->next;
2847                 }
2848                 /* Put first mbuf info in last shadow queue entry */
2849                 mrvl_fill_shadowq(sq, mbuf);
2850                 /* Update descriptor with last segment */
2851                 mrvl_fill_desc(&descs[tail++], seg);
2852
2853                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2854                 /* In case unsupported ol_flags were passed
2855                  * do not update descriptor offload information
2856                  */
2857                 if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS))
2858                         continue;
2859                 mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type,
2860                                         &gen_l3_cksum, &gen_l4_cksum);
2861
2862                 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
2863                                                   l4_type, mbuf->l2_len,
2864                                                   mbuf->l2_len + mbuf->l3_len,
2865                                                   gen_l3_cksum, gen_l4_cksum);
2866         }
2867
2868         num = total_descs;
2869         pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs,
2870                          &total_descs, &pkts);
2871         /* number of packets that were not sent */
2872         if (unlikely(num > total_descs)) {
2873                 for (i = total_descs; i < num; i++) {
2874                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2875                                 MRVL_PP2_TX_SHADOWQ_MASK;
2876
2877                         addr = sq->ent[sq->head].buff.cookie;
2878                         if (addr)
2879                                 bytes_sent -=
2880                                         rte_pktmbuf_pkt_len((struct rte_mbuf *)
2881                                                 (cookie_addr_high | addr));
2882                 }
2883                 sq->size -= num - total_descs;
2884                 nb_pkts = pkts.num;
2885         }
2886
2887         q->bytes_sent += bytes_sent;
2888
2889         return nb_pkts;
2890 }
2891
2892 /**
2893  * Initialize packet processor.
2894  *
2895  * @return
2896  *   0 on success, negative error value otherwise.
2897  */
2898 static int
2899 mrvl_init_pp2(void)
2900 {
2901         struct pp2_init_params init_params;
2902
2903         memset(&init_params, 0, sizeof(init_params));
2904         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2905         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2906         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2907         if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs)
2908                 memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs,
2909                        sizeof(struct pp2_parse_udfs));
2910         return pp2_init(&init_params);
2911 }
2912
2913 /**
2914  * Deinitialize packet processor.
2915  *
2916  * @return
2917  *   0 on success, negative error value otherwise.
2918  */
2919 static void
2920 mrvl_deinit_pp2(void)
2921 {
2922         pp2_deinit();
2923 }
2924
2925 /**
2926  * Create private device structure.
2927  *
2928  * @param dev_name
2929  *   Pointer to the port name passed in the initialization parameters.
2930  *
2931  * @return
2932  *   Pointer to the newly allocated private device structure.
2933  */
2934 static struct mrvl_priv *
2935 mrvl_priv_create(const char *dev_name)
2936 {
2937         struct pp2_bpool_params bpool_params;
2938         char match[MRVL_MATCH_LEN];
2939         struct mrvl_priv *priv;
2940         int ret, bpool_bit;
2941
2942         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2943         if (!priv)
2944                 return NULL;
2945
2946         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2947                                        &priv->pp_id, &priv->ppio_id);
2948         if (ret)
2949                 goto out_free_priv;
2950
2951         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2952                                      PP2_BPOOL_NUM_POOLS);
2953         if (bpool_bit < 0)
2954                 goto out_free_priv;
2955         priv->bpool_bit = bpool_bit;
2956
2957         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2958                  priv->bpool_bit);
2959         memset(&bpool_params, 0, sizeof(bpool_params));
2960         bpool_params.match = match;
2961         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2962         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2963         if (ret)
2964                 goto out_clear_bpool_bit;
2965
2966         priv->ppio_params.type = PP2_PPIO_T_NIC;
2967         rte_spinlock_init(&priv->lock);
2968
2969         return priv;
2970 out_clear_bpool_bit:
2971         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2972 out_free_priv:
2973         rte_free(priv);
2974         return NULL;
2975 }
2976
2977 /**
2978  * Create device representing Ethernet port.
2979  *
2980  * @param name
2981  *   Pointer to the port's name.
2982  *
2983  * @return
2984  *   0 on success, negative error value otherwise.
2985  */
2986 static int
2987 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2988 {
2989         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2990         struct rte_eth_dev *eth_dev;
2991         struct mrvl_priv *priv;
2992         struct ifreq req;
2993
2994         eth_dev = rte_eth_dev_allocate(name);
2995         if (!eth_dev)
2996                 return -ENOMEM;
2997
2998         priv = mrvl_priv_create(name);
2999         if (!priv) {
3000                 ret = -ENOMEM;
3001                 goto out_free;
3002         }
3003         eth_dev->data->dev_private = priv;
3004
3005         eth_dev->data->mac_addrs =
3006                 rte_zmalloc("mac_addrs",
3007                             RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
3008         if (!eth_dev->data->mac_addrs) {
3009                 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
3010                 ret = -ENOMEM;
3011                 goto out_free;
3012         }
3013
3014         memset(&req, 0, sizeof(req));
3015         strcpy(req.ifr_name, name);
3016         ret = ioctl(fd, SIOCGIFHWADDR, &req);
3017         if (ret)
3018                 goto out_free;
3019
3020         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
3021                req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN);
3022
3023         eth_dev->device = &vdev->device;
3024         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
3025         mrvl_set_tx_function(eth_dev);
3026         eth_dev->dev_ops = &mrvl_ops;
3027         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
3028
3029         eth_dev->data->dev_link.link_status = ETH_LINK_UP;
3030
3031         rte_eth_dev_probing_finish(eth_dev);
3032         return 0;
3033 out_free:
3034         rte_eth_dev_release_port(eth_dev);
3035
3036         return ret;
3037 }
3038
3039 /**
3040  * Callback used by rte_kvargs_process() during argument parsing.
3041  *
3042  * @param key
3043  *   Pointer to the parsed key (unused).
3044  * @param value
3045  *   Pointer to the parsed value.
3046  * @param extra_args
3047  *   Pointer to the extra arguments which contains address of the
3048  *   table of pointers to parsed interface names.
3049  *
3050  * @return
3051  *   Always 0.
3052  */
3053 static int
3054 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
3055                  void *extra_args)
3056 {
3057         struct mrvl_ifnames *ifnames = extra_args;
3058
3059         ifnames->names[ifnames->idx++] = value;
3060
3061         return 0;
3062 }
3063
3064 /**
3065  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
3066  */
3067 static void
3068 mrvl_deinit_hifs(void)
3069 {
3070         int i;
3071
3072         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
3073                 if (hifs[i])
3074                         pp2_hif_deinit(hifs[i]);
3075         }
3076         used_hifs = MRVL_MUSDK_HIFS_RESERVED;
3077         memset(hifs, 0, sizeof(hifs));
3078 }
3079
3080 /**
3081  * DPDK callback to register the virtual device.
3082  *
3083  * @param vdev
3084  *   Pointer to the virtual device.
3085  *
3086  * @return
3087  *   0 on success, negative error value otherwise.
3088  */
3089 static int
3090 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
3091 {
3092         struct rte_kvargs *kvlist;
3093         struct mrvl_ifnames ifnames;
3094         int ret = -EINVAL;
3095         uint32_t i, ifnum, cfgnum;
3096         const char *params;
3097
3098         params = rte_vdev_device_args(vdev);
3099         if (!params)
3100                 return -EINVAL;
3101
3102         kvlist = rte_kvargs_parse(params, valid_args);
3103         if (!kvlist)
3104                 return -EINVAL;
3105
3106         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
3107         if (ifnum > RTE_DIM(ifnames.names))
3108                 goto out_free_kvlist;
3109
3110         ifnames.idx = 0;
3111         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
3112                            mrvl_get_ifnames, &ifnames);
3113
3114
3115         /*
3116          * The below system initialization should be done only once,
3117          * on the first provided configuration file
3118          */
3119         if (!mrvl_cfg) {
3120                 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
3121                 MRVL_LOG(INFO, "Parsing config file!");
3122                 if (cfgnum > 1) {
3123                         MRVL_LOG(ERR, "Cannot handle more than one config file!");
3124                         goto out_free_kvlist;
3125                 } else if (cfgnum == 1) {
3126                         rte_kvargs_process(kvlist, MRVL_CFG_ARG,
3127                                            mrvl_get_cfg, &mrvl_cfg);
3128                 }
3129         }
3130
3131         if (mrvl_dev_num)
3132                 goto init_devices;
3133
3134         MRVL_LOG(INFO, "Perform MUSDK initializations");
3135
3136         ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
3137         if (ret)
3138                 goto out_free_kvlist;
3139
3140         ret = mrvl_init_pp2();
3141         if (ret) {
3142                 MRVL_LOG(ERR, "Failed to init PP!");
3143                 rte_mvep_deinit(MVEP_MOD_T_PP2);
3144                 goto out_free_kvlist;
3145         }
3146
3147         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
3148         memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
3149
3150         mrvl_lcore_first = RTE_MAX_LCORE;
3151         mrvl_lcore_last = 0;
3152
3153 init_devices:
3154         for (i = 0; i < ifnum; i++) {
3155                 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
3156                 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
3157                 if (ret)
3158                         goto out_cleanup;
3159                 mrvl_dev_num++;
3160         }
3161
3162         rte_kvargs_free(kvlist);
3163
3164         return 0;
3165 out_cleanup:
3166         rte_pmd_mrvl_remove(vdev);
3167
3168 out_free_kvlist:
3169         rte_kvargs_free(kvlist);
3170
3171         return ret;
3172 }
3173
3174 /**
3175  * DPDK callback to remove virtual device.
3176  *
3177  * @param vdev
3178  *   Pointer to the removed virtual device.
3179  *
3180  * @return
3181  *   0 on success, negative error value otherwise.
3182  */
3183 static int
3184 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
3185 {
3186         uint16_t port_id;
3187         int ret = 0;
3188
3189         RTE_ETH_FOREACH_DEV(port_id) {
3190                 if (rte_eth_devices[port_id].device != &vdev->device)
3191                         continue;
3192                 ret |= rte_eth_dev_close(port_id);
3193         }
3194
3195         return ret == 0 ? 0 : -EIO;
3196 }
3197
3198 static struct rte_vdev_driver pmd_mrvl_drv = {
3199         .probe = rte_pmd_mrvl_probe,
3200         .remove = rte_pmd_mrvl_remove,
3201 };
3202
3203 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
3204 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
3205 RTE_LOG_REGISTER(mrvl_logtype, pmd.net.mvpp2, NOTICE);