1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_ethdev_driver.h>
8 #include <rte_kvargs.h>
10 #include <rte_malloc.h>
11 #include <rte_bus_vdev.h>
13 /* Unluckily, container_of is defined by both DPDK and MUSDK,
14 * we'll declare only one version.
16 * Note that it is not used in this PMD anyway.
23 #include <linux/ethtool.h>
24 #include <linux/sockios.h>
26 #include <net/if_arp.h>
27 #include <sys/ioctl.h>
28 #include <sys/socket.h>
30 #include <sys/types.h>
32 #include "mrvl_ethdev.h"
35 /* bitmask with reserved hifs */
36 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
37 /* bitmask with reserved bpools */
38 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
39 /* bitmask with reserved kernel RSS tables */
40 #define MRVL_MUSDK_RSS_RESERVED 0x01
41 /* maximum number of available hifs */
42 #define MRVL_MUSDK_HIFS_MAX 9
45 #define MRVL_MUSDK_PREFETCH_SHIFT 2
47 /* TCAM has 25 entries reserved for uc/mc filter entries */
48 #define MRVL_MAC_ADDRS_MAX 25
49 #define MRVL_MATCH_LEN 16
50 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
51 /* Maximum allowable packet size */
52 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
54 #define MRVL_IFACE_NAME_ARG "iface"
55 #define MRVL_CFG_ARG "cfg"
57 #define MRVL_BURST_SIZE 64
59 #define MRVL_ARP_LENGTH 28
61 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
63 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
64 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
66 /* Memory size (in bytes) for MUSDK dma buffers */
67 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
69 /** Port Rx offload capabilities */
70 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
71 DEV_RX_OFFLOAD_JUMBO_FRAME | \
72 DEV_RX_OFFLOAD_CRC_STRIP | \
73 DEV_RX_OFFLOAD_CHECKSUM)
75 /** Port Tx offloads capabilities */
76 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
77 DEV_TX_OFFLOAD_UDP_CKSUM | \
78 DEV_TX_OFFLOAD_TCP_CKSUM)
80 static const char * const valid_args[] = {
86 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
87 static struct pp2_hif *hifs[RTE_MAX_LCORE];
88 static int used_bpools[PP2_NUM_PKT_PROC] = {
89 MRVL_MUSDK_BPOOLS_RESERVED,
90 MRVL_MUSDK_BPOOLS_RESERVED
93 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
94 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
95 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
100 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
105 * To use buffer harvesting based on loopback port shadow queue structure
106 * was introduced for buffers information bookkeeping.
108 * Before sending the packet, related buffer information (pp2_buff_inf) is
109 * stored in shadow queue. After packet is transmitted no longer used
110 * packet buffer is released back to it's original hardware pool,
111 * on condition it originated from interface.
112 * In case it was generated by application itself i.e: mbuf->port field is
113 * 0xff then its released to software mempool.
115 struct mrvl_shadow_txq {
116 int head; /* write index - used when sending buffers */
117 int tail; /* read index - used when releasing buffers */
118 u16 size; /* queue occupied size */
119 u16 num_to_release; /* number of buffers sent, that can be released */
120 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
124 struct mrvl_priv *priv;
125 struct rte_mempool *mp;
134 struct mrvl_priv *priv;
138 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
139 int tx_deferred_start;
142 static int mrvl_lcore_first;
143 static int mrvl_lcore_last;
144 static int mrvl_dev_num;
146 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
147 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
148 struct pp2_hif *hif, unsigned int core_id,
149 struct mrvl_shadow_txq *sq, int qid, int force);
151 #define MRVL_XSTATS_TBL_ENTRY(name) { \
152 #name, offsetof(struct pp2_ppio_statistics, name), \
153 sizeof(((struct pp2_ppio_statistics *)0)->name) \
156 /* Table with xstats data */
161 } mrvl_xstats_tbl[] = {
162 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
163 MRVL_XSTATS_TBL_ENTRY(rx_packets),
164 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
165 MRVL_XSTATS_TBL_ENTRY(rx_errors),
166 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
168 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
169 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
170 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
171 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
172 MRVL_XSTATS_TBL_ENTRY(tx_packets),
173 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
174 MRVL_XSTATS_TBL_ENTRY(tx_errors)
178 mrvl_get_bpool_size(int pp2_id, int pool_id)
183 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
184 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
190 mrvl_reserve_bit(int *bitmap, int max)
192 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
203 mrvl_init_hif(int core_id)
205 struct pp2_hif_params params;
206 char match[MRVL_MATCH_LEN];
209 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
211 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
215 snprintf(match, sizeof(match), "hif-%d", ret);
216 memset(¶ms, 0, sizeof(params));
217 params.match = match;
218 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
219 ret = pp2_hif_init(¶ms, &hifs[core_id]);
221 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
228 static inline struct pp2_hif*
229 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
233 if (likely(hifs[core_id] != NULL))
234 return hifs[core_id];
236 rte_spinlock_lock(&priv->lock);
238 ret = mrvl_init_hif(core_id);
240 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
244 if (core_id < mrvl_lcore_first)
245 mrvl_lcore_first = core_id;
247 if (core_id > mrvl_lcore_last)
248 mrvl_lcore_last = core_id;
250 rte_spinlock_unlock(&priv->lock);
252 return hifs[core_id];
256 * Configure rss based on dpdk rss configuration.
259 * Pointer to private structure.
261 * Pointer to RSS configuration.
264 * 0 on success, negative error value otherwise.
267 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
269 if (rss_conf->rss_key)
270 MRVL_LOG(WARNING, "Changing hash key is not supported");
272 if (rss_conf->rss_hf == 0) {
273 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
274 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
275 priv->ppio_params.inqs_params.hash_type =
276 PP2_PPIO_HASH_T_2_TUPLE;
277 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
278 priv->ppio_params.inqs_params.hash_type =
279 PP2_PPIO_HASH_T_5_TUPLE;
280 priv->rss_hf_tcp = 1;
281 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
282 priv->ppio_params.inqs_params.hash_type =
283 PP2_PPIO_HASH_T_5_TUPLE;
284 priv->rss_hf_tcp = 0;
293 * Ethernet device configuration.
295 * Prepare the driver for a given number of TX and RX queues and
299 * Pointer to Ethernet device structure.
302 * 0 on success, negative error value otherwise.
305 mrvl_dev_configure(struct rte_eth_dev *dev)
307 struct mrvl_priv *priv = dev->data->dev_private;
310 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
311 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
312 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
313 dev->data->dev_conf.rxmode.mq_mode);
317 /* KEEP_CRC offload flag is not supported by PMD
318 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
320 if (rte_eth_dev_must_keep_crc(dev->data->dev_conf.rxmode.offloads)) {
321 MRVL_LOG(INFO, "L2 CRC stripping is always enabled in hw");
322 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
325 if (dev->data->dev_conf.rxmode.split_hdr_size) {
326 MRVL_LOG(INFO, "Split headers not supported");
330 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
331 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
332 ETHER_HDR_LEN - ETHER_CRC_LEN;
334 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
335 dev->data->nb_rx_queues);
339 ret = mrvl_configure_txqs(priv, dev->data->port_id,
340 dev->data->nb_tx_queues);
344 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
345 priv->ppio_params.maintain_stats = 1;
346 priv->nb_rx_queues = dev->data->nb_rx_queues;
348 if (dev->data->nb_rx_queues == 1 &&
349 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
350 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
351 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
356 return mrvl_configure_rss(priv,
357 &dev->data->dev_conf.rx_adv_conf.rss_conf);
361 * DPDK callback to change the MTU.
363 * Setting the MTU affects hardware MRU (packets larger than the MRU
367 * Pointer to Ethernet device structure.
372 * 0 on success, negative error value otherwise.
375 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
377 struct mrvl_priv *priv = dev->data->dev_private;
378 /* extra MV_MH_SIZE bytes are required for Marvell tag */
379 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
382 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
388 ret = pp2_ppio_set_mru(priv->ppio, mru);
392 return pp2_ppio_set_mtu(priv->ppio, mtu);
396 * DPDK callback to bring the link up.
399 * Pointer to Ethernet device structure.
402 * 0 on success, negative error value otherwise.
405 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
407 struct mrvl_priv *priv = dev->data->dev_private;
413 ret = pp2_ppio_enable(priv->ppio);
418 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
419 * as pp2_ppio_enable() changes port->t_mode from default 0 to
420 * PP2_TRAFFIC_INGRESS_EGRESS.
422 * Set mtu to default DPDK value here.
424 ret = mrvl_mtu_set(dev, dev->data->mtu);
426 pp2_ppio_disable(priv->ppio);
432 * DPDK callback to bring the link down.
435 * Pointer to Ethernet device structure.
438 * 0 on success, negative error value otherwise.
441 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
443 struct mrvl_priv *priv = dev->data->dev_private;
448 return pp2_ppio_disable(priv->ppio);
452 * DPDK callback to start tx queue.
455 * Pointer to Ethernet device structure.
457 * Transmit queue index.
460 * 0 on success, negative error value otherwise.
463 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
465 struct mrvl_priv *priv = dev->data->dev_private;
471 /* passing 1 enables given tx queue */
472 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
474 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
478 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
484 * DPDK callback to stop tx queue.
487 * Pointer to Ethernet device structure.
489 * Transmit queue index.
492 * 0 on success, negative error value otherwise.
495 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
497 struct mrvl_priv *priv = dev->data->dev_private;
503 /* passing 0 disables given tx queue */
504 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
506 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
510 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
516 * DPDK callback to start the device.
519 * Pointer to Ethernet device structure.
522 * 0 on success, negative errno value on failure.
525 mrvl_dev_start(struct rte_eth_dev *dev)
527 struct mrvl_priv *priv = dev->data->dev_private;
528 char match[MRVL_MATCH_LEN];
529 int ret = 0, i, def_init_size;
531 snprintf(match, sizeof(match), "ppio-%d:%d",
532 priv->pp_id, priv->ppio_id);
533 priv->ppio_params.match = match;
536 * Calculate the minimum bpool size for refill feature as follows:
537 * 2 default burst sizes multiply by number of rx queues.
538 * If the bpool size will be below this value, new buffers will
539 * be added to the pool.
541 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
543 /* In case initial bpool size configured in queues setup is
544 * smaller than minimum size add more buffers
546 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
547 if (priv->bpool_init_size < def_init_size) {
548 int buffs_to_add = def_init_size - priv->bpool_init_size;
550 priv->bpool_init_size += buffs_to_add;
551 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
553 MRVL_LOG(ERR, "Failed to add buffers to bpool");
557 * Calculate the maximum bpool size for refill feature as follows:
558 * maximum number of descriptors in rx queue multiply by number
559 * of rx queues plus minimum bpool size.
560 * In case the bpool size will exceed this value, superfluous buffers
563 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
564 priv->bpool_min_size;
566 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
568 MRVL_LOG(ERR, "Failed to init ppio");
573 * In case there are some some stale uc/mc mac addresses flush them
574 * here. It cannot be done during mrvl_dev_close() as port information
575 * is already gone at that point (due to pp2_ppio_deinit() in
578 if (!priv->uc_mc_flushed) {
579 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
582 "Failed to flush uc/mc filter list");
585 priv->uc_mc_flushed = 1;
588 if (!priv->vlan_flushed) {
589 ret = pp2_ppio_flush_vlan(priv->ppio);
591 MRVL_LOG(ERR, "Failed to flush vlan list");
594 * once pp2_ppio_flush_vlan() is supported jump to out
598 priv->vlan_flushed = 1;
601 /* For default QoS config, don't start classifier. */
603 ret = mrvl_start_qos_mapping(priv);
605 MRVL_LOG(ERR, "Failed to setup QoS mapping");
610 ret = mrvl_dev_set_link_up(dev);
612 MRVL_LOG(ERR, "Failed to set link up");
616 /* start tx queues */
617 for (i = 0; i < dev->data->nb_tx_queues; i++) {
618 struct mrvl_txq *txq = dev->data->tx_queues[i];
620 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
622 if (!txq->tx_deferred_start)
626 * All txqs are started by default. Stop them
627 * so that tx_deferred_start works as expected.
629 ret = mrvl_tx_queue_stop(dev, i);
636 MRVL_LOG(ERR, "Failed to start device");
637 pp2_ppio_deinit(priv->ppio);
642 * Flush receive queues.
645 * Pointer to Ethernet device structure.
648 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
652 MRVL_LOG(INFO, "Flushing rx queues");
653 for (i = 0; i < dev->data->nb_rx_queues; i++) {
657 struct mrvl_rxq *q = dev->data->rx_queues[i];
658 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
660 num = MRVL_PP2_RXD_MAX;
661 ret = pp2_ppio_recv(q->priv->ppio,
662 q->priv->rxq_map[q->queue_id].tc,
663 q->priv->rxq_map[q->queue_id].inq,
664 descs, (uint16_t *)&num);
665 } while (ret == 0 && num);
670 * Flush transmit shadow queues.
673 * Pointer to Ethernet device structure.
676 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
679 struct mrvl_txq *txq;
681 MRVL_LOG(INFO, "Flushing tx shadow queues");
682 for (i = 0; i < dev->data->nb_tx_queues; i++) {
683 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
685 for (j = 0; j < RTE_MAX_LCORE; j++) {
686 struct mrvl_shadow_txq *sq;
691 sq = &txq->shadow_txqs[j];
692 mrvl_free_sent_buffers(txq->priv->ppio,
693 hifs[j], j, sq, txq->queue_id, 1);
694 while (sq->tail != sq->head) {
695 uint64_t addr = cookie_addr_high |
696 sq->ent[sq->tail].buff.cookie;
698 (struct rte_mbuf *)addr);
699 sq->tail = (sq->tail + 1) &
700 MRVL_PP2_TX_SHADOWQ_MASK;
702 memset(sq, 0, sizeof(*sq));
708 * Flush hardware bpool (buffer-pool).
711 * Pointer to Ethernet device structure.
714 mrvl_flush_bpool(struct rte_eth_dev *dev)
716 struct mrvl_priv *priv = dev->data->dev_private;
720 unsigned int core_id = rte_lcore_id();
722 if (core_id == LCORE_ID_ANY)
725 hif = mrvl_get_hif(priv, core_id);
727 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
729 MRVL_LOG(ERR, "Failed to get bpool buffers number");
734 struct pp2_buff_inf inf;
737 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
741 addr = cookie_addr_high | inf.cookie;
742 rte_pktmbuf_free((struct rte_mbuf *)addr);
747 * DPDK callback to stop the device.
750 * Pointer to Ethernet device structure.
753 mrvl_dev_stop(struct rte_eth_dev *dev)
755 struct mrvl_priv *priv = dev->data->dev_private;
757 mrvl_dev_set_link_down(dev);
758 mrvl_flush_rx_queues(dev);
759 mrvl_flush_tx_shadow_queues(dev);
761 pp2_cls_tbl_deinit(priv->cls_tbl);
762 priv->cls_tbl = NULL;
765 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
766 priv->qos_tbl = NULL;
769 pp2_ppio_deinit(priv->ppio);
772 /* policer must be released after ppio deinitialization */
774 pp2_cls_plcr_deinit(priv->policer);
775 priv->policer = NULL;
780 * DPDK callback to close the device.
783 * Pointer to Ethernet device structure.
786 mrvl_dev_close(struct rte_eth_dev *dev)
788 struct mrvl_priv *priv = dev->data->dev_private;
791 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
792 struct pp2_ppio_tc_params *tc_params =
793 &priv->ppio_params.inqs_params.tcs_params[i];
795 if (tc_params->inqs_params) {
796 rte_free(tc_params->inqs_params);
797 tc_params->inqs_params = NULL;
801 mrvl_flush_bpool(dev);
805 * DPDK callback to retrieve physical link information.
808 * Pointer to Ethernet device structure.
809 * @param wait_to_complete
810 * Wait for request completion (ignored).
813 * 0 on success, negative error value otherwise.
816 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
820 * once MUSDK provides necessary API use it here
822 struct mrvl_priv *priv = dev->data->dev_private;
823 struct ethtool_cmd edata;
825 int ret, fd, link_up;
830 edata.cmd = ETHTOOL_GSET;
832 strcpy(req.ifr_name, dev->data->name);
833 req.ifr_data = (void *)&edata;
835 fd = socket(AF_INET, SOCK_DGRAM, 0);
839 ret = ioctl(fd, SIOCETHTOOL, &req);
847 switch (ethtool_cmd_speed(&edata)) {
849 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
852 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
855 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
858 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
861 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
864 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
865 ETH_LINK_HALF_DUPLEX;
866 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
868 pp2_ppio_get_link_state(priv->ppio, &link_up);
869 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
875 * DPDK callback to enable promiscuous mode.
878 * Pointer to Ethernet device structure.
881 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
883 struct mrvl_priv *priv = dev->data->dev_private;
892 ret = pp2_ppio_set_promisc(priv->ppio, 1);
894 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
898 * DPDK callback to enable allmulti mode.
901 * Pointer to Ethernet device structure.
904 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
906 struct mrvl_priv *priv = dev->data->dev_private;
915 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
917 MRVL_LOG(ERR, "Failed enable all-multicast mode");
921 * DPDK callback to disable promiscuous mode.
924 * Pointer to Ethernet device structure.
927 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
929 struct mrvl_priv *priv = dev->data->dev_private;
935 ret = pp2_ppio_set_promisc(priv->ppio, 0);
937 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
941 * DPDK callback to disable allmulticast mode.
944 * Pointer to Ethernet device structure.
947 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
949 struct mrvl_priv *priv = dev->data->dev_private;
955 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
957 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
961 * DPDK callback to remove a MAC address.
964 * Pointer to Ethernet device structure.
969 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
971 struct mrvl_priv *priv = dev->data->dev_private;
972 char buf[ETHER_ADDR_FMT_SIZE];
981 ret = pp2_ppio_remove_mac_addr(priv->ppio,
982 dev->data->mac_addrs[index].addr_bytes);
984 ether_format_addr(buf, sizeof(buf),
985 &dev->data->mac_addrs[index]);
986 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
991 * DPDK callback to add a MAC address.
994 * Pointer to Ethernet device structure.
996 * MAC address to register.
1000 * VMDq pool index to associate address with (unused).
1003 * 0 on success, negative error value otherwise.
1006 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1007 uint32_t index, uint32_t vmdq __rte_unused)
1009 struct mrvl_priv *priv = dev->data->dev_private;
1010 char buf[ETHER_ADDR_FMT_SIZE];
1017 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1024 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1025 * parameter uc_filter_max. Maximum number of mc addresses is then
1026 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1029 * If more than uc_filter_max uc addresses were added to filter list
1030 * then NIC will switch to promiscuous mode automatically.
1032 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1033 * were added to filter list then NIC will switch to all-multicast mode
1036 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1038 ether_format_addr(buf, sizeof(buf), mac_addr);
1039 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1047 * DPDK callback to set the primary MAC address.
1050 * Pointer to Ethernet device structure.
1052 * MAC address to register.
1055 * 0 on success, negative error value otherwise.
1058 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1060 struct mrvl_priv *priv = dev->data->dev_private;
1069 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1071 char buf[ETHER_ADDR_FMT_SIZE];
1072 ether_format_addr(buf, sizeof(buf), mac_addr);
1073 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1080 * DPDK callback to get device statistics.
1083 * Pointer to Ethernet device structure.
1085 * Stats structure output buffer.
1088 * 0 on success, negative error value otherwise.
1091 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1093 struct mrvl_priv *priv = dev->data->dev_private;
1094 struct pp2_ppio_statistics ppio_stats;
1095 uint64_t drop_mac = 0;
1096 unsigned int i, idx, ret;
1101 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1102 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1103 struct pp2_ppio_inq_statistics rx_stats;
1108 idx = rxq->queue_id;
1109 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1111 "rx queue %d stats out of range (0 - %d)",
1112 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1116 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1117 priv->rxq_map[idx].tc,
1118 priv->rxq_map[idx].inq,
1120 if (unlikely(ret)) {
1122 "Failed to update rx queue %d stats", idx);
1126 stats->q_ibytes[idx] = rxq->bytes_recv;
1127 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1128 stats->q_errors[idx] = rx_stats.drop_early +
1129 rx_stats.drop_fullq +
1132 stats->ibytes += rxq->bytes_recv;
1133 drop_mac += rxq->drop_mac;
1136 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1137 struct mrvl_txq *txq = dev->data->tx_queues[i];
1138 struct pp2_ppio_outq_statistics tx_stats;
1143 idx = txq->queue_id;
1144 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1146 "tx queue %d stats out of range (0 - %d)",
1147 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1150 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1152 if (unlikely(ret)) {
1154 "Failed to update tx queue %d stats", idx);
1158 stats->q_opackets[idx] = tx_stats.deq_desc;
1159 stats->q_obytes[idx] = txq->bytes_sent;
1160 stats->obytes += txq->bytes_sent;
1163 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1164 if (unlikely(ret)) {
1165 MRVL_LOG(ERR, "Failed to update port statistics");
1169 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1170 stats->opackets += ppio_stats.tx_packets;
1171 stats->imissed += ppio_stats.rx_fullq_dropped +
1172 ppio_stats.rx_bm_dropped +
1173 ppio_stats.rx_early_dropped +
1174 ppio_stats.rx_fifo_dropped +
1175 ppio_stats.rx_cls_dropped;
1176 stats->ierrors = drop_mac;
1182 * DPDK callback to clear device statistics.
1185 * Pointer to Ethernet device structure.
1188 mrvl_stats_reset(struct rte_eth_dev *dev)
1190 struct mrvl_priv *priv = dev->data->dev_private;
1196 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1197 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1199 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1200 priv->rxq_map[i].inq, NULL, 1);
1201 rxq->bytes_recv = 0;
1205 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1206 struct mrvl_txq *txq = dev->data->tx_queues[i];
1208 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1209 txq->bytes_sent = 0;
1212 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1216 * DPDK callback to get extended statistics.
1219 * Pointer to Ethernet device structure.
1221 * Pointer to xstats table.
1223 * Number of entries in xstats table.
1225 * Negative value on error, number of read xstats otherwise.
1228 mrvl_xstats_get(struct rte_eth_dev *dev,
1229 struct rte_eth_xstat *stats, unsigned int n)
1231 struct mrvl_priv *priv = dev->data->dev_private;
1232 struct pp2_ppio_statistics ppio_stats;
1238 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1239 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1242 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1243 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1244 mrvl_xstats_tbl[i].offset);
1245 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1246 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1247 mrvl_xstats_tbl[i].offset);
1252 stats[i].value = val;
1259 * DPDK callback to reset extended statistics.
1262 * Pointer to Ethernet device structure.
1265 mrvl_xstats_reset(struct rte_eth_dev *dev)
1267 mrvl_stats_reset(dev);
1271 * DPDK callback to get extended statistics names.
1273 * @param dev (unused)
1274 * Pointer to Ethernet device structure.
1275 * @param xstats_names
1276 * Pointer to xstats names table.
1278 * Size of the xstats names table.
1280 * Number of read names.
1283 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1284 struct rte_eth_xstat_name *xstats_names,
1290 return RTE_DIM(mrvl_xstats_tbl);
1292 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1293 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1294 mrvl_xstats_tbl[i].name);
1300 * DPDK callback to get information about the device.
1303 * Pointer to Ethernet device structure (unused).
1305 * Info structure output buffer.
1308 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1309 struct rte_eth_dev_info *info)
1311 info->speed_capa = ETH_LINK_SPEED_10M |
1312 ETH_LINK_SPEED_100M |
1316 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1317 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1318 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1320 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1321 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1322 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1324 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1325 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1326 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1328 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1329 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1331 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1332 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1334 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1335 ETH_RSS_NONFRAG_IPV4_TCP |
1336 ETH_RSS_NONFRAG_IPV4_UDP;
1338 /* By default packets are dropped if no descriptors are available */
1339 info->default_rxconf.rx_drop_en = 1;
1340 info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1342 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1346 * Return supported packet types.
1349 * Pointer to Ethernet device structure (unused).
1352 * Const pointer to the table with supported packet types.
1354 static const uint32_t *
1355 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1357 static const uint32_t ptypes[] = {
1360 RTE_PTYPE_L3_IPV4_EXT,
1361 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1363 RTE_PTYPE_L3_IPV6_EXT,
1364 RTE_PTYPE_L2_ETHER_ARP,
1373 * DPDK callback to get information about specific receive queue.
1376 * Pointer to Ethernet device structure.
1377 * @param rx_queue_id
1378 * Receive queue index.
1380 * Receive queue information structure.
1382 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1383 struct rte_eth_rxq_info *qinfo)
1385 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1386 struct mrvl_priv *priv = dev->data->dev_private;
1387 int inq = priv->rxq_map[rx_queue_id].inq;
1388 int tc = priv->rxq_map[rx_queue_id].tc;
1389 struct pp2_ppio_tc_params *tc_params =
1390 &priv->ppio_params.inqs_params.tcs_params[tc];
1393 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1397 * DPDK callback to get information about specific transmit queue.
1400 * Pointer to Ethernet device structure.
1401 * @param tx_queue_id
1402 * Transmit queue index.
1404 * Transmit queue information structure.
1406 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1407 struct rte_eth_txq_info *qinfo)
1409 struct mrvl_priv *priv = dev->data->dev_private;
1410 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1413 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1414 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1418 * DPDK callback to Configure a VLAN filter.
1421 * Pointer to Ethernet device structure.
1423 * VLAN ID to filter.
1428 * 0 on success, negative error value otherwise.
1431 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1433 struct mrvl_priv *priv = dev->data->dev_private;
1441 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1442 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1446 * Release buffers to hardware bpool (buffer-pool)
1449 * Receive queue pointer.
1451 * Number of buffers to release to bpool.
1454 * 0 on success, negative error value otherwise.
1457 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1459 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1460 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1462 unsigned int core_id;
1463 struct pp2_hif *hif;
1464 struct pp2_bpool *bpool;
1466 core_id = rte_lcore_id();
1467 if (core_id == LCORE_ID_ANY)
1470 hif = mrvl_get_hif(rxq->priv, core_id);
1474 bpool = rxq->priv->bpool;
1476 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1480 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1482 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1484 for (i = 0; i < num; i++) {
1485 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1486 != cookie_addr_high) {
1488 "mbuf virtual addr high 0x%lx out of range",
1489 (uint64_t)mbufs[i] >> 32);
1493 entries[i].buff.addr =
1494 rte_mbuf_data_iova_default(mbufs[i]);
1495 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1496 entries[i].bpool = bpool;
1499 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1500 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1507 for (; i < num; i++)
1508 rte_pktmbuf_free(mbufs[i]);
1514 * DPDK callback to configure the receive queue.
1517 * Pointer to Ethernet device structure.
1521 * Number of descriptors to configure in queue.
1523 * NUMA socket on which memory must be allocated.
1525 * Thresholds parameters.
1527 * Memory pool for buffer allocations.
1530 * 0 on success, negative error value otherwise.
1533 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1534 unsigned int socket,
1535 const struct rte_eth_rxconf *conf,
1536 struct rte_mempool *mp)
1538 struct mrvl_priv *priv = dev->data->dev_private;
1539 struct mrvl_rxq *rxq;
1541 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1545 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1547 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1549 * Unknown TC mapping, mapping will not have a correct queue.
1551 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1552 idx, priv->ppio_id);
1556 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1557 MRVL_PKT_EFFEC_OFFS;
1558 if (min_size < max_rx_pkt_len) {
1560 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.",
1561 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1562 MRVL_PKT_EFFEC_OFFS,
1567 if (dev->data->rx_queues[idx]) {
1568 rte_free(dev->data->rx_queues[idx]);
1569 dev->data->rx_queues[idx] = NULL;
1572 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1578 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1579 rxq->queue_id = idx;
1580 rxq->port_id = dev->data->port_id;
1581 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1583 tc = priv->rxq_map[rxq->queue_id].tc,
1584 inq = priv->rxq_map[rxq->queue_id].inq;
1585 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1588 ret = mrvl_fill_bpool(rxq, desc);
1594 priv->bpool_init_size += desc;
1596 dev->data->rx_queues[idx] = rxq;
1602 * DPDK callback to release the receive queue.
1605 * Generic receive queue pointer.
1608 mrvl_rx_queue_release(void *rxq)
1610 struct mrvl_rxq *q = rxq;
1611 struct pp2_ppio_tc_params *tc_params;
1612 int i, num, tc, inq;
1613 struct pp2_hif *hif;
1614 unsigned int core_id = rte_lcore_id();
1616 if (core_id == LCORE_ID_ANY)
1622 hif = mrvl_get_hif(q->priv, core_id);
1627 tc = q->priv->rxq_map[q->queue_id].tc;
1628 inq = q->priv->rxq_map[q->queue_id].inq;
1629 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1630 num = tc_params->inqs_params[inq].size;
1631 for (i = 0; i < num; i++) {
1632 struct pp2_buff_inf inf;
1635 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1636 addr = cookie_addr_high | inf.cookie;
1637 rte_pktmbuf_free((struct rte_mbuf *)addr);
1644 * DPDK callback to configure the transmit queue.
1647 * Pointer to Ethernet device structure.
1649 * Transmit queue index.
1651 * Number of descriptors to configure in the queue.
1653 * NUMA socket on which memory must be allocated.
1655 * Tx queue configuration parameters.
1658 * 0 on success, negative error value otherwise.
1661 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1662 unsigned int socket,
1663 const struct rte_eth_txconf *conf)
1665 struct mrvl_priv *priv = dev->data->dev_private;
1666 struct mrvl_txq *txq;
1668 if (dev->data->tx_queues[idx]) {
1669 rte_free(dev->data->tx_queues[idx]);
1670 dev->data->tx_queues[idx] = NULL;
1673 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1678 txq->queue_id = idx;
1679 txq->port_id = dev->data->port_id;
1680 txq->tx_deferred_start = conf->tx_deferred_start;
1681 dev->data->tx_queues[idx] = txq;
1683 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1689 * DPDK callback to release the transmit queue.
1692 * Generic transmit queue pointer.
1695 mrvl_tx_queue_release(void *txq)
1697 struct mrvl_txq *q = txq;
1706 * DPDK callback to get flow control configuration.
1709 * Pointer to Ethernet device structure.
1711 * Pointer to the flow control configuration.
1714 * 0 on success, negative error value otherwise.
1717 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1719 struct mrvl_priv *priv = dev->data->dev_private;
1725 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1727 MRVL_LOG(ERR, "Failed to read rx pause state");
1731 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1737 * DPDK callback to set flow control configuration.
1740 * Pointer to Ethernet device structure.
1742 * Pointer to the flow control configuration.
1745 * 0 on success, negative error value otherwise.
1748 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1750 struct mrvl_priv *priv = dev->data->dev_private;
1755 if (fc_conf->high_water ||
1756 fc_conf->low_water ||
1757 fc_conf->pause_time ||
1758 fc_conf->mac_ctrl_frame_fwd ||
1760 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1765 if (fc_conf->mode == RTE_FC_NONE ||
1766 fc_conf->mode == RTE_FC_RX_PAUSE) {
1769 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1770 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1773 "Failed to change flowctrl on RX side");
1782 * Update RSS hash configuration
1785 * Pointer to Ethernet device structure.
1787 * Pointer to RSS configuration.
1790 * 0 on success, negative error value otherwise.
1793 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1794 struct rte_eth_rss_conf *rss_conf)
1796 struct mrvl_priv *priv = dev->data->dev_private;
1801 return mrvl_configure_rss(priv, rss_conf);
1805 * DPDK callback to get RSS hash configuration.
1808 * Pointer to Ethernet device structure.
1810 * Pointer to RSS configuration.
1816 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1817 struct rte_eth_rss_conf *rss_conf)
1819 struct mrvl_priv *priv = dev->data->dev_private;
1820 enum pp2_ppio_hash_type hash_type =
1821 priv->ppio_params.inqs_params.hash_type;
1823 rss_conf->rss_key = NULL;
1825 if (hash_type == PP2_PPIO_HASH_T_NONE)
1826 rss_conf->rss_hf = 0;
1827 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1828 rss_conf->rss_hf = ETH_RSS_IPV4;
1829 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1830 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1831 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1832 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1838 * DPDK callback to get rte_flow callbacks.
1841 * Pointer to the device structure.
1845 * Flow filter operation.
1847 * Pointer to pass the flow ops.
1850 * 0 on success, negative error value otherwise.
1853 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1854 enum rte_filter_type filter_type,
1855 enum rte_filter_op filter_op, void *arg)
1857 switch (filter_type) {
1858 case RTE_ETH_FILTER_GENERIC:
1859 if (filter_op != RTE_ETH_FILTER_GET)
1861 *(const void **)arg = &mrvl_flow_ops;
1864 MRVL_LOG(WARNING, "Filter type (%d) not supported",
1870 static const struct eth_dev_ops mrvl_ops = {
1871 .dev_configure = mrvl_dev_configure,
1872 .dev_start = mrvl_dev_start,
1873 .dev_stop = mrvl_dev_stop,
1874 .dev_set_link_up = mrvl_dev_set_link_up,
1875 .dev_set_link_down = mrvl_dev_set_link_down,
1876 .dev_close = mrvl_dev_close,
1877 .link_update = mrvl_link_update,
1878 .promiscuous_enable = mrvl_promiscuous_enable,
1879 .allmulticast_enable = mrvl_allmulticast_enable,
1880 .promiscuous_disable = mrvl_promiscuous_disable,
1881 .allmulticast_disable = mrvl_allmulticast_disable,
1882 .mac_addr_remove = mrvl_mac_addr_remove,
1883 .mac_addr_add = mrvl_mac_addr_add,
1884 .mac_addr_set = mrvl_mac_addr_set,
1885 .mtu_set = mrvl_mtu_set,
1886 .stats_get = mrvl_stats_get,
1887 .stats_reset = mrvl_stats_reset,
1888 .xstats_get = mrvl_xstats_get,
1889 .xstats_reset = mrvl_xstats_reset,
1890 .xstats_get_names = mrvl_xstats_get_names,
1891 .dev_infos_get = mrvl_dev_infos_get,
1892 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1893 .rxq_info_get = mrvl_rxq_info_get,
1894 .txq_info_get = mrvl_txq_info_get,
1895 .vlan_filter_set = mrvl_vlan_filter_set,
1896 .tx_queue_start = mrvl_tx_queue_start,
1897 .tx_queue_stop = mrvl_tx_queue_stop,
1898 .rx_queue_setup = mrvl_rx_queue_setup,
1899 .rx_queue_release = mrvl_rx_queue_release,
1900 .tx_queue_setup = mrvl_tx_queue_setup,
1901 .tx_queue_release = mrvl_tx_queue_release,
1902 .flow_ctrl_get = mrvl_flow_ctrl_get,
1903 .flow_ctrl_set = mrvl_flow_ctrl_set,
1904 .rss_hash_update = mrvl_rss_hash_update,
1905 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1906 .filter_ctrl = mrvl_eth_filter_ctrl,
1910 * Return packet type information and l3/l4 offsets.
1913 * Pointer to the received packet descriptor.
1920 * Packet type information.
1922 static inline uint64_t
1923 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1924 uint8_t *l3_offset, uint8_t *l4_offset)
1926 enum pp2_inq_l3_type l3_type;
1927 enum pp2_inq_l4_type l4_type;
1928 uint64_t packet_type;
1930 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1931 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1933 packet_type = RTE_PTYPE_L2_ETHER;
1936 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1937 packet_type |= RTE_PTYPE_L3_IPV4;
1939 case PP2_INQ_L3_TYPE_IPV4_OK:
1940 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1942 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1943 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1945 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1946 packet_type |= RTE_PTYPE_L3_IPV6;
1948 case PP2_INQ_L3_TYPE_IPV6_EXT:
1949 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1951 case PP2_INQ_L3_TYPE_ARP:
1952 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1954 * In case of ARP l4_offset is set to wrong value.
1955 * Set it to proper one so that later on mbuf->l3_len can be
1956 * calculated subtracting l4_offset and l3_offset.
1958 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1961 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
1966 case PP2_INQ_L4_TYPE_TCP:
1967 packet_type |= RTE_PTYPE_L4_TCP;
1969 case PP2_INQ_L4_TYPE_UDP:
1970 packet_type |= RTE_PTYPE_L4_UDP;
1973 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
1981 * Get offload information from the received packet descriptor.
1984 * Pointer to the received packet descriptor.
1987 * Mbuf offload flags.
1989 static inline uint64_t
1990 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1993 enum pp2_inq_desc_status status;
1995 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1996 if (unlikely(status != PP2_DESC_ERR_OK))
1997 flags = PKT_RX_IP_CKSUM_BAD;
1999 flags = PKT_RX_IP_CKSUM_GOOD;
2001 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2002 if (unlikely(status != PP2_DESC_ERR_OK))
2003 flags |= PKT_RX_L4_CKSUM_BAD;
2005 flags |= PKT_RX_L4_CKSUM_GOOD;
2011 * DPDK callback for receive.
2014 * Generic pointer to the receive queue.
2016 * Array to store received packets.
2018 * Maximum number of packets in array.
2021 * Number of packets successfully received.
2024 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2026 struct mrvl_rxq *q = rxq;
2027 struct pp2_ppio_desc descs[nb_pkts];
2028 struct pp2_bpool *bpool;
2029 int i, ret, rx_done = 0;
2031 struct pp2_hif *hif;
2032 unsigned int core_id = rte_lcore_id();
2034 hif = mrvl_get_hif(q->priv, core_id);
2036 if (unlikely(!q->priv->ppio || !hif))
2039 bpool = q->priv->bpool;
2041 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2042 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2043 if (unlikely(ret < 0)) {
2044 MRVL_LOG(ERR, "Failed to receive packets");
2047 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2049 for (i = 0; i < nb_pkts; i++) {
2050 struct rte_mbuf *mbuf;
2051 uint8_t l3_offset, l4_offset;
2052 enum pp2_inq_desc_status status;
2055 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2056 struct pp2_ppio_desc *pref_desc;
2059 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2060 pref_addr = cookie_addr_high |
2061 pp2_ppio_inq_desc_get_cookie(pref_desc);
2062 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2063 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2066 addr = cookie_addr_high |
2067 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2068 mbuf = (struct rte_mbuf *)addr;
2069 rte_pktmbuf_reset(mbuf);
2071 /* drop packet in case of mac, overrun or resource error */
2072 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2073 if (unlikely(status != PP2_DESC_ERR_OK)) {
2074 struct pp2_buff_inf binf = {
2075 .addr = rte_mbuf_data_iova_default(mbuf),
2076 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
2079 pp2_bpool_put_buff(hif, bpool, &binf);
2080 mrvl_port_bpool_size
2081 [bpool->pp2_id][bpool->id][core_id]++;
2086 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2087 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2088 mbuf->data_len = mbuf->pkt_len;
2089 mbuf->port = q->port_id;
2091 mrvl_desc_to_packet_type_and_offset(&descs[i],
2094 mbuf->l2_len = l3_offset;
2095 mbuf->l3_len = l4_offset - l3_offset;
2097 if (likely(q->cksum_enabled))
2098 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2100 rx_pkts[rx_done++] = mbuf;
2101 q->bytes_recv += mbuf->pkt_len;
2104 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2105 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2107 if (unlikely(num <= q->priv->bpool_min_size ||
2108 (!rx_done && num < q->priv->bpool_init_size))) {
2109 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2111 MRVL_LOG(ERR, "Failed to fill bpool");
2112 } else if (unlikely(num > q->priv->bpool_max_size)) {
2114 int pkt_to_remove = num - q->priv->bpool_init_size;
2115 struct rte_mbuf *mbuf;
2116 struct pp2_buff_inf buff;
2119 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2120 bpool->pp2_id, q->priv->ppio->port_id,
2121 bpool->id, pkt_to_remove, num,
2122 q->priv->bpool_init_size);
2124 for (i = 0; i < pkt_to_remove; i++) {
2125 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2128 mbuf = (struct rte_mbuf *)
2129 (cookie_addr_high | buff.cookie);
2130 rte_pktmbuf_free(mbuf);
2132 mrvl_port_bpool_size
2133 [bpool->pp2_id][bpool->id][core_id] -= i;
2135 rte_spinlock_unlock(&q->priv->lock);
2142 * Prepare offload information.
2146 * @param packet_type
2147 * Packet type bitfield.
2149 * Pointer to the pp2_ouq_l3_type structure.
2151 * Pointer to the pp2_outq_l4_type structure.
2152 * @param gen_l3_cksum
2153 * Will be set to 1 in case l3 checksum is computed.
2155 * Will be set to 1 in case l4 checksum is computed.
2158 * 0 on success, negative error value otherwise.
2161 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2162 enum pp2_outq_l3_type *l3_type,
2163 enum pp2_outq_l4_type *l4_type,
2168 * Based on ol_flags prepare information
2169 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2172 if (ol_flags & PKT_TX_IPV4) {
2173 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2174 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2175 } else if (ol_flags & PKT_TX_IPV6) {
2176 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2177 /* no checksum for ipv6 header */
2180 /* if something different then stop processing */
2184 ol_flags &= PKT_TX_L4_MASK;
2185 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2186 ol_flags == PKT_TX_TCP_CKSUM) {
2187 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2189 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2190 ol_flags == PKT_TX_UDP_CKSUM) {
2191 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2194 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2195 /* no checksum for other type */
2203 * Release already sent buffers to bpool (buffer-pool).
2206 * Pointer to the port structure.
2208 * Pointer to the MUSDK hardware interface.
2210 * Pointer to the shadow queue.
2214 * Force releasing packets.
2217 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2218 unsigned int core_id, struct mrvl_shadow_txq *sq,
2221 struct buff_release_entry *entry;
2222 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2225 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2227 sq->num_to_release += nb_done;
2229 if (likely(!force &&
2230 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2233 nb_done = sq->num_to_release;
2234 sq->num_to_release = 0;
2236 for (i = 0; i < nb_done; i++) {
2237 entry = &sq->ent[sq->tail + num];
2238 if (unlikely(!entry->buff.addr)) {
2240 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2241 sq->tail, (u64)entry->buff.cookie,
2242 (u64)entry->buff.addr);
2247 if (unlikely(!entry->bpool)) {
2248 struct rte_mbuf *mbuf;
2250 mbuf = (struct rte_mbuf *)
2251 (cookie_addr_high | entry->buff.cookie);
2252 rte_pktmbuf_free(mbuf);
2257 mrvl_port_bpool_size
2258 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2260 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2265 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2267 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2274 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2275 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2281 * DPDK callback for transmit.
2284 * Generic pointer transmit queue.
2286 * Packets to transmit.
2288 * Number of packets in array.
2291 * Number of packets successfully transmitted.
2294 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2296 struct mrvl_txq *q = txq;
2297 struct mrvl_shadow_txq *sq;
2298 struct pp2_hif *hif;
2299 struct pp2_ppio_desc descs[nb_pkts];
2300 unsigned int core_id = rte_lcore_id();
2301 int i, ret, bytes_sent = 0;
2302 uint16_t num, sq_free_size;
2305 hif = mrvl_get_hif(q->priv, core_id);
2306 sq = &q->shadow_txqs[core_id];
2308 if (unlikely(!q->priv->ppio || !hif))
2312 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2313 sq, q->queue_id, 0);
2315 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2316 if (unlikely(nb_pkts > sq_free_size)) {
2318 "No room in shadow queue for %d packets! %d packets will be sent.",
2319 nb_pkts, sq_free_size);
2320 nb_pkts = sq_free_size;
2323 for (i = 0; i < nb_pkts; i++) {
2324 struct rte_mbuf *mbuf = tx_pkts[i];
2325 int gen_l3_cksum, gen_l4_cksum;
2326 enum pp2_outq_l3_type l3_type;
2327 enum pp2_outq_l4_type l4_type;
2329 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2330 struct rte_mbuf *pref_pkt_hdr;
2332 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2333 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2334 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2337 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2338 sq->ent[sq->head].buff.addr =
2339 rte_mbuf_data_iova_default(mbuf);
2340 sq->ent[sq->head].bpool =
2341 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2342 mbuf->refcnt > 1)) ? NULL :
2343 mrvl_port_to_bpool_lookup[mbuf->port];
2344 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2347 pp2_ppio_outq_desc_reset(&descs[i]);
2348 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2349 rte_pktmbuf_iova(mbuf));
2350 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2351 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2352 rte_pktmbuf_pkt_len(mbuf));
2354 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2356 * in case unsupported ol_flags were passed
2357 * do not update descriptor offload information
2359 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2360 &l3_type, &l4_type, &gen_l3_cksum,
2365 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2367 mbuf->l2_len + mbuf->l3_len,
2368 gen_l3_cksum, gen_l4_cksum);
2372 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2373 /* number of packets that were not sent */
2374 if (unlikely(num > nb_pkts)) {
2375 for (i = nb_pkts; i < num; i++) {
2376 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2377 MRVL_PP2_TX_SHADOWQ_MASK;
2378 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2380 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2382 sq->size -= num - nb_pkts;
2385 q->bytes_sent += bytes_sent;
2391 * Initialize packet processor.
2394 * 0 on success, negative error value otherwise.
2399 struct pp2_init_params init_params;
2401 memset(&init_params, 0, sizeof(init_params));
2402 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2403 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2404 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2406 return pp2_init(&init_params);
2410 * Deinitialize packet processor.
2413 * 0 on success, negative error value otherwise.
2416 mrvl_deinit_pp2(void)
2422 * Create private device structure.
2425 * Pointer to the port name passed in the initialization parameters.
2428 * Pointer to the newly allocated private device structure.
2430 static struct mrvl_priv *
2431 mrvl_priv_create(const char *dev_name)
2433 struct pp2_bpool_params bpool_params;
2434 char match[MRVL_MATCH_LEN];
2435 struct mrvl_priv *priv;
2438 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2442 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2443 &priv->pp_id, &priv->ppio_id);
2447 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2448 PP2_BPOOL_NUM_POOLS);
2451 priv->bpool_bit = bpool_bit;
2453 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2455 memset(&bpool_params, 0, sizeof(bpool_params));
2456 bpool_params.match = match;
2457 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2458 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2460 goto out_clear_bpool_bit;
2462 priv->ppio_params.type = PP2_PPIO_T_NIC;
2463 rte_spinlock_init(&priv->lock);
2466 out_clear_bpool_bit:
2467 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2474 * Create device representing Ethernet port.
2477 * Pointer to the port's name.
2480 * 0 on success, negative error value otherwise.
2483 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2485 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2486 struct rte_eth_dev *eth_dev;
2487 struct mrvl_priv *priv;
2490 eth_dev = rte_eth_dev_allocate(name);
2494 priv = mrvl_priv_create(name);
2500 eth_dev->data->mac_addrs =
2501 rte_zmalloc("mac_addrs",
2502 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2503 if (!eth_dev->data->mac_addrs) {
2504 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2509 memset(&req, 0, sizeof(req));
2510 strcpy(req.ifr_name, name);
2511 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2515 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2516 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2518 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2519 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2520 eth_dev->data->kdrv = RTE_KDRV_NONE;
2521 eth_dev->data->dev_private = priv;
2522 eth_dev->device = &vdev->device;
2523 eth_dev->dev_ops = &mrvl_ops;
2525 rte_eth_dev_probing_finish(eth_dev);
2528 rte_free(eth_dev->data->mac_addrs);
2530 rte_eth_dev_release_port(eth_dev);
2538 * Cleanup previously created device representing Ethernet port.
2541 * Pointer to the port name.
2544 mrvl_eth_dev_destroy(const char *name)
2546 struct rte_eth_dev *eth_dev;
2547 struct mrvl_priv *priv;
2549 eth_dev = rte_eth_dev_allocated(name);
2553 priv = eth_dev->data->dev_private;
2554 pp2_bpool_deinit(priv->bpool);
2555 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2557 rte_free(eth_dev->data->mac_addrs);
2558 rte_eth_dev_release_port(eth_dev);
2562 * Callback used by rte_kvargs_process() during argument parsing.
2565 * Pointer to the parsed key (unused).
2567 * Pointer to the parsed value.
2569 * Pointer to the extra arguments which contains address of the
2570 * table of pointers to parsed interface names.
2576 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2579 struct mrvl_ifnames *ifnames = extra_args;
2581 ifnames->names[ifnames->idx++] = value;
2587 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2590 mrvl_deinit_hifs(void)
2594 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2596 pp2_hif_deinit(hifs[i]);
2598 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2599 memset(hifs, 0, sizeof(hifs));
2603 * DPDK callback to register the virtual device.
2606 * Pointer to the virtual device.
2609 * 0 on success, negative error value otherwise.
2612 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2614 struct rte_kvargs *kvlist;
2615 struct mrvl_ifnames ifnames;
2617 uint32_t i, ifnum, cfgnum;
2620 params = rte_vdev_device_args(vdev);
2624 kvlist = rte_kvargs_parse(params, valid_args);
2628 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2629 if (ifnum > RTE_DIM(ifnames.names))
2630 goto out_free_kvlist;
2633 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2634 mrvl_get_ifnames, &ifnames);
2638 * The below system initialization should be done only once,
2639 * on the first provided configuration file
2641 if (!mrvl_qos_cfg) {
2642 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2643 MRVL_LOG(INFO, "Parsing config file!");
2645 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2646 goto out_free_kvlist;
2647 } else if (cfgnum == 1) {
2648 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2649 mrvl_get_qoscfg, &mrvl_qos_cfg);
2656 MRVL_LOG(INFO, "Perform MUSDK initializations");
2658 * ret == -EEXIST is correct, it means DMA
2659 * has been already initialized (by another PMD).
2661 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2664 goto out_free_kvlist;
2667 "DMA memory has been already initialized by a different driver.");
2670 ret = mrvl_init_pp2();
2672 MRVL_LOG(ERR, "Failed to init PP!");
2673 goto out_deinit_dma;
2676 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2677 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2679 mrvl_lcore_first = RTE_MAX_LCORE;
2680 mrvl_lcore_last = 0;
2683 for (i = 0; i < ifnum; i++) {
2684 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2685 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2689 mrvl_dev_num += ifnum;
2691 rte_kvargs_free(kvlist);
2696 mrvl_eth_dev_destroy(ifnames.names[i]);
2698 if (mrvl_dev_num == 0)
2701 if (mrvl_dev_num == 0)
2702 mv_sys_dma_mem_destroy();
2704 rte_kvargs_free(kvlist);
2710 * DPDK callback to remove virtual device.
2713 * Pointer to the removed virtual device.
2716 * 0 on success, negative error value otherwise.
2719 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2724 name = rte_vdev_device_name(vdev);
2728 MRVL_LOG(INFO, "Removing %s", name);
2730 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
2731 char ifname[RTE_ETH_NAME_MAX_LEN];
2733 rte_eth_dev_get_name_by_port(i, ifname);
2734 mrvl_eth_dev_destroy(ifname);
2738 if (mrvl_dev_num == 0) {
2739 MRVL_LOG(INFO, "Perform MUSDK deinit");
2742 mv_sys_dma_mem_destroy();
2748 static struct rte_vdev_driver pmd_mrvl_drv = {
2749 .probe = rte_pmd_mrvl_probe,
2750 .remove = rte_pmd_mrvl_remove,
2753 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
2754 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
2756 RTE_INIT(mrvl_init_log);
2760 mrvl_logtype = rte_log_register("pmd.net.mvpp2");
2761 if (mrvl_logtype >= 0)
2762 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE);