1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #ifndef _MRVL_ETHDEV_H_
8 #define _MRVL_ETHDEV_H_
10 #include <rte_spinlock.h>
11 #include <rte_flow_driver.h>
14 * container_of is defined by both DPDK and MUSDK,
15 * we'll declare only one version.
17 * Note that it is not used in this PMD anyway.
23 #include <env/mv_autogen_comp_flags.h>
24 #include <drivers/mv_pp2.h>
25 #include <drivers/mv_pp2_bpool.h>
26 #include <drivers/mv_pp2_cls.h>
27 #include <drivers/mv_pp2_hif.h>
28 #include <drivers/mv_pp2_ppio.h>
29 #include "env/mv_common.h" /* for BIT() */
31 /** Maximum number of rx queues per port */
32 #define MRVL_PP2_RXQ_MAX 32
34 /** Maximum number of tx queues per port */
35 #define MRVL_PP2_TXQ_MAX 8
37 /** Minimum number of descriptors in tx queue */
38 #define MRVL_PP2_TXD_MIN 16
40 /** Maximum number of descriptors in tx queue */
41 #define MRVL_PP2_TXD_MAX 2048
43 /** Tx queue descriptors alignment */
44 #define MRVL_PP2_TXD_ALIGN 16
46 /** Minimum number of descriptors in rx queue */
47 #define MRVL_PP2_RXD_MIN 16
49 /** Maximum number of descriptors in rx queue */
50 #define MRVL_PP2_RXD_MAX 2048
52 /** Rx queue descriptors alignment */
53 #define MRVL_PP2_RXD_ALIGN 16
55 /** Maximum number of descriptors in tx aggregated queue */
56 #define MRVL_PP2_AGGR_TXQD_MAX 2048
58 /** Maximum number of Traffic Classes. */
59 #define MRVL_PP2_TC_MAX 8
61 /** Packet offset inside RX buffer. */
62 #define MRVL_PKT_OFFS 64
64 /** Maximum number of descriptors in shadow queue. Must be power of 2 */
65 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
67 /** Shadow queue size mask (since shadow queue size is power of 2) */
68 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
70 /** Minimum number of sent buffers to release from shadow queue to BM */
71 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
74 /* Hot fields, used in fast path. */
75 struct pp2_bpool *bpool; /**< BPool pointer */
76 struct pp2_ppio *ppio; /**< Port handler pointer */
77 rte_spinlock_t lock; /**< Spinlock for checking bpool status */
78 uint16_t bpool_max_size; /**< BPool maximum size */
79 uint16_t bpool_min_size; /**< BPool minimum size */
80 uint16_t bpool_init_size; /**< Configured BPool size */
82 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
84 uint8_t tc; /**< Traffic Class */
85 uint8_t inq; /**< Relative in-queue number */
86 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
88 /* Configuration data, used sporadically. */
93 uint8_t uc_mc_flushed;
97 struct pp2_ppio_params ppio_params;
98 struct pp2_cls_qos_tbl_params qos_tbl_params;
99 struct pp2_cls_tbl *qos_tbl;
100 uint16_t nb_rx_queues;
102 struct pp2_cls_tbl_params cls_tbl_params;
103 struct pp2_cls_tbl *cls_tbl;
104 uint32_t cls_tbl_pattern;
105 LIST_HEAD(mrvl_flows, rte_flow) flows;
107 struct pp2_cls_plcr *policer;
110 /** Flow operations forward declaration. */
111 extern const struct rte_flow_ops mrvl_flow_ops;
113 /** Current log type. */
114 extern int mrvl_logtype;
116 #define MRVL_LOG(level, fmt, args...) \
117 rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \
120 #endif /* _MRVL_ETHDEV_H_ */