drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfpcore/nfp_cpp.h"
  59 #include "nfpcore/nfp_nffw.h"
  60 #include "nfpcore/nfp_hwinfo.h"
  61 #include "nfpcore/nfp_mip.h"
  62 #include "nfpcore/nfp_rtsym.h"
  63 #include "nfpcore/nfp_nsp.h"
  64
  65 #include "nfp_net_pmd.h"
  66 #include "nfp_net_logs.h"
  67 #include "nfp_net_ctrl.h"
  68
  69 /* Prototypes */
  70 static void nfp_net_close(struct rte_eth_dev *dev);
  71 static int nfp_net_configure(struct rte_eth_dev *dev);
  72 static void nfp_net_dev_interrupt_handler(void *param);
  73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  76                               struct rte_eth_dev_info *dev_info);
  77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  83                                        uint16_t queue_idx);
  84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  85                                   uint16_t nb_pkts);
  86 static void nfp_net_rx_queue_release(void *rxq);
  87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_rxconf *rx_conf,
  90                                   struct rte_mempool *mp);
  91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  92 static void nfp_net_tx_queue_release(void *txq);
  93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  94                                   uint16_t nb_desc, unsigned int socket_id,
  95                                   const struct rte_eth_txconf *tx_conf);
  96 static int nfp_net_start(struct rte_eth_dev *dev);
  97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  98                               struct rte_eth_stats *stats);
  99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
 100 static void nfp_net_stop(struct rte_eth_dev *dev);
 101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 102                                   uint16_t nb_pkts);
 103
 104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
 105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 106                                    struct rte_eth_rss_conf *rss_conf);
 107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 108                     struct rte_eth_rss_reta_entry64 *reta_conf,
 109                     uint16_t reta_size);
 110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 111                         struct rte_eth_rss_conf *rss_conf);
 112 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
 113                              struct ether_addr *mac_addr);
 114
 115 /* The offset of the queue controller queues in the PCIe Target */
 116 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 117
 118 /* Maximum value which can be added to a queue with one transaction */
 119 #define NFP_QCP_MAX_ADD 0x7f
 120
 121 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 122         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 123
 124 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 125 enum nfp_qcp_ptr {
 126         NFP_QCP_READ_PTR = 0,
 127         NFP_QCP_WRITE_PTR
 128 };
 129
 130 /*
 131  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 132  * @q: Base address for queue structure
 133  * @ptr: Add to the Read or Write pointer
 134  * @val: Value to add to the queue pointer
 135  *
 136  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 137  */
 138 static inline void
 139 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 140 {
 141         uint32_t off;
 142
 143         if (ptr == NFP_QCP_READ_PTR)
 144                 off = NFP_QCP_QUEUE_ADD_RPTR;
 145         else
 146                 off = NFP_QCP_QUEUE_ADD_WPTR;
 147
 148         while (val > NFP_QCP_MAX_ADD) {
 149                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 150                 val -= NFP_QCP_MAX_ADD;
 151         }
 152
 153         nn_writel(rte_cpu_to_le_32(val), q + off);
 154 }
 155
 156 /*
 157  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 158  * @q:  Base address for queue structure
 159  * @ptr: Read or Write pointer
 160  */
 161 static inline uint32_t
 162 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 163 {
 164         uint32_t off;
 165         uint32_t val;
 166
 167         if (ptr == NFP_QCP_READ_PTR)
 168                 off = NFP_QCP_QUEUE_STS_LO;
 169         else
 170                 off = NFP_QCP_QUEUE_STS_HI;
 171
 172         val = rte_cpu_to_le_32(nn_readl(q + off));
 173
 174         if (ptr == NFP_QCP_READ_PTR)
 175                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 176         else
 177                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 178 }
 179
 180 /*
 181  * Functions to read/write from/to Config BAR
 182  * Performs any endian conversion necessary.
 183  */
 184 static inline uint8_t
 185 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 186 {
 187         return nn_readb(hw->ctrl_bar + off);
 188 }
 189
 190 static inline void
 191 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 192 {
 193         nn_writeb(val, hw->ctrl_bar + off);
 194 }
 195
 196 static inline uint32_t
 197 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 198 {
 199         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 200 }
 201
 202 static inline void
 203 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 204 {
 205         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 206 }
 207
 208 static inline uint64_t
 209 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 210 {
 211         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 212 }
 213
 214 static inline void
 215 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 216 {
 217         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 218 }
 219
 220 static void
 221 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 222 {
 223         unsigned i;
 224
 225         if (rxq->rxbufs == NULL)
 226                 return;
 227
 228         for (i = 0; i < rxq->rx_count; i++) {
 229                 if (rxq->rxbufs[i].mbuf) {
 230                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 231                         rxq->rxbufs[i].mbuf = NULL;
 232                 }
 233         }
 234 }
 235
 236 static void
 237 nfp_net_rx_queue_release(void *rx_queue)
 238 {
 239         struct nfp_net_rxq *rxq = rx_queue;
 240
 241         if (rxq) {
 242                 nfp_net_rx_queue_release_mbufs(rxq);
 243                 rte_free(rxq->rxbufs);
 244                 rte_free(rxq);
 245         }
 246 }
 247
 248 static void
 249 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 250 {
 251         nfp_net_rx_queue_release_mbufs(rxq);
 252         rxq->rd_p = 0;
 253         rxq->nb_rx_hold = 0;
 254 }
 255
 256 static void
 257 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 258 {
 259         unsigned i;
 260
 261         if (txq->txbufs == NULL)
 262                 return;
 263
 264         for (i = 0; i < txq->tx_count; i++) {
 265                 if (txq->txbufs[i].mbuf) {
 266                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 267                         txq->txbufs[i].mbuf = NULL;
 268                 }
 269         }
 270 }
 271
 272 static void
 273 nfp_net_tx_queue_release(void *tx_queue)
 274 {
 275         struct nfp_net_txq *txq = tx_queue;
 276
 277         if (txq) {
 278                 nfp_net_tx_queue_release_mbufs(txq);
 279                 rte_free(txq->txbufs);
 280                 rte_free(txq);
 281         }
 282 }
 283
 284 static void
 285 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 286 {
 287         nfp_net_tx_queue_release_mbufs(txq);
 288         txq->wr_p = 0;
 289         txq->rd_p = 0;
 290 }
 291
 292 static int
 293 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 294 {
 295         int cnt;
 296         uint32_t new;
 297         struct timespec wait;
 298
 299         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 300                     hw->qcp_cfg);
 301
 302         if (hw->qcp_cfg == NULL)
 303                 rte_panic("Bad configuration queue pointer\n");
 304
 305         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 306
 307         wait.tv_sec = 0;
 308         wait.tv_nsec = 1000000;
 309
 310         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 311
 312         /* Poll update field, waiting for NFP to ack the config */
 313         for (cnt = 0; ; cnt++) {
 314                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 315                 if (new == 0)
 316                         break;
 317                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 318                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 319                         return -1;
 320                 }
 321                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 322                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 323                                           " %dms", update, cnt);
 324                         rte_panic("Exiting\n");
 325                 }
 326                 nanosleep(&wait, 0); /* waiting for a 1ms */
 327         }
 328         PMD_DRV_LOG(DEBUG, "Ack DONE");
 329         return 0;
 330 }
 331
 332 /*
 333  * Reconfigure the NIC
 334  * @nn:    device to reconfigure
 335  * @ctrl:    The value for the ctrl field in the BAR config
 336  * @update:  The value for the update field in the BAR config
 337  *
 338  * Write the update word to the BAR and ping the reconfig queue. Then poll
 339  * until the firmware has acknowledged the update by zeroing the update word.
 340  */
 341 static int
 342 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 343 {
 344         uint32_t err;
 345
 346         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 347                     ctrl, update);
 348
 349         rte_spinlock_lock(&hw->reconfig_lock);
 350
 351         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 352         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 353
 354         rte_wmb();
 355
 356         err = __nfp_net_reconfig(hw, update);
 357
 358         rte_spinlock_unlock(&hw->reconfig_lock);
 359
 360         if (!err)
 361                 return 0;
 362
 363         /*
 364          * Reconfig errors imply situations where they can be handled.
 365          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 366          */
 367         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 368                      ctrl, update);
 369         return -EIO;
 370 }
 371
 372 /*
 373  * Configure an Ethernet device. This function must be invoked first
 374  * before any other function in the Ethernet API. This function can
 375  * also be re-invoked when a device is in the stopped state.
 376  */
 377 static int
 378 nfp_net_configure(struct rte_eth_dev *dev)
 379 {
 380         struct rte_eth_conf *dev_conf;
 381         struct rte_eth_rxmode *rxmode;
 382         struct rte_eth_txmode *txmode;
 383         struct nfp_net_hw *hw;
 384
 385         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 386
 387         /*
 388          * A DPDK app sends info about how many queues to use and how
 389          * those queues need to be configured. This is used by the
 390          * DPDK core and it makes sure no more queues than those
 391          * advertised by the driver are requested. This function is
 392          * called after that internal process
 393          */
 394
 395         PMD_INIT_LOG(DEBUG, "Configure");
 396
 397         dev_conf = &dev->data->dev_conf;
 398         rxmode = &dev_conf->rxmode;
 399         txmode = &dev_conf->txmode;
 400
 401         /* Checking TX mode */
 402         if (txmode->mq_mode) {
 403                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 404                 return -EINVAL;
 405         }
 406
 407         /* Checking RX mode */
 408         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 409             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 410                 PMD_INIT_LOG(INFO, "RSS not supported");
 411                 return -EINVAL;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static void
 418 nfp_net_enable_queues(struct rte_eth_dev *dev)
 419 {
 420         struct nfp_net_hw *hw;
 421         uint64_t enabled_queues = 0;
 422         int i;
 423
 424         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 425
 426         /* Enabling the required TX queues in the device */
 427         for (i = 0; i < dev->data->nb_tx_queues; i++)
 428                 enabled_queues |= (1 << i);
 429
 430         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 431
 432         enabled_queues = 0;
 433
 434         /* Enabling the required RX queues in the device */
 435         for (i = 0; i < dev->data->nb_rx_queues; i++)
 436                 enabled_queues |= (1 << i);
 437
 438         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 439 }
 440
 441 static void
 442 nfp_net_disable_queues(struct rte_eth_dev *dev)
 443 {
 444         struct nfp_net_hw *hw;
 445         uint32_t new_ctrl, update = 0;
 446
 447         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 448
 449         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 450         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 451
 452         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 453         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 454                  NFP_NET_CFG_UPDATE_MSIX;
 455
 456         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 457                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 458
 459         /* If an error when reconfig we avoid to change hw state */
 460         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 461                 return;
 462
 463         hw->ctrl = new_ctrl;
 464 }
 465
 466 static int
 467 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 468 {
 469         int i;
 470
 471         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 472                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 473                         return -1;
 474         }
 475         return 0;
 476 }
 477
 478 static void
 479 nfp_net_params_setup(struct nfp_net_hw *hw)
 480 {
 481         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 482         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 483 }
 484
 485 static void
 486 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 487 {
 488         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 489 }
 490
 491 #define ETH_ADDR_LEN    6
 492
 493 static void
 494 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 495 {
 496         int i;
 497
 498         for (i = 0; i < ETH_ADDR_LEN; i++)
 499                 dst[i] = src[i];
 500 }
 501
 502 static int
 503 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 504 {
 505         struct nfp_eth_table *nfp_eth_table;
 506
 507         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 508         /*
 509          * hw points to port0 private data. We need hw now pointing to
 510          * right port.
 511          */
 512         hw += port;
 513         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 514                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 515
 516         free(nfp_eth_table);
 517         return 0;
 518 }
 519
 520 static void
 521 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 522 {
 523         uint32_t tmp;
 524
 525         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 526         memcpy(&hw->mac_addr[0], &tmp, 4);
 527
 528         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 529         memcpy(&hw->mac_addr[4], &tmp, 2);
 530 }
 531
 532 static void
 533 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 534 {
 535         uint32_t mac0 = *(uint32_t *)mac;
 536         uint16_t mac1;
 537
 538         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 539
 540         mac += 4;
 541         mac1 = *(uint16_t *)mac;
 542         nn_writew(rte_cpu_to_be_16(mac1),
 543                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 544 }
 545
 546 int
 547 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 548 {
 549         struct nfp_net_hw *hw;
 550         uint32_t update, ctrl;
 551
 552         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 554             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 555                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 556                                   " port enabled");
 557                 return -EBUSY;
 558         }
 559
 560         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 561             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 562                 return -EBUSY;
 563
 564         /* Writing new MAC to the specific port BAR address */
 565         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 566
 567         /* Signal the NIC about the change */
 568         update = NFP_NET_CFG_UPDATE_MACADDR;
 569         ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR;
 570         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 571                 PMD_INIT_LOG(INFO, "MAC address update failed");
 572                 return -EIO;
 573         }
 574         return 0;
 575 }
 576
 577 static int
 578 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 579                            struct rte_intr_handle *intr_handle)
 580 {
 581         struct nfp_net_hw *hw;
 582         int i;
 583
 584         if (!intr_handle->intr_vec) {
 585                 intr_handle->intr_vec =
 586                         rte_zmalloc("intr_vec",
 587                                     dev->data->nb_rx_queues * sizeof(int), 0);
 588                 if (!intr_handle->intr_vec) {
 589                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 590                                      " intr_vec", dev->data->nb_rx_queues);
 591                         return -ENOMEM;
 592                 }
 593         }
 594
 595         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 596
 597         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 598                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 599                 /* UIO just supports one queue and no LSC*/
 600                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 601                 intr_handle->intr_vec[0] = 0;
 602         } else {
 603                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 604                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 605                         /*
 606                          * The first msix vector is reserved for non
 607                          * efd interrupts
 608                         */
 609                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 610                         intr_handle->intr_vec[i] = i + 1;
 611                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 612                                             intr_handle->intr_vec[i]);
 613                 }
 614         }
 615
 616         /* Avoiding TX interrupts */
 617         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 618         return 0;
 619 }
 620
 621 static uint32_t
 622 nfp_check_offloads(struct rte_eth_dev *dev)
 623 {
 624         struct nfp_net_hw *hw;
 625         struct rte_eth_conf *dev_conf;
 626         struct rte_eth_rxmode *rxmode;
 627         struct rte_eth_txmode *txmode;
 628         uint32_t ctrl = 0;
 629
 630         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632         dev_conf = &dev->data->dev_conf;
 633         rxmode = &dev_conf->rxmode;
 634         txmode = &dev_conf->txmode;
 635
 636         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 637                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 638                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 639         }
 640
 641         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 642                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 643                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 644         }
 645
 646         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 647                 hw->mtu = rxmode->max_rx_pkt_len;
 648
 649         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 650                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 651
 652         /* L2 broadcast */
 653         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 654                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 655
 656         /* L2 multicast */
 657         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 658                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 659
 660         /* TX checksum offload */
 661         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 662             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 663             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 664                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 665
 666         /* LSO offload */
 667         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 668                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 669                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 670                 else
 671                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 672         }
 673
 674         /* RX gather */
 675         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 676                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 677
 678         return ctrl;
 679 }
 680
 681 static int
 682 nfp_net_start(struct rte_eth_dev *dev)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t new_ctrl, update = 0;
 687         struct nfp_net_hw *hw;
 688         struct rte_eth_conf *dev_conf;
 689         struct rte_eth_rxmode *rxmode;
 690         uint32_t intr_vector;
 691         int ret;
 692
 693         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 694
 695         PMD_INIT_LOG(DEBUG, "Start");
 696
 697         /* Disabling queues just in case... */
 698         nfp_net_disable_queues(dev);
 699
 700         /* Enabling the required queues in the device */
 701         nfp_net_enable_queues(dev);
 702
 703         /* check and configure queue intr-vector mapping */
 704         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 705                 if (hw->pf_multiport_enabled) {
 706                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 707                                           "with NFP multiport PF");
 708                                 return -EINVAL;
 709                 }
 710                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 711                         /*
 712                          * Better not to share LSC with RX interrupts.
 713                          * Unregistering LSC interrupt handler
 714                          */
 715                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 716                                 nfp_net_dev_interrupt_handler, (void *)dev);
 717
 718                         if (dev->data->nb_rx_queues > 1) {
 719                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 720                                              "supports 1 queue with UIO");
 721                                 return -EIO;
 722                         }
 723                 }
 724                 intr_vector = dev->data->nb_rx_queues;
 725                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 726                         return -1;
 727
 728                 nfp_configure_rx_interrupt(dev, intr_handle);
 729                 update = NFP_NET_CFG_UPDATE_MSIX;
 730         }
 731
 732         rte_intr_enable(intr_handle);
 733
 734         new_ctrl = nfp_check_offloads(dev);
 735
 736         /* Writing configuration parameters in the device */
 737         nfp_net_params_setup(hw);
 738
 739         dev_conf = &dev->data->dev_conf;
 740         rxmode = &dev_conf->rxmode;
 741
 742         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 743                 nfp_net_rss_config_default(dev);
 744                 update |= NFP_NET_CFG_UPDATE_RSS;
 745                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 746         }
 747
 748         /* Enable device */
 749         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 750
 751         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 752
 753         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 754                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 755
 756         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 757         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 758                 return -EIO;
 759
 760         /*
 761          * Allocating rte mbuffs for configured rx queues.
 762          * This requires queues being enabled before
 763          */
 764         if (nfp_net_rx_freelist_setup(dev) < 0) {
 765                 ret = -ENOMEM;
 766                 goto error;
 767         }
 768
 769         if (hw->is_pf)
 770                 /* Configure the physical port up */
 771                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 772
 773         hw->ctrl = new_ctrl;
 774
 775         return 0;
 776
 777 error:
 778         /*
 779          * An error returned by this function should mean the app
 780          * exiting and then the system releasing all the memory
 781          * allocated even memory coming from hugepages.
 782          *
 783          * The device could be enabled at this point with some queues
 784          * ready for getting packets. This is true if the call to
 785          * nfp_net_rx_freelist_setup() succeeds for some queues but
 786          * fails for subsequent queues.
 787          *
 788          * This should make the app exiting but better if we tell the
 789          * device first.
 790          */
 791         nfp_net_disable_queues(dev);
 792
 793         return ret;
 794 }
 795
 796 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 797 static void
 798 nfp_net_stop(struct rte_eth_dev *dev)
 799 {
 800         int i;
 801         struct nfp_net_hw *hw;
 802
 803         PMD_INIT_LOG(DEBUG, "Stop");
 804
 805         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 806
 807         nfp_net_disable_queues(dev);
 808
 809         /* Clear queues */
 810         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 811                 nfp_net_reset_tx_queue(
 812                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 813         }
 814
 815         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 816                 nfp_net_reset_rx_queue(
 817                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 818         }
 819
 820         if (hw->is_pf)
 821                 /* Configure the physical port down */
 822                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 823 }
 824
 825 /* Reset and stop device. The device can not be restarted. */
 826 static void
 827 nfp_net_close(struct rte_eth_dev *dev)
 828 {
 829         struct nfp_net_hw *hw;
 830         struct rte_pci_device *pci_dev;
 831         int i;
 832
 833         PMD_INIT_LOG(DEBUG, "Close");
 834
 835         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 836         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 837
 838         /*
 839          * We assume that the DPDK application is stopping all the
 840          * threads/queues before calling the device close function.
 841          */
 842
 843         nfp_net_disable_queues(dev);
 844
 845         /* Clear queues */
 846         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 847                 nfp_net_reset_tx_queue(
 848                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 849         }
 850
 851         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 852                 nfp_net_reset_rx_queue(
 853                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 854         }
 855
 856         rte_intr_disable(&pci_dev->intr_handle);
 857         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 858
 859         /* unregister callback func from eal lib */
 860         rte_intr_callback_unregister(&pci_dev->intr_handle,
 861                                      nfp_net_dev_interrupt_handler,
 862                                      (void *)dev);
 863
 864         /*
 865          * The ixgbe PMD driver disables the pcie master on the
 866          * device. The i40e does not...
 867          */
 868 }
 869
 870 static void
 871 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 872 {
 873         uint32_t new_ctrl, update = 0;
 874         struct nfp_net_hw *hw;
 875
 876         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 877
 878         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 879
 880         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 881                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 882                 return;
 883         }
 884
 885         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 886                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 887                 return;
 888         }
 889
 890         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 891         update = NFP_NET_CFG_UPDATE_GEN;
 892
 893         /*
 894          * DPDK sets promiscuous mode on just after this call assuming
 895          * it can not fail ...
 896          */
 897         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 898                 return;
 899
 900         hw->ctrl = new_ctrl;
 901 }
 902
 903 static void
 904 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 905 {
 906         uint32_t new_ctrl, update = 0;
 907         struct nfp_net_hw *hw;
 908
 909         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 910
 911         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 912                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 913                 return;
 914         }
 915
 916         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 917         update = NFP_NET_CFG_UPDATE_GEN;
 918
 919         /*
 920          * DPDK sets promiscuous mode off just before this call
 921          * assuming it can not fail ...
 922          */
 923         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 924                 return;
 925
 926         hw->ctrl = new_ctrl;
 927 }
 928
 929 /*
 930  * return 0 means link status changed, -1 means not changed
 931  *
 932  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 933  * status.
 934  */
 935 static int
 936 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 937 {
 938         struct nfp_net_hw *hw;
 939         struct rte_eth_link link;
 940         uint32_t nn_link_status;
 941         int ret;
 942
 943         static const uint32_t ls_to_ethtool[] = {
 944                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 945                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 946                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 947                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 948                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 949                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 950                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 951                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 952         };
 953
 954         PMD_DRV_LOG(DEBUG, "Link update");
 955
 956         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 957
 958         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 959
 960         memset(&link, 0, sizeof(struct rte_eth_link));
 961
 962         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 963                 link.link_status = ETH_LINK_UP;
 964
 965         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 966
 967         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 968                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 969
 970         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 971                 link.link_speed = ETH_SPEED_NUM_NONE;
 972         else
 973                 link.link_speed = ls_to_ethtool[nn_link_status];
 974
 975         ret = rte_eth_linkstatus_set(dev, &link);
 976         if (ret == 0) {
 977                 if (link.link_status)
 978                         PMD_DRV_LOG(INFO, "NIC Link is Up");
 979                 else
 980                         PMD_DRV_LOG(INFO, "NIC Link is Down");
 981         }
 982         return ret;
 983 }
 984
 985 static int
 986 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 987 {
 988         int i;
 989         struct nfp_net_hw *hw;
 990         struct rte_eth_stats nfp_dev_stats;
 991
 992         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 993
 994         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
 995
 996         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
 997
 998         /* reading per RX ring stats */
 999         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1000                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1001                         break;
1002
1003                 nfp_dev_stats.q_ipackets[i] =
1004                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1005
1006                 nfp_dev_stats.q_ipackets[i] -=
1007                         hw->eth_stats_base.q_ipackets[i];
1008
1009                 nfp_dev_stats.q_ibytes[i] =
1010                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1011
1012                 nfp_dev_stats.q_ibytes[i] -=
1013                         hw->eth_stats_base.q_ibytes[i];
1014         }
1015
1016         /* reading per TX ring stats */
1017         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1018                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1019                         break;
1020
1021                 nfp_dev_stats.q_opackets[i] =
1022                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1023
1024                 nfp_dev_stats.q_opackets[i] -=
1025                         hw->eth_stats_base.q_opackets[i];
1026
1027                 nfp_dev_stats.q_obytes[i] =
1028                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1029
1030                 nfp_dev_stats.q_obytes[i] -=
1031                         hw->eth_stats_base.q_obytes[i];
1032         }
1033
1034         nfp_dev_stats.ipackets =
1035                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1036
1037         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1038
1039         nfp_dev_stats.ibytes =
1040                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1041
1042         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1043
1044         nfp_dev_stats.opackets =
1045                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1046
1047         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1048
1049         nfp_dev_stats.obytes =
1050                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1051
1052         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1053
1054         /* reading general device stats */
1055         nfp_dev_stats.ierrors =
1056                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1057
1058         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1059
1060         nfp_dev_stats.oerrors =
1061                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1062
1063         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1064
1065         /* RX ring mbuf allocation failures */
1066         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1067
1068         nfp_dev_stats.imissed =
1069                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1070
1071         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1072
1073         if (stats) {
1074                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1075                 return 0;
1076         }
1077         return -EINVAL;
1078 }
1079
1080 static void
1081 nfp_net_stats_reset(struct rte_eth_dev *dev)
1082 {
1083         int i;
1084         struct nfp_net_hw *hw;
1085
1086         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087
1088         /*
1089          * hw->eth_stats_base records the per counter starting point.
1090          * Lets update it now
1091          */
1092
1093         /* reading per RX ring stats */
1094         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1095                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1096                         break;
1097
1098                 hw->eth_stats_base.q_ipackets[i] =
1099                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1100
1101                 hw->eth_stats_base.q_ibytes[i] =
1102                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1103         }
1104
1105         /* reading per TX ring stats */
1106         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1107                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1108                         break;
1109
1110                 hw->eth_stats_base.q_opackets[i] =
1111                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1112
1113                 hw->eth_stats_base.q_obytes[i] =
1114                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1115         }
1116
1117         hw->eth_stats_base.ipackets =
1118                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1119
1120         hw->eth_stats_base.ibytes =
1121                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1122
1123         hw->eth_stats_base.opackets =
1124                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1125
1126         hw->eth_stats_base.obytes =
1127                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1128
1129         /* reading general device stats */
1130         hw->eth_stats_base.ierrors =
1131                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1132
1133         hw->eth_stats_base.oerrors =
1134                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1135
1136         /* RX ring mbuf allocation failures */
1137         dev->data->rx_mbuf_alloc_failed = 0;
1138
1139         hw->eth_stats_base.imissed =
1140                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1141 }
1142
1143 static void
1144 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1145 {
1146         struct nfp_net_hw *hw;
1147
1148         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149
1150         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1151         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1152         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1153         dev_info->max_rx_pktlen = hw->max_mtu;
1154         /* Next should change when PF support is implemented */
1155         dev_info->max_mac_addrs = 1;
1156
1157         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1158                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1159
1160         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1161                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1162                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1163                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1164
1165         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1166
1167         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1168                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1169
1170         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1171                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1172                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1173                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1174
1175         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1176                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1177
1178         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1179                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1180
1181         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1182                 .rx_thresh = {
1183                         .pthresh = DEFAULT_RX_PTHRESH,
1184                         .hthresh = DEFAULT_RX_HTHRESH,
1185                         .wthresh = DEFAULT_RX_WTHRESH,
1186                 },
1187                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1188                 .rx_drop_en = 0,
1189         };
1190
1191         dev_info->default_txconf = (struct rte_eth_txconf) {
1192                 .tx_thresh = {
1193                         .pthresh = DEFAULT_TX_PTHRESH,
1194                         .hthresh = DEFAULT_TX_HTHRESH,
1195                         .wthresh = DEFAULT_TX_WTHRESH,
1196                 },
1197                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1198                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1199         };
1200
1201         dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1202                                            ETH_RSS_NONFRAG_IPV4_UDP |
1203                                            ETH_RSS_NONFRAG_IPV6_TCP |
1204                                            ETH_RSS_NONFRAG_IPV6_UDP;
1205
1206         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1207         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1208
1209         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1210                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1211                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1212 }
1213
1214 static const uint32_t *
1215 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1216 {
1217         static const uint32_t ptypes[] = {
1218                 /* refers to nfp_net_set_hash() */
1219                 RTE_PTYPE_INNER_L3_IPV4,
1220                 RTE_PTYPE_INNER_L3_IPV6,
1221                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1222                 RTE_PTYPE_INNER_L4_MASK,
1223                 RTE_PTYPE_UNKNOWN
1224         };
1225
1226         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1227                 return ptypes;
1228         return NULL;
1229 }
1230
1231 static uint32_t
1232 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1233 {
1234         struct nfp_net_rxq *rxq;
1235         struct nfp_net_rx_desc *rxds;
1236         uint32_t idx;
1237         uint32_t count;
1238
1239         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1240
1241         idx = rxq->rd_p;
1242
1243         count = 0;
1244
1245         /*
1246          * Other PMDs are just checking the DD bit in intervals of 4
1247          * descriptors and counting all four if the first has the DD
1248          * bit on. Of course, this is not accurate but can be good for
1249          * performance. But ideally that should be done in descriptors
1250          * chunks belonging to the same cache line
1251          */
1252
1253         while (count < rxq->rx_count) {
1254                 rxds = &rxq->rxds[idx];
1255                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1256                         break;
1257
1258                 count++;
1259                 idx++;
1260
1261                 /* Wrapping? */
1262                 if ((idx) == rxq->rx_count)
1263                         idx = 0;
1264         }
1265
1266         return count;
1267 }
1268
1269 static int
1270 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1271 {
1272         struct rte_pci_device *pci_dev;
1273         struct nfp_net_hw *hw;
1274         int base = 0;
1275
1276         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1277         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1278
1279         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1280                 base = 1;
1281
1282         /* Make sure all updates are written before un-masking */
1283         rte_wmb();
1284         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1285                       NFP_NET_CFG_ICR_UNMASKED);
1286         return 0;
1287 }
1288
1289 static int
1290 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1291 {
1292         struct rte_pci_device *pci_dev;
1293         struct nfp_net_hw *hw;
1294         int base = 0;
1295
1296         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1297         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1298
1299         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1300                 base = 1;
1301
1302         /* Make sure all updates are written before un-masking */
1303         rte_wmb();
1304         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1305         return 0;
1306 }
1307
1308 static void
1309 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1310 {
1311         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1312         struct rte_eth_link link;
1313
1314         rte_eth_linkstatus_get(dev, &link);
1315         if (link.link_status)
1316                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1317                             dev->data->port_id, link.link_speed,
1318                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1319                             ? "full-duplex" : "half-duplex");
1320         else
1321                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1322                             dev->data->port_id);
1323
1324         PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1325                 pci_dev->addr.domain, pci_dev->addr.bus,
1326                 pci_dev->addr.devid, pci_dev->addr.function);
1327 }
1328
1329 /* Interrupt configuration and handling */
1330
1331 /*
1332  * nfp_net_irq_unmask - Unmask an interrupt
1333  *
1334  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1335  * clear the ICR for the entry.
1336  */
1337 static void
1338 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1339 {
1340         struct nfp_net_hw *hw;
1341         struct rte_pci_device *pci_dev;
1342
1343         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1344         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1345
1346         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1347                 /* If MSI-X auto-masking is used, clear the entry */
1348                 rte_wmb();
1349                 rte_intr_enable(&pci_dev->intr_handle);
1350         } else {
1351                 /* Make sure all updates are written before un-masking */
1352                 rte_wmb();
1353                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1354                               NFP_NET_CFG_ICR_UNMASKED);
1355         }
1356 }
1357
1358 static void
1359 nfp_net_dev_interrupt_handler(void *param)
1360 {
1361         int64_t timeout;
1362         struct rte_eth_link link;
1363         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1364
1365         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1366
1367         rte_eth_linkstatus_get(dev, &link);
1368
1369         nfp_net_link_update(dev, 0);
1370
1371         /* likely to up */
1372         if (!link.link_status) {
1373                 /* handle it 1 sec later, wait it being stable */
1374                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1375                 /* likely to down */
1376         } else {
1377                 /* handle it 4 sec later, wait it being stable */
1378                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1379         }
1380
1381         if (rte_eal_alarm_set(timeout * 1000,
1382                               nfp_net_dev_interrupt_delayed_handler,
1383                               (void *)dev) < 0) {
1384                 PMD_INIT_LOG(ERR, "Error setting alarm");
1385                 /* Unmasking */
1386                 nfp_net_irq_unmask(dev);
1387         }
1388 }
1389
1390 /*
1391  * Interrupt handler which shall be registered for alarm callback for delayed
1392  * handling specific interrupt to wait for the stable nic state. As the NIC
1393  * interrupt state is not stable for nfp after link is just down, it needs
1394  * to wait 4 seconds to get the stable status.
1395  *
1396  * @param handle   Pointer to interrupt handle.
1397  * @param param    The address of parameter (struct rte_eth_dev *)
1398  *
1399  * @return  void
1400  */
1401 static void
1402 nfp_net_dev_interrupt_delayed_handler(void *param)
1403 {
1404         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1405
1406         nfp_net_link_update(dev, 0);
1407         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1408
1409         nfp_net_dev_link_status_print(dev);
1410
1411         /* Unmasking */
1412         nfp_net_irq_unmask(dev);
1413 }
1414
1415 static int
1416 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1417 {
1418         struct nfp_net_hw *hw;
1419
1420         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421
1422         /* check that mtu is within the allowed range */
1423         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1424                 return -EINVAL;
1425
1426         /* mtu setting is forbidden if port is started */
1427         if (dev->data->dev_started) {
1428                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1429                             dev->data->port_id);
1430                 return -EBUSY;
1431         }
1432
1433         /* switch to jumbo mode if needed */
1434         if ((uint32_t)mtu > ETHER_MAX_LEN)
1435                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1436         else
1437                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1438
1439         /* update max frame size */
1440         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1441
1442         /* writing to configuration space */
1443         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1444
1445         hw->mtu = mtu;
1446
1447         return 0;
1448 }
1449
1450 static int
1451 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1452                        uint16_t queue_idx, uint16_t nb_desc,
1453                        unsigned int socket_id,
1454                        const struct rte_eth_rxconf *rx_conf,
1455                        struct rte_mempool *mp)
1456 {
1457         const struct rte_memzone *tz;
1458         struct nfp_net_rxq *rxq;
1459         struct nfp_net_hw *hw;
1460
1461         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462
1463         PMD_INIT_FUNC_TRACE();
1464
1465         /* Validating number of descriptors */
1466         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1467             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1468             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1469                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1470                 return -EINVAL;
1471         }
1472
1473         /*
1474          * Free memory prior to re-allocation if needed. This is the case after
1475          * calling nfp_net_stop
1476          */
1477         if (dev->data->rx_queues[queue_idx]) {
1478                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1479                 dev->data->rx_queues[queue_idx] = NULL;
1480         }
1481
1482         /* Allocating rx queue data structure */
1483         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1484                                  RTE_CACHE_LINE_SIZE, socket_id);
1485         if (rxq == NULL)
1486                 return -ENOMEM;
1487
1488         /* Hw queues mapping based on firmware confifguration */
1489         rxq->qidx = queue_idx;
1490         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1491         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1492         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1493         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1494
1495         /*
1496          * Tracking mbuf size for detecting a potential mbuf overflow due to
1497          * RX offset
1498          */
1499         rxq->mem_pool = mp;
1500         rxq->mbuf_size = rxq->mem_pool->elt_size;
1501         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1502         hw->flbufsz = rxq->mbuf_size;
1503
1504         rxq->rx_count = nb_desc;
1505         rxq->port_id = dev->data->port_id;
1506         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1507         rxq->drop_en = rx_conf->rx_drop_en;
1508
1509         /*
1510          * Allocate RX ring hardware descriptors. A memzone large enough to
1511          * handle the maximum ring size is allocated in order to allow for
1512          * resizing in later calls to the queue setup function.
1513          */
1514         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1515                                    sizeof(struct nfp_net_rx_desc) *
1516                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1517                                    socket_id);
1518
1519         if (tz == NULL) {
1520                 PMD_DRV_LOG(ERR, "Error allocatig rx dma");
1521                 nfp_net_rx_queue_release(rxq);
1522                 return -ENOMEM;
1523         }
1524
1525         /* Saving physical and virtual addresses for the RX ring */
1526         rxq->dma = (uint64_t)tz->iova;
1527         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1528
1529         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1530         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1531                                          sizeof(*rxq->rxbufs) * nb_desc,
1532                                          RTE_CACHE_LINE_SIZE, socket_id);
1533         if (rxq->rxbufs == NULL) {
1534                 nfp_net_rx_queue_release(rxq);
1535                 return -ENOMEM;
1536         }
1537
1538         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1539                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1540
1541         nfp_net_reset_rx_queue(rxq);
1542
1543         dev->data->rx_queues[queue_idx] = rxq;
1544         rxq->hw = hw;
1545
1546         /*
1547          * Telling the HW about the physical address of the RX ring and number
1548          * of descriptors in log2 format
1549          */
1550         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1551         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1552
1553         return 0;
1554 }
1555
1556 static int
1557 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1558 {
1559         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1560         uint64_t dma_addr;
1561         unsigned i;
1562
1563         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1564                    rxq->rx_count);
1565
1566         for (i = 0; i < rxq->rx_count; i++) {
1567                 struct nfp_net_rx_desc *rxd;
1568                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1569
1570                 if (mbuf == NULL) {
1571                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1572                                 (unsigned)rxq->qidx);
1573                         return -ENOMEM;
1574                 }
1575
1576                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1577
1578                 rxd = &rxq->rxds[i];
1579                 rxd->fld.dd = 0;
1580                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1581                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1582                 rxe[i].mbuf = mbuf;
1583                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1584         }
1585
1586         /* Make sure all writes are flushed before telling the hardware */
1587         rte_wmb();
1588
1589         /* Not advertising the whole ring as the firmware gets confused if so */
1590         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1591                    rxq->rx_count - 1);
1592
1593         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1594
1595         return 0;
1596 }
1597
1598 static int
1599 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1600                        uint16_t nb_desc, unsigned int socket_id,
1601                        const struct rte_eth_txconf *tx_conf)
1602 {
1603         const struct rte_memzone *tz;
1604         struct nfp_net_txq *txq;
1605         uint16_t tx_free_thresh;
1606         struct nfp_net_hw *hw;
1607
1608         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1609
1610         PMD_INIT_FUNC_TRACE();
1611
1612         /* Validating number of descriptors */
1613         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1614             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1615             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1616                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1617                 return -EINVAL;
1618         }
1619
1620         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1621                                     tx_conf->tx_free_thresh :
1622                                     DEFAULT_TX_FREE_THRESH);
1623
1624         if (tx_free_thresh > (nb_desc)) {
1625                 PMD_DRV_LOG(ERR,
1626                         "tx_free_thresh must be less than the number of TX "
1627                         "descriptors. (tx_free_thresh=%u port=%d "
1628                         "queue=%d)", (unsigned int)tx_free_thresh,
1629                         dev->data->port_id, (int)queue_idx);
1630                 return -(EINVAL);
1631         }
1632
1633         /*
1634          * Free memory prior to re-allocation if needed. This is the case after
1635          * calling nfp_net_stop
1636          */
1637         if (dev->data->tx_queues[queue_idx]) {
1638                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1639                            queue_idx);
1640                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1641                 dev->data->tx_queues[queue_idx] = NULL;
1642         }
1643
1644         /* Allocating tx queue data structure */
1645         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1646                                  RTE_CACHE_LINE_SIZE, socket_id);
1647         if (txq == NULL) {
1648                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1649                 return -ENOMEM;
1650         }
1651
1652         /*
1653          * Allocate TX ring hardware descriptors. A memzone large enough to
1654          * handle the maximum ring size is allocated in order to allow for
1655          * resizing in later calls to the queue setup function.
1656          */
1657         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1658                                    sizeof(struct nfp_net_tx_desc) *
1659                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1660                                    socket_id);
1661         if (tz == NULL) {
1662                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1663                 nfp_net_tx_queue_release(txq);
1664                 return -ENOMEM;
1665         }
1666
1667         txq->tx_count = nb_desc;
1668         txq->tx_free_thresh = tx_free_thresh;
1669         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1670         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1671         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1672
1673         /* queue mapping based on firmware configuration */
1674         txq->qidx = queue_idx;
1675         txq->tx_qcidx = queue_idx * hw->stride_tx;
1676         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1677
1678         txq->port_id = dev->data->port_id;
1679
1680         /* Saving physical and virtual addresses for the TX ring */
1681         txq->dma = (uint64_t)tz->iova;
1682         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1683
1684         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1685         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1686                                          sizeof(*txq->txbufs) * nb_desc,
1687                                          RTE_CACHE_LINE_SIZE, socket_id);
1688         if (txq->txbufs == NULL) {
1689                 nfp_net_tx_queue_release(txq);
1690                 return -ENOMEM;
1691         }
1692         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1693                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1694
1695         nfp_net_reset_tx_queue(txq);
1696
1697         dev->data->tx_queues[queue_idx] = txq;
1698         txq->hw = hw;
1699
1700         /*
1701          * Telling the HW about the physical address of the TX ring and number
1702          * of descriptors in log2 format
1703          */
1704         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1705         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1706
1707         return 0;
1708 }
1709
1710 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1711 static inline void
1712 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1713                struct rte_mbuf *mb)
1714 {
1715         uint64_t ol_flags;
1716         struct nfp_net_hw *hw = txq->hw;
1717
1718         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1719                 goto clean_txd;
1720
1721         ol_flags = mb->ol_flags;
1722
1723         if (!(ol_flags & PKT_TX_TCP_SEG))
1724                 goto clean_txd;
1725
1726         txd->l3_offset = mb->l2_len;
1727         txd->l4_offset = mb->l2_len + mb->l3_len;
1728         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1729         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1730         txd->flags = PCIE_DESC_TX_LSO;
1731         return;
1732
1733 clean_txd:
1734         txd->flags = 0;
1735         txd->l3_offset = 0;
1736         txd->l4_offset = 0;
1737         txd->lso_hdrlen = 0;
1738         txd->mss = 0;
1739 }
1740
1741 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1742 static inline void
1743 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1744                  struct rte_mbuf *mb)
1745 {
1746         uint64_t ol_flags;
1747         struct nfp_net_hw *hw = txq->hw;
1748
1749         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1750                 return;
1751
1752         ol_flags = mb->ol_flags;
1753
1754         /* IPv6 does not need checksum */
1755         if (ol_flags & PKT_TX_IP_CKSUM)
1756                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1757
1758         switch (ol_flags & PKT_TX_L4_MASK) {
1759         case PKT_TX_UDP_CKSUM:
1760                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1761                 break;
1762         case PKT_TX_TCP_CKSUM:
1763                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1764                 break;
1765         }
1766
1767         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1768                 txd->flags |= PCIE_DESC_TX_CSUM;
1769 }
1770
1771 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1772 static inline void
1773 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1774                  struct rte_mbuf *mb)
1775 {
1776         struct nfp_net_hw *hw = rxq->hw;
1777
1778         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1779                 return;
1780
1781         /* If IPv4 and IP checksum error, fail */
1782         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1783             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1784                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1785
1786         /* If neither UDP nor TCP return */
1787         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1788             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1789                 return;
1790
1791         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1792             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1793                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1794
1795         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1796             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1797                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1798 }
1799
1800 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1801 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1802
1803 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1804
1805 /*
1806  * nfp_net_set_hash - Set mbuf hash data
1807  *
1808  * The RSS hash and hash-type are pre-pended to the packet data.
1809  * Extract and decode it and set the mbuf fields.
1810  */
1811 static inline void
1812 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1813                  struct rte_mbuf *mbuf)
1814 {
1815         struct nfp_net_hw *hw = rxq->hw;
1816         uint8_t *meta_offset;
1817         uint32_t meta_info;
1818         uint32_t hash = 0;
1819         uint32_t hash_type = 0;
1820
1821         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1822                 return;
1823
1824         /* this is true for new firmwares */
1825         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1826             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1827              NFP_DESC_META_LEN(rxd))) {
1828                 /*
1829                  * new metadata api:
1830                  * <----  32 bit  ----->
1831                  * m    field type word
1832                  * e     data field #2
1833                  * t     data field #1
1834                  * a     data field #0
1835                  * ====================
1836                  *    packet data
1837                  *
1838                  * Field type word contains up to 8 4bit field types
1839                  * A 4bit field type refers to a data field word
1840                  * A data field word can have several 4bit field types
1841                  */
1842                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1843                 meta_offset -= NFP_DESC_META_LEN(rxd);
1844                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1845                 meta_offset += 4;
1846                 /* NFP PMD just supports metadata for hashing */
1847                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1848                 case NFP_NET_META_HASH:
1849                         /* next field type is about the hash type */
1850                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1851                         /* hash value is in the data field */
1852                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1853                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1854                         break;
1855                 default:
1856                         /* Unsupported metadata can be a performance issue */
1857                         return;
1858                 }
1859         } else {
1860                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1861                         return;
1862
1863                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1864                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1865         }
1866
1867         mbuf->hash.rss = hash;
1868         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1869
1870         switch (hash_type) {
1871         case NFP_NET_RSS_IPV4:
1872                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1873                 break;
1874         case NFP_NET_RSS_IPV6:
1875                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1876                 break;
1877         case NFP_NET_RSS_IPV6_EX:
1878                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1879                 break;
1880         default:
1881                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1882         }
1883 }
1884
1885 static inline void
1886 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1887 {
1888         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1889 }
1890
1891 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1892
1893 /*
1894  * RX path design:
1895  *
1896  * There are some decissions to take:
1897  * 1) How to check DD RX descriptors bit
1898  * 2) How and when to allocate new mbufs
1899  *
1900  * Current implementation checks just one single DD bit each loop. As each
1901  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1902  * a single cache line instead. Tests with this change have not shown any
1903  * performance improvement but it requires further investigation. For example,
1904  * depending on which descriptor is next, the number of descriptors could be
1905  * less than 8 for just checking those in the same cache line. This implies
1906  * extra work which could be counterproductive by itself. Indeed, last firmware
1907  * changes are just doing this: writing several descriptors with the DD bit
1908  * for saving PCIe bandwidth and DMA operations from the NFP.
1909  *
1910  * Mbuf allocation is done when a new packet is received. Then the descriptor
1911  * is automatically linked with the new mbuf and the old one is given to the
1912  * user. The main drawback with this design is mbuf allocation is heavier than
1913  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1914  * cache point of view it does not seem allocating the mbuf early on as we are
1915  * doing now have any benefit at all. Again, tests with this change have not
1916  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1917  * so looking at the implications of this type of allocation should be studied
1918  * deeply
1919  */
1920
1921 static uint16_t
1922 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1923 {
1924         struct nfp_net_rxq *rxq;
1925         struct nfp_net_rx_desc *rxds;
1926         struct nfp_net_rx_buff *rxb;
1927         struct nfp_net_hw *hw;
1928         struct rte_mbuf *mb;
1929         struct rte_mbuf *new_mb;
1930         uint16_t nb_hold;
1931         uint64_t dma_addr;
1932         int avail;
1933
1934         rxq = rx_queue;
1935         if (unlikely(rxq == NULL)) {
1936                 /*
1937                  * DPDK just checks the queue is lower than max queues
1938                  * enabled. But the queue needs to be configured
1939                  */
1940                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1941                 return -EINVAL;
1942         }
1943
1944         hw = rxq->hw;
1945         avail = 0;
1946         nb_hold = 0;
1947
1948         while (avail < nb_pkts) {
1949                 rxb = &rxq->rxbufs[rxq->rd_p];
1950                 if (unlikely(rxb == NULL)) {
1951                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1952                         break;
1953                 }
1954
1955                 rxds = &rxq->rxds[rxq->rd_p];
1956                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1957                         break;
1958
1959                 /*
1960                  * Memory barrier to ensure that we won't do other
1961                  * reads before the DD bit.
1962                  */
1963                 rte_rmb();
1964
1965                 /*
1966                  * We got a packet. Let's alloc a new mbuff for refilling the
1967                  * free descriptor ring as soon as possible
1968                  */
1969                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1970                 if (unlikely(new_mb == NULL)) {
1971                         RTE_LOG_DP(DEBUG, PMD,
1972                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
1973                                 rxq->port_id, (unsigned int)rxq->qidx);
1974                         nfp_net_mbuf_alloc_failed(rxq);
1975                         break;
1976                 }
1977
1978                 nb_hold++;
1979
1980                 /*
1981                  * Grab the mbuff and refill the descriptor with the
1982                  * previously allocated mbuff
1983                  */
1984                 mb = rxb->mbuf;
1985                 rxb->mbuf = new_mb;
1986
1987                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
1988                            rxds->rxd.data_len, rxq->mbuf_size);
1989
1990                 /* Size of this segment */
1991                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1992                 /* Size of the whole packet. We just support 1 segment */
1993                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1994
1995                 if (unlikely((mb->data_len + hw->rx_offset) >
1996                              rxq->mbuf_size)) {
1997                         /*
1998                          * This should not happen and the user has the
1999                          * responsibility of avoiding it. But we have
2000                          * to give some info about the error
2001                          */
2002                         RTE_LOG_DP(ERR, PMD,
2003                                 "mbuf overflow likely due to the RX offset.\n"
2004                                 "\t\tYour mbuf size should have extra space for"
2005                                 " RX offset=%u bytes.\n"
2006                                 "\t\tCurrently you just have %u bytes available"
2007                                 " but the received packet is %u bytes long",
2008                                 hw->rx_offset,
2009                                 rxq->mbuf_size - hw->rx_offset,
2010                                 mb->data_len);
2011                         return -EINVAL;
2012                 }
2013
2014                 /* Filling the received mbuff with packet info */
2015                 if (hw->rx_offset)
2016                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2017                 else
2018                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2019                                        NFP_DESC_META_LEN(rxds);
2020
2021                 /* No scatter mode supported */
2022                 mb->nb_segs = 1;
2023                 mb->next = NULL;
2024
2025                 mb->port = rxq->port_id;
2026
2027                 /* Checking the RSS flag */
2028                 nfp_net_set_hash(rxq, rxds, mb);
2029
2030                 /* Checking the checksum flag */
2031                 nfp_net_rx_cksum(rxq, rxds, mb);
2032
2033                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2034                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2035                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2036                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2037                 }
2038
2039                 /* Adding the mbuff to the mbuff array passed by the app */
2040                 rx_pkts[avail++] = mb;
2041
2042                 /* Now resetting and updating the descriptor */
2043                 rxds->vals[0] = 0;
2044                 rxds->vals[1] = 0;
2045                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2046                 rxds->fld.dd = 0;
2047                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2048                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2049
2050                 rxq->rd_p++;
2051                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2052                         rxq->rd_p = 0;
2053         }
2054
2055         if (nb_hold == 0)
2056                 return nb_hold;
2057
2058         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2059                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2060
2061         nb_hold += rxq->nb_rx_hold;
2062
2063         /*
2064          * FL descriptors needs to be written before incrementing the
2065          * FL queue WR pointer
2066          */
2067         rte_wmb();
2068         if (nb_hold > rxq->rx_free_thresh) {
2069                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2070                            rxq->port_id, (unsigned int)rxq->qidx,
2071                            (unsigned)nb_hold, (unsigned)avail);
2072                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2073                 nb_hold = 0;
2074         }
2075         rxq->nb_rx_hold = nb_hold;
2076
2077         return avail;
2078 }
2079
2080 /*
2081  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2082  * status
2083  * @txq: TX queue to work with
2084  * Returns number of descriptors freed
2085  */
2086 int
2087 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2088 {
2089         uint32_t qcp_rd_p;
2090         int todo;
2091
2092         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2093                    " status", txq->qidx);
2094
2095         /* Work out how many packets have been sent */
2096         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2097
2098         if (qcp_rd_p == txq->rd_p) {
2099                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2100                            "packets (%u, %u)", txq->qidx,
2101                            qcp_rd_p, txq->rd_p);
2102                 return 0;
2103         }
2104
2105         if (qcp_rd_p > txq->rd_p)
2106                 todo = qcp_rd_p - txq->rd_p;
2107         else
2108                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2109
2110         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2111                    qcp_rd_p, txq->rd_p, txq->rd_p);
2112
2113         if (todo == 0)
2114                 return todo;
2115
2116         txq->rd_p += todo;
2117         if (unlikely(txq->rd_p >= txq->tx_count))
2118                 txq->rd_p -= txq->tx_count;
2119
2120         return todo;
2121 }
2122
2123 /* Leaving always free descriptors for avoiding wrapping confusion */
2124 static inline
2125 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2126 {
2127         if (txq->wr_p >= txq->rd_p)
2128                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2129         else
2130                 return txq->rd_p - txq->wr_p - 8;
2131 }
2132
2133 /*
2134  * nfp_net_txq_full - Check if the TX queue free descriptors
2135  * is below tx_free_threshold
2136  *
2137  * @txq: TX queue to check
2138  *
2139  * This function uses the host copy* of read/write pointers
2140  */
2141 static inline
2142 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2143 {
2144         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2145 }
2146
2147 static uint16_t
2148 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2149 {
2150         struct nfp_net_txq *txq;
2151         struct nfp_net_hw *hw;
2152         struct nfp_net_tx_desc *txds, txd;
2153         struct rte_mbuf *pkt;
2154         uint64_t dma_addr;
2155         int pkt_size, dma_size;
2156         uint16_t free_descs, issued_descs;
2157         struct rte_mbuf **lmbuf;
2158         int i;
2159
2160         txq = tx_queue;
2161         hw = txq->hw;
2162         txds = &txq->txds[txq->wr_p];
2163
2164         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2165                    txq->qidx, txq->wr_p, nb_pkts);
2166
2167         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2168                 nfp_net_tx_free_bufs(txq);
2169
2170         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2171         if (unlikely(free_descs == 0))
2172                 return 0;
2173
2174         pkt = *tx_pkts;
2175
2176         i = 0;
2177         issued_descs = 0;
2178         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2179                    txq->qidx, nb_pkts);
2180         /* Sending packets */
2181         while ((i < nb_pkts) && free_descs) {
2182                 /* Grabbing the mbuf linked to the current descriptor */
2183                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2184                 /* Warming the cache for releasing the mbuf later on */
2185                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2186
2187                 pkt = *(tx_pkts + i);
2188
2189                 if (unlikely((pkt->nb_segs > 1) &&
2190                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2191                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2192                         rte_panic("Multisegment packet unsupported\n");
2193                 }
2194
2195                 /* Checking if we have enough descriptors */
2196                 if (unlikely(pkt->nb_segs > free_descs))
2197                         goto xmit_end;
2198
2199                 /*
2200                  * Checksum and VLAN flags just in the first descriptor for a
2201                  * multisegment packet, but TSO info needs to be in all of them.
2202                  */
2203                 txd.data_len = pkt->pkt_len;
2204                 nfp_net_tx_tso(txq, &txd, pkt);
2205                 nfp_net_tx_cksum(txq, &txd, pkt);
2206
2207                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2208                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2209                         txd.flags |= PCIE_DESC_TX_VLAN;
2210                         txd.vlan = pkt->vlan_tci;
2211                 }
2212
2213                 /*
2214                  * mbuf data_len is the data in one segment and pkt_len data
2215                  * in the whole packet. When the packet is just one segment,
2216                  * then data_len = pkt_len
2217                  */
2218                 pkt_size = pkt->pkt_len;
2219
2220                 while (pkt) {
2221                         /* Copying TSO, VLAN and cksum info */
2222                         *txds = txd;
2223
2224                         /* Releasing mbuf used by this descriptor previously*/
2225                         if (*lmbuf)
2226                                 rte_pktmbuf_free_seg(*lmbuf);
2227
2228                         /*
2229                          * Linking mbuf with descriptor for being released
2230                          * next time descriptor is used
2231                          */
2232                         *lmbuf = pkt;
2233
2234                         dma_size = pkt->data_len;
2235                         dma_addr = rte_mbuf_data_iova(pkt);
2236                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2237                                    "%" PRIx64 "", dma_addr);
2238
2239                         /* Filling descriptors fields */
2240                         txds->dma_len = dma_size;
2241                         txds->data_len = txd.data_len;
2242                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2243                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2244                         ASSERT(free_descs > 0);
2245                         free_descs--;
2246
2247                         txq->wr_p++;
2248                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2249                                 txq->wr_p = 0;
2250
2251                         pkt_size -= dma_size;
2252
2253                         /*
2254                          * Making the EOP, packets with just one segment
2255                          * the priority
2256                          */
2257                         if (likely(!pkt_size))
2258                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2259                         else
2260                                 txds->offset_eop = 0;
2261
2262                         pkt = pkt->next;
2263                         /* Referencing next free TX descriptor */
2264                         txds = &txq->txds[txq->wr_p];
2265                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2266                         issued_descs++;
2267                 }
2268                 i++;
2269         }
2270
2271 xmit_end:
2272         /* Increment write pointers. Force memory write before we let HW know */
2273         rte_wmb();
2274         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2275
2276         return i;
2277 }
2278
2279 static int
2280 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2281 {
2282         uint32_t new_ctrl, update;
2283         struct nfp_net_hw *hw;
2284         int ret;
2285
2286         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         new_ctrl = 0;
2288
2289         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2290             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2291                 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2292                         " ETH_VLAN_EXTEND_OFFLOAD");
2293
2294         /* Enable vlan strip if it is not configured yet */
2295         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2296             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2297                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2298
2299         /* Disable vlan strip just if it is configured */
2300         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2301             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2302                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2303
2304         if (new_ctrl == 0)
2305                 return 0;
2306
2307         update = NFP_NET_CFG_UPDATE_GEN;
2308
2309         ret = nfp_net_reconfig(hw, new_ctrl, update);
2310         if (!ret)
2311                 hw->ctrl = new_ctrl;
2312
2313         return ret;
2314 }
2315
2316 static int
2317 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2318                     struct rte_eth_rss_reta_entry64 *reta_conf,
2319                     uint16_t reta_size)
2320 {
2321         uint32_t reta, mask;
2322         int i, j;
2323         int idx, shift;
2324         struct nfp_net_hw *hw =
2325                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326
2327         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2328                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2329                         "(%d) doesn't match the number hardware can supported "
2330                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2331                 return -EINVAL;
2332         }
2333
2334         /*
2335          * Update Redirection Table. There are 128 8bit-entries which can be
2336          * manage as 32 32bit-entries
2337          */
2338         for (i = 0; i < reta_size; i += 4) {
2339                 /* Handling 4 RSS entries per loop */
2340                 idx = i / RTE_RETA_GROUP_SIZE;
2341                 shift = i % RTE_RETA_GROUP_SIZE;
2342                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2343
2344                 if (!mask)
2345                         continue;
2346
2347                 reta = 0;
2348                 /* If all 4 entries were set, don't need read RETA register */
2349                 if (mask != 0xF)
2350                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2351
2352                 for (j = 0; j < 4; j++) {
2353                         if (!(mask & (0x1 << j)))
2354                                 continue;
2355                         if (mask != 0xF)
2356                                 /* Clearing the entry bits */
2357                                 reta &= ~(0xFF << (8 * j));
2358                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2359                 }
2360                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2361                               reta);
2362         }
2363         return 0;
2364 }
2365
2366 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2367 static int
2368 nfp_net_reta_update(struct rte_eth_dev *dev,
2369                     struct rte_eth_rss_reta_entry64 *reta_conf,
2370                     uint16_t reta_size)
2371 {
2372         struct nfp_net_hw *hw =
2373                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374         uint32_t update;
2375         int ret;
2376
2377         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2378                 return -EINVAL;
2379
2380         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2381         if (ret != 0)
2382                 return ret;
2383
2384         update = NFP_NET_CFG_UPDATE_RSS;
2385
2386         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2387                 return -EIO;
2388
2389         return 0;
2390 }
2391
2392  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2393 static int
2394 nfp_net_reta_query(struct rte_eth_dev *dev,
2395                    struct rte_eth_rss_reta_entry64 *reta_conf,
2396                    uint16_t reta_size)
2397 {
2398         uint8_t i, j, mask;
2399         int idx, shift;
2400         uint32_t reta;
2401         struct nfp_net_hw *hw;
2402
2403         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404
2405         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2406                 return -EINVAL;
2407
2408         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2409                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2410                         "(%d) doesn't match the number hardware can supported "
2411                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2412                 return -EINVAL;
2413         }
2414
2415         /*
2416          * Reading Redirection Table. There are 128 8bit-entries which can be
2417          * manage as 32 32bit-entries
2418          */
2419         for (i = 0; i < reta_size; i += 4) {
2420                 /* Handling 4 RSS entries per loop */
2421                 idx = i / RTE_RETA_GROUP_SIZE;
2422                 shift = i % RTE_RETA_GROUP_SIZE;
2423                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2424
2425                 if (!mask)
2426                         continue;
2427
2428                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2429                                     shift);
2430                 for (j = 0; j < 4; j++) {
2431                         if (!(mask & (0x1 << j)))
2432                                 continue;
2433                         reta_conf->reta[shift + j] =
2434                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2435                 }
2436         }
2437         return 0;
2438 }
2439
2440 static int
2441 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2442                         struct rte_eth_rss_conf *rss_conf)
2443 {
2444         struct nfp_net_hw *hw;
2445         uint64_t rss_hf;
2446         uint32_t cfg_rss_ctrl = 0;
2447         uint8_t key;
2448         int i;
2449
2450         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451
2452         /* Writing the key byte a byte */
2453         for (i = 0; i < rss_conf->rss_key_len; i++) {
2454                 memcpy(&key, &rss_conf->rss_key[i], 1);
2455                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2456         }
2457
2458         rss_hf = rss_conf->rss_hf;
2459
2460         if (rss_hf & ETH_RSS_IPV4)
2461                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2462                                 NFP_NET_CFG_RSS_IPV4_TCP |
2463                                 NFP_NET_CFG_RSS_IPV4_UDP;
2464
2465         if (rss_hf & ETH_RSS_IPV6)
2466                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2467                                 NFP_NET_CFG_RSS_IPV6_TCP |
2468                                 NFP_NET_CFG_RSS_IPV6_UDP;
2469
2470         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2471         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2472
2473         /* configuring where to apply the RSS hash */
2474         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2475
2476         /* Writing the key size */
2477         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2478
2479         return 0;
2480 }
2481
2482 static int
2483 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2484                         struct rte_eth_rss_conf *rss_conf)
2485 {
2486         uint32_t update;
2487         uint64_t rss_hf;
2488         struct nfp_net_hw *hw;
2489
2490         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491
2492         rss_hf = rss_conf->rss_hf;
2493
2494         /* Checking if RSS is enabled */
2495         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2496                 if (rss_hf != 0) { /* Enable RSS? */
2497                         PMD_DRV_LOG(ERR, "RSS unsupported");
2498                         return -EINVAL;
2499                 }
2500                 return 0; /* Nothing to do */
2501         }
2502
2503         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2504                 PMD_DRV_LOG(ERR, "hash key too long");
2505                 return -EINVAL;
2506         }
2507
2508         nfp_net_rss_hash_write(dev, rss_conf);
2509
2510         update = NFP_NET_CFG_UPDATE_RSS;
2511
2512         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2513                 return -EIO;
2514
2515         return 0;
2516 }
2517
2518 static int
2519 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2520                           struct rte_eth_rss_conf *rss_conf)
2521 {
2522         uint64_t rss_hf;
2523         uint32_t cfg_rss_ctrl;
2524         uint8_t key;
2525         int i;
2526         struct nfp_net_hw *hw;
2527
2528         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2529
2530         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2531                 return -EINVAL;
2532
2533         rss_hf = rss_conf->rss_hf;
2534         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2535
2536         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2537                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2538
2539         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2540                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2541
2542         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2543                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2544
2545         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2546                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2547
2548         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2549                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2550
2551         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2552                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2553
2554         /* Reading the key size */
2555         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2556
2557         /* Reading the key byte a byte */
2558         for (i = 0; i < rss_conf->rss_key_len; i++) {
2559                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2560                 memcpy(&rss_conf->rss_key[i], &key, 1);
2561         }
2562
2563         return 0;
2564 }
2565
2566 static int
2567 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2568 {
2569         struct rte_eth_conf *dev_conf;
2570         struct rte_eth_rss_conf rss_conf;
2571         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2572         uint16_t rx_queues = dev->data->nb_rx_queues;
2573         uint16_t queue;
2574         int i, j, ret;
2575
2576         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2577                 rx_queues);
2578
2579         nfp_reta_conf[0].mask = ~0x0;
2580         nfp_reta_conf[1].mask = ~0x0;
2581
2582         queue = 0;
2583         for (i = 0; i < 0x40; i += 8) {
2584                 for (j = i; j < (i + 8); j++) {
2585                         nfp_reta_conf[0].reta[j] = queue;
2586                         nfp_reta_conf[1].reta[j] = queue++;
2587                         queue %= rx_queues;
2588                 }
2589         }
2590         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2591         if (ret != 0)
2592                 return ret;
2593
2594         dev_conf = &dev->data->dev_conf;
2595         if (!dev_conf) {
2596                 PMD_DRV_LOG(INFO, "wrong rss conf");
2597                 return -EINVAL;
2598         }
2599         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2600
2601         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2602
2603         return ret;
2604 }
2605
2606
2607 /* Initialise and register driver with DPDK Application */
2608 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2609         .dev_configure          = nfp_net_configure,
2610         .dev_start              = nfp_net_start,
2611         .dev_stop               = nfp_net_stop,
2612         .dev_close              = nfp_net_close,
2613         .promiscuous_enable     = nfp_net_promisc_enable,
2614         .promiscuous_disable    = nfp_net_promisc_disable,
2615         .link_update            = nfp_net_link_update,
2616         .stats_get              = nfp_net_stats_get,
2617         .stats_reset            = nfp_net_stats_reset,
2618         .dev_infos_get          = nfp_net_infos_get,
2619         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2620         .mtu_set                = nfp_net_dev_mtu_set,
2621         .mac_addr_set           = nfp_set_mac_addr,
2622         .vlan_offload_set       = nfp_net_vlan_offload_set,
2623         .reta_update            = nfp_net_reta_update,
2624         .reta_query             = nfp_net_reta_query,
2625         .rss_hash_update        = nfp_net_rss_hash_update,
2626         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2627         .rx_queue_setup         = nfp_net_rx_queue_setup,
2628         .rx_queue_release       = nfp_net_rx_queue_release,
2629         .rx_queue_count         = nfp_net_rx_queue_count,
2630         .tx_queue_setup         = nfp_net_tx_queue_setup,
2631         .tx_queue_release       = nfp_net_tx_queue_release,
2632         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2633         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2634 };
2635
2636 /*
2637  * All eth_dev created got its private data, but before nfp_net_init, that
2638  * private data is referencing private data for all the PF ports. This is due
2639  * to how the vNIC bars are mapped based on first port, so all ports need info
2640  * about port 0 private data. Inside nfp_net_init the private data pointer is
2641  * changed to the right address for each port once the bars have been mapped.
2642  *
2643  * This functions helps to find out which port and therefore which offset
2644  * inside the private data array to use.
2645  */
2646 static int
2647 get_pf_port_number(char *name)
2648 {
2649         char *pf_str = name;
2650         int size = 0;
2651
2652         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2653                 pf_str++;
2654
2655         if (size == 30)
2656                 /*
2657                  * This should not happen at all and it would mean major
2658                  * implementation fault.
2659                  */
2660                 rte_panic("nfp_net: problem with pf device name\n");
2661
2662         /* Expecting _portX with X within [0,7] */
2663         pf_str += 5;
2664
2665         return (int)strtol(pf_str, NULL, 10);
2666 }
2667
2668 static int
2669 nfp_net_init(struct rte_eth_dev *eth_dev)
2670 {
2671         struct rte_pci_device *pci_dev;
2672         struct nfp_net_hw *hw, *hwport0;
2673
2674         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2675         uint32_t start_q;
2676         int stride = 4;
2677         int port = 0;
2678         int err;
2679
2680         PMD_INIT_FUNC_TRACE();
2681
2682         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2683
2684         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2685             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2686                 port = get_pf_port_number(eth_dev->data->name);
2687                 if (port < 0 || port > 7) {
2688                         PMD_DRV_LOG(ERR, "Port value is wrong");
2689                         return -ENODEV;
2690                 }
2691
2692                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2693
2694                 /* This points to port 0 private data */
2695                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2696
2697                 /* This points to the specific port private data */
2698                 hw = &hwport0[port];
2699         } else {
2700                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2701                 hwport0 = 0;
2702         }
2703
2704         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2705         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2706         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2707
2708         /* For secondary processes, the primary has done all the work */
2709         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2710                 return 0;
2711
2712         rte_eth_copy_pci_info(eth_dev, pci_dev);
2713
2714         hw->device_id = pci_dev->id.device_id;
2715         hw->vendor_id = pci_dev->id.vendor_id;
2716         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2717         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2718
2719         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2720                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2721                      pci_dev->addr.domain, pci_dev->addr.bus,
2722                      pci_dev->addr.devid, pci_dev->addr.function);
2723
2724         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2725         if (hw->ctrl_bar == NULL) {
2726                 PMD_DRV_LOG(ERR,
2727                         "hw->ctrl_bar is NULL. BAR0 not configured");
2728                 return -ENODEV;
2729         }
2730
2731         if (hw->is_pf && port == 0) {
2732                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2733                                              hw->total_ports * 32768,
2734                                              &hw->ctrl_area);
2735                 if (!hw->ctrl_bar) {
2736                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2737                         return -EIO;
2738                 }
2739
2740                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2741         }
2742
2743         if (port > 0) {
2744                 if (!hwport0->ctrl_bar)
2745                         return -ENODEV;
2746
2747                 /* address based on port0 offset */
2748                 hw->ctrl_bar = hwport0->ctrl_bar +
2749                                (port * NFP_PF_CSR_SLICE_SIZE);
2750         }
2751
2752         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2753
2754         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2755         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2756
2757         /* Work out where in the BAR the queues start. */
2758         switch (pci_dev->id.device_id) {
2759         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2760         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2761         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2762                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2763                 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2764                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2765                 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2766                 break;
2767         default:
2768                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2769                 err = -ENODEV;
2770                 goto dev_err_ctrl_map;
2771         }
2772
2773         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2774         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2775
2776         if (hw->is_pf && port == 0) {
2777                 /* configure access to tx/rx vNIC BARs */
2778                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2779                                                       NFP_PCIE_QUEUE(0),
2780                                                       NFP_QCP_QUEUE_AREA_SZ,
2781                                                       &hw->hwqueues_area);
2782
2783                 if (!hwport0->hw_queues) {
2784                         printf("nfp_rtsym_map fails for net.qc");
2785                         err = -EIO;
2786                         goto dev_err_ctrl_map;
2787                 }
2788
2789                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2790                                     hwport0->hw_queues);
2791         }
2792
2793         if (hw->is_pf) {
2794                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2795                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2796                 eth_dev->data->dev_private = hw;
2797         } else {
2798                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2799                              tx_bar_off;
2800                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2801                              rx_bar_off;
2802         }
2803
2804         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2805                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2806
2807         nfp_net_cfg_queue_setup(hw);
2808
2809         /* Get some of the read-only fields from the config BAR */
2810         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2811         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2812         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2813         hw->mtu = ETHER_MTU;
2814
2815         /* VLAN insertion is incompatible with LSOv2 */
2816         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2817                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2818
2819         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2820                 hw->rx_offset = NFP_NET_RX_OFFSET;
2821         else
2822                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2823
2824         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2825                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2826                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2827
2828         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2829                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2830                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2831                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2832                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2833                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2834                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2835                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2836                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2837                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2838                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2839                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2840                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2841                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2842                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2843
2844         hw->ctrl = 0;
2845
2846         hw->stride_rx = stride;
2847         hw->stride_tx = stride;
2848
2849         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2850                      hw->max_rx_queues, hw->max_tx_queues);
2851
2852         /* Initializing spinlock for reconfigs */
2853         rte_spinlock_init(&hw->reconfig_lock);
2854
2855         /* Allocating memory for mac addr */
2856         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2857         if (eth_dev->data->mac_addrs == NULL) {
2858                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2859                 err = -ENOMEM;
2860                 goto dev_err_queues_map;
2861         }
2862
2863         if (hw->is_pf) {
2864                 nfp_net_pf_read_mac(hwport0, port);
2865                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2866         } else {
2867                 nfp_net_vf_read_mac(hw);
2868         }
2869
2870         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2871                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2872                                    port);
2873                 /* Using random mac addresses for VFs */
2874                 eth_random_addr(&hw->mac_addr[0]);
2875                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2876         }
2877
2878         /* Copying mac address to DPDK eth_dev struct */
2879         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2880                         &eth_dev->data->mac_addrs[0]);
2881
2882         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2883                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2884
2885         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2886                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2887                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2888                      pci_dev->id.device_id,
2889                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2890                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2891
2892         /* Registering LSC interrupt handler */
2893         rte_intr_callback_register(&pci_dev->intr_handle,
2894                                    nfp_net_dev_interrupt_handler,
2895                                    (void *)eth_dev);
2896
2897         /* Telling the firmware about the LSC interrupt entry */
2898         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2899
2900         /* Recording current stats counters values */
2901         nfp_net_stats_reset(eth_dev);
2902
2903         return 0;
2904
2905 dev_err_queues_map:
2906                 nfp_cpp_area_free(hw->hwqueues_area);
2907 dev_err_ctrl_map:
2908                 nfp_cpp_area_free(hw->ctrl_area);
2909
2910         return err;
2911 }
2912
2913 static int
2914 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2915                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
2916                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
2917 {
2918         struct rte_eth_dev *eth_dev;
2919         struct nfp_net_hw *hw;
2920         char *port_name;
2921         int ret;
2922
2923         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2924         if (!port_name)
2925                 return -ENOMEM;
2926
2927         if (ports > 1)
2928                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2929         else
2930                 sprintf(port_name, "%s", dev->device.name);
2931
2932         eth_dev = rte_eth_dev_allocate(port_name);
2933         if (!eth_dev)
2934                 return -ENOMEM;
2935
2936         if (port == 0) {
2937                 *priv = rte_zmalloc(port_name,
2938                                     sizeof(struct nfp_net_adapter) * ports,
2939                                     RTE_CACHE_LINE_SIZE);
2940                 if (!*priv) {
2941                         rte_eth_dev_release_port(eth_dev);
2942                         return -ENOMEM;
2943                 }
2944         }
2945
2946         eth_dev->data->dev_private = *priv;
2947
2948         /*
2949          * dev_private pointing to port0 dev_private because we need
2950          * to configure vNIC bars based on port0 at nfp_net_init.
2951          * Then dev_private is adjusted per port.
2952          */
2953         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2954         hw->cpp = cpp;
2955         hw->hwinfo = hwinfo;
2956         hw->sym_tbl = sym_tbl;
2957         hw->pf_port_idx = phys_port;
2958         hw->is_pf = 1;
2959         if (ports > 1)
2960                 hw->pf_multiport_enabled = 1;
2961
2962         hw->total_ports = ports;
2963
2964         eth_dev->device = &dev->device;
2965         rte_eth_copy_pci_info(eth_dev, dev);
2966
2967         ret = nfp_net_init(eth_dev);
2968
2969         if (ret)
2970                 rte_eth_dev_release_port(eth_dev);
2971         else
2972                 rte_eth_dev_probing_finish(eth_dev);
2973
2974         rte_free(port_name);
2975
2976         return ret;
2977 }
2978
2979 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
2980
2981 static int
2982 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
2983 {
2984         struct nfp_cpp *cpp = nsp->cpp;
2985         int fw_f;
2986         char *fw_buf;
2987         char fw_name[125];
2988         char serial[40];
2989         struct stat file_stat;
2990         off_t fsize, bytes;
2991
2992         /* Looking for firmware file in order of priority */
2993
2994         /* First try to find a firmware image specific for this device */
2995         sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
2996                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
2997                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
2998                 cpp->interface & 0xff);
2999
3000         sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3001
3002         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3003         fw_f = open(fw_name, O_RDONLY);
3004         if (fw_f > 0)
3005                 goto read_fw;
3006
3007         /* Then try the PCI name */
3008         sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3009
3010         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3011         fw_f = open(fw_name, O_RDONLY);
3012         if (fw_f > 0)
3013                 goto read_fw;
3014
3015         /* Finally try the card type and media */
3016         sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3017         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3018         fw_f = open(fw_name, O_RDONLY);
3019         if (fw_f < 0) {
3020                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3021                 return -ENOENT;
3022         }
3023
3024 read_fw:
3025         if (fstat(fw_f, &file_stat) < 0) {
3026                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3027                 close(fw_f);
3028                 return -ENOENT;
3029         }
3030
3031         fsize = file_stat.st_size;
3032         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3033                             fw_name, (uint64_t)fsize);
3034
3035         fw_buf = malloc((size_t)fsize);
3036         if (!fw_buf) {
3037                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3038                 close(fw_f);
3039                 return -ENOMEM;
3040         }
3041         memset(fw_buf, 0, fsize);
3042
3043         bytes = read(fw_f, fw_buf, fsize);
3044         if (bytes != fsize) {
3045                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3046                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3047                                    (uint64_t)bytes, (uint64_t)fsize);
3048                 free(fw_buf);
3049                 close(fw_f);
3050                 return -EIO;
3051         }
3052
3053         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3054         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3055         PMD_DRV_LOG(INFO, "Done");
3056
3057         free(fw_buf);
3058         close(fw_f);
3059
3060         return 0;
3061 }
3062
3063 static int
3064 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3065              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3066 {
3067         struct nfp_nsp *nsp;
3068         const char *nfp_fw_model;
3069         char card_desc[100];
3070         int err = 0;
3071
3072         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3073
3074         if (nfp_fw_model) {
3075                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3076         } else {
3077                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3078                 return -EIO;
3079         }
3080
3081         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3082                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3083                        nfp_eth_table->count);
3084                 return -EIO;
3085         }
3086
3087         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3088                            nfp_eth_table->count);
3089
3090         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3091
3092         sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3093                 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3094
3095         nsp = nfp_nsp_open(cpp);
3096         if (!nsp) {
3097                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3098                 return -EIO;
3099         }
3100
3101         nfp_nsp_device_soft_reset(nsp);
3102         err = nfp_fw_upload(dev, nsp, card_desc);
3103
3104         nfp_nsp_close(nsp);
3105         return err;
3106 }
3107
3108 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3109                             struct rte_pci_device *dev)
3110 {
3111         struct nfp_cpp *cpp;
3112         struct nfp_hwinfo *hwinfo;
3113         struct nfp_rtsym_table *sym_tbl;
3114         struct nfp_eth_table *nfp_eth_table = NULL;
3115         int total_ports;
3116         void *priv = 0;
3117         int ret = -ENODEV;
3118         int err;
3119         int i;
3120
3121         if (!dev)
3122                 return ret;
3123
3124         /*
3125          * When device bound to UIO, the device could be used, by mistake,
3126          * by two DPDK apps, and the UIO driver does not avoid it. This
3127          * could lead to a serious problem when configuring the NFP CPP
3128          * interface. Here we avoid this telling to the CPP init code to
3129          * use a lock file if UIO is being used.
3130          */
3131         if (dev->kdrv == RTE_KDRV_VFIO)
3132                 cpp = nfp_cpp_from_device_name(dev, 0);
3133         else
3134                 cpp = nfp_cpp_from_device_name(dev, 1);
3135
3136         if (!cpp) {
3137                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3138                 ret = -EIO;
3139                 goto error;
3140         }
3141
3142         hwinfo = nfp_hwinfo_read(cpp);
3143         if (!hwinfo) {
3144                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3145                 return -EIO;
3146         }
3147
3148         nfp_eth_table = nfp_eth_read_ports(cpp);
3149         if (!nfp_eth_table) {
3150                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3151                 return -EIO;
3152         }
3153
3154         if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3155                 PMD_DRV_LOG(INFO, "Error when uploading firmware");
3156                 ret = -EIO;
3157                 goto error;
3158         }
3159
3160         /* Now the symbol table should be there */
3161         sym_tbl = nfp_rtsym_table_read(cpp);
3162         if (!sym_tbl) {
3163                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3164                                 " symbol table");
3165                 ret = -EIO;
3166                 goto error;
3167         }
3168
3169         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3170         if (total_ports != (int)nfp_eth_table->count) {
3171                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3172                 ret = -EIO;
3173                 goto error;
3174         }
3175         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3176
3177         if (total_ports <= 0 || total_ports > 8) {
3178                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3179                 ret = -ENODEV;
3180                 goto error;
3181         }
3182
3183         for (i = 0; i < total_ports; i++) {
3184                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3185                                         nfp_eth_table->ports[i].index,
3186                                         sym_tbl, &priv);
3187                 if (ret)
3188                         break;
3189         }
3190
3191 error:
3192         free(nfp_eth_table);
3193         return ret;
3194 }
3195
3196 int nfp_logtype_init;
3197 int nfp_logtype_driver;
3198
3199 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3200         {
3201                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3202                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3203         },
3204         {
3205                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3206                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3207         },
3208         {
3209                 .vendor_id = 0,
3210         },
3211 };
3212
3213 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3214         {
3215                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3216                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3217         },
3218         {
3219                 .vendor_id = 0,
3220         },
3221 };
3222
3223 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3224         struct rte_pci_device *pci_dev)
3225 {
3226         return rte_eth_dev_pci_generic_probe(pci_dev,
3227                 sizeof(struct nfp_net_adapter), nfp_net_init);
3228 }
3229
3230 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3231 {
3232         struct rte_eth_dev *eth_dev;
3233         struct nfp_net_hw *hw, *hwport0;
3234         int port = 0;
3235
3236         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3237         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3238             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3239                 port = get_pf_port_number(eth_dev->data->name);
3240                 /*
3241                  * hotplug is not possible with multiport PF although freeing
3242                  * data structures can be done for first port.
3243                  */
3244                 if (port != 0)
3245                         return -ENOTSUP;
3246                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3247                 hw = &hwport0[port];
3248                 nfp_cpp_area_free(hw->ctrl_area);
3249                 nfp_cpp_area_free(hw->hwqueues_area);
3250                 free(hw->hwinfo);
3251                 free(hw->sym_tbl);
3252                 nfp_cpp_free(hw->cpp);
3253         } else {
3254                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3255         }
3256         /* hotplug is not possible with multiport PF */
3257         if (hw->pf_multiport_enabled)
3258                 return -ENOTSUP;
3259         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3260 }
3261
3262 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3263         .id_table = pci_id_nfp_pf_net_map,
3264         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3265         .probe = nfp_pf_pci_probe,
3266         .remove = eth_nfp_pci_remove,
3267 };
3268
3269 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3270         .id_table = pci_id_nfp_vf_net_map,
3271         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3272         .probe = eth_nfp_pci_probe,
3273         .remove = eth_nfp_pci_remove,
3274 };
3275
3276 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3277 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3278 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3279 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3280 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3281 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3282
3283 RTE_INIT(nfp_init_log)
3284 {
3285         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3286         if (nfp_logtype_init >= 0)
3287                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3288         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3289         if (nfp_logtype_driver >= 0)
3290                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3291 }
3292 /*
3293  * Local variables:
3294  * c-file-style: "Linux"
3295  * indent-tabs-mode: t
3296  * End:
3297  */