drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57 #include <rte_service_component.h>
  58
  59 #include "nfpcore/nfp_cpp.h"
  60 #include "nfpcore/nfp_nffw.h"
  61 #include "nfpcore/nfp_hwinfo.h"
  62 #include "nfpcore/nfp_mip.h"
  63 #include "nfpcore/nfp_rtsym.h"
  64 #include "nfpcore/nfp_nsp.h"
  65
  66 #include "nfp_net_pmd.h"
  67 #include "nfp_net_logs.h"
  68 #include "nfp_net_ctrl.h"
  69
  70 #include <sys/types.h>
  71 #include <sys/socket.h>
  72 #include <sys/un.h>
  73 #include <unistd.h>
  74 #include <stdio.h>
  75 #include <sys/ioctl.h>
  76 #include <errno.h>
  77
  78 /* Prototypes */
  79 static void nfp_net_close(struct rte_eth_dev *dev);
  80 static int nfp_net_configure(struct rte_eth_dev *dev);
  81 static void nfp_net_dev_interrupt_handler(void *param);
  82 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  83 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  84 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  85                               struct rte_eth_dev_info *dev_info);
  86 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  87 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  88 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  89 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  90 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  91 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  92                                        uint16_t queue_idx);
  93 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  94                                   uint16_t nb_pkts);
  95 static void nfp_net_rx_queue_release(void *rxq);
  96 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  97                                   uint16_t nb_desc, unsigned int socket_id,
  98                                   const struct rte_eth_rxconf *rx_conf,
  99                                   struct rte_mempool *mp);
 100 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
 101 static void nfp_net_tx_queue_release(void *txq);
 102 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 103                                   uint16_t nb_desc, unsigned int socket_id,
 104                                   const struct rte_eth_txconf *tx_conf);
 105 static int nfp_net_start(struct rte_eth_dev *dev);
 106 static int nfp_net_stats_get(struct rte_eth_dev *dev,
 107                               struct rte_eth_stats *stats);
 108 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
 109 static void nfp_net_stop(struct rte_eth_dev *dev);
 110 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 111                                   uint16_t nb_pkts);
 112
 113 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
 114 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 115                                    struct rte_eth_rss_conf *rss_conf);
 116 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 117                     struct rte_eth_rss_reta_entry64 *reta_conf,
 118                     uint16_t reta_size);
 119 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 120                         struct rte_eth_rss_conf *rss_conf);
 121 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
 122                              struct ether_addr *mac_addr);
 123
 124 /* The offset of the queue controller queues in the PCIe Target */
 125 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 126
 127 /* Maximum value which can be added to a queue with one transaction */
 128 #define NFP_QCP_MAX_ADD 0x7f
 129
 130 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 131         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 132
 133 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 134 enum nfp_qcp_ptr {
 135         NFP_QCP_READ_PTR = 0,
 136         NFP_QCP_WRITE_PTR
 137 };
 138
 139 /*
 140  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 141  * @q: Base address for queue structure
 142  * @ptr: Add to the Read or Write pointer
 143  * @val: Value to add to the queue pointer
 144  *
 145  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 146  */
 147 static inline void
 148 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 149 {
 150         uint32_t off;
 151
 152         if (ptr == NFP_QCP_READ_PTR)
 153                 off = NFP_QCP_QUEUE_ADD_RPTR;
 154         else
 155                 off = NFP_QCP_QUEUE_ADD_WPTR;
 156
 157         while (val > NFP_QCP_MAX_ADD) {
 158                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 159                 val -= NFP_QCP_MAX_ADD;
 160         }
 161
 162         nn_writel(rte_cpu_to_le_32(val), q + off);
 163 }
 164
 165 /*
 166  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 167  * @q:  Base address for queue structure
 168  * @ptr: Read or Write pointer
 169  */
 170 static inline uint32_t
 171 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 172 {
 173         uint32_t off;
 174         uint32_t val;
 175
 176         if (ptr == NFP_QCP_READ_PTR)
 177                 off = NFP_QCP_QUEUE_STS_LO;
 178         else
 179                 off = NFP_QCP_QUEUE_STS_HI;
 180
 181         val = rte_cpu_to_le_32(nn_readl(q + off));
 182
 183         if (ptr == NFP_QCP_READ_PTR)
 184                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 185         else
 186                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 187 }
 188
 189 /*
 190  * Functions to read/write from/to Config BAR
 191  * Performs any endian conversion necessary.
 192  */
 193 static inline uint8_t
 194 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 195 {
 196         return nn_readb(hw->ctrl_bar + off);
 197 }
 198
 199 static inline void
 200 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 201 {
 202         nn_writeb(val, hw->ctrl_bar + off);
 203 }
 204
 205 static inline uint32_t
 206 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 207 {
 208         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 209 }
 210
 211 static inline void
 212 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 213 {
 214         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 215 }
 216
 217 static inline uint64_t
 218 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 219 {
 220         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 221 }
 222
 223 static inline void
 224 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 225 {
 226         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 227 }
 228
 229 static void
 230 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 231 {
 232         unsigned i;
 233
 234         if (rxq->rxbufs == NULL)
 235                 return;
 236
 237         for (i = 0; i < rxq->rx_count; i++) {
 238                 if (rxq->rxbufs[i].mbuf) {
 239                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 240                         rxq->rxbufs[i].mbuf = NULL;
 241                 }
 242         }
 243 }
 244
 245 static void
 246 nfp_net_rx_queue_release(void *rx_queue)
 247 {
 248         struct nfp_net_rxq *rxq = rx_queue;
 249
 250         if (rxq) {
 251                 nfp_net_rx_queue_release_mbufs(rxq);
 252                 rte_free(rxq->rxbufs);
 253                 rte_free(rxq);
 254         }
 255 }
 256
 257 static void
 258 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 259 {
 260         nfp_net_rx_queue_release_mbufs(rxq);
 261         rxq->rd_p = 0;
 262         rxq->nb_rx_hold = 0;
 263 }
 264
 265 static void
 266 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 267 {
 268         unsigned i;
 269
 270         if (txq->txbufs == NULL)
 271                 return;
 272
 273         for (i = 0; i < txq->tx_count; i++) {
 274                 if (txq->txbufs[i].mbuf) {
 275                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 276                         txq->txbufs[i].mbuf = NULL;
 277                 }
 278         }
 279 }
 280
 281 static void
 282 nfp_net_tx_queue_release(void *tx_queue)
 283 {
 284         struct nfp_net_txq *txq = tx_queue;
 285
 286         if (txq) {
 287                 nfp_net_tx_queue_release_mbufs(txq);
 288                 rte_free(txq->txbufs);
 289                 rte_free(txq);
 290         }
 291 }
 292
 293 static void
 294 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 295 {
 296         nfp_net_tx_queue_release_mbufs(txq);
 297         txq->wr_p = 0;
 298         txq->rd_p = 0;
 299 }
 300
 301 static int
 302 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 303 {
 304         int cnt;
 305         uint32_t new;
 306         struct timespec wait;
 307
 308         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 309                     hw->qcp_cfg);
 310
 311         if (hw->qcp_cfg == NULL)
 312                 rte_panic("Bad configuration queue pointer\n");
 313
 314         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 315
 316         wait.tv_sec = 0;
 317         wait.tv_nsec = 1000000;
 318
 319         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 320
 321         /* Poll update field, waiting for NFP to ack the config */
 322         for (cnt = 0; ; cnt++) {
 323                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 324                 if (new == 0)
 325                         break;
 326                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 327                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 328                         return -1;
 329                 }
 330                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 331                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 332                                           " %dms", update, cnt);
 333                         rte_panic("Exiting\n");
 334                 }
 335                 nanosleep(&wait, 0); /* waiting for a 1ms */
 336         }
 337         PMD_DRV_LOG(DEBUG, "Ack DONE");
 338         return 0;
 339 }
 340
 341 /*
 342  * Reconfigure the NIC
 343  * @nn:    device to reconfigure
 344  * @ctrl:    The value for the ctrl field in the BAR config
 345  * @update:  The value for the update field in the BAR config
 346  *
 347  * Write the update word to the BAR and ping the reconfig queue. Then poll
 348  * until the firmware has acknowledged the update by zeroing the update word.
 349  */
 350 static int
 351 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 352 {
 353         uint32_t err;
 354
 355         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 356                     ctrl, update);
 357
 358         rte_spinlock_lock(&hw->reconfig_lock);
 359
 360         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 361         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 362
 363         rte_wmb();
 364
 365         err = __nfp_net_reconfig(hw, update);
 366
 367         rte_spinlock_unlock(&hw->reconfig_lock);
 368
 369         if (!err)
 370                 return 0;
 371
 372         /*
 373          * Reconfig errors imply situations where they can be handled.
 374          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 375          */
 376         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 377                      ctrl, update);
 378         return -EIO;
 379 }
 380
 381 /*
 382  * Configure an Ethernet device. This function must be invoked first
 383  * before any other function in the Ethernet API. This function can
 384  * also be re-invoked when a device is in the stopped state.
 385  */
 386 static int
 387 nfp_net_configure(struct rte_eth_dev *dev)
 388 {
 389         struct rte_eth_conf *dev_conf;
 390         struct rte_eth_rxmode *rxmode;
 391         struct rte_eth_txmode *txmode;
 392         struct nfp_net_hw *hw;
 393
 394         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 395
 396         /*
 397          * A DPDK app sends info about how many queues to use and how
 398          * those queues need to be configured. This is used by the
 399          * DPDK core and it makes sure no more queues than those
 400          * advertised by the driver are requested. This function is
 401          * called after that internal process
 402          */
 403
 404         PMD_INIT_LOG(DEBUG, "Configure");
 405
 406         dev_conf = &dev->data->dev_conf;
 407         rxmode = &dev_conf->rxmode;
 408         txmode = &dev_conf->txmode;
 409
 410         /* Checking TX mode */
 411         if (txmode->mq_mode) {
 412                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 413                 return -EINVAL;
 414         }
 415
 416         /* Checking RX mode */
 417         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 418             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 419                 PMD_INIT_LOG(INFO, "RSS not supported");
 420                 return -EINVAL;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static void
 427 nfp_net_enable_queues(struct rte_eth_dev *dev)
 428 {
 429         struct nfp_net_hw *hw;
 430         uint64_t enabled_queues = 0;
 431         int i;
 432
 433         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434
 435         /* Enabling the required TX queues in the device */
 436         for (i = 0; i < dev->data->nb_tx_queues; i++)
 437                 enabled_queues |= (1 << i);
 438
 439         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 440
 441         enabled_queues = 0;
 442
 443         /* Enabling the required RX queues in the device */
 444         for (i = 0; i < dev->data->nb_rx_queues; i++)
 445                 enabled_queues |= (1 << i);
 446
 447         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 448 }
 449
 450 static void
 451 nfp_net_disable_queues(struct rte_eth_dev *dev)
 452 {
 453         struct nfp_net_hw *hw;
 454         uint32_t new_ctrl, update = 0;
 455
 456         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 457
 458         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 459         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 460
 461         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 462         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 463                  NFP_NET_CFG_UPDATE_MSIX;
 464
 465         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 466                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 467
 468         /* If an error when reconfig we avoid to change hw state */
 469         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 470                 return;
 471
 472         hw->ctrl = new_ctrl;
 473 }
 474
 475 static int
 476 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 477 {
 478         int i;
 479
 480         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 481                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 482                         return -1;
 483         }
 484         return 0;
 485 }
 486
 487 static void
 488 nfp_net_params_setup(struct nfp_net_hw *hw)
 489 {
 490         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 491         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 492 }
 493
 494 static void
 495 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 496 {
 497         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 498 }
 499
 500 #define ETH_ADDR_LEN    6
 501
 502 static void
 503 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 504 {
 505         int i;
 506
 507         for (i = 0; i < ETH_ADDR_LEN; i++)
 508                 dst[i] = src[i];
 509 }
 510
 511 static int
 512 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 513 {
 514         struct nfp_eth_table *nfp_eth_table;
 515
 516         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 517         /*
 518          * hw points to port0 private data. We need hw now pointing to
 519          * right port.
 520          */
 521         hw += port;
 522         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 523                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 524
 525         free(nfp_eth_table);
 526         return 0;
 527 }
 528
 529 static void
 530 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 531 {
 532         uint32_t tmp;
 533
 534         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 535         memcpy(&hw->mac_addr[0], &tmp, 4);
 536
 537         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 538         memcpy(&hw->mac_addr[4], &tmp, 2);
 539 }
 540
 541 static void
 542 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 543 {
 544         uint32_t mac0 = *(uint32_t *)mac;
 545         uint16_t mac1;
 546
 547         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 548
 549         mac += 4;
 550         mac1 = *(uint16_t *)mac;
 551         nn_writew(rte_cpu_to_be_16(mac1),
 552                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 553 }
 554
 555 int
 556 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 557 {
 558         struct nfp_net_hw *hw;
 559         uint32_t update, ctrl;
 560
 561         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 562         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 563             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 564                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 565                                   " port enabled");
 566                 return -EBUSY;
 567         }
 568
 569         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 570             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 571                 return -EBUSY;
 572
 573         /* Writing new MAC to the specific port BAR address */
 574         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 575
 576         /* Signal the NIC about the change */
 577         update = NFP_NET_CFG_UPDATE_MACADDR;
 578         ctrl = hw->ctrl;
 579         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 580             (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 581                 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
 582         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 583                 PMD_INIT_LOG(INFO, "MAC address update failed");
 584                 return -EIO;
 585         }
 586         return 0;
 587 }
 588
 589 static int
 590 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 591                            struct rte_intr_handle *intr_handle)
 592 {
 593         struct nfp_net_hw *hw;
 594         int i;
 595
 596         if (!intr_handle->intr_vec) {
 597                 intr_handle->intr_vec =
 598                         rte_zmalloc("intr_vec",
 599                                     dev->data->nb_rx_queues * sizeof(int), 0);
 600                 if (!intr_handle->intr_vec) {
 601                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 602                                      " intr_vec", dev->data->nb_rx_queues);
 603                         return -ENOMEM;
 604                 }
 605         }
 606
 607         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 608
 609         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 610                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 611                 /* UIO just supports one queue and no LSC*/
 612                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 613                 intr_handle->intr_vec[0] = 0;
 614         } else {
 615                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 616                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 617                         /*
 618                          * The first msix vector is reserved for non
 619                          * efd interrupts
 620                         */
 621                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 622                         intr_handle->intr_vec[i] = i + 1;
 623                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 624                                             intr_handle->intr_vec[i]);
 625                 }
 626         }
 627
 628         /* Avoiding TX interrupts */
 629         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 630         return 0;
 631 }
 632
 633 static uint32_t
 634 nfp_check_offloads(struct rte_eth_dev *dev)
 635 {
 636         struct nfp_net_hw *hw;
 637         struct rte_eth_conf *dev_conf;
 638         struct rte_eth_rxmode *rxmode;
 639         struct rte_eth_txmode *txmode;
 640         uint32_t ctrl = 0;
 641
 642         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 643
 644         dev_conf = &dev->data->dev_conf;
 645         rxmode = &dev_conf->rxmode;
 646         txmode = &dev_conf->txmode;
 647
 648         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 649                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 650                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 651         }
 652
 653         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 654                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 655                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 656         }
 657
 658         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 659                 hw->mtu = rxmode->max_rx_pkt_len;
 660
 661         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 662                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 663
 664         /* L2 broadcast */
 665         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 666                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 667
 668         /* L2 multicast */
 669         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 670                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 671
 672         /* TX checksum offload */
 673         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 674             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 675             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 676                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 677
 678         /* LSO offload */
 679         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 680                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 681                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 682                 else
 683                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 684         }
 685
 686         /* RX gather */
 687         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 688                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 689
 690         return ctrl;
 691 }
 692
 693 static int
 694 nfp_net_start(struct rte_eth_dev *dev)
 695 {
 696         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 697         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 698         uint32_t new_ctrl, update = 0;
 699         struct nfp_net_hw *hw;
 700         struct rte_eth_conf *dev_conf;
 701         struct rte_eth_rxmode *rxmode;
 702         uint32_t intr_vector;
 703         int ret;
 704
 705         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 706
 707         PMD_INIT_LOG(DEBUG, "Start");
 708
 709         /* Disabling queues just in case... */
 710         nfp_net_disable_queues(dev);
 711
 712         /* Enabling the required queues in the device */
 713         nfp_net_enable_queues(dev);
 714
 715         /* check and configure queue intr-vector mapping */
 716         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 717                 if (hw->pf_multiport_enabled) {
 718                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 719                                           "with NFP multiport PF");
 720                                 return -EINVAL;
 721                 }
 722                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 723                         /*
 724                          * Better not to share LSC with RX interrupts.
 725                          * Unregistering LSC interrupt handler
 726                          */
 727                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 728                                 nfp_net_dev_interrupt_handler, (void *)dev);
 729
 730                         if (dev->data->nb_rx_queues > 1) {
 731                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 732                                              "supports 1 queue with UIO");
 733                                 return -EIO;
 734                         }
 735                 }
 736                 intr_vector = dev->data->nb_rx_queues;
 737                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 738                         return -1;
 739
 740                 nfp_configure_rx_interrupt(dev, intr_handle);
 741                 update = NFP_NET_CFG_UPDATE_MSIX;
 742         }
 743
 744         rte_intr_enable(intr_handle);
 745
 746         new_ctrl = nfp_check_offloads(dev);
 747
 748         /* Writing configuration parameters in the device */
 749         nfp_net_params_setup(hw);
 750
 751         dev_conf = &dev->data->dev_conf;
 752         rxmode = &dev_conf->rxmode;
 753
 754         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 755                 nfp_net_rss_config_default(dev);
 756                 update |= NFP_NET_CFG_UPDATE_RSS;
 757                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 758         }
 759
 760         /* Enable device */
 761         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 762
 763         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 764
 765         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 766                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 767
 768         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 769         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 770                 return -EIO;
 771
 772         /*
 773          * Allocating rte mbuffs for configured rx queues.
 774          * This requires queues being enabled before
 775          */
 776         if (nfp_net_rx_freelist_setup(dev) < 0) {
 777                 ret = -ENOMEM;
 778                 goto error;
 779         }
 780
 781         if (hw->is_pf) {
 782                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 783                         /* Configure the physical port up */
 784                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 785                 else
 786                         nfp_eth_set_configured(dev->process_private,
 787                                                hw->pf_port_idx, 1);
 788         }
 789
 790         hw->ctrl = new_ctrl;
 791
 792         return 0;
 793
 794 error:
 795         /*
 796          * An error returned by this function should mean the app
 797          * exiting and then the system releasing all the memory
 798          * allocated even memory coming from hugepages.
 799          *
 800          * The device could be enabled at this point with some queues
 801          * ready for getting packets. This is true if the call to
 802          * nfp_net_rx_freelist_setup() succeeds for some queues but
 803          * fails for subsequent queues.
 804          *
 805          * This should make the app exiting but better if we tell the
 806          * device first.
 807          */
 808         nfp_net_disable_queues(dev);
 809
 810         return ret;
 811 }
 812
 813 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 814 static void
 815 nfp_net_stop(struct rte_eth_dev *dev)
 816 {
 817         int i;
 818         struct nfp_net_hw *hw;
 819
 820         PMD_INIT_LOG(DEBUG, "Stop");
 821
 822         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 823
 824         nfp_net_disable_queues(dev);
 825
 826         /* Clear queues */
 827         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 828                 nfp_net_reset_tx_queue(
 829                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 830         }
 831
 832         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 833                 nfp_net_reset_rx_queue(
 834                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 835         }
 836
 837         if (hw->is_pf) {
 838                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 839                         /* Configure the physical port down */
 840                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 841                 else
 842                         nfp_eth_set_configured(dev->process_private,
 843                                                hw->pf_port_idx, 0);
 844         }
 845 }
 846
 847 /* Reset and stop device. The device can not be restarted. */
 848 static void
 849 nfp_net_close(struct rte_eth_dev *dev)
 850 {
 851         struct nfp_net_hw *hw;
 852         struct rte_pci_device *pci_dev;
 853         int i;
 854
 855         PMD_INIT_LOG(DEBUG, "Close");
 856
 857         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 858         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 859
 860         /*
 861          * We assume that the DPDK application is stopping all the
 862          * threads/queues before calling the device close function.
 863          */
 864
 865         nfp_net_disable_queues(dev);
 866
 867         /* Clear queues */
 868         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 869                 nfp_net_reset_tx_queue(
 870                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 871         }
 872
 873         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 874                 nfp_net_reset_rx_queue(
 875                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 876         }
 877
 878         rte_intr_disable(&pci_dev->intr_handle);
 879         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 880
 881         /* unregister callback func from eal lib */
 882         rte_intr_callback_unregister(&pci_dev->intr_handle,
 883                                      nfp_net_dev_interrupt_handler,
 884                                      (void *)dev);
 885
 886         /*
 887          * The ixgbe PMD driver disables the pcie master on the
 888          * device. The i40e does not...
 889          */
 890 }
 891
 892 static void
 893 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 894 {
 895         uint32_t new_ctrl, update = 0;
 896         struct nfp_net_hw *hw;
 897
 898         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 899
 900         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 901
 902         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 903                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 904                 return;
 905         }
 906
 907         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 908                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 909                 return;
 910         }
 911
 912         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 913         update = NFP_NET_CFG_UPDATE_GEN;
 914
 915         /*
 916          * DPDK sets promiscuous mode on just after this call assuming
 917          * it can not fail ...
 918          */
 919         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 920                 return;
 921
 922         hw->ctrl = new_ctrl;
 923 }
 924
 925 static void
 926 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 927 {
 928         uint32_t new_ctrl, update = 0;
 929         struct nfp_net_hw *hw;
 930
 931         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 932
 933         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 934                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 935                 return;
 936         }
 937
 938         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 939         update = NFP_NET_CFG_UPDATE_GEN;
 940
 941         /*
 942          * DPDK sets promiscuous mode off just before this call
 943          * assuming it can not fail ...
 944          */
 945         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 946                 return;
 947
 948         hw->ctrl = new_ctrl;
 949 }
 950
 951 /*
 952  * return 0 means link status changed, -1 means not changed
 953  *
 954  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 955  * status.
 956  */
 957 static int
 958 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 959 {
 960         struct nfp_net_hw *hw;
 961         struct rte_eth_link link;
 962         uint32_t nn_link_status;
 963         int ret;
 964
 965         static const uint32_t ls_to_ethtool[] = {
 966                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 967                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 968                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 969                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 970                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 971                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 972                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 973                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 974         };
 975
 976         PMD_DRV_LOG(DEBUG, "Link update");
 977
 978         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 979
 980         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 981
 982         memset(&link, 0, sizeof(struct rte_eth_link));
 983
 984         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 985                 link.link_status = ETH_LINK_UP;
 986
 987         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 988
 989         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 990                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 991
 992         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 993                 link.link_speed = ETH_SPEED_NUM_NONE;
 994         else
 995                 link.link_speed = ls_to_ethtool[nn_link_status];
 996
 997         ret = rte_eth_linkstatus_set(dev, &link);
 998         if (ret == 0) {
 999                 if (link.link_status)
1000                         PMD_DRV_LOG(INFO, "NIC Link is Up");
1001                 else
1002                         PMD_DRV_LOG(INFO, "NIC Link is Down");
1003         }
1004         return ret;
1005 }
1006
1007 static int
1008 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1009 {
1010         int i;
1011         struct nfp_net_hw *hw;
1012         struct rte_eth_stats nfp_dev_stats;
1013
1014         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1015
1016         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1017
1018         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1019
1020         /* reading per RX ring stats */
1021         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1022                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1023                         break;
1024
1025                 nfp_dev_stats.q_ipackets[i] =
1026                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1027
1028                 nfp_dev_stats.q_ipackets[i] -=
1029                         hw->eth_stats_base.q_ipackets[i];
1030
1031                 nfp_dev_stats.q_ibytes[i] =
1032                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1033
1034                 nfp_dev_stats.q_ibytes[i] -=
1035                         hw->eth_stats_base.q_ibytes[i];
1036         }
1037
1038         /* reading per TX ring stats */
1039         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1040                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1041                         break;
1042
1043                 nfp_dev_stats.q_opackets[i] =
1044                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1045
1046                 nfp_dev_stats.q_opackets[i] -=
1047                         hw->eth_stats_base.q_opackets[i];
1048
1049                 nfp_dev_stats.q_obytes[i] =
1050                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1051
1052                 nfp_dev_stats.q_obytes[i] -=
1053                         hw->eth_stats_base.q_obytes[i];
1054         }
1055
1056         nfp_dev_stats.ipackets =
1057                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1058
1059         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1060
1061         nfp_dev_stats.ibytes =
1062                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1063
1064         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1065
1066         nfp_dev_stats.opackets =
1067                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1068
1069         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1070
1071         nfp_dev_stats.obytes =
1072                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1073
1074         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1075
1076         /* reading general device stats */
1077         nfp_dev_stats.ierrors =
1078                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1079
1080         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1081
1082         nfp_dev_stats.oerrors =
1083                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1084
1085         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1086
1087         /* RX ring mbuf allocation failures */
1088         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1089
1090         nfp_dev_stats.imissed =
1091                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1092
1093         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1094
1095         if (stats) {
1096                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1097                 return 0;
1098         }
1099         return -EINVAL;
1100 }
1101
1102 static void
1103 nfp_net_stats_reset(struct rte_eth_dev *dev)
1104 {
1105         int i;
1106         struct nfp_net_hw *hw;
1107
1108         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1109
1110         /*
1111          * hw->eth_stats_base records the per counter starting point.
1112          * Lets update it now
1113          */
1114
1115         /* reading per RX ring stats */
1116         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1117                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1118                         break;
1119
1120                 hw->eth_stats_base.q_ipackets[i] =
1121                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1122
1123                 hw->eth_stats_base.q_ibytes[i] =
1124                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1125         }
1126
1127         /* reading per TX ring stats */
1128         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1129                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1130                         break;
1131
1132                 hw->eth_stats_base.q_opackets[i] =
1133                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1134
1135                 hw->eth_stats_base.q_obytes[i] =
1136                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1137         }
1138
1139         hw->eth_stats_base.ipackets =
1140                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1141
1142         hw->eth_stats_base.ibytes =
1143                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1144
1145         hw->eth_stats_base.opackets =
1146                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1147
1148         hw->eth_stats_base.obytes =
1149                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1150
1151         /* reading general device stats */
1152         hw->eth_stats_base.ierrors =
1153                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1154
1155         hw->eth_stats_base.oerrors =
1156                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1157
1158         /* RX ring mbuf allocation failures */
1159         dev->data->rx_mbuf_alloc_failed = 0;
1160
1161         hw->eth_stats_base.imissed =
1162                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1163 }
1164
1165 static void
1166 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1167 {
1168         struct nfp_net_hw *hw;
1169
1170         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1171
1172         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1173         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1174         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1175         dev_info->max_rx_pktlen = hw->max_mtu;
1176         /* Next should change when PF support is implemented */
1177         dev_info->max_mac_addrs = 1;
1178
1179         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1180                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1181
1182         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1183                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1184                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1185                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1186
1187         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1188
1189         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1190                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1191
1192         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1193                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1194                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1195                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1196
1197         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1198                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1199
1200         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1201                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1202
1203         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1204                 .rx_thresh = {
1205                         .pthresh = DEFAULT_RX_PTHRESH,
1206                         .hthresh = DEFAULT_RX_HTHRESH,
1207                         .wthresh = DEFAULT_RX_WTHRESH,
1208                 },
1209                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1210                 .rx_drop_en = 0,
1211         };
1212
1213         dev_info->default_txconf = (struct rte_eth_txconf) {
1214                 .tx_thresh = {
1215                         .pthresh = DEFAULT_TX_PTHRESH,
1216                         .hthresh = DEFAULT_TX_HTHRESH,
1217                         .wthresh = DEFAULT_TX_WTHRESH,
1218                 },
1219                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1220                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1221         };
1222
1223         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1224                                            ETH_RSS_NONFRAG_IPV4_TCP |
1225                                            ETH_RSS_NONFRAG_IPV4_UDP |
1226                                            ETH_RSS_IPV6 |
1227                                            ETH_RSS_NONFRAG_IPV6_TCP |
1228                                            ETH_RSS_NONFRAG_IPV6_UDP;
1229
1230         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1231         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1232
1233         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1234                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1235                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1236 }
1237
1238 static const uint32_t *
1239 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1240 {
1241         static const uint32_t ptypes[] = {
1242                 /* refers to nfp_net_set_hash() */
1243                 RTE_PTYPE_INNER_L3_IPV4,
1244                 RTE_PTYPE_INNER_L3_IPV6,
1245                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1246                 RTE_PTYPE_INNER_L4_MASK,
1247                 RTE_PTYPE_UNKNOWN
1248         };
1249
1250         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1251                 return ptypes;
1252         return NULL;
1253 }
1254
1255 static uint32_t
1256 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1257 {
1258         struct nfp_net_rxq *rxq;
1259         struct nfp_net_rx_desc *rxds;
1260         uint32_t idx;
1261         uint32_t count;
1262
1263         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1264
1265         idx = rxq->rd_p;
1266
1267         count = 0;
1268
1269         /*
1270          * Other PMDs are just checking the DD bit in intervals of 4
1271          * descriptors and counting all four if the first has the DD
1272          * bit on. Of course, this is not accurate but can be good for
1273          * performance. But ideally that should be done in descriptors
1274          * chunks belonging to the same cache line
1275          */
1276
1277         while (count < rxq->rx_count) {
1278                 rxds = &rxq->rxds[idx];
1279                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1280                         break;
1281
1282                 count++;
1283                 idx++;
1284
1285                 /* Wrapping? */
1286                 if ((idx) == rxq->rx_count)
1287                         idx = 0;
1288         }
1289
1290         return count;
1291 }
1292
1293 static int
1294 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1295 {
1296         struct rte_pci_device *pci_dev;
1297         struct nfp_net_hw *hw;
1298         int base = 0;
1299
1300         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1302
1303         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1304                 base = 1;
1305
1306         /* Make sure all updates are written before un-masking */
1307         rte_wmb();
1308         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1309                       NFP_NET_CFG_ICR_UNMASKED);
1310         return 0;
1311 }
1312
1313 static int
1314 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1315 {
1316         struct rte_pci_device *pci_dev;
1317         struct nfp_net_hw *hw;
1318         int base = 0;
1319
1320         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1322
1323         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1324                 base = 1;
1325
1326         /* Make sure all updates are written before un-masking */
1327         rte_wmb();
1328         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1329         return 0;
1330 }
1331
1332 static void
1333 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1334 {
1335         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1336         struct rte_eth_link link;
1337
1338         rte_eth_linkstatus_get(dev, &link);
1339         if (link.link_status)
1340                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1341                             dev->data->port_id, link.link_speed,
1342                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1343                             ? "full-duplex" : "half-duplex");
1344         else
1345                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1346                             dev->data->port_id);
1347
1348         PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1349                 pci_dev->addr.domain, pci_dev->addr.bus,
1350                 pci_dev->addr.devid, pci_dev->addr.function);
1351 }
1352
1353 /* Interrupt configuration and handling */
1354
1355 /*
1356  * nfp_net_irq_unmask - Unmask an interrupt
1357  *
1358  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1359  * clear the ICR for the entry.
1360  */
1361 static void
1362 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1363 {
1364         struct nfp_net_hw *hw;
1365         struct rte_pci_device *pci_dev;
1366
1367         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1369
1370         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1371                 /* If MSI-X auto-masking is used, clear the entry */
1372                 rte_wmb();
1373                 rte_intr_enable(&pci_dev->intr_handle);
1374         } else {
1375                 /* Make sure all updates are written before un-masking */
1376                 rte_wmb();
1377                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1378                               NFP_NET_CFG_ICR_UNMASKED);
1379         }
1380 }
1381
1382 static void
1383 nfp_net_dev_interrupt_handler(void *param)
1384 {
1385         int64_t timeout;
1386         struct rte_eth_link link;
1387         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1388
1389         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1390
1391         rte_eth_linkstatus_get(dev, &link);
1392
1393         nfp_net_link_update(dev, 0);
1394
1395         /* likely to up */
1396         if (!link.link_status) {
1397                 /* handle it 1 sec later, wait it being stable */
1398                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1399                 /* likely to down */
1400         } else {
1401                 /* handle it 4 sec later, wait it being stable */
1402                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1403         }
1404
1405         if (rte_eal_alarm_set(timeout * 1000,
1406                               nfp_net_dev_interrupt_delayed_handler,
1407                               (void *)dev) < 0) {
1408                 PMD_INIT_LOG(ERR, "Error setting alarm");
1409                 /* Unmasking */
1410                 nfp_net_irq_unmask(dev);
1411         }
1412 }
1413
1414 /*
1415  * Interrupt handler which shall be registered for alarm callback for delayed
1416  * handling specific interrupt to wait for the stable nic state. As the NIC
1417  * interrupt state is not stable for nfp after link is just down, it needs
1418  * to wait 4 seconds to get the stable status.
1419  *
1420  * @param handle   Pointer to interrupt handle.
1421  * @param param    The address of parameter (struct rte_eth_dev *)
1422  *
1423  * @return  void
1424  */
1425 static void
1426 nfp_net_dev_interrupt_delayed_handler(void *param)
1427 {
1428         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1429
1430         nfp_net_link_update(dev, 0);
1431         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1432
1433         nfp_net_dev_link_status_print(dev);
1434
1435         /* Unmasking */
1436         nfp_net_irq_unmask(dev);
1437 }
1438
1439 static int
1440 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1441 {
1442         struct nfp_net_hw *hw;
1443
1444         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445
1446         /* check that mtu is within the allowed range */
1447         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1448                 return -EINVAL;
1449
1450         /* mtu setting is forbidden if port is started */
1451         if (dev->data->dev_started) {
1452                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1453                             dev->data->port_id);
1454                 return -EBUSY;
1455         }
1456
1457         /* switch to jumbo mode if needed */
1458         if ((uint32_t)mtu > ETHER_MAX_LEN)
1459                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1460         else
1461                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1462
1463         /* update max frame size */
1464         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1465
1466         /* writing to configuration space */
1467         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1468
1469         hw->mtu = mtu;
1470
1471         return 0;
1472 }
1473
1474 static int
1475 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1476                        uint16_t queue_idx, uint16_t nb_desc,
1477                        unsigned int socket_id,
1478                        const struct rte_eth_rxconf *rx_conf,
1479                        struct rte_mempool *mp)
1480 {
1481         const struct rte_memzone *tz;
1482         struct nfp_net_rxq *rxq;
1483         struct nfp_net_hw *hw;
1484
1485         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486
1487         PMD_INIT_FUNC_TRACE();
1488
1489         /* Validating number of descriptors */
1490         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1491             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1492             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1493                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1494                 return -EINVAL;
1495         }
1496
1497         /*
1498          * Free memory prior to re-allocation if needed. This is the case after
1499          * calling nfp_net_stop
1500          */
1501         if (dev->data->rx_queues[queue_idx]) {
1502                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1503                 dev->data->rx_queues[queue_idx] = NULL;
1504         }
1505
1506         /* Allocating rx queue data structure */
1507         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1508                                  RTE_CACHE_LINE_SIZE, socket_id);
1509         if (rxq == NULL)
1510                 return -ENOMEM;
1511
1512         /* Hw queues mapping based on firmware confifguration */
1513         rxq->qidx = queue_idx;
1514         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1515         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1516         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1517         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1518
1519         /*
1520          * Tracking mbuf size for detecting a potential mbuf overflow due to
1521          * RX offset
1522          */
1523         rxq->mem_pool = mp;
1524         rxq->mbuf_size = rxq->mem_pool->elt_size;
1525         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1526         hw->flbufsz = rxq->mbuf_size;
1527
1528         rxq->rx_count = nb_desc;
1529         rxq->port_id = dev->data->port_id;
1530         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1531         rxq->drop_en = rx_conf->rx_drop_en;
1532
1533         /*
1534          * Allocate RX ring hardware descriptors. A memzone large enough to
1535          * handle the maximum ring size is allocated in order to allow for
1536          * resizing in later calls to the queue setup function.
1537          */
1538         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1539                                    sizeof(struct nfp_net_rx_desc) *
1540                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1541                                    socket_id);
1542
1543         if (tz == NULL) {
1544                 PMD_DRV_LOG(ERR, "Error allocatig rx dma");
1545                 nfp_net_rx_queue_release(rxq);
1546                 return -ENOMEM;
1547         }
1548
1549         /* Saving physical and virtual addresses for the RX ring */
1550         rxq->dma = (uint64_t)tz->iova;
1551         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1552
1553         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1554         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1555                                          sizeof(*rxq->rxbufs) * nb_desc,
1556                                          RTE_CACHE_LINE_SIZE, socket_id);
1557         if (rxq->rxbufs == NULL) {
1558                 nfp_net_rx_queue_release(rxq);
1559                 return -ENOMEM;
1560         }
1561
1562         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1563                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1564
1565         nfp_net_reset_rx_queue(rxq);
1566
1567         dev->data->rx_queues[queue_idx] = rxq;
1568         rxq->hw = hw;
1569
1570         /*
1571          * Telling the HW about the physical address of the RX ring and number
1572          * of descriptors in log2 format
1573          */
1574         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1575         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1576
1577         return 0;
1578 }
1579
1580 static int
1581 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1582 {
1583         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1584         uint64_t dma_addr;
1585         unsigned i;
1586
1587         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1588                    rxq->rx_count);
1589
1590         for (i = 0; i < rxq->rx_count; i++) {
1591                 struct nfp_net_rx_desc *rxd;
1592                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1593
1594                 if (mbuf == NULL) {
1595                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1596                                 (unsigned)rxq->qidx);
1597                         return -ENOMEM;
1598                 }
1599
1600                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1601
1602                 rxd = &rxq->rxds[i];
1603                 rxd->fld.dd = 0;
1604                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1605                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1606                 rxe[i].mbuf = mbuf;
1607                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1608         }
1609
1610         /* Make sure all writes are flushed before telling the hardware */
1611         rte_wmb();
1612
1613         /* Not advertising the whole ring as the firmware gets confused if so */
1614         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1615                    rxq->rx_count - 1);
1616
1617         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1618
1619         return 0;
1620 }
1621
1622 static int
1623 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1624                        uint16_t nb_desc, unsigned int socket_id,
1625                        const struct rte_eth_txconf *tx_conf)
1626 {
1627         const struct rte_memzone *tz;
1628         struct nfp_net_txq *txq;
1629         uint16_t tx_free_thresh;
1630         struct nfp_net_hw *hw;
1631
1632         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633
1634         PMD_INIT_FUNC_TRACE();
1635
1636         /* Validating number of descriptors */
1637         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1638             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1639             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1640                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1641                 return -EINVAL;
1642         }
1643
1644         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1645                                     tx_conf->tx_free_thresh :
1646                                     DEFAULT_TX_FREE_THRESH);
1647
1648         if (tx_free_thresh > (nb_desc)) {
1649                 PMD_DRV_LOG(ERR,
1650                         "tx_free_thresh must be less than the number of TX "
1651                         "descriptors. (tx_free_thresh=%u port=%d "
1652                         "queue=%d)", (unsigned int)tx_free_thresh,
1653                         dev->data->port_id, (int)queue_idx);
1654                 return -(EINVAL);
1655         }
1656
1657         /*
1658          * Free memory prior to re-allocation if needed. This is the case after
1659          * calling nfp_net_stop
1660          */
1661         if (dev->data->tx_queues[queue_idx]) {
1662                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1663                            queue_idx);
1664                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1665                 dev->data->tx_queues[queue_idx] = NULL;
1666         }
1667
1668         /* Allocating tx queue data structure */
1669         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1670                                  RTE_CACHE_LINE_SIZE, socket_id);
1671         if (txq == NULL) {
1672                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1673                 return -ENOMEM;
1674         }
1675
1676         /*
1677          * Allocate TX ring hardware descriptors. A memzone large enough to
1678          * handle the maximum ring size is allocated in order to allow for
1679          * resizing in later calls to the queue setup function.
1680          */
1681         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1682                                    sizeof(struct nfp_net_tx_desc) *
1683                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1684                                    socket_id);
1685         if (tz == NULL) {
1686                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1687                 nfp_net_tx_queue_release(txq);
1688                 return -ENOMEM;
1689         }
1690
1691         txq->tx_count = nb_desc;
1692         txq->tx_free_thresh = tx_free_thresh;
1693         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1694         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1695         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1696
1697         /* queue mapping based on firmware configuration */
1698         txq->qidx = queue_idx;
1699         txq->tx_qcidx = queue_idx * hw->stride_tx;
1700         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1701
1702         txq->port_id = dev->data->port_id;
1703
1704         /* Saving physical and virtual addresses for the TX ring */
1705         txq->dma = (uint64_t)tz->iova;
1706         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1707
1708         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1709         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1710                                          sizeof(*txq->txbufs) * nb_desc,
1711                                          RTE_CACHE_LINE_SIZE, socket_id);
1712         if (txq->txbufs == NULL) {
1713                 nfp_net_tx_queue_release(txq);
1714                 return -ENOMEM;
1715         }
1716         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1717                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1718
1719         nfp_net_reset_tx_queue(txq);
1720
1721         dev->data->tx_queues[queue_idx] = txq;
1722         txq->hw = hw;
1723
1724         /*
1725          * Telling the HW about the physical address of the TX ring and number
1726          * of descriptors in log2 format
1727          */
1728         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1729         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1730
1731         return 0;
1732 }
1733
1734 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1735 static inline void
1736 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1737                struct rte_mbuf *mb)
1738 {
1739         uint64_t ol_flags;
1740         struct nfp_net_hw *hw = txq->hw;
1741
1742         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1743                 goto clean_txd;
1744
1745         ol_flags = mb->ol_flags;
1746
1747         if (!(ol_flags & PKT_TX_TCP_SEG))
1748                 goto clean_txd;
1749
1750         txd->l3_offset = mb->l2_len;
1751         txd->l4_offset = mb->l2_len + mb->l3_len;
1752         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1753         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1754         txd->flags = PCIE_DESC_TX_LSO;
1755         return;
1756
1757 clean_txd:
1758         txd->flags = 0;
1759         txd->l3_offset = 0;
1760         txd->l4_offset = 0;
1761         txd->lso_hdrlen = 0;
1762         txd->mss = 0;
1763 }
1764
1765 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1766 static inline void
1767 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1768                  struct rte_mbuf *mb)
1769 {
1770         uint64_t ol_flags;
1771         struct nfp_net_hw *hw = txq->hw;
1772
1773         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1774                 return;
1775
1776         ol_flags = mb->ol_flags;
1777
1778         /* IPv6 does not need checksum */
1779         if (ol_flags & PKT_TX_IP_CKSUM)
1780                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1781
1782         switch (ol_flags & PKT_TX_L4_MASK) {
1783         case PKT_TX_UDP_CKSUM:
1784                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1785                 break;
1786         case PKT_TX_TCP_CKSUM:
1787                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1788                 break;
1789         }
1790
1791         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1792                 txd->flags |= PCIE_DESC_TX_CSUM;
1793 }
1794
1795 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1796 static inline void
1797 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1798                  struct rte_mbuf *mb)
1799 {
1800         struct nfp_net_hw *hw = rxq->hw;
1801
1802         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1803                 return;
1804
1805         /* If IPv4 and IP checksum error, fail */
1806         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1807             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1808                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1809         else
1810                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1811
1812         /* If neither UDP nor TCP return */
1813         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1814             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1815                 return;
1816
1817         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1818                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1819         else
1820                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1821 }
1822
1823 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1824 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1825
1826 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1827
1828 /*
1829  * nfp_net_set_hash - Set mbuf hash data
1830  *
1831  * The RSS hash and hash-type are pre-pended to the packet data.
1832  * Extract and decode it and set the mbuf fields.
1833  */
1834 static inline void
1835 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1836                  struct rte_mbuf *mbuf)
1837 {
1838         struct nfp_net_hw *hw = rxq->hw;
1839         uint8_t *meta_offset;
1840         uint32_t meta_info;
1841         uint32_t hash = 0;
1842         uint32_t hash_type = 0;
1843
1844         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1845                 return;
1846
1847         /* this is true for new firmwares */
1848         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1849             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1850              NFP_DESC_META_LEN(rxd))) {
1851                 /*
1852                  * new metadata api:
1853                  * <----  32 bit  ----->
1854                  * m    field type word
1855                  * e     data field #2
1856                  * t     data field #1
1857                  * a     data field #0
1858                  * ====================
1859                  *    packet data
1860                  *
1861                  * Field type word contains up to 8 4bit field types
1862                  * A 4bit field type refers to a data field word
1863                  * A data field word can have several 4bit field types
1864                  */
1865                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1866                 meta_offset -= NFP_DESC_META_LEN(rxd);
1867                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1868                 meta_offset += 4;
1869                 /* NFP PMD just supports metadata for hashing */
1870                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1871                 case NFP_NET_META_HASH:
1872                         /* next field type is about the hash type */
1873                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1874                         /* hash value is in the data field */
1875                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1876                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1877                         break;
1878                 default:
1879                         /* Unsupported metadata can be a performance issue */
1880                         return;
1881                 }
1882         } else {
1883                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1884                         return;
1885
1886                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1887                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1888         }
1889
1890         mbuf->hash.rss = hash;
1891         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1892
1893         switch (hash_type) {
1894         case NFP_NET_RSS_IPV4:
1895                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1896                 break;
1897         case NFP_NET_RSS_IPV6:
1898                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1899                 break;
1900         case NFP_NET_RSS_IPV6_EX:
1901                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1902                 break;
1903         case NFP_NET_RSS_IPV4_TCP:
1904                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1905                 break;
1906         case NFP_NET_RSS_IPV6_TCP:
1907                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1908                 break;
1909         case NFP_NET_RSS_IPV4_UDP:
1910                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1911                 break;
1912         case NFP_NET_RSS_IPV6_UDP:
1913                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1914                 break;
1915         default:
1916                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1917         }
1918 }
1919
1920 static inline void
1921 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1922 {
1923         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1924 }
1925
1926 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1927
1928 /*
1929  * RX path design:
1930  *
1931  * There are some decissions to take:
1932  * 1) How to check DD RX descriptors bit
1933  * 2) How and when to allocate new mbufs
1934  *
1935  * Current implementation checks just one single DD bit each loop. As each
1936  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1937  * a single cache line instead. Tests with this change have not shown any
1938  * performance improvement but it requires further investigation. For example,
1939  * depending on which descriptor is next, the number of descriptors could be
1940  * less than 8 for just checking those in the same cache line. This implies
1941  * extra work which could be counterproductive by itself. Indeed, last firmware
1942  * changes are just doing this: writing several descriptors with the DD bit
1943  * for saving PCIe bandwidth and DMA operations from the NFP.
1944  *
1945  * Mbuf allocation is done when a new packet is received. Then the descriptor
1946  * is automatically linked with the new mbuf and the old one is given to the
1947  * user. The main drawback with this design is mbuf allocation is heavier than
1948  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1949  * cache point of view it does not seem allocating the mbuf early on as we are
1950  * doing now have any benefit at all. Again, tests with this change have not
1951  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1952  * so looking at the implications of this type of allocation should be studied
1953  * deeply
1954  */
1955
1956 static uint16_t
1957 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1958 {
1959         struct nfp_net_rxq *rxq;
1960         struct nfp_net_rx_desc *rxds;
1961         struct nfp_net_rx_buff *rxb;
1962         struct nfp_net_hw *hw;
1963         struct rte_mbuf *mb;
1964         struct rte_mbuf *new_mb;
1965         uint16_t nb_hold;
1966         uint64_t dma_addr;
1967         int avail;
1968
1969         rxq = rx_queue;
1970         if (unlikely(rxq == NULL)) {
1971                 /*
1972                  * DPDK just checks the queue is lower than max queues
1973                  * enabled. But the queue needs to be configured
1974                  */
1975                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1976                 return -EINVAL;
1977         }
1978
1979         hw = rxq->hw;
1980         avail = 0;
1981         nb_hold = 0;
1982
1983         while (avail < nb_pkts) {
1984                 rxb = &rxq->rxbufs[rxq->rd_p];
1985                 if (unlikely(rxb == NULL)) {
1986                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1987                         break;
1988                 }
1989
1990                 rxds = &rxq->rxds[rxq->rd_p];
1991                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1992                         break;
1993
1994                 /*
1995                  * Memory barrier to ensure that we won't do other
1996                  * reads before the DD bit.
1997                  */
1998                 rte_rmb();
1999
2000                 /*
2001                  * We got a packet. Let's alloc a new mbuff for refilling the
2002                  * free descriptor ring as soon as possible
2003                  */
2004                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2005                 if (unlikely(new_mb == NULL)) {
2006                         RTE_LOG_DP(DEBUG, PMD,
2007                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2008                                 rxq->port_id, (unsigned int)rxq->qidx);
2009                         nfp_net_mbuf_alloc_failed(rxq);
2010                         break;
2011                 }
2012
2013                 nb_hold++;
2014
2015                 /*
2016                  * Grab the mbuff and refill the descriptor with the
2017                  * previously allocated mbuff
2018                  */
2019                 mb = rxb->mbuf;
2020                 rxb->mbuf = new_mb;
2021
2022                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2023                            rxds->rxd.data_len, rxq->mbuf_size);
2024
2025                 /* Size of this segment */
2026                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2027                 /* Size of the whole packet. We just support 1 segment */
2028                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2029
2030                 if (unlikely((mb->data_len + hw->rx_offset) >
2031                              rxq->mbuf_size)) {
2032                         /*
2033                          * This should not happen and the user has the
2034                          * responsibility of avoiding it. But we have
2035                          * to give some info about the error
2036                          */
2037                         RTE_LOG_DP(ERR, PMD,
2038                                 "mbuf overflow likely due to the RX offset.\n"
2039                                 "\t\tYour mbuf size should have extra space for"
2040                                 " RX offset=%u bytes.\n"
2041                                 "\t\tCurrently you just have %u bytes available"
2042                                 " but the received packet is %u bytes long",
2043                                 hw->rx_offset,
2044                                 rxq->mbuf_size - hw->rx_offset,
2045                                 mb->data_len);
2046                         return -EINVAL;
2047                 }
2048
2049                 /* Filling the received mbuff with packet info */
2050                 if (hw->rx_offset)
2051                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2052                 else
2053                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2054                                        NFP_DESC_META_LEN(rxds);
2055
2056                 /* No scatter mode supported */
2057                 mb->nb_segs = 1;
2058                 mb->next = NULL;
2059
2060                 mb->port = rxq->port_id;
2061
2062                 /* Checking the RSS flag */
2063                 nfp_net_set_hash(rxq, rxds, mb);
2064
2065                 /* Checking the checksum flag */
2066                 nfp_net_rx_cksum(rxq, rxds, mb);
2067
2068                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2069                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2070                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2071                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2072                 }
2073
2074                 /* Adding the mbuff to the mbuff array passed by the app */
2075                 rx_pkts[avail++] = mb;
2076
2077                 /* Now resetting and updating the descriptor */
2078                 rxds->vals[0] = 0;
2079                 rxds->vals[1] = 0;
2080                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2081                 rxds->fld.dd = 0;
2082                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2083                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2084
2085                 rxq->rd_p++;
2086                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2087                         rxq->rd_p = 0;
2088         }
2089
2090         if (nb_hold == 0)
2091                 return nb_hold;
2092
2093         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2094                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2095
2096         nb_hold += rxq->nb_rx_hold;
2097
2098         /*
2099          * FL descriptors needs to be written before incrementing the
2100          * FL queue WR pointer
2101          */
2102         rte_wmb();
2103         if (nb_hold > rxq->rx_free_thresh) {
2104                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2105                            rxq->port_id, (unsigned int)rxq->qidx,
2106                            (unsigned)nb_hold, (unsigned)avail);
2107                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2108                 nb_hold = 0;
2109         }
2110         rxq->nb_rx_hold = nb_hold;
2111
2112         return avail;
2113 }
2114
2115 /*
2116  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2117  * status
2118  * @txq: TX queue to work with
2119  * Returns number of descriptors freed
2120  */
2121 int
2122 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2123 {
2124         uint32_t qcp_rd_p;
2125         int todo;
2126
2127         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2128                    " status", txq->qidx);
2129
2130         /* Work out how many packets have been sent */
2131         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2132
2133         if (qcp_rd_p == txq->rd_p) {
2134                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2135                            "packets (%u, %u)", txq->qidx,
2136                            qcp_rd_p, txq->rd_p);
2137                 return 0;
2138         }
2139
2140         if (qcp_rd_p > txq->rd_p)
2141                 todo = qcp_rd_p - txq->rd_p;
2142         else
2143                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2144
2145         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2146                    qcp_rd_p, txq->rd_p, txq->rd_p);
2147
2148         if (todo == 0)
2149                 return todo;
2150
2151         txq->rd_p += todo;
2152         if (unlikely(txq->rd_p >= txq->tx_count))
2153                 txq->rd_p -= txq->tx_count;
2154
2155         return todo;
2156 }
2157
2158 /* Leaving always free descriptors for avoiding wrapping confusion */
2159 static inline
2160 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2161 {
2162         if (txq->wr_p >= txq->rd_p)
2163                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2164         else
2165                 return txq->rd_p - txq->wr_p - 8;
2166 }
2167
2168 /*
2169  * nfp_net_txq_full - Check if the TX queue free descriptors
2170  * is below tx_free_threshold
2171  *
2172  * @txq: TX queue to check
2173  *
2174  * This function uses the host copy* of read/write pointers
2175  */
2176 static inline
2177 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2178 {
2179         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2180 }
2181
2182 static uint16_t
2183 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2184 {
2185         struct nfp_net_txq *txq;
2186         struct nfp_net_hw *hw;
2187         struct nfp_net_tx_desc *txds, txd;
2188         struct rte_mbuf *pkt;
2189         uint64_t dma_addr;
2190         int pkt_size, dma_size;
2191         uint16_t free_descs, issued_descs;
2192         struct rte_mbuf **lmbuf;
2193         int i;
2194
2195         txq = tx_queue;
2196         hw = txq->hw;
2197         txds = &txq->txds[txq->wr_p];
2198
2199         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2200                    txq->qidx, txq->wr_p, nb_pkts);
2201
2202         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2203                 nfp_net_tx_free_bufs(txq);
2204
2205         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2206         if (unlikely(free_descs == 0))
2207                 return 0;
2208
2209         pkt = *tx_pkts;
2210
2211         i = 0;
2212         issued_descs = 0;
2213         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2214                    txq->qidx, nb_pkts);
2215         /* Sending packets */
2216         while ((i < nb_pkts) && free_descs) {
2217                 /* Grabbing the mbuf linked to the current descriptor */
2218                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2219                 /* Warming the cache for releasing the mbuf later on */
2220                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2221
2222                 pkt = *(tx_pkts + i);
2223
2224                 if (unlikely((pkt->nb_segs > 1) &&
2225                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2226                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2227                         rte_panic("Multisegment packet unsupported\n");
2228                 }
2229
2230                 /* Checking if we have enough descriptors */
2231                 if (unlikely(pkt->nb_segs > free_descs))
2232                         goto xmit_end;
2233
2234                 /*
2235                  * Checksum and VLAN flags just in the first descriptor for a
2236                  * multisegment packet, but TSO info needs to be in all of them.
2237                  */
2238                 txd.data_len = pkt->pkt_len;
2239                 nfp_net_tx_tso(txq, &txd, pkt);
2240                 nfp_net_tx_cksum(txq, &txd, pkt);
2241
2242                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2243                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2244                         txd.flags |= PCIE_DESC_TX_VLAN;
2245                         txd.vlan = pkt->vlan_tci;
2246                 }
2247
2248                 /*
2249                  * mbuf data_len is the data in one segment and pkt_len data
2250                  * in the whole packet. When the packet is just one segment,
2251                  * then data_len = pkt_len
2252                  */
2253                 pkt_size = pkt->pkt_len;
2254
2255                 while (pkt) {
2256                         /* Copying TSO, VLAN and cksum info */
2257                         *txds = txd;
2258
2259                         /* Releasing mbuf used by this descriptor previously*/
2260                         if (*lmbuf)
2261                                 rte_pktmbuf_free_seg(*lmbuf);
2262
2263                         /*
2264                          * Linking mbuf with descriptor for being released
2265                          * next time descriptor is used
2266                          */
2267                         *lmbuf = pkt;
2268
2269                         dma_size = pkt->data_len;
2270                         dma_addr = rte_mbuf_data_iova(pkt);
2271                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2272                                    "%" PRIx64 "", dma_addr);
2273
2274                         /* Filling descriptors fields */
2275                         txds->dma_len = dma_size;
2276                         txds->data_len = txd.data_len;
2277                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2278                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2279                         ASSERT(free_descs > 0);
2280                         free_descs--;
2281
2282                         txq->wr_p++;
2283                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2284                                 txq->wr_p = 0;
2285
2286                         pkt_size -= dma_size;
2287
2288                         /*
2289                          * Making the EOP, packets with just one segment
2290                          * the priority
2291                          */
2292                         if (likely(!pkt_size))
2293                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2294                         else
2295                                 txds->offset_eop = 0;
2296
2297                         pkt = pkt->next;
2298                         /* Referencing next free TX descriptor */
2299                         txds = &txq->txds[txq->wr_p];
2300                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2301                         issued_descs++;
2302                 }
2303                 i++;
2304         }
2305
2306 xmit_end:
2307         /* Increment write pointers. Force memory write before we let HW know */
2308         rte_wmb();
2309         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2310
2311         return i;
2312 }
2313
2314 static int
2315 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2316 {
2317         uint32_t new_ctrl, update;
2318         struct nfp_net_hw *hw;
2319         int ret;
2320
2321         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322         new_ctrl = 0;
2323
2324         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2325             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2326                 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2327                         " ETH_VLAN_EXTEND_OFFLOAD");
2328
2329         /* Enable vlan strip if it is not configured yet */
2330         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2331             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2332                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2333
2334         /* Disable vlan strip just if it is configured */
2335         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2336             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2337                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2338
2339         if (new_ctrl == 0)
2340                 return 0;
2341
2342         update = NFP_NET_CFG_UPDATE_GEN;
2343
2344         ret = nfp_net_reconfig(hw, new_ctrl, update);
2345         if (!ret)
2346                 hw->ctrl = new_ctrl;
2347
2348         return ret;
2349 }
2350
2351 static int
2352 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2353                     struct rte_eth_rss_reta_entry64 *reta_conf,
2354                     uint16_t reta_size)
2355 {
2356         uint32_t reta, mask;
2357         int i, j;
2358         int idx, shift;
2359         struct nfp_net_hw *hw =
2360                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361
2362         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2363                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2364                         "(%d) doesn't match the number hardware can supported "
2365                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2366                 return -EINVAL;
2367         }
2368
2369         /*
2370          * Update Redirection Table. There are 128 8bit-entries which can be
2371          * manage as 32 32bit-entries
2372          */
2373         for (i = 0; i < reta_size; i += 4) {
2374                 /* Handling 4 RSS entries per loop */
2375                 idx = i / RTE_RETA_GROUP_SIZE;
2376                 shift = i % RTE_RETA_GROUP_SIZE;
2377                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2378
2379                 if (!mask)
2380                         continue;
2381
2382                 reta = 0;
2383                 /* If all 4 entries were set, don't need read RETA register */
2384                 if (mask != 0xF)
2385                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2386
2387                 for (j = 0; j < 4; j++) {
2388                         if (!(mask & (0x1 << j)))
2389                                 continue;
2390                         if (mask != 0xF)
2391                                 /* Clearing the entry bits */
2392                                 reta &= ~(0xFF << (8 * j));
2393                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2394                 }
2395                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2396                               reta);
2397         }
2398         return 0;
2399 }
2400
2401 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2402 static int
2403 nfp_net_reta_update(struct rte_eth_dev *dev,
2404                     struct rte_eth_rss_reta_entry64 *reta_conf,
2405                     uint16_t reta_size)
2406 {
2407         struct nfp_net_hw *hw =
2408                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409         uint32_t update;
2410         int ret;
2411
2412         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2413                 return -EINVAL;
2414
2415         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2416         if (ret != 0)
2417                 return ret;
2418
2419         update = NFP_NET_CFG_UPDATE_RSS;
2420
2421         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2422                 return -EIO;
2423
2424         return 0;
2425 }
2426
2427  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2428 static int
2429 nfp_net_reta_query(struct rte_eth_dev *dev,
2430                    struct rte_eth_rss_reta_entry64 *reta_conf,
2431                    uint16_t reta_size)
2432 {
2433         uint8_t i, j, mask;
2434         int idx, shift;
2435         uint32_t reta;
2436         struct nfp_net_hw *hw;
2437
2438         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439
2440         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2441                 return -EINVAL;
2442
2443         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2444                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2445                         "(%d) doesn't match the number hardware can supported "
2446                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2447                 return -EINVAL;
2448         }
2449
2450         /*
2451          * Reading Redirection Table. There are 128 8bit-entries which can be
2452          * manage as 32 32bit-entries
2453          */
2454         for (i = 0; i < reta_size; i += 4) {
2455                 /* Handling 4 RSS entries per loop */
2456                 idx = i / RTE_RETA_GROUP_SIZE;
2457                 shift = i % RTE_RETA_GROUP_SIZE;
2458                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2459
2460                 if (!mask)
2461                         continue;
2462
2463                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2464                                     shift);
2465                 for (j = 0; j < 4; j++) {
2466                         if (!(mask & (0x1 << j)))
2467                                 continue;
2468                         reta_conf[idx].reta[shift + j] =
2469                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2470                 }
2471         }
2472         return 0;
2473 }
2474
2475 static int
2476 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2477                         struct rte_eth_rss_conf *rss_conf)
2478 {
2479         struct nfp_net_hw *hw;
2480         uint64_t rss_hf;
2481         uint32_t cfg_rss_ctrl = 0;
2482         uint8_t key;
2483         int i;
2484
2485         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486
2487         /* Writing the key byte a byte */
2488         for (i = 0; i < rss_conf->rss_key_len; i++) {
2489                 memcpy(&key, &rss_conf->rss_key[i], 1);
2490                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2491         }
2492
2493         rss_hf = rss_conf->rss_hf;
2494
2495         if (rss_hf & ETH_RSS_IPV4)
2496                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2497
2498         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2499                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2500
2501         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2502                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2503
2504         if (rss_hf & ETH_RSS_IPV6)
2505                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2506
2507         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2508                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2509
2510         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2511                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2512
2513         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2514         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2515
2516         /* configuring where to apply the RSS hash */
2517         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2518
2519         /* Writing the key size */
2520         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2521
2522         return 0;
2523 }
2524
2525 static int
2526 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2527                         struct rte_eth_rss_conf *rss_conf)
2528 {
2529         uint32_t update;
2530         uint64_t rss_hf;
2531         struct nfp_net_hw *hw;
2532
2533         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534
2535         rss_hf = rss_conf->rss_hf;
2536
2537         /* Checking if RSS is enabled */
2538         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2539                 if (rss_hf != 0) { /* Enable RSS? */
2540                         PMD_DRV_LOG(ERR, "RSS unsupported");
2541                         return -EINVAL;
2542                 }
2543                 return 0; /* Nothing to do */
2544         }
2545
2546         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2547                 PMD_DRV_LOG(ERR, "hash key too long");
2548                 return -EINVAL;
2549         }
2550
2551         nfp_net_rss_hash_write(dev, rss_conf);
2552
2553         update = NFP_NET_CFG_UPDATE_RSS;
2554
2555         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2556                 return -EIO;
2557
2558         return 0;
2559 }
2560
2561 static int
2562 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2563                           struct rte_eth_rss_conf *rss_conf)
2564 {
2565         uint64_t rss_hf;
2566         uint32_t cfg_rss_ctrl;
2567         uint8_t key;
2568         int i;
2569         struct nfp_net_hw *hw;
2570
2571         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2572
2573         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2574                 return -EINVAL;
2575
2576         rss_hf = rss_conf->rss_hf;
2577         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2578
2579         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2580                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2581
2582         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2583                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2584
2585         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2586                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2587
2588         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2589                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2590
2591         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2592                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2593
2594         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2595                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2596
2597         /* Reading the key size */
2598         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2599
2600         /* Reading the key byte a byte */
2601         for (i = 0; i < rss_conf->rss_key_len; i++) {
2602                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2603                 memcpy(&rss_conf->rss_key[i], &key, 1);
2604         }
2605
2606         return 0;
2607 }
2608
2609 static int
2610 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2611 {
2612         struct rte_eth_conf *dev_conf;
2613         struct rte_eth_rss_conf rss_conf;
2614         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2615         uint16_t rx_queues = dev->data->nb_rx_queues;
2616         uint16_t queue;
2617         int i, j, ret;
2618
2619         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2620                 rx_queues);
2621
2622         nfp_reta_conf[0].mask = ~0x0;
2623         nfp_reta_conf[1].mask = ~0x0;
2624
2625         queue = 0;
2626         for (i = 0; i < 0x40; i += 8) {
2627                 for (j = i; j < (i + 8); j++) {
2628                         nfp_reta_conf[0].reta[j] = queue;
2629                         nfp_reta_conf[1].reta[j] = queue++;
2630                         queue %= rx_queues;
2631                 }
2632         }
2633         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2634         if (ret != 0)
2635                 return ret;
2636
2637         dev_conf = &dev->data->dev_conf;
2638         if (!dev_conf) {
2639                 PMD_DRV_LOG(INFO, "wrong rss conf");
2640                 return -EINVAL;
2641         }
2642         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2643
2644         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2645
2646         return ret;
2647 }
2648
2649
2650 /* Initialise and register driver with DPDK Application */
2651 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2652         .dev_configure          = nfp_net_configure,
2653         .dev_start              = nfp_net_start,
2654         .dev_stop               = nfp_net_stop,
2655         .dev_close              = nfp_net_close,
2656         .promiscuous_enable     = nfp_net_promisc_enable,
2657         .promiscuous_disable    = nfp_net_promisc_disable,
2658         .link_update            = nfp_net_link_update,
2659         .stats_get              = nfp_net_stats_get,
2660         .stats_reset            = nfp_net_stats_reset,
2661         .dev_infos_get          = nfp_net_infos_get,
2662         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2663         .mtu_set                = nfp_net_dev_mtu_set,
2664         .mac_addr_set           = nfp_set_mac_addr,
2665         .vlan_offload_set       = nfp_net_vlan_offload_set,
2666         .reta_update            = nfp_net_reta_update,
2667         .reta_query             = nfp_net_reta_query,
2668         .rss_hash_update        = nfp_net_rss_hash_update,
2669         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2670         .rx_queue_setup         = nfp_net_rx_queue_setup,
2671         .rx_queue_release       = nfp_net_rx_queue_release,
2672         .rx_queue_count         = nfp_net_rx_queue_count,
2673         .tx_queue_setup         = nfp_net_tx_queue_setup,
2674         .tx_queue_release       = nfp_net_tx_queue_release,
2675         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2676         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2677 };
2678
2679 /*
2680  * All eth_dev created got its private data, but before nfp_net_init, that
2681  * private data is referencing private data for all the PF ports. This is due
2682  * to how the vNIC bars are mapped based on first port, so all ports need info
2683  * about port 0 private data. Inside nfp_net_init the private data pointer is
2684  * changed to the right address for each port once the bars have been mapped.
2685  *
2686  * This functions helps to find out which port and therefore which offset
2687  * inside the private data array to use.
2688  */
2689 static int
2690 get_pf_port_number(char *name)
2691 {
2692         char *pf_str = name;
2693         int size = 0;
2694
2695         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2696                 pf_str++;
2697
2698         if (size == 30)
2699                 /*
2700                  * This should not happen at all and it would mean major
2701                  * implementation fault.
2702                  */
2703                 rte_panic("nfp_net: problem with pf device name\n");
2704
2705         /* Expecting _portX with X within [0,7] */
2706         pf_str += 5;
2707
2708         return (int)strtol(pf_str, NULL, 10);
2709 }
2710
2711 static int
2712 nfp_net_init(struct rte_eth_dev *eth_dev)
2713 {
2714         struct rte_pci_device *pci_dev;
2715         struct nfp_net_hw *hw, *hwport0;
2716
2717         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2718         uint32_t start_q;
2719         int stride = 4;
2720         int port = 0;
2721         int err;
2722
2723         PMD_INIT_FUNC_TRACE();
2724
2725         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2726
2727         /* NFP can not handle DMA addresses requiring more than 40 bits */
2728         if (rte_mem_check_dma_mask(40)) {
2729                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2730                                    pci_dev->device.name);
2731                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2732                 return -ENODEV;
2733         };
2734
2735         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2736             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2737                 port = get_pf_port_number(eth_dev->data->name);
2738                 if (port < 0 || port > 7) {
2739                         PMD_DRV_LOG(ERR, "Port value is wrong");
2740                         return -ENODEV;
2741                 }
2742
2743                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2744
2745                 /* This points to port 0 private data */
2746                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2747
2748                 /* This points to the specific port private data */
2749                 hw = &hwport0[port];
2750         } else {
2751                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2752                 hwport0 = 0;
2753         }
2754
2755         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2756         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2757         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2758
2759         /* For secondary processes, the primary has done all the work */
2760         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2761                 return 0;
2762
2763         rte_eth_copy_pci_info(eth_dev, pci_dev);
2764
2765         hw->device_id = pci_dev->id.device_id;
2766         hw->vendor_id = pci_dev->id.vendor_id;
2767         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2768         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2769
2770         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2771                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2772                      pci_dev->addr.domain, pci_dev->addr.bus,
2773                      pci_dev->addr.devid, pci_dev->addr.function);
2774
2775         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2776         if (hw->ctrl_bar == NULL) {
2777                 PMD_DRV_LOG(ERR,
2778                         "hw->ctrl_bar is NULL. BAR0 not configured");
2779                 return -ENODEV;
2780         }
2781
2782         if (hw->is_pf && port == 0) {
2783                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2784                                              hw->total_ports * 32768,
2785                                              &hw->ctrl_area);
2786                 if (!hw->ctrl_bar) {
2787                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2788                         return -EIO;
2789                 }
2790
2791                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2792         }
2793
2794         if (port > 0) {
2795                 if (!hwport0->ctrl_bar)
2796                         return -ENODEV;
2797
2798                 /* address based on port0 offset */
2799                 hw->ctrl_bar = hwport0->ctrl_bar +
2800                                (port * NFP_PF_CSR_SLICE_SIZE);
2801         }
2802
2803         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2804
2805         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2806         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2807
2808         /* Work out where in the BAR the queues start. */
2809         switch (pci_dev->id.device_id) {
2810         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2811         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2812         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2813                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2814                 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2815                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2816                 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2817                 break;
2818         default:
2819                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2820                 err = -ENODEV;
2821                 goto dev_err_ctrl_map;
2822         }
2823
2824         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2825         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2826
2827         if (hw->is_pf && port == 0) {
2828                 /* configure access to tx/rx vNIC BARs */
2829                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2830                                                       NFP_PCIE_QUEUE(0),
2831                                                       NFP_QCP_QUEUE_AREA_SZ,
2832                                                       &hw->hwqueues_area);
2833
2834                 if (!hwport0->hw_queues) {
2835                         printf("nfp_rtsym_map fails for net.qc");
2836                         err = -EIO;
2837                         goto dev_err_ctrl_map;
2838                 }
2839
2840                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2841                                     hwport0->hw_queues);
2842         }
2843
2844         if (hw->is_pf) {
2845                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2846                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2847                 eth_dev->data->dev_private = hw;
2848         } else {
2849                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2850                              tx_bar_off;
2851                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2852                              rx_bar_off;
2853         }
2854
2855         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2856                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2857
2858         nfp_net_cfg_queue_setup(hw);
2859
2860         /* Get some of the read-only fields from the config BAR */
2861         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2862         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2863         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2864         hw->mtu = ETHER_MTU;
2865
2866         /* VLAN insertion is incompatible with LSOv2 */
2867         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2868                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2869
2870         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2871                 hw->rx_offset = NFP_NET_RX_OFFSET;
2872         else
2873                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2874
2875         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2876                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2877                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2878
2879         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2880                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2881                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2882                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2883                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2884                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2885                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2886                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2887                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2888                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2889                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2890                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2891                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2892                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2893                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2894
2895         hw->ctrl = 0;
2896
2897         hw->stride_rx = stride;
2898         hw->stride_tx = stride;
2899
2900         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2901                      hw->max_rx_queues, hw->max_tx_queues);
2902
2903         /* Initializing spinlock for reconfigs */
2904         rte_spinlock_init(&hw->reconfig_lock);
2905
2906         /* Allocating memory for mac addr */
2907         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2908         if (eth_dev->data->mac_addrs == NULL) {
2909                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2910                 err = -ENOMEM;
2911                 goto dev_err_queues_map;
2912         }
2913
2914         if (hw->is_pf) {
2915                 nfp_net_pf_read_mac(hwport0, port);
2916                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2917         } else {
2918                 nfp_net_vf_read_mac(hw);
2919         }
2920
2921         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2922                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2923                                    port);
2924                 /* Using random mac addresses for VFs */
2925                 eth_random_addr(&hw->mac_addr[0]);
2926                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2927         }
2928
2929         /* Copying mac address to DPDK eth_dev struct */
2930         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2931                         &eth_dev->data->mac_addrs[0]);
2932
2933         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2934                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2935
2936         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2937                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2938                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2939                      pci_dev->id.device_id,
2940                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2941                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2942
2943         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2944                 /* Registering LSC interrupt handler */
2945                 rte_intr_callback_register(&pci_dev->intr_handle,
2946                                            nfp_net_dev_interrupt_handler,
2947                                            (void *)eth_dev);
2948                 /* Telling the firmware about the LSC interrupt entry */
2949                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2950                 /* Recording current stats counters values */
2951                 nfp_net_stats_reset(eth_dev);
2952         }
2953
2954         return 0;
2955
2956 dev_err_queues_map:
2957                 nfp_cpp_area_free(hw->hwqueues_area);
2958 dev_err_ctrl_map:
2959                 nfp_cpp_area_free(hw->ctrl_area);
2960
2961         return err;
2962 }
2963
2964 #define NFP_CPP_MEMIO_BOUNDARY          (1 << 20)
2965
2966 /*
2967  * Serving a write request to NFP from host programs. The request
2968  * sends the write size and the CPP target. The bridge makes use
2969  * of CPP interface handler configured by the PMD setup.
2970  */
2971 static int
2972 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
2973 {
2974         struct nfp_cpp_area *area;
2975         off_t offset, nfp_offset;
2976         uint32_t cpp_id, pos, len;
2977         uint32_t tmpbuf[16];
2978         size_t count, curlen, totlen = 0;
2979         int err = 0;
2980
2981         PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
2982                 sizeof(off_t), sizeof(size_t));
2983
2984         /* Reading the count param */
2985         err = recv(sockfd, &count, sizeof(off_t), 0);
2986         if (err != sizeof(off_t))
2987                 return -EINVAL;
2988
2989         curlen = count;
2990
2991         /* Reading the offset param */
2992         err = recv(sockfd, &offset, sizeof(off_t), 0);
2993         if (err != sizeof(off_t))
2994                 return -EINVAL;
2995
2996         /* Obtain target's CPP ID and offset in target */
2997         cpp_id = (offset >> 40) << 8;
2998         nfp_offset = offset & ((1ull << 40) - 1);
2999
3000         PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
3001                 offset);
3002         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3003                 cpp_id, nfp_offset);
3004
3005         /* Adjust length if not aligned */
3006         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3007             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3008                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3009                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3010         }
3011
3012         while (count > 0) {
3013                 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3014                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3015                                                     nfp_offset, curlen);
3016                 if (!area) {
3017                         RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3018                         return -EIO;
3019                 }
3020
3021                 /* mapping the target */
3022                 err = nfp_cpp_area_acquire(area);
3023                 if (err < 0) {
3024                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3025                         nfp_cpp_area_free(area);
3026                         return -EIO;
3027                 }
3028
3029                 for (pos = 0; pos < curlen; pos += len) {
3030                         len = curlen - pos;
3031                         if (len > sizeof(tmpbuf))
3032                                 len = sizeof(tmpbuf);
3033
3034                         PMD_CPP_LOG(DEBUG, "%s: Receive %u of %lu\n", __func__,
3035                                            len, count);
3036                         err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3037                         if (err != (int)len) {
3038                                 RTE_LOG(ERR, PMD,
3039                                         "%s: error when receiving, %d of %lu\n",
3040                                         __func__, err, count);
3041                                 nfp_cpp_area_release(area);
3042                                 nfp_cpp_area_free(area);
3043                                 return -EIO;
3044                         }
3045                         err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3046                         if (err < 0) {
3047                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3048                                 nfp_cpp_area_release(area);
3049                                 nfp_cpp_area_free(area);
3050                                 return -EIO;
3051                         }
3052                 }
3053
3054                 nfp_offset += pos;
3055                 totlen += pos;
3056                 nfp_cpp_area_release(area);
3057                 nfp_cpp_area_free(area);
3058
3059                 count -= pos;
3060                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3061                          NFP_CPP_MEMIO_BOUNDARY : count;
3062         }
3063
3064         return 0;
3065 }
3066
3067 /*
3068  * Serving a read request to NFP from host programs. The request
3069  * sends the read size and the CPP target. The bridge makes use
3070  * of CPP interface handler configured by the PMD setup. The read
3071  * data is sent to the requester using the same socket.
3072  */
3073 static int
3074 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3075 {
3076         struct nfp_cpp_area *area;
3077         off_t offset, nfp_offset;
3078         uint32_t cpp_id, pos, len;
3079         uint32_t tmpbuf[16];
3080         size_t count, curlen, totlen = 0;
3081         int err = 0;
3082
3083         PMD_CPP_LOG(DEBUG, "%s: offset size %lu, count_size: %lu\n", __func__,
3084                 sizeof(off_t), sizeof(size_t));
3085
3086         /* Reading the count param */
3087         err = recv(sockfd, &count, sizeof(off_t), 0);
3088         if (err != sizeof(off_t))
3089                 return -EINVAL;
3090
3091         curlen = count;
3092
3093         /* Reading the offset param */
3094         err = recv(sockfd, &offset, sizeof(off_t), 0);
3095         if (err != sizeof(off_t))
3096                 return -EINVAL;
3097
3098         /* Obtain target's CPP ID and offset in target */
3099         cpp_id = (offset >> 40) << 8;
3100         nfp_offset = offset & ((1ull << 40) - 1);
3101
3102         PMD_CPP_LOG(DEBUG, "%s: count %lu and offset %ld\n", __func__, count,
3103                            offset);
3104         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %ld\n", __func__,
3105                            cpp_id, nfp_offset);
3106
3107         /* Adjust length if not aligned */
3108         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3109             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3110                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3111                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3112         }
3113
3114         while (count > 0) {
3115                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3116                                                     nfp_offset, curlen);
3117                 if (!area) {
3118                         RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3119                         return -EIO;
3120                 }
3121
3122                 err = nfp_cpp_area_acquire(area);
3123                 if (err < 0) {
3124                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3125                         nfp_cpp_area_free(area);
3126                         return -EIO;
3127                 }
3128
3129                 for (pos = 0; pos < curlen; pos += len) {
3130                         len = curlen - pos;
3131                         if (len > sizeof(tmpbuf))
3132                                 len = sizeof(tmpbuf);
3133
3134                         err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3135                         if (err < 0) {
3136                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3137                                 nfp_cpp_area_release(area);
3138                                 nfp_cpp_area_free(area);
3139                                 return -EIO;
3140                         }
3141                         PMD_CPP_LOG(DEBUG, "%s: sending %u of %lu\n", __func__,
3142                                            len, count);
3143
3144                         err = send(sockfd, tmpbuf, len, 0);
3145                         if (err != (int)len) {
3146                                 RTE_LOG(ERR, PMD,
3147                                         "%s: error when sending: %d of %lu\n",
3148                                         __func__, err, count);
3149                                 nfp_cpp_area_release(area);
3150                                 nfp_cpp_area_free(area);
3151                                 return -EIO;
3152                         }
3153                 }
3154
3155                 nfp_offset += pos;
3156                 totlen += pos;
3157                 nfp_cpp_area_release(area);
3158                 nfp_cpp_area_free(area);
3159
3160                 count -= pos;
3161                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3162                         NFP_CPP_MEMIO_BOUNDARY : count;
3163         }
3164         return 0;
3165 }
3166
3167 #define NFP_IOCTL 'n'
3168 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3169 /*
3170  * Serving a ioctl command from host NFP tools. This usually goes to
3171  * a kernel driver char driver but it is not available when the PF is
3172  * bound to the PMD. Currently just one ioctl command is served and it
3173  * does not require any CPP access at all.
3174  */
3175 static int
3176 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3177 {
3178         uint32_t cmd, ident_size, tmp;
3179         int err;
3180
3181         /* Reading now the IOCTL command */
3182         err = recv(sockfd, &cmd, 4, 0);
3183         if (err != 4) {
3184                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3185                 return -EIO;
3186         }
3187
3188         /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3189         if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3190                 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3191                 return -EINVAL;
3192         }
3193
3194         err = recv(sockfd, &ident_size, 4, 0);
3195         if (err != 4) {
3196                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3197                 return -EIO;
3198         }
3199
3200         tmp = nfp_cpp_model(cpp);
3201
3202         PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3203
3204         err = send(sockfd, &tmp, 4, 0);
3205         if (err != 4) {
3206                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3207                 return -EIO;
3208         }
3209
3210         tmp = cpp->interface;
3211
3212         PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3213
3214         err = send(sockfd, &tmp, 4, 0);
3215         if (err != 4) {
3216                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3217                 return -EIO;
3218         }
3219
3220         return 0;
3221 }
3222
3223 #define NFP_BRIDGE_OP_READ      20
3224 #define NFP_BRIDGE_OP_WRITE     30
3225 #define NFP_BRIDGE_OP_IOCTL     40
3226
3227 /*
3228  * This is the code to be executed by a service core. The CPP bridge interface
3229  * is based on a unix socket and requests usually received by a kernel char
3230  * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3231  * can be executed with a wrapper library and LD_LIBRARY being completely
3232  * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3233  * accesses.
3234  */
3235 static int32_t
3236 nfp_cpp_bridge_service_func(void *args)
3237 {
3238         struct sockaddr address;
3239         struct nfp_cpp *cpp = args;
3240         int sockfd, datafd, op, ret;
3241
3242         unlink("/tmp/nfp_cpp");
3243         sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3244         if (sockfd < 0) {
3245                 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3246                         __func__);
3247                 return -EIO;
3248         }
3249
3250         memset(&address, 0, sizeof(struct sockaddr));
3251
3252         address.sa_family = AF_UNIX;
3253         strcpy(address.sa_data, "/tmp/nfp_cpp");
3254
3255         ret = bind(sockfd, (const struct sockaddr *)&address,
3256                    sizeof(struct sockaddr));
3257         if (ret < 0) {
3258                 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3259                                   __func__, errno);
3260                 return ret;
3261         }
3262
3263         ret = listen(sockfd, 20);
3264         if (ret < 0) {
3265                 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3266                                   __func__, errno);
3267                 return ret;
3268         }
3269
3270         for (;;) {
3271                 datafd = accept(sockfd, NULL, NULL);
3272                 if (datafd < 0) {
3273                         RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3274                                           __func__, errno);
3275                         RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3276                         return -EIO;
3277                 }
3278
3279                 while (1) {
3280                         ret = recv(datafd, &op, 4, 0);
3281                         if (ret <= 0) {
3282                                 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3283                                                    __func__);
3284                                 break;
3285                         }
3286
3287                         PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3288
3289                         if (op == NFP_BRIDGE_OP_READ)
3290                                 nfp_cpp_bridge_serve_read(datafd, cpp);
3291
3292                         if (op == NFP_BRIDGE_OP_WRITE)
3293                                 nfp_cpp_bridge_serve_write(datafd, cpp);
3294
3295                         if (op == NFP_BRIDGE_OP_IOCTL)
3296                                 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3297
3298                         if (op == 0)
3299                                 break;
3300                 }
3301                 close(datafd);
3302         }
3303         close(sockfd);
3304
3305         return 0;
3306 }
3307
3308 static int
3309 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3310                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3311                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3312 {
3313         struct rte_eth_dev *eth_dev;
3314         struct nfp_net_hw *hw = NULL;
3315         char *port_name;
3316         struct rte_service_spec service;
3317         int retval;
3318
3319         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3320         if (!port_name)
3321                 return -ENOMEM;
3322
3323         if (ports > 1)
3324                 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3325         else
3326                 strlcat(port_name, dev->device.name, 100);
3327
3328
3329         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3330                 eth_dev = rte_eth_dev_allocate(port_name);
3331                 if (!eth_dev) {
3332                         rte_free(port_name);
3333                         return -ENODEV;
3334                 }
3335                 if (port == 0) {
3336                         *priv = rte_zmalloc(port_name,
3337                                             sizeof(struct nfp_net_adapter) *
3338                                             ports, RTE_CACHE_LINE_SIZE);
3339                         if (!*priv) {
3340                                 rte_free(port_name);
3341                                 rte_eth_dev_release_port(eth_dev);
3342                                 return -ENOMEM;
3343                         }
3344                 }
3345                 eth_dev->data->dev_private = *priv;
3346
3347                 /*
3348                  * dev_private pointing to port0 dev_private because we need
3349                  * to configure vNIC bars based on port0 at nfp_net_init.
3350                  * Then dev_private is adjusted per port.
3351                  */
3352                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3353                 hw->cpp = cpp;
3354                 hw->hwinfo = hwinfo;
3355                 hw->sym_tbl = sym_tbl;
3356                 hw->pf_port_idx = phys_port;
3357                 hw->is_pf = 1;
3358                 if (ports > 1)
3359                         hw->pf_multiport_enabled = 1;
3360
3361                 hw->total_ports = ports;
3362         } else {
3363                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3364                 if (!eth_dev) {
3365                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3366                                 "ethdev doesn't exist");
3367                         rte_free(port_name);
3368                         return -ENODEV;
3369                 }
3370                 eth_dev->process_private = cpp;
3371         }
3372
3373         eth_dev->device = &dev->device;
3374         rte_eth_copy_pci_info(eth_dev, dev);
3375
3376         retval = nfp_net_init(eth_dev);
3377
3378         if (retval) {
3379                 retval = -ENODEV;
3380                 goto probe_failed;
3381         } else {
3382                 rte_eth_dev_probing_finish(eth_dev);
3383         }
3384
3385         rte_free(port_name);
3386
3387         if (port == 0) {
3388                 /*
3389                  * The rte_service needs to be created just once per PMD.
3390                  * And the cpp handler needs to be linked to the service.
3391                  * Secondary processes will be used for debugging DPDK apps
3392                  * when requiring to use the CPP interface for accessing NFP
3393                  * components. And the cpp handler for secondary processes is
3394                  * available at this point.
3395                  */
3396                 memset(&service, 0, sizeof(struct rte_service_spec));
3397                 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3398                 service.callback = nfp_cpp_bridge_service_func;
3399                 service.callback_userdata = (void *)cpp;
3400
3401                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3402
3403                 if (rte_service_component_register(&service,
3404                                                    &hw->nfp_cpp_service_id))
3405                         RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3406                 else
3407                         RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3408         }
3409
3410         return retval;
3411
3412 probe_failed:
3413         rte_free(port_name);
3414         /* free ports private data if primary process */
3415         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3416                 rte_free(eth_dev->data->dev_private);
3417
3418         rte_eth_dev_release_port(eth_dev);
3419
3420         return retval;
3421 }
3422
3423 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3424
3425 static int
3426 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3427 {
3428         struct nfp_cpp *cpp = nsp->cpp;
3429         int fw_f;
3430         char *fw_buf;
3431         char fw_name[125];
3432         char serial[40];
3433         struct stat file_stat;
3434         off_t fsize, bytes;
3435
3436         /* Looking for firmware file in order of priority */
3437
3438         /* First try to find a firmware image specific for this device */
3439         snprintf(serial, sizeof(serial),
3440                         "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3441                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3442                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3443                 cpp->interface & 0xff);
3444
3445         snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3446                         serial);
3447
3448         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3449         fw_f = open(fw_name, O_RDONLY);
3450         if (fw_f > 0)
3451                 goto read_fw;
3452
3453         /* Then try the PCI name */
3454         snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3455                         dev->device.name);
3456
3457         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3458         fw_f = open(fw_name, O_RDONLY);
3459         if (fw_f > 0)
3460                 goto read_fw;
3461
3462         /* Finally try the card type and media */
3463         snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3464         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3465         fw_f = open(fw_name, O_RDONLY);
3466         if (fw_f < 0) {
3467                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3468                 return -ENOENT;
3469         }
3470
3471 read_fw:
3472         if (fstat(fw_f, &file_stat) < 0) {
3473                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3474                 close(fw_f);
3475                 return -ENOENT;
3476         }
3477
3478         fsize = file_stat.st_size;
3479         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3480                             fw_name, (uint64_t)fsize);
3481
3482         fw_buf = malloc((size_t)fsize);
3483         if (!fw_buf) {
3484                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3485                 close(fw_f);
3486                 return -ENOMEM;
3487         }
3488         memset(fw_buf, 0, fsize);
3489
3490         bytes = read(fw_f, fw_buf, fsize);
3491         if (bytes != fsize) {
3492                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3493                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3494                                    (uint64_t)bytes, (uint64_t)fsize);
3495                 free(fw_buf);
3496                 close(fw_f);
3497                 return -EIO;
3498         }
3499
3500         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3501         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3502         PMD_DRV_LOG(INFO, "Done");
3503
3504         free(fw_buf);
3505         close(fw_f);
3506
3507         return 0;
3508 }
3509
3510 static int
3511 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3512              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3513 {
3514         struct nfp_nsp *nsp;
3515         const char *nfp_fw_model;
3516         char card_desc[100];
3517         int err = 0;
3518
3519         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3520
3521         if (nfp_fw_model) {
3522                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3523         } else {
3524                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3525                 return -EIO;
3526         }
3527
3528         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3529                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3530                        nfp_eth_table->count);
3531                 return -EIO;
3532         }
3533
3534         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3535                            nfp_eth_table->count);
3536
3537         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3538
3539         snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3540                         nfp_fw_model, nfp_eth_table->count,
3541                         nfp_eth_table->ports[0].speed / 1000);
3542
3543         nsp = nfp_nsp_open(cpp);
3544         if (!nsp) {
3545                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3546                 return -EIO;
3547         }
3548
3549         nfp_nsp_device_soft_reset(nsp);
3550         err = nfp_fw_upload(dev, nsp, card_desc);
3551
3552         nfp_nsp_close(nsp);
3553         return err;
3554 }
3555
3556 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3557                             struct rte_pci_device *dev)
3558 {
3559         struct nfp_cpp *cpp;
3560         struct nfp_hwinfo *hwinfo;
3561         struct nfp_rtsym_table *sym_tbl;
3562         struct nfp_eth_table *nfp_eth_table = NULL;
3563         int total_ports;
3564         void *priv = 0;
3565         int ret = -ENODEV;
3566         int err;
3567         int i;
3568
3569         if (!dev)
3570                 return ret;
3571
3572         /*
3573          * When device bound to UIO, the device could be used, by mistake,
3574          * by two DPDK apps, and the UIO driver does not avoid it. This
3575          * could lead to a serious problem when configuring the NFP CPP
3576          * interface. Here we avoid this telling to the CPP init code to
3577          * use a lock file if UIO is being used.
3578          */
3579         if (dev->kdrv == RTE_KDRV_VFIO)
3580                 cpp = nfp_cpp_from_device_name(dev, 0);
3581         else
3582                 cpp = nfp_cpp_from_device_name(dev, 1);
3583
3584         if (!cpp) {
3585                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3586                 ret = -EIO;
3587                 goto error;
3588         }
3589
3590         hwinfo = nfp_hwinfo_read(cpp);
3591         if (!hwinfo) {
3592                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3593                 return -EIO;
3594         }
3595
3596         nfp_eth_table = nfp_eth_read_ports(cpp);
3597         if (!nfp_eth_table) {
3598                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3599                 return -EIO;
3600         }
3601
3602         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3603                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3604                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3605                         ret = -EIO;
3606                         goto error;
3607                 }
3608         }
3609
3610         /* Now the symbol table should be there */
3611         sym_tbl = nfp_rtsym_table_read(cpp);
3612         if (!sym_tbl) {
3613                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3614                                 " symbol table");
3615                 ret = -EIO;
3616                 goto error;
3617         }
3618
3619         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3620         if (total_ports != (int)nfp_eth_table->count) {
3621                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3622                 ret = -EIO;
3623                 goto error;
3624         }
3625         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3626
3627         if (total_ports <= 0 || total_ports > 8) {
3628                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3629                 ret = -ENODEV;
3630                 goto error;
3631         }
3632
3633         for (i = 0; i < total_ports; i++) {
3634                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3635                                         nfp_eth_table->ports[i].index,
3636                                         sym_tbl, &priv);
3637                 if (ret)
3638                         break;
3639         }
3640
3641 error:
3642         free(nfp_eth_table);
3643         return ret;
3644 }
3645
3646 int nfp_logtype_init;
3647 int nfp_logtype_driver;
3648
3649 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3650         {
3651                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3652                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3653         },
3654         {
3655                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3656                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3657         },
3658         {
3659                 .vendor_id = 0,
3660         },
3661 };
3662
3663 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3664         {
3665                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3666                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3667         },
3668         {
3669                 .vendor_id = 0,
3670         },
3671 };
3672
3673 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3674         struct rte_pci_device *pci_dev)
3675 {
3676         return rte_eth_dev_pci_generic_probe(pci_dev,
3677                 sizeof(struct nfp_net_adapter), nfp_net_init);
3678 }
3679
3680 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3681 {
3682         struct rte_eth_dev *eth_dev;
3683         struct nfp_net_hw *hw, *hwport0;
3684         int port = 0;
3685
3686         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3687         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3688             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3689                 port = get_pf_port_number(eth_dev->data->name);
3690                 /*
3691                  * hotplug is not possible with multiport PF although freeing
3692                  * data structures can be done for first port.
3693                  */
3694                 if (port != 0)
3695                         return -ENOTSUP;
3696                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3697                 hw = &hwport0[port];
3698                 nfp_cpp_area_free(hw->ctrl_area);
3699                 nfp_cpp_area_free(hw->hwqueues_area);
3700                 free(hw->hwinfo);
3701                 free(hw->sym_tbl);
3702                 nfp_cpp_free(hw->cpp);
3703         } else {
3704                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3705         }
3706         /* hotplug is not possible with multiport PF */
3707         if (hw->pf_multiport_enabled)
3708                 return -ENOTSUP;
3709         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3710 }
3711
3712 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3713         .id_table = pci_id_nfp_pf_net_map,
3714         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3715                      RTE_PCI_DRV_IOVA_AS_VA,
3716         .probe = nfp_pf_pci_probe,
3717         .remove = eth_nfp_pci_remove,
3718 };
3719
3720 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3721         .id_table = pci_id_nfp_vf_net_map,
3722         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3723                      RTE_PCI_DRV_IOVA_AS_VA,
3724         .probe = eth_nfp_pci_probe,
3725         .remove = eth_nfp_pci_remove,
3726 };
3727
3728 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3729 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3730 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3731 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3732 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3733 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3734
3735 RTE_INIT(nfp_init_log)
3736 {
3737         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3738         if (nfp_logtype_init >= 0)
3739                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3740         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3741         if (nfp_logtype_driver >= 0)
3742                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3743 }
3744 /*
3745  * Local variables:
3746  * c-file-style: "Linux"
3747  * indent-tabs-mode: t
3748  * End:
3749  */