drivers/net/nfp/nfp_net.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  */
   7
   8 /*
   9  * vim:shiftwidth=8:noexpandtab
  10  *
  11  * @file dpdk/pmd/nfp_net.c
  12  *
  13  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  14  */
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_log.h>
  19 #include <rte_debug.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_dev.h>
  23 #include <rte_ether.h>
  24 #include <rte_malloc.h>
  25 #include <rte_memzone.h>
  26 #include <rte_mempool.h>
  27 #include <rte_version.h>
  28 #include <rte_string_fns.h>
  29 #include <rte_alarm.h>
  30 #include <rte_spinlock.h>
  31 #include <rte_service_component.h>
  32
  33 #include "nfpcore/nfp_cpp.h"
  34 #include "nfpcore/nfp_nffw.h"
  35 #include "nfpcore/nfp_hwinfo.h"
  36 #include "nfpcore/nfp_mip.h"
  37 #include "nfpcore/nfp_rtsym.h"
  38 #include "nfpcore/nfp_nsp.h"
  39
  40 #include "nfp_net_pmd.h"
  41 #include "nfp_net_logs.h"
  42 #include "nfp_net_ctrl.h"
  43
  44 #include <sys/types.h>
  45 #include <sys/socket.h>
  46 #include <sys/un.h>
  47 #include <unistd.h>
  48 #include <stdio.h>
  49 #include <sys/ioctl.h>
  50 #include <errno.h>
  51
  52 /* Prototypes */
  53 static int nfp_net_close(struct rte_eth_dev *dev);
  54 static int nfp_net_configure(struct rte_eth_dev *dev);
  55 static void nfp_net_dev_interrupt_handler(void *param);
  56 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  57 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  58 static int nfp_net_infos_get(struct rte_eth_dev *dev,
  59                              struct rte_eth_dev_info *dev_info);
  60 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  61 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  62 static int nfp_net_promisc_enable(struct rte_eth_dev *dev);
  63 static int nfp_net_promisc_disable(struct rte_eth_dev *dev);
  64 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  65 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  66                                        uint16_t queue_idx);
  67 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  68                                   uint16_t nb_pkts);
  69 static void nfp_net_rx_queue_release(void *rxq);
  70 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  71                                   uint16_t nb_desc, unsigned int socket_id,
  72                                   const struct rte_eth_rxconf *rx_conf,
  73                                   struct rte_mempool *mp);
  74 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  75 static void nfp_net_tx_queue_release(void *txq);
  76 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  77                                   uint16_t nb_desc, unsigned int socket_id,
  78                                   const struct rte_eth_txconf *tx_conf);
  79 static int nfp_net_start(struct rte_eth_dev *dev);
  80 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  81                               struct rte_eth_stats *stats);
  82 static int nfp_net_stats_reset(struct rte_eth_dev *dev);
  83 static void nfp_net_stop(struct rte_eth_dev *dev);
  84 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  85                                   uint16_t nb_pkts);
  86
  87 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
  88 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
  89                                    struct rte_eth_rss_conf *rss_conf);
  90 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
  91                     struct rte_eth_rss_reta_entry64 *reta_conf,
  92                     uint16_t reta_size);
  93 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
  94                         struct rte_eth_rss_conf *rss_conf);
  95 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
  96                              struct rte_ether_addr *mac_addr);
  97
  98 /* The offset of the queue controller queues in the PCIe Target */
  99 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 100
 101 /* Maximum value which can be added to a queue with one transaction */
 102 #define NFP_QCP_MAX_ADD 0x7f
 103
 104 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 105         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 106
 107 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 108 enum nfp_qcp_ptr {
 109         NFP_QCP_READ_PTR = 0,
 110         NFP_QCP_WRITE_PTR
 111 };
 112
 113 /*
 114  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 115  * @q: Base address for queue structure
 116  * @ptr: Add to the Read or Write pointer
 117  * @val: Value to add to the queue pointer
 118  *
 119  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 120  */
 121 static inline void
 122 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 123 {
 124         uint32_t off;
 125
 126         if (ptr == NFP_QCP_READ_PTR)
 127                 off = NFP_QCP_QUEUE_ADD_RPTR;
 128         else
 129                 off = NFP_QCP_QUEUE_ADD_WPTR;
 130
 131         while (val > NFP_QCP_MAX_ADD) {
 132                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 133                 val -= NFP_QCP_MAX_ADD;
 134         }
 135
 136         nn_writel(rte_cpu_to_le_32(val), q + off);
 137 }
 138
 139 /*
 140  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 141  * @q:  Base address for queue structure
 142  * @ptr: Read or Write pointer
 143  */
 144 static inline uint32_t
 145 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 146 {
 147         uint32_t off;
 148         uint32_t val;
 149
 150         if (ptr == NFP_QCP_READ_PTR)
 151                 off = NFP_QCP_QUEUE_STS_LO;
 152         else
 153                 off = NFP_QCP_QUEUE_STS_HI;
 154
 155         val = rte_cpu_to_le_32(nn_readl(q + off));
 156
 157         if (ptr == NFP_QCP_READ_PTR)
 158                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 159         else
 160                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 161 }
 162
 163 /*
 164  * Functions to read/write from/to Config BAR
 165  * Performs any endian conversion necessary.
 166  */
 167 static inline uint8_t
 168 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 169 {
 170         return nn_readb(hw->ctrl_bar + off);
 171 }
 172
 173 static inline void
 174 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 175 {
 176         nn_writeb(val, hw->ctrl_bar + off);
 177 }
 178
 179 static inline uint32_t
 180 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 181 {
 182         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 183 }
 184
 185 static inline void
 186 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 187 {
 188         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 189 }
 190
 191 static inline uint64_t
 192 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 193 {
 194         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 195 }
 196
 197 static inline void
 198 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 199 {
 200         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 201 }
 202
 203 static void
 204 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 205 {
 206         unsigned i;
 207
 208         if (rxq->rxbufs == NULL)
 209                 return;
 210
 211         for (i = 0; i < rxq->rx_count; i++) {
 212                 if (rxq->rxbufs[i].mbuf) {
 213                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 214                         rxq->rxbufs[i].mbuf = NULL;
 215                 }
 216         }
 217 }
 218
 219 static void
 220 nfp_net_rx_queue_release(void *rx_queue)
 221 {
 222         struct nfp_net_rxq *rxq = rx_queue;
 223
 224         if (rxq) {
 225                 nfp_net_rx_queue_release_mbufs(rxq);
 226                 rte_free(rxq->rxbufs);
 227                 rte_free(rxq);
 228         }
 229 }
 230
 231 static void
 232 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 233 {
 234         nfp_net_rx_queue_release_mbufs(rxq);
 235         rxq->rd_p = 0;
 236         rxq->nb_rx_hold = 0;
 237 }
 238
 239 static void
 240 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 241 {
 242         unsigned i;
 243
 244         if (txq->txbufs == NULL)
 245                 return;
 246
 247         for (i = 0; i < txq->tx_count; i++) {
 248                 if (txq->txbufs[i].mbuf) {
 249                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 250                         txq->txbufs[i].mbuf = NULL;
 251                 }
 252         }
 253 }
 254
 255 static void
 256 nfp_net_tx_queue_release(void *tx_queue)
 257 {
 258         struct nfp_net_txq *txq = tx_queue;
 259
 260         if (txq) {
 261                 nfp_net_tx_queue_release_mbufs(txq);
 262                 rte_free(txq->txbufs);
 263                 rte_free(txq);
 264         }
 265 }
 266
 267 static void
 268 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 269 {
 270         nfp_net_tx_queue_release_mbufs(txq);
 271         txq->wr_p = 0;
 272         txq->rd_p = 0;
 273 }
 274
 275 static int
 276 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 277 {
 278         int cnt;
 279         uint32_t new;
 280         struct timespec wait;
 281
 282         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 283                     hw->qcp_cfg);
 284
 285         if (hw->qcp_cfg == NULL)
 286                 rte_panic("Bad configuration queue pointer\n");
 287
 288         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 289
 290         wait.tv_sec = 0;
 291         wait.tv_nsec = 1000000;
 292
 293         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 294
 295         /* Poll update field, waiting for NFP to ack the config */
 296         for (cnt = 0; ; cnt++) {
 297                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 298                 if (new == 0)
 299                         break;
 300                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 301                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 302                         return -1;
 303                 }
 304                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 305                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 306                                           " %dms", update, cnt);
 307                         rte_panic("Exiting\n");
 308                 }
 309                 nanosleep(&wait, 0); /* waiting for a 1ms */
 310         }
 311         PMD_DRV_LOG(DEBUG, "Ack DONE");
 312         return 0;
 313 }
 314
 315 /*
 316  * Reconfigure the NIC
 317  * @nn:    device to reconfigure
 318  * @ctrl:    The value for the ctrl field in the BAR config
 319  * @update:  The value for the update field in the BAR config
 320  *
 321  * Write the update word to the BAR and ping the reconfig queue. Then poll
 322  * until the firmware has acknowledged the update by zeroing the update word.
 323  */
 324 static int
 325 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 326 {
 327         uint32_t err;
 328
 329         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 330                     ctrl, update);
 331
 332         rte_spinlock_lock(&hw->reconfig_lock);
 333
 334         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 335         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 336
 337         rte_wmb();
 338
 339         err = __nfp_net_reconfig(hw, update);
 340
 341         rte_spinlock_unlock(&hw->reconfig_lock);
 342
 343         if (!err)
 344                 return 0;
 345
 346         /*
 347          * Reconfig errors imply situations where they can be handled.
 348          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 349          */
 350         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 351                      ctrl, update);
 352         return -EIO;
 353 }
 354
 355 /*
 356  * Configure an Ethernet device. This function must be invoked first
 357  * before any other function in the Ethernet API. This function can
 358  * also be re-invoked when a device is in the stopped state.
 359  */
 360 static int
 361 nfp_net_configure(struct rte_eth_dev *dev)
 362 {
 363         struct rte_eth_conf *dev_conf;
 364         struct rte_eth_rxmode *rxmode;
 365         struct rte_eth_txmode *txmode;
 366         struct nfp_net_hw *hw;
 367
 368         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 369
 370         /*
 371          * A DPDK app sends info about how many queues to use and how
 372          * those queues need to be configured. This is used by the
 373          * DPDK core and it makes sure no more queues than those
 374          * advertised by the driver are requested. This function is
 375          * called after that internal process
 376          */
 377
 378         PMD_INIT_LOG(DEBUG, "Configure");
 379
 380         dev_conf = &dev->data->dev_conf;
 381         rxmode = &dev_conf->rxmode;
 382         txmode = &dev_conf->txmode;
 383
 384         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
 385                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 386
 387         /* Checking TX mode */
 388         if (txmode->mq_mode) {
 389                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 390                 return -EINVAL;
 391         }
 392
 393         /* Checking RX mode */
 394         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 395             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 396                 PMD_INIT_LOG(INFO, "RSS not supported");
 397                 return -EINVAL;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static void
 404 nfp_net_enable_queues(struct rte_eth_dev *dev)
 405 {
 406         struct nfp_net_hw *hw;
 407         uint64_t enabled_queues = 0;
 408         int i;
 409
 410         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 411
 412         /* Enabling the required TX queues in the device */
 413         for (i = 0; i < dev->data->nb_tx_queues; i++)
 414                 enabled_queues |= (1 << i);
 415
 416         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 417
 418         enabled_queues = 0;
 419
 420         /* Enabling the required RX queues in the device */
 421         for (i = 0; i < dev->data->nb_rx_queues; i++)
 422                 enabled_queues |= (1 << i);
 423
 424         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 425 }
 426
 427 static void
 428 nfp_net_disable_queues(struct rte_eth_dev *dev)
 429 {
 430         struct nfp_net_hw *hw;
 431         uint32_t new_ctrl, update = 0;
 432
 433         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434
 435         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 436         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 437
 438         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 439         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 440                  NFP_NET_CFG_UPDATE_MSIX;
 441
 442         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 443                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 444
 445         /* If an error when reconfig we avoid to change hw state */
 446         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 447                 return;
 448
 449         hw->ctrl = new_ctrl;
 450 }
 451
 452 static int
 453 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 454 {
 455         int i;
 456
 457         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 458                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 459                         return -1;
 460         }
 461         return 0;
 462 }
 463
 464 static void
 465 nfp_net_params_setup(struct nfp_net_hw *hw)
 466 {
 467         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 468         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 469 }
 470
 471 static void
 472 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 473 {
 474         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 475 }
 476
 477 #define ETH_ADDR_LEN    6
 478
 479 static void
 480 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 481 {
 482         int i;
 483
 484         for (i = 0; i < ETH_ADDR_LEN; i++)
 485                 dst[i] = src[i];
 486 }
 487
 488 static int
 489 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 490 {
 491         struct nfp_eth_table *nfp_eth_table;
 492
 493         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 494         /*
 495          * hw points to port0 private data. We need hw now pointing to
 496          * right port.
 497          */
 498         hw += port;
 499         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 500                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 501
 502         free(nfp_eth_table);
 503         return 0;
 504 }
 505
 506 static void
 507 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 508 {
 509         uint32_t tmp;
 510
 511         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 512         memcpy(&hw->mac_addr[0], &tmp, 4);
 513
 514         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 515         memcpy(&hw->mac_addr[4], &tmp, 2);
 516 }
 517
 518 static void
 519 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 520 {
 521         uint32_t mac0 = *(uint32_t *)mac;
 522         uint16_t mac1;
 523
 524         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 525
 526         mac += 4;
 527         mac1 = *(uint16_t *)mac;
 528         nn_writew(rte_cpu_to_be_16(mac1),
 529                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 530 }
 531
 532 int
 533 nfp_set_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
 534 {
 535         struct nfp_net_hw *hw;
 536         uint32_t update, ctrl;
 537
 538         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 539         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 540             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 541                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 542                                   " port enabled");
 543                 return -EBUSY;
 544         }
 545
 546         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 547             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 548                 return -EBUSY;
 549
 550         /* Writing new MAC to the specific port BAR address */
 551         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 552
 553         /* Signal the NIC about the change */
 554         update = NFP_NET_CFG_UPDATE_MACADDR;
 555         ctrl = hw->ctrl;
 556         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 557             (hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 558                 ctrl |= NFP_NET_CFG_CTRL_LIVE_ADDR;
 559         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 560                 PMD_INIT_LOG(INFO, "MAC address update failed");
 561                 return -EIO;
 562         }
 563         return 0;
 564 }
 565
 566 static int
 567 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 568                            struct rte_intr_handle *intr_handle)
 569 {
 570         struct nfp_net_hw *hw;
 571         int i;
 572
 573         if (!intr_handle->intr_vec) {
 574                 intr_handle->intr_vec =
 575                         rte_zmalloc("intr_vec",
 576                                     dev->data->nb_rx_queues * sizeof(int), 0);
 577                 if (!intr_handle->intr_vec) {
 578                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 579                                      " intr_vec", dev->data->nb_rx_queues);
 580                         return -ENOMEM;
 581                 }
 582         }
 583
 584         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 585
 586         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 587                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 588                 /* UIO just supports one queue and no LSC*/
 589                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 590                 intr_handle->intr_vec[0] = 0;
 591         } else {
 592                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 593                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 594                         /*
 595                          * The first msix vector is reserved for non
 596                          * efd interrupts
 597                         */
 598                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 599                         intr_handle->intr_vec[i] = i + 1;
 600                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 601                                             intr_handle->intr_vec[i]);
 602                 }
 603         }
 604
 605         /* Avoiding TX interrupts */
 606         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 607         return 0;
 608 }
 609
 610 static uint32_t
 611 nfp_check_offloads(struct rte_eth_dev *dev)
 612 {
 613         struct nfp_net_hw *hw;
 614         struct rte_eth_conf *dev_conf;
 615         struct rte_eth_rxmode *rxmode;
 616         struct rte_eth_txmode *txmode;
 617         uint32_t ctrl = 0;
 618
 619         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 620
 621         dev_conf = &dev->data->dev_conf;
 622         rxmode = &dev_conf->rxmode;
 623         txmode = &dev_conf->txmode;
 624
 625         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 626                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 627                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 628         }
 629
 630         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 631                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 632                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 633         }
 634
 635         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 636                 hw->mtu = rxmode->max_rx_pkt_len;
 637
 638         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 639                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 640
 641         /* L2 broadcast */
 642         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 643                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 644
 645         /* L2 multicast */
 646         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 647                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 648
 649         /* TX checksum offload */
 650         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 651             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 652             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 653                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 654
 655         /* LSO offload */
 656         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 657                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 658                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 659                 else
 660                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 661         }
 662
 663         /* RX gather */
 664         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 665                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 666
 667         return ctrl;
 668 }
 669
 670 static int
 671 nfp_net_start(struct rte_eth_dev *dev)
 672 {
 673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 674         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 675         uint32_t new_ctrl, update = 0;
 676         struct nfp_net_hw *hw;
 677         struct rte_eth_conf *dev_conf;
 678         struct rte_eth_rxmode *rxmode;
 679         uint32_t intr_vector;
 680         int ret;
 681
 682         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 683
 684         PMD_INIT_LOG(DEBUG, "Start");
 685
 686         /* Disabling queues just in case... */
 687         nfp_net_disable_queues(dev);
 688
 689         /* Enabling the required queues in the device */
 690         nfp_net_enable_queues(dev);
 691
 692         /* check and configure queue intr-vector mapping */
 693         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 694                 if (hw->pf_multiport_enabled) {
 695                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 696                                           "with NFP multiport PF");
 697                                 return -EINVAL;
 698                 }
 699                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 700                         /*
 701                          * Better not to share LSC with RX interrupts.
 702                          * Unregistering LSC interrupt handler
 703                          */
 704                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 705                                 nfp_net_dev_interrupt_handler, (void *)dev);
 706
 707                         if (dev->data->nb_rx_queues > 1) {
 708                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 709                                              "supports 1 queue with UIO");
 710                                 return -EIO;
 711                         }
 712                 }
 713                 intr_vector = dev->data->nb_rx_queues;
 714                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 715                         return -1;
 716
 717                 nfp_configure_rx_interrupt(dev, intr_handle);
 718                 update = NFP_NET_CFG_UPDATE_MSIX;
 719         }
 720
 721         rte_intr_enable(intr_handle);
 722
 723         new_ctrl = nfp_check_offloads(dev);
 724
 725         /* Writing configuration parameters in the device */
 726         nfp_net_params_setup(hw);
 727
 728         dev_conf = &dev->data->dev_conf;
 729         rxmode = &dev_conf->rxmode;
 730
 731         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 732                 nfp_net_rss_config_default(dev);
 733                 update |= NFP_NET_CFG_UPDATE_RSS;
 734                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 735         }
 736
 737         /* Enable device */
 738         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 739
 740         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 741
 742         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 743                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 744
 745         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 746         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 747                 return -EIO;
 748
 749         /*
 750          * Allocating rte mbufs for configured rx queues.
 751          * This requires queues being enabled before
 752          */
 753         if (nfp_net_rx_freelist_setup(dev) < 0) {
 754                 ret = -ENOMEM;
 755                 goto error;
 756         }
 757
 758         if (hw->is_pf) {
 759                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 760                         /* Configure the physical port up */
 761                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 762                 else
 763                         nfp_eth_set_configured(dev->process_private,
 764                                                hw->pf_port_idx, 1);
 765         }
 766
 767         hw->ctrl = new_ctrl;
 768
 769         return 0;
 770
 771 error:
 772         /*
 773          * An error returned by this function should mean the app
 774          * exiting and then the system releasing all the memory
 775          * allocated even memory coming from hugepages.
 776          *
 777          * The device could be enabled at this point with some queues
 778          * ready for getting packets. This is true if the call to
 779          * nfp_net_rx_freelist_setup() succeeds for some queues but
 780          * fails for subsequent queues.
 781          *
 782          * This should make the app exiting but better if we tell the
 783          * device first.
 784          */
 785         nfp_net_disable_queues(dev);
 786
 787         return ret;
 788 }
 789
 790 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 791 static void
 792 nfp_net_stop(struct rte_eth_dev *dev)
 793 {
 794         int i;
 795         struct nfp_net_hw *hw;
 796
 797         PMD_INIT_LOG(DEBUG, "Stop");
 798
 799         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 800
 801         nfp_net_disable_queues(dev);
 802
 803         /* Clear queues */
 804         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 805                 nfp_net_reset_tx_queue(
 806                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 807         }
 808
 809         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 810                 nfp_net_reset_rx_queue(
 811                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 812         }
 813
 814         if (hw->is_pf) {
 815                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 816                         /* Configure the physical port down */
 817                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 818                 else
 819                         nfp_eth_set_configured(dev->process_private,
 820                                                hw->pf_port_idx, 0);
 821         }
 822 }
 823
 824 /* Set the link up. */
 825 static int
 826 nfp_net_set_link_up(struct rte_eth_dev *dev)
 827 {
 828         struct nfp_net_hw *hw;
 829
 830         PMD_DRV_LOG(DEBUG, "Set link up");
 831
 832         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 833
 834         if (!hw->is_pf)
 835                 return -ENOTSUP;
 836
 837         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 838                 /* Configure the physical port down */
 839                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 840         else
 841                 return nfp_eth_set_configured(dev->process_private,
 842                                               hw->pf_port_idx, 1);
 843 }
 844
 845 /* Set the link down. */
 846 static int
 847 nfp_net_set_link_down(struct rte_eth_dev *dev)
 848 {
 849         struct nfp_net_hw *hw;
 850
 851         PMD_DRV_LOG(DEBUG, "Set link down");
 852
 853         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854
 855         if (!hw->is_pf)
 856                 return -ENOTSUP;
 857
 858         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 859                 /* Configure the physical port down */
 860                 return nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 861         else
 862                 return nfp_eth_set_configured(dev->process_private,
 863                                               hw->pf_port_idx, 0);
 864 }
 865
 866 /* Reset and stop device. The device can not be restarted. */
 867 static int
 868 nfp_net_close(struct rte_eth_dev *dev)
 869 {
 870         struct nfp_net_hw *hw;
 871         struct rte_pci_device *pci_dev;
 872         int i;
 873
 874         PMD_INIT_LOG(DEBUG, "Close");
 875
 876         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 878
 879         /*
 880          * We assume that the DPDK application is stopping all the
 881          * threads/queues before calling the device close function.
 882          */
 883
 884         nfp_net_disable_queues(dev);
 885
 886         /* Clear queues */
 887         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 888                 nfp_net_reset_tx_queue(
 889                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 890         }
 891
 892         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 893                 nfp_net_reset_rx_queue(
 894                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 895         }
 896
 897         rte_intr_disable(&pci_dev->intr_handle);
 898         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 899
 900         /* unregister callback func from eal lib */
 901         rte_intr_callback_unregister(&pci_dev->intr_handle,
 902                                      nfp_net_dev_interrupt_handler,
 903                                      (void *)dev);
 904
 905         /*
 906          * The ixgbe PMD driver disables the pcie master on the
 907          * device. The i40e does not...
 908          */
 909
 910         return 0;
 911 }
 912
 913 static int
 914 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 915 {
 916         uint32_t new_ctrl, update = 0;
 917         struct nfp_net_hw *hw;
 918         int ret;
 919
 920         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 921
 922         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923
 924         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 925                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 926                 return -ENOTSUP;
 927         }
 928
 929         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 930                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 931                 return 0;
 932         }
 933
 934         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 935         update = NFP_NET_CFG_UPDATE_GEN;
 936
 937         /*
 938          * DPDK sets promiscuous mode on just after this call assuming
 939          * it can not fail ...
 940          */
 941         ret = nfp_net_reconfig(hw, new_ctrl, update);
 942         if (ret < 0)
 943                 return ret;
 944
 945         hw->ctrl = new_ctrl;
 946
 947         return 0;
 948 }
 949
 950 static int
 951 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 952 {
 953         uint32_t new_ctrl, update = 0;
 954         struct nfp_net_hw *hw;
 955         int ret;
 956
 957         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 958
 959         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 960                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 961                 return 0;
 962         }
 963
 964         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 965         update = NFP_NET_CFG_UPDATE_GEN;
 966
 967         /*
 968          * DPDK sets promiscuous mode off just before this call
 969          * assuming it can not fail ...
 970          */
 971         ret = nfp_net_reconfig(hw, new_ctrl, update);
 972         if (ret < 0)
 973                 return ret;
 974
 975         hw->ctrl = new_ctrl;
 976
 977         return 0;
 978 }
 979
 980 /*
 981  * return 0 means link status changed, -1 means not changed
 982  *
 983  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 984  * status.
 985  */
 986 static int
 987 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 988 {
 989         struct nfp_net_hw *hw;
 990         struct rte_eth_link link;
 991         uint32_t nn_link_status;
 992         int ret;
 993
 994         static const uint32_t ls_to_ethtool[] = {
 995                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 996                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 997                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 998                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 999                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
1000                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
1001                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
1002                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
1003         };
1004
1005         PMD_DRV_LOG(DEBUG, "Link update");
1006
1007         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1008
1009         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1010
1011         memset(&link, 0, sizeof(struct rte_eth_link));
1012
1013         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1014                 link.link_status = ETH_LINK_UP;
1015
1016         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1017
1018         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1019                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1020
1021         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1022                 link.link_speed = ETH_SPEED_NUM_NONE;
1023         else
1024                 link.link_speed = ls_to_ethtool[nn_link_status];
1025
1026         ret = rte_eth_linkstatus_set(dev, &link);
1027         if (ret == 0) {
1028                 if (link.link_status)
1029                         PMD_DRV_LOG(INFO, "NIC Link is Up");
1030                 else
1031                         PMD_DRV_LOG(INFO, "NIC Link is Down");
1032         }
1033         return ret;
1034 }
1035
1036 static int
1037 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1038 {
1039         int i;
1040         struct nfp_net_hw *hw;
1041         struct rte_eth_stats nfp_dev_stats;
1042
1043         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044
1045         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1046
1047         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1048
1049         /* reading per RX ring stats */
1050         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1051                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1052                         break;
1053
1054                 nfp_dev_stats.q_ipackets[i] =
1055                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1056
1057                 nfp_dev_stats.q_ipackets[i] -=
1058                         hw->eth_stats_base.q_ipackets[i];
1059
1060                 nfp_dev_stats.q_ibytes[i] =
1061                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1062
1063                 nfp_dev_stats.q_ibytes[i] -=
1064                         hw->eth_stats_base.q_ibytes[i];
1065         }
1066
1067         /* reading per TX ring stats */
1068         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1069                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1070                         break;
1071
1072                 nfp_dev_stats.q_opackets[i] =
1073                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1074
1075                 nfp_dev_stats.q_opackets[i] -=
1076                         hw->eth_stats_base.q_opackets[i];
1077
1078                 nfp_dev_stats.q_obytes[i] =
1079                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1080
1081                 nfp_dev_stats.q_obytes[i] -=
1082                         hw->eth_stats_base.q_obytes[i];
1083         }
1084
1085         nfp_dev_stats.ipackets =
1086                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1087
1088         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1089
1090         nfp_dev_stats.ibytes =
1091                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1092
1093         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1094
1095         nfp_dev_stats.opackets =
1096                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1097
1098         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1099
1100         nfp_dev_stats.obytes =
1101                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1102
1103         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1104
1105         /* reading general device stats */
1106         nfp_dev_stats.ierrors =
1107                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1108
1109         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1110
1111         nfp_dev_stats.oerrors =
1112                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1113
1114         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1115
1116         /* RX ring mbuf allocation failures */
1117         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1118
1119         nfp_dev_stats.imissed =
1120                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1121
1122         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1123
1124         if (stats) {
1125                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1126                 return 0;
1127         }
1128         return -EINVAL;
1129 }
1130
1131 static int
1132 nfp_net_stats_reset(struct rte_eth_dev *dev)
1133 {
1134         int i;
1135         struct nfp_net_hw *hw;
1136
1137         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1138
1139         /*
1140          * hw->eth_stats_base records the per counter starting point.
1141          * Lets update it now
1142          */
1143
1144         /* reading per RX ring stats */
1145         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1146                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1147                         break;
1148
1149                 hw->eth_stats_base.q_ipackets[i] =
1150                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1151
1152                 hw->eth_stats_base.q_ibytes[i] =
1153                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1154         }
1155
1156         /* reading per TX ring stats */
1157         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1158                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1159                         break;
1160
1161                 hw->eth_stats_base.q_opackets[i] =
1162                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1163
1164                 hw->eth_stats_base.q_obytes[i] =
1165                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1166         }
1167
1168         hw->eth_stats_base.ipackets =
1169                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1170
1171         hw->eth_stats_base.ibytes =
1172                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1173
1174         hw->eth_stats_base.opackets =
1175                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1176
1177         hw->eth_stats_base.obytes =
1178                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1179
1180         /* reading general device stats */
1181         hw->eth_stats_base.ierrors =
1182                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1183
1184         hw->eth_stats_base.oerrors =
1185                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1186
1187         /* RX ring mbuf allocation failures */
1188         dev->data->rx_mbuf_alloc_failed = 0;
1189
1190         hw->eth_stats_base.imissed =
1191                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1192
1193         return 0;
1194 }
1195
1196 static int
1197 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1198 {
1199         struct nfp_net_hw *hw;
1200
1201         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1202
1203         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1204         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1205         dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1206         dev_info->max_rx_pktlen = hw->max_mtu;
1207         /* Next should change when PF support is implemented */
1208         dev_info->max_mac_addrs = 1;
1209
1210         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1211                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1212
1213         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1214                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1215                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1216                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1217
1218         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME |
1219                                      DEV_RX_OFFLOAD_RSS_HASH;
1220
1221         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1222                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1223
1224         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1225                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1226                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1227                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1228
1229         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1230                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1231
1232         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1233                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1234
1235         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1236                 .rx_thresh = {
1237                         .pthresh = DEFAULT_RX_PTHRESH,
1238                         .hthresh = DEFAULT_RX_HTHRESH,
1239                         .wthresh = DEFAULT_RX_WTHRESH,
1240                 },
1241                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1242                 .rx_drop_en = 0,
1243         };
1244
1245         dev_info->default_txconf = (struct rte_eth_txconf) {
1246                 .tx_thresh = {
1247                         .pthresh = DEFAULT_TX_PTHRESH,
1248                         .hthresh = DEFAULT_TX_HTHRESH,
1249                         .wthresh = DEFAULT_TX_WTHRESH,
1250                 },
1251                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1252                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1253         };
1254
1255         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1256                 .nb_max = NFP_NET_MAX_RX_DESC,
1257                 .nb_min = NFP_NET_MIN_RX_DESC,
1258                 .nb_align = NFP_ALIGN_RING_DESC,
1259         };
1260
1261         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1262                 .nb_max = NFP_NET_MAX_TX_DESC,
1263                 .nb_min = NFP_NET_MIN_TX_DESC,
1264                 .nb_align = NFP_ALIGN_RING_DESC,
1265                 .nb_seg_max = NFP_TX_MAX_SEG,
1266                 .nb_mtu_seg_max = NFP_TX_MAX_MTU_SEG,
1267         };
1268
1269         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1270                                            ETH_RSS_NONFRAG_IPV4_TCP |
1271                                            ETH_RSS_NONFRAG_IPV4_UDP |
1272                                            ETH_RSS_IPV6 |
1273                                            ETH_RSS_NONFRAG_IPV6_TCP |
1274                                            ETH_RSS_NONFRAG_IPV6_UDP;
1275
1276         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1277         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1278
1279         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1280                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1281                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1282
1283         return 0;
1284 }
1285
1286 static const uint32_t *
1287 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1288 {
1289         static const uint32_t ptypes[] = {
1290                 /* refers to nfp_net_set_hash() */
1291                 RTE_PTYPE_INNER_L3_IPV4,
1292                 RTE_PTYPE_INNER_L3_IPV6,
1293                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1294                 RTE_PTYPE_INNER_L4_MASK,
1295                 RTE_PTYPE_UNKNOWN
1296         };
1297
1298         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1299                 return ptypes;
1300         return NULL;
1301 }
1302
1303 static uint32_t
1304 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1305 {
1306         struct nfp_net_rxq *rxq;
1307         struct nfp_net_rx_desc *rxds;
1308         uint32_t idx;
1309         uint32_t count;
1310
1311         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1312
1313         idx = rxq->rd_p;
1314
1315         count = 0;
1316
1317         /*
1318          * Other PMDs are just checking the DD bit in intervals of 4
1319          * descriptors and counting all four if the first has the DD
1320          * bit on. Of course, this is not accurate but can be good for
1321          * performance. But ideally that should be done in descriptors
1322          * chunks belonging to the same cache line
1323          */
1324
1325         while (count < rxq->rx_count) {
1326                 rxds = &rxq->rxds[idx];
1327                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1328                         break;
1329
1330                 count++;
1331                 idx++;
1332
1333                 /* Wrapping? */
1334                 if ((idx) == rxq->rx_count)
1335                         idx = 0;
1336         }
1337
1338         return count;
1339 }
1340
1341 static int
1342 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1343 {
1344         struct rte_pci_device *pci_dev;
1345         struct nfp_net_hw *hw;
1346         int base = 0;
1347
1348         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1350
1351         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1352                 base = 1;
1353
1354         /* Make sure all updates are written before un-masking */
1355         rte_wmb();
1356         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1357                       NFP_NET_CFG_ICR_UNMASKED);
1358         return 0;
1359 }
1360
1361 static int
1362 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1363 {
1364         struct rte_pci_device *pci_dev;
1365         struct nfp_net_hw *hw;
1366         int base = 0;
1367
1368         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1369         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1370
1371         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1372                 base = 1;
1373
1374         /* Make sure all updates are written before un-masking */
1375         rte_wmb();
1376         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1377         return 0;
1378 }
1379
1380 static void
1381 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1382 {
1383         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1384         struct rte_eth_link link;
1385
1386         rte_eth_linkstatus_get(dev, &link);
1387         if (link.link_status)
1388                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1389                             dev->data->port_id, link.link_speed,
1390                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1391                             ? "full-duplex" : "half-duplex");
1392         else
1393                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1394                             dev->data->port_id);
1395
1396         PMD_DRV_LOG(INFO, "PCI Address: " PCI_PRI_FMT,
1397                     pci_dev->addr.domain, pci_dev->addr.bus,
1398                     pci_dev->addr.devid, pci_dev->addr.function);
1399 }
1400
1401 /* Interrupt configuration and handling */
1402
1403 /*
1404  * nfp_net_irq_unmask - Unmask an interrupt
1405  *
1406  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1407  * clear the ICR for the entry.
1408  */
1409 static void
1410 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1411 {
1412         struct nfp_net_hw *hw;
1413         struct rte_pci_device *pci_dev;
1414
1415         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1416         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1417
1418         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1419                 /* If MSI-X auto-masking is used, clear the entry */
1420                 rte_wmb();
1421                 rte_intr_ack(&pci_dev->intr_handle);
1422         } else {
1423                 /* Make sure all updates are written before un-masking */
1424                 rte_wmb();
1425                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1426                               NFP_NET_CFG_ICR_UNMASKED);
1427         }
1428 }
1429
1430 static void
1431 nfp_net_dev_interrupt_handler(void *param)
1432 {
1433         int64_t timeout;
1434         struct rte_eth_link link;
1435         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1436
1437         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1438
1439         rte_eth_linkstatus_get(dev, &link);
1440
1441         nfp_net_link_update(dev, 0);
1442
1443         /* likely to up */
1444         if (!link.link_status) {
1445                 /* handle it 1 sec later, wait it being stable */
1446                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1447                 /* likely to down */
1448         } else {
1449                 /* handle it 4 sec later, wait it being stable */
1450                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1451         }
1452
1453         if (rte_eal_alarm_set(timeout * 1000,
1454                               nfp_net_dev_interrupt_delayed_handler,
1455                               (void *)dev) < 0) {
1456                 PMD_INIT_LOG(ERR, "Error setting alarm");
1457                 /* Unmasking */
1458                 nfp_net_irq_unmask(dev);
1459         }
1460 }
1461
1462 /*
1463  * Interrupt handler which shall be registered for alarm callback for delayed
1464  * handling specific interrupt to wait for the stable nic state. As the NIC
1465  * interrupt state is not stable for nfp after link is just down, it needs
1466  * to wait 4 seconds to get the stable status.
1467  *
1468  * @param handle   Pointer to interrupt handle.
1469  * @param param    The address of parameter (struct rte_eth_dev *)
1470  *
1471  * @return  void
1472  */
1473 static void
1474 nfp_net_dev_interrupt_delayed_handler(void *param)
1475 {
1476         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1477
1478         nfp_net_link_update(dev, 0);
1479         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1480
1481         nfp_net_dev_link_status_print(dev);
1482
1483         /* Unmasking */
1484         nfp_net_irq_unmask(dev);
1485 }
1486
1487 static int
1488 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1489 {
1490         struct nfp_net_hw *hw;
1491
1492         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1493
1494         /* check that mtu is within the allowed range */
1495         if (mtu < RTE_ETHER_MIN_MTU || (uint32_t)mtu > hw->max_mtu)
1496                 return -EINVAL;
1497
1498         /* mtu setting is forbidden if port is started */
1499         if (dev->data->dev_started) {
1500                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1501                             dev->data->port_id);
1502                 return -EBUSY;
1503         }
1504
1505         /* switch to jumbo mode if needed */
1506         if ((uint32_t)mtu > RTE_ETHER_MAX_LEN)
1507                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1508         else
1509                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1510
1511         /* update max frame size */
1512         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1513
1514         /* writing to configuration space */
1515         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1516
1517         hw->mtu = mtu;
1518
1519         return 0;
1520 }
1521
1522 static int
1523 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1524                        uint16_t queue_idx, uint16_t nb_desc,
1525                        unsigned int socket_id,
1526                        const struct rte_eth_rxconf *rx_conf,
1527                        struct rte_mempool *mp)
1528 {
1529         const struct rte_memzone *tz;
1530         struct nfp_net_rxq *rxq;
1531         struct nfp_net_hw *hw;
1532         uint32_t rx_desc_sz;
1533
1534         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1535
1536         PMD_INIT_FUNC_TRACE();
1537
1538         /* Validating number of descriptors */
1539         rx_desc_sz = nb_desc * sizeof(struct nfp_net_rx_desc);
1540         if (rx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1541             nb_desc > NFP_NET_MAX_RX_DESC ||
1542             nb_desc < NFP_NET_MIN_RX_DESC) {
1543                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1544                 return -EINVAL;
1545         }
1546
1547         /*
1548          * Free memory prior to re-allocation if needed. This is the case after
1549          * calling nfp_net_stop
1550          */
1551         if (dev->data->rx_queues[queue_idx]) {
1552                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1553                 dev->data->rx_queues[queue_idx] = NULL;
1554         }
1555
1556         /* Allocating rx queue data structure */
1557         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1558                                  RTE_CACHE_LINE_SIZE, socket_id);
1559         if (rxq == NULL)
1560                 return -ENOMEM;
1561
1562         /* Hw queues mapping based on firmware configuration */
1563         rxq->qidx = queue_idx;
1564         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1565         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1566         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1567         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1568
1569         /*
1570          * Tracking mbuf size for detecting a potential mbuf overflow due to
1571          * RX offset
1572          */
1573         rxq->mem_pool = mp;
1574         rxq->mbuf_size = rxq->mem_pool->elt_size;
1575         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1576         hw->flbufsz = rxq->mbuf_size;
1577
1578         rxq->rx_count = nb_desc;
1579         rxq->port_id = dev->data->port_id;
1580         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1581         rxq->drop_en = rx_conf->rx_drop_en;
1582
1583         /*
1584          * Allocate RX ring hardware descriptors. A memzone large enough to
1585          * handle the maximum ring size is allocated in order to allow for
1586          * resizing in later calls to the queue setup function.
1587          */
1588         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1589                                    sizeof(struct nfp_net_rx_desc) *
1590                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1591                                    socket_id);
1592
1593         if (tz == NULL) {
1594                 PMD_DRV_LOG(ERR, "Error allocating rx dma");
1595                 nfp_net_rx_queue_release(rxq);
1596                 return -ENOMEM;
1597         }
1598
1599         /* Saving physical and virtual addresses for the RX ring */
1600         rxq->dma = (uint64_t)tz->iova;
1601         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1602
1603         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1604         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1605                                          sizeof(*rxq->rxbufs) * nb_desc,
1606                                          RTE_CACHE_LINE_SIZE, socket_id);
1607         if (rxq->rxbufs == NULL) {
1608                 nfp_net_rx_queue_release(rxq);
1609                 return -ENOMEM;
1610         }
1611
1612         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1613                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1614
1615         nfp_net_reset_rx_queue(rxq);
1616
1617         dev->data->rx_queues[queue_idx] = rxq;
1618         rxq->hw = hw;
1619
1620         /*
1621          * Telling the HW about the physical address of the RX ring and number
1622          * of descriptors in log2 format
1623          */
1624         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1625         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1626
1627         return 0;
1628 }
1629
1630 static int
1631 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1632 {
1633         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1634         uint64_t dma_addr;
1635         unsigned i;
1636
1637         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1638                    rxq->rx_count);
1639
1640         for (i = 0; i < rxq->rx_count; i++) {
1641                 struct nfp_net_rx_desc *rxd;
1642                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1643
1644                 if (mbuf == NULL) {
1645                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1646                                 (unsigned)rxq->qidx);
1647                         return -ENOMEM;
1648                 }
1649
1650                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1651
1652                 rxd = &rxq->rxds[i];
1653                 rxd->fld.dd = 0;
1654                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1655                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1656                 rxe[i].mbuf = mbuf;
1657                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1658         }
1659
1660         /* Make sure all writes are flushed before telling the hardware */
1661         rte_wmb();
1662
1663         /* Not advertising the whole ring as the firmware gets confused if so */
1664         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1665                    rxq->rx_count - 1);
1666
1667         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1668
1669         return 0;
1670 }
1671
1672 static int
1673 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1674                        uint16_t nb_desc, unsigned int socket_id,
1675                        const struct rte_eth_txconf *tx_conf)
1676 {
1677         const struct rte_memzone *tz;
1678         struct nfp_net_txq *txq;
1679         uint16_t tx_free_thresh;
1680         struct nfp_net_hw *hw;
1681         uint32_t tx_desc_sz;
1682
1683         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684
1685         PMD_INIT_FUNC_TRACE();
1686
1687         /* Validating number of descriptors */
1688         tx_desc_sz = nb_desc * sizeof(struct nfp_net_tx_desc);
1689         if (tx_desc_sz % NFP_ALIGN_RING_DESC != 0 ||
1690             nb_desc > NFP_NET_MAX_TX_DESC ||
1691             nb_desc < NFP_NET_MIN_TX_DESC) {
1692                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1693                 return -EINVAL;
1694         }
1695
1696         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1697                                     tx_conf->tx_free_thresh :
1698                                     DEFAULT_TX_FREE_THRESH);
1699
1700         if (tx_free_thresh > (nb_desc)) {
1701                 PMD_DRV_LOG(ERR,
1702                         "tx_free_thresh must be less than the number of TX "
1703                         "descriptors. (tx_free_thresh=%u port=%d "
1704                         "queue=%d)", (unsigned int)tx_free_thresh,
1705                         dev->data->port_id, (int)queue_idx);
1706                 return -(EINVAL);
1707         }
1708
1709         /*
1710          * Free memory prior to re-allocation if needed. This is the case after
1711          * calling nfp_net_stop
1712          */
1713         if (dev->data->tx_queues[queue_idx]) {
1714                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1715                            queue_idx);
1716                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1717                 dev->data->tx_queues[queue_idx] = NULL;
1718         }
1719
1720         /* Allocating tx queue data structure */
1721         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1722                                  RTE_CACHE_LINE_SIZE, socket_id);
1723         if (txq == NULL) {
1724                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1725                 return -ENOMEM;
1726         }
1727
1728         /*
1729          * Allocate TX ring hardware descriptors. A memzone large enough to
1730          * handle the maximum ring size is allocated in order to allow for
1731          * resizing in later calls to the queue setup function.
1732          */
1733         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1734                                    sizeof(struct nfp_net_tx_desc) *
1735                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1736                                    socket_id);
1737         if (tz == NULL) {
1738                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1739                 nfp_net_tx_queue_release(txq);
1740                 return -ENOMEM;
1741         }
1742
1743         txq->tx_count = nb_desc;
1744         txq->tx_free_thresh = tx_free_thresh;
1745         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1746         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1747         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1748
1749         /* queue mapping based on firmware configuration */
1750         txq->qidx = queue_idx;
1751         txq->tx_qcidx = queue_idx * hw->stride_tx;
1752         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1753
1754         txq->port_id = dev->data->port_id;
1755
1756         /* Saving physical and virtual addresses for the TX ring */
1757         txq->dma = (uint64_t)tz->iova;
1758         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1759
1760         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1761         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1762                                          sizeof(*txq->txbufs) * nb_desc,
1763                                          RTE_CACHE_LINE_SIZE, socket_id);
1764         if (txq->txbufs == NULL) {
1765                 nfp_net_tx_queue_release(txq);
1766                 return -ENOMEM;
1767         }
1768         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1769                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1770
1771         nfp_net_reset_tx_queue(txq);
1772
1773         dev->data->tx_queues[queue_idx] = txq;
1774         txq->hw = hw;
1775
1776         /*
1777          * Telling the HW about the physical address of the TX ring and number
1778          * of descriptors in log2 format
1779          */
1780         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1781         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1782
1783         return 0;
1784 }
1785
1786 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1787 static inline void
1788 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1789                struct rte_mbuf *mb)
1790 {
1791         uint64_t ol_flags;
1792         struct nfp_net_hw *hw = txq->hw;
1793
1794         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1795                 goto clean_txd;
1796
1797         ol_flags = mb->ol_flags;
1798
1799         if (!(ol_flags & PKT_TX_TCP_SEG))
1800                 goto clean_txd;
1801
1802         txd->l3_offset = mb->l2_len;
1803         txd->l4_offset = mb->l2_len + mb->l3_len;
1804         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1805         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1806         txd->flags = PCIE_DESC_TX_LSO;
1807         return;
1808
1809 clean_txd:
1810         txd->flags = 0;
1811         txd->l3_offset = 0;
1812         txd->l4_offset = 0;
1813         txd->lso_hdrlen = 0;
1814         txd->mss = 0;
1815 }
1816
1817 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1818 static inline void
1819 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1820                  struct rte_mbuf *mb)
1821 {
1822         uint64_t ol_flags;
1823         struct nfp_net_hw *hw = txq->hw;
1824
1825         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1826                 return;
1827
1828         ol_flags = mb->ol_flags;
1829
1830         /* IPv6 does not need checksum */
1831         if (ol_flags & PKT_TX_IP_CKSUM)
1832                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1833
1834         switch (ol_flags & PKT_TX_L4_MASK) {
1835         case PKT_TX_UDP_CKSUM:
1836                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1837                 break;
1838         case PKT_TX_TCP_CKSUM:
1839                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1840                 break;
1841         }
1842
1843         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1844                 txd->flags |= PCIE_DESC_TX_CSUM;
1845 }
1846
1847 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1848 static inline void
1849 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1850                  struct rte_mbuf *mb)
1851 {
1852         struct nfp_net_hw *hw = rxq->hw;
1853
1854         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1855                 return;
1856
1857         /* If IPv4 and IP checksum error, fail */
1858         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1859             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1860                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1861         else
1862                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1863
1864         /* If neither UDP nor TCP return */
1865         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1866             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1867                 return;
1868
1869         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1870                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1871         else
1872                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1873 }
1874
1875 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1876 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1877
1878 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1879
1880 /*
1881  * nfp_net_set_hash - Set mbuf hash data
1882  *
1883  * The RSS hash and hash-type are pre-pended to the packet data.
1884  * Extract and decode it and set the mbuf fields.
1885  */
1886 static inline void
1887 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1888                  struct rte_mbuf *mbuf)
1889 {
1890         struct nfp_net_hw *hw = rxq->hw;
1891         uint8_t *meta_offset;
1892         uint32_t meta_info;
1893         uint32_t hash = 0;
1894         uint32_t hash_type = 0;
1895
1896         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1897                 return;
1898
1899         /* this is true for new firmwares */
1900         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1901             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1902              NFP_DESC_META_LEN(rxd))) {
1903                 /*
1904                  * new metadata api:
1905                  * <----  32 bit  ----->
1906                  * m    field type word
1907                  * e     data field #2
1908                  * t     data field #1
1909                  * a     data field #0
1910                  * ====================
1911                  *    packet data
1912                  *
1913                  * Field type word contains up to 8 4bit field types
1914                  * A 4bit field type refers to a data field word
1915                  * A data field word can have several 4bit field types
1916                  */
1917                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1918                 meta_offset -= NFP_DESC_META_LEN(rxd);
1919                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1920                 meta_offset += 4;
1921                 /* NFP PMD just supports metadata for hashing */
1922                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1923                 case NFP_NET_META_HASH:
1924                         /* next field type is about the hash type */
1925                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1926                         /* hash value is in the data field */
1927                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1928                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1929                         break;
1930                 default:
1931                         /* Unsupported metadata can be a performance issue */
1932                         return;
1933                 }
1934         } else {
1935                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1936                         return;
1937
1938                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1939                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1940         }
1941
1942         mbuf->hash.rss = hash;
1943         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1944
1945         switch (hash_type) {
1946         case NFP_NET_RSS_IPV4:
1947                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1948                 break;
1949         case NFP_NET_RSS_IPV6:
1950                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1951                 break;
1952         case NFP_NET_RSS_IPV6_EX:
1953                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1954                 break;
1955         case NFP_NET_RSS_IPV4_TCP:
1956                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1957                 break;
1958         case NFP_NET_RSS_IPV6_TCP:
1959                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1960                 break;
1961         case NFP_NET_RSS_IPV4_UDP:
1962                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1963                 break;
1964         case NFP_NET_RSS_IPV6_UDP:
1965                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1966                 break;
1967         default:
1968                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1969         }
1970 }
1971
1972 static inline void
1973 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1974 {
1975         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1976 }
1977
1978 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1979
1980 /*
1981  * RX path design:
1982  *
1983  * There are some decisions to take:
1984  * 1) How to check DD RX descriptors bit
1985  * 2) How and when to allocate new mbufs
1986  *
1987  * Current implementation checks just one single DD bit each loop. As each
1988  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1989  * a single cache line instead. Tests with this change have not shown any
1990  * performance improvement but it requires further investigation. For example,
1991  * depending on which descriptor is next, the number of descriptors could be
1992  * less than 8 for just checking those in the same cache line. This implies
1993  * extra work which could be counterproductive by itself. Indeed, last firmware
1994  * changes are just doing this: writing several descriptors with the DD bit
1995  * for saving PCIe bandwidth and DMA operations from the NFP.
1996  *
1997  * Mbuf allocation is done when a new packet is received. Then the descriptor
1998  * is automatically linked with the new mbuf and the old one is given to the
1999  * user. The main drawback with this design is mbuf allocation is heavier than
2000  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
2001  * cache point of view it does not seem allocating the mbuf early on as we are
2002  * doing now have any benefit at all. Again, tests with this change have not
2003  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
2004  * so looking at the implications of this type of allocation should be studied
2005  * deeply
2006  */
2007
2008 static uint16_t
2009 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2010 {
2011         struct nfp_net_rxq *rxq;
2012         struct nfp_net_rx_desc *rxds;
2013         struct nfp_net_rx_buff *rxb;
2014         struct nfp_net_hw *hw;
2015         struct rte_mbuf *mb;
2016         struct rte_mbuf *new_mb;
2017         uint16_t nb_hold;
2018         uint64_t dma_addr;
2019         int avail;
2020
2021         rxq = rx_queue;
2022         if (unlikely(rxq == NULL)) {
2023                 /*
2024                  * DPDK just checks the queue is lower than max queues
2025                  * enabled. But the queue needs to be configured
2026                  */
2027                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
2028                 return -EINVAL;
2029         }
2030
2031         hw = rxq->hw;
2032         avail = 0;
2033         nb_hold = 0;
2034
2035         while (avail < nb_pkts) {
2036                 rxb = &rxq->rxbufs[rxq->rd_p];
2037                 if (unlikely(rxb == NULL)) {
2038                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2039                         break;
2040                 }
2041
2042                 rxds = &rxq->rxds[rxq->rd_p];
2043                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2044                         break;
2045
2046                 /*
2047                  * Memory barrier to ensure that we won't do other
2048                  * reads before the DD bit.
2049                  */
2050                 rte_rmb();
2051
2052                 /*
2053                  * We got a packet. Let's alloc a new mbuf for refilling the
2054                  * free descriptor ring as soon as possible
2055                  */
2056                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2057                 if (unlikely(new_mb == NULL)) {
2058                         RTE_LOG_DP(DEBUG, PMD,
2059                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2060                                 rxq->port_id, (unsigned int)rxq->qidx);
2061                         nfp_net_mbuf_alloc_failed(rxq);
2062                         break;
2063                 }
2064
2065                 nb_hold++;
2066
2067                 /*
2068                  * Grab the mbuf and refill the descriptor with the
2069                  * previously allocated mbuf
2070                  */
2071                 mb = rxb->mbuf;
2072                 rxb->mbuf = new_mb;
2073
2074                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2075                            rxds->rxd.data_len, rxq->mbuf_size);
2076
2077                 /* Size of this segment */
2078                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2079                 /* Size of the whole packet. We just support 1 segment */
2080                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2081
2082                 if (unlikely((mb->data_len + hw->rx_offset) >
2083                              rxq->mbuf_size)) {
2084                         /*
2085                          * This should not happen and the user has the
2086                          * responsibility of avoiding it. But we have
2087                          * to give some info about the error
2088                          */
2089                         RTE_LOG_DP(ERR, PMD,
2090                                 "mbuf overflow likely due to the RX offset.\n"
2091                                 "\t\tYour mbuf size should have extra space for"
2092                                 " RX offset=%u bytes.\n"
2093                                 "\t\tCurrently you just have %u bytes available"
2094                                 " but the received packet is %u bytes long",
2095                                 hw->rx_offset,
2096                                 rxq->mbuf_size - hw->rx_offset,
2097                                 mb->data_len);
2098                         return -EINVAL;
2099                 }
2100
2101                 /* Filling the received mbuf with packet info */
2102                 if (hw->rx_offset)
2103                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2104                 else
2105                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2106                                        NFP_DESC_META_LEN(rxds);
2107
2108                 /* No scatter mode supported */
2109                 mb->nb_segs = 1;
2110                 mb->next = NULL;
2111
2112                 mb->port = rxq->port_id;
2113
2114                 /* Checking the RSS flag */
2115                 nfp_net_set_hash(rxq, rxds, mb);
2116
2117                 /* Checking the checksum flag */
2118                 nfp_net_rx_cksum(rxq, rxds, mb);
2119
2120                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2121                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2122                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2123                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2124                 }
2125
2126                 /* Adding the mbuf to the mbuf array passed by the app */
2127                 rx_pkts[avail++] = mb;
2128
2129                 /* Now resetting and updating the descriptor */
2130                 rxds->vals[0] = 0;
2131                 rxds->vals[1] = 0;
2132                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2133                 rxds->fld.dd = 0;
2134                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2135                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2136
2137                 rxq->rd_p++;
2138                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2139                         rxq->rd_p = 0;
2140         }
2141
2142         if (nb_hold == 0)
2143                 return nb_hold;
2144
2145         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2146                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2147
2148         nb_hold += rxq->nb_rx_hold;
2149
2150         /*
2151          * FL descriptors needs to be written before incrementing the
2152          * FL queue WR pointer
2153          */
2154         rte_wmb();
2155         if (nb_hold > rxq->rx_free_thresh) {
2156                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2157                            rxq->port_id, (unsigned int)rxq->qidx,
2158                            (unsigned)nb_hold, (unsigned)avail);
2159                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2160                 nb_hold = 0;
2161         }
2162         rxq->nb_rx_hold = nb_hold;
2163
2164         return avail;
2165 }
2166
2167 /*
2168  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2169  * status
2170  * @txq: TX queue to work with
2171  * Returns number of descriptors freed
2172  */
2173 int
2174 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2175 {
2176         uint32_t qcp_rd_p;
2177         int todo;
2178
2179         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2180                    " status", txq->qidx);
2181
2182         /* Work out how many packets have been sent */
2183         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2184
2185         if (qcp_rd_p == txq->rd_p) {
2186                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2187                            "packets (%u, %u)", txq->qidx,
2188                            qcp_rd_p, txq->rd_p);
2189                 return 0;
2190         }
2191
2192         if (qcp_rd_p > txq->rd_p)
2193                 todo = qcp_rd_p - txq->rd_p;
2194         else
2195                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2196
2197         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2198                    qcp_rd_p, txq->rd_p, txq->rd_p);
2199
2200         if (todo == 0)
2201                 return todo;
2202
2203         txq->rd_p += todo;
2204         if (unlikely(txq->rd_p >= txq->tx_count))
2205                 txq->rd_p -= txq->tx_count;
2206
2207         return todo;
2208 }
2209
2210 /* Leaving always free descriptors for avoiding wrapping confusion */
2211 static inline
2212 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2213 {
2214         if (txq->wr_p >= txq->rd_p)
2215                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2216         else
2217                 return txq->rd_p - txq->wr_p - 8;
2218 }
2219
2220 /*
2221  * nfp_net_txq_full - Check if the TX queue free descriptors
2222  * is below tx_free_threshold
2223  *
2224  * @txq: TX queue to check
2225  *
2226  * This function uses the host copy* of read/write pointers
2227  */
2228 static inline
2229 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2230 {
2231         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2232 }
2233
2234 static uint16_t
2235 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2236 {
2237         struct nfp_net_txq *txq;
2238         struct nfp_net_hw *hw;
2239         struct nfp_net_tx_desc *txds, txd;
2240         struct rte_mbuf *pkt;
2241         uint64_t dma_addr;
2242         int pkt_size, dma_size;
2243         uint16_t free_descs, issued_descs;
2244         struct rte_mbuf **lmbuf;
2245         int i;
2246
2247         txq = tx_queue;
2248         hw = txq->hw;
2249         txds = &txq->txds[txq->wr_p];
2250
2251         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2252                    txq->qidx, txq->wr_p, nb_pkts);
2253
2254         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2255                 nfp_net_tx_free_bufs(txq);
2256
2257         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2258         if (unlikely(free_descs == 0))
2259                 return 0;
2260
2261         pkt = *tx_pkts;
2262
2263         i = 0;
2264         issued_descs = 0;
2265         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2266                    txq->qidx, nb_pkts);
2267         /* Sending packets */
2268         while ((i < nb_pkts) && free_descs) {
2269                 /* Grabbing the mbuf linked to the current descriptor */
2270                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2271                 /* Warming the cache for releasing the mbuf later on */
2272                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2273
2274                 pkt = *(tx_pkts + i);
2275
2276                 if (unlikely((pkt->nb_segs > 1) &&
2277                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2278                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2279                         rte_panic("Multisegment packet unsupported\n");
2280                 }
2281
2282                 /* Checking if we have enough descriptors */
2283                 if (unlikely(pkt->nb_segs > free_descs))
2284                         goto xmit_end;
2285
2286                 /*
2287                  * Checksum and VLAN flags just in the first descriptor for a
2288                  * multisegment packet, but TSO info needs to be in all of them.
2289                  */
2290                 txd.data_len = pkt->pkt_len;
2291                 nfp_net_tx_tso(txq, &txd, pkt);
2292                 nfp_net_tx_cksum(txq, &txd, pkt);
2293
2294                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2295                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2296                         txd.flags |= PCIE_DESC_TX_VLAN;
2297                         txd.vlan = pkt->vlan_tci;
2298                 }
2299
2300                 /*
2301                  * mbuf data_len is the data in one segment and pkt_len data
2302                  * in the whole packet. When the packet is just one segment,
2303                  * then data_len = pkt_len
2304                  */
2305                 pkt_size = pkt->pkt_len;
2306
2307                 while (pkt) {
2308                         /* Copying TSO, VLAN and cksum info */
2309                         *txds = txd;
2310
2311                         /* Releasing mbuf used by this descriptor previously*/
2312                         if (*lmbuf)
2313                                 rte_pktmbuf_free_seg(*lmbuf);
2314
2315                         /*
2316                          * Linking mbuf with descriptor for being released
2317                          * next time descriptor is used
2318                          */
2319                         *lmbuf = pkt;
2320
2321                         dma_size = pkt->data_len;
2322                         dma_addr = rte_mbuf_data_iova(pkt);
2323                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2324                                    "%" PRIx64 "", dma_addr);
2325
2326                         /* Filling descriptors fields */
2327                         txds->dma_len = dma_size;
2328                         txds->data_len = txd.data_len;
2329                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2330                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2331                         ASSERT(free_descs > 0);
2332                         free_descs--;
2333
2334                         txq->wr_p++;
2335                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2336                                 txq->wr_p = 0;
2337
2338                         pkt_size -= dma_size;
2339
2340                         /*
2341                          * Making the EOP, packets with just one segment
2342                          * the priority
2343                          */
2344                         if (likely(!pkt_size))
2345                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2346                         else
2347                                 txds->offset_eop = 0;
2348
2349                         pkt = pkt->next;
2350                         /* Referencing next free TX descriptor */
2351                         txds = &txq->txds[txq->wr_p];
2352                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2353                         issued_descs++;
2354                 }
2355                 i++;
2356         }
2357
2358 xmit_end:
2359         /* Increment write pointers. Force memory write before we let HW know */
2360         rte_wmb();
2361         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2362
2363         return i;
2364 }
2365
2366 static int
2367 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2368 {
2369         uint32_t new_ctrl, update;
2370         struct nfp_net_hw *hw;
2371         int ret;
2372
2373         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374         new_ctrl = 0;
2375
2376         /* Enable vlan strip if it is not configured yet */
2377         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2378             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2379                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2380
2381         /* Disable vlan strip just if it is configured */
2382         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2383             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2384                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2385
2386         if (new_ctrl == 0)
2387                 return 0;
2388
2389         update = NFP_NET_CFG_UPDATE_GEN;
2390
2391         ret = nfp_net_reconfig(hw, new_ctrl, update);
2392         if (!ret)
2393                 hw->ctrl = new_ctrl;
2394
2395         return ret;
2396 }
2397
2398 static int
2399 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2400                     struct rte_eth_rss_reta_entry64 *reta_conf,
2401                     uint16_t reta_size)
2402 {
2403         uint32_t reta, mask;
2404         int i, j;
2405         int idx, shift;
2406         struct nfp_net_hw *hw =
2407                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2408
2409         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2410                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2411                         "(%d) doesn't match the number hardware can supported "
2412                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2413                 return -EINVAL;
2414         }
2415
2416         /*
2417          * Update Redirection Table. There are 128 8bit-entries which can be
2418          * manage as 32 32bit-entries
2419          */
2420         for (i = 0; i < reta_size; i += 4) {
2421                 /* Handling 4 RSS entries per loop */
2422                 idx = i / RTE_RETA_GROUP_SIZE;
2423                 shift = i % RTE_RETA_GROUP_SIZE;
2424                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2425
2426                 if (!mask)
2427                         continue;
2428
2429                 reta = 0;
2430                 /* If all 4 entries were set, don't need read RETA register */
2431                 if (mask != 0xF)
2432                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2433
2434                 for (j = 0; j < 4; j++) {
2435                         if (!(mask & (0x1 << j)))
2436                                 continue;
2437                         if (mask != 0xF)
2438                                 /* Clearing the entry bits */
2439                                 reta &= ~(0xFF << (8 * j));
2440                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2441                 }
2442                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2443                               reta);
2444         }
2445         return 0;
2446 }
2447
2448 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2449 static int
2450 nfp_net_reta_update(struct rte_eth_dev *dev,
2451                     struct rte_eth_rss_reta_entry64 *reta_conf,
2452                     uint16_t reta_size)
2453 {
2454         struct nfp_net_hw *hw =
2455                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456         uint32_t update;
2457         int ret;
2458
2459         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2460                 return -EINVAL;
2461
2462         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2463         if (ret != 0)
2464                 return ret;
2465
2466         update = NFP_NET_CFG_UPDATE_RSS;
2467
2468         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2469                 return -EIO;
2470
2471         return 0;
2472 }
2473
2474  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2475 static int
2476 nfp_net_reta_query(struct rte_eth_dev *dev,
2477                    struct rte_eth_rss_reta_entry64 *reta_conf,
2478                    uint16_t reta_size)
2479 {
2480         uint8_t i, j, mask;
2481         int idx, shift;
2482         uint32_t reta;
2483         struct nfp_net_hw *hw;
2484
2485         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486
2487         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2488                 return -EINVAL;
2489
2490         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2491                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2492                         "(%d) doesn't match the number hardware can supported "
2493                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2494                 return -EINVAL;
2495         }
2496
2497         /*
2498          * Reading Redirection Table. There are 128 8bit-entries which can be
2499          * manage as 32 32bit-entries
2500          */
2501         for (i = 0; i < reta_size; i += 4) {
2502                 /* Handling 4 RSS entries per loop */
2503                 idx = i / RTE_RETA_GROUP_SIZE;
2504                 shift = i % RTE_RETA_GROUP_SIZE;
2505                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2506
2507                 if (!mask)
2508                         continue;
2509
2510                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2511                                     shift);
2512                 for (j = 0; j < 4; j++) {
2513                         if (!(mask & (0x1 << j)))
2514                                 continue;
2515                         reta_conf[idx].reta[shift + j] =
2516                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2517                 }
2518         }
2519         return 0;
2520 }
2521
2522 static int
2523 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2524                         struct rte_eth_rss_conf *rss_conf)
2525 {
2526         struct nfp_net_hw *hw;
2527         uint64_t rss_hf;
2528         uint32_t cfg_rss_ctrl = 0;
2529         uint8_t key;
2530         int i;
2531
2532         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2533
2534         /* Writing the key byte a byte */
2535         for (i = 0; i < rss_conf->rss_key_len; i++) {
2536                 memcpy(&key, &rss_conf->rss_key[i], 1);
2537                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2538         }
2539
2540         rss_hf = rss_conf->rss_hf;
2541
2542         if (rss_hf & ETH_RSS_IPV4)
2543                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2544
2545         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2546                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2547
2548         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2549                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2550
2551         if (rss_hf & ETH_RSS_IPV6)
2552                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2553
2554         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2555                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2556
2557         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2558                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2559
2560         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2561         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2562
2563         /* configuring where to apply the RSS hash */
2564         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2565
2566         /* Writing the key size */
2567         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2568
2569         return 0;
2570 }
2571
2572 static int
2573 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2574                         struct rte_eth_rss_conf *rss_conf)
2575 {
2576         uint32_t update;
2577         uint64_t rss_hf;
2578         struct nfp_net_hw *hw;
2579
2580         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581
2582         rss_hf = rss_conf->rss_hf;
2583
2584         /* Checking if RSS is enabled */
2585         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2586                 if (rss_hf != 0) { /* Enable RSS? */
2587                         PMD_DRV_LOG(ERR, "RSS unsupported");
2588                         return -EINVAL;
2589                 }
2590                 return 0; /* Nothing to do */
2591         }
2592
2593         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2594                 PMD_DRV_LOG(ERR, "hash key too long");
2595                 return -EINVAL;
2596         }
2597
2598         nfp_net_rss_hash_write(dev, rss_conf);
2599
2600         update = NFP_NET_CFG_UPDATE_RSS;
2601
2602         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2603                 return -EIO;
2604
2605         return 0;
2606 }
2607
2608 static int
2609 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2610                           struct rte_eth_rss_conf *rss_conf)
2611 {
2612         uint64_t rss_hf;
2613         uint32_t cfg_rss_ctrl;
2614         uint8_t key;
2615         int i;
2616         struct nfp_net_hw *hw;
2617
2618         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2619
2620         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2621                 return -EINVAL;
2622
2623         rss_hf = rss_conf->rss_hf;
2624         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2625
2626         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2627                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2628
2629         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2630                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2631
2632         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2633                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2634
2635         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2636                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2637
2638         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2639                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2640
2641         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2642                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2643
2644         /* Propagate current RSS hash functions to caller */
2645         rss_conf->rss_hf = rss_hf;
2646
2647         /* Reading the key size */
2648         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2649
2650         /* Reading the key byte a byte */
2651         for (i = 0; i < rss_conf->rss_key_len; i++) {
2652                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2653                 memcpy(&rss_conf->rss_key[i], &key, 1);
2654         }
2655
2656         return 0;
2657 }
2658
2659 static int
2660 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2661 {
2662         struct rte_eth_conf *dev_conf;
2663         struct rte_eth_rss_conf rss_conf;
2664         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2665         uint16_t rx_queues = dev->data->nb_rx_queues;
2666         uint16_t queue;
2667         int i, j, ret;
2668
2669         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2670                 rx_queues);
2671
2672         nfp_reta_conf[0].mask = ~0x0;
2673         nfp_reta_conf[1].mask = ~0x0;
2674
2675         queue = 0;
2676         for (i = 0; i < 0x40; i += 8) {
2677                 for (j = i; j < (i + 8); j++) {
2678                         nfp_reta_conf[0].reta[j] = queue;
2679                         nfp_reta_conf[1].reta[j] = queue++;
2680                         queue %= rx_queues;
2681                 }
2682         }
2683         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2684         if (ret != 0)
2685                 return ret;
2686
2687         dev_conf = &dev->data->dev_conf;
2688         if (!dev_conf) {
2689                 PMD_DRV_LOG(INFO, "wrong rss conf");
2690                 return -EINVAL;
2691         }
2692         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2693
2694         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2695
2696         return ret;
2697 }
2698
2699
2700 /* Initialise and register driver with DPDK Application */
2701 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2702         .dev_configure          = nfp_net_configure,
2703         .dev_start              = nfp_net_start,
2704         .dev_stop               = nfp_net_stop,
2705         .dev_set_link_up        = nfp_net_set_link_up,
2706         .dev_set_link_down      = nfp_net_set_link_down,
2707         .dev_close              = nfp_net_close,
2708         .promiscuous_enable     = nfp_net_promisc_enable,
2709         .promiscuous_disable    = nfp_net_promisc_disable,
2710         .link_update            = nfp_net_link_update,
2711         .stats_get              = nfp_net_stats_get,
2712         .stats_reset            = nfp_net_stats_reset,
2713         .dev_infos_get          = nfp_net_infos_get,
2714         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2715         .mtu_set                = nfp_net_dev_mtu_set,
2716         .mac_addr_set           = nfp_set_mac_addr,
2717         .vlan_offload_set       = nfp_net_vlan_offload_set,
2718         .reta_update            = nfp_net_reta_update,
2719         .reta_query             = nfp_net_reta_query,
2720         .rss_hash_update        = nfp_net_rss_hash_update,
2721         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2722         .rx_queue_setup         = nfp_net_rx_queue_setup,
2723         .rx_queue_release       = nfp_net_rx_queue_release,
2724         .tx_queue_setup         = nfp_net_tx_queue_setup,
2725         .tx_queue_release       = nfp_net_tx_queue_release,
2726         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2727         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2728 };
2729
2730 /*
2731  * All eth_dev created got its private data, but before nfp_net_init, that
2732  * private data is referencing private data for all the PF ports. This is due
2733  * to how the vNIC bars are mapped based on first port, so all ports need info
2734  * about port 0 private data. Inside nfp_net_init the private data pointer is
2735  * changed to the right address for each port once the bars have been mapped.
2736  *
2737  * This functions helps to find out which port and therefore which offset
2738  * inside the private data array to use.
2739  */
2740 static int
2741 get_pf_port_number(char *name)
2742 {
2743         char *pf_str = name;
2744         int size = 0;
2745
2746         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2747                 pf_str++;
2748
2749         if (size == 30)
2750                 /*
2751                  * This should not happen at all and it would mean major
2752                  * implementation fault.
2753                  */
2754                 rte_panic("nfp_net: problem with pf device name\n");
2755
2756         /* Expecting _portX with X within [0,7] */
2757         pf_str += 5;
2758
2759         return (int)strtol(pf_str, NULL, 10);
2760 }
2761
2762 static int
2763 nfp_net_init(struct rte_eth_dev *eth_dev)
2764 {
2765         struct rte_pci_device *pci_dev;
2766         struct nfp_net_hw *hw, *hwport0;
2767
2768         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2769         uint32_t start_q;
2770         int stride = 4;
2771         int port = 0;
2772         int err;
2773
2774         PMD_INIT_FUNC_TRACE();
2775
2776         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2777
2778         /* NFP can not handle DMA addresses requiring more than 40 bits */
2779         if (rte_mem_check_dma_mask(40)) {
2780                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2781                                    pci_dev->device.name);
2782                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2783                 return -ENODEV;
2784         };
2785
2786         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2787             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2788                 port = get_pf_port_number(eth_dev->data->name);
2789                 if (port < 0 || port > 7) {
2790                         PMD_DRV_LOG(ERR, "Port value is wrong");
2791                         return -ENODEV;
2792                 }
2793
2794                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2795
2796                 /* This points to port 0 private data */
2797                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2798
2799                 /* This points to the specific port private data */
2800                 hw = &hwport0[port];
2801         } else {
2802                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2803                 hwport0 = 0;
2804         }
2805
2806         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2807         eth_dev->rx_queue_count = nfp_net_rx_queue_count;
2808         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2809         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2810
2811         /* For secondary processes, the primary has done all the work */
2812         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2813                 return 0;
2814
2815         rte_eth_copy_pci_info(eth_dev, pci_dev);
2816
2817         hw->device_id = pci_dev->id.device_id;
2818         hw->vendor_id = pci_dev->id.vendor_id;
2819         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2820         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2821
2822         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2823                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2824                      pci_dev->addr.domain, pci_dev->addr.bus,
2825                      pci_dev->addr.devid, pci_dev->addr.function);
2826
2827         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2828         if (hw->ctrl_bar == NULL) {
2829                 PMD_DRV_LOG(ERR,
2830                         "hw->ctrl_bar is NULL. BAR0 not configured");
2831                 return -ENODEV;
2832         }
2833
2834         if (hw->is_pf && port == 0) {
2835                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2836                                              hw->total_ports * 32768,
2837                                              &hw->ctrl_area);
2838                 if (!hw->ctrl_bar) {
2839                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2840                         return -EIO;
2841                 }
2842
2843                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2844         }
2845
2846         if (port > 0) {
2847                 if (!hwport0->ctrl_bar)
2848                         return -ENODEV;
2849
2850                 /* address based on port0 offset */
2851                 hw->ctrl_bar = hwport0->ctrl_bar +
2852                                (port * NFP_PF_CSR_SLICE_SIZE);
2853         }
2854
2855         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2856
2857         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2858         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2859
2860         /* Work out where in the BAR the queues start. */
2861         switch (pci_dev->id.device_id) {
2862         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2863         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2864         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2865                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2866                 tx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2867                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2868                 rx_bar_off = (uint64_t)start_q * NFP_QCP_QUEUE_ADDR_SZ;
2869                 break;
2870         default:
2871                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2872                 err = -ENODEV;
2873                 goto dev_err_ctrl_map;
2874         }
2875
2876         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2877         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2878
2879         if (hw->is_pf && port == 0) {
2880                 /* configure access to tx/rx vNIC BARs */
2881                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2882                                                       NFP_PCIE_QUEUE(0),
2883                                                       NFP_QCP_QUEUE_AREA_SZ,
2884                                                       &hw->hwqueues_area);
2885
2886                 if (!hwport0->hw_queues) {
2887                         printf("nfp_rtsym_map fails for net.qc");
2888                         err = -EIO;
2889                         goto dev_err_ctrl_map;
2890                 }
2891
2892                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2893                                     hwport0->hw_queues);
2894         }
2895
2896         if (hw->is_pf) {
2897                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2898                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2899                 eth_dev->data->dev_private = hw;
2900         } else {
2901                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2902                              tx_bar_off;
2903                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2904                              rx_bar_off;
2905         }
2906
2907         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2908                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2909
2910         nfp_net_cfg_queue_setup(hw);
2911
2912         /* Get some of the read-only fields from the config BAR */
2913         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2914         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2915         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2916         hw->mtu = RTE_ETHER_MTU;
2917
2918         /* VLAN insertion is incompatible with LSOv2 */
2919         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2920                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2921
2922         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2923                 hw->rx_offset = NFP_NET_RX_OFFSET;
2924         else
2925                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2926
2927         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2928                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2929                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2930
2931         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2932                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2933                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2934                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2935                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2936                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2937                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2938                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2939                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2940                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2941                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2942                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2943                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2944                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2945                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2946
2947         hw->ctrl = 0;
2948
2949         hw->stride_rx = stride;
2950         hw->stride_tx = stride;
2951
2952         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2953                      hw->max_rx_queues, hw->max_tx_queues);
2954
2955         /* Initializing spinlock for reconfigs */
2956         rte_spinlock_init(&hw->reconfig_lock);
2957
2958         /* Allocating memory for mac addr */
2959         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2960                                                RTE_ETHER_ADDR_LEN, 0);
2961         if (eth_dev->data->mac_addrs == NULL) {
2962                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2963                 err = -ENOMEM;
2964                 goto dev_err_queues_map;
2965         }
2966
2967         if (hw->is_pf) {
2968                 nfp_net_pf_read_mac(hwport0, port);
2969                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2970         } else {
2971                 nfp_net_vf_read_mac(hw);
2972         }
2973
2974         if (!rte_is_valid_assigned_ether_addr(
2975                     (struct rte_ether_addr *)&hw->mac_addr)) {
2976                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2977                                    port);
2978                 /* Using random mac addresses for VFs */
2979                 rte_eth_random_addr(&hw->mac_addr[0]);
2980                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2981         }
2982
2983         /* Copying mac address to DPDK eth_dev struct */
2984         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac_addr,
2985                         &eth_dev->data->mac_addrs[0]);
2986
2987         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2988                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2989
2990         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2991                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2992                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2993                      pci_dev->id.device_id,
2994                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2995                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2996
2997         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2998                 /* Registering LSC interrupt handler */
2999                 rte_intr_callback_register(&pci_dev->intr_handle,
3000                                            nfp_net_dev_interrupt_handler,
3001                                            (void *)eth_dev);
3002                 /* Telling the firmware about the LSC interrupt entry */
3003                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
3004                 /* Recording current stats counters values */
3005                 nfp_net_stats_reset(eth_dev);
3006         }
3007
3008         return 0;
3009
3010 dev_err_queues_map:
3011                 nfp_cpp_area_free(hw->hwqueues_area);
3012 dev_err_ctrl_map:
3013                 nfp_cpp_area_free(hw->ctrl_area);
3014
3015         return err;
3016 }
3017
3018 #define NFP_CPP_MEMIO_BOUNDARY          (1 << 20)
3019
3020 /*
3021  * Serving a write request to NFP from host programs. The request
3022  * sends the write size and the CPP target. The bridge makes use
3023  * of CPP interface handler configured by the PMD setup.
3024  */
3025 static int
3026 nfp_cpp_bridge_serve_write(int sockfd, struct nfp_cpp *cpp)
3027 {
3028         struct nfp_cpp_area *area;
3029         off_t offset, nfp_offset;
3030         uint32_t cpp_id, pos, len;
3031         uint32_t tmpbuf[16];
3032         size_t count, curlen, totlen = 0;
3033         int err = 0;
3034
3035         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3036                 sizeof(off_t), sizeof(size_t));
3037
3038         /* Reading the count param */
3039         err = recv(sockfd, &count, sizeof(off_t), 0);
3040         if (err != sizeof(off_t))
3041                 return -EINVAL;
3042
3043         curlen = count;
3044
3045         /* Reading the offset param */
3046         err = recv(sockfd, &offset, sizeof(off_t), 0);
3047         if (err != sizeof(off_t))
3048                 return -EINVAL;
3049
3050         /* Obtain target's CPP ID and offset in target */
3051         cpp_id = (offset >> 40) << 8;
3052         nfp_offset = offset & ((1ull << 40) - 1);
3053
3054         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3055                 offset);
3056         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3057                 cpp_id, nfp_offset);
3058
3059         /* Adjust length if not aligned */
3060         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3061             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3062                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3063                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3064         }
3065
3066         while (count > 0) {
3067                 /* configure a CPP PCIe2CPP BAR for mapping the CPP target */
3068                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3069                                                     nfp_offset, curlen);
3070                 if (!area) {
3071                         RTE_LOG(ERR, PMD, "%s: area alloc fail\n", __func__);
3072                         return -EIO;
3073                 }
3074
3075                 /* mapping the target */
3076                 err = nfp_cpp_area_acquire(area);
3077                 if (err < 0) {
3078                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3079                         nfp_cpp_area_free(area);
3080                         return -EIO;
3081                 }
3082
3083                 for (pos = 0; pos < curlen; pos += len) {
3084                         len = curlen - pos;
3085                         if (len > sizeof(tmpbuf))
3086                                 len = sizeof(tmpbuf);
3087
3088                         PMD_CPP_LOG(DEBUG, "%s: Receive %u of %zu\n", __func__,
3089                                            len, count);
3090                         err = recv(sockfd, tmpbuf, len, MSG_WAITALL);
3091                         if (err != (int)len) {
3092                                 RTE_LOG(ERR, PMD,
3093                                         "%s: error when receiving, %d of %zu\n",
3094                                         __func__, err, count);
3095                                 nfp_cpp_area_release(area);
3096                                 nfp_cpp_area_free(area);
3097                                 return -EIO;
3098                         }
3099                         err = nfp_cpp_area_write(area, pos, tmpbuf, len);
3100                         if (err < 0) {
3101                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_write error\n");
3102                                 nfp_cpp_area_release(area);
3103                                 nfp_cpp_area_free(area);
3104                                 return -EIO;
3105                         }
3106                 }
3107
3108                 nfp_offset += pos;
3109                 totlen += pos;
3110                 nfp_cpp_area_release(area);
3111                 nfp_cpp_area_free(area);
3112
3113                 count -= pos;
3114                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3115                          NFP_CPP_MEMIO_BOUNDARY : count;
3116         }
3117
3118         return 0;
3119 }
3120
3121 /*
3122  * Serving a read request to NFP from host programs. The request
3123  * sends the read size and the CPP target. The bridge makes use
3124  * of CPP interface handler configured by the PMD setup. The read
3125  * data is sent to the requester using the same socket.
3126  */
3127 static int
3128 nfp_cpp_bridge_serve_read(int sockfd, struct nfp_cpp *cpp)
3129 {
3130         struct nfp_cpp_area *area;
3131         off_t offset, nfp_offset;
3132         uint32_t cpp_id, pos, len;
3133         uint32_t tmpbuf[16];
3134         size_t count, curlen, totlen = 0;
3135         int err = 0;
3136
3137         PMD_CPP_LOG(DEBUG, "%s: offset size %zu, count_size: %zu\n", __func__,
3138                 sizeof(off_t), sizeof(size_t));
3139
3140         /* Reading the count param */
3141         err = recv(sockfd, &count, sizeof(off_t), 0);
3142         if (err != sizeof(off_t))
3143                 return -EINVAL;
3144
3145         curlen = count;
3146
3147         /* Reading the offset param */
3148         err = recv(sockfd, &offset, sizeof(off_t), 0);
3149         if (err != sizeof(off_t))
3150                 return -EINVAL;
3151
3152         /* Obtain target's CPP ID and offset in target */
3153         cpp_id = (offset >> 40) << 8;
3154         nfp_offset = offset & ((1ull << 40) - 1);
3155
3156         PMD_CPP_LOG(DEBUG, "%s: count %zu and offset %jd\n", __func__, count,
3157                            offset);
3158         PMD_CPP_LOG(DEBUG, "%s: cpp_id %08x and nfp_offset %jd\n", __func__,
3159                            cpp_id, nfp_offset);
3160
3161         /* Adjust length if not aligned */
3162         if (((nfp_offset + (off_t)count - 1) & ~(NFP_CPP_MEMIO_BOUNDARY - 1)) !=
3163             (nfp_offset & ~(NFP_CPP_MEMIO_BOUNDARY - 1))) {
3164                 curlen = NFP_CPP_MEMIO_BOUNDARY -
3165                         (nfp_offset & (NFP_CPP_MEMIO_BOUNDARY - 1));
3166         }
3167
3168         while (count > 0) {
3169                 area = nfp_cpp_area_alloc_with_name(cpp, cpp_id, "nfp.cdev",
3170                                                     nfp_offset, curlen);
3171                 if (!area) {
3172                         RTE_LOG(ERR, PMD, "%s: area alloc failed\n", __func__);
3173                         return -EIO;
3174                 }
3175
3176                 err = nfp_cpp_area_acquire(area);
3177                 if (err < 0) {
3178                         RTE_LOG(ERR, PMD, "area acquire failed\n");
3179                         nfp_cpp_area_free(area);
3180                         return -EIO;
3181                 }
3182
3183                 for (pos = 0; pos < curlen; pos += len) {
3184                         len = curlen - pos;
3185                         if (len > sizeof(tmpbuf))
3186                                 len = sizeof(tmpbuf);
3187
3188                         err = nfp_cpp_area_read(area, pos, tmpbuf, len);
3189                         if (err < 0) {
3190                                 RTE_LOG(ERR, PMD, "nfp_cpp_area_read error\n");
3191                                 nfp_cpp_area_release(area);
3192                                 nfp_cpp_area_free(area);
3193                                 return -EIO;
3194                         }
3195                         PMD_CPP_LOG(DEBUG, "%s: sending %u of %zu\n", __func__,
3196                                            len, count);
3197
3198                         err = send(sockfd, tmpbuf, len, 0);
3199                         if (err != (int)len) {
3200                                 RTE_LOG(ERR, PMD,
3201                                         "%s: error when sending: %d of %zu\n",
3202                                         __func__, err, count);
3203                                 nfp_cpp_area_release(area);
3204                                 nfp_cpp_area_free(area);
3205                                 return -EIO;
3206                         }
3207                 }
3208
3209                 nfp_offset += pos;
3210                 totlen += pos;
3211                 nfp_cpp_area_release(area);
3212                 nfp_cpp_area_free(area);
3213
3214                 count -= pos;
3215                 curlen = (count > NFP_CPP_MEMIO_BOUNDARY) ?
3216                         NFP_CPP_MEMIO_BOUNDARY : count;
3217         }
3218         return 0;
3219 }
3220
3221 #define NFP_IOCTL 'n'
3222 #define NFP_IOCTL_CPP_IDENTIFICATION _IOW(NFP_IOCTL, 0x8f, uint32_t)
3223 /*
3224  * Serving a ioctl command from host NFP tools. This usually goes to
3225  * a kernel driver char driver but it is not available when the PF is
3226  * bound to the PMD. Currently just one ioctl command is served and it
3227  * does not require any CPP access at all.
3228  */
3229 static int
3230 nfp_cpp_bridge_serve_ioctl(int sockfd, struct nfp_cpp *cpp)
3231 {
3232         uint32_t cmd, ident_size, tmp;
3233         int err;
3234
3235         /* Reading now the IOCTL command */
3236         err = recv(sockfd, &cmd, 4, 0);
3237         if (err != 4) {
3238                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3239                 return -EIO;
3240         }
3241
3242         /* Only supporting NFP_IOCTL_CPP_IDENTIFICATION */
3243         if (cmd != NFP_IOCTL_CPP_IDENTIFICATION) {
3244                 RTE_LOG(ERR, PMD, "%s: unknown cmd %d\n", __func__, cmd);
3245                 return -EINVAL;
3246         }
3247
3248         err = recv(sockfd, &ident_size, 4, 0);
3249         if (err != 4) {
3250                 RTE_LOG(ERR, PMD, "%s: read error from socket\n", __func__);
3251                 return -EIO;
3252         }
3253
3254         tmp = nfp_cpp_model(cpp);
3255
3256         PMD_CPP_LOG(DEBUG, "%s: sending NFP model %08x\n", __func__, tmp);
3257
3258         err = send(sockfd, &tmp, 4, 0);
3259         if (err != 4) {
3260                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3261                 return -EIO;
3262         }
3263
3264         tmp = cpp->interface;
3265
3266         PMD_CPP_LOG(DEBUG, "%s: sending NFP interface %08x\n", __func__, tmp);
3267
3268         err = send(sockfd, &tmp, 4, 0);
3269         if (err != 4) {
3270                 RTE_LOG(ERR, PMD, "%s: error writing to socket\n", __func__);
3271                 return -EIO;
3272         }
3273
3274         return 0;
3275 }
3276
3277 #define NFP_BRIDGE_OP_READ      20
3278 #define NFP_BRIDGE_OP_WRITE     30
3279 #define NFP_BRIDGE_OP_IOCTL     40
3280
3281 /*
3282  * This is the code to be executed by a service core. The CPP bridge interface
3283  * is based on a unix socket and requests usually received by a kernel char
3284  * driver, read, write and ioctl, are handled by the CPP bridge. NFP host tools
3285  * can be executed with a wrapper library and LD_LIBRARY being completely
3286  * unaware of the CPP bridge performing the NFP kernel char driver for CPP
3287  * accesses.
3288  */
3289 static int32_t
3290 nfp_cpp_bridge_service_func(void *args)
3291 {
3292         struct sockaddr address;
3293         struct nfp_cpp *cpp = args;
3294         int sockfd, datafd, op, ret;
3295
3296         unlink("/tmp/nfp_cpp");
3297         sockfd = socket(AF_UNIX, SOCK_STREAM, 0);
3298         if (sockfd < 0) {
3299                 RTE_LOG(ERR, PMD, "%s: socket creation error. Service failed\n",
3300                         __func__);
3301                 return -EIO;
3302         }
3303
3304         memset(&address, 0, sizeof(struct sockaddr));
3305
3306         address.sa_family = AF_UNIX;
3307         strcpy(address.sa_data, "/tmp/nfp_cpp");
3308
3309         ret = bind(sockfd, (const struct sockaddr *)&address,
3310                    sizeof(struct sockaddr));
3311         if (ret < 0) {
3312                 RTE_LOG(ERR, PMD, "%s: bind error (%d). Service failed\n",
3313                                   __func__, errno);
3314                 close(sockfd);
3315                 return ret;
3316         }
3317
3318         ret = listen(sockfd, 20);
3319         if (ret < 0) {
3320                 RTE_LOG(ERR, PMD, "%s: listen error(%d). Service failed\n",
3321                                   __func__, errno);
3322                 close(sockfd);
3323                 return ret;
3324         }
3325
3326         for (;;) {
3327                 datafd = accept(sockfd, NULL, NULL);
3328                 if (datafd < 0) {
3329                         RTE_LOG(ERR, PMD, "%s: accept call error (%d)\n",
3330                                           __func__, errno);
3331                         RTE_LOG(ERR, PMD, "%s: service failed\n", __func__);
3332                         close(sockfd);
3333                         return -EIO;
3334                 }
3335
3336                 while (1) {
3337                         ret = recv(datafd, &op, 4, 0);
3338                         if (ret <= 0) {
3339                                 PMD_CPP_LOG(DEBUG, "%s: socket close\n",
3340                                                    __func__);
3341                                 break;
3342                         }
3343
3344                         PMD_CPP_LOG(DEBUG, "%s: getting op %u\n", __func__, op);
3345
3346                         if (op == NFP_BRIDGE_OP_READ)
3347                                 nfp_cpp_bridge_serve_read(datafd, cpp);
3348
3349                         if (op == NFP_BRIDGE_OP_WRITE)
3350                                 nfp_cpp_bridge_serve_write(datafd, cpp);
3351
3352                         if (op == NFP_BRIDGE_OP_IOCTL)
3353                                 nfp_cpp_bridge_serve_ioctl(datafd, cpp);
3354
3355                         if (op == 0)
3356                                 break;
3357                 }
3358                 close(datafd);
3359         }
3360         close(sockfd);
3361
3362         return 0;
3363 }
3364
3365 static int
3366 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
3367                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
3368                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
3369 {
3370         struct rte_eth_dev *eth_dev;
3371         struct nfp_net_hw *hw = NULL;
3372         char *port_name;
3373         struct rte_service_spec service;
3374         int retval;
3375
3376         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
3377         if (!port_name)
3378                 return -ENOMEM;
3379
3380         if (ports > 1)
3381                 snprintf(port_name, 100, "%s_port%d", dev->device.name, port);
3382         else
3383                 strlcat(port_name, dev->device.name, 100);
3384
3385
3386         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3387                 eth_dev = rte_eth_dev_allocate(port_name);
3388                 if (!eth_dev) {
3389                         rte_free(port_name);
3390                         return -ENODEV;
3391                 }
3392                 if (port == 0) {
3393                         *priv = rte_zmalloc(port_name,
3394                                             sizeof(struct nfp_net_adapter) *
3395                                             ports, RTE_CACHE_LINE_SIZE);
3396                         if (!*priv) {
3397                                 rte_free(port_name);
3398                                 rte_eth_dev_release_port(eth_dev);
3399                                 return -ENOMEM;
3400                         }
3401                 }
3402                 eth_dev->data->dev_private = *priv;
3403
3404                 /*
3405                  * dev_private pointing to port0 dev_private because we need
3406                  * to configure vNIC bars based on port0 at nfp_net_init.
3407                  * Then dev_private is adjusted per port.
3408                  */
3409                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
3410                 hw->cpp = cpp;
3411                 hw->hwinfo = hwinfo;
3412                 hw->sym_tbl = sym_tbl;
3413                 hw->pf_port_idx = phys_port;
3414                 hw->is_pf = 1;
3415                 if (ports > 1)
3416                         hw->pf_multiport_enabled = 1;
3417
3418                 hw->total_ports = ports;
3419         } else {
3420                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3421                 if (!eth_dev) {
3422                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3423                                 "ethdev doesn't exist");
3424                         rte_free(port_name);
3425                         return -ENODEV;
3426                 }
3427                 eth_dev->process_private = cpp;
3428         }
3429
3430         eth_dev->device = &dev->device;
3431         rte_eth_copy_pci_info(eth_dev, dev);
3432
3433         retval = nfp_net_init(eth_dev);
3434
3435         if (retval) {
3436                 retval = -ENODEV;
3437                 goto probe_failed;
3438         } else {
3439                 rte_eth_dev_probing_finish(eth_dev);
3440         }
3441
3442         rte_free(port_name);
3443
3444         if (port == 0) {
3445                 /*
3446                  * The rte_service needs to be created just once per PMD.
3447                  * And the cpp handler needs to be linked to the service.
3448                  * Secondary processes will be used for debugging DPDK apps
3449                  * when requiring to use the CPP interface for accessing NFP
3450                  * components. And the cpp handler for secondary processes is
3451                  * available at this point.
3452                  */
3453                 memset(&service, 0, sizeof(struct rte_service_spec));
3454                 snprintf(service.name, sizeof(service.name), "nfp_cpp_service");
3455                 service.callback = nfp_cpp_bridge_service_func;
3456                 service.callback_userdata = (void *)cpp;
3457
3458                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private);
3459
3460                 if (rte_service_component_register(&service,
3461                                                    &hw->nfp_cpp_service_id))
3462                         RTE_LOG(ERR, PMD, "NFP CPP bridge service register() failed");
3463                 else
3464                         RTE_LOG(DEBUG, PMD, "NFP CPP bridge service registered");
3465         }
3466
3467         return retval;
3468
3469 probe_failed:
3470         rte_free(port_name);
3471         /* free ports private data if primary process */
3472         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3473                 rte_free(eth_dev->data->dev_private);
3474                 eth_dev->data->dev_private = NULL;
3475         }
3476         rte_eth_dev_release_port(eth_dev);
3477
3478         return retval;
3479 }
3480
3481 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3482
3483 static int
3484 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3485 {
3486         struct nfp_cpp *cpp = nsp->cpp;
3487         int fw_f;
3488         char *fw_buf;
3489         char fw_name[125];
3490         char serial[40];
3491         struct stat file_stat;
3492         off_t fsize, bytes;
3493
3494         /* Looking for firmware file in order of priority */
3495
3496         /* First try to find a firmware image specific for this device */
3497         snprintf(serial, sizeof(serial),
3498                         "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3499                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3500                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3501                 cpp->interface & 0xff);
3502
3503         snprintf(fw_name, sizeof(fw_name), "%s/%s.nffw", DEFAULT_FW_PATH,
3504                         serial);
3505
3506         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3507         fw_f = open(fw_name, O_RDONLY);
3508         if (fw_f >= 0)
3509                 goto read_fw;
3510
3511         /* Then try the PCI name */
3512         snprintf(fw_name, sizeof(fw_name), "%s/pci-%s.nffw", DEFAULT_FW_PATH,
3513                         dev->device.name);
3514
3515         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3516         fw_f = open(fw_name, O_RDONLY);
3517         if (fw_f >= 0)
3518                 goto read_fw;
3519
3520         /* Finally try the card type and media */
3521         snprintf(fw_name, sizeof(fw_name), "%s/%s", DEFAULT_FW_PATH, card);
3522         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3523         fw_f = open(fw_name, O_RDONLY);
3524         if (fw_f < 0) {
3525                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3526                 return -ENOENT;
3527         }
3528
3529 read_fw:
3530         if (fstat(fw_f, &file_stat) < 0) {
3531                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3532                 close(fw_f);
3533                 return -ENOENT;
3534         }
3535
3536         fsize = file_stat.st_size;
3537         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3538                             fw_name, (uint64_t)fsize);
3539
3540         fw_buf = malloc((size_t)fsize);
3541         if (!fw_buf) {
3542                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3543                 close(fw_f);
3544                 return -ENOMEM;
3545         }
3546         memset(fw_buf, 0, fsize);
3547
3548         bytes = read(fw_f, fw_buf, fsize);
3549         if (bytes != fsize) {
3550                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3551                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3552                                    (uint64_t)bytes, (uint64_t)fsize);
3553                 free(fw_buf);
3554                 close(fw_f);
3555                 return -EIO;
3556         }
3557
3558         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3559         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3560         PMD_DRV_LOG(INFO, "Done");
3561
3562         free(fw_buf);
3563         close(fw_f);
3564
3565         return 0;
3566 }
3567
3568 static int
3569 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3570              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3571 {
3572         struct nfp_nsp *nsp;
3573         const char *nfp_fw_model;
3574         char card_desc[100];
3575         int err = 0;
3576
3577         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3578
3579         if (nfp_fw_model) {
3580                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3581         } else {
3582                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3583                 return -EIO;
3584         }
3585
3586         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3587                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3588                        nfp_eth_table->count);
3589                 return -EIO;
3590         }
3591
3592         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3593                            nfp_eth_table->count);
3594
3595         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3596
3597         snprintf(card_desc, sizeof(card_desc), "nic_%s_%dx%d.nffw",
3598                         nfp_fw_model, nfp_eth_table->count,
3599                         nfp_eth_table->ports[0].speed / 1000);
3600
3601         nsp = nfp_nsp_open(cpp);
3602         if (!nsp) {
3603                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3604                 return -EIO;
3605         }
3606
3607         nfp_nsp_device_soft_reset(nsp);
3608         err = nfp_fw_upload(dev, nsp, card_desc);
3609
3610         nfp_nsp_close(nsp);
3611         return err;
3612 }
3613
3614 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3615                             struct rte_pci_device *dev)
3616 {
3617         struct nfp_cpp *cpp;
3618         struct nfp_hwinfo *hwinfo;
3619         struct nfp_rtsym_table *sym_tbl;
3620         struct nfp_eth_table *nfp_eth_table = NULL;
3621         int total_ports;
3622         void *priv = 0;
3623         int ret = -ENODEV;
3624         int err;
3625         int i;
3626
3627         if (!dev)
3628                 return ret;
3629
3630         /*
3631          * When device bound to UIO, the device could be used, by mistake,
3632          * by two DPDK apps, and the UIO driver does not avoid it. This
3633          * could lead to a serious problem when configuring the NFP CPP
3634          * interface. Here we avoid this telling to the CPP init code to
3635          * use a lock file if UIO is being used.
3636          */
3637         if (dev->kdrv == RTE_PCI_KDRV_VFIO)
3638                 cpp = nfp_cpp_from_device_name(dev, 0);
3639         else
3640                 cpp = nfp_cpp_from_device_name(dev, 1);
3641
3642         if (!cpp) {
3643                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3644                 ret = -EIO;
3645                 goto error;
3646         }
3647
3648         hwinfo = nfp_hwinfo_read(cpp);
3649         if (!hwinfo) {
3650                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3651                 return -EIO;
3652         }
3653
3654         nfp_eth_table = nfp_eth_read_ports(cpp);
3655         if (!nfp_eth_table) {
3656                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3657                 return -EIO;
3658         }
3659
3660         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3661                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3662                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3663                         ret = -EIO;
3664                         goto error;
3665                 }
3666         }
3667
3668         /* Now the symbol table should be there */
3669         sym_tbl = nfp_rtsym_table_read(cpp);
3670         if (!sym_tbl) {
3671                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3672                                 " symbol table");
3673                 ret = -EIO;
3674                 goto error;
3675         }
3676
3677         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3678         if (total_ports != (int)nfp_eth_table->count) {
3679                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3680                 ret = -EIO;
3681                 goto error;
3682         }
3683         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3684
3685         if (total_ports <= 0 || total_ports > 8) {
3686                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3687                 ret = -ENODEV;
3688                 goto error;
3689         }
3690
3691         for (i = 0; i < total_ports; i++) {
3692                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3693                                         nfp_eth_table->ports[i].index,
3694                                         sym_tbl, &priv);
3695                 if (ret)
3696                         break;
3697         }
3698
3699 error:
3700         free(nfp_eth_table);
3701         return ret;
3702 }
3703
3704 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3705         {
3706                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3707                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3708         },
3709         {
3710                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3711                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3712         },
3713         {
3714                 .vendor_id = 0,
3715         },
3716 };
3717
3718 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3719         {
3720                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3721                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3722         },
3723         {
3724                 .vendor_id = 0,
3725         },
3726 };
3727
3728 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3729         struct rte_pci_device *pci_dev)
3730 {
3731         return rte_eth_dev_pci_generic_probe(pci_dev,
3732                 sizeof(struct nfp_net_adapter), nfp_net_init);
3733 }
3734
3735 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3736 {
3737         struct rte_eth_dev *eth_dev;
3738         struct nfp_net_hw *hw, *hwport0;
3739         int port = 0;
3740
3741         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3742         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3743             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3744                 port = get_pf_port_number(eth_dev->data->name);
3745                 /*
3746                  * hotplug is not possible with multiport PF although freeing
3747                  * data structures can be done for first port.
3748                  */
3749                 if (port != 0)
3750                         return -ENOTSUP;
3751                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3752                 hw = &hwport0[port];
3753                 nfp_cpp_area_free(hw->ctrl_area);
3754                 nfp_cpp_area_free(hw->hwqueues_area);
3755                 free(hw->hwinfo);
3756                 free(hw->sym_tbl);
3757                 nfp_cpp_free(hw->cpp);
3758         } else {
3759                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3760         }
3761         /* hotplug is not possible with multiport PF */
3762         if (hw->pf_multiport_enabled)
3763                 return -ENOTSUP;
3764         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3765 }
3766
3767 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3768         .id_table = pci_id_nfp_pf_net_map,
3769         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3770         .probe = nfp_pf_pci_probe,
3771         .remove = eth_nfp_pci_remove,
3772 };
3773
3774 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3775         .id_table = pci_id_nfp_vf_net_map,
3776         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3777         .probe = eth_nfp_pci_probe,
3778         .remove = eth_nfp_pci_remove,
3779 };
3780
3781 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3782 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3783 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3784 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3785 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3786 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3787 RTE_LOG_REGISTER(nfp_logtype_init, pmd.net.nfp.init, NOTICE);
3788 RTE_LOG_REGISTER(nfp_logtype_driver, pmd.net.nfp.driver, NOTICE);
3789 /*
3790  * Local variables:
3791  * c-file-style: "Linux"
3792  * indent-tabs-mode: t
3793  * End:
3794  */