2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
50 #include <rte_ether.h>
51 #include <rte_malloc.h>
52 #include <rte_memzone.h>
53 #include <rte_mempool.h>
54 #include <rte_version.h>
55 #include <rte_string_fns.h>
56 #include <rte_alarm.h>
57 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
68 static void nfp_net_dev_interrupt_delayed_handler(void *param);
69 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
70 static void nfp_net_infos_get(struct rte_eth_dev *dev,
71 struct rte_eth_dev_info *dev_info);
72 static int nfp_net_init(struct rte_eth_dev *eth_dev);
73 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
74 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
75 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
76 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
77 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
79 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
81 static void nfp_net_rx_queue_release(void *rxq);
82 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
83 uint16_t nb_desc, unsigned int socket_id,
84 const struct rte_eth_rxconf *rx_conf,
85 struct rte_mempool *mp);
86 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
87 static void nfp_net_tx_queue_release(void *txq);
88 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
89 uint16_t nb_desc, unsigned int socket_id,
90 const struct rte_eth_txconf *tx_conf);
91 static int nfp_net_start(struct rte_eth_dev *dev);
92 static void nfp_net_stats_get(struct rte_eth_dev *dev,
93 struct rte_eth_stats *stats);
94 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
95 static void nfp_net_stop(struct rte_eth_dev *dev);
96 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
100 * The offset of the queue controller queues in the PCIe Target. These
101 * happen to be at the same offset on the NFP6000 and the NFP3200 so
102 * we use a single macro here.
104 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
106 /* Maximum value which can be added to a queue with one transaction */
107 #define NFP_QCP_MAX_ADD 0x7f
109 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
110 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
112 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
114 NFP_QCP_READ_PTR = 0,
119 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
120 * @q: Base address for queue structure
121 * @ptr: Add to the Read or Write pointer
122 * @val: Value to add to the queue pointer
124 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
127 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
131 if (ptr == NFP_QCP_READ_PTR)
132 off = NFP_QCP_QUEUE_ADD_RPTR;
134 off = NFP_QCP_QUEUE_ADD_WPTR;
136 while (val > NFP_QCP_MAX_ADD) {
137 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
138 val -= NFP_QCP_MAX_ADD;
141 nn_writel(rte_cpu_to_le_32(val), q + off);
145 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
146 * @q: Base address for queue structure
147 * @ptr: Read or Write pointer
149 static inline uint32_t
150 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
155 if (ptr == NFP_QCP_READ_PTR)
156 off = NFP_QCP_QUEUE_STS_LO;
158 off = NFP_QCP_QUEUE_STS_HI;
160 val = rte_cpu_to_le_32(nn_readl(q + off));
162 if (ptr == NFP_QCP_READ_PTR)
163 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
165 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
169 * Functions to read/write from/to Config BAR
170 * Performs any endian conversion necessary.
172 static inline uint8_t
173 nn_cfg_readb(struct nfp_net_hw *hw, int off)
175 return nn_readb(hw->ctrl_bar + off);
179 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
181 nn_writeb(val, hw->ctrl_bar + off);
184 static inline uint32_t
185 nn_cfg_readl(struct nfp_net_hw *hw, int off)
187 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
191 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
193 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
196 static inline uint64_t
197 nn_cfg_readq(struct nfp_net_hw *hw, int off)
199 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
203 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
205 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 /* Creating memzone for hardware rings. */
209 static const struct rte_memzone *
210 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
211 uint16_t queue_id, uint32_t ring_size, int socket_id)
213 char z_name[RTE_MEMZONE_NAMESIZE];
214 const struct rte_memzone *mz;
216 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
217 dev->driver->pci_drv.driver.name,
218 ring_name, dev->data->port_id, queue_id);
220 mz = rte_memzone_lookup(z_name);
224 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
229 * Atomically reads link status information from global structure rte_eth_dev.
232 * - Pointer to the structure rte_eth_dev to read from.
233 * - Pointer to the buffer to be saved with the link status.
236 * - On success, zero.
237 * - On failure, negative value.
240 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
241 struct rte_eth_link *link)
243 struct rte_eth_link *dst = link;
244 struct rte_eth_link *src = &dev->data->dev_link;
246 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
247 *(uint64_t *)src) == 0)
254 * Atomically writes the link status information into global
255 * structure rte_eth_dev.
258 * - Pointer to the structure rte_eth_dev to read from.
259 * - Pointer to the buffer to be saved with the link status.
262 * - On success, zero.
263 * - On failure, negative value.
266 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
267 struct rte_eth_link *link)
269 struct rte_eth_link *dst = &dev->data->dev_link;
270 struct rte_eth_link *src = link;
272 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
273 *(uint64_t *)src) == 0)
280 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
284 if (rxq->rxbufs == NULL)
287 for (i = 0; i < rxq->rx_count; i++) {
288 if (rxq->rxbufs[i].mbuf) {
289 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
290 rxq->rxbufs[i].mbuf = NULL;
296 nfp_net_rx_queue_release(void *rx_queue)
298 struct nfp_net_rxq *rxq = rx_queue;
301 nfp_net_rx_queue_release_mbufs(rxq);
302 rte_free(rxq->rxbufs);
308 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
310 nfp_net_rx_queue_release_mbufs(rxq);
316 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
320 if (txq->txbufs == NULL)
323 for (i = 0; i < txq->tx_count; i++) {
324 if (txq->txbufs[i].mbuf) {
325 rte_pktmbuf_free(txq->txbufs[i].mbuf);
326 txq->txbufs[i].mbuf = NULL;
332 nfp_net_tx_queue_release(void *tx_queue)
334 struct nfp_net_txq *txq = tx_queue;
337 nfp_net_tx_queue_release_mbufs(txq);
338 rte_free(txq->txbufs);
344 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
346 nfp_net_tx_queue_release_mbufs(txq);
352 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
356 struct timespec wait;
358 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
361 if (hw->qcp_cfg == NULL)
362 rte_panic("Bad configuration queue pointer\n");
364 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
367 wait.tv_nsec = 1000000;
369 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
371 /* Poll update field, waiting for NFP to ack the config */
372 for (cnt = 0; ; cnt++) {
373 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
376 if (new & NFP_NET_CFG_UPDATE_ERR) {
377 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
380 if (cnt >= NFP_NET_POLL_TIMEOUT) {
381 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
382 " %dms\n", update, cnt);
383 rte_panic("Exiting\n");
385 nanosleep(&wait, 0); /* waiting for a 1ms */
387 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
392 * Reconfigure the NIC
393 * @nn: device to reconfigure
394 * @ctrl: The value for the ctrl field in the BAR config
395 * @update: The value for the update field in the BAR config
397 * Write the update word to the BAR and ping the reconfig queue. Then poll
398 * until the firmware has acknowledged the update by zeroing the update word.
401 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
405 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
408 rte_spinlock_lock(&hw->reconfig_lock);
410 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
411 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
415 err = __nfp_net_reconfig(hw, update);
417 rte_spinlock_unlock(&hw->reconfig_lock);
423 * Reconfig errors imply situations where they can be handled.
424 * Otherwise, rte_panic is called inside __nfp_net_reconfig
426 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
432 * Configure an Ethernet device. This function must be invoked first
433 * before any other function in the Ethernet API. This function can
434 * also be re-invoked when a device is in the stopped state.
437 nfp_net_configure(struct rte_eth_dev *dev)
439 struct rte_eth_conf *dev_conf;
440 struct rte_eth_rxmode *rxmode;
441 struct rte_eth_txmode *txmode;
442 uint32_t new_ctrl = 0;
444 struct nfp_net_hw *hw;
446 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
449 * A DPDK app sends info about how many queues to use and how
450 * those queues need to be configured. This is used by the
451 * DPDK core and it makes sure no more queues than those
452 * advertised by the driver are requested. This function is
453 * called after that internal process
456 PMD_INIT_LOG(DEBUG, "Configure\n");
458 dev_conf = &dev->data->dev_conf;
459 rxmode = &dev_conf->rxmode;
460 txmode = &dev_conf->txmode;
462 /* Checking TX mode */
463 if (txmode->mq_mode) {
464 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
468 /* Checking RX mode */
469 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
470 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
471 update = NFP_NET_CFG_UPDATE_RSS;
472 new_ctrl = NFP_NET_CFG_CTRL_RSS;
474 PMD_INIT_LOG(INFO, "RSS not supported\n");
479 if (rxmode->split_hdr_size) {
480 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
484 if (rxmode->hw_ip_checksum) {
485 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
486 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
488 PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
493 if (rxmode->hw_vlan_filter) {
494 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
498 if (rxmode->hw_vlan_strip) {
499 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
500 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
502 PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
507 if (rxmode->hw_vlan_extend) {
508 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
512 /* Supporting VLAN insertion by default */
513 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
514 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
516 if (rxmode->jumbo_frame)
517 /* this is handled in rte_eth_dev_configure */
519 if (rxmode->hw_strip_crc) {
520 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
524 if (rxmode->enable_scatter) {
525 PMD_INIT_LOG(INFO, "Scatter not supported\n");
532 update |= NFP_NET_CFG_UPDATE_GEN;
534 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
535 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
544 nfp_net_enable_queues(struct rte_eth_dev *dev)
546 struct nfp_net_hw *hw;
547 uint64_t enabled_queues = 0;
550 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 /* Enabling the required TX queues in the device */
553 for (i = 0; i < dev->data->nb_tx_queues; i++)
554 enabled_queues |= (1 << i);
556 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
560 /* Enabling the required RX queues in the device */
561 for (i = 0; i < dev->data->nb_rx_queues; i++)
562 enabled_queues |= (1 << i);
564 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
568 nfp_net_disable_queues(struct rte_eth_dev *dev)
570 struct nfp_net_hw *hw;
571 uint32_t new_ctrl, update = 0;
573 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
575 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
576 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
578 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
579 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
580 NFP_NET_CFG_UPDATE_MSIX;
582 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
583 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
585 /* If an error when reconfig we avoid to change hw state */
586 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
593 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
597 for (i = 0; i < dev->data->nb_rx_queues; i++) {
598 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
605 nfp_net_params_setup(struct nfp_net_hw *hw)
607 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
608 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
612 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
614 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
617 static void nfp_net_read_mac(struct nfp_net_hw *hw)
621 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
622 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
624 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
625 memcpy(&hw->mac_addr[4], &tmp, 2);
629 nfp_net_start(struct rte_eth_dev *dev)
631 uint32_t new_ctrl, update = 0;
632 struct nfp_net_hw *hw;
635 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
637 PMD_INIT_LOG(DEBUG, "Start\n");
639 /* Disabling queues just in case... */
640 nfp_net_disable_queues(dev);
642 /* Writing configuration parameters in the device */
643 nfp_net_params_setup(hw);
645 /* Enabling the required queues in the device */
646 nfp_net_enable_queues(dev);
649 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
650 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
652 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
653 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
655 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
656 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
660 * Allocating rte mbuffs for configured rx queues.
661 * This requires queues being enabled before
663 if (nfp_net_rx_freelist_setup(dev) < 0) {
674 * An error returned by this function should mean the app
675 * exiting and then the system releasing all the memory
676 * allocated even memory coming from hugepages.
678 * The device could be enabled at this point with some queues
679 * ready for getting packets. This is true if the call to
680 * nfp_net_rx_freelist_setup() succeeds for some queues but
681 * fails for subsequent queues.
683 * This should make the app exiting but better if we tell the
686 nfp_net_disable_queues(dev);
691 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
693 nfp_net_stop(struct rte_eth_dev *dev)
697 PMD_INIT_LOG(DEBUG, "Stop\n");
699 nfp_net_disable_queues(dev);
702 for (i = 0; i < dev->data->nb_tx_queues; i++) {
703 nfp_net_reset_tx_queue(
704 (struct nfp_net_txq *)dev->data->tx_queues[i]);
707 for (i = 0; i < dev->data->nb_rx_queues; i++) {
708 nfp_net_reset_rx_queue(
709 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
713 /* Reset and stop device. The device can not be restarted. */
715 nfp_net_close(struct rte_eth_dev *dev)
717 struct nfp_net_hw *hw;
718 struct rte_pci_device *pci_dev;
720 PMD_INIT_LOG(DEBUG, "Close\n");
722 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
723 pci_dev = RTE_DEV_TO_PCI(dev->device);
726 * We assume that the DPDK application is stopping all the
727 * threads/queues before calling the device close function.
732 rte_intr_disable(&pci_dev->intr_handle);
733 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
735 /* unregister callback func from eal lib */
736 rte_intr_callback_unregister(&pci_dev->intr_handle,
737 nfp_net_dev_interrupt_handler,
741 * The ixgbe PMD driver disables the pcie master on the
742 * device. The i40e does not...
747 nfp_net_promisc_enable(struct rte_eth_dev *dev)
749 uint32_t new_ctrl, update = 0;
750 struct nfp_net_hw *hw;
752 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
754 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
756 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
757 PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
761 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
762 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
766 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
767 update = NFP_NET_CFG_UPDATE_GEN;
770 * DPDK sets promiscuous mode on just after this call assuming
771 * it can not fail ...
773 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
780 nfp_net_promisc_disable(struct rte_eth_dev *dev)
782 uint32_t new_ctrl, update = 0;
783 struct nfp_net_hw *hw;
785 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
787 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
788 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
792 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
793 update = NFP_NET_CFG_UPDATE_GEN;
796 * DPDK sets promiscuous mode off just before this call
797 * assuming it can not fail ...
799 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
806 * return 0 means link status changed, -1 means not changed
808 * Wait to complete is needed as it can take up to 9 seconds to get the Link
812 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
814 struct nfp_net_hw *hw;
815 struct rte_eth_link link, old;
816 uint32_t nn_link_status;
818 static const uint32_t ls_to_ethtool[] = {
819 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
820 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
821 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
822 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
823 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
824 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
825 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
826 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
829 PMD_DRV_LOG(DEBUG, "Link update\n");
831 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
833 memset(&old, 0, sizeof(old));
834 nfp_net_dev_atomic_read_link_status(dev, &old);
836 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
838 memset(&link, 0, sizeof(struct rte_eth_link));
840 if (nn_link_status & NFP_NET_CFG_STS_LINK)
841 link.link_status = ETH_LINK_UP;
843 link.link_duplex = ETH_LINK_FULL_DUPLEX;
845 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
846 NFP_NET_CFG_STS_LINK_RATE_MASK;
848 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
849 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
850 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
851 /* We really do not know the speed wil old firmware */
852 link.link_speed = ETH_SPEED_NUM_NONE;
854 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
855 link.link_speed = ETH_SPEED_NUM_NONE;
857 link.link_speed = ls_to_ethtool[nn_link_status];
860 if (old.link_status != link.link_status) {
861 nfp_net_dev_atomic_write_link_status(dev, &link);
862 if (link.link_status)
863 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
865 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
873 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
876 struct nfp_net_hw *hw;
877 struct rte_eth_stats nfp_dev_stats;
879 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
881 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
883 /* reading per RX ring stats */
884 for (i = 0; i < dev->data->nb_rx_queues; i++) {
885 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
888 nfp_dev_stats.q_ipackets[i] =
889 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
891 nfp_dev_stats.q_ipackets[i] -=
892 hw->eth_stats_base.q_ipackets[i];
894 nfp_dev_stats.q_ibytes[i] =
895 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
897 nfp_dev_stats.q_ibytes[i] -=
898 hw->eth_stats_base.q_ibytes[i];
901 /* reading per TX ring stats */
902 for (i = 0; i < dev->data->nb_tx_queues; i++) {
903 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
906 nfp_dev_stats.q_opackets[i] =
907 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
909 nfp_dev_stats.q_opackets[i] -=
910 hw->eth_stats_base.q_opackets[i];
912 nfp_dev_stats.q_obytes[i] =
913 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
915 nfp_dev_stats.q_obytes[i] -=
916 hw->eth_stats_base.q_obytes[i];
919 nfp_dev_stats.ipackets =
920 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
922 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
924 nfp_dev_stats.ibytes =
925 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
927 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
929 nfp_dev_stats.opackets =
930 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
932 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
934 nfp_dev_stats.obytes =
935 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
937 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
939 /* reading general device stats */
940 nfp_dev_stats.ierrors =
941 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
943 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
945 nfp_dev_stats.oerrors =
946 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
948 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
950 /* RX ring mbuf allocation failures */
951 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
953 nfp_dev_stats.imissed =
954 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
956 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
959 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
963 nfp_net_stats_reset(struct rte_eth_dev *dev)
966 struct nfp_net_hw *hw;
968 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
971 * hw->eth_stats_base records the per counter starting point.
975 /* reading per RX ring stats */
976 for (i = 0; i < dev->data->nb_rx_queues; i++) {
977 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
980 hw->eth_stats_base.q_ipackets[i] =
981 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
983 hw->eth_stats_base.q_ibytes[i] =
984 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
987 /* reading per TX ring stats */
988 for (i = 0; i < dev->data->nb_tx_queues; i++) {
989 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
992 hw->eth_stats_base.q_opackets[i] =
993 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
995 hw->eth_stats_base.q_obytes[i] =
996 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
999 hw->eth_stats_base.ipackets =
1000 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1002 hw->eth_stats_base.ibytes =
1003 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1005 hw->eth_stats_base.opackets =
1006 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1008 hw->eth_stats_base.obytes =
1009 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1011 /* reading general device stats */
1012 hw->eth_stats_base.ierrors =
1013 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1015 hw->eth_stats_base.oerrors =
1016 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1018 /* RX ring mbuf allocation failures */
1019 dev->data->rx_mbuf_alloc_failed = 0;
1021 hw->eth_stats_base.imissed =
1022 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1026 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1028 struct nfp_net_hw *hw;
1030 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1033 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1034 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1035 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1036 dev_info->max_rx_pktlen = hw->mtu;
1037 /* Next should change when PF support is implemented */
1038 dev_info->max_mac_addrs = 1;
1040 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1041 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1043 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1044 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1045 DEV_RX_OFFLOAD_UDP_CKSUM |
1046 DEV_RX_OFFLOAD_TCP_CKSUM;
1048 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1049 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1051 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1052 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1053 DEV_TX_OFFLOAD_UDP_CKSUM |
1054 DEV_TX_OFFLOAD_TCP_CKSUM;
1056 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1058 .pthresh = DEFAULT_RX_PTHRESH,
1059 .hthresh = DEFAULT_RX_HTHRESH,
1060 .wthresh = DEFAULT_RX_WTHRESH,
1062 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1066 dev_info->default_txconf = (struct rte_eth_txconf) {
1068 .pthresh = DEFAULT_TX_PTHRESH,
1069 .hthresh = DEFAULT_TX_HTHRESH,
1070 .wthresh = DEFAULT_TX_WTHRESH,
1072 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1073 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1074 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1075 ETH_TXQ_FLAGS_NOOFFLOADS,
1078 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1079 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1081 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1082 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1083 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1086 static const uint32_t *
1087 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1089 static const uint32_t ptypes[] = {
1090 /* refers to nfp_net_set_hash() */
1091 RTE_PTYPE_INNER_L3_IPV4,
1092 RTE_PTYPE_INNER_L3_IPV6,
1093 RTE_PTYPE_INNER_L3_IPV6_EXT,
1094 RTE_PTYPE_INNER_L4_MASK,
1098 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1104 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1106 struct nfp_net_rxq *rxq;
1107 struct nfp_net_rx_desc *rxds;
1111 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1114 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1123 * Other PMDs are just checking the DD bit in intervals of 4
1124 * descriptors and counting all four if the first has the DD
1125 * bit on. Of course, this is not accurate but can be good for
1126 * perfomance. But ideally that should be done in descriptors
1127 * chunks belonging to the same cache line
1130 while (count < rxq->rx_count) {
1131 rxds = &rxq->rxds[idx];
1132 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1139 if ((idx) == rxq->rx_count)
1147 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1149 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1150 struct rte_eth_link link;
1152 memset(&link, 0, sizeof(link));
1153 nfp_net_dev_atomic_read_link_status(dev, &link);
1154 if (link.link_status)
1155 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1156 (int)(dev->data->port_id), (unsigned)link.link_speed,
1157 link.link_duplex == ETH_LINK_FULL_DUPLEX
1158 ? "full-duplex" : "half-duplex");
1160 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1161 (int)(dev->data->port_id));
1163 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1164 pci_dev->addr.domain, pci_dev->addr.bus,
1165 pci_dev->addr.devid, pci_dev->addr.function);
1168 /* Interrupt configuration and handling */
1171 * nfp_net_irq_unmask - Unmask an interrupt
1173 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1174 * clear the ICR for the entry.
1177 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1179 struct nfp_net_hw *hw;
1180 struct rte_pci_device *pci_dev;
1182 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183 pci_dev = RTE_DEV_TO_PCI(dev->device);
1185 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1186 /* If MSI-X auto-masking is used, clear the entry */
1188 rte_intr_enable(&pci_dev->intr_handle);
1190 /* Make sure all updates are written before un-masking */
1192 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1193 NFP_NET_CFG_ICR_UNMASKED);
1198 nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1202 struct rte_eth_link link;
1203 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1205 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1207 /* get the link status */
1208 memset(&link, 0, sizeof(link));
1209 nfp_net_dev_atomic_read_link_status(dev, &link);
1211 nfp_net_link_update(dev, 0);
1214 if (!link.link_status) {
1215 /* handle it 1 sec later, wait it being stable */
1216 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1217 /* likely to down */
1219 /* handle it 4 sec later, wait it being stable */
1220 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1223 if (rte_eal_alarm_set(timeout * 1000,
1224 nfp_net_dev_interrupt_delayed_handler,
1226 RTE_LOG(ERR, PMD, "Error setting alarm");
1228 nfp_net_irq_unmask(dev);
1233 * Interrupt handler which shall be registered for alarm callback for delayed
1234 * handling specific interrupt to wait for the stable nic state. As the NIC
1235 * interrupt state is not stable for nfp after link is just down, it needs
1236 * to wait 4 seconds to get the stable status.
1238 * @param handle Pointer to interrupt handle.
1239 * @param param The address of parameter (struct rte_eth_dev *)
1244 nfp_net_dev_interrupt_delayed_handler(void *param)
1246 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1248 nfp_net_link_update(dev, 0);
1249 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1251 nfp_net_dev_link_status_print(dev);
1254 nfp_net_irq_unmask(dev);
1258 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1260 struct nfp_net_hw *hw;
1262 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1264 /* check that mtu is within the allowed range */
1265 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1268 /* switch to jumbo mode if needed */
1269 if ((uint32_t)mtu > ETHER_MAX_LEN)
1270 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1272 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1274 /* update max frame size */
1275 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1277 /* writing to configuration space */
1278 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1286 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1287 uint16_t queue_idx, uint16_t nb_desc,
1288 unsigned int socket_id,
1289 const struct rte_eth_rxconf *rx_conf,
1290 struct rte_mempool *mp)
1292 const struct rte_memzone *tz;
1293 struct nfp_net_rxq *rxq;
1294 struct nfp_net_hw *hw;
1296 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1298 PMD_INIT_FUNC_TRACE();
1300 /* Validating number of descriptors */
1301 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1302 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1303 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1304 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1309 * Free memory prior to re-allocation if needed. This is the case after
1310 * calling nfp_net_stop
1312 if (dev->data->rx_queues[queue_idx]) {
1313 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1314 dev->data->rx_queues[queue_idx] = NULL;
1317 /* Allocating rx queue data structure */
1318 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1319 RTE_CACHE_LINE_SIZE, socket_id);
1323 /* Hw queues mapping based on firmware confifguration */
1324 rxq->qidx = queue_idx;
1325 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1326 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1327 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1328 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1331 * Tracking mbuf size for detecting a potential mbuf overflow due to
1335 rxq->mbuf_size = rxq->mem_pool->elt_size;
1336 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1337 hw->flbufsz = rxq->mbuf_size;
1339 rxq->rx_count = nb_desc;
1340 rxq->port_id = dev->data->port_id;
1341 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1342 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1344 rxq->drop_en = rx_conf->rx_drop_en;
1347 * Allocate RX ring hardware descriptors. A memzone large enough to
1348 * handle the maximum ring size is allocated in order to allow for
1349 * resizing in later calls to the queue setup function.
1351 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1352 sizeof(struct nfp_net_rx_desc) *
1353 NFP_NET_MAX_RX_DESC, socket_id);
1356 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1357 nfp_net_rx_queue_release(rxq);
1361 /* Saving physical and virtual addresses for the RX ring */
1362 rxq->dma = (uint64_t)tz->phys_addr;
1363 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1365 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1366 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1367 sizeof(*rxq->rxbufs) * nb_desc,
1368 RTE_CACHE_LINE_SIZE, socket_id);
1369 if (rxq->rxbufs == NULL) {
1370 nfp_net_rx_queue_release(rxq);
1374 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1375 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1377 nfp_net_reset_rx_queue(rxq);
1379 dev->data->rx_queues[queue_idx] = rxq;
1383 * Telling the HW about the physical address of the RX ring and number
1384 * of descriptors in log2 format
1386 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1387 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1393 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1395 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1399 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1402 for (i = 0; i < rxq->rx_count; i++) {
1403 struct nfp_net_rx_desc *rxd;
1404 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1407 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1408 (unsigned)rxq->qidx);
1412 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1414 rxd = &rxq->rxds[i];
1416 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1417 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1419 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1422 /* Make sure all writes are flushed before telling the hardware */
1425 /* Not advertising the whole ring as the firmware gets confused if so */
1426 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1429 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1435 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1436 uint16_t nb_desc, unsigned int socket_id,
1437 const struct rte_eth_txconf *tx_conf)
1439 const struct rte_memzone *tz;
1440 struct nfp_net_txq *txq;
1441 uint16_t tx_free_thresh;
1442 struct nfp_net_hw *hw;
1444 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1446 PMD_INIT_FUNC_TRACE();
1448 /* Validating number of descriptors */
1449 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1450 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1451 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1452 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1456 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1457 tx_conf->tx_free_thresh :
1458 DEFAULT_TX_FREE_THRESH);
1460 if (tx_free_thresh > (nb_desc)) {
1462 "tx_free_thresh must be less than the number of TX "
1463 "descriptors. (tx_free_thresh=%u port=%d "
1464 "queue=%d)\n", (unsigned int)tx_free_thresh,
1465 (int)dev->data->port_id, (int)queue_idx);
1470 * Free memory prior to re-allocation if needed. This is the case after
1471 * calling nfp_net_stop
1473 if (dev->data->tx_queues[queue_idx]) {
1474 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1476 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1477 dev->data->tx_queues[queue_idx] = NULL;
1480 /* Allocating tx queue data structure */
1481 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1482 RTE_CACHE_LINE_SIZE, socket_id);
1484 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1489 * Allocate TX ring hardware descriptors. A memzone large enough to
1490 * handle the maximum ring size is allocated in order to allow for
1491 * resizing in later calls to the queue setup function.
1493 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1494 sizeof(struct nfp_net_tx_desc) *
1495 NFP_NET_MAX_TX_DESC, socket_id);
1497 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1498 nfp_net_tx_queue_release(txq);
1502 txq->tx_count = nb_desc;
1503 txq->tx_free_thresh = tx_free_thresh;
1504 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1505 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1506 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1508 /* queue mapping based on firmware configuration */
1509 txq->qidx = queue_idx;
1510 txq->tx_qcidx = queue_idx * hw->stride_tx;
1511 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1513 txq->port_id = dev->data->port_id;
1514 txq->txq_flags = tx_conf->txq_flags;
1516 /* Saving physical and virtual addresses for the TX ring */
1517 txq->dma = (uint64_t)tz->phys_addr;
1518 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1520 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1521 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1522 sizeof(*txq->txbufs) * nb_desc,
1523 RTE_CACHE_LINE_SIZE, socket_id);
1524 if (txq->txbufs == NULL) {
1525 nfp_net_tx_queue_release(txq);
1528 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1529 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1531 nfp_net_reset_tx_queue(txq);
1533 dev->data->tx_queues[queue_idx] = txq;
1537 * Telling the HW about the physical address of the TX ring and number
1538 * of descriptors in log2 format
1540 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1541 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1546 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1548 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1549 struct rte_mbuf *mb)
1552 struct nfp_net_hw *hw = txq->hw;
1554 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1557 ol_flags = mb->ol_flags;
1559 /* IPv6 does not need checksum */
1560 if (ol_flags & PKT_TX_IP_CKSUM)
1561 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1563 switch (ol_flags & PKT_TX_L4_MASK) {
1564 case PKT_TX_UDP_CKSUM:
1565 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1567 case PKT_TX_TCP_CKSUM:
1568 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1572 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1573 txd->flags |= PCIE_DESC_TX_CSUM;
1576 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1578 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1579 struct rte_mbuf *mb)
1581 struct nfp_net_hw *hw = rxq->hw;
1583 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1586 /* If IPv4 and IP checksum error, fail */
1587 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1588 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1589 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1591 /* If neither UDP nor TCP return */
1592 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1593 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1596 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1597 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1598 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1600 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1601 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1602 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1605 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1606 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1609 * nfp_net_set_hash - Set mbuf hash data
1611 * The RSS hash and hash-type are pre-pended to the packet data.
1612 * Extract and decode it and set the mbuf fields.
1615 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1616 struct rte_mbuf *mbuf)
1620 struct nfp_net_hw *hw = rxq->hw;
1622 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1625 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1628 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1629 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1631 mbuf->hash.rss = hash;
1632 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1634 switch (hash_type) {
1635 case NFP_NET_RSS_IPV4:
1636 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1638 case NFP_NET_RSS_IPV6:
1639 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1641 case NFP_NET_RSS_IPV6_EX:
1642 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1645 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1650 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1652 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1655 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1660 * There are some decissions to take:
1661 * 1) How to check DD RX descriptors bit
1662 * 2) How and when to allocate new mbufs
1664 * Current implementation checks just one single DD bit each loop. As each
1665 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1666 * a single cache line instead. Tests with this change have not shown any
1667 * performance improvement but it requires further investigation. For example,
1668 * depending on which descriptor is next, the number of descriptors could be
1669 * less than 8 for just checking those in the same cache line. This implies
1670 * extra work which could be counterproductive by itself. Indeed, last firmware
1671 * changes are just doing this: writing several descriptors with the DD bit
1672 * for saving PCIe bandwidth and DMA operations from the NFP.
1674 * Mbuf allocation is done when a new packet is received. Then the descriptor
1675 * is automatically linked with the new mbuf and the old one is given to the
1676 * user. The main drawback with this design is mbuf allocation is heavier than
1677 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1678 * cache point of view it does not seem allocating the mbuf early on as we are
1679 * doing now have any benefit at all. Again, tests with this change have not
1680 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1681 * so looking at the implications of this type of allocation should be studied
1686 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1688 struct nfp_net_rxq *rxq;
1689 struct nfp_net_rx_desc *rxds;
1690 struct nfp_net_rx_buff *rxb;
1691 struct nfp_net_hw *hw;
1692 struct rte_mbuf *mb;
1693 struct rte_mbuf *new_mb;
1699 if (unlikely(rxq == NULL)) {
1701 * DPDK just checks the queue is lower than max queues
1702 * enabled. But the queue needs to be configured
1704 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1712 while (avail < nb_pkts) {
1713 rxb = &rxq->rxbufs[rxq->rd_p];
1714 if (unlikely(rxb == NULL)) {
1715 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1720 * Memory barrier to ensure that we won't do other
1721 * reads before the DD bit.
1725 rxds = &rxq->rxds[rxq->rd_p];
1726 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1730 * We got a packet. Let's alloc a new mbuff for refilling the
1731 * free descriptor ring as soon as possible
1733 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1734 if (unlikely(new_mb == NULL)) {
1735 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1736 "queue_id=%u\n", (unsigned)rxq->port_id,
1737 (unsigned)rxq->qidx);
1738 nfp_net_mbuf_alloc_failed(rxq);
1745 * Grab the mbuff and refill the descriptor with the
1746 * previously allocated mbuff
1751 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1752 rxds->rxd.data_len, rxq->mbuf_size);
1754 /* Size of this segment */
1755 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1756 /* Size of the whole packet. We just support 1 segment */
1757 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1759 if (unlikely((mb->data_len + hw->rx_offset) >
1762 * This should not happen and the user has the
1763 * responsibility of avoiding it. But we have
1764 * to give some info about the error
1766 RTE_LOG_DP(ERR, PMD,
1767 "mbuf overflow likely due to the RX offset.\n"
1768 "\t\tYour mbuf size should have extra space for"
1769 " RX offset=%u bytes.\n"
1770 "\t\tCurrently you just have %u bytes available"
1771 " but the received packet is %u bytes long",
1773 rxq->mbuf_size - hw->rx_offset,
1778 /* Filling the received mbuff with packet info */
1780 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1782 mb->data_off = RTE_PKTMBUF_HEADROOM +
1783 NFP_DESC_META_LEN(rxds);
1785 /* No scatter mode supported */
1789 /* Checking the RSS flag */
1790 nfp_net_set_hash(rxq, rxds, mb);
1792 /* Checking the checksum flag */
1793 nfp_net_rx_cksum(rxq, rxds, mb);
1795 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1796 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1797 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1798 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1801 /* Adding the mbuff to the mbuff array passed by the app */
1802 rx_pkts[avail++] = mb;
1804 /* Now resetting and updating the descriptor */
1807 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1809 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1810 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1813 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1820 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1821 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1823 nb_hold += rxq->nb_rx_hold;
1826 * FL descriptors needs to be written before incrementing the
1827 * FL queue WR pointer
1830 if (nb_hold > rxq->rx_free_thresh) {
1831 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1832 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1833 (unsigned)nb_hold, (unsigned)avail);
1834 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1837 rxq->nb_rx_hold = nb_hold;
1843 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1845 * @txq: TX queue to work with
1846 * Returns number of descriptors freed
1849 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1854 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1855 " status\n", txq->qidx);
1857 /* Work out how many packets have been sent */
1858 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1860 if (qcp_rd_p == txq->rd_p) {
1861 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1862 "packets (%u, %u)\n", txq->qidx,
1863 qcp_rd_p, txq->rd_p);
1867 if (qcp_rd_p > txq->rd_p)
1868 todo = qcp_rd_p - txq->rd_p;
1870 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
1872 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
1873 qcp_rd_p, txq->rd_p, txq->rd_p);
1879 if (unlikely(txq->rd_p >= txq->tx_count))
1880 txq->rd_p -= txq->tx_count;
1885 /* Leaving always free descriptors for avoiding wrapping confusion */
1887 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
1889 if (txq->wr_p >= txq->rd_p)
1890 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
1892 return txq->rd_p - txq->wr_p - 8;
1896 * nfp_net_txq_full - Check if the TX queue free descriptors
1897 * is below tx_free_threshold
1899 * @txq: TX queue to check
1901 * This function uses the host copy* of read/write pointers
1904 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
1906 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
1910 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1912 struct nfp_net_txq *txq;
1913 struct nfp_net_hw *hw;
1914 struct nfp_net_tx_desc *txds;
1915 struct rte_mbuf *pkt;
1917 int pkt_size, dma_size;
1918 uint16_t free_descs, issued_descs;
1919 struct rte_mbuf **lmbuf;
1924 txds = &txq->txds[txq->wr_p];
1926 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1927 txq->qidx, txq->wr_p, nb_pkts);
1929 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1930 nfp_net_tx_free_bufs(txq);
1932 free_descs = (uint16_t)nfp_free_tx_desc(txq);
1933 if (unlikely(free_descs == 0))
1940 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1941 txq->qidx, nb_pkts);
1942 /* Sending packets */
1943 while ((i < nb_pkts) && free_descs) {
1944 /* Grabbing the mbuf linked to the current descriptor */
1945 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
1946 /* Warming the cache for releasing the mbuf later on */
1947 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1949 pkt = *(tx_pkts + i);
1951 if (unlikely((pkt->nb_segs > 1) &&
1952 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1953 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1954 rte_panic("Multisegment packet unsupported\n");
1957 /* Checking if we have enough descriptors */
1958 if (unlikely(pkt->nb_segs > free_descs))
1962 * Checksum and VLAN flags just in the first descriptor for a
1963 * multisegment packet
1965 nfp_net_tx_cksum(txq, txds, pkt);
1967 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1968 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1969 txds->flags |= PCIE_DESC_TX_VLAN;
1970 txds->vlan = pkt->vlan_tci;
1973 if (pkt->ol_flags & PKT_TX_TCP_SEG)
1974 rte_panic("TSO is not supported\n");
1977 * mbuf data_len is the data in one segment and pkt_len data
1978 * in the whole packet. When the packet is just one segment,
1979 * then data_len = pkt_len
1981 pkt_size = pkt->pkt_len;
1983 /* Releasing mbuf which was prefetched above */
1985 rte_pktmbuf_free(*lmbuf);
1987 * Linking mbuf with descriptor for being released
1988 * next time descriptor is used
1993 dma_size = pkt->data_len;
1994 dma_addr = rte_mbuf_data_dma_addr(pkt);
1995 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
1996 "%" PRIx64 "\n", dma_addr);
1998 /* Filling descriptors fields */
1999 txds->dma_len = dma_size;
2000 txds->data_len = pkt->pkt_len;
2001 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2002 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2003 ASSERT(free_descs > 0);
2007 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2010 pkt_size -= dma_size;
2013 txds->offset_eop |= PCIE_DESC_TX_EOP;
2015 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2018 /* Referencing next free TX descriptor */
2019 txds = &txq->txds[txq->wr_p];
2026 /* Increment write pointers. Force memory write before we let HW know */
2028 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2034 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2036 uint32_t new_ctrl, update;
2037 struct nfp_net_hw *hw;
2039 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2042 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2043 (mask & ETH_VLAN_FILTER_OFFLOAD))
2044 RTE_LOG(INFO, PMD, "Not support for ETH_VLAN_FILTER_OFFLOAD or"
2045 " ETH_VLAN_FILTER_EXTEND");
2047 /* Enable vlan strip if it is not configured yet */
2048 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2049 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2050 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2052 /* Disable vlan strip just if it is configured */
2053 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2054 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2055 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2060 update = NFP_NET_CFG_UPDATE_GEN;
2062 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2065 hw->ctrl = new_ctrl;
2068 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2070 nfp_net_reta_update(struct rte_eth_dev *dev,
2071 struct rte_eth_rss_reta_entry64 *reta_conf,
2074 uint32_t reta, mask;
2078 struct nfp_net_hw *hw =
2079 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2081 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2084 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2085 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2086 "(%d) doesn't match the number hardware can supported "
2087 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2092 * Update Redirection Table. There are 128 8bit-entries which can be
2093 * manage as 32 32bit-entries
2095 for (i = 0; i < reta_size; i += 4) {
2096 /* Handling 4 RSS entries per loop */
2097 idx = i / RTE_RETA_GROUP_SIZE;
2098 shift = i % RTE_RETA_GROUP_SIZE;
2099 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2105 /* If all 4 entries were set, don't need read RETA register */
2107 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2109 for (j = 0; j < 4; j++) {
2110 if (!(mask & (0x1 << j)))
2113 /* Clearing the entry bits */
2114 reta &= ~(0xFF << (8 * j));
2115 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2117 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2120 update = NFP_NET_CFG_UPDATE_RSS;
2122 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2128 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2130 nfp_net_reta_query(struct rte_eth_dev *dev,
2131 struct rte_eth_rss_reta_entry64 *reta_conf,
2137 struct nfp_net_hw *hw;
2139 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2144 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2145 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2146 "(%d) doesn't match the number hardware can supported "
2147 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2152 * Reading Redirection Table. There are 128 8bit-entries which can be
2153 * manage as 32 32bit-entries
2155 for (i = 0; i < reta_size; i += 4) {
2156 /* Handling 4 RSS entries per loop */
2157 idx = i / RTE_RETA_GROUP_SIZE;
2158 shift = i % RTE_RETA_GROUP_SIZE;
2159 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2164 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2165 for (j = 0; j < 4; j++) {
2166 if (!(mask & (0x1 << j)))
2168 reta_conf->reta[shift + j] =
2169 (uint8_t)((reta >> (8 * j)) & 0xF);
2176 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2177 struct rte_eth_rss_conf *rss_conf)
2180 uint32_t cfg_rss_ctrl = 0;
2184 struct nfp_net_hw *hw;
2186 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188 rss_hf = rss_conf->rss_hf;
2190 /* Checking if RSS is enabled */
2191 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2192 if (rss_hf != 0) { /* Enable RSS? */
2193 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2196 return 0; /* Nothing to do */
2199 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2200 RTE_LOG(ERR, PMD, "hash key too long\n");
2204 if (rss_hf & ETH_RSS_IPV4)
2205 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2206 NFP_NET_CFG_RSS_IPV4_TCP |
2207 NFP_NET_CFG_RSS_IPV4_UDP;
2209 if (rss_hf & ETH_RSS_IPV6)
2210 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2211 NFP_NET_CFG_RSS_IPV6_TCP |
2212 NFP_NET_CFG_RSS_IPV6_UDP;
2214 /* configuring where to apply the RSS hash */
2215 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2217 /* Writing the key byte a byte */
2218 for (i = 0; i < rss_conf->rss_key_len; i++) {
2219 memcpy(&key, &rss_conf->rss_key[i], 1);
2220 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2223 /* Writing the key size */
2224 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2226 update = NFP_NET_CFG_UPDATE_RSS;
2228 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2235 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2236 struct rte_eth_rss_conf *rss_conf)
2239 uint32_t cfg_rss_ctrl;
2242 struct nfp_net_hw *hw;
2244 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2249 rss_hf = rss_conf->rss_hf;
2250 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2252 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2253 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2255 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2256 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2258 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2259 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2261 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2262 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2264 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2265 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2267 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2268 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2270 /* Reading the key size */
2271 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2273 /* Reading the key byte a byte */
2274 for (i = 0; i < rss_conf->rss_key_len; i++) {
2275 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2276 memcpy(&rss_conf->rss_key[i], &key, 1);
2282 /* Initialise and register driver with DPDK Application */
2283 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2284 .dev_configure = nfp_net_configure,
2285 .dev_start = nfp_net_start,
2286 .dev_stop = nfp_net_stop,
2287 .dev_close = nfp_net_close,
2288 .promiscuous_enable = nfp_net_promisc_enable,
2289 .promiscuous_disable = nfp_net_promisc_disable,
2290 .link_update = nfp_net_link_update,
2291 .stats_get = nfp_net_stats_get,
2292 .stats_reset = nfp_net_stats_reset,
2293 .dev_infos_get = nfp_net_infos_get,
2294 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2295 .mtu_set = nfp_net_dev_mtu_set,
2296 .vlan_offload_set = nfp_net_vlan_offload_set,
2297 .reta_update = nfp_net_reta_update,
2298 .reta_query = nfp_net_reta_query,
2299 .rss_hash_update = nfp_net_rss_hash_update,
2300 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2301 .rx_queue_setup = nfp_net_rx_queue_setup,
2302 .rx_queue_release = nfp_net_rx_queue_release,
2303 .rx_queue_count = nfp_net_rx_queue_count,
2304 .tx_queue_setup = nfp_net_tx_queue_setup,
2305 .tx_queue_release = nfp_net_tx_queue_release,
2309 nfp_net_init(struct rte_eth_dev *eth_dev)
2311 struct rte_pci_device *pci_dev;
2312 struct nfp_net_hw *hw;
2314 uint32_t tx_bar_off, rx_bar_off;
2318 PMD_INIT_FUNC_TRACE();
2320 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2322 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2323 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2324 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2326 /* For secondary processes, the primary has done all the work */
2327 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2330 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2331 rte_eth_copy_pci_info(eth_dev, pci_dev);
2332 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
2334 hw->device_id = pci_dev->id.device_id;
2335 hw->vendor_id = pci_dev->id.vendor_id;
2336 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2337 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2339 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2340 pci_dev->id.vendor_id, pci_dev->id.device_id,
2341 pci_dev->addr.domain, pci_dev->addr.bus,
2342 pci_dev->addr.devid, pci_dev->addr.function);
2344 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2345 if (hw->ctrl_bar == NULL) {
2347 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2350 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2351 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2353 /* Work out where in the BAR the queues start. */
2354 switch (pci_dev->id.device_id) {
2355 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2356 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2357 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2358 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2359 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2362 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2366 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2367 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2369 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2370 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2372 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2373 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2375 nfp_net_cfg_queue_setup(hw);
2377 /* Get some of the read-only fields from the config BAR */
2378 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2379 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2380 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2381 hw->mtu = hw->max_mtu;
2383 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2384 hw->rx_offset = NFP_NET_RX_OFFSET;
2386 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2388 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2389 hw->ver, hw->max_mtu);
2390 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2391 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2392 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2393 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2394 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2395 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2396 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2397 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2398 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2399 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2403 hw->stride_rx = stride;
2404 hw->stride_tx = stride;
2406 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2407 hw->max_rx_queues, hw->max_tx_queues);
2409 /* Initializing spinlock for reconfigs */
2410 rte_spinlock_init(&hw->reconfig_lock);
2412 /* Allocating memory for mac addr */
2413 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2414 if (eth_dev->data->mac_addrs == NULL) {
2415 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2419 nfp_net_read_mac(hw);
2421 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr))
2422 /* Using random mac addresses for VFs */
2423 eth_random_addr(&hw->mac_addr[0]);
2425 /* Copying mac address to DPDK eth_dev struct */
2426 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2427 ð_dev->data->mac_addrs[0]);
2429 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2430 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2431 eth_dev->data->port_id, pci_dev->id.vendor_id,
2432 pci_dev->id.device_id,
2433 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2434 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2436 /* Registering LSC interrupt handler */
2437 rte_intr_callback_register(&pci_dev->intr_handle,
2438 nfp_net_dev_interrupt_handler,
2441 /* enable uio intr after callback register */
2442 rte_intr_enable(&pci_dev->intr_handle);
2444 /* Telling the firmware about the LSC interrupt entry */
2445 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2447 /* Recording current stats counters values */
2448 nfp_net_stats_reset(eth_dev);
2453 static struct rte_pci_id pci_id_nfp_net_map[] = {
2455 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2456 PCI_DEVICE_ID_NFP6000_PF_NIC)
2459 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2460 PCI_DEVICE_ID_NFP6000_VF_NIC)
2467 static struct eth_driver rte_nfp_net_pmd = {
2469 .id_table = pci_id_nfp_net_map,
2470 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2471 .probe = rte_eth_dev_pci_probe,
2472 .remove = rte_eth_dev_pci_remove,
2474 .eth_dev_init = nfp_net_init,
2475 .dev_private_size = sizeof(struct nfp_net_adapter),
2478 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd.pci_drv);
2479 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2480 RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio");
2484 * c-file-style: "Linux"
2485 * indent-tabs-mode: t