drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfpcore/nfp_cpp.h"
  59 #include "nfpcore/nfp_nffw.h"
  60 #include "nfpcore/nfp_hwinfo.h"
  61 #include "nfpcore/nfp_mip.h"
  62 #include "nfpcore/nfp_rtsym.h"
  63 #include "nfpcore/nfp_nsp.h"
  64
  65 #include "nfp_net_pmd.h"
  66 #include "nfp_net_logs.h"
  67 #include "nfp_net_ctrl.h"
  68
  69 /* Prototypes */
  70 static void nfp_net_close(struct rte_eth_dev *dev);
  71 static int nfp_net_configure(struct rte_eth_dev *dev);
  72 static void nfp_net_dev_interrupt_handler(void *param);
  73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  76                               struct rte_eth_dev_info *dev_info);
  77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  83                                        uint16_t queue_idx);
  84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  85                                   uint16_t nb_pkts);
  86 static void nfp_net_rx_queue_release(void *rxq);
  87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_rxconf *rx_conf,
  90                                   struct rte_mempool *mp);
  91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  92 static void nfp_net_tx_queue_release(void *txq);
  93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  94                                   uint16_t nb_desc, unsigned int socket_id,
  95                                   const struct rte_eth_txconf *tx_conf);
  96 static int nfp_net_start(struct rte_eth_dev *dev);
  97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  98                               struct rte_eth_stats *stats);
  99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
 100 static void nfp_net_stop(struct rte_eth_dev *dev);
 101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 102                                   uint16_t nb_pkts);
 103
 104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
 105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 106                                    struct rte_eth_rss_conf *rss_conf);
 107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 108                     struct rte_eth_rss_reta_entry64 *reta_conf,
 109                     uint16_t reta_size);
 110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 111                         struct rte_eth_rss_conf *rss_conf);
 112 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
 113                              struct ether_addr *mac_addr);
 114
 115 /* The offset of the queue controller queues in the PCIe Target */
 116 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 117
 118 /* Maximum value which can be added to a queue with one transaction */
 119 #define NFP_QCP_MAX_ADD 0x7f
 120
 121 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 122         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 123
 124 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 125 enum nfp_qcp_ptr {
 126         NFP_QCP_READ_PTR = 0,
 127         NFP_QCP_WRITE_PTR
 128 };
 129
 130 /*
 131  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 132  * @q: Base address for queue structure
 133  * @ptr: Add to the Read or Write pointer
 134  * @val: Value to add to the queue pointer
 135  *
 136  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 137  */
 138 static inline void
 139 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 140 {
 141         uint32_t off;
 142
 143         if (ptr == NFP_QCP_READ_PTR)
 144                 off = NFP_QCP_QUEUE_ADD_RPTR;
 145         else
 146                 off = NFP_QCP_QUEUE_ADD_WPTR;
 147
 148         while (val > NFP_QCP_MAX_ADD) {
 149                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 150                 val -= NFP_QCP_MAX_ADD;
 151         }
 152
 153         nn_writel(rte_cpu_to_le_32(val), q + off);
 154 }
 155
 156 /*
 157  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 158  * @q:  Base address for queue structure
 159  * @ptr: Read or Write pointer
 160  */
 161 static inline uint32_t
 162 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 163 {
 164         uint32_t off;
 165         uint32_t val;
 166
 167         if (ptr == NFP_QCP_READ_PTR)
 168                 off = NFP_QCP_QUEUE_STS_LO;
 169         else
 170                 off = NFP_QCP_QUEUE_STS_HI;
 171
 172         val = rte_cpu_to_le_32(nn_readl(q + off));
 173
 174         if (ptr == NFP_QCP_READ_PTR)
 175                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 176         else
 177                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 178 }
 179
 180 /*
 181  * Functions to read/write from/to Config BAR
 182  * Performs any endian conversion necessary.
 183  */
 184 static inline uint8_t
 185 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 186 {
 187         return nn_readb(hw->ctrl_bar + off);
 188 }
 189
 190 static inline void
 191 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 192 {
 193         nn_writeb(val, hw->ctrl_bar + off);
 194 }
 195
 196 static inline uint32_t
 197 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 198 {
 199         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 200 }
 201
 202 static inline void
 203 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 204 {
 205         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 206 }
 207
 208 static inline uint64_t
 209 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 210 {
 211         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 212 }
 213
 214 static inline void
 215 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 216 {
 217         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 218 }
 219
 220 static void
 221 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 222 {
 223         unsigned i;
 224
 225         if (rxq->rxbufs == NULL)
 226                 return;
 227
 228         for (i = 0; i < rxq->rx_count; i++) {
 229                 if (rxq->rxbufs[i].mbuf) {
 230                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 231                         rxq->rxbufs[i].mbuf = NULL;
 232                 }
 233         }
 234 }
 235
 236 static void
 237 nfp_net_rx_queue_release(void *rx_queue)
 238 {
 239         struct nfp_net_rxq *rxq = rx_queue;
 240
 241         if (rxq) {
 242                 nfp_net_rx_queue_release_mbufs(rxq);
 243                 rte_free(rxq->rxbufs);
 244                 rte_free(rxq);
 245         }
 246 }
 247
 248 static void
 249 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 250 {
 251         nfp_net_rx_queue_release_mbufs(rxq);
 252         rxq->rd_p = 0;
 253         rxq->nb_rx_hold = 0;
 254 }
 255
 256 static void
 257 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 258 {
 259         unsigned i;
 260
 261         if (txq->txbufs == NULL)
 262                 return;
 263
 264         for (i = 0; i < txq->tx_count; i++) {
 265                 if (txq->txbufs[i].mbuf) {
 266                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 267                         txq->txbufs[i].mbuf = NULL;
 268                 }
 269         }
 270 }
 271
 272 static void
 273 nfp_net_tx_queue_release(void *tx_queue)
 274 {
 275         struct nfp_net_txq *txq = tx_queue;
 276
 277         if (txq) {
 278                 nfp_net_tx_queue_release_mbufs(txq);
 279                 rte_free(txq->txbufs);
 280                 rte_free(txq);
 281         }
 282 }
 283
 284 static void
 285 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 286 {
 287         nfp_net_tx_queue_release_mbufs(txq);
 288         txq->wr_p = 0;
 289         txq->rd_p = 0;
 290 }
 291
 292 static int
 293 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 294 {
 295         int cnt;
 296         uint32_t new;
 297         struct timespec wait;
 298
 299         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 300                     hw->qcp_cfg);
 301
 302         if (hw->qcp_cfg == NULL)
 303                 rte_panic("Bad configuration queue pointer\n");
 304
 305         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 306
 307         wait.tv_sec = 0;
 308         wait.tv_nsec = 1000000;
 309
 310         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 311
 312         /* Poll update field, waiting for NFP to ack the config */
 313         for (cnt = 0; ; cnt++) {
 314                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 315                 if (new == 0)
 316                         break;
 317                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 318                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 319                         return -1;
 320                 }
 321                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 322                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 323                                           " %dms", update, cnt);
 324                         rte_panic("Exiting\n");
 325                 }
 326                 nanosleep(&wait, 0); /* waiting for a 1ms */
 327         }
 328         PMD_DRV_LOG(DEBUG, "Ack DONE");
 329         return 0;
 330 }
 331
 332 /*
 333  * Reconfigure the NIC
 334  * @nn:    device to reconfigure
 335  * @ctrl:    The value for the ctrl field in the BAR config
 336  * @update:  The value for the update field in the BAR config
 337  *
 338  * Write the update word to the BAR and ping the reconfig queue. Then poll
 339  * until the firmware has acknowledged the update by zeroing the update word.
 340  */
 341 static int
 342 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 343 {
 344         uint32_t err;
 345
 346         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 347                     ctrl, update);
 348
 349         rte_spinlock_lock(&hw->reconfig_lock);
 350
 351         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 352         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 353
 354         rte_wmb();
 355
 356         err = __nfp_net_reconfig(hw, update);
 357
 358         rte_spinlock_unlock(&hw->reconfig_lock);
 359
 360         if (!err)
 361                 return 0;
 362
 363         /*
 364          * Reconfig errors imply situations where they can be handled.
 365          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 366          */
 367         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 368                      ctrl, update);
 369         return -EIO;
 370 }
 371
 372 /*
 373  * Configure an Ethernet device. This function must be invoked first
 374  * before any other function in the Ethernet API. This function can
 375  * also be re-invoked when a device is in the stopped state.
 376  */
 377 static int
 378 nfp_net_configure(struct rte_eth_dev *dev)
 379 {
 380         struct rte_eth_conf *dev_conf;
 381         struct rte_eth_rxmode *rxmode;
 382         struct rte_eth_txmode *txmode;
 383         struct nfp_net_hw *hw;
 384
 385         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 386
 387         /*
 388          * A DPDK app sends info about how many queues to use and how
 389          * those queues need to be configured. This is used by the
 390          * DPDK core and it makes sure no more queues than those
 391          * advertised by the driver are requested. This function is
 392          * called after that internal process
 393          */
 394
 395         PMD_INIT_LOG(DEBUG, "Configure");
 396
 397         dev_conf = &dev->data->dev_conf;
 398         rxmode = &dev_conf->rxmode;
 399         txmode = &dev_conf->txmode;
 400
 401         /* Checking TX mode */
 402         if (txmode->mq_mode) {
 403                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 404                 return -EINVAL;
 405         }
 406
 407         /* Checking RX mode */
 408         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 409             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 410                 PMD_INIT_LOG(INFO, "RSS not supported");
 411                 return -EINVAL;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static void
 418 nfp_net_enable_queues(struct rte_eth_dev *dev)
 419 {
 420         struct nfp_net_hw *hw;
 421         uint64_t enabled_queues = 0;
 422         int i;
 423
 424         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 425
 426         /* Enabling the required TX queues in the device */
 427         for (i = 0; i < dev->data->nb_tx_queues; i++)
 428                 enabled_queues |= (1 << i);
 429
 430         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 431
 432         enabled_queues = 0;
 433
 434         /* Enabling the required RX queues in the device */
 435         for (i = 0; i < dev->data->nb_rx_queues; i++)
 436                 enabled_queues |= (1 << i);
 437
 438         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 439 }
 440
 441 static void
 442 nfp_net_disable_queues(struct rte_eth_dev *dev)
 443 {
 444         struct nfp_net_hw *hw;
 445         uint32_t new_ctrl, update = 0;
 446
 447         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 448
 449         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 450         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 451
 452         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 453         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 454                  NFP_NET_CFG_UPDATE_MSIX;
 455
 456         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 457                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 458
 459         /* If an error when reconfig we avoid to change hw state */
 460         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 461                 return;
 462
 463         hw->ctrl = new_ctrl;
 464 }
 465
 466 static int
 467 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 468 {
 469         int i;
 470
 471         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 472                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 473                         return -1;
 474         }
 475         return 0;
 476 }
 477
 478 static void
 479 nfp_net_params_setup(struct nfp_net_hw *hw)
 480 {
 481         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 482         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 483 }
 484
 485 static void
 486 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 487 {
 488         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 489 }
 490
 491 #define ETH_ADDR_LEN    6
 492
 493 static void
 494 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 495 {
 496         int i;
 497
 498         for (i = 0; i < ETH_ADDR_LEN; i++)
 499                 dst[i] = src[i];
 500 }
 501
 502 static int
 503 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 504 {
 505         struct nfp_eth_table *nfp_eth_table;
 506
 507         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 508         /*
 509          * hw points to port0 private data. We need hw now pointing to
 510          * right port.
 511          */
 512         hw += port;
 513         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 514                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 515
 516         free(nfp_eth_table);
 517         return 0;
 518 }
 519
 520 static void
 521 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 522 {
 523         uint32_t tmp;
 524
 525         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 526         memcpy(&hw->mac_addr[0], &tmp, 4);
 527
 528         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 529         memcpy(&hw->mac_addr[4], &tmp, 2);
 530 }
 531
 532 static void
 533 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 534 {
 535         uint32_t mac0 = *(uint32_t *)mac;
 536         uint16_t mac1;
 537
 538         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 539
 540         mac += 4;
 541         mac1 = *(uint16_t *)mac;
 542         nn_writew(rte_cpu_to_be_16(mac1),
 543                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 544 }
 545
 546 int
 547 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 548 {
 549         struct nfp_net_hw *hw;
 550         uint32_t update, ctrl;
 551
 552         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 554             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 555                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 556                                   " port enabled");
 557                 return -EBUSY;
 558         }
 559
 560         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 561             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 562                 return -EBUSY;
 563
 564         /* Writing new MAC to the specific port BAR address */
 565         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 566
 567         /* Signal the NIC about the change */
 568         update = NFP_NET_CFG_UPDATE_MACADDR;
 569         ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR;
 570         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 571                 PMD_INIT_LOG(INFO, "MAC address update failed");
 572                 return -EIO;
 573         }
 574         return 0;
 575 }
 576
 577 static int
 578 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 579                            struct rte_intr_handle *intr_handle)
 580 {
 581         struct nfp_net_hw *hw;
 582         int i;
 583
 584         if (!intr_handle->intr_vec) {
 585                 intr_handle->intr_vec =
 586                         rte_zmalloc("intr_vec",
 587                                     dev->data->nb_rx_queues * sizeof(int), 0);
 588                 if (!intr_handle->intr_vec) {
 589                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 590                                      " intr_vec", dev->data->nb_rx_queues);
 591                         return -ENOMEM;
 592                 }
 593         }
 594
 595         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 596
 597         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 598                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 599                 /* UIO just supports one queue and no LSC*/
 600                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 601                 intr_handle->intr_vec[0] = 0;
 602         } else {
 603                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 604                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 605                         /*
 606                          * The first msix vector is reserved for non
 607                          * efd interrupts
 608                         */
 609                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 610                         intr_handle->intr_vec[i] = i + 1;
 611                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 612                                             intr_handle->intr_vec[i]);
 613                 }
 614         }
 615
 616         /* Avoiding TX interrupts */
 617         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 618         return 0;
 619 }
 620
 621 static uint32_t
 622 nfp_check_offloads(struct rte_eth_dev *dev)
 623 {
 624         struct nfp_net_hw *hw;
 625         struct rte_eth_conf *dev_conf;
 626         struct rte_eth_rxmode *rxmode;
 627         struct rte_eth_txmode *txmode;
 628         uint32_t ctrl = 0;
 629
 630         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632         dev_conf = &dev->data->dev_conf;
 633         rxmode = &dev_conf->rxmode;
 634         txmode = &dev_conf->txmode;
 635
 636         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 637                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 638                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 639         }
 640
 641         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 642                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 643                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 644         }
 645
 646         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 647                 hw->mtu = rxmode->max_rx_pkt_len;
 648
 649         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 650                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 651
 652         /* L2 broadcast */
 653         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 654                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 655
 656         /* L2 multicast */
 657         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 658                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 659
 660         /* TX checksum offload */
 661         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 662             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 663             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 664                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 665
 666         /* LSO offload */
 667         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 668                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 669                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 670                 else
 671                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 672         }
 673
 674         /* RX gather */
 675         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 676                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 677
 678         return ctrl;
 679 }
 680
 681 static int
 682 nfp_net_start(struct rte_eth_dev *dev)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t new_ctrl, update = 0;
 687         struct nfp_net_hw *hw;
 688         struct rte_eth_conf *dev_conf;
 689         struct rte_eth_rxmode *rxmode;
 690         uint32_t intr_vector;
 691         int ret;
 692
 693         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 694
 695         PMD_INIT_LOG(DEBUG, "Start");
 696
 697         /* Disabling queues just in case... */
 698         nfp_net_disable_queues(dev);
 699
 700         /* Enabling the required queues in the device */
 701         nfp_net_enable_queues(dev);
 702
 703         /* check and configure queue intr-vector mapping */
 704         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 705                 if (hw->pf_multiport_enabled) {
 706                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 707                                           "with NFP multiport PF");
 708                                 return -EINVAL;
 709                 }
 710                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 711                         /*
 712                          * Better not to share LSC with RX interrupts.
 713                          * Unregistering LSC interrupt handler
 714                          */
 715                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 716                                 nfp_net_dev_interrupt_handler, (void *)dev);
 717
 718                         if (dev->data->nb_rx_queues > 1) {
 719                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 720                                              "supports 1 queue with UIO");
 721                                 return -EIO;
 722                         }
 723                 }
 724                 intr_vector = dev->data->nb_rx_queues;
 725                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 726                         return -1;
 727
 728                 nfp_configure_rx_interrupt(dev, intr_handle);
 729                 update = NFP_NET_CFG_UPDATE_MSIX;
 730         }
 731
 732         rte_intr_enable(intr_handle);
 733
 734         new_ctrl = nfp_check_offloads(dev);
 735
 736         /* Writing configuration parameters in the device */
 737         nfp_net_params_setup(hw);
 738
 739         dev_conf = &dev->data->dev_conf;
 740         rxmode = &dev_conf->rxmode;
 741
 742         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 743                 nfp_net_rss_config_default(dev);
 744                 update |= NFP_NET_CFG_UPDATE_RSS;
 745                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 746         }
 747
 748         /* Enable device */
 749         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 750
 751         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 752
 753         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 754                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 755
 756         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 757         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 758                 return -EIO;
 759
 760         /*
 761          * Allocating rte mbuffs for configured rx queues.
 762          * This requires queues being enabled before
 763          */
 764         if (nfp_net_rx_freelist_setup(dev) < 0) {
 765                 ret = -ENOMEM;
 766                 goto error;
 767         }
 768
 769         if (hw->is_pf) {
 770                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 771                         /* Configure the physical port up */
 772                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 773                 else
 774                         nfp_eth_set_configured(dev->process_private,
 775                                                hw->pf_port_idx, 1);
 776         }
 777
 778         hw->ctrl = new_ctrl;
 779
 780         return 0;
 781
 782 error:
 783         /*
 784          * An error returned by this function should mean the app
 785          * exiting and then the system releasing all the memory
 786          * allocated even memory coming from hugepages.
 787          *
 788          * The device could be enabled at this point with some queues
 789          * ready for getting packets. This is true if the call to
 790          * nfp_net_rx_freelist_setup() succeeds for some queues but
 791          * fails for subsequent queues.
 792          *
 793          * This should make the app exiting but better if we tell the
 794          * device first.
 795          */
 796         nfp_net_disable_queues(dev);
 797
 798         return ret;
 799 }
 800
 801 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 802 static void
 803 nfp_net_stop(struct rte_eth_dev *dev)
 804 {
 805         int i;
 806         struct nfp_net_hw *hw;
 807
 808         PMD_INIT_LOG(DEBUG, "Stop");
 809
 810         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 811
 812         nfp_net_disable_queues(dev);
 813
 814         /* Clear queues */
 815         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 816                 nfp_net_reset_tx_queue(
 817                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 818         }
 819
 820         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 821                 nfp_net_reset_rx_queue(
 822                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 823         }
 824
 825         if (hw->is_pf) {
 826                 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 827                         /* Configure the physical port down */
 828                         nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 829                 else
 830                         nfp_eth_set_configured(dev->process_private,
 831                                                hw->pf_port_idx, 0);
 832         }
 833 }
 834
 835 /* Reset and stop device. The device can not be restarted. */
 836 static void
 837 nfp_net_close(struct rte_eth_dev *dev)
 838 {
 839         struct nfp_net_hw *hw;
 840         struct rte_pci_device *pci_dev;
 841         int i;
 842
 843         PMD_INIT_LOG(DEBUG, "Close");
 844
 845         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 846         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 847
 848         /*
 849          * We assume that the DPDK application is stopping all the
 850          * threads/queues before calling the device close function.
 851          */
 852
 853         nfp_net_disable_queues(dev);
 854
 855         /* Clear queues */
 856         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 857                 nfp_net_reset_tx_queue(
 858                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 859         }
 860
 861         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 862                 nfp_net_reset_rx_queue(
 863                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 864         }
 865
 866         rte_intr_disable(&pci_dev->intr_handle);
 867         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 868
 869         /* unregister callback func from eal lib */
 870         rte_intr_callback_unregister(&pci_dev->intr_handle,
 871                                      nfp_net_dev_interrupt_handler,
 872                                      (void *)dev);
 873
 874         /*
 875          * The ixgbe PMD driver disables the pcie master on the
 876          * device. The i40e does not...
 877          */
 878 }
 879
 880 static void
 881 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 882 {
 883         uint32_t new_ctrl, update = 0;
 884         struct nfp_net_hw *hw;
 885
 886         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 887
 888         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 889
 890         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 891                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 892                 return;
 893         }
 894
 895         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 896                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 897                 return;
 898         }
 899
 900         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 901         update = NFP_NET_CFG_UPDATE_GEN;
 902
 903         /*
 904          * DPDK sets promiscuous mode on just after this call assuming
 905          * it can not fail ...
 906          */
 907         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 908                 return;
 909
 910         hw->ctrl = new_ctrl;
 911 }
 912
 913 static void
 914 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 915 {
 916         uint32_t new_ctrl, update = 0;
 917         struct nfp_net_hw *hw;
 918
 919         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920
 921         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 922                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 923                 return;
 924         }
 925
 926         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 927         update = NFP_NET_CFG_UPDATE_GEN;
 928
 929         /*
 930          * DPDK sets promiscuous mode off just before this call
 931          * assuming it can not fail ...
 932          */
 933         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 934                 return;
 935
 936         hw->ctrl = new_ctrl;
 937 }
 938
 939 /*
 940  * return 0 means link status changed, -1 means not changed
 941  *
 942  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 943  * status.
 944  */
 945 static int
 946 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 947 {
 948         struct nfp_net_hw *hw;
 949         struct rte_eth_link link;
 950         uint32_t nn_link_status;
 951         int ret;
 952
 953         static const uint32_t ls_to_ethtool[] = {
 954                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 955                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 956                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 957                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 958                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 959                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 960                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 961                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 962         };
 963
 964         PMD_DRV_LOG(DEBUG, "Link update");
 965
 966         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 967
 968         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 969
 970         memset(&link, 0, sizeof(struct rte_eth_link));
 971
 972         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 973                 link.link_status = ETH_LINK_UP;
 974
 975         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 976
 977         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 978                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 979
 980         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 981                 link.link_speed = ETH_SPEED_NUM_NONE;
 982         else
 983                 link.link_speed = ls_to_ethtool[nn_link_status];
 984
 985         ret = rte_eth_linkstatus_set(dev, &link);
 986         if (ret == 0) {
 987                 if (link.link_status)
 988                         PMD_DRV_LOG(INFO, "NIC Link is Up");
 989                 else
 990                         PMD_DRV_LOG(INFO, "NIC Link is Down");
 991         }
 992         return ret;
 993 }
 994
 995 static int
 996 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 997 {
 998         int i;
 999         struct nfp_net_hw *hw;
1000         struct rte_eth_stats nfp_dev_stats;
1001
1002         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1003
1004         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1005
1006         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1007
1008         /* reading per RX ring stats */
1009         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1010                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1011                         break;
1012
1013                 nfp_dev_stats.q_ipackets[i] =
1014                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1015
1016                 nfp_dev_stats.q_ipackets[i] -=
1017                         hw->eth_stats_base.q_ipackets[i];
1018
1019                 nfp_dev_stats.q_ibytes[i] =
1020                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1021
1022                 nfp_dev_stats.q_ibytes[i] -=
1023                         hw->eth_stats_base.q_ibytes[i];
1024         }
1025
1026         /* reading per TX ring stats */
1027         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1028                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1029                         break;
1030
1031                 nfp_dev_stats.q_opackets[i] =
1032                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1033
1034                 nfp_dev_stats.q_opackets[i] -=
1035                         hw->eth_stats_base.q_opackets[i];
1036
1037                 nfp_dev_stats.q_obytes[i] =
1038                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1039
1040                 nfp_dev_stats.q_obytes[i] -=
1041                         hw->eth_stats_base.q_obytes[i];
1042         }
1043
1044         nfp_dev_stats.ipackets =
1045                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1046
1047         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1048
1049         nfp_dev_stats.ibytes =
1050                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1051
1052         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1053
1054         nfp_dev_stats.opackets =
1055                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1056
1057         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1058
1059         nfp_dev_stats.obytes =
1060                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1061
1062         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1063
1064         /* reading general device stats */
1065         nfp_dev_stats.ierrors =
1066                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1067
1068         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1069
1070         nfp_dev_stats.oerrors =
1071                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1072
1073         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1074
1075         /* RX ring mbuf allocation failures */
1076         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1077
1078         nfp_dev_stats.imissed =
1079                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1080
1081         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1082
1083         if (stats) {
1084                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1085                 return 0;
1086         }
1087         return -EINVAL;
1088 }
1089
1090 static void
1091 nfp_net_stats_reset(struct rte_eth_dev *dev)
1092 {
1093         int i;
1094         struct nfp_net_hw *hw;
1095
1096         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1097
1098         /*
1099          * hw->eth_stats_base records the per counter starting point.
1100          * Lets update it now
1101          */
1102
1103         /* reading per RX ring stats */
1104         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1105                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1106                         break;
1107
1108                 hw->eth_stats_base.q_ipackets[i] =
1109                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1110
1111                 hw->eth_stats_base.q_ibytes[i] =
1112                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1113         }
1114
1115         /* reading per TX ring stats */
1116         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1117                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1118                         break;
1119
1120                 hw->eth_stats_base.q_opackets[i] =
1121                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1122
1123                 hw->eth_stats_base.q_obytes[i] =
1124                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1125         }
1126
1127         hw->eth_stats_base.ipackets =
1128                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1129
1130         hw->eth_stats_base.ibytes =
1131                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1132
1133         hw->eth_stats_base.opackets =
1134                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1135
1136         hw->eth_stats_base.obytes =
1137                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1138
1139         /* reading general device stats */
1140         hw->eth_stats_base.ierrors =
1141                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1142
1143         hw->eth_stats_base.oerrors =
1144                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1145
1146         /* RX ring mbuf allocation failures */
1147         dev->data->rx_mbuf_alloc_failed = 0;
1148
1149         hw->eth_stats_base.imissed =
1150                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1151 }
1152
1153 static void
1154 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1155 {
1156         struct nfp_net_hw *hw;
1157
1158         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1159
1160         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1161         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1162         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1163         dev_info->max_rx_pktlen = hw->max_mtu;
1164         /* Next should change when PF support is implemented */
1165         dev_info->max_mac_addrs = 1;
1166
1167         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1168                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1169
1170         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1171                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1172                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1173                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1174
1175         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1176
1177         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1178                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1179
1180         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1181                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1182                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1183                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1184
1185         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1186                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1187
1188         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1189                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1190
1191         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1192                 .rx_thresh = {
1193                         .pthresh = DEFAULT_RX_PTHRESH,
1194                         .hthresh = DEFAULT_RX_HTHRESH,
1195                         .wthresh = DEFAULT_RX_WTHRESH,
1196                 },
1197                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1198                 .rx_drop_en = 0,
1199         };
1200
1201         dev_info->default_txconf = (struct rte_eth_txconf) {
1202                 .tx_thresh = {
1203                         .pthresh = DEFAULT_TX_PTHRESH,
1204                         .hthresh = DEFAULT_TX_HTHRESH,
1205                         .wthresh = DEFAULT_TX_WTHRESH,
1206                 },
1207                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1208                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1209         };
1210
1211         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1212                                            ETH_RSS_NONFRAG_IPV4_TCP |
1213                                            ETH_RSS_NONFRAG_IPV4_UDP |
1214                                            ETH_RSS_IPV6 |
1215                                            ETH_RSS_NONFRAG_IPV6_TCP |
1216                                            ETH_RSS_NONFRAG_IPV6_UDP;
1217
1218         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1219         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1220
1221         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1222                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1223                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1224 }
1225
1226 static const uint32_t *
1227 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1228 {
1229         static const uint32_t ptypes[] = {
1230                 /* refers to nfp_net_set_hash() */
1231                 RTE_PTYPE_INNER_L3_IPV4,
1232                 RTE_PTYPE_INNER_L3_IPV6,
1233                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1234                 RTE_PTYPE_INNER_L4_MASK,
1235                 RTE_PTYPE_UNKNOWN
1236         };
1237
1238         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1239                 return ptypes;
1240         return NULL;
1241 }
1242
1243 static uint32_t
1244 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1245 {
1246         struct nfp_net_rxq *rxq;
1247         struct nfp_net_rx_desc *rxds;
1248         uint32_t idx;
1249         uint32_t count;
1250
1251         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1252
1253         idx = rxq->rd_p;
1254
1255         count = 0;
1256
1257         /*
1258          * Other PMDs are just checking the DD bit in intervals of 4
1259          * descriptors and counting all four if the first has the DD
1260          * bit on. Of course, this is not accurate but can be good for
1261          * performance. But ideally that should be done in descriptors
1262          * chunks belonging to the same cache line
1263          */
1264
1265         while (count < rxq->rx_count) {
1266                 rxds = &rxq->rxds[idx];
1267                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1268                         break;
1269
1270                 count++;
1271                 idx++;
1272
1273                 /* Wrapping? */
1274                 if ((idx) == rxq->rx_count)
1275                         idx = 0;
1276         }
1277
1278         return count;
1279 }
1280
1281 static int
1282 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1283 {
1284         struct rte_pci_device *pci_dev;
1285         struct nfp_net_hw *hw;
1286         int base = 0;
1287
1288         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1289         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1290
1291         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1292                 base = 1;
1293
1294         /* Make sure all updates are written before un-masking */
1295         rte_wmb();
1296         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1297                       NFP_NET_CFG_ICR_UNMASKED);
1298         return 0;
1299 }
1300
1301 static int
1302 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1303 {
1304         struct rte_pci_device *pci_dev;
1305         struct nfp_net_hw *hw;
1306         int base = 0;
1307
1308         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1310
1311         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1312                 base = 1;
1313
1314         /* Make sure all updates are written before un-masking */
1315         rte_wmb();
1316         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1317         return 0;
1318 }
1319
1320 static void
1321 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1322 {
1323         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1324         struct rte_eth_link link;
1325
1326         rte_eth_linkstatus_get(dev, &link);
1327         if (link.link_status)
1328                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1329                             dev->data->port_id, link.link_speed,
1330                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1331                             ? "full-duplex" : "half-duplex");
1332         else
1333                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1334                             dev->data->port_id);
1335
1336         PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1337                 pci_dev->addr.domain, pci_dev->addr.bus,
1338                 pci_dev->addr.devid, pci_dev->addr.function);
1339 }
1340
1341 /* Interrupt configuration and handling */
1342
1343 /*
1344  * nfp_net_irq_unmask - Unmask an interrupt
1345  *
1346  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1347  * clear the ICR for the entry.
1348  */
1349 static void
1350 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1351 {
1352         struct nfp_net_hw *hw;
1353         struct rte_pci_device *pci_dev;
1354
1355         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1356         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1357
1358         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1359                 /* If MSI-X auto-masking is used, clear the entry */
1360                 rte_wmb();
1361                 rte_intr_enable(&pci_dev->intr_handle);
1362         } else {
1363                 /* Make sure all updates are written before un-masking */
1364                 rte_wmb();
1365                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1366                               NFP_NET_CFG_ICR_UNMASKED);
1367         }
1368 }
1369
1370 static void
1371 nfp_net_dev_interrupt_handler(void *param)
1372 {
1373         int64_t timeout;
1374         struct rte_eth_link link;
1375         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1376
1377         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1378
1379         rte_eth_linkstatus_get(dev, &link);
1380
1381         nfp_net_link_update(dev, 0);
1382
1383         /* likely to up */
1384         if (!link.link_status) {
1385                 /* handle it 1 sec later, wait it being stable */
1386                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1387                 /* likely to down */
1388         } else {
1389                 /* handle it 4 sec later, wait it being stable */
1390                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1391         }
1392
1393         if (rte_eal_alarm_set(timeout * 1000,
1394                               nfp_net_dev_interrupt_delayed_handler,
1395                               (void *)dev) < 0) {
1396                 PMD_INIT_LOG(ERR, "Error setting alarm");
1397                 /* Unmasking */
1398                 nfp_net_irq_unmask(dev);
1399         }
1400 }
1401
1402 /*
1403  * Interrupt handler which shall be registered for alarm callback for delayed
1404  * handling specific interrupt to wait for the stable nic state. As the NIC
1405  * interrupt state is not stable for nfp after link is just down, it needs
1406  * to wait 4 seconds to get the stable status.
1407  *
1408  * @param handle   Pointer to interrupt handle.
1409  * @param param    The address of parameter (struct rte_eth_dev *)
1410  *
1411  * @return  void
1412  */
1413 static void
1414 nfp_net_dev_interrupt_delayed_handler(void *param)
1415 {
1416         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1417
1418         nfp_net_link_update(dev, 0);
1419         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1420
1421         nfp_net_dev_link_status_print(dev);
1422
1423         /* Unmasking */
1424         nfp_net_irq_unmask(dev);
1425 }
1426
1427 static int
1428 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1429 {
1430         struct nfp_net_hw *hw;
1431
1432         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1433
1434         /* check that mtu is within the allowed range */
1435         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1436                 return -EINVAL;
1437
1438         /* mtu setting is forbidden if port is started */
1439         if (dev->data->dev_started) {
1440                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1441                             dev->data->port_id);
1442                 return -EBUSY;
1443         }
1444
1445         /* switch to jumbo mode if needed */
1446         if ((uint32_t)mtu > ETHER_MAX_LEN)
1447                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1448         else
1449                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1450
1451         /* update max frame size */
1452         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1453
1454         /* writing to configuration space */
1455         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1456
1457         hw->mtu = mtu;
1458
1459         return 0;
1460 }
1461
1462 static int
1463 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1464                        uint16_t queue_idx, uint16_t nb_desc,
1465                        unsigned int socket_id,
1466                        const struct rte_eth_rxconf *rx_conf,
1467                        struct rte_mempool *mp)
1468 {
1469         const struct rte_memzone *tz;
1470         struct nfp_net_rxq *rxq;
1471         struct nfp_net_hw *hw;
1472
1473         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1474
1475         PMD_INIT_FUNC_TRACE();
1476
1477         /* Validating number of descriptors */
1478         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1479             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1480             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1481                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1482                 return -EINVAL;
1483         }
1484
1485         /*
1486          * Free memory prior to re-allocation if needed. This is the case after
1487          * calling nfp_net_stop
1488          */
1489         if (dev->data->rx_queues[queue_idx]) {
1490                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1491                 dev->data->rx_queues[queue_idx] = NULL;
1492         }
1493
1494         /* Allocating rx queue data structure */
1495         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1496                                  RTE_CACHE_LINE_SIZE, socket_id);
1497         if (rxq == NULL)
1498                 return -ENOMEM;
1499
1500         /* Hw queues mapping based on firmware confifguration */
1501         rxq->qidx = queue_idx;
1502         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1503         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1504         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1505         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1506
1507         /*
1508          * Tracking mbuf size for detecting a potential mbuf overflow due to
1509          * RX offset
1510          */
1511         rxq->mem_pool = mp;
1512         rxq->mbuf_size = rxq->mem_pool->elt_size;
1513         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1514         hw->flbufsz = rxq->mbuf_size;
1515
1516         rxq->rx_count = nb_desc;
1517         rxq->port_id = dev->data->port_id;
1518         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1519         rxq->drop_en = rx_conf->rx_drop_en;
1520
1521         /*
1522          * Allocate RX ring hardware descriptors. A memzone large enough to
1523          * handle the maximum ring size is allocated in order to allow for
1524          * resizing in later calls to the queue setup function.
1525          */
1526         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1527                                    sizeof(struct nfp_net_rx_desc) *
1528                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1529                                    socket_id);
1530
1531         if (tz == NULL) {
1532                 PMD_DRV_LOG(ERR, "Error allocatig rx dma");
1533                 nfp_net_rx_queue_release(rxq);
1534                 return -ENOMEM;
1535         }
1536
1537         /* Saving physical and virtual addresses for the RX ring */
1538         rxq->dma = (uint64_t)tz->iova;
1539         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1540
1541         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1542         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1543                                          sizeof(*rxq->rxbufs) * nb_desc,
1544                                          RTE_CACHE_LINE_SIZE, socket_id);
1545         if (rxq->rxbufs == NULL) {
1546                 nfp_net_rx_queue_release(rxq);
1547                 return -ENOMEM;
1548         }
1549
1550         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1551                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1552
1553         nfp_net_reset_rx_queue(rxq);
1554
1555         dev->data->rx_queues[queue_idx] = rxq;
1556         rxq->hw = hw;
1557
1558         /*
1559          * Telling the HW about the physical address of the RX ring and number
1560          * of descriptors in log2 format
1561          */
1562         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1563         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1564
1565         return 0;
1566 }
1567
1568 static int
1569 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1570 {
1571         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1572         uint64_t dma_addr;
1573         unsigned i;
1574
1575         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1576                    rxq->rx_count);
1577
1578         for (i = 0; i < rxq->rx_count; i++) {
1579                 struct nfp_net_rx_desc *rxd;
1580                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1581
1582                 if (mbuf == NULL) {
1583                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1584                                 (unsigned)rxq->qidx);
1585                         return -ENOMEM;
1586                 }
1587
1588                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1589
1590                 rxd = &rxq->rxds[i];
1591                 rxd->fld.dd = 0;
1592                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1593                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1594                 rxe[i].mbuf = mbuf;
1595                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1596         }
1597
1598         /* Make sure all writes are flushed before telling the hardware */
1599         rte_wmb();
1600
1601         /* Not advertising the whole ring as the firmware gets confused if so */
1602         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1603                    rxq->rx_count - 1);
1604
1605         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1606
1607         return 0;
1608 }
1609
1610 static int
1611 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1612                        uint16_t nb_desc, unsigned int socket_id,
1613                        const struct rte_eth_txconf *tx_conf)
1614 {
1615         const struct rte_memzone *tz;
1616         struct nfp_net_txq *txq;
1617         uint16_t tx_free_thresh;
1618         struct nfp_net_hw *hw;
1619
1620         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621
1622         PMD_INIT_FUNC_TRACE();
1623
1624         /* Validating number of descriptors */
1625         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1626             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1627             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1628                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1629                 return -EINVAL;
1630         }
1631
1632         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1633                                     tx_conf->tx_free_thresh :
1634                                     DEFAULT_TX_FREE_THRESH);
1635
1636         if (tx_free_thresh > (nb_desc)) {
1637                 PMD_DRV_LOG(ERR,
1638                         "tx_free_thresh must be less than the number of TX "
1639                         "descriptors. (tx_free_thresh=%u port=%d "
1640                         "queue=%d)", (unsigned int)tx_free_thresh,
1641                         dev->data->port_id, (int)queue_idx);
1642                 return -(EINVAL);
1643         }
1644
1645         /*
1646          * Free memory prior to re-allocation if needed. This is the case after
1647          * calling nfp_net_stop
1648          */
1649         if (dev->data->tx_queues[queue_idx]) {
1650                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1651                            queue_idx);
1652                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1653                 dev->data->tx_queues[queue_idx] = NULL;
1654         }
1655
1656         /* Allocating tx queue data structure */
1657         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1658                                  RTE_CACHE_LINE_SIZE, socket_id);
1659         if (txq == NULL) {
1660                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1661                 return -ENOMEM;
1662         }
1663
1664         /*
1665          * Allocate TX ring hardware descriptors. A memzone large enough to
1666          * handle the maximum ring size is allocated in order to allow for
1667          * resizing in later calls to the queue setup function.
1668          */
1669         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1670                                    sizeof(struct nfp_net_tx_desc) *
1671                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1672                                    socket_id);
1673         if (tz == NULL) {
1674                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1675                 nfp_net_tx_queue_release(txq);
1676                 return -ENOMEM;
1677         }
1678
1679         txq->tx_count = nb_desc;
1680         txq->tx_free_thresh = tx_free_thresh;
1681         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1682         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1683         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1684
1685         /* queue mapping based on firmware configuration */
1686         txq->qidx = queue_idx;
1687         txq->tx_qcidx = queue_idx * hw->stride_tx;
1688         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1689
1690         txq->port_id = dev->data->port_id;
1691
1692         /* Saving physical and virtual addresses for the TX ring */
1693         txq->dma = (uint64_t)tz->iova;
1694         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1695
1696         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1697         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1698                                          sizeof(*txq->txbufs) * nb_desc,
1699                                          RTE_CACHE_LINE_SIZE, socket_id);
1700         if (txq->txbufs == NULL) {
1701                 nfp_net_tx_queue_release(txq);
1702                 return -ENOMEM;
1703         }
1704         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1705                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1706
1707         nfp_net_reset_tx_queue(txq);
1708
1709         dev->data->tx_queues[queue_idx] = txq;
1710         txq->hw = hw;
1711
1712         /*
1713          * Telling the HW about the physical address of the TX ring and number
1714          * of descriptors in log2 format
1715          */
1716         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1717         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1718
1719         return 0;
1720 }
1721
1722 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1723 static inline void
1724 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1725                struct rte_mbuf *mb)
1726 {
1727         uint64_t ol_flags;
1728         struct nfp_net_hw *hw = txq->hw;
1729
1730         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1731                 goto clean_txd;
1732
1733         ol_flags = mb->ol_flags;
1734
1735         if (!(ol_flags & PKT_TX_TCP_SEG))
1736                 goto clean_txd;
1737
1738         txd->l3_offset = mb->l2_len;
1739         txd->l4_offset = mb->l2_len + mb->l3_len;
1740         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1741         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1742         txd->flags = PCIE_DESC_TX_LSO;
1743         return;
1744
1745 clean_txd:
1746         txd->flags = 0;
1747         txd->l3_offset = 0;
1748         txd->l4_offset = 0;
1749         txd->lso_hdrlen = 0;
1750         txd->mss = 0;
1751 }
1752
1753 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1754 static inline void
1755 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1756                  struct rte_mbuf *mb)
1757 {
1758         uint64_t ol_flags;
1759         struct nfp_net_hw *hw = txq->hw;
1760
1761         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1762                 return;
1763
1764         ol_flags = mb->ol_flags;
1765
1766         /* IPv6 does not need checksum */
1767         if (ol_flags & PKT_TX_IP_CKSUM)
1768                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1769
1770         switch (ol_flags & PKT_TX_L4_MASK) {
1771         case PKT_TX_UDP_CKSUM:
1772                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1773                 break;
1774         case PKT_TX_TCP_CKSUM:
1775                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1776                 break;
1777         }
1778
1779         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1780                 txd->flags |= PCIE_DESC_TX_CSUM;
1781 }
1782
1783 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1784 static inline void
1785 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1786                  struct rte_mbuf *mb)
1787 {
1788         struct nfp_net_hw *hw = rxq->hw;
1789
1790         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1791                 return;
1792
1793         /* If IPv4 and IP checksum error, fail */
1794         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1795             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1796                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1797         else
1798                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1799
1800         /* If neither UDP nor TCP return */
1801         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1802             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1803                 return;
1804
1805         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1806                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1807         else
1808                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1809 }
1810
1811 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1812 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1813
1814 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1815
1816 /*
1817  * nfp_net_set_hash - Set mbuf hash data
1818  *
1819  * The RSS hash and hash-type are pre-pended to the packet data.
1820  * Extract and decode it and set the mbuf fields.
1821  */
1822 static inline void
1823 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1824                  struct rte_mbuf *mbuf)
1825 {
1826         struct nfp_net_hw *hw = rxq->hw;
1827         uint8_t *meta_offset;
1828         uint32_t meta_info;
1829         uint32_t hash = 0;
1830         uint32_t hash_type = 0;
1831
1832         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1833                 return;
1834
1835         /* this is true for new firmwares */
1836         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1837             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1838              NFP_DESC_META_LEN(rxd))) {
1839                 /*
1840                  * new metadata api:
1841                  * <----  32 bit  ----->
1842                  * m    field type word
1843                  * e     data field #2
1844                  * t     data field #1
1845                  * a     data field #0
1846                  * ====================
1847                  *    packet data
1848                  *
1849                  * Field type word contains up to 8 4bit field types
1850                  * A 4bit field type refers to a data field word
1851                  * A data field word can have several 4bit field types
1852                  */
1853                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1854                 meta_offset -= NFP_DESC_META_LEN(rxd);
1855                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1856                 meta_offset += 4;
1857                 /* NFP PMD just supports metadata for hashing */
1858                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1859                 case NFP_NET_META_HASH:
1860                         /* next field type is about the hash type */
1861                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1862                         /* hash value is in the data field */
1863                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1864                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1865                         break;
1866                 default:
1867                         /* Unsupported metadata can be a performance issue */
1868                         return;
1869                 }
1870         } else {
1871                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1872                         return;
1873
1874                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1875                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1876         }
1877
1878         mbuf->hash.rss = hash;
1879         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1880
1881         switch (hash_type) {
1882         case NFP_NET_RSS_IPV4:
1883                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1884                 break;
1885         case NFP_NET_RSS_IPV6:
1886                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1887                 break;
1888         case NFP_NET_RSS_IPV6_EX:
1889                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1890                 break;
1891         case NFP_NET_RSS_IPV4_TCP:
1892                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1893                 break;
1894         case NFP_NET_RSS_IPV6_TCP:
1895                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1896                 break;
1897         case NFP_NET_RSS_IPV4_UDP:
1898                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1899                 break;
1900         case NFP_NET_RSS_IPV6_UDP:
1901                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1902                 break;
1903         default:
1904                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1905         }
1906 }
1907
1908 static inline void
1909 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1910 {
1911         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1912 }
1913
1914 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1915
1916 /*
1917  * RX path design:
1918  *
1919  * There are some decissions to take:
1920  * 1) How to check DD RX descriptors bit
1921  * 2) How and when to allocate new mbufs
1922  *
1923  * Current implementation checks just one single DD bit each loop. As each
1924  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1925  * a single cache line instead. Tests with this change have not shown any
1926  * performance improvement but it requires further investigation. For example,
1927  * depending on which descriptor is next, the number of descriptors could be
1928  * less than 8 for just checking those in the same cache line. This implies
1929  * extra work which could be counterproductive by itself. Indeed, last firmware
1930  * changes are just doing this: writing several descriptors with the DD bit
1931  * for saving PCIe bandwidth and DMA operations from the NFP.
1932  *
1933  * Mbuf allocation is done when a new packet is received. Then the descriptor
1934  * is automatically linked with the new mbuf and the old one is given to the
1935  * user. The main drawback with this design is mbuf allocation is heavier than
1936  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1937  * cache point of view it does not seem allocating the mbuf early on as we are
1938  * doing now have any benefit at all. Again, tests with this change have not
1939  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1940  * so looking at the implications of this type of allocation should be studied
1941  * deeply
1942  */
1943
1944 static uint16_t
1945 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1946 {
1947         struct nfp_net_rxq *rxq;
1948         struct nfp_net_rx_desc *rxds;
1949         struct nfp_net_rx_buff *rxb;
1950         struct nfp_net_hw *hw;
1951         struct rte_mbuf *mb;
1952         struct rte_mbuf *new_mb;
1953         uint16_t nb_hold;
1954         uint64_t dma_addr;
1955         int avail;
1956
1957         rxq = rx_queue;
1958         if (unlikely(rxq == NULL)) {
1959                 /*
1960                  * DPDK just checks the queue is lower than max queues
1961                  * enabled. But the queue needs to be configured
1962                  */
1963                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1964                 return -EINVAL;
1965         }
1966
1967         hw = rxq->hw;
1968         avail = 0;
1969         nb_hold = 0;
1970
1971         while (avail < nb_pkts) {
1972                 rxb = &rxq->rxbufs[rxq->rd_p];
1973                 if (unlikely(rxb == NULL)) {
1974                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1975                         break;
1976                 }
1977
1978                 rxds = &rxq->rxds[rxq->rd_p];
1979                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1980                         break;
1981
1982                 /*
1983                  * Memory barrier to ensure that we won't do other
1984                  * reads before the DD bit.
1985                  */
1986                 rte_rmb();
1987
1988                 /*
1989                  * We got a packet. Let's alloc a new mbuff for refilling the
1990                  * free descriptor ring as soon as possible
1991                  */
1992                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1993                 if (unlikely(new_mb == NULL)) {
1994                         RTE_LOG_DP(DEBUG, PMD,
1995                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
1996                                 rxq->port_id, (unsigned int)rxq->qidx);
1997                         nfp_net_mbuf_alloc_failed(rxq);
1998                         break;
1999                 }
2000
2001                 nb_hold++;
2002
2003                 /*
2004                  * Grab the mbuff and refill the descriptor with the
2005                  * previously allocated mbuff
2006                  */
2007                 mb = rxb->mbuf;
2008                 rxb->mbuf = new_mb;
2009
2010                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2011                            rxds->rxd.data_len, rxq->mbuf_size);
2012
2013                 /* Size of this segment */
2014                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2015                 /* Size of the whole packet. We just support 1 segment */
2016                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2017
2018                 if (unlikely((mb->data_len + hw->rx_offset) >
2019                              rxq->mbuf_size)) {
2020                         /*
2021                          * This should not happen and the user has the
2022                          * responsibility of avoiding it. But we have
2023                          * to give some info about the error
2024                          */
2025                         RTE_LOG_DP(ERR, PMD,
2026                                 "mbuf overflow likely due to the RX offset.\n"
2027                                 "\t\tYour mbuf size should have extra space for"
2028                                 " RX offset=%u bytes.\n"
2029                                 "\t\tCurrently you just have %u bytes available"
2030                                 " but the received packet is %u bytes long",
2031                                 hw->rx_offset,
2032                                 rxq->mbuf_size - hw->rx_offset,
2033                                 mb->data_len);
2034                         return -EINVAL;
2035                 }
2036
2037                 /* Filling the received mbuff with packet info */
2038                 if (hw->rx_offset)
2039                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2040                 else
2041                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2042                                        NFP_DESC_META_LEN(rxds);
2043
2044                 /* No scatter mode supported */
2045                 mb->nb_segs = 1;
2046                 mb->next = NULL;
2047
2048                 mb->port = rxq->port_id;
2049
2050                 /* Checking the RSS flag */
2051                 nfp_net_set_hash(rxq, rxds, mb);
2052
2053                 /* Checking the checksum flag */
2054                 nfp_net_rx_cksum(rxq, rxds, mb);
2055
2056                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2057                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2058                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2059                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2060                 }
2061
2062                 /* Adding the mbuff to the mbuff array passed by the app */
2063                 rx_pkts[avail++] = mb;
2064
2065                 /* Now resetting and updating the descriptor */
2066                 rxds->vals[0] = 0;
2067                 rxds->vals[1] = 0;
2068                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2069                 rxds->fld.dd = 0;
2070                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2071                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2072
2073                 rxq->rd_p++;
2074                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2075                         rxq->rd_p = 0;
2076         }
2077
2078         if (nb_hold == 0)
2079                 return nb_hold;
2080
2081         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2082                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2083
2084         nb_hold += rxq->nb_rx_hold;
2085
2086         /*
2087          * FL descriptors needs to be written before incrementing the
2088          * FL queue WR pointer
2089          */
2090         rte_wmb();
2091         if (nb_hold > rxq->rx_free_thresh) {
2092                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2093                            rxq->port_id, (unsigned int)rxq->qidx,
2094                            (unsigned)nb_hold, (unsigned)avail);
2095                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2096                 nb_hold = 0;
2097         }
2098         rxq->nb_rx_hold = nb_hold;
2099
2100         return avail;
2101 }
2102
2103 /*
2104  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2105  * status
2106  * @txq: TX queue to work with
2107  * Returns number of descriptors freed
2108  */
2109 int
2110 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2111 {
2112         uint32_t qcp_rd_p;
2113         int todo;
2114
2115         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2116                    " status", txq->qidx);
2117
2118         /* Work out how many packets have been sent */
2119         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2120
2121         if (qcp_rd_p == txq->rd_p) {
2122                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2123                            "packets (%u, %u)", txq->qidx,
2124                            qcp_rd_p, txq->rd_p);
2125                 return 0;
2126         }
2127
2128         if (qcp_rd_p > txq->rd_p)
2129                 todo = qcp_rd_p - txq->rd_p;
2130         else
2131                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2132
2133         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2134                    qcp_rd_p, txq->rd_p, txq->rd_p);
2135
2136         if (todo == 0)
2137                 return todo;
2138
2139         txq->rd_p += todo;
2140         if (unlikely(txq->rd_p >= txq->tx_count))
2141                 txq->rd_p -= txq->tx_count;
2142
2143         return todo;
2144 }
2145
2146 /* Leaving always free descriptors for avoiding wrapping confusion */
2147 static inline
2148 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2149 {
2150         if (txq->wr_p >= txq->rd_p)
2151                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2152         else
2153                 return txq->rd_p - txq->wr_p - 8;
2154 }
2155
2156 /*
2157  * nfp_net_txq_full - Check if the TX queue free descriptors
2158  * is below tx_free_threshold
2159  *
2160  * @txq: TX queue to check
2161  *
2162  * This function uses the host copy* of read/write pointers
2163  */
2164 static inline
2165 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2166 {
2167         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2168 }
2169
2170 static uint16_t
2171 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2172 {
2173         struct nfp_net_txq *txq;
2174         struct nfp_net_hw *hw;
2175         struct nfp_net_tx_desc *txds, txd;
2176         struct rte_mbuf *pkt;
2177         uint64_t dma_addr;
2178         int pkt_size, dma_size;
2179         uint16_t free_descs, issued_descs;
2180         struct rte_mbuf **lmbuf;
2181         int i;
2182
2183         txq = tx_queue;
2184         hw = txq->hw;
2185         txds = &txq->txds[txq->wr_p];
2186
2187         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2188                    txq->qidx, txq->wr_p, nb_pkts);
2189
2190         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2191                 nfp_net_tx_free_bufs(txq);
2192
2193         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2194         if (unlikely(free_descs == 0))
2195                 return 0;
2196
2197         pkt = *tx_pkts;
2198
2199         i = 0;
2200         issued_descs = 0;
2201         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2202                    txq->qidx, nb_pkts);
2203         /* Sending packets */
2204         while ((i < nb_pkts) && free_descs) {
2205                 /* Grabbing the mbuf linked to the current descriptor */
2206                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2207                 /* Warming the cache for releasing the mbuf later on */
2208                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2209
2210                 pkt = *(tx_pkts + i);
2211
2212                 if (unlikely((pkt->nb_segs > 1) &&
2213                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2214                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2215                         rte_panic("Multisegment packet unsupported\n");
2216                 }
2217
2218                 /* Checking if we have enough descriptors */
2219                 if (unlikely(pkt->nb_segs > free_descs))
2220                         goto xmit_end;
2221
2222                 /*
2223                  * Checksum and VLAN flags just in the first descriptor for a
2224                  * multisegment packet, but TSO info needs to be in all of them.
2225                  */
2226                 txd.data_len = pkt->pkt_len;
2227                 nfp_net_tx_tso(txq, &txd, pkt);
2228                 nfp_net_tx_cksum(txq, &txd, pkt);
2229
2230                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2231                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2232                         txd.flags |= PCIE_DESC_TX_VLAN;
2233                         txd.vlan = pkt->vlan_tci;
2234                 }
2235
2236                 /*
2237                  * mbuf data_len is the data in one segment and pkt_len data
2238                  * in the whole packet. When the packet is just one segment,
2239                  * then data_len = pkt_len
2240                  */
2241                 pkt_size = pkt->pkt_len;
2242
2243                 while (pkt) {
2244                         /* Copying TSO, VLAN and cksum info */
2245                         *txds = txd;
2246
2247                         /* Releasing mbuf used by this descriptor previously*/
2248                         if (*lmbuf)
2249                                 rte_pktmbuf_free_seg(*lmbuf);
2250
2251                         /*
2252                          * Linking mbuf with descriptor for being released
2253                          * next time descriptor is used
2254                          */
2255                         *lmbuf = pkt;
2256
2257                         dma_size = pkt->data_len;
2258                         dma_addr = rte_mbuf_data_iova(pkt);
2259                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2260                                    "%" PRIx64 "", dma_addr);
2261
2262                         /* Filling descriptors fields */
2263                         txds->dma_len = dma_size;
2264                         txds->data_len = txd.data_len;
2265                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2266                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2267                         ASSERT(free_descs > 0);
2268                         free_descs--;
2269
2270                         txq->wr_p++;
2271                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2272                                 txq->wr_p = 0;
2273
2274                         pkt_size -= dma_size;
2275
2276                         /*
2277                          * Making the EOP, packets with just one segment
2278                          * the priority
2279                          */
2280                         if (likely(!pkt_size))
2281                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2282                         else
2283                                 txds->offset_eop = 0;
2284
2285                         pkt = pkt->next;
2286                         /* Referencing next free TX descriptor */
2287                         txds = &txq->txds[txq->wr_p];
2288                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2289                         issued_descs++;
2290                 }
2291                 i++;
2292         }
2293
2294 xmit_end:
2295         /* Increment write pointers. Force memory write before we let HW know */
2296         rte_wmb();
2297         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2298
2299         return i;
2300 }
2301
2302 static int
2303 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2304 {
2305         uint32_t new_ctrl, update;
2306         struct nfp_net_hw *hw;
2307         int ret;
2308
2309         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2310         new_ctrl = 0;
2311
2312         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2313             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2314                 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2315                         " ETH_VLAN_EXTEND_OFFLOAD");
2316
2317         /* Enable vlan strip if it is not configured yet */
2318         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2319             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2320                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2321
2322         /* Disable vlan strip just if it is configured */
2323         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2324             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2325                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2326
2327         if (new_ctrl == 0)
2328                 return 0;
2329
2330         update = NFP_NET_CFG_UPDATE_GEN;
2331
2332         ret = nfp_net_reconfig(hw, new_ctrl, update);
2333         if (!ret)
2334                 hw->ctrl = new_ctrl;
2335
2336         return ret;
2337 }
2338
2339 static int
2340 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2341                     struct rte_eth_rss_reta_entry64 *reta_conf,
2342                     uint16_t reta_size)
2343 {
2344         uint32_t reta, mask;
2345         int i, j;
2346         int idx, shift;
2347         struct nfp_net_hw *hw =
2348                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2349
2350         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2351                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2352                         "(%d) doesn't match the number hardware can supported "
2353                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2354                 return -EINVAL;
2355         }
2356
2357         /*
2358          * Update Redirection Table. There are 128 8bit-entries which can be
2359          * manage as 32 32bit-entries
2360          */
2361         for (i = 0; i < reta_size; i += 4) {
2362                 /* Handling 4 RSS entries per loop */
2363                 idx = i / RTE_RETA_GROUP_SIZE;
2364                 shift = i % RTE_RETA_GROUP_SIZE;
2365                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2366
2367                 if (!mask)
2368                         continue;
2369
2370                 reta = 0;
2371                 /* If all 4 entries were set, don't need read RETA register */
2372                 if (mask != 0xF)
2373                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2374
2375                 for (j = 0; j < 4; j++) {
2376                         if (!(mask & (0x1 << j)))
2377                                 continue;
2378                         if (mask != 0xF)
2379                                 /* Clearing the entry bits */
2380                                 reta &= ~(0xFF << (8 * j));
2381                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2382                 }
2383                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2384                               reta);
2385         }
2386         return 0;
2387 }
2388
2389 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2390 static int
2391 nfp_net_reta_update(struct rte_eth_dev *dev,
2392                     struct rte_eth_rss_reta_entry64 *reta_conf,
2393                     uint16_t reta_size)
2394 {
2395         struct nfp_net_hw *hw =
2396                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397         uint32_t update;
2398         int ret;
2399
2400         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2401                 return -EINVAL;
2402
2403         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2404         if (ret != 0)
2405                 return ret;
2406
2407         update = NFP_NET_CFG_UPDATE_RSS;
2408
2409         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2410                 return -EIO;
2411
2412         return 0;
2413 }
2414
2415  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2416 static int
2417 nfp_net_reta_query(struct rte_eth_dev *dev,
2418                    struct rte_eth_rss_reta_entry64 *reta_conf,
2419                    uint16_t reta_size)
2420 {
2421         uint8_t i, j, mask;
2422         int idx, shift;
2423         uint32_t reta;
2424         struct nfp_net_hw *hw;
2425
2426         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427
2428         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2429                 return -EINVAL;
2430
2431         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2432                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2433                         "(%d) doesn't match the number hardware can supported "
2434                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2435                 return -EINVAL;
2436         }
2437
2438         /*
2439          * Reading Redirection Table. There are 128 8bit-entries which can be
2440          * manage as 32 32bit-entries
2441          */
2442         for (i = 0; i < reta_size; i += 4) {
2443                 /* Handling 4 RSS entries per loop */
2444                 idx = i / RTE_RETA_GROUP_SIZE;
2445                 shift = i % RTE_RETA_GROUP_SIZE;
2446                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2447
2448                 if (!mask)
2449                         continue;
2450
2451                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2452                                     shift);
2453                 for (j = 0; j < 4; j++) {
2454                         if (!(mask & (0x1 << j)))
2455                                 continue;
2456                         reta_conf->reta[shift + j] =
2457                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2458                 }
2459         }
2460         return 0;
2461 }
2462
2463 static int
2464 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2465                         struct rte_eth_rss_conf *rss_conf)
2466 {
2467         struct nfp_net_hw *hw;
2468         uint64_t rss_hf;
2469         uint32_t cfg_rss_ctrl = 0;
2470         uint8_t key;
2471         int i;
2472
2473         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2474
2475         /* Writing the key byte a byte */
2476         for (i = 0; i < rss_conf->rss_key_len; i++) {
2477                 memcpy(&key, &rss_conf->rss_key[i], 1);
2478                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2479         }
2480
2481         rss_hf = rss_conf->rss_hf;
2482
2483         if (rss_hf & ETH_RSS_IPV4)
2484                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2485
2486         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2487                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2488
2489         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2490                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2491
2492         if (rss_hf & ETH_RSS_IPV6)
2493                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2494
2495         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2496                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2497
2498         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2499                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2500
2501         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2502         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2503
2504         /* configuring where to apply the RSS hash */
2505         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2506
2507         /* Writing the key size */
2508         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2509
2510         return 0;
2511 }
2512
2513 static int
2514 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2515                         struct rte_eth_rss_conf *rss_conf)
2516 {
2517         uint32_t update;
2518         uint64_t rss_hf;
2519         struct nfp_net_hw *hw;
2520
2521         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522
2523         rss_hf = rss_conf->rss_hf;
2524
2525         /* Checking if RSS is enabled */
2526         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2527                 if (rss_hf != 0) { /* Enable RSS? */
2528                         PMD_DRV_LOG(ERR, "RSS unsupported");
2529                         return -EINVAL;
2530                 }
2531                 return 0; /* Nothing to do */
2532         }
2533
2534         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2535                 PMD_DRV_LOG(ERR, "hash key too long");
2536                 return -EINVAL;
2537         }
2538
2539         nfp_net_rss_hash_write(dev, rss_conf);
2540
2541         update = NFP_NET_CFG_UPDATE_RSS;
2542
2543         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2544                 return -EIO;
2545
2546         return 0;
2547 }
2548
2549 static int
2550 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2551                           struct rte_eth_rss_conf *rss_conf)
2552 {
2553         uint64_t rss_hf;
2554         uint32_t cfg_rss_ctrl;
2555         uint8_t key;
2556         int i;
2557         struct nfp_net_hw *hw;
2558
2559         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560
2561         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2562                 return -EINVAL;
2563
2564         rss_hf = rss_conf->rss_hf;
2565         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2566
2567         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2568                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2569
2570         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2571                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2572
2573         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2574                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2575
2576         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2577                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2578
2579         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2580                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2581
2582         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2583                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2584
2585         /* Reading the key size */
2586         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2587
2588         /* Reading the key byte a byte */
2589         for (i = 0; i < rss_conf->rss_key_len; i++) {
2590                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2591                 memcpy(&rss_conf->rss_key[i], &key, 1);
2592         }
2593
2594         return 0;
2595 }
2596
2597 static int
2598 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2599 {
2600         struct rte_eth_conf *dev_conf;
2601         struct rte_eth_rss_conf rss_conf;
2602         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2603         uint16_t rx_queues = dev->data->nb_rx_queues;
2604         uint16_t queue;
2605         int i, j, ret;
2606
2607         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2608                 rx_queues);
2609
2610         nfp_reta_conf[0].mask = ~0x0;
2611         nfp_reta_conf[1].mask = ~0x0;
2612
2613         queue = 0;
2614         for (i = 0; i < 0x40; i += 8) {
2615                 for (j = i; j < (i + 8); j++) {
2616                         nfp_reta_conf[0].reta[j] = queue;
2617                         nfp_reta_conf[1].reta[j] = queue++;
2618                         queue %= rx_queues;
2619                 }
2620         }
2621         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2622         if (ret != 0)
2623                 return ret;
2624
2625         dev_conf = &dev->data->dev_conf;
2626         if (!dev_conf) {
2627                 PMD_DRV_LOG(INFO, "wrong rss conf");
2628                 return -EINVAL;
2629         }
2630         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2631
2632         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2633
2634         return ret;
2635 }
2636
2637
2638 /* Initialise and register driver with DPDK Application */
2639 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2640         .dev_configure          = nfp_net_configure,
2641         .dev_start              = nfp_net_start,
2642         .dev_stop               = nfp_net_stop,
2643         .dev_close              = nfp_net_close,
2644         .promiscuous_enable     = nfp_net_promisc_enable,
2645         .promiscuous_disable    = nfp_net_promisc_disable,
2646         .link_update            = nfp_net_link_update,
2647         .stats_get              = nfp_net_stats_get,
2648         .stats_reset            = nfp_net_stats_reset,
2649         .dev_infos_get          = nfp_net_infos_get,
2650         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2651         .mtu_set                = nfp_net_dev_mtu_set,
2652         .mac_addr_set           = nfp_set_mac_addr,
2653         .vlan_offload_set       = nfp_net_vlan_offload_set,
2654         .reta_update            = nfp_net_reta_update,
2655         .reta_query             = nfp_net_reta_query,
2656         .rss_hash_update        = nfp_net_rss_hash_update,
2657         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2658         .rx_queue_setup         = nfp_net_rx_queue_setup,
2659         .rx_queue_release       = nfp_net_rx_queue_release,
2660         .rx_queue_count         = nfp_net_rx_queue_count,
2661         .tx_queue_setup         = nfp_net_tx_queue_setup,
2662         .tx_queue_release       = nfp_net_tx_queue_release,
2663         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2664         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2665 };
2666
2667 /*
2668  * All eth_dev created got its private data, but before nfp_net_init, that
2669  * private data is referencing private data for all the PF ports. This is due
2670  * to how the vNIC bars are mapped based on first port, so all ports need info
2671  * about port 0 private data. Inside nfp_net_init the private data pointer is
2672  * changed to the right address for each port once the bars have been mapped.
2673  *
2674  * This functions helps to find out which port and therefore which offset
2675  * inside the private data array to use.
2676  */
2677 static int
2678 get_pf_port_number(char *name)
2679 {
2680         char *pf_str = name;
2681         int size = 0;
2682
2683         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2684                 pf_str++;
2685
2686         if (size == 30)
2687                 /*
2688                  * This should not happen at all and it would mean major
2689                  * implementation fault.
2690                  */
2691                 rte_panic("nfp_net: problem with pf device name\n");
2692
2693         /* Expecting _portX with X within [0,7] */
2694         pf_str += 5;
2695
2696         return (int)strtol(pf_str, NULL, 10);
2697 }
2698
2699 static int
2700 nfp_net_init(struct rte_eth_dev *eth_dev)
2701 {
2702         struct rte_pci_device *pci_dev;
2703         struct nfp_net_hw *hw, *hwport0;
2704
2705         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2706         uint32_t start_q;
2707         int stride = 4;
2708         int port = 0;
2709         int err;
2710
2711         PMD_INIT_FUNC_TRACE();
2712
2713         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2714
2715         /* NFP can not handle DMA addresses requiring more than 40 bits */
2716         if (rte_mem_check_dma_mask(40)) {
2717                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2718                                    pci_dev->device.name);
2719                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2720                 return -ENODEV;
2721         };
2722
2723         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2724             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2725                 port = get_pf_port_number(eth_dev->data->name);
2726                 if (port < 0 || port > 7) {
2727                         PMD_DRV_LOG(ERR, "Port value is wrong");
2728                         return -ENODEV;
2729                 }
2730
2731                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2732
2733                 /* This points to port 0 private data */
2734                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2735
2736                 /* This points to the specific port private data */
2737                 hw = &hwport0[port];
2738         } else {
2739                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2740                 hwport0 = 0;
2741         }
2742
2743         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2744         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2745         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2746
2747         /* For secondary processes, the primary has done all the work */
2748         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2749                 return 0;
2750
2751         rte_eth_copy_pci_info(eth_dev, pci_dev);
2752
2753         hw->device_id = pci_dev->id.device_id;
2754         hw->vendor_id = pci_dev->id.vendor_id;
2755         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2756         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2757
2758         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2759                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2760                      pci_dev->addr.domain, pci_dev->addr.bus,
2761                      pci_dev->addr.devid, pci_dev->addr.function);
2762
2763         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2764         if (hw->ctrl_bar == NULL) {
2765                 PMD_DRV_LOG(ERR,
2766                         "hw->ctrl_bar is NULL. BAR0 not configured");
2767                 return -ENODEV;
2768         }
2769
2770         if (hw->is_pf && port == 0) {
2771                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2772                                              hw->total_ports * 32768,
2773                                              &hw->ctrl_area);
2774                 if (!hw->ctrl_bar) {
2775                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2776                         return -EIO;
2777                 }
2778
2779                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2780         }
2781
2782         if (port > 0) {
2783                 if (!hwport0->ctrl_bar)
2784                         return -ENODEV;
2785
2786                 /* address based on port0 offset */
2787                 hw->ctrl_bar = hwport0->ctrl_bar +
2788                                (port * NFP_PF_CSR_SLICE_SIZE);
2789         }
2790
2791         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2792
2793         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2794         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2795
2796         /* Work out where in the BAR the queues start. */
2797         switch (pci_dev->id.device_id) {
2798         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2799         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2800         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2801                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2802                 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2803                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2804                 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2805                 break;
2806         default:
2807                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2808                 err = -ENODEV;
2809                 goto dev_err_ctrl_map;
2810         }
2811
2812         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2813         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2814
2815         if (hw->is_pf && port == 0) {
2816                 /* configure access to tx/rx vNIC BARs */
2817                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2818                                                       NFP_PCIE_QUEUE(0),
2819                                                       NFP_QCP_QUEUE_AREA_SZ,
2820                                                       &hw->hwqueues_area);
2821
2822                 if (!hwport0->hw_queues) {
2823                         printf("nfp_rtsym_map fails for net.qc");
2824                         err = -EIO;
2825                         goto dev_err_ctrl_map;
2826                 }
2827
2828                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2829                                     hwport0->hw_queues);
2830         }
2831
2832         if (hw->is_pf) {
2833                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2834                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2835                 eth_dev->data->dev_private = hw;
2836         } else {
2837                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2838                              tx_bar_off;
2839                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2840                              rx_bar_off;
2841         }
2842
2843         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2844                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2845
2846         nfp_net_cfg_queue_setup(hw);
2847
2848         /* Get some of the read-only fields from the config BAR */
2849         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2850         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2851         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2852         hw->mtu = ETHER_MTU;
2853
2854         /* VLAN insertion is incompatible with LSOv2 */
2855         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2856                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2857
2858         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2859                 hw->rx_offset = NFP_NET_RX_OFFSET;
2860         else
2861                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2862
2863         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2864                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2865                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2866
2867         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2868                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2869                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2870                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2871                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2872                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2873                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2874                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2875                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2876                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2877                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2878                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2879                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2880                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2881                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2882
2883         hw->ctrl = 0;
2884
2885         hw->stride_rx = stride;
2886         hw->stride_tx = stride;
2887
2888         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2889                      hw->max_rx_queues, hw->max_tx_queues);
2890
2891         /* Initializing spinlock for reconfigs */
2892         rte_spinlock_init(&hw->reconfig_lock);
2893
2894         /* Allocating memory for mac addr */
2895         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2896         if (eth_dev->data->mac_addrs == NULL) {
2897                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2898                 err = -ENOMEM;
2899                 goto dev_err_queues_map;
2900         }
2901
2902         if (hw->is_pf) {
2903                 nfp_net_pf_read_mac(hwport0, port);
2904                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2905         } else {
2906                 nfp_net_vf_read_mac(hw);
2907         }
2908
2909         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2910                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2911                                    port);
2912                 /* Using random mac addresses for VFs */
2913                 eth_random_addr(&hw->mac_addr[0]);
2914                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2915         }
2916
2917         /* Copying mac address to DPDK eth_dev struct */
2918         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2919                         &eth_dev->data->mac_addrs[0]);
2920
2921         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2922                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2923
2924         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2925                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2926                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2927                      pci_dev->id.device_id,
2928                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2929                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2930
2931         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2932                 /* Registering LSC interrupt handler */
2933                 rte_intr_callback_register(&pci_dev->intr_handle,
2934                                            nfp_net_dev_interrupt_handler,
2935                                            (void *)eth_dev);
2936                 /* Telling the firmware about the LSC interrupt entry */
2937                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2938                 /* Recording current stats counters values */
2939                 nfp_net_stats_reset(eth_dev);
2940         }
2941
2942         return 0;
2943
2944 dev_err_queues_map:
2945                 nfp_cpp_area_free(hw->hwqueues_area);
2946 dev_err_ctrl_map:
2947                 nfp_cpp_area_free(hw->ctrl_area);
2948
2949         return err;
2950 }
2951
2952 static int
2953 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2954                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
2955                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
2956 {
2957         struct rte_eth_dev *eth_dev;
2958         struct nfp_net_hw *hw;
2959         char *port_name;
2960         int retval;
2961
2962         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2963         if (!port_name)
2964                 return -ENOMEM;
2965
2966         if (ports > 1)
2967                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2968         else
2969                 sprintf(port_name, "%s", dev->device.name);
2970
2971
2972         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2973                 eth_dev = rte_eth_dev_allocate(port_name);
2974                 if (!eth_dev) {
2975                         rte_free(port_name);
2976                         return -ENODEV;
2977                 }
2978                 if (port == 0) {
2979                         *priv = rte_zmalloc(port_name,
2980                                             sizeof(struct nfp_net_adapter) *
2981                                             ports, RTE_CACHE_LINE_SIZE);
2982                         if (!*priv) {
2983                                 rte_free(port_name);
2984                                 rte_eth_dev_release_port(eth_dev);
2985                                 return -ENOMEM;
2986                         }
2987                 }
2988                 eth_dev->data->dev_private = *priv;
2989
2990                 /*
2991                  * dev_private pointing to port0 dev_private because we need
2992                  * to configure vNIC bars based on port0 at nfp_net_init.
2993                  * Then dev_private is adjusted per port.
2994                  */
2995                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2996                 hw->cpp = cpp;
2997                 hw->hwinfo = hwinfo;
2998                 hw->sym_tbl = sym_tbl;
2999                 hw->pf_port_idx = phys_port;
3000                 hw->is_pf = 1;
3001                 if (ports > 1)
3002                         hw->pf_multiport_enabled = 1;
3003
3004                 hw->total_ports = ports;
3005         } else {
3006                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3007                 if (!eth_dev) {
3008                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3009                                 "ethdev doesn't exist");
3010                         rte_free(port_name);
3011                         return -ENODEV;
3012                 }
3013                 eth_dev->process_private = cpp;
3014         }
3015
3016         eth_dev->device = &dev->device;
3017         rte_eth_copy_pci_info(eth_dev, dev);
3018
3019         retval = nfp_net_init(eth_dev);
3020
3021         if (retval) {
3022                 retval = -ENODEV;
3023                 goto probe_failed;
3024         } else {
3025                 rte_eth_dev_probing_finish(eth_dev);
3026         }
3027
3028         rte_free(port_name);
3029
3030         return retval;
3031
3032 probe_failed:
3033         rte_free(port_name);
3034         /* free ports private data if primary process */
3035         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3036                 rte_free(eth_dev->data->dev_private);
3037
3038         rte_eth_dev_release_port(eth_dev);
3039
3040         return retval;
3041 }
3042
3043 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3044
3045 static int
3046 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3047 {
3048         struct nfp_cpp *cpp = nsp->cpp;
3049         int fw_f;
3050         char *fw_buf;
3051         char fw_name[125];
3052         char serial[40];
3053         struct stat file_stat;
3054         off_t fsize, bytes;
3055
3056         /* Looking for firmware file in order of priority */
3057
3058         /* First try to find a firmware image specific for this device */
3059         sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3060                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3061                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3062                 cpp->interface & 0xff);
3063
3064         sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3065
3066         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3067         fw_f = open(fw_name, O_RDONLY);
3068         if (fw_f > 0)
3069                 goto read_fw;
3070
3071         /* Then try the PCI name */
3072         sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3073
3074         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3075         fw_f = open(fw_name, O_RDONLY);
3076         if (fw_f > 0)
3077                 goto read_fw;
3078
3079         /* Finally try the card type and media */
3080         sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3081         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3082         fw_f = open(fw_name, O_RDONLY);
3083         if (fw_f < 0) {
3084                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3085                 return -ENOENT;
3086         }
3087
3088 read_fw:
3089         if (fstat(fw_f, &file_stat) < 0) {
3090                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3091                 close(fw_f);
3092                 return -ENOENT;
3093         }
3094
3095         fsize = file_stat.st_size;
3096         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3097                             fw_name, (uint64_t)fsize);
3098
3099         fw_buf = malloc((size_t)fsize);
3100         if (!fw_buf) {
3101                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3102                 close(fw_f);
3103                 return -ENOMEM;
3104         }
3105         memset(fw_buf, 0, fsize);
3106
3107         bytes = read(fw_f, fw_buf, fsize);
3108         if (bytes != fsize) {
3109                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3110                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3111                                    (uint64_t)bytes, (uint64_t)fsize);
3112                 free(fw_buf);
3113                 close(fw_f);
3114                 return -EIO;
3115         }
3116
3117         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3118         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3119         PMD_DRV_LOG(INFO, "Done");
3120
3121         free(fw_buf);
3122         close(fw_f);
3123
3124         return 0;
3125 }
3126
3127 static int
3128 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3129              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3130 {
3131         struct nfp_nsp *nsp;
3132         const char *nfp_fw_model;
3133         char card_desc[100];
3134         int err = 0;
3135
3136         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3137
3138         if (nfp_fw_model) {
3139                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3140         } else {
3141                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3142                 return -EIO;
3143         }
3144
3145         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3146                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3147                        nfp_eth_table->count);
3148                 return -EIO;
3149         }
3150
3151         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3152                            nfp_eth_table->count);
3153
3154         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3155
3156         sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3157                 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3158
3159         nsp = nfp_nsp_open(cpp);
3160         if (!nsp) {
3161                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3162                 return -EIO;
3163         }
3164
3165         nfp_nsp_device_soft_reset(nsp);
3166         err = nfp_fw_upload(dev, nsp, card_desc);
3167
3168         nfp_nsp_close(nsp);
3169         return err;
3170 }
3171
3172 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3173                             struct rte_pci_device *dev)
3174 {
3175         struct nfp_cpp *cpp;
3176         struct nfp_hwinfo *hwinfo;
3177         struct nfp_rtsym_table *sym_tbl;
3178         struct nfp_eth_table *nfp_eth_table = NULL;
3179         int total_ports;
3180         void *priv = 0;
3181         int ret = -ENODEV;
3182         int err;
3183         int i;
3184
3185         if (!dev)
3186                 return ret;
3187
3188         /*
3189          * When device bound to UIO, the device could be used, by mistake,
3190          * by two DPDK apps, and the UIO driver does not avoid it. This
3191          * could lead to a serious problem when configuring the NFP CPP
3192          * interface. Here we avoid this telling to the CPP init code to
3193          * use a lock file if UIO is being used.
3194          */
3195         if (dev->kdrv == RTE_KDRV_VFIO)
3196                 cpp = nfp_cpp_from_device_name(dev, 0);
3197         else
3198                 cpp = nfp_cpp_from_device_name(dev, 1);
3199
3200         if (!cpp) {
3201                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3202                 ret = -EIO;
3203                 goto error;
3204         }
3205
3206         hwinfo = nfp_hwinfo_read(cpp);
3207         if (!hwinfo) {
3208                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3209                 return -EIO;
3210         }
3211
3212         nfp_eth_table = nfp_eth_read_ports(cpp);
3213         if (!nfp_eth_table) {
3214                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3215                 return -EIO;
3216         }
3217
3218         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3219                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3220                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3221                         ret = -EIO;
3222                         goto error;
3223                 }
3224         }
3225
3226         /* Now the symbol table should be there */
3227         sym_tbl = nfp_rtsym_table_read(cpp);
3228         if (!sym_tbl) {
3229                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3230                                 " symbol table");
3231                 ret = -EIO;
3232                 goto error;
3233         }
3234
3235         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3236         if (total_ports != (int)nfp_eth_table->count) {
3237                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3238                 ret = -EIO;
3239                 goto error;
3240         }
3241         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3242
3243         if (total_ports <= 0 || total_ports > 8) {
3244                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3245                 ret = -ENODEV;
3246                 goto error;
3247         }
3248
3249         for (i = 0; i < total_ports; i++) {
3250                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3251                                         nfp_eth_table->ports[i].index,
3252                                         sym_tbl, &priv);
3253                 if (ret)
3254                         break;
3255         }
3256
3257 error:
3258         free(nfp_eth_table);
3259         return ret;
3260 }
3261
3262 int nfp_logtype_init;
3263 int nfp_logtype_driver;
3264
3265 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3266         {
3267                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3268                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3269         },
3270         {
3271                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3272                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3273         },
3274         {
3275                 .vendor_id = 0,
3276         },
3277 };
3278
3279 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3280         {
3281                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3282                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3283         },
3284         {
3285                 .vendor_id = 0,
3286         },
3287 };
3288
3289 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3290         struct rte_pci_device *pci_dev)
3291 {
3292         return rte_eth_dev_pci_generic_probe(pci_dev,
3293                 sizeof(struct nfp_net_adapter), nfp_net_init);
3294 }
3295
3296 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3297 {
3298         struct rte_eth_dev *eth_dev;
3299         struct nfp_net_hw *hw, *hwport0;
3300         int port = 0;
3301
3302         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3303         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3304             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3305                 port = get_pf_port_number(eth_dev->data->name);
3306                 /*
3307                  * hotplug is not possible with multiport PF although freeing
3308                  * data structures can be done for first port.
3309                  */
3310                 if (port != 0)
3311                         return -ENOTSUP;
3312                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3313                 hw = &hwport0[port];
3314                 nfp_cpp_area_free(hw->ctrl_area);
3315                 nfp_cpp_area_free(hw->hwqueues_area);
3316                 free(hw->hwinfo);
3317                 free(hw->sym_tbl);
3318                 nfp_cpp_free(hw->cpp);
3319         } else {
3320                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3321         }
3322         /* hotplug is not possible with multiport PF */
3323         if (hw->pf_multiport_enabled)
3324                 return -ENOTSUP;
3325         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3326 }
3327
3328 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3329         .id_table = pci_id_nfp_pf_net_map,
3330         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3331                      RTE_PCI_DRV_IOVA_AS_VA,
3332         .probe = nfp_pf_pci_probe,
3333         .remove = eth_nfp_pci_remove,
3334 };
3335
3336 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3337         .id_table = pci_id_nfp_vf_net_map,
3338         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3339                      RTE_PCI_DRV_IOVA_AS_VA,
3340         .probe = eth_nfp_pci_probe,
3341         .remove = eth_nfp_pci_remove,
3342 };
3343
3344 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3345 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3346 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3347 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3348 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3349 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3350
3351 RTE_INIT(nfp_init_log)
3352 {
3353         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3354         if (nfp_logtype_init >= 0)
3355                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3356         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3357         if (nfp_logtype_driver >= 0)
3358                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3359 }
3360 /*
3361  * Local variables:
3362  * c-file-style: "Linux"
3363  * indent-tabs-mode: t
3364  * End:
3365  */