drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfpcore/nfp_cpp.h"
  59 #include "nfpcore/nfp_nffw.h"
  60 #include "nfpcore/nfp_hwinfo.h"
  61 #include "nfpcore/nfp_mip.h"
  62 #include "nfpcore/nfp_rtsym.h"
  63 #include "nfpcore/nfp_nsp.h"
  64
  65 #include "nfp_net_pmd.h"
  66 #include "nfp_net_logs.h"
  67 #include "nfp_net_ctrl.h"
  68
  69 /* Prototypes */
  70 static void nfp_net_close(struct rte_eth_dev *dev);
  71 static int nfp_net_configure(struct rte_eth_dev *dev);
  72 static void nfp_net_dev_interrupt_handler(void *param);
  73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  76                               struct rte_eth_dev_info *dev_info);
  77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  83                                        uint16_t queue_idx);
  84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  85                                   uint16_t nb_pkts);
  86 static void nfp_net_rx_queue_release(void *rxq);
  87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_rxconf *rx_conf,
  90                                   struct rte_mempool *mp);
  91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  92 static void nfp_net_tx_queue_release(void *txq);
  93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  94                                   uint16_t nb_desc, unsigned int socket_id,
  95                                   const struct rte_eth_txconf *tx_conf);
  96 static int nfp_net_start(struct rte_eth_dev *dev);
  97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  98                               struct rte_eth_stats *stats);
  99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
 100 static void nfp_net_stop(struct rte_eth_dev *dev);
 101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 102                                   uint16_t nb_pkts);
 103
 104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
 105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 106                                    struct rte_eth_rss_conf *rss_conf);
 107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 108                     struct rte_eth_rss_reta_entry64 *reta_conf,
 109                     uint16_t reta_size);
 110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 111                         struct rte_eth_rss_conf *rss_conf);
 112 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
 113                              struct ether_addr *mac_addr);
 114
 115 /* The offset of the queue controller queues in the PCIe Target */
 116 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 117
 118 /* Maximum value which can be added to a queue with one transaction */
 119 #define NFP_QCP_MAX_ADD 0x7f
 120
 121 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 122         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 123
 124 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 125 enum nfp_qcp_ptr {
 126         NFP_QCP_READ_PTR = 0,
 127         NFP_QCP_WRITE_PTR
 128 };
 129
 130 /*
 131  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 132  * @q: Base address for queue structure
 133  * @ptr: Add to the Read or Write pointer
 134  * @val: Value to add to the queue pointer
 135  *
 136  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 137  */
 138 static inline void
 139 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 140 {
 141         uint32_t off;
 142
 143         if (ptr == NFP_QCP_READ_PTR)
 144                 off = NFP_QCP_QUEUE_ADD_RPTR;
 145         else
 146                 off = NFP_QCP_QUEUE_ADD_WPTR;
 147
 148         while (val > NFP_QCP_MAX_ADD) {
 149                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 150                 val -= NFP_QCP_MAX_ADD;
 151         }
 152
 153         nn_writel(rte_cpu_to_le_32(val), q + off);
 154 }
 155
 156 /*
 157  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 158  * @q:  Base address for queue structure
 159  * @ptr: Read or Write pointer
 160  */
 161 static inline uint32_t
 162 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 163 {
 164         uint32_t off;
 165         uint32_t val;
 166
 167         if (ptr == NFP_QCP_READ_PTR)
 168                 off = NFP_QCP_QUEUE_STS_LO;
 169         else
 170                 off = NFP_QCP_QUEUE_STS_HI;
 171
 172         val = rte_cpu_to_le_32(nn_readl(q + off));
 173
 174         if (ptr == NFP_QCP_READ_PTR)
 175                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 176         else
 177                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 178 }
 179
 180 /*
 181  * Functions to read/write from/to Config BAR
 182  * Performs any endian conversion necessary.
 183  */
 184 static inline uint8_t
 185 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 186 {
 187         return nn_readb(hw->ctrl_bar + off);
 188 }
 189
 190 static inline void
 191 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 192 {
 193         nn_writeb(val, hw->ctrl_bar + off);
 194 }
 195
 196 static inline uint32_t
 197 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 198 {
 199         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 200 }
 201
 202 static inline void
 203 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 204 {
 205         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 206 }
 207
 208 static inline uint64_t
 209 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 210 {
 211         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 212 }
 213
 214 static inline void
 215 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 216 {
 217         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 218 }
 219
 220 static void
 221 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 222 {
 223         unsigned i;
 224
 225         if (rxq->rxbufs == NULL)
 226                 return;
 227
 228         for (i = 0; i < rxq->rx_count; i++) {
 229                 if (rxq->rxbufs[i].mbuf) {
 230                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 231                         rxq->rxbufs[i].mbuf = NULL;
 232                 }
 233         }
 234 }
 235
 236 static void
 237 nfp_net_rx_queue_release(void *rx_queue)
 238 {
 239         struct nfp_net_rxq *rxq = rx_queue;
 240
 241         if (rxq) {
 242                 nfp_net_rx_queue_release_mbufs(rxq);
 243                 rte_free(rxq->rxbufs);
 244                 rte_free(rxq);
 245         }
 246 }
 247
 248 static void
 249 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 250 {
 251         nfp_net_rx_queue_release_mbufs(rxq);
 252         rxq->rd_p = 0;
 253         rxq->nb_rx_hold = 0;
 254 }
 255
 256 static void
 257 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 258 {
 259         unsigned i;
 260
 261         if (txq->txbufs == NULL)
 262                 return;
 263
 264         for (i = 0; i < txq->tx_count; i++) {
 265                 if (txq->txbufs[i].mbuf) {
 266                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 267                         txq->txbufs[i].mbuf = NULL;
 268                 }
 269         }
 270 }
 271
 272 static void
 273 nfp_net_tx_queue_release(void *tx_queue)
 274 {
 275         struct nfp_net_txq *txq = tx_queue;
 276
 277         if (txq) {
 278                 nfp_net_tx_queue_release_mbufs(txq);
 279                 rte_free(txq->txbufs);
 280                 rte_free(txq);
 281         }
 282 }
 283
 284 static void
 285 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 286 {
 287         nfp_net_tx_queue_release_mbufs(txq);
 288         txq->wr_p = 0;
 289         txq->rd_p = 0;
 290 }
 291
 292 static int
 293 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 294 {
 295         int cnt;
 296         uint32_t new;
 297         struct timespec wait;
 298
 299         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 300                     hw->qcp_cfg);
 301
 302         if (hw->qcp_cfg == NULL)
 303                 rte_panic("Bad configuration queue pointer\n");
 304
 305         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 306
 307         wait.tv_sec = 0;
 308         wait.tv_nsec = 1000000;
 309
 310         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 311
 312         /* Poll update field, waiting for NFP to ack the config */
 313         for (cnt = 0; ; cnt++) {
 314                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 315                 if (new == 0)
 316                         break;
 317                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 318                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 319                         return -1;
 320                 }
 321                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 322                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 323                                           " %dms", update, cnt);
 324                         rte_panic("Exiting\n");
 325                 }
 326                 nanosleep(&wait, 0); /* waiting for a 1ms */
 327         }
 328         PMD_DRV_LOG(DEBUG, "Ack DONE");
 329         return 0;
 330 }
 331
 332 /*
 333  * Reconfigure the NIC
 334  * @nn:    device to reconfigure
 335  * @ctrl:    The value for the ctrl field in the BAR config
 336  * @update:  The value for the update field in the BAR config
 337  *
 338  * Write the update word to the BAR and ping the reconfig queue. Then poll
 339  * until the firmware has acknowledged the update by zeroing the update word.
 340  */
 341 static int
 342 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 343 {
 344         uint32_t err;
 345
 346         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 347                     ctrl, update);
 348
 349         rte_spinlock_lock(&hw->reconfig_lock);
 350
 351         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 352         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 353
 354         rte_wmb();
 355
 356         err = __nfp_net_reconfig(hw, update);
 357
 358         rte_spinlock_unlock(&hw->reconfig_lock);
 359
 360         if (!err)
 361                 return 0;
 362
 363         /*
 364          * Reconfig errors imply situations where they can be handled.
 365          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 366          */
 367         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 368                      ctrl, update);
 369         return -EIO;
 370 }
 371
 372 /*
 373  * Configure an Ethernet device. This function must be invoked first
 374  * before any other function in the Ethernet API. This function can
 375  * also be re-invoked when a device is in the stopped state.
 376  */
 377 static int
 378 nfp_net_configure(struct rte_eth_dev *dev)
 379 {
 380         struct rte_eth_conf *dev_conf;
 381         struct rte_eth_rxmode *rxmode;
 382         struct rte_eth_txmode *txmode;
 383         struct nfp_net_hw *hw;
 384
 385         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 386
 387         /*
 388          * A DPDK app sends info about how many queues to use and how
 389          * those queues need to be configured. This is used by the
 390          * DPDK core and it makes sure no more queues than those
 391          * advertised by the driver are requested. This function is
 392          * called after that internal process
 393          */
 394
 395         PMD_INIT_LOG(DEBUG, "Configure");
 396
 397         dev_conf = &dev->data->dev_conf;
 398         rxmode = &dev_conf->rxmode;
 399         txmode = &dev_conf->txmode;
 400
 401         /* Checking TX mode */
 402         if (txmode->mq_mode) {
 403                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 404                 return -EINVAL;
 405         }
 406
 407         /* Checking RX mode */
 408         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 409             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 410                 PMD_INIT_LOG(INFO, "RSS not supported");
 411                 return -EINVAL;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static void
 418 nfp_net_enable_queues(struct rte_eth_dev *dev)
 419 {
 420         struct nfp_net_hw *hw;
 421         uint64_t enabled_queues = 0;
 422         int i;
 423
 424         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 425
 426         /* Enabling the required TX queues in the device */
 427         for (i = 0; i < dev->data->nb_tx_queues; i++)
 428                 enabled_queues |= (1 << i);
 429
 430         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 431
 432         enabled_queues = 0;
 433
 434         /* Enabling the required RX queues in the device */
 435         for (i = 0; i < dev->data->nb_rx_queues; i++)
 436                 enabled_queues |= (1 << i);
 437
 438         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 439 }
 440
 441 static void
 442 nfp_net_disable_queues(struct rte_eth_dev *dev)
 443 {
 444         struct nfp_net_hw *hw;
 445         uint32_t new_ctrl, update = 0;
 446
 447         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 448
 449         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 450         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 451
 452         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 453         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 454                  NFP_NET_CFG_UPDATE_MSIX;
 455
 456         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 457                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 458
 459         /* If an error when reconfig we avoid to change hw state */
 460         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 461                 return;
 462
 463         hw->ctrl = new_ctrl;
 464 }
 465
 466 static int
 467 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 468 {
 469         int i;
 470
 471         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 472                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 473                         return -1;
 474         }
 475         return 0;
 476 }
 477
 478 static void
 479 nfp_net_params_setup(struct nfp_net_hw *hw)
 480 {
 481         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 482         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 483 }
 484
 485 static void
 486 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 487 {
 488         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 489 }
 490
 491 #define ETH_ADDR_LEN    6
 492
 493 static void
 494 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 495 {
 496         int i;
 497
 498         for (i = 0; i < ETH_ADDR_LEN; i++)
 499                 dst[i] = src[i];
 500 }
 501
 502 static int
 503 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 504 {
 505         struct nfp_eth_table *nfp_eth_table;
 506
 507         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 508         /*
 509          * hw points to port0 private data. We need hw now pointing to
 510          * right port.
 511          */
 512         hw += port;
 513         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 514                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 515
 516         free(nfp_eth_table);
 517         return 0;
 518 }
 519
 520 static void
 521 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 522 {
 523         uint32_t tmp;
 524
 525         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 526         memcpy(&hw->mac_addr[0], &tmp, 4);
 527
 528         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 529         memcpy(&hw->mac_addr[4], &tmp, 2);
 530 }
 531
 532 static void
 533 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 534 {
 535         uint32_t mac0 = *(uint32_t *)mac;
 536         uint16_t mac1;
 537
 538         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 539
 540         mac += 4;
 541         mac1 = *(uint16_t *)mac;
 542         nn_writew(rte_cpu_to_be_16(mac1),
 543                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 544 }
 545
 546 int
 547 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 548 {
 549         struct nfp_net_hw *hw;
 550         uint32_t update, ctrl;
 551
 552         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 554             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 555                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 556                                   " port enabled");
 557                 return -EBUSY;
 558         }
 559
 560         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 561             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 562                 return -EBUSY;
 563
 564         /* Writing new MAC to the specific port BAR address */
 565         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 566
 567         /* Signal the NIC about the change */
 568         update = NFP_NET_CFG_UPDATE_MACADDR;
 569         ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR;
 570         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 571                 PMD_INIT_LOG(INFO, "MAC address update failed");
 572                 return -EIO;
 573         }
 574         return 0;
 575 }
 576
 577 static int
 578 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 579                            struct rte_intr_handle *intr_handle)
 580 {
 581         struct nfp_net_hw *hw;
 582         int i;
 583
 584         if (!intr_handle->intr_vec) {
 585                 intr_handle->intr_vec =
 586                         rte_zmalloc("intr_vec",
 587                                     dev->data->nb_rx_queues * sizeof(int), 0);
 588                 if (!intr_handle->intr_vec) {
 589                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 590                                      " intr_vec", dev->data->nb_rx_queues);
 591                         return -ENOMEM;
 592                 }
 593         }
 594
 595         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 596
 597         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 598                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 599                 /* UIO just supports one queue and no LSC*/
 600                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 601                 intr_handle->intr_vec[0] = 0;
 602         } else {
 603                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 604                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 605                         /*
 606                          * The first msix vector is reserved for non
 607                          * efd interrupts
 608                         */
 609                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 610                         intr_handle->intr_vec[i] = i + 1;
 611                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 612                                             intr_handle->intr_vec[i]);
 613                 }
 614         }
 615
 616         /* Avoiding TX interrupts */
 617         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 618         return 0;
 619 }
 620
 621 static uint32_t
 622 nfp_check_offloads(struct rte_eth_dev *dev)
 623 {
 624         struct nfp_net_hw *hw;
 625         struct rte_eth_conf *dev_conf;
 626         struct rte_eth_rxmode *rxmode;
 627         struct rte_eth_txmode *txmode;
 628         uint32_t ctrl = 0;
 629
 630         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632         dev_conf = &dev->data->dev_conf;
 633         rxmode = &dev_conf->rxmode;
 634         txmode = &dev_conf->txmode;
 635
 636         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 637                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 638                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 639         }
 640
 641         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 642                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 643                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 644         }
 645
 646         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 647                 hw->mtu = rxmode->max_rx_pkt_len;
 648
 649         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 650                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 651
 652         /* L2 broadcast */
 653         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 654                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 655
 656         /* L2 multicast */
 657         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 658                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 659
 660         /* TX checksum offload */
 661         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 662             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 663             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 664                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 665
 666         /* LSO offload */
 667         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 668                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 669                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 670                 else
 671                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 672         }
 673
 674         /* RX gather */
 675         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 676                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 677
 678         return ctrl;
 679 }
 680
 681 static int
 682 nfp_net_start(struct rte_eth_dev *dev)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t new_ctrl, update = 0;
 687         struct nfp_net_hw *hw;
 688         struct rte_eth_conf *dev_conf;
 689         struct rte_eth_rxmode *rxmode;
 690         uint32_t intr_vector;
 691         int ret;
 692
 693         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 694
 695         PMD_INIT_LOG(DEBUG, "Start");
 696
 697         /* Disabling queues just in case... */
 698         nfp_net_disable_queues(dev);
 699
 700         /* Enabling the required queues in the device */
 701         nfp_net_enable_queues(dev);
 702
 703         /* check and configure queue intr-vector mapping */
 704         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 705                 if (hw->pf_multiport_enabled) {
 706                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 707                                           "with NFP multiport PF");
 708                                 return -EINVAL;
 709                 }
 710                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 711                         /*
 712                          * Better not to share LSC with RX interrupts.
 713                          * Unregistering LSC interrupt handler
 714                          */
 715                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 716                                 nfp_net_dev_interrupt_handler, (void *)dev);
 717
 718                         if (dev->data->nb_rx_queues > 1) {
 719                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 720                                              "supports 1 queue with UIO");
 721                                 return -EIO;
 722                         }
 723                 }
 724                 intr_vector = dev->data->nb_rx_queues;
 725                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 726                         return -1;
 727
 728                 nfp_configure_rx_interrupt(dev, intr_handle);
 729                 update = NFP_NET_CFG_UPDATE_MSIX;
 730         }
 731
 732         rte_intr_enable(intr_handle);
 733
 734         new_ctrl = nfp_check_offloads(dev);
 735
 736         /* Writing configuration parameters in the device */
 737         nfp_net_params_setup(hw);
 738
 739         dev_conf = &dev->data->dev_conf;
 740         rxmode = &dev_conf->rxmode;
 741
 742         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 743                 nfp_net_rss_config_default(dev);
 744                 update |= NFP_NET_CFG_UPDATE_RSS;
 745                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 746         }
 747
 748         /* Enable device */
 749         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 750
 751         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 752
 753         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 754                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 755
 756         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 757         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 758                 return -EIO;
 759
 760         /*
 761          * Allocating rte mbuffs for configured rx queues.
 762          * This requires queues being enabled before
 763          */
 764         if (nfp_net_rx_freelist_setup(dev) < 0) {
 765                 ret = -ENOMEM;
 766                 goto error;
 767         }
 768
 769         if (hw->is_pf && rte_eal_process_type() == RTE_PROC_PRIMARY)
 770                 /* Configure the physical port up */
 771                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 772         else
 773                 nfp_eth_set_configured(dev->process_private,
 774                                        hw->pf_port_idx, 1);
 775
 776         hw->ctrl = new_ctrl;
 777
 778         return 0;
 779
 780 error:
 781         /*
 782          * An error returned by this function should mean the app
 783          * exiting and then the system releasing all the memory
 784          * allocated even memory coming from hugepages.
 785          *
 786          * The device could be enabled at this point with some queues
 787          * ready for getting packets. This is true if the call to
 788          * nfp_net_rx_freelist_setup() succeeds for some queues but
 789          * fails for subsequent queues.
 790          *
 791          * This should make the app exiting but better if we tell the
 792          * device first.
 793          */
 794         nfp_net_disable_queues(dev);
 795
 796         return ret;
 797 }
 798
 799 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 800 static void
 801 nfp_net_stop(struct rte_eth_dev *dev)
 802 {
 803         int i;
 804         struct nfp_net_hw *hw;
 805
 806         PMD_INIT_LOG(DEBUG, "Stop");
 807
 808         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 809
 810         nfp_net_disable_queues(dev);
 811
 812         /* Clear queues */
 813         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 814                 nfp_net_reset_tx_queue(
 815                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 816         }
 817
 818         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 819                 nfp_net_reset_rx_queue(
 820                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 821         }
 822
 823         if (hw->is_pf && rte_eal_process_type() == RTE_PROC_PRIMARY)
 824                 /* Configure the physical port down */
 825                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 826         else
 827                 nfp_eth_set_configured(dev->process_private,
 828                                        hw->pf_port_idx, 0);
 829 }
 830
 831 /* Reset and stop device. The device can not be restarted. */
 832 static void
 833 nfp_net_close(struct rte_eth_dev *dev)
 834 {
 835         struct nfp_net_hw *hw;
 836         struct rte_pci_device *pci_dev;
 837         int i;
 838
 839         PMD_INIT_LOG(DEBUG, "Close");
 840
 841         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 842         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 843
 844         /*
 845          * We assume that the DPDK application is stopping all the
 846          * threads/queues before calling the device close function.
 847          */
 848
 849         nfp_net_disable_queues(dev);
 850
 851         /* Clear queues */
 852         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 853                 nfp_net_reset_tx_queue(
 854                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 855         }
 856
 857         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 858                 nfp_net_reset_rx_queue(
 859                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 860         }
 861
 862         rte_intr_disable(&pci_dev->intr_handle);
 863         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 864
 865         /* unregister callback func from eal lib */
 866         rte_intr_callback_unregister(&pci_dev->intr_handle,
 867                                      nfp_net_dev_interrupt_handler,
 868                                      (void *)dev);
 869
 870         /*
 871          * The ixgbe PMD driver disables the pcie master on the
 872          * device. The i40e does not...
 873          */
 874 }
 875
 876 static void
 877 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 878 {
 879         uint32_t new_ctrl, update = 0;
 880         struct nfp_net_hw *hw;
 881
 882         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 883
 884         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 885
 886         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 887                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 888                 return;
 889         }
 890
 891         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 892                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 893                 return;
 894         }
 895
 896         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 897         update = NFP_NET_CFG_UPDATE_GEN;
 898
 899         /*
 900          * DPDK sets promiscuous mode on just after this call assuming
 901          * it can not fail ...
 902          */
 903         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 904                 return;
 905
 906         hw->ctrl = new_ctrl;
 907 }
 908
 909 static void
 910 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 911 {
 912         uint32_t new_ctrl, update = 0;
 913         struct nfp_net_hw *hw;
 914
 915         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916
 917         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 918                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 919                 return;
 920         }
 921
 922         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 923         update = NFP_NET_CFG_UPDATE_GEN;
 924
 925         /*
 926          * DPDK sets promiscuous mode off just before this call
 927          * assuming it can not fail ...
 928          */
 929         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 930                 return;
 931
 932         hw->ctrl = new_ctrl;
 933 }
 934
 935 /*
 936  * return 0 means link status changed, -1 means not changed
 937  *
 938  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 939  * status.
 940  */
 941 static int
 942 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 943 {
 944         struct nfp_net_hw *hw;
 945         struct rte_eth_link link;
 946         uint32_t nn_link_status;
 947         int ret;
 948
 949         static const uint32_t ls_to_ethtool[] = {
 950                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 951                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 952                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 953                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 954                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 955                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 956                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 957                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 958         };
 959
 960         PMD_DRV_LOG(DEBUG, "Link update");
 961
 962         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 963
 964         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 965
 966         memset(&link, 0, sizeof(struct rte_eth_link));
 967
 968         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 969                 link.link_status = ETH_LINK_UP;
 970
 971         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 972
 973         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 974                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 975
 976         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 977                 link.link_speed = ETH_SPEED_NUM_NONE;
 978         else
 979                 link.link_speed = ls_to_ethtool[nn_link_status];
 980
 981         ret = rte_eth_linkstatus_set(dev, &link);
 982         if (ret == 0) {
 983                 if (link.link_status)
 984                         PMD_DRV_LOG(INFO, "NIC Link is Up");
 985                 else
 986                         PMD_DRV_LOG(INFO, "NIC Link is Down");
 987         }
 988         return ret;
 989 }
 990
 991 static int
 992 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 993 {
 994         int i;
 995         struct nfp_net_hw *hw;
 996         struct rte_eth_stats nfp_dev_stats;
 997
 998         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 999
1000         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1001
1002         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1003
1004         /* reading per RX ring stats */
1005         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1006                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1007                         break;
1008
1009                 nfp_dev_stats.q_ipackets[i] =
1010                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1011
1012                 nfp_dev_stats.q_ipackets[i] -=
1013                         hw->eth_stats_base.q_ipackets[i];
1014
1015                 nfp_dev_stats.q_ibytes[i] =
1016                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1017
1018                 nfp_dev_stats.q_ibytes[i] -=
1019                         hw->eth_stats_base.q_ibytes[i];
1020         }
1021
1022         /* reading per TX ring stats */
1023         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1024                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1025                         break;
1026
1027                 nfp_dev_stats.q_opackets[i] =
1028                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1029
1030                 nfp_dev_stats.q_opackets[i] -=
1031                         hw->eth_stats_base.q_opackets[i];
1032
1033                 nfp_dev_stats.q_obytes[i] =
1034                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1035
1036                 nfp_dev_stats.q_obytes[i] -=
1037                         hw->eth_stats_base.q_obytes[i];
1038         }
1039
1040         nfp_dev_stats.ipackets =
1041                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1042
1043         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1044
1045         nfp_dev_stats.ibytes =
1046                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1047
1048         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1049
1050         nfp_dev_stats.opackets =
1051                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1052
1053         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1054
1055         nfp_dev_stats.obytes =
1056                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1057
1058         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1059
1060         /* reading general device stats */
1061         nfp_dev_stats.ierrors =
1062                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1063
1064         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1065
1066         nfp_dev_stats.oerrors =
1067                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1068
1069         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1070
1071         /* RX ring mbuf allocation failures */
1072         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1073
1074         nfp_dev_stats.imissed =
1075                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1076
1077         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1078
1079         if (stats) {
1080                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1081                 return 0;
1082         }
1083         return -EINVAL;
1084 }
1085
1086 static void
1087 nfp_net_stats_reset(struct rte_eth_dev *dev)
1088 {
1089         int i;
1090         struct nfp_net_hw *hw;
1091
1092         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093
1094         /*
1095          * hw->eth_stats_base records the per counter starting point.
1096          * Lets update it now
1097          */
1098
1099         /* reading per RX ring stats */
1100         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1101                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1102                         break;
1103
1104                 hw->eth_stats_base.q_ipackets[i] =
1105                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1106
1107                 hw->eth_stats_base.q_ibytes[i] =
1108                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1109         }
1110
1111         /* reading per TX ring stats */
1112         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1113                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1114                         break;
1115
1116                 hw->eth_stats_base.q_opackets[i] =
1117                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1118
1119                 hw->eth_stats_base.q_obytes[i] =
1120                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1121         }
1122
1123         hw->eth_stats_base.ipackets =
1124                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1125
1126         hw->eth_stats_base.ibytes =
1127                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1128
1129         hw->eth_stats_base.opackets =
1130                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1131
1132         hw->eth_stats_base.obytes =
1133                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1134
1135         /* reading general device stats */
1136         hw->eth_stats_base.ierrors =
1137                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1138
1139         hw->eth_stats_base.oerrors =
1140                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1141
1142         /* RX ring mbuf allocation failures */
1143         dev->data->rx_mbuf_alloc_failed = 0;
1144
1145         hw->eth_stats_base.imissed =
1146                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1147 }
1148
1149 static void
1150 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1151 {
1152         struct nfp_net_hw *hw;
1153
1154         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1155
1156         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1157         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1158         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1159         dev_info->max_rx_pktlen = hw->max_mtu;
1160         /* Next should change when PF support is implemented */
1161         dev_info->max_mac_addrs = 1;
1162
1163         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1164                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1165
1166         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1167                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1168                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1169                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1170
1171         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1172
1173         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1174                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1175
1176         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1177                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1178                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1179                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1180
1181         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1182                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1183
1184         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1185                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1186
1187         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1188                 .rx_thresh = {
1189                         .pthresh = DEFAULT_RX_PTHRESH,
1190                         .hthresh = DEFAULT_RX_HTHRESH,
1191                         .wthresh = DEFAULT_RX_WTHRESH,
1192                 },
1193                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1194                 .rx_drop_en = 0,
1195         };
1196
1197         dev_info->default_txconf = (struct rte_eth_txconf) {
1198                 .tx_thresh = {
1199                         .pthresh = DEFAULT_TX_PTHRESH,
1200                         .hthresh = DEFAULT_TX_HTHRESH,
1201                         .wthresh = DEFAULT_TX_WTHRESH,
1202                 },
1203                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1204                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1205         };
1206
1207         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1208                                            ETH_RSS_NONFRAG_IPV4_TCP |
1209                                            ETH_RSS_NONFRAG_IPV4_UDP |
1210                                            ETH_RSS_IPV6 |
1211                                            ETH_RSS_NONFRAG_IPV6_TCP |
1212                                            ETH_RSS_NONFRAG_IPV6_UDP;
1213
1214         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1215         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1216
1217         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1218                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1219                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1220 }
1221
1222 static const uint32_t *
1223 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1224 {
1225         static const uint32_t ptypes[] = {
1226                 /* refers to nfp_net_set_hash() */
1227                 RTE_PTYPE_INNER_L3_IPV4,
1228                 RTE_PTYPE_INNER_L3_IPV6,
1229                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1230                 RTE_PTYPE_INNER_L4_MASK,
1231                 RTE_PTYPE_UNKNOWN
1232         };
1233
1234         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1235                 return ptypes;
1236         return NULL;
1237 }
1238
1239 static uint32_t
1240 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1241 {
1242         struct nfp_net_rxq *rxq;
1243         struct nfp_net_rx_desc *rxds;
1244         uint32_t idx;
1245         uint32_t count;
1246
1247         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1248
1249         idx = rxq->rd_p;
1250
1251         count = 0;
1252
1253         /*
1254          * Other PMDs are just checking the DD bit in intervals of 4
1255          * descriptors and counting all four if the first has the DD
1256          * bit on. Of course, this is not accurate but can be good for
1257          * performance. But ideally that should be done in descriptors
1258          * chunks belonging to the same cache line
1259          */
1260
1261         while (count < rxq->rx_count) {
1262                 rxds = &rxq->rxds[idx];
1263                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1264                         break;
1265
1266                 count++;
1267                 idx++;
1268
1269                 /* Wrapping? */
1270                 if ((idx) == rxq->rx_count)
1271                         idx = 0;
1272         }
1273
1274         return count;
1275 }
1276
1277 static int
1278 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1279 {
1280         struct rte_pci_device *pci_dev;
1281         struct nfp_net_hw *hw;
1282         int base = 0;
1283
1284         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1286
1287         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1288                 base = 1;
1289
1290         /* Make sure all updates are written before un-masking */
1291         rte_wmb();
1292         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1293                       NFP_NET_CFG_ICR_UNMASKED);
1294         return 0;
1295 }
1296
1297 static int
1298 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1299 {
1300         struct rte_pci_device *pci_dev;
1301         struct nfp_net_hw *hw;
1302         int base = 0;
1303
1304         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1306
1307         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1308                 base = 1;
1309
1310         /* Make sure all updates are written before un-masking */
1311         rte_wmb();
1312         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1313         return 0;
1314 }
1315
1316 static void
1317 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1318 {
1319         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1320         struct rte_eth_link link;
1321
1322         rte_eth_linkstatus_get(dev, &link);
1323         if (link.link_status)
1324                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1325                             dev->data->port_id, link.link_speed,
1326                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1327                             ? "full-duplex" : "half-duplex");
1328         else
1329                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1330                             dev->data->port_id);
1331
1332         PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1333                 pci_dev->addr.domain, pci_dev->addr.bus,
1334                 pci_dev->addr.devid, pci_dev->addr.function);
1335 }
1336
1337 /* Interrupt configuration and handling */
1338
1339 /*
1340  * nfp_net_irq_unmask - Unmask an interrupt
1341  *
1342  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1343  * clear the ICR for the entry.
1344  */
1345 static void
1346 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1347 {
1348         struct nfp_net_hw *hw;
1349         struct rte_pci_device *pci_dev;
1350
1351         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1353
1354         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1355                 /* If MSI-X auto-masking is used, clear the entry */
1356                 rte_wmb();
1357                 rte_intr_enable(&pci_dev->intr_handle);
1358         } else {
1359                 /* Make sure all updates are written before un-masking */
1360                 rte_wmb();
1361                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1362                               NFP_NET_CFG_ICR_UNMASKED);
1363         }
1364 }
1365
1366 static void
1367 nfp_net_dev_interrupt_handler(void *param)
1368 {
1369         int64_t timeout;
1370         struct rte_eth_link link;
1371         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1372
1373         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1374
1375         rte_eth_linkstatus_get(dev, &link);
1376
1377         nfp_net_link_update(dev, 0);
1378
1379         /* likely to up */
1380         if (!link.link_status) {
1381                 /* handle it 1 sec later, wait it being stable */
1382                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1383                 /* likely to down */
1384         } else {
1385                 /* handle it 4 sec later, wait it being stable */
1386                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1387         }
1388
1389         if (rte_eal_alarm_set(timeout * 1000,
1390                               nfp_net_dev_interrupt_delayed_handler,
1391                               (void *)dev) < 0) {
1392                 PMD_INIT_LOG(ERR, "Error setting alarm");
1393                 /* Unmasking */
1394                 nfp_net_irq_unmask(dev);
1395         }
1396 }
1397
1398 /*
1399  * Interrupt handler which shall be registered for alarm callback for delayed
1400  * handling specific interrupt to wait for the stable nic state. As the NIC
1401  * interrupt state is not stable for nfp after link is just down, it needs
1402  * to wait 4 seconds to get the stable status.
1403  *
1404  * @param handle   Pointer to interrupt handle.
1405  * @param param    The address of parameter (struct rte_eth_dev *)
1406  *
1407  * @return  void
1408  */
1409 static void
1410 nfp_net_dev_interrupt_delayed_handler(void *param)
1411 {
1412         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1413
1414         nfp_net_link_update(dev, 0);
1415         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1416
1417         nfp_net_dev_link_status_print(dev);
1418
1419         /* Unmasking */
1420         nfp_net_irq_unmask(dev);
1421 }
1422
1423 static int
1424 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1425 {
1426         struct nfp_net_hw *hw;
1427
1428         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429
1430         /* check that mtu is within the allowed range */
1431         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1432                 return -EINVAL;
1433
1434         /* mtu setting is forbidden if port is started */
1435         if (dev->data->dev_started) {
1436                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1437                             dev->data->port_id);
1438                 return -EBUSY;
1439         }
1440
1441         /* switch to jumbo mode if needed */
1442         if ((uint32_t)mtu > ETHER_MAX_LEN)
1443                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1444         else
1445                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1446
1447         /* update max frame size */
1448         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1449
1450         /* writing to configuration space */
1451         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1452
1453         hw->mtu = mtu;
1454
1455         return 0;
1456 }
1457
1458 static int
1459 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1460                        uint16_t queue_idx, uint16_t nb_desc,
1461                        unsigned int socket_id,
1462                        const struct rte_eth_rxconf *rx_conf,
1463                        struct rte_mempool *mp)
1464 {
1465         const struct rte_memzone *tz;
1466         struct nfp_net_rxq *rxq;
1467         struct nfp_net_hw *hw;
1468
1469         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1470
1471         PMD_INIT_FUNC_TRACE();
1472
1473         /* Validating number of descriptors */
1474         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1475             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1476             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1477                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1478                 return -EINVAL;
1479         }
1480
1481         /*
1482          * Free memory prior to re-allocation if needed. This is the case after
1483          * calling nfp_net_stop
1484          */
1485         if (dev->data->rx_queues[queue_idx]) {
1486                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1487                 dev->data->rx_queues[queue_idx] = NULL;
1488         }
1489
1490         /* Allocating rx queue data structure */
1491         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1492                                  RTE_CACHE_LINE_SIZE, socket_id);
1493         if (rxq == NULL)
1494                 return -ENOMEM;
1495
1496         /* Hw queues mapping based on firmware confifguration */
1497         rxq->qidx = queue_idx;
1498         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1499         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1500         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1501         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1502
1503         /*
1504          * Tracking mbuf size for detecting a potential mbuf overflow due to
1505          * RX offset
1506          */
1507         rxq->mem_pool = mp;
1508         rxq->mbuf_size = rxq->mem_pool->elt_size;
1509         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1510         hw->flbufsz = rxq->mbuf_size;
1511
1512         rxq->rx_count = nb_desc;
1513         rxq->port_id = dev->data->port_id;
1514         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1515         rxq->drop_en = rx_conf->rx_drop_en;
1516
1517         /*
1518          * Allocate RX ring hardware descriptors. A memzone large enough to
1519          * handle the maximum ring size is allocated in order to allow for
1520          * resizing in later calls to the queue setup function.
1521          */
1522         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1523                                    sizeof(struct nfp_net_rx_desc) *
1524                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1525                                    socket_id);
1526
1527         if (tz == NULL) {
1528                 PMD_DRV_LOG(ERR, "Error allocatig rx dma");
1529                 nfp_net_rx_queue_release(rxq);
1530                 return -ENOMEM;
1531         }
1532
1533         /* Saving physical and virtual addresses for the RX ring */
1534         rxq->dma = (uint64_t)tz->iova;
1535         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1536
1537         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1538         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1539                                          sizeof(*rxq->rxbufs) * nb_desc,
1540                                          RTE_CACHE_LINE_SIZE, socket_id);
1541         if (rxq->rxbufs == NULL) {
1542                 nfp_net_rx_queue_release(rxq);
1543                 return -ENOMEM;
1544         }
1545
1546         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1547                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1548
1549         nfp_net_reset_rx_queue(rxq);
1550
1551         dev->data->rx_queues[queue_idx] = rxq;
1552         rxq->hw = hw;
1553
1554         /*
1555          * Telling the HW about the physical address of the RX ring and number
1556          * of descriptors in log2 format
1557          */
1558         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1559         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1560
1561         return 0;
1562 }
1563
1564 static int
1565 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1566 {
1567         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1568         uint64_t dma_addr;
1569         unsigned i;
1570
1571         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1572                    rxq->rx_count);
1573
1574         for (i = 0; i < rxq->rx_count; i++) {
1575                 struct nfp_net_rx_desc *rxd;
1576                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1577
1578                 if (mbuf == NULL) {
1579                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1580                                 (unsigned)rxq->qidx);
1581                         return -ENOMEM;
1582                 }
1583
1584                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1585
1586                 rxd = &rxq->rxds[i];
1587                 rxd->fld.dd = 0;
1588                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1589                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1590                 rxe[i].mbuf = mbuf;
1591                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1592         }
1593
1594         /* Make sure all writes are flushed before telling the hardware */
1595         rte_wmb();
1596
1597         /* Not advertising the whole ring as the firmware gets confused if so */
1598         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1599                    rxq->rx_count - 1);
1600
1601         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1602
1603         return 0;
1604 }
1605
1606 static int
1607 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1608                        uint16_t nb_desc, unsigned int socket_id,
1609                        const struct rte_eth_txconf *tx_conf)
1610 {
1611         const struct rte_memzone *tz;
1612         struct nfp_net_txq *txq;
1613         uint16_t tx_free_thresh;
1614         struct nfp_net_hw *hw;
1615
1616         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617
1618         PMD_INIT_FUNC_TRACE();
1619
1620         /* Validating number of descriptors */
1621         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1622             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1623             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1624                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1625                 return -EINVAL;
1626         }
1627
1628         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1629                                     tx_conf->tx_free_thresh :
1630                                     DEFAULT_TX_FREE_THRESH);
1631
1632         if (tx_free_thresh > (nb_desc)) {
1633                 PMD_DRV_LOG(ERR,
1634                         "tx_free_thresh must be less than the number of TX "
1635                         "descriptors. (tx_free_thresh=%u port=%d "
1636                         "queue=%d)", (unsigned int)tx_free_thresh,
1637                         dev->data->port_id, (int)queue_idx);
1638                 return -(EINVAL);
1639         }
1640
1641         /*
1642          * Free memory prior to re-allocation if needed. This is the case after
1643          * calling nfp_net_stop
1644          */
1645         if (dev->data->tx_queues[queue_idx]) {
1646                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1647                            queue_idx);
1648                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1649                 dev->data->tx_queues[queue_idx] = NULL;
1650         }
1651
1652         /* Allocating tx queue data structure */
1653         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1654                                  RTE_CACHE_LINE_SIZE, socket_id);
1655         if (txq == NULL) {
1656                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1657                 return -ENOMEM;
1658         }
1659
1660         /*
1661          * Allocate TX ring hardware descriptors. A memzone large enough to
1662          * handle the maximum ring size is allocated in order to allow for
1663          * resizing in later calls to the queue setup function.
1664          */
1665         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1666                                    sizeof(struct nfp_net_tx_desc) *
1667                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1668                                    socket_id);
1669         if (tz == NULL) {
1670                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1671                 nfp_net_tx_queue_release(txq);
1672                 return -ENOMEM;
1673         }
1674
1675         txq->tx_count = nb_desc;
1676         txq->tx_free_thresh = tx_free_thresh;
1677         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1678         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1679         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1680
1681         /* queue mapping based on firmware configuration */
1682         txq->qidx = queue_idx;
1683         txq->tx_qcidx = queue_idx * hw->stride_tx;
1684         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1685
1686         txq->port_id = dev->data->port_id;
1687
1688         /* Saving physical and virtual addresses for the TX ring */
1689         txq->dma = (uint64_t)tz->iova;
1690         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1691
1692         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1693         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1694                                          sizeof(*txq->txbufs) * nb_desc,
1695                                          RTE_CACHE_LINE_SIZE, socket_id);
1696         if (txq->txbufs == NULL) {
1697                 nfp_net_tx_queue_release(txq);
1698                 return -ENOMEM;
1699         }
1700         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1701                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1702
1703         nfp_net_reset_tx_queue(txq);
1704
1705         dev->data->tx_queues[queue_idx] = txq;
1706         txq->hw = hw;
1707
1708         /*
1709          * Telling the HW about the physical address of the TX ring and number
1710          * of descriptors in log2 format
1711          */
1712         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1713         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1714
1715         return 0;
1716 }
1717
1718 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1719 static inline void
1720 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1721                struct rte_mbuf *mb)
1722 {
1723         uint64_t ol_flags;
1724         struct nfp_net_hw *hw = txq->hw;
1725
1726         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1727                 goto clean_txd;
1728
1729         ol_flags = mb->ol_flags;
1730
1731         if (!(ol_flags & PKT_TX_TCP_SEG))
1732                 goto clean_txd;
1733
1734         txd->l3_offset = mb->l2_len;
1735         txd->l4_offset = mb->l2_len + mb->l3_len;
1736         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1737         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1738         txd->flags = PCIE_DESC_TX_LSO;
1739         return;
1740
1741 clean_txd:
1742         txd->flags = 0;
1743         txd->l3_offset = 0;
1744         txd->l4_offset = 0;
1745         txd->lso_hdrlen = 0;
1746         txd->mss = 0;
1747 }
1748
1749 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1750 static inline void
1751 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1752                  struct rte_mbuf *mb)
1753 {
1754         uint64_t ol_flags;
1755         struct nfp_net_hw *hw = txq->hw;
1756
1757         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1758                 return;
1759
1760         ol_flags = mb->ol_flags;
1761
1762         /* IPv6 does not need checksum */
1763         if (ol_flags & PKT_TX_IP_CKSUM)
1764                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1765
1766         switch (ol_flags & PKT_TX_L4_MASK) {
1767         case PKT_TX_UDP_CKSUM:
1768                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1769                 break;
1770         case PKT_TX_TCP_CKSUM:
1771                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1772                 break;
1773         }
1774
1775         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1776                 txd->flags |= PCIE_DESC_TX_CSUM;
1777 }
1778
1779 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1780 static inline void
1781 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1782                  struct rte_mbuf *mb)
1783 {
1784         struct nfp_net_hw *hw = rxq->hw;
1785
1786         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1787                 return;
1788
1789         /* If IPv4 and IP checksum error, fail */
1790         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1791             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1792                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1793         else
1794                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1795
1796         /* If neither UDP nor TCP return */
1797         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1798             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1799                 return;
1800
1801         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1802                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1803         else
1804                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1805 }
1806
1807 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1808 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1809
1810 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1811
1812 /*
1813  * nfp_net_set_hash - Set mbuf hash data
1814  *
1815  * The RSS hash and hash-type are pre-pended to the packet data.
1816  * Extract and decode it and set the mbuf fields.
1817  */
1818 static inline void
1819 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1820                  struct rte_mbuf *mbuf)
1821 {
1822         struct nfp_net_hw *hw = rxq->hw;
1823         uint8_t *meta_offset;
1824         uint32_t meta_info;
1825         uint32_t hash = 0;
1826         uint32_t hash_type = 0;
1827
1828         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1829                 return;
1830
1831         /* this is true for new firmwares */
1832         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1833             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1834              NFP_DESC_META_LEN(rxd))) {
1835                 /*
1836                  * new metadata api:
1837                  * <----  32 bit  ----->
1838                  * m    field type word
1839                  * e     data field #2
1840                  * t     data field #1
1841                  * a     data field #0
1842                  * ====================
1843                  *    packet data
1844                  *
1845                  * Field type word contains up to 8 4bit field types
1846                  * A 4bit field type refers to a data field word
1847                  * A data field word can have several 4bit field types
1848                  */
1849                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1850                 meta_offset -= NFP_DESC_META_LEN(rxd);
1851                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1852                 meta_offset += 4;
1853                 /* NFP PMD just supports metadata for hashing */
1854                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1855                 case NFP_NET_META_HASH:
1856                         /* next field type is about the hash type */
1857                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1858                         /* hash value is in the data field */
1859                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1860                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1861                         break;
1862                 default:
1863                         /* Unsupported metadata can be a performance issue */
1864                         return;
1865                 }
1866         } else {
1867                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1868                         return;
1869
1870                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1871                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1872         }
1873
1874         mbuf->hash.rss = hash;
1875         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1876
1877         switch (hash_type) {
1878         case NFP_NET_RSS_IPV4:
1879                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1880                 break;
1881         case NFP_NET_RSS_IPV6:
1882                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1883                 break;
1884         case NFP_NET_RSS_IPV6_EX:
1885                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1886                 break;
1887         case NFP_NET_RSS_IPV4_TCP:
1888                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1889                 break;
1890         case NFP_NET_RSS_IPV6_TCP:
1891                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1892                 break;
1893         case NFP_NET_RSS_IPV4_UDP:
1894                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1895                 break;
1896         case NFP_NET_RSS_IPV6_UDP:
1897                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1898                 break;
1899         default:
1900                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1901         }
1902 }
1903
1904 static inline void
1905 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1906 {
1907         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1908 }
1909
1910 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1911
1912 /*
1913  * RX path design:
1914  *
1915  * There are some decissions to take:
1916  * 1) How to check DD RX descriptors bit
1917  * 2) How and when to allocate new mbufs
1918  *
1919  * Current implementation checks just one single DD bit each loop. As each
1920  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1921  * a single cache line instead. Tests with this change have not shown any
1922  * performance improvement but it requires further investigation. For example,
1923  * depending on which descriptor is next, the number of descriptors could be
1924  * less than 8 for just checking those in the same cache line. This implies
1925  * extra work which could be counterproductive by itself. Indeed, last firmware
1926  * changes are just doing this: writing several descriptors with the DD bit
1927  * for saving PCIe bandwidth and DMA operations from the NFP.
1928  *
1929  * Mbuf allocation is done when a new packet is received. Then the descriptor
1930  * is automatically linked with the new mbuf and the old one is given to the
1931  * user. The main drawback with this design is mbuf allocation is heavier than
1932  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1933  * cache point of view it does not seem allocating the mbuf early on as we are
1934  * doing now have any benefit at all. Again, tests with this change have not
1935  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1936  * so looking at the implications of this type of allocation should be studied
1937  * deeply
1938  */
1939
1940 static uint16_t
1941 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1942 {
1943         struct nfp_net_rxq *rxq;
1944         struct nfp_net_rx_desc *rxds;
1945         struct nfp_net_rx_buff *rxb;
1946         struct nfp_net_hw *hw;
1947         struct rte_mbuf *mb;
1948         struct rte_mbuf *new_mb;
1949         uint16_t nb_hold;
1950         uint64_t dma_addr;
1951         int avail;
1952
1953         rxq = rx_queue;
1954         if (unlikely(rxq == NULL)) {
1955                 /*
1956                  * DPDK just checks the queue is lower than max queues
1957                  * enabled. But the queue needs to be configured
1958                  */
1959                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1960                 return -EINVAL;
1961         }
1962
1963         hw = rxq->hw;
1964         avail = 0;
1965         nb_hold = 0;
1966
1967         while (avail < nb_pkts) {
1968                 rxb = &rxq->rxbufs[rxq->rd_p];
1969                 if (unlikely(rxb == NULL)) {
1970                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1971                         break;
1972                 }
1973
1974                 rxds = &rxq->rxds[rxq->rd_p];
1975                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1976                         break;
1977
1978                 /*
1979                  * Memory barrier to ensure that we won't do other
1980                  * reads before the DD bit.
1981                  */
1982                 rte_rmb();
1983
1984                 /*
1985                  * We got a packet. Let's alloc a new mbuff for refilling the
1986                  * free descriptor ring as soon as possible
1987                  */
1988                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1989                 if (unlikely(new_mb == NULL)) {
1990                         RTE_LOG_DP(DEBUG, PMD,
1991                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
1992                                 rxq->port_id, (unsigned int)rxq->qidx);
1993                         nfp_net_mbuf_alloc_failed(rxq);
1994                         break;
1995                 }
1996
1997                 nb_hold++;
1998
1999                 /*
2000                  * Grab the mbuff and refill the descriptor with the
2001                  * previously allocated mbuff
2002                  */
2003                 mb = rxb->mbuf;
2004                 rxb->mbuf = new_mb;
2005
2006                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2007                            rxds->rxd.data_len, rxq->mbuf_size);
2008
2009                 /* Size of this segment */
2010                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2011                 /* Size of the whole packet. We just support 1 segment */
2012                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2013
2014                 if (unlikely((mb->data_len + hw->rx_offset) >
2015                              rxq->mbuf_size)) {
2016                         /*
2017                          * This should not happen and the user has the
2018                          * responsibility of avoiding it. But we have
2019                          * to give some info about the error
2020                          */
2021                         RTE_LOG_DP(ERR, PMD,
2022                                 "mbuf overflow likely due to the RX offset.\n"
2023                                 "\t\tYour mbuf size should have extra space for"
2024                                 " RX offset=%u bytes.\n"
2025                                 "\t\tCurrently you just have %u bytes available"
2026                                 " but the received packet is %u bytes long",
2027                                 hw->rx_offset,
2028                                 rxq->mbuf_size - hw->rx_offset,
2029                                 mb->data_len);
2030                         return -EINVAL;
2031                 }
2032
2033                 /* Filling the received mbuff with packet info */
2034                 if (hw->rx_offset)
2035                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2036                 else
2037                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2038                                        NFP_DESC_META_LEN(rxds);
2039
2040                 /* No scatter mode supported */
2041                 mb->nb_segs = 1;
2042                 mb->next = NULL;
2043
2044                 mb->port = rxq->port_id;
2045
2046                 /* Checking the RSS flag */
2047                 nfp_net_set_hash(rxq, rxds, mb);
2048
2049                 /* Checking the checksum flag */
2050                 nfp_net_rx_cksum(rxq, rxds, mb);
2051
2052                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2053                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2054                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2055                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2056                 }
2057
2058                 /* Adding the mbuff to the mbuff array passed by the app */
2059                 rx_pkts[avail++] = mb;
2060
2061                 /* Now resetting and updating the descriptor */
2062                 rxds->vals[0] = 0;
2063                 rxds->vals[1] = 0;
2064                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2065                 rxds->fld.dd = 0;
2066                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2067                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2068
2069                 rxq->rd_p++;
2070                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2071                         rxq->rd_p = 0;
2072         }
2073
2074         if (nb_hold == 0)
2075                 return nb_hold;
2076
2077         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2078                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2079
2080         nb_hold += rxq->nb_rx_hold;
2081
2082         /*
2083          * FL descriptors needs to be written before incrementing the
2084          * FL queue WR pointer
2085          */
2086         rte_wmb();
2087         if (nb_hold > rxq->rx_free_thresh) {
2088                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2089                            rxq->port_id, (unsigned int)rxq->qidx,
2090                            (unsigned)nb_hold, (unsigned)avail);
2091                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2092                 nb_hold = 0;
2093         }
2094         rxq->nb_rx_hold = nb_hold;
2095
2096         return avail;
2097 }
2098
2099 /*
2100  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2101  * status
2102  * @txq: TX queue to work with
2103  * Returns number of descriptors freed
2104  */
2105 int
2106 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2107 {
2108         uint32_t qcp_rd_p;
2109         int todo;
2110
2111         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2112                    " status", txq->qidx);
2113
2114         /* Work out how many packets have been sent */
2115         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2116
2117         if (qcp_rd_p == txq->rd_p) {
2118                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2119                            "packets (%u, %u)", txq->qidx,
2120                            qcp_rd_p, txq->rd_p);
2121                 return 0;
2122         }
2123
2124         if (qcp_rd_p > txq->rd_p)
2125                 todo = qcp_rd_p - txq->rd_p;
2126         else
2127                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2128
2129         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2130                    qcp_rd_p, txq->rd_p, txq->rd_p);
2131
2132         if (todo == 0)
2133                 return todo;
2134
2135         txq->rd_p += todo;
2136         if (unlikely(txq->rd_p >= txq->tx_count))
2137                 txq->rd_p -= txq->tx_count;
2138
2139         return todo;
2140 }
2141
2142 /* Leaving always free descriptors for avoiding wrapping confusion */
2143 static inline
2144 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2145 {
2146         if (txq->wr_p >= txq->rd_p)
2147                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2148         else
2149                 return txq->rd_p - txq->wr_p - 8;
2150 }
2151
2152 /*
2153  * nfp_net_txq_full - Check if the TX queue free descriptors
2154  * is below tx_free_threshold
2155  *
2156  * @txq: TX queue to check
2157  *
2158  * This function uses the host copy* of read/write pointers
2159  */
2160 static inline
2161 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2162 {
2163         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2164 }
2165
2166 static uint16_t
2167 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2168 {
2169         struct nfp_net_txq *txq;
2170         struct nfp_net_hw *hw;
2171         struct nfp_net_tx_desc *txds, txd;
2172         struct rte_mbuf *pkt;
2173         uint64_t dma_addr;
2174         int pkt_size, dma_size;
2175         uint16_t free_descs, issued_descs;
2176         struct rte_mbuf **lmbuf;
2177         int i;
2178
2179         txq = tx_queue;
2180         hw = txq->hw;
2181         txds = &txq->txds[txq->wr_p];
2182
2183         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2184                    txq->qidx, txq->wr_p, nb_pkts);
2185
2186         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2187                 nfp_net_tx_free_bufs(txq);
2188
2189         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2190         if (unlikely(free_descs == 0))
2191                 return 0;
2192
2193         pkt = *tx_pkts;
2194
2195         i = 0;
2196         issued_descs = 0;
2197         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2198                    txq->qidx, nb_pkts);
2199         /* Sending packets */
2200         while ((i < nb_pkts) && free_descs) {
2201                 /* Grabbing the mbuf linked to the current descriptor */
2202                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2203                 /* Warming the cache for releasing the mbuf later on */
2204                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2205
2206                 pkt = *(tx_pkts + i);
2207
2208                 if (unlikely((pkt->nb_segs > 1) &&
2209                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2210                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2211                         rte_panic("Multisegment packet unsupported\n");
2212                 }
2213
2214                 /* Checking if we have enough descriptors */
2215                 if (unlikely(pkt->nb_segs > free_descs))
2216                         goto xmit_end;
2217
2218                 /*
2219                  * Checksum and VLAN flags just in the first descriptor for a
2220                  * multisegment packet, but TSO info needs to be in all of them.
2221                  */
2222                 txd.data_len = pkt->pkt_len;
2223                 nfp_net_tx_tso(txq, &txd, pkt);
2224                 nfp_net_tx_cksum(txq, &txd, pkt);
2225
2226                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2227                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2228                         txd.flags |= PCIE_DESC_TX_VLAN;
2229                         txd.vlan = pkt->vlan_tci;
2230                 }
2231
2232                 /*
2233                  * mbuf data_len is the data in one segment and pkt_len data
2234                  * in the whole packet. When the packet is just one segment,
2235                  * then data_len = pkt_len
2236                  */
2237                 pkt_size = pkt->pkt_len;
2238
2239                 while (pkt) {
2240                         /* Copying TSO, VLAN and cksum info */
2241                         *txds = txd;
2242
2243                         /* Releasing mbuf used by this descriptor previously*/
2244                         if (*lmbuf)
2245                                 rte_pktmbuf_free_seg(*lmbuf);
2246
2247                         /*
2248                          * Linking mbuf with descriptor for being released
2249                          * next time descriptor is used
2250                          */
2251                         *lmbuf = pkt;
2252
2253                         dma_size = pkt->data_len;
2254                         dma_addr = rte_mbuf_data_iova(pkt);
2255                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2256                                    "%" PRIx64 "", dma_addr);
2257
2258                         /* Filling descriptors fields */
2259                         txds->dma_len = dma_size;
2260                         txds->data_len = txd.data_len;
2261                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2262                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2263                         ASSERT(free_descs > 0);
2264                         free_descs--;
2265
2266                         txq->wr_p++;
2267                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2268                                 txq->wr_p = 0;
2269
2270                         pkt_size -= dma_size;
2271
2272                         /*
2273                          * Making the EOP, packets with just one segment
2274                          * the priority
2275                          */
2276                         if (likely(!pkt_size))
2277                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2278                         else
2279                                 txds->offset_eop = 0;
2280
2281                         pkt = pkt->next;
2282                         /* Referencing next free TX descriptor */
2283                         txds = &txq->txds[txq->wr_p];
2284                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2285                         issued_descs++;
2286                 }
2287                 i++;
2288         }
2289
2290 xmit_end:
2291         /* Increment write pointers. Force memory write before we let HW know */
2292         rte_wmb();
2293         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2294
2295         return i;
2296 }
2297
2298 static int
2299 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2300 {
2301         uint32_t new_ctrl, update;
2302         struct nfp_net_hw *hw;
2303         int ret;
2304
2305         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306         new_ctrl = 0;
2307
2308         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2309             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2310                 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2311                         " ETH_VLAN_EXTEND_OFFLOAD");
2312
2313         /* Enable vlan strip if it is not configured yet */
2314         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2315             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2316                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2317
2318         /* Disable vlan strip just if it is configured */
2319         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2320             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2321                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2322
2323         if (new_ctrl == 0)
2324                 return 0;
2325
2326         update = NFP_NET_CFG_UPDATE_GEN;
2327
2328         ret = nfp_net_reconfig(hw, new_ctrl, update);
2329         if (!ret)
2330                 hw->ctrl = new_ctrl;
2331
2332         return ret;
2333 }
2334
2335 static int
2336 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2337                     struct rte_eth_rss_reta_entry64 *reta_conf,
2338                     uint16_t reta_size)
2339 {
2340         uint32_t reta, mask;
2341         int i, j;
2342         int idx, shift;
2343         struct nfp_net_hw *hw =
2344                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345
2346         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2347                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2348                         "(%d) doesn't match the number hardware can supported "
2349                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2350                 return -EINVAL;
2351         }
2352
2353         /*
2354          * Update Redirection Table. There are 128 8bit-entries which can be
2355          * manage as 32 32bit-entries
2356          */
2357         for (i = 0; i < reta_size; i += 4) {
2358                 /* Handling 4 RSS entries per loop */
2359                 idx = i / RTE_RETA_GROUP_SIZE;
2360                 shift = i % RTE_RETA_GROUP_SIZE;
2361                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2362
2363                 if (!mask)
2364                         continue;
2365
2366                 reta = 0;
2367                 /* If all 4 entries were set, don't need read RETA register */
2368                 if (mask != 0xF)
2369                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2370
2371                 for (j = 0; j < 4; j++) {
2372                         if (!(mask & (0x1 << j)))
2373                                 continue;
2374                         if (mask != 0xF)
2375                                 /* Clearing the entry bits */
2376                                 reta &= ~(0xFF << (8 * j));
2377                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2378                 }
2379                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2380                               reta);
2381         }
2382         return 0;
2383 }
2384
2385 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2386 static int
2387 nfp_net_reta_update(struct rte_eth_dev *dev,
2388                     struct rte_eth_rss_reta_entry64 *reta_conf,
2389                     uint16_t reta_size)
2390 {
2391         struct nfp_net_hw *hw =
2392                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393         uint32_t update;
2394         int ret;
2395
2396         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2397                 return -EINVAL;
2398
2399         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2400         if (ret != 0)
2401                 return ret;
2402
2403         update = NFP_NET_CFG_UPDATE_RSS;
2404
2405         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2406                 return -EIO;
2407
2408         return 0;
2409 }
2410
2411  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2412 static int
2413 nfp_net_reta_query(struct rte_eth_dev *dev,
2414                    struct rte_eth_rss_reta_entry64 *reta_conf,
2415                    uint16_t reta_size)
2416 {
2417         uint8_t i, j, mask;
2418         int idx, shift;
2419         uint32_t reta;
2420         struct nfp_net_hw *hw;
2421
2422         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423
2424         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2425                 return -EINVAL;
2426
2427         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2428                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2429                         "(%d) doesn't match the number hardware can supported "
2430                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2431                 return -EINVAL;
2432         }
2433
2434         /*
2435          * Reading Redirection Table. There are 128 8bit-entries which can be
2436          * manage as 32 32bit-entries
2437          */
2438         for (i = 0; i < reta_size; i += 4) {
2439                 /* Handling 4 RSS entries per loop */
2440                 idx = i / RTE_RETA_GROUP_SIZE;
2441                 shift = i % RTE_RETA_GROUP_SIZE;
2442                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2443
2444                 if (!mask)
2445                         continue;
2446
2447                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2448                                     shift);
2449                 for (j = 0; j < 4; j++) {
2450                         if (!(mask & (0x1 << j)))
2451                                 continue;
2452                         reta_conf->reta[shift + j] =
2453                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2454                 }
2455         }
2456         return 0;
2457 }
2458
2459 static int
2460 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2461                         struct rte_eth_rss_conf *rss_conf)
2462 {
2463         struct nfp_net_hw *hw;
2464         uint64_t rss_hf;
2465         uint32_t cfg_rss_ctrl = 0;
2466         uint8_t key;
2467         int i;
2468
2469         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470
2471         /* Writing the key byte a byte */
2472         for (i = 0; i < rss_conf->rss_key_len; i++) {
2473                 memcpy(&key, &rss_conf->rss_key[i], 1);
2474                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2475         }
2476
2477         rss_hf = rss_conf->rss_hf;
2478
2479         if (rss_hf & ETH_RSS_IPV4)
2480                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2481
2482         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2483                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2484
2485         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2486                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2487
2488         if (rss_hf & ETH_RSS_IPV6)
2489                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2490
2491         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2492                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2493
2494         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2495                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2496
2497         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2498         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2499
2500         /* configuring where to apply the RSS hash */
2501         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2502
2503         /* Writing the key size */
2504         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2505
2506         return 0;
2507 }
2508
2509 static int
2510 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2511                         struct rte_eth_rss_conf *rss_conf)
2512 {
2513         uint32_t update;
2514         uint64_t rss_hf;
2515         struct nfp_net_hw *hw;
2516
2517         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518
2519         rss_hf = rss_conf->rss_hf;
2520
2521         /* Checking if RSS is enabled */
2522         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2523                 if (rss_hf != 0) { /* Enable RSS? */
2524                         PMD_DRV_LOG(ERR, "RSS unsupported");
2525                         return -EINVAL;
2526                 }
2527                 return 0; /* Nothing to do */
2528         }
2529
2530         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2531                 PMD_DRV_LOG(ERR, "hash key too long");
2532                 return -EINVAL;
2533         }
2534
2535         nfp_net_rss_hash_write(dev, rss_conf);
2536
2537         update = NFP_NET_CFG_UPDATE_RSS;
2538
2539         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2540                 return -EIO;
2541
2542         return 0;
2543 }
2544
2545 static int
2546 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2547                           struct rte_eth_rss_conf *rss_conf)
2548 {
2549         uint64_t rss_hf;
2550         uint32_t cfg_rss_ctrl;
2551         uint8_t key;
2552         int i;
2553         struct nfp_net_hw *hw;
2554
2555         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556
2557         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2558                 return -EINVAL;
2559
2560         rss_hf = rss_conf->rss_hf;
2561         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2562
2563         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2564                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2565
2566         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2567                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2568
2569         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2570                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2571
2572         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2573                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2574
2575         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2576                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2577
2578         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2579                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2580
2581         /* Reading the key size */
2582         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2583
2584         /* Reading the key byte a byte */
2585         for (i = 0; i < rss_conf->rss_key_len; i++) {
2586                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2587                 memcpy(&rss_conf->rss_key[i], &key, 1);
2588         }
2589
2590         return 0;
2591 }
2592
2593 static int
2594 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2595 {
2596         struct rte_eth_conf *dev_conf;
2597         struct rte_eth_rss_conf rss_conf;
2598         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2599         uint16_t rx_queues = dev->data->nb_rx_queues;
2600         uint16_t queue;
2601         int i, j, ret;
2602
2603         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2604                 rx_queues);
2605
2606         nfp_reta_conf[0].mask = ~0x0;
2607         nfp_reta_conf[1].mask = ~0x0;
2608
2609         queue = 0;
2610         for (i = 0; i < 0x40; i += 8) {
2611                 for (j = i; j < (i + 8); j++) {
2612                         nfp_reta_conf[0].reta[j] = queue;
2613                         nfp_reta_conf[1].reta[j] = queue++;
2614                         queue %= rx_queues;
2615                 }
2616         }
2617         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2618         if (ret != 0)
2619                 return ret;
2620
2621         dev_conf = &dev->data->dev_conf;
2622         if (!dev_conf) {
2623                 PMD_DRV_LOG(INFO, "wrong rss conf");
2624                 return -EINVAL;
2625         }
2626         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2627
2628         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2629
2630         return ret;
2631 }
2632
2633
2634 /* Initialise and register driver with DPDK Application */
2635 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2636         .dev_configure          = nfp_net_configure,
2637         .dev_start              = nfp_net_start,
2638         .dev_stop               = nfp_net_stop,
2639         .dev_close              = nfp_net_close,
2640         .promiscuous_enable     = nfp_net_promisc_enable,
2641         .promiscuous_disable    = nfp_net_promisc_disable,
2642         .link_update            = nfp_net_link_update,
2643         .stats_get              = nfp_net_stats_get,
2644         .stats_reset            = nfp_net_stats_reset,
2645         .dev_infos_get          = nfp_net_infos_get,
2646         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2647         .mtu_set                = nfp_net_dev_mtu_set,
2648         .mac_addr_set           = nfp_set_mac_addr,
2649         .vlan_offload_set       = nfp_net_vlan_offload_set,
2650         .reta_update            = nfp_net_reta_update,
2651         .reta_query             = nfp_net_reta_query,
2652         .rss_hash_update        = nfp_net_rss_hash_update,
2653         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2654         .rx_queue_setup         = nfp_net_rx_queue_setup,
2655         .rx_queue_release       = nfp_net_rx_queue_release,
2656         .rx_queue_count         = nfp_net_rx_queue_count,
2657         .tx_queue_setup         = nfp_net_tx_queue_setup,
2658         .tx_queue_release       = nfp_net_tx_queue_release,
2659         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2660         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2661 };
2662
2663 /*
2664  * All eth_dev created got its private data, but before nfp_net_init, that
2665  * private data is referencing private data for all the PF ports. This is due
2666  * to how the vNIC bars are mapped based on first port, so all ports need info
2667  * about port 0 private data. Inside nfp_net_init the private data pointer is
2668  * changed to the right address for each port once the bars have been mapped.
2669  *
2670  * This functions helps to find out which port and therefore which offset
2671  * inside the private data array to use.
2672  */
2673 static int
2674 get_pf_port_number(char *name)
2675 {
2676         char *pf_str = name;
2677         int size = 0;
2678
2679         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2680                 pf_str++;
2681
2682         if (size == 30)
2683                 /*
2684                  * This should not happen at all and it would mean major
2685                  * implementation fault.
2686                  */
2687                 rte_panic("nfp_net: problem with pf device name\n");
2688
2689         /* Expecting _portX with X within [0,7] */
2690         pf_str += 5;
2691
2692         return (int)strtol(pf_str, NULL, 10);
2693 }
2694
2695 static int
2696 nfp_net_init(struct rte_eth_dev *eth_dev)
2697 {
2698         struct rte_pci_device *pci_dev;
2699         struct nfp_net_hw *hw, *hwport0;
2700
2701         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2702         uint32_t start_q;
2703         int stride = 4;
2704         int port = 0;
2705         int err;
2706
2707         PMD_INIT_FUNC_TRACE();
2708
2709         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2710
2711         /* NFP can not handle DMA addresses requiring more than 40 bits */
2712         if (rte_mem_check_dma_mask(40)) {
2713                 RTE_LOG(ERR, PMD, "device %s can not be used:",
2714                                    pci_dev->device.name);
2715                 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2716                 return -ENODEV;
2717         };
2718
2719         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2720             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2721                 port = get_pf_port_number(eth_dev->data->name);
2722                 if (port < 0 || port > 7) {
2723                         PMD_DRV_LOG(ERR, "Port value is wrong");
2724                         return -ENODEV;
2725                 }
2726
2727                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2728
2729                 /* This points to port 0 private data */
2730                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2731
2732                 /* This points to the specific port private data */
2733                 hw = &hwport0[port];
2734         } else {
2735                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2736                 hwport0 = 0;
2737         }
2738
2739         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2740         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2741         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2742
2743         /* For secondary processes, the primary has done all the work */
2744         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2745                 return 0;
2746
2747         rte_eth_copy_pci_info(eth_dev, pci_dev);
2748
2749         hw->device_id = pci_dev->id.device_id;
2750         hw->vendor_id = pci_dev->id.vendor_id;
2751         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2752         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2753
2754         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2755                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2756                      pci_dev->addr.domain, pci_dev->addr.bus,
2757                      pci_dev->addr.devid, pci_dev->addr.function);
2758
2759         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2760         if (hw->ctrl_bar == NULL) {
2761                 PMD_DRV_LOG(ERR,
2762                         "hw->ctrl_bar is NULL. BAR0 not configured");
2763                 return -ENODEV;
2764         }
2765
2766         if (hw->is_pf && port == 0) {
2767                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2768                                              hw->total_ports * 32768,
2769                                              &hw->ctrl_area);
2770                 if (!hw->ctrl_bar) {
2771                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2772                         return -EIO;
2773                 }
2774
2775                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2776         }
2777
2778         if (port > 0) {
2779                 if (!hwport0->ctrl_bar)
2780                         return -ENODEV;
2781
2782                 /* address based on port0 offset */
2783                 hw->ctrl_bar = hwport0->ctrl_bar +
2784                                (port * NFP_PF_CSR_SLICE_SIZE);
2785         }
2786
2787         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2788
2789         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2790         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2791
2792         /* Work out where in the BAR the queues start. */
2793         switch (pci_dev->id.device_id) {
2794         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2795         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2796         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2797                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2798                 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2799                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2800                 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2801                 break;
2802         default:
2803                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2804                 err = -ENODEV;
2805                 goto dev_err_ctrl_map;
2806         }
2807
2808         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2809         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2810
2811         if (hw->is_pf && port == 0) {
2812                 /* configure access to tx/rx vNIC BARs */
2813                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2814                                                       NFP_PCIE_QUEUE(0),
2815                                                       NFP_QCP_QUEUE_AREA_SZ,
2816                                                       &hw->hwqueues_area);
2817
2818                 if (!hwport0->hw_queues) {
2819                         printf("nfp_rtsym_map fails for net.qc");
2820                         err = -EIO;
2821                         goto dev_err_ctrl_map;
2822                 }
2823
2824                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2825                                     hwport0->hw_queues);
2826         }
2827
2828         if (hw->is_pf) {
2829                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2830                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2831                 eth_dev->data->dev_private = hw;
2832         } else {
2833                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2834                              tx_bar_off;
2835                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2836                              rx_bar_off;
2837         }
2838
2839         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2840                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2841
2842         nfp_net_cfg_queue_setup(hw);
2843
2844         /* Get some of the read-only fields from the config BAR */
2845         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2846         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2847         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2848         hw->mtu = ETHER_MTU;
2849
2850         /* VLAN insertion is incompatible with LSOv2 */
2851         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2852                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2853
2854         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2855                 hw->rx_offset = NFP_NET_RX_OFFSET;
2856         else
2857                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2858
2859         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2860                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2861                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2862
2863         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2864                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2865                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2866                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2867                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2868                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2869                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2870                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2871                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2872                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2873                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2874                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2875                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2876                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2877                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2878
2879         hw->ctrl = 0;
2880
2881         hw->stride_rx = stride;
2882         hw->stride_tx = stride;
2883
2884         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2885                      hw->max_rx_queues, hw->max_tx_queues);
2886
2887         /* Initializing spinlock for reconfigs */
2888         rte_spinlock_init(&hw->reconfig_lock);
2889
2890         /* Allocating memory for mac addr */
2891         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2892         if (eth_dev->data->mac_addrs == NULL) {
2893                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2894                 err = -ENOMEM;
2895                 goto dev_err_queues_map;
2896         }
2897
2898         if (hw->is_pf) {
2899                 nfp_net_pf_read_mac(hwport0, port);
2900                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2901         } else {
2902                 nfp_net_vf_read_mac(hw);
2903         }
2904
2905         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2906                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2907                                    port);
2908                 /* Using random mac addresses for VFs */
2909                 eth_random_addr(&hw->mac_addr[0]);
2910                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2911         }
2912
2913         /* Copying mac address to DPDK eth_dev struct */
2914         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2915                         &eth_dev->data->mac_addrs[0]);
2916
2917         if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2918                 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2919
2920         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2921                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2922                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2923                      pci_dev->id.device_id,
2924                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2925                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2926
2927         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2928                 /* Registering LSC interrupt handler */
2929                 rte_intr_callback_register(&pci_dev->intr_handle,
2930                                            nfp_net_dev_interrupt_handler,
2931                                            (void *)eth_dev);
2932                 /* Telling the firmware about the LSC interrupt entry */
2933                 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2934                 /* Recording current stats counters values */
2935                 nfp_net_stats_reset(eth_dev);
2936         }
2937
2938         return 0;
2939
2940 dev_err_queues_map:
2941                 nfp_cpp_area_free(hw->hwqueues_area);
2942 dev_err_ctrl_map:
2943                 nfp_cpp_area_free(hw->ctrl_area);
2944
2945         return err;
2946 }
2947
2948 static int
2949 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2950                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
2951                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
2952 {
2953         struct rte_eth_dev *eth_dev;
2954         struct nfp_net_hw *hw;
2955         char *port_name;
2956         int retval;
2957
2958         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2959         if (!port_name)
2960                 return -ENOMEM;
2961
2962         if (ports > 1)
2963                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2964         else
2965                 sprintf(port_name, "%s", dev->device.name);
2966
2967
2968         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2969                 eth_dev = rte_eth_dev_allocate(port_name);
2970                 if (!eth_dev) {
2971                         rte_free(port_name);
2972                         return -ENODEV;
2973                 }
2974                 if (port == 0) {
2975                         *priv = rte_zmalloc(port_name,
2976                                             sizeof(struct nfp_net_adapter) *
2977                                             ports, RTE_CACHE_LINE_SIZE);
2978                         if (!*priv) {
2979                                 rte_free(port_name);
2980                                 rte_eth_dev_release_port(eth_dev);
2981                                 return -ENOMEM;
2982                         }
2983                 }
2984                 eth_dev->data->dev_private = *priv;
2985
2986                 /*
2987                  * dev_private pointing to port0 dev_private because we need
2988                  * to configure vNIC bars based on port0 at nfp_net_init.
2989                  * Then dev_private is adjusted per port.
2990                  */
2991                 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2992                 hw->cpp = cpp;
2993                 hw->hwinfo = hwinfo;
2994                 hw->sym_tbl = sym_tbl;
2995                 hw->pf_port_idx = phys_port;
2996                 hw->is_pf = 1;
2997                 if (ports > 1)
2998                         hw->pf_multiport_enabled = 1;
2999
3000                 hw->total_ports = ports;
3001         } else {
3002                 eth_dev = rte_eth_dev_attach_secondary(port_name);
3003                 if (!eth_dev) {
3004                         RTE_LOG(ERR, EAL, "secondary process attach failed, "
3005                                 "ethdev doesn't exist");
3006                         rte_free(port_name);
3007                         return -ENODEV;
3008                 }
3009                 eth_dev->process_private = cpp;
3010         }
3011
3012         eth_dev->device = &dev->device;
3013         rte_eth_copy_pci_info(eth_dev, dev);
3014
3015         retval = nfp_net_init(eth_dev);
3016
3017         if (retval) {
3018                 retval = -ENODEV;
3019                 goto probe_failed;
3020         } else {
3021                 rte_eth_dev_probing_finish(eth_dev);
3022         }
3023
3024         rte_free(port_name);
3025
3026         return retval;
3027
3028 probe_failed:
3029         rte_free(port_name);
3030         /* free ports private data if primary process */
3031         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3032                 rte_free(eth_dev->data->dev_private);
3033
3034         rte_eth_dev_release_port(eth_dev);
3035
3036         return retval;
3037 }
3038
3039 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
3040
3041 static int
3042 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3043 {
3044         struct nfp_cpp *cpp = nsp->cpp;
3045         int fw_f;
3046         char *fw_buf;
3047         char fw_name[125];
3048         char serial[40];
3049         struct stat file_stat;
3050         off_t fsize, bytes;
3051
3052         /* Looking for firmware file in order of priority */
3053
3054         /* First try to find a firmware image specific for this device */
3055         sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3056                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3057                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3058                 cpp->interface & 0xff);
3059
3060         sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3061
3062         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3063         fw_f = open(fw_name, O_RDONLY);
3064         if (fw_f > 0)
3065                 goto read_fw;
3066
3067         /* Then try the PCI name */
3068         sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3069
3070         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3071         fw_f = open(fw_name, O_RDONLY);
3072         if (fw_f > 0)
3073                 goto read_fw;
3074
3075         /* Finally try the card type and media */
3076         sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3077         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3078         fw_f = open(fw_name, O_RDONLY);
3079         if (fw_f < 0) {
3080                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3081                 return -ENOENT;
3082         }
3083
3084 read_fw:
3085         if (fstat(fw_f, &file_stat) < 0) {
3086                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3087                 close(fw_f);
3088                 return -ENOENT;
3089         }
3090
3091         fsize = file_stat.st_size;
3092         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3093                             fw_name, (uint64_t)fsize);
3094
3095         fw_buf = malloc((size_t)fsize);
3096         if (!fw_buf) {
3097                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3098                 close(fw_f);
3099                 return -ENOMEM;
3100         }
3101         memset(fw_buf, 0, fsize);
3102
3103         bytes = read(fw_f, fw_buf, fsize);
3104         if (bytes != fsize) {
3105                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3106                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3107                                    (uint64_t)bytes, (uint64_t)fsize);
3108                 free(fw_buf);
3109                 close(fw_f);
3110                 return -EIO;
3111         }
3112
3113         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3114         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3115         PMD_DRV_LOG(INFO, "Done");
3116
3117         free(fw_buf);
3118         close(fw_f);
3119
3120         return 0;
3121 }
3122
3123 static int
3124 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3125              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3126 {
3127         struct nfp_nsp *nsp;
3128         const char *nfp_fw_model;
3129         char card_desc[100];
3130         int err = 0;
3131
3132         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3133
3134         if (nfp_fw_model) {
3135                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3136         } else {
3137                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3138                 return -EIO;
3139         }
3140
3141         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3142                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3143                        nfp_eth_table->count);
3144                 return -EIO;
3145         }
3146
3147         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3148                            nfp_eth_table->count);
3149
3150         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3151
3152         sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3153                 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3154
3155         nsp = nfp_nsp_open(cpp);
3156         if (!nsp) {
3157                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3158                 return -EIO;
3159         }
3160
3161         nfp_nsp_device_soft_reset(nsp);
3162         err = nfp_fw_upload(dev, nsp, card_desc);
3163
3164         nfp_nsp_close(nsp);
3165         return err;
3166 }
3167
3168 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3169                             struct rte_pci_device *dev)
3170 {
3171         struct nfp_cpp *cpp;
3172         struct nfp_hwinfo *hwinfo;
3173         struct nfp_rtsym_table *sym_tbl;
3174         struct nfp_eth_table *nfp_eth_table = NULL;
3175         int total_ports;
3176         void *priv = 0;
3177         int ret = -ENODEV;
3178         int err;
3179         int i;
3180
3181         if (!dev)
3182                 return ret;
3183
3184         /*
3185          * When device bound to UIO, the device could be used, by mistake,
3186          * by two DPDK apps, and the UIO driver does not avoid it. This
3187          * could lead to a serious problem when configuring the NFP CPP
3188          * interface. Here we avoid this telling to the CPP init code to
3189          * use a lock file if UIO is being used.
3190          */
3191         if (dev->kdrv == RTE_KDRV_VFIO)
3192                 cpp = nfp_cpp_from_device_name(dev, 0);
3193         else
3194                 cpp = nfp_cpp_from_device_name(dev, 1);
3195
3196         if (!cpp) {
3197                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3198                 ret = -EIO;
3199                 goto error;
3200         }
3201
3202         hwinfo = nfp_hwinfo_read(cpp);
3203         if (!hwinfo) {
3204                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3205                 return -EIO;
3206         }
3207
3208         nfp_eth_table = nfp_eth_read_ports(cpp);
3209         if (!nfp_eth_table) {
3210                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3211                 return -EIO;
3212         }
3213
3214         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3215                 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3216                         PMD_DRV_LOG(INFO, "Error when uploading firmware");
3217                         ret = -EIO;
3218                         goto error;
3219                 }
3220         }
3221
3222         /* Now the symbol table should be there */
3223         sym_tbl = nfp_rtsym_table_read(cpp);
3224         if (!sym_tbl) {
3225                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3226                                 " symbol table");
3227                 ret = -EIO;
3228                 goto error;
3229         }
3230
3231         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3232         if (total_ports != (int)nfp_eth_table->count) {
3233                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3234                 ret = -EIO;
3235                 goto error;
3236         }
3237         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3238
3239         if (total_ports <= 0 || total_ports > 8) {
3240                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3241                 ret = -ENODEV;
3242                 goto error;
3243         }
3244
3245         for (i = 0; i < total_ports; i++) {
3246                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3247                                         nfp_eth_table->ports[i].index,
3248                                         sym_tbl, &priv);
3249                 if (ret)
3250                         break;
3251         }
3252
3253 error:
3254         free(nfp_eth_table);
3255         return ret;
3256 }
3257
3258 int nfp_logtype_init;
3259 int nfp_logtype_driver;
3260
3261 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3262         {
3263                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3264                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3265         },
3266         {
3267                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3268                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3269         },
3270         {
3271                 .vendor_id = 0,
3272         },
3273 };
3274
3275 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3276         {
3277                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3278                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3279         },
3280         {
3281                 .vendor_id = 0,
3282         },
3283 };
3284
3285 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3286         struct rte_pci_device *pci_dev)
3287 {
3288         return rte_eth_dev_pci_generic_probe(pci_dev,
3289                 sizeof(struct nfp_net_adapter), nfp_net_init);
3290 }
3291
3292 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3293 {
3294         struct rte_eth_dev *eth_dev;
3295         struct nfp_net_hw *hw, *hwport0;
3296         int port = 0;
3297
3298         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3299         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3300             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3301                 port = get_pf_port_number(eth_dev->data->name);
3302                 /*
3303                  * hotplug is not possible with multiport PF although freeing
3304                  * data structures can be done for first port.
3305                  */
3306                 if (port != 0)
3307                         return -ENOTSUP;
3308                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3309                 hw = &hwport0[port];
3310                 nfp_cpp_area_free(hw->ctrl_area);
3311                 nfp_cpp_area_free(hw->hwqueues_area);
3312                 free(hw->hwinfo);
3313                 free(hw->sym_tbl);
3314                 nfp_cpp_free(hw->cpp);
3315         } else {
3316                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3317         }
3318         /* hotplug is not possible with multiport PF */
3319         if (hw->pf_multiport_enabled)
3320                 return -ENOTSUP;
3321         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3322 }
3323
3324 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3325         .id_table = pci_id_nfp_pf_net_map,
3326         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3327                      RTE_PCI_DRV_IOVA_AS_VA,
3328         .probe = nfp_pf_pci_probe,
3329         .remove = eth_nfp_pci_remove,
3330 };
3331
3332 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3333         .id_table = pci_id_nfp_vf_net_map,
3334         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3335                      RTE_PCI_DRV_IOVA_AS_VA,
3336         .probe = eth_nfp_pci_probe,
3337         .remove = eth_nfp_pci_remove,
3338 };
3339
3340 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3341 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3342 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3343 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3344 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3345 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3346
3347 RTE_INIT(nfp_init_log)
3348 {
3349         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3350         if (nfp_logtype_init >= 0)
3351                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3352         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3353         if (nfp_logtype_driver >= 0)
3354                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3355 }
3356 /*
3357  * Local variables:
3358  * c-file-style: "Linux"
3359  * indent-tabs-mode: t
3360  * End:
3361  */