2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(void *param);
67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
70 struct rte_eth_dev_info *dev_info);
71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80 static void nfp_net_rx_queue_release(void *rxq);
81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
82 uint16_t nb_desc, unsigned int socket_id,
83 const struct rte_eth_rxconf *rx_conf,
84 struct rte_mempool *mp);
85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
86 static void nfp_net_tx_queue_release(void *txq);
87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_txconf *tx_conf);
90 static int nfp_net_start(struct rte_eth_dev *dev);
91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
92 struct rte_eth_stats *stats);
93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
94 static void nfp_net_stop(struct rte_eth_dev *dev);
95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
99 * The offset of the queue controller queues in the PCIe Target. These
100 * happen to be at the same offset on the NFP6000 and the NFP3200 so
101 * we use a single macro here.
103 #define NFP_PCIE_QUEUE(_q) (0x800 * ((_q) & 0xff))
105 /* Maximum value which can be added to a queue with one transaction */
106 #define NFP_QCP_MAX_ADD 0x7f
108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
109 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
113 NFP_QCP_READ_PTR = 0,
118 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
119 * @q: Base address for queue structure
120 * @ptr: Add to the Read or Write pointer
121 * @val: Value to add to the queue pointer
123 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
130 if (ptr == NFP_QCP_READ_PTR)
131 off = NFP_QCP_QUEUE_ADD_RPTR;
133 off = NFP_QCP_QUEUE_ADD_WPTR;
135 while (val > NFP_QCP_MAX_ADD) {
136 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
137 val -= NFP_QCP_MAX_ADD;
140 nn_writel(rte_cpu_to_le_32(val), q + off);
144 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
145 * @q: Base address for queue structure
146 * @ptr: Read or Write pointer
148 static inline uint32_t
149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
154 if (ptr == NFP_QCP_READ_PTR)
155 off = NFP_QCP_QUEUE_STS_LO;
157 off = NFP_QCP_QUEUE_STS_HI;
159 val = rte_cpu_to_le_32(nn_readl(q + off));
161 if (ptr == NFP_QCP_READ_PTR)
162 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
164 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
168 * Functions to read/write from/to Config BAR
169 * Performs any endian conversion necessary.
171 static inline uint8_t
172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
174 return nn_readb(hw->ctrl_bar + off);
178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
180 nn_writeb(val, hw->ctrl_bar + off);
183 static inline uint32_t
184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
186 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
192 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
195 static inline uint64_t
196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
198 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
204 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 * Atomically reads link status information from global structure rte_eth_dev.
211 * - Pointer to the structure rte_eth_dev to read from.
212 * - Pointer to the buffer to be saved with the link status.
215 * - On success, zero.
216 * - On failure, negative value.
219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
220 struct rte_eth_link *link)
222 struct rte_eth_link *dst = link;
223 struct rte_eth_link *src = &dev->data->dev_link;
225 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
226 *(uint64_t *)src) == 0)
233 * Atomically writes the link status information into global
234 * structure rte_eth_dev.
237 * - Pointer to the structure rte_eth_dev to read from.
238 * - Pointer to the buffer to be saved with the link status.
241 * - On success, zero.
242 * - On failure, negative value.
245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
246 struct rte_eth_link *link)
248 struct rte_eth_link *dst = &dev->data->dev_link;
249 struct rte_eth_link *src = link;
251 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
252 *(uint64_t *)src) == 0)
259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
263 if (rxq->rxbufs == NULL)
266 for (i = 0; i < rxq->rx_count; i++) {
267 if (rxq->rxbufs[i].mbuf) {
268 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
269 rxq->rxbufs[i].mbuf = NULL;
275 nfp_net_rx_queue_release(void *rx_queue)
277 struct nfp_net_rxq *rxq = rx_queue;
280 nfp_net_rx_queue_release_mbufs(rxq);
281 rte_free(rxq->rxbufs);
287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
289 nfp_net_rx_queue_release_mbufs(rxq);
295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
299 if (txq->txbufs == NULL)
302 for (i = 0; i < txq->tx_count; i++) {
303 if (txq->txbufs[i].mbuf) {
304 rte_pktmbuf_free(txq->txbufs[i].mbuf);
305 txq->txbufs[i].mbuf = NULL;
311 nfp_net_tx_queue_release(void *tx_queue)
313 struct nfp_net_txq *txq = tx_queue;
316 nfp_net_tx_queue_release_mbufs(txq);
317 rte_free(txq->txbufs);
323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
325 nfp_net_tx_queue_release_mbufs(txq);
331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
335 struct timespec wait;
337 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
340 if (hw->qcp_cfg == NULL)
341 rte_panic("Bad configuration queue pointer\n");
343 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
346 wait.tv_nsec = 1000000;
348 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
350 /* Poll update field, waiting for NFP to ack the config */
351 for (cnt = 0; ; cnt++) {
352 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
355 if (new & NFP_NET_CFG_UPDATE_ERR) {
356 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
359 if (cnt >= NFP_NET_POLL_TIMEOUT) {
360 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
361 " %dms", update, cnt);
362 rte_panic("Exiting\n");
364 nanosleep(&wait, 0); /* waiting for a 1ms */
366 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
371 * Reconfigure the NIC
372 * @nn: device to reconfigure
373 * @ctrl: The value for the ctrl field in the BAR config
374 * @update: The value for the update field in the BAR config
376 * Write the update word to the BAR and ping the reconfig queue. Then poll
377 * until the firmware has acknowledged the update by zeroing the update word.
380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
384 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
387 rte_spinlock_lock(&hw->reconfig_lock);
389 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
390 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
394 err = __nfp_net_reconfig(hw, update);
396 rte_spinlock_unlock(&hw->reconfig_lock);
402 * Reconfig errors imply situations where they can be handled.
403 * Otherwise, rte_panic is called inside __nfp_net_reconfig
405 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
411 * Configure an Ethernet device. This function must be invoked first
412 * before any other function in the Ethernet API. This function can
413 * also be re-invoked when a device is in the stopped state.
416 nfp_net_configure(struct rte_eth_dev *dev)
418 struct rte_eth_conf *dev_conf;
419 struct rte_eth_rxmode *rxmode;
420 struct rte_eth_txmode *txmode;
421 uint32_t new_ctrl = 0;
423 struct nfp_net_hw *hw;
425 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
428 * A DPDK app sends info about how many queues to use and how
429 * those queues need to be configured. This is used by the
430 * DPDK core and it makes sure no more queues than those
431 * advertised by the driver are requested. This function is
432 * called after that internal process
435 PMD_INIT_LOG(DEBUG, "Configure");
437 dev_conf = &dev->data->dev_conf;
438 rxmode = &dev_conf->rxmode;
439 txmode = &dev_conf->txmode;
441 /* Checking TX mode */
442 if (txmode->mq_mode) {
443 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
447 /* Checking RX mode */
448 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
449 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
450 update = NFP_NET_CFG_UPDATE_RSS;
451 new_ctrl = NFP_NET_CFG_CTRL_RSS;
453 PMD_INIT_LOG(INFO, "RSS not supported");
458 if (rxmode->split_hdr_size) {
459 PMD_INIT_LOG(INFO, "rxmode does not support split header");
463 if (rxmode->hw_ip_checksum) {
464 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
465 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
467 PMD_INIT_LOG(INFO, "RXCSUM not supported");
472 if (rxmode->hw_vlan_filter) {
473 PMD_INIT_LOG(INFO, "VLAN filter not supported");
477 if (rxmode->hw_vlan_strip) {
478 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
479 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
481 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
486 if (rxmode->hw_vlan_extend) {
487 PMD_INIT_LOG(INFO, "VLAN extended not supported");
491 /* Supporting VLAN insertion by default */
492 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
493 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
495 if (rxmode->jumbo_frame)
496 /* this is handled in rte_eth_dev_configure */
498 if (rxmode->hw_strip_crc) {
499 PMD_INIT_LOG(INFO, "strip CRC not supported");
503 if (rxmode->enable_scatter) {
504 PMD_INIT_LOG(INFO, "Scatter not supported");
511 update |= NFP_NET_CFG_UPDATE_GEN;
513 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
514 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
523 nfp_net_enable_queues(struct rte_eth_dev *dev)
525 struct nfp_net_hw *hw;
526 uint64_t enabled_queues = 0;
529 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
531 /* Enabling the required TX queues in the device */
532 for (i = 0; i < dev->data->nb_tx_queues; i++)
533 enabled_queues |= (1 << i);
535 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
539 /* Enabling the required RX queues in the device */
540 for (i = 0; i < dev->data->nb_rx_queues; i++)
541 enabled_queues |= (1 << i);
543 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
547 nfp_net_disable_queues(struct rte_eth_dev *dev)
549 struct nfp_net_hw *hw;
550 uint32_t new_ctrl, update = 0;
552 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
554 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
555 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
557 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
558 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
559 NFP_NET_CFG_UPDATE_MSIX;
561 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
562 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
564 /* If an error when reconfig we avoid to change hw state */
565 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
572 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
576 for (i = 0; i < dev->data->nb_rx_queues; i++) {
577 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
584 nfp_net_params_setup(struct nfp_net_hw *hw)
586 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
587 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
591 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
593 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
596 #define ETH_ADDR_LEN 6
599 nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
603 for (i = 0; i < ETH_ADDR_LEN; i++)
604 dst[ETH_ADDR_LEN - i - 1] = src[i];
608 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
610 union eth_table_entry *entry;
614 entry = hw->eth_table;
616 /* Reading NFP ethernet table obtained before */
617 for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
618 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
619 /* port not in use */
629 if (i == NSP_ETH_MAX_COUNT)
633 * hw points to port0 private data. We need hw now pointing to
637 nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
638 (uint8_t *)&entry->mac_addr);
644 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
648 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
649 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
651 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
652 memcpy(&hw->mac_addr[4], &tmp, 2);
656 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
658 uint32_t mac0 = *(uint32_t *)mac;
661 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
664 mac1 = *(uint16_t *)mac;
665 nn_writew(rte_cpu_to_be_16(mac1),
666 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
670 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
671 struct rte_intr_handle *intr_handle)
673 struct nfp_net_hw *hw;
676 if (!intr_handle->intr_vec) {
677 intr_handle->intr_vec =
678 rte_zmalloc("intr_vec",
679 dev->data->nb_rx_queues * sizeof(int), 0);
680 if (!intr_handle->intr_vec) {
681 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
682 " intr_vec", dev->data->nb_rx_queues);
687 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
689 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
690 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
691 /* UIO just supports one queue and no LSC*/
692 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
693 intr_handle->intr_vec[0] = 0;
695 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
696 for (i = 0; i < dev->data->nb_rx_queues; i++) {
698 * The first msix vector is reserved for non
701 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
702 intr_handle->intr_vec[i] = i + 1;
703 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
704 intr_handle->intr_vec[i]);
708 /* Avoiding TX interrupts */
709 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
714 nfp_net_start(struct rte_eth_dev *dev)
716 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
717 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
718 uint32_t new_ctrl, update = 0;
719 struct nfp_net_hw *hw;
720 uint32_t intr_vector;
723 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
725 PMD_INIT_LOG(DEBUG, "Start");
727 /* Disabling queues just in case... */
728 nfp_net_disable_queues(dev);
730 /* Writing configuration parameters in the device */
731 nfp_net_params_setup(hw);
733 /* Enabling the required queues in the device */
734 nfp_net_enable_queues(dev);
736 /* check and configure queue intr-vector mapping */
737 if (dev->data->dev_conf.intr_conf.rxq != 0) {
738 if (hw->pf_multiport_enabled) {
739 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
740 "with NFP multiport PF");
743 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
745 * Better not to share LSC with RX interrupts.
746 * Unregistering LSC interrupt handler
748 rte_intr_callback_unregister(&pci_dev->intr_handle,
749 nfp_net_dev_interrupt_handler, (void *)dev);
751 if (dev->data->nb_rx_queues > 1) {
752 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
753 "supports 1 queue with UIO");
757 intr_vector = dev->data->nb_rx_queues;
758 if (rte_intr_efd_enable(intr_handle, intr_vector))
761 nfp_configure_rx_interrupt(dev, intr_handle);
762 update = NFP_NET_CFG_UPDATE_MSIX;
765 rte_intr_enable(intr_handle);
768 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
770 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
772 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
773 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
775 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
776 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
780 * Allocating rte mbuffs for configured rx queues.
781 * This requires queues being enabled before
783 if (nfp_net_rx_freelist_setup(dev) < 0) {
789 /* Configure the physical port up */
790 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
798 * An error returned by this function should mean the app
799 * exiting and then the system releasing all the memory
800 * allocated even memory coming from hugepages.
802 * The device could be enabled at this point with some queues
803 * ready for getting packets. This is true if the call to
804 * nfp_net_rx_freelist_setup() succeeds for some queues but
805 * fails for subsequent queues.
807 * This should make the app exiting but better if we tell the
810 nfp_net_disable_queues(dev);
815 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
817 nfp_net_stop(struct rte_eth_dev *dev)
820 struct nfp_net_hw *hw;
822 PMD_INIT_LOG(DEBUG, "Stop");
824 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
826 nfp_net_disable_queues(dev);
829 for (i = 0; i < dev->data->nb_tx_queues; i++) {
830 nfp_net_reset_tx_queue(
831 (struct nfp_net_txq *)dev->data->tx_queues[i]);
834 for (i = 0; i < dev->data->nb_rx_queues; i++) {
835 nfp_net_reset_rx_queue(
836 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
840 /* Configure the physical port down */
841 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
844 /* Reset and stop device. The device can not be restarted. */
846 nfp_net_close(struct rte_eth_dev *dev)
848 struct nfp_net_hw *hw;
849 struct rte_pci_device *pci_dev;
852 PMD_INIT_LOG(DEBUG, "Close");
854 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
855 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
858 * We assume that the DPDK application is stopping all the
859 * threads/queues before calling the device close function.
862 nfp_net_disable_queues(dev);
865 for (i = 0; i < dev->data->nb_tx_queues; i++) {
866 nfp_net_reset_tx_queue(
867 (struct nfp_net_txq *)dev->data->tx_queues[i]);
870 for (i = 0; i < dev->data->nb_rx_queues; i++) {
871 nfp_net_reset_rx_queue(
872 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
875 rte_intr_disable(&pci_dev->intr_handle);
876 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
878 /* unregister callback func from eal lib */
879 rte_intr_callback_unregister(&pci_dev->intr_handle,
880 nfp_net_dev_interrupt_handler,
884 * The ixgbe PMD driver disables the pcie master on the
885 * device. The i40e does not...
890 nfp_net_promisc_enable(struct rte_eth_dev *dev)
892 uint32_t new_ctrl, update = 0;
893 struct nfp_net_hw *hw;
895 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
897 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
899 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
900 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
904 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
905 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
909 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
910 update = NFP_NET_CFG_UPDATE_GEN;
913 * DPDK sets promiscuous mode on just after this call assuming
914 * it can not fail ...
916 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
923 nfp_net_promisc_disable(struct rte_eth_dev *dev)
925 uint32_t new_ctrl, update = 0;
926 struct nfp_net_hw *hw;
928 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
930 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
931 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
935 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
936 update = NFP_NET_CFG_UPDATE_GEN;
939 * DPDK sets promiscuous mode off just before this call
940 * assuming it can not fail ...
942 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
949 * return 0 means link status changed, -1 means not changed
951 * Wait to complete is needed as it can take up to 9 seconds to get the Link
955 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
957 struct nfp_net_hw *hw;
958 struct rte_eth_link link, old;
959 uint32_t nn_link_status;
961 static const uint32_t ls_to_ethtool[] = {
962 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
963 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
964 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
965 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
966 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
967 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
968 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
969 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
972 PMD_DRV_LOG(DEBUG, "Link update\n");
974 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
976 memset(&old, 0, sizeof(old));
977 nfp_net_dev_atomic_read_link_status(dev, &old);
979 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
981 memset(&link, 0, sizeof(struct rte_eth_link));
983 if (nn_link_status & NFP_NET_CFG_STS_LINK)
984 link.link_status = ETH_LINK_UP;
986 link.link_duplex = ETH_LINK_FULL_DUPLEX;
988 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
989 NFP_NET_CFG_STS_LINK_RATE_MASK;
991 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
992 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
993 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
994 /* We really do not know the speed wil old firmware */
995 link.link_speed = ETH_SPEED_NUM_NONE;
997 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
998 link.link_speed = ETH_SPEED_NUM_NONE;
1000 link.link_speed = ls_to_ethtool[nn_link_status];
1003 if (old.link_status != link.link_status) {
1004 nfp_net_dev_atomic_write_link_status(dev, &link);
1005 if (link.link_status)
1006 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1008 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1016 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1019 struct nfp_net_hw *hw;
1020 struct rte_eth_stats nfp_dev_stats;
1022 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1026 /* reading per RX ring stats */
1027 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1028 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1031 nfp_dev_stats.q_ipackets[i] =
1032 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1034 nfp_dev_stats.q_ipackets[i] -=
1035 hw->eth_stats_base.q_ipackets[i];
1037 nfp_dev_stats.q_ibytes[i] =
1038 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1040 nfp_dev_stats.q_ibytes[i] -=
1041 hw->eth_stats_base.q_ibytes[i];
1044 /* reading per TX ring stats */
1045 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1046 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1049 nfp_dev_stats.q_opackets[i] =
1050 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1052 nfp_dev_stats.q_opackets[i] -=
1053 hw->eth_stats_base.q_opackets[i];
1055 nfp_dev_stats.q_obytes[i] =
1056 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1058 nfp_dev_stats.q_obytes[i] -=
1059 hw->eth_stats_base.q_obytes[i];
1062 nfp_dev_stats.ipackets =
1063 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1065 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1067 nfp_dev_stats.ibytes =
1068 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1070 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1072 nfp_dev_stats.opackets =
1073 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1075 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1077 nfp_dev_stats.obytes =
1078 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1080 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1082 /* reading general device stats */
1083 nfp_dev_stats.ierrors =
1084 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1086 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1088 nfp_dev_stats.oerrors =
1089 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1091 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1093 /* RX ring mbuf allocation failures */
1094 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1096 nfp_dev_stats.imissed =
1097 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1099 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1102 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1106 nfp_net_stats_reset(struct rte_eth_dev *dev)
1109 struct nfp_net_hw *hw;
1111 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114 * hw->eth_stats_base records the per counter starting point.
1115 * Lets update it now
1118 /* reading per RX ring stats */
1119 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1120 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1123 hw->eth_stats_base.q_ipackets[i] =
1124 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1126 hw->eth_stats_base.q_ibytes[i] =
1127 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1130 /* reading per TX ring stats */
1131 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1132 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1135 hw->eth_stats_base.q_opackets[i] =
1136 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1138 hw->eth_stats_base.q_obytes[i] =
1139 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1142 hw->eth_stats_base.ipackets =
1143 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1145 hw->eth_stats_base.ibytes =
1146 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1148 hw->eth_stats_base.opackets =
1149 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1151 hw->eth_stats_base.obytes =
1152 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1154 /* reading general device stats */
1155 hw->eth_stats_base.ierrors =
1156 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1158 hw->eth_stats_base.oerrors =
1159 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1161 /* RX ring mbuf allocation failures */
1162 dev->data->rx_mbuf_alloc_failed = 0;
1164 hw->eth_stats_base.imissed =
1165 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1169 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1171 struct nfp_net_hw *hw;
1173 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1176 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1177 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1178 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1179 dev_info->max_rx_pktlen = hw->mtu;
1180 /* Next should change when PF support is implemented */
1181 dev_info->max_mac_addrs = 1;
1183 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1184 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1186 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1187 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1188 DEV_RX_OFFLOAD_UDP_CKSUM |
1189 DEV_RX_OFFLOAD_TCP_CKSUM;
1191 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1192 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1194 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1195 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1196 DEV_TX_OFFLOAD_UDP_CKSUM |
1197 DEV_TX_OFFLOAD_TCP_CKSUM;
1199 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1201 .pthresh = DEFAULT_RX_PTHRESH,
1202 .hthresh = DEFAULT_RX_HTHRESH,
1203 .wthresh = DEFAULT_RX_WTHRESH,
1205 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1209 dev_info->default_txconf = (struct rte_eth_txconf) {
1211 .pthresh = DEFAULT_TX_PTHRESH,
1212 .hthresh = DEFAULT_TX_HTHRESH,
1213 .wthresh = DEFAULT_TX_WTHRESH,
1215 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1216 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1217 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1218 ETH_TXQ_FLAGS_NOOFFLOADS,
1221 dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1222 ETH_RSS_NONFRAG_IPV4_UDP |
1223 ETH_RSS_NONFRAG_IPV6_TCP |
1224 ETH_RSS_NONFRAG_IPV6_UDP;
1226 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1227 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1229 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1230 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1231 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1233 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1234 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1237 static const uint32_t *
1238 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1240 static const uint32_t ptypes[] = {
1241 /* refers to nfp_net_set_hash() */
1242 RTE_PTYPE_INNER_L3_IPV4,
1243 RTE_PTYPE_INNER_L3_IPV6,
1244 RTE_PTYPE_INNER_L3_IPV6_EXT,
1245 RTE_PTYPE_INNER_L4_MASK,
1249 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1255 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1257 struct nfp_net_rxq *rxq;
1258 struct nfp_net_rx_desc *rxds;
1262 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1269 * Other PMDs are just checking the DD bit in intervals of 4
1270 * descriptors and counting all four if the first has the DD
1271 * bit on. Of course, this is not accurate but can be good for
1272 * performance. But ideally that should be done in descriptors
1273 * chunks belonging to the same cache line
1276 while (count < rxq->rx_count) {
1277 rxds = &rxq->rxds[idx];
1278 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1285 if ((idx) == rxq->rx_count)
1293 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1295 struct rte_pci_device *pci_dev;
1296 struct nfp_net_hw *hw;
1299 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1300 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1302 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1305 /* Make sure all updates are written before un-masking */
1307 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1308 NFP_NET_CFG_ICR_UNMASKED);
1313 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1315 struct rte_pci_device *pci_dev;
1316 struct nfp_net_hw *hw;
1319 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1322 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1325 /* Make sure all updates are written before un-masking */
1327 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1332 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1334 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1335 struct rte_eth_link link;
1337 memset(&link, 0, sizeof(link));
1338 nfp_net_dev_atomic_read_link_status(dev, &link);
1339 if (link.link_status)
1340 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1341 (int)(dev->data->port_id), (unsigned)link.link_speed,
1342 link.link_duplex == ETH_LINK_FULL_DUPLEX
1343 ? "full-duplex" : "half-duplex");
1345 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1346 (int)(dev->data->port_id));
1348 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1349 pci_dev->addr.domain, pci_dev->addr.bus,
1350 pci_dev->addr.devid, pci_dev->addr.function);
1353 /* Interrupt configuration and handling */
1356 * nfp_net_irq_unmask - Unmask an interrupt
1358 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1359 * clear the ICR for the entry.
1362 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1364 struct nfp_net_hw *hw;
1365 struct rte_pci_device *pci_dev;
1367 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1370 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1371 /* If MSI-X auto-masking is used, clear the entry */
1373 rte_intr_enable(&pci_dev->intr_handle);
1375 /* Make sure all updates are written before un-masking */
1377 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1378 NFP_NET_CFG_ICR_UNMASKED);
1383 nfp_net_dev_interrupt_handler(void *param)
1386 struct rte_eth_link link;
1387 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1389 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1391 /* get the link status */
1392 memset(&link, 0, sizeof(link));
1393 nfp_net_dev_atomic_read_link_status(dev, &link);
1395 nfp_net_link_update(dev, 0);
1398 if (!link.link_status) {
1399 /* handle it 1 sec later, wait it being stable */
1400 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1401 /* likely to down */
1403 /* handle it 4 sec later, wait it being stable */
1404 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1407 if (rte_eal_alarm_set(timeout * 1000,
1408 nfp_net_dev_interrupt_delayed_handler,
1410 RTE_LOG(ERR, PMD, "Error setting alarm");
1412 nfp_net_irq_unmask(dev);
1417 * Interrupt handler which shall be registered for alarm callback for delayed
1418 * handling specific interrupt to wait for the stable nic state. As the NIC
1419 * interrupt state is not stable for nfp after link is just down, it needs
1420 * to wait 4 seconds to get the stable status.
1422 * @param handle Pointer to interrupt handle.
1423 * @param param The address of parameter (struct rte_eth_dev *)
1428 nfp_net_dev_interrupt_delayed_handler(void *param)
1430 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1432 nfp_net_link_update(dev, 0);
1433 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1435 nfp_net_dev_link_status_print(dev);
1438 nfp_net_irq_unmask(dev);
1442 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1444 struct nfp_net_hw *hw;
1446 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1448 /* check that mtu is within the allowed range */
1449 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1452 /* switch to jumbo mode if needed */
1453 if ((uint32_t)mtu > ETHER_MAX_LEN)
1454 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1456 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1458 /* update max frame size */
1459 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1461 /* writing to configuration space */
1462 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1470 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1471 uint16_t queue_idx, uint16_t nb_desc,
1472 unsigned int socket_id,
1473 const struct rte_eth_rxconf *rx_conf,
1474 struct rte_mempool *mp)
1476 const struct rte_memzone *tz;
1477 struct nfp_net_rxq *rxq;
1478 struct nfp_net_hw *hw;
1480 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1482 PMD_INIT_FUNC_TRACE();
1484 /* Validating number of descriptors */
1485 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1486 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1487 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1488 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1493 * Free memory prior to re-allocation if needed. This is the case after
1494 * calling nfp_net_stop
1496 if (dev->data->rx_queues[queue_idx]) {
1497 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1498 dev->data->rx_queues[queue_idx] = NULL;
1501 /* Allocating rx queue data structure */
1502 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1503 RTE_CACHE_LINE_SIZE, socket_id);
1507 /* Hw queues mapping based on firmware confifguration */
1508 rxq->qidx = queue_idx;
1509 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1510 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1511 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1512 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1515 * Tracking mbuf size for detecting a potential mbuf overflow due to
1519 rxq->mbuf_size = rxq->mem_pool->elt_size;
1520 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1521 hw->flbufsz = rxq->mbuf_size;
1523 rxq->rx_count = nb_desc;
1524 rxq->port_id = dev->data->port_id;
1525 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1526 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1528 rxq->drop_en = rx_conf->rx_drop_en;
1531 * Allocate RX ring hardware descriptors. A memzone large enough to
1532 * handle the maximum ring size is allocated in order to allow for
1533 * resizing in later calls to the queue setup function.
1535 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1536 sizeof(struct nfp_net_rx_desc) *
1537 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1541 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1542 nfp_net_rx_queue_release(rxq);
1546 /* Saving physical and virtual addresses for the RX ring */
1547 rxq->dma = (uint64_t)tz->phys_addr;
1548 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1550 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1551 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1552 sizeof(*rxq->rxbufs) * nb_desc,
1553 RTE_CACHE_LINE_SIZE, socket_id);
1554 if (rxq->rxbufs == NULL) {
1555 nfp_net_rx_queue_release(rxq);
1559 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1560 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1562 nfp_net_reset_rx_queue(rxq);
1564 dev->data->rx_queues[queue_idx] = rxq;
1568 * Telling the HW about the physical address of the RX ring and number
1569 * of descriptors in log2 format
1571 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1572 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1578 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1580 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1584 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1587 for (i = 0; i < rxq->rx_count; i++) {
1588 struct nfp_net_rx_desc *rxd;
1589 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1592 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1593 (unsigned)rxq->qidx);
1597 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1599 rxd = &rxq->rxds[i];
1601 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1602 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1604 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1607 /* Make sure all writes are flushed before telling the hardware */
1610 /* Not advertising the whole ring as the firmware gets confused if so */
1611 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1614 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1620 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1621 uint16_t nb_desc, unsigned int socket_id,
1622 const struct rte_eth_txconf *tx_conf)
1624 const struct rte_memzone *tz;
1625 struct nfp_net_txq *txq;
1626 uint16_t tx_free_thresh;
1627 struct nfp_net_hw *hw;
1629 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631 PMD_INIT_FUNC_TRACE();
1633 /* Validating number of descriptors */
1634 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1635 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1636 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1637 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1641 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1642 tx_conf->tx_free_thresh :
1643 DEFAULT_TX_FREE_THRESH);
1645 if (tx_free_thresh > (nb_desc)) {
1647 "tx_free_thresh must be less than the number of TX "
1648 "descriptors. (tx_free_thresh=%u port=%d "
1649 "queue=%d)\n", (unsigned int)tx_free_thresh,
1650 (int)dev->data->port_id, (int)queue_idx);
1655 * Free memory prior to re-allocation if needed. This is the case after
1656 * calling nfp_net_stop
1658 if (dev->data->tx_queues[queue_idx]) {
1659 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1661 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1662 dev->data->tx_queues[queue_idx] = NULL;
1665 /* Allocating tx queue data structure */
1666 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1667 RTE_CACHE_LINE_SIZE, socket_id);
1669 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1674 * Allocate TX ring hardware descriptors. A memzone large enough to
1675 * handle the maximum ring size is allocated in order to allow for
1676 * resizing in later calls to the queue setup function.
1678 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1679 sizeof(struct nfp_net_tx_desc) *
1680 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1683 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1684 nfp_net_tx_queue_release(txq);
1688 txq->tx_count = nb_desc;
1689 txq->tx_free_thresh = tx_free_thresh;
1690 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1691 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1692 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1694 /* queue mapping based on firmware configuration */
1695 txq->qidx = queue_idx;
1696 txq->tx_qcidx = queue_idx * hw->stride_tx;
1697 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1699 txq->port_id = dev->data->port_id;
1700 txq->txq_flags = tx_conf->txq_flags;
1702 /* Saving physical and virtual addresses for the TX ring */
1703 txq->dma = (uint64_t)tz->phys_addr;
1704 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1706 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1707 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1708 sizeof(*txq->txbufs) * nb_desc,
1709 RTE_CACHE_LINE_SIZE, socket_id);
1710 if (txq->txbufs == NULL) {
1711 nfp_net_tx_queue_release(txq);
1714 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1715 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1717 nfp_net_reset_tx_queue(txq);
1719 dev->data->tx_queues[queue_idx] = txq;
1723 * Telling the HW about the physical address of the TX ring and number
1724 * of descriptors in log2 format
1726 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1727 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1732 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1734 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1735 struct rte_mbuf *mb)
1738 struct nfp_net_hw *hw = txq->hw;
1740 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1743 ol_flags = mb->ol_flags;
1745 if (!(ol_flags & PKT_TX_TCP_SEG))
1748 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1749 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1750 txd->flags = PCIE_DESC_TX_LSO;
1759 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1761 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1762 struct rte_mbuf *mb)
1765 struct nfp_net_hw *hw = txq->hw;
1767 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1770 ol_flags = mb->ol_flags;
1772 /* IPv6 does not need checksum */
1773 if (ol_flags & PKT_TX_IP_CKSUM)
1774 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1776 switch (ol_flags & PKT_TX_L4_MASK) {
1777 case PKT_TX_UDP_CKSUM:
1778 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1780 case PKT_TX_TCP_CKSUM:
1781 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1785 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1786 txd->flags |= PCIE_DESC_TX_CSUM;
1789 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1791 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1792 struct rte_mbuf *mb)
1794 struct nfp_net_hw *hw = rxq->hw;
1796 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1799 /* If IPv4 and IP checksum error, fail */
1800 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1801 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1802 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1804 /* If neither UDP nor TCP return */
1805 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1806 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1809 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1810 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1811 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1813 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1814 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1815 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1818 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1819 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1821 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1824 * nfp_net_set_hash - Set mbuf hash data
1826 * The RSS hash and hash-type are pre-pended to the packet data.
1827 * Extract and decode it and set the mbuf fields.
1830 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1831 struct rte_mbuf *mbuf)
1833 struct nfp_net_hw *hw = rxq->hw;
1834 uint8_t *meta_offset;
1837 uint32_t hash_type = 0;
1839 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1842 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1843 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1846 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1847 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1849 } else if (NFP_DESC_META_LEN(rxd)) {
1852 * <---- 32 bit ----->
1857 * ====================
1860 * Field type word contains up to 8 4bit field types
1861 * A 4bit field type refers to a data field word
1862 * A data field word can have several 4bit field types
1864 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1865 meta_offset -= NFP_DESC_META_LEN(rxd);
1866 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1868 /* NFP PMD just supports metadata for hashing */
1869 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1870 case NFP_NET_META_HASH:
1871 /* next field type is about the hash type */
1872 meta_info >>= NFP_NET_META_FIELD_SIZE;
1873 /* hash value is in the data field */
1874 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1875 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1878 /* Unsupported metadata can be a performance issue */
1885 mbuf->hash.rss = hash;
1886 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1888 switch (hash_type) {
1889 case NFP_NET_RSS_IPV4:
1890 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1892 case NFP_NET_RSS_IPV6:
1893 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1895 case NFP_NET_RSS_IPV6_EX:
1896 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1899 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1904 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1906 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1909 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1914 * There are some decissions to take:
1915 * 1) How to check DD RX descriptors bit
1916 * 2) How and when to allocate new mbufs
1918 * Current implementation checks just one single DD bit each loop. As each
1919 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1920 * a single cache line instead. Tests with this change have not shown any
1921 * performance improvement but it requires further investigation. For example,
1922 * depending on which descriptor is next, the number of descriptors could be
1923 * less than 8 for just checking those in the same cache line. This implies
1924 * extra work which could be counterproductive by itself. Indeed, last firmware
1925 * changes are just doing this: writing several descriptors with the DD bit
1926 * for saving PCIe bandwidth and DMA operations from the NFP.
1928 * Mbuf allocation is done when a new packet is received. Then the descriptor
1929 * is automatically linked with the new mbuf and the old one is given to the
1930 * user. The main drawback with this design is mbuf allocation is heavier than
1931 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1932 * cache point of view it does not seem allocating the mbuf early on as we are
1933 * doing now have any benefit at all. Again, tests with this change have not
1934 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1935 * so looking at the implications of this type of allocation should be studied
1940 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1942 struct nfp_net_rxq *rxq;
1943 struct nfp_net_rx_desc *rxds;
1944 struct nfp_net_rx_buff *rxb;
1945 struct nfp_net_hw *hw;
1946 struct rte_mbuf *mb;
1947 struct rte_mbuf *new_mb;
1953 if (unlikely(rxq == NULL)) {
1955 * DPDK just checks the queue is lower than max queues
1956 * enabled. But the queue needs to be configured
1958 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1966 while (avail < nb_pkts) {
1967 rxb = &rxq->rxbufs[rxq->rd_p];
1968 if (unlikely(rxb == NULL)) {
1969 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1974 * Memory barrier to ensure that we won't do other
1975 * reads before the DD bit.
1979 rxds = &rxq->rxds[rxq->rd_p];
1980 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1984 * We got a packet. Let's alloc a new mbuff for refilling the
1985 * free descriptor ring as soon as possible
1987 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1988 if (unlikely(new_mb == NULL)) {
1989 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1990 "queue_id=%u\n", (unsigned)rxq->port_id,
1991 (unsigned)rxq->qidx);
1992 nfp_net_mbuf_alloc_failed(rxq);
1999 * Grab the mbuff and refill the descriptor with the
2000 * previously allocated mbuff
2005 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2006 rxds->rxd.data_len, rxq->mbuf_size);
2008 /* Size of this segment */
2009 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2010 /* Size of the whole packet. We just support 1 segment */
2011 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2013 if (unlikely((mb->data_len + hw->rx_offset) >
2016 * This should not happen and the user has the
2017 * responsibility of avoiding it. But we have
2018 * to give some info about the error
2020 RTE_LOG_DP(ERR, PMD,
2021 "mbuf overflow likely due to the RX offset.\n"
2022 "\t\tYour mbuf size should have extra space for"
2023 " RX offset=%u bytes.\n"
2024 "\t\tCurrently you just have %u bytes available"
2025 " but the received packet is %u bytes long",
2027 rxq->mbuf_size - hw->rx_offset,
2032 /* Filling the received mbuff with packet info */
2034 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2036 mb->data_off = RTE_PKTMBUF_HEADROOM +
2037 NFP_DESC_META_LEN(rxds);
2039 /* No scatter mode supported */
2043 /* Checking the RSS flag */
2044 nfp_net_set_hash(rxq, rxds, mb);
2046 /* Checking the checksum flag */
2047 nfp_net_rx_cksum(rxq, rxds, mb);
2049 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2050 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2051 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2052 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
2055 /* Adding the mbuff to the mbuff array passed by the app */
2056 rx_pkts[avail++] = mb;
2058 /* Now resetting and updating the descriptor */
2061 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2063 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2064 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2067 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2074 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
2075 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
2077 nb_hold += rxq->nb_rx_hold;
2080 * FL descriptors needs to be written before incrementing the
2081 * FL queue WR pointer
2084 if (nb_hold > rxq->rx_free_thresh) {
2085 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2086 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
2087 (unsigned)nb_hold, (unsigned)avail);
2088 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2091 rxq->nb_rx_hold = nb_hold;
2097 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2099 * @txq: TX queue to work with
2100 * Returns number of descriptors freed
2103 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2108 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2109 " status\n", txq->qidx);
2111 /* Work out how many packets have been sent */
2112 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2114 if (qcp_rd_p == txq->rd_p) {
2115 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2116 "packets (%u, %u)\n", txq->qidx,
2117 qcp_rd_p, txq->rd_p);
2121 if (qcp_rd_p > txq->rd_p)
2122 todo = qcp_rd_p - txq->rd_p;
2124 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2126 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2127 qcp_rd_p, txq->rd_p, txq->rd_p);
2133 if (unlikely(txq->rd_p >= txq->tx_count))
2134 txq->rd_p -= txq->tx_count;
2139 /* Leaving always free descriptors for avoiding wrapping confusion */
2141 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2143 if (txq->wr_p >= txq->rd_p)
2144 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2146 return txq->rd_p - txq->wr_p - 8;
2150 * nfp_net_txq_full - Check if the TX queue free descriptors
2151 * is below tx_free_threshold
2153 * @txq: TX queue to check
2155 * This function uses the host copy* of read/write pointers
2158 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2160 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2164 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2166 struct nfp_net_txq *txq;
2167 struct nfp_net_hw *hw;
2168 struct nfp_net_tx_desc *txds, txd;
2169 struct rte_mbuf *pkt;
2171 int pkt_size, dma_size;
2172 uint16_t free_descs, issued_descs;
2173 struct rte_mbuf **lmbuf;
2178 txds = &txq->txds[txq->wr_p];
2180 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2181 txq->qidx, txq->wr_p, nb_pkts);
2183 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2184 nfp_net_tx_free_bufs(txq);
2186 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2187 if (unlikely(free_descs == 0))
2194 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2195 txq->qidx, nb_pkts);
2196 /* Sending packets */
2197 while ((i < nb_pkts) && free_descs) {
2198 /* Grabbing the mbuf linked to the current descriptor */
2199 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2200 /* Warming the cache for releasing the mbuf later on */
2201 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2203 pkt = *(tx_pkts + i);
2205 if (unlikely((pkt->nb_segs > 1) &&
2206 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2207 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2208 rte_panic("Multisegment packet unsupported\n");
2211 /* Checking if we have enough descriptors */
2212 if (unlikely(pkt->nb_segs > free_descs))
2216 * Checksum and VLAN flags just in the first descriptor for a
2217 * multisegment packet, but TSO info needs to be in all of them.
2219 txd.data_len = pkt->pkt_len;
2220 nfp_net_tx_tso(txq, &txd, pkt);
2221 nfp_net_tx_cksum(txq, &txd, pkt);
2223 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2224 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2225 txd.flags |= PCIE_DESC_TX_VLAN;
2226 txd.vlan = pkt->vlan_tci;
2230 * mbuf data_len is the data in one segment and pkt_len data
2231 * in the whole packet. When the packet is just one segment,
2232 * then data_len = pkt_len
2234 pkt_size = pkt->pkt_len;
2237 /* Copying TSO, VLAN and cksum info */
2240 /* Releasing mbuf used by this descriptor previously*/
2242 rte_pktmbuf_free_seg(*lmbuf);
2245 * Linking mbuf with descriptor for being released
2246 * next time descriptor is used
2250 dma_size = pkt->data_len;
2251 dma_addr = rte_mbuf_data_dma_addr(pkt);
2252 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2253 "%" PRIx64 "\n", dma_addr);
2255 /* Filling descriptors fields */
2256 txds->dma_len = dma_size;
2257 txds->data_len = txd.data_len;
2258 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2259 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2260 ASSERT(free_descs > 0);
2264 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2267 pkt_size -= dma_size;
2270 txds->offset_eop |= PCIE_DESC_TX_EOP;
2272 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2275 /* Referencing next free TX descriptor */
2276 txds = &txq->txds[txq->wr_p];
2277 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2284 /* Increment write pointers. Force memory write before we let HW know */
2286 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2292 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2294 uint32_t new_ctrl, update;
2295 struct nfp_net_hw *hw;
2297 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2301 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2302 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2303 " ETH_VLAN_EXTEND_OFFLOAD");
2305 /* Enable vlan strip if it is not configured yet */
2306 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2307 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2308 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2310 /* Disable vlan strip just if it is configured */
2311 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2312 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2313 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2318 update = NFP_NET_CFG_UPDATE_GEN;
2320 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2323 hw->ctrl = new_ctrl;
2326 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2328 nfp_net_reta_update(struct rte_eth_dev *dev,
2329 struct rte_eth_rss_reta_entry64 *reta_conf,
2332 uint32_t reta, mask;
2336 struct nfp_net_hw *hw =
2337 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2342 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2343 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2344 "(%d) doesn't match the number hardware can supported "
2345 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2350 * Update Redirection Table. There are 128 8bit-entries which can be
2351 * manage as 32 32bit-entries
2353 for (i = 0; i < reta_size; i += 4) {
2354 /* Handling 4 RSS entries per loop */
2355 idx = i / RTE_RETA_GROUP_SIZE;
2356 shift = i % RTE_RETA_GROUP_SIZE;
2357 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2363 /* If all 4 entries were set, don't need read RETA register */
2365 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2367 for (j = 0; j < 4; j++) {
2368 if (!(mask & (0x1 << j)))
2371 /* Clearing the entry bits */
2372 reta &= ~(0xFF << (8 * j));
2373 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2375 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2379 update = NFP_NET_CFG_UPDATE_RSS;
2381 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2387 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2389 nfp_net_reta_query(struct rte_eth_dev *dev,
2390 struct rte_eth_rss_reta_entry64 *reta_conf,
2396 struct nfp_net_hw *hw;
2398 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2403 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2404 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2405 "(%d) doesn't match the number hardware can supported "
2406 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2411 * Reading Redirection Table. There are 128 8bit-entries which can be
2412 * manage as 32 32bit-entries
2414 for (i = 0; i < reta_size; i += 4) {
2415 /* Handling 4 RSS entries per loop */
2416 idx = i / RTE_RETA_GROUP_SIZE;
2417 shift = i % RTE_RETA_GROUP_SIZE;
2418 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2423 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2425 for (j = 0; j < 4; j++) {
2426 if (!(mask & (0x1 << j)))
2428 reta_conf->reta[shift + j] =
2429 (uint8_t)((reta >> (8 * j)) & 0xF);
2436 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2437 struct rte_eth_rss_conf *rss_conf)
2440 uint32_t cfg_rss_ctrl = 0;
2444 struct nfp_net_hw *hw;
2446 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448 rss_hf = rss_conf->rss_hf;
2450 /* Checking if RSS is enabled */
2451 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2452 if (rss_hf != 0) { /* Enable RSS? */
2453 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2456 return 0; /* Nothing to do */
2459 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2460 RTE_LOG(ERR, PMD, "hash key too long\n");
2464 if (rss_hf & ETH_RSS_IPV4)
2465 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2466 NFP_NET_CFG_RSS_IPV4_TCP |
2467 NFP_NET_CFG_RSS_IPV4_UDP;
2469 if (rss_hf & ETH_RSS_IPV6)
2470 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2471 NFP_NET_CFG_RSS_IPV6_TCP |
2472 NFP_NET_CFG_RSS_IPV6_UDP;
2474 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2475 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2477 /* configuring where to apply the RSS hash */
2478 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2480 /* Writing the key byte a byte */
2481 for (i = 0; i < rss_conf->rss_key_len; i++) {
2482 memcpy(&key, &rss_conf->rss_key[i], 1);
2483 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2486 /* Writing the key size */
2487 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2489 update = NFP_NET_CFG_UPDATE_RSS;
2491 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2498 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2499 struct rte_eth_rss_conf *rss_conf)
2502 uint32_t cfg_rss_ctrl;
2505 struct nfp_net_hw *hw;
2507 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2512 rss_hf = rss_conf->rss_hf;
2513 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2515 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2516 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2518 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2519 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2521 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2522 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2524 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2525 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2527 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2528 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2530 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2531 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2533 /* Reading the key size */
2534 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2536 /* Reading the key byte a byte */
2537 for (i = 0; i < rss_conf->rss_key_len; i++) {
2538 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2539 memcpy(&rss_conf->rss_key[i], &key, 1);
2545 /* Initialise and register driver with DPDK Application */
2546 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2547 .dev_configure = nfp_net_configure,
2548 .dev_start = nfp_net_start,
2549 .dev_stop = nfp_net_stop,
2550 .dev_close = nfp_net_close,
2551 .promiscuous_enable = nfp_net_promisc_enable,
2552 .promiscuous_disable = nfp_net_promisc_disable,
2553 .link_update = nfp_net_link_update,
2554 .stats_get = nfp_net_stats_get,
2555 .stats_reset = nfp_net_stats_reset,
2556 .dev_infos_get = nfp_net_infos_get,
2557 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2558 .mtu_set = nfp_net_dev_mtu_set,
2559 .vlan_offload_set = nfp_net_vlan_offload_set,
2560 .reta_update = nfp_net_reta_update,
2561 .reta_query = nfp_net_reta_query,
2562 .rss_hash_update = nfp_net_rss_hash_update,
2563 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2564 .rx_queue_setup = nfp_net_rx_queue_setup,
2565 .rx_queue_release = nfp_net_rx_queue_release,
2566 .rx_queue_count = nfp_net_rx_queue_count,
2567 .tx_queue_setup = nfp_net_tx_queue_setup,
2568 .tx_queue_release = nfp_net_tx_queue_release,
2569 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2570 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2574 * All eth_dev created got its private data, but before nfp_net_init, that
2575 * private data is referencing private data for all the PF ports. This is due
2576 * to how the vNIC bars are mapped based on first port, so all ports need info
2577 * about port 0 private data. Inside nfp_net_init the private data pointer is
2578 * changed to the right address for each port once the bars have been mapped.
2580 * This functions helps to find out which port and therefore which offset
2581 * inside the private data array to use.
2584 get_pf_port_number(char *name)
2586 char *pf_str = name;
2589 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2594 * This should not happen at all and it would mean major
2595 * implementation fault.
2597 rte_panic("nfp_net: problem with pf device name\n");
2599 /* Expecting _portX with X within [0,7] */
2602 return (int)strtol(pf_str, NULL, 10);
2606 nfp_net_init(struct rte_eth_dev *eth_dev)
2608 struct rte_pci_device *pci_dev;
2609 struct nfp_net_hw *hw, *hwport0;
2611 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2615 nspu_desc_t *nspu_desc = NULL;
2616 uint64_t bar_offset;
2619 PMD_INIT_FUNC_TRACE();
2621 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2623 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2624 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2625 port = get_pf_port_number(eth_dev->data->name);
2626 if (port < 0 || port > 7) {
2627 RTE_LOG(ERR, PMD, "Port value is wrong\n");
2631 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2633 /* This points to port 0 private data */
2634 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2636 /* This points to the specific port private data */
2637 hw = &hwport0[port];
2638 hw->pf_port_idx = port;
2640 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2644 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2645 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2646 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2648 /* For secondary processes, the primary has done all the work */
2649 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2652 rte_eth_copy_pci_info(eth_dev, pci_dev);
2653 /* hotplug is not possible with multiport PF */
2654 if (!hw->pf_multiport_enabled)
2655 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2657 hw->device_id = pci_dev->id.device_id;
2658 hw->vendor_id = pci_dev->id.vendor_id;
2659 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2660 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2662 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2663 pci_dev->id.vendor_id, pci_dev->id.device_id,
2664 pci_dev->addr.domain, pci_dev->addr.bus,
2665 pci_dev->addr.devid, pci_dev->addr.function);
2667 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2668 if (hw->ctrl_bar == NULL) {
2670 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2674 if (hw->is_pf && port == 0) {
2675 nspu_desc = hw->nspu_desc;
2677 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2679 * A firmware should be there after PF probe so this
2680 * should not happen.
2682 RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2686 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2687 hw->ctrl_bar += bar_offset;
2688 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2692 if (!hwport0->ctrl_bar)
2695 /* address based on port0 offset */
2696 hw->ctrl_bar = hwport0->ctrl_bar +
2697 (port * NFP_PF_CSR_SLICE_SIZE);
2700 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2702 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2703 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2705 /* Work out where in the BAR the queues start. */
2706 switch (pci_dev->id.device_id) {
2707 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2708 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2709 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2710 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2711 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2712 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2713 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2716 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2720 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2721 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2723 if (hw->is_pf && port == 0) {
2724 /* configure access to tx/rx vNIC BARs */
2725 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2726 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2728 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2730 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2731 hwport0->hw_queues += bar_offset;
2733 /* Lets seize the chance to read eth table from hw */
2734 if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
2739 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2740 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2741 eth_dev->data->dev_private = hw;
2743 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2745 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2749 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2750 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2752 nfp_net_cfg_queue_setup(hw);
2754 /* Get some of the read-only fields from the config BAR */
2755 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2756 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2757 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2758 hw->mtu = hw->max_mtu;
2760 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2761 hw->rx_offset = NFP_NET_RX_OFFSET;
2763 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2765 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2766 hw->ver, hw->max_mtu);
2767 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2768 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2769 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2770 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2771 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2772 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2773 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2774 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2775 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2776 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2780 hw->stride_rx = stride;
2781 hw->stride_tx = stride;
2783 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2784 hw->max_rx_queues, hw->max_tx_queues);
2786 /* Initializing spinlock for reconfigs */
2787 rte_spinlock_init(&hw->reconfig_lock);
2789 /* Allocating memory for mac addr */
2790 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2791 if (eth_dev->data->mac_addrs == NULL) {
2792 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2797 nfp_net_pf_read_mac(hwport0, port);
2799 nfp_net_vf_read_mac(hw);
2801 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2802 /* Using random mac addresses for VFs */
2803 eth_random_addr(&hw->mac_addr[0]);
2804 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2807 /* Copying mac address to DPDK eth_dev struct */
2808 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2809 ð_dev->data->mac_addrs[0]);
2811 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2812 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2813 eth_dev->data->port_id, pci_dev->id.vendor_id,
2814 pci_dev->id.device_id,
2815 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2816 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2818 /* Registering LSC interrupt handler */
2819 rte_intr_callback_register(&pci_dev->intr_handle,
2820 nfp_net_dev_interrupt_handler,
2823 /* Telling the firmware about the LSC interrupt entry */
2824 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2826 /* Recording current stats counters values */
2827 nfp_net_stats_reset(eth_dev);
2833 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2834 nfpu_desc_t *nfpu_desc, void **priv)
2836 struct rte_eth_dev *eth_dev;
2837 struct nfp_net_hw *hw;
2841 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2846 sprintf(port_name, "%s_port%d", dev->device.name, port);
2848 sprintf(port_name, "%s", dev->device.name);
2850 eth_dev = rte_eth_dev_allocate(port_name);
2855 *priv = rte_zmalloc(port_name,
2856 sizeof(struct nfp_net_adapter) * ports,
2857 RTE_CACHE_LINE_SIZE);
2859 rte_eth_dev_release_port(eth_dev);
2864 eth_dev->data->dev_private = *priv;
2867 * dev_private pointing to port0 dev_private because we need
2868 * to configure vNIC bars based on port0 at nfp_net_init.
2869 * Then dev_private is adjusted per port.
2871 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2872 hw->nspu_desc = nfpu_desc->nspu;
2873 hw->nfpu_desc = nfpu_desc;
2876 hw->pf_multiport_enabled = 1;
2878 eth_dev->device = &dev->device;
2879 rte_eth_copy_pci_info(eth_dev, dev);
2881 ret = nfp_net_init(eth_dev);
2884 rte_eth_dev_release_port(eth_dev);
2886 rte_free(port_name);
2891 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2892 struct rte_pci_device *dev)
2894 nfpu_desc_t *nfpu_desc;
2895 nspu_desc_t *nspu_desc;
2896 uint64_t offset_symbol;
2897 uint8_t *bar_offset;
2907 nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2911 if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2913 "nfpu_open failed\n");
2917 nspu_desc = nfpu_desc->nspu;
2920 /* Check NSP ABI version */
2921 if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2922 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2925 PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2927 if ((major == 0) && (minor < 20)) {
2928 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2932 ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2937 bar_offset = (uint8_t *)dev->mem_resource[0].addr;
2938 bar_offset += offset_symbol;
2939 total_ports = (uint32_t)*bar_offset;
2940 PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
2942 if (total_ports <= 0 || total_ports > 8) {
2943 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
2948 for (i = 0; i < total_ports; i++) {
2949 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
2957 nfpu_close(nfpu_desc);
2959 rte_free(nfpu_desc);
2964 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2966 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2967 PCI_DEVICE_ID_NFP4000_PF_NIC)
2970 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2971 PCI_DEVICE_ID_NFP6000_PF_NIC)
2978 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
2980 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2981 PCI_DEVICE_ID_NFP6000_VF_NIC)
2988 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2989 struct rte_pci_device *pci_dev)
2991 return rte_eth_dev_pci_generic_probe(pci_dev,
2992 sizeof(struct nfp_net_adapter), nfp_net_init);
2995 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
2997 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3000 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3001 .id_table = pci_id_nfp_pf_net_map,
3002 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3003 .probe = nfp_pf_pci_probe,
3004 .remove = eth_nfp_pci_remove,
3007 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3008 .id_table = pci_id_nfp_vf_net_map,
3009 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3010 .probe = eth_nfp_pci_probe,
3011 .remove = eth_nfp_pci_remove,
3014 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3015 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3016 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3017 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3018 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3019 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3023 * c-file-style: "Linux"
3024 * indent-tabs-mode: t