1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Netronome Systems, Inc.
8 * Authors: Vinayak Tammineedi <vinayak.tammineedi@netronome.com>
10 * Multiplexes the NFP BARs between NFP internal resources and
11 * implements the PCIe specific interface for generic CPP bus access.
13 * The BARs are managed and allocated if they are available.
14 * The generic CPP bus abstraction builds upon this BAR interface.
34 #include <rte_ethdev_pci.h>
35 #include <rte_string_fns.h>
38 #include "nfp_target.h"
39 #include "nfp6000/nfp6000.h"
41 #define NFP_PCIE_BAR(_pf) (0x30000 + ((_pf) & 7) * 0xc0)
43 #define NFP_PCIE_BAR_PCIE2CPP_ACTION_BASEADDRESS(_x) (((_x) & 0x1f) << 16)
44 #define NFP_PCIE_BAR_PCIE2CPP_BASEADDRESS(_x) (((_x) & 0xffff) << 0)
45 #define NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT(_x) (((_x) & 0x3) << 27)
46 #define NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_32BIT 0
47 #define NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_64BIT 1
48 #define NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_0BYTE 3
49 #define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE(_x) (((_x) & 0x7) << 29)
50 #define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_OF(_x) (((_x) >> 29) & 0x7)
51 #define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_FIXED 0
52 #define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_BULK 1
53 #define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_TARGET 2
54 #define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_GENERAL 3
55 #define NFP_PCIE_BAR_PCIE2CPP_TARGET_BASEADDRESS(_x) (((_x) & 0xf) << 23)
56 #define NFP_PCIE_BAR_PCIE2CPP_TOKEN_BASEADDRESS(_x) (((_x) & 0x3) << 21)
59 * Minimal size of the PCIe cfg memory we depend on being mapped,
60 * queue controller and DMA controller don't have to be covered.
62 #define NFP_PCI_MIN_MAP_SIZE 0x080000
64 #define NFP_PCIE_P2C_FIXED_SIZE(bar) (1 << (bar)->bitsize)
65 #define NFP_PCIE_P2C_BULK_SIZE(bar) (1 << (bar)->bitsize)
66 #define NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(bar, x) ((x) << ((bar)->bitsize - 2))
67 #define NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(bar, x) ((x) << ((bar)->bitsize - 4))
68 #define NFP_PCIE_P2C_GENERAL_SIZE(bar) (1 << ((bar)->bitsize - 4))
70 #define NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(bar, slot) \
71 (NFP_PCIE_BAR(0) + ((bar) * 8 + (slot)) * 4)
73 #define NFP_PCIE_CPP_BAR_PCIETOCPPEXPBAR(bar, slot) \
74 (((bar) * 8 + (slot)) * 4)
77 * Define to enable a bit more verbose debug output.
78 * Set to 1 to enable a bit more verbose debug output.
81 struct nfp6000_area_priv;
84 * struct nfp_bar - describes BAR configuration and usage
85 * @nfp: backlink to owner
86 * @barcfg: cached contents of BAR config CSR
87 * @base: the BAR's base CPP offset
88 * @mask: mask for the BAR aperture (read only)
89 * @bitsize: bitsize of BAR aperture (read only)
90 * @index: index of the BAR
91 * @lock: lock to specify if bar is in use
92 * @refcnt: number of current users
93 * @iomem: mapped IO memory
97 struct nfp_pcie_user *nfp;
99 uint64_t base; /* CPP address base */
100 uint64_t mask; /* Bit mask of the bar */
101 uint32_t bitsize; /* Bit size of the bar */
110 struct nfp_pcie_user {
111 struct nfp_bar bar[NFP_BAR_MAX];
115 char busdev[BUSDEV_SZ];
121 nfp_bar_maptype(struct nfp_bar *bar)
123 return NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_OF(bar->barcfg);
126 #define TARGET_WIDTH_32 4
127 #define TARGET_WIDTH_64 8
130 nfp_compute_bar(const struct nfp_bar *bar, uint32_t *bar_config,
131 uint64_t *bar_base, int tgt, int act, int tok,
132 uint64_t offset, size_t size, int width)
144 NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT
145 (NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_64BIT);
149 NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT
150 (NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_32BIT);
154 NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT
155 (NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_0BYTE);
161 if (act != NFP_CPP_ACTION_RW && act != 0) {
162 /* Fixed CPP mapping with specific action */
163 mask = ~(NFP_PCIE_P2C_FIXED_SIZE(bar) - 1);
166 NFP_PCIE_BAR_PCIE2CPP_MAPTYPE
167 (NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_FIXED);
168 newcfg |= NFP_PCIE_BAR_PCIE2CPP_TARGET_BASEADDRESS(tgt);
169 newcfg |= NFP_PCIE_BAR_PCIE2CPP_ACTION_BASEADDRESS(act);
170 newcfg |= NFP_PCIE_BAR_PCIE2CPP_TOKEN_BASEADDRESS(tok);
172 if ((offset & mask) != ((offset + size - 1) & mask)) {
173 printf("BAR%d: Won't use for Fixed mapping\n",
175 printf("\t<%#llx,%#llx>, action=%d\n",
176 (unsigned long long)offset,
177 (unsigned long long)(offset + size), act);
178 printf("\tBAR too small (0x%llx).\n",
179 (unsigned long long)mask);
185 printf("BAR%d: Created Fixed mapping\n", bar->index);
186 printf("\t%d:%d:%d:0x%#llx-0x%#llx>\n", tgt, act, tok,
187 (unsigned long long)offset,
188 (unsigned long long)(offset + mask));
193 mask = ~(NFP_PCIE_P2C_BULK_SIZE(bar) - 1);
197 NFP_PCIE_BAR_PCIE2CPP_MAPTYPE
198 (NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_BULK);
200 newcfg |= NFP_PCIE_BAR_PCIE2CPP_TARGET_BASEADDRESS(tgt);
201 newcfg |= NFP_PCIE_BAR_PCIE2CPP_TOKEN_BASEADDRESS(tok);
203 if ((offset & mask) != ((offset + size - 1) & mask)) {
204 printf("BAR%d: Won't use for bulk mapping\n",
206 printf("\t<%#llx,%#llx>\n", (unsigned long long)offset,
207 (unsigned long long)(offset + size));
208 printf("\ttarget=%d, token=%d\n", tgt, tok);
209 printf("\tBAR too small (%#llx) - (%#llx != %#llx).\n",
210 (unsigned long long)mask,
211 (unsigned long long)(offset & mask),
212 (unsigned long long)(offset + size - 1) & mask);
220 printf("BAR%d: Created bulk mapping %d:x:%d:%#llx-%#llx\n",
221 bar->index, tgt, tok, (unsigned long long)offset,
222 (unsigned long long)(offset + ~mask));
228 if (bar->bitsize < bitsize) {
229 printf("BAR%d: Too small for %d:%d:%d\n", bar->index, tgt, tok,
234 newcfg |= offset >> bitsize;
240 *bar_config = newcfg;
246 nfp_bar_write(struct nfp_pcie_user *nfp, struct nfp_bar *bar,
251 base = bar->index >> 3;
252 slot = bar->index & 7;
257 bar->csr = nfp->cfg +
258 NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(base, slot);
260 *(uint32_t *)(bar->csr) = newcfg;
262 bar->barcfg = newcfg;
264 printf("BAR%d: updated to 0x%08x\n", bar->index, newcfg);
271 nfp_reconfigure_bar(struct nfp_pcie_user *nfp, struct nfp_bar *bar, int tgt,
272 int act, int tok, uint64_t offset, size_t size, int width)
278 err = nfp_compute_bar(bar, &newcfg, &newbase, tgt, act, tok, offset,
285 return nfp_bar_write(nfp, bar, newcfg);
289 * Map all PCI bars. We assume that the BAR with the PCIe config block is
292 * BAR0.0: Reserved for General Mapping (for MSI-X access to PCIe SRAM)
295 nfp_enable_bars(struct nfp_pcie_user *nfp)
300 for (x = ARRAY_SIZE(nfp->bar); x > 0; x--) {
301 bar = &nfp->bar[x - 1];
305 bar->mask = (1 << (nfp->barsz - 3)) - 1;
306 bar->bitsize = nfp->barsz - 3;
310 bar->csr = nfp->cfg +
311 NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(bar->index >> 3,
314 bar->iomem = nfp->cfg + (bar->index << bar->bitsize);
319 static struct nfp_bar *
320 nfp_alloc_bar(struct nfp_pcie_user *nfp)
325 for (x = ARRAY_SIZE(nfp->bar); x > 0; x--) {
326 bar = &nfp->bar[x - 1];
336 nfp_disable_bars(struct nfp_pcie_user *nfp)
341 for (x = ARRAY_SIZE(nfp->bar); x > 0; x--) {
342 bar = &nfp->bar[x - 1];
351 * Generic CPP bus access interface.
354 struct nfp6000_area_priv {
372 nfp6000_area_init(struct nfp_cpp_area *area, uint32_t dest,
373 unsigned long long address, unsigned long size)
375 struct nfp_pcie_user *nfp = nfp_cpp_priv(nfp_cpp_area_cpp(area));
376 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
377 uint32_t target = NFP_CPP_ID_TARGET_of(dest);
378 uint32_t action = NFP_CPP_ID_ACTION_of(dest);
379 uint32_t token = NFP_CPP_ID_TOKEN_of(dest);
382 pp = nfp6000_target_pushpull(NFP_CPP_ID(target, action, token),
387 priv->width.read = PUSH_WIDTH(pp);
388 priv->width.write = PULL_WIDTH(pp);
390 if (priv->width.read > 0 &&
391 priv->width.write > 0 && priv->width.read != priv->width.write)
394 if (priv->width.read > 0)
395 priv->width.bar = priv->width.read;
397 priv->width.bar = priv->width.write;
399 priv->bar = nfp_alloc_bar(nfp);
400 if (priv->bar == NULL)
403 priv->target = target;
404 priv->action = action;
406 priv->offset = address;
409 ret = nfp_reconfigure_bar(nfp, priv->bar, priv->target, priv->action,
410 priv->token, priv->offset, priv->size,
417 nfp6000_area_acquire(struct nfp_cpp_area *area)
419 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
421 /* Calculate offset into BAR. */
422 if (nfp_bar_maptype(priv->bar) ==
423 NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_GENERAL) {
424 priv->bar_offset = priv->offset &
425 (NFP_PCIE_P2C_GENERAL_SIZE(priv->bar) - 1);
427 NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(priv->bar,
430 NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(priv->bar, priv->token);
432 priv->bar_offset = priv->offset & priv->bar->mask;
435 /* Must have been too big. Sub-allocate. */
436 if (!priv->bar->iomem)
439 priv->iomem = priv->bar->iomem + priv->bar_offset;
445 nfp6000_area_mapped(struct nfp_cpp_area *area)
447 struct nfp6000_area_priv *area_priv = nfp_cpp_area_priv(area);
449 if (!area_priv->iomem)
452 return area_priv->iomem;
456 nfp6000_area_release(struct nfp_cpp_area *area)
458 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
465 nfp6000_area_iomem(struct nfp_cpp_area *area)
467 struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);
472 nfp6000_area_read(struct nfp_cpp_area *area, void *kernel_vaddr,
473 unsigned long offset, unsigned int length)
475 uint64_t *wrptr64 = kernel_vaddr;
476 const volatile uint64_t *rdptr64;
477 struct nfp6000_area_priv *priv;
478 uint32_t *wrptr32 = kernel_vaddr;
479 const volatile uint32_t *rdptr32;
484 priv = nfp_cpp_area_priv(area);
485 rdptr64 = (uint64_t *)(priv->iomem + offset);
486 rdptr32 = (uint32_t *)(priv->iomem + offset);
488 if (offset + length > priv->size)
491 width = priv->width.read;
496 /* Unaligned? Translate to an explicit access */
497 if ((priv->offset + offset) & (width - 1)) {
498 printf("aread_read unaligned!!!\n");
502 is_64 = width == TARGET_WIDTH_64;
504 /* MU reads via a PCIe2CPP BAR supports 32bit (and other) lengths */
505 if (priv->target == (NFP_CPP_TARGET_ID_MASK & NFP_CPP_TARGET_MU) &&
506 priv->action == NFP_CPP_ACTION_RW) {
511 if (offset % sizeof(uint64_t) != 0 ||
512 length % sizeof(uint64_t) != 0)
515 if (offset % sizeof(uint32_t) != 0 ||
516 length % sizeof(uint32_t) != 0)
524 for (n = 0; n < length; n += sizeof(uint64_t)) {
530 for (n = 0; n < length; n += sizeof(uint32_t)) {
540 nfp6000_area_write(struct nfp_cpp_area *area, const void *kernel_vaddr,
541 unsigned long offset, unsigned int length)
543 const uint64_t *rdptr64 = kernel_vaddr;
545 const uint32_t *rdptr32 = kernel_vaddr;
546 struct nfp6000_area_priv *priv;
552 priv = nfp_cpp_area_priv(area);
553 wrptr64 = (uint64_t *)(priv->iomem + offset);
554 wrptr32 = (uint32_t *)(priv->iomem + offset);
556 if (offset + length > priv->size)
559 width = priv->width.write;
564 /* Unaligned? Translate to an explicit access */
565 if ((priv->offset + offset) & (width - 1))
568 is_64 = width == TARGET_WIDTH_64;
570 /* MU writes via a PCIe2CPP BAR supports 32bit (and other) lengths */
571 if (priv->target == (NFP_CPP_TARGET_ID_MASK & NFP_CPP_TARGET_MU) &&
572 priv->action == NFP_CPP_ACTION_RW)
576 if (offset % sizeof(uint64_t) != 0 ||
577 length % sizeof(uint64_t) != 0)
580 if (offset % sizeof(uint32_t) != 0 ||
581 length % sizeof(uint32_t) != 0)
589 for (n = 0; n < length; n += sizeof(uint64_t)) {
595 for (n = 0; n < length; n += sizeof(uint32_t)) {
604 #define PCI_DEVICES "/sys/bus/pci/devices"
607 nfp_acquire_process_lock(struct nfp_pcie_user *desc)
613 memset(&lock, 0, sizeof(lock));
615 snprintf(lockname, sizeof(lockname), "/var/lock/nfp_%s", desc->busdev);
616 desc->lock = open(lockname, O_RDWR | O_CREAT, 0666);
620 lock.l_type = F_WRLCK;
621 lock.l_whence = SEEK_SET;
624 rc = fcntl(desc->lock, F_SETLKW, &lock);
626 if (errno != EAGAIN && errno != EACCES) {
637 nfp6000_set_model(struct rte_pci_device *dev, struct nfp_cpp *cpp)
641 if (rte_pci_read_config(dev, &model, 4, 0x2e) < 0) {
642 printf("nfp set model failed\n");
647 nfp_cpp_model_set(cpp, model);
653 nfp6000_set_interface(struct rte_pci_device *dev, struct nfp_cpp *cpp)
657 if (rte_pci_read_config(dev, &interface, 2, 0x154) < 0) {
658 printf("nfp set interface failed\n");
662 nfp_cpp_interface_set(cpp, interface);
667 #define PCI_CFG_SPACE_SIZE 256
668 #define PCI_CFG_SPACE_EXP_SIZE 4096
669 #define PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff)
670 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
671 #define PCI_EXT_CAP_ID_DSN 0x03
673 nfp_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
677 int pos = PCI_CFG_SPACE_SIZE;
679 /* minimum 8 bytes per capability */
680 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
682 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
683 printf("nfp error reading extended capabilities\n");
688 * If we have no capabilities, this is indicated by cap ID,
689 * cap version and next pointer all being 0.
695 if (PCI_EXT_CAP_ID(header) == cap)
698 pos = PCI_EXT_CAP_NEXT(header);
699 if (pos < PCI_CFG_SPACE_SIZE)
702 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
703 printf("nfp error reading extended capabilities\n");
712 nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp)
719 pos = nfp_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
721 printf("PCI_EXT_CAP_ID_DSN not found. nfp set serial failed\n");
727 if (rte_pci_read_config(dev, &tmp, 2, pos) < 0) {
728 printf("nfp set serial failed\n");
732 serial[4] = (uint8_t)((tmp >> 8) & 0xff);
733 serial[5] = (uint8_t)(tmp & 0xff);
736 if (rte_pci_read_config(dev, &tmp, 2, pos) < 0) {
737 printf("nfp set serial failed\n");
741 serial[2] = (uint8_t)((tmp >> 8) & 0xff);
742 serial[3] = (uint8_t)(tmp & 0xff);
745 if (rte_pci_read_config(dev, &tmp, 2, pos) < 0) {
746 printf("nfp set serial failed\n");
750 serial[0] = (uint8_t)((tmp >> 8) & 0xff);
751 serial[1] = (uint8_t)(tmp & 0xff);
753 nfp_cpp_serial_set(cpp, serial, serial_len);
759 nfp6000_set_barsz(struct rte_pci_device *dev, struct nfp_pcie_user *desc)
764 tmp = dev->mem_resource[0].len;
774 nfp6000_init(struct nfp_cpp *cpp, struct rte_pci_device *dev)
778 struct nfp_pcie_user *desc;
780 desc = malloc(sizeof(*desc));
785 memset(desc->busdev, 0, BUSDEV_SZ);
786 strlcpy(desc->busdev, dev->device.name, sizeof(desc->busdev));
788 if (cpp->driver_lock_needed) {
789 ret = nfp_acquire_process_lock(desc);
794 if (nfp6000_set_model(dev, cpp) < 0)
796 if (nfp6000_set_interface(dev, cpp) < 0)
798 if (nfp6000_set_serial(dev, cpp) < 0)
800 if (nfp6000_set_barsz(dev, desc) < 0)
803 desc->cfg = (char *)dev->mem_resource[0].addr;
805 nfp_enable_bars(desc);
807 nfp_cpp_priv_set(cpp, desc);
809 model = __nfp_cpp_model_autodetect(cpp);
810 nfp_cpp_model_set(cpp, model);
816 nfp6000_free(struct nfp_cpp *cpp)
818 struct nfp_pcie_user *desc = nfp_cpp_priv(cpp);
820 nfp_disable_bars(desc);
821 if (cpp->driver_lock_needed)
827 static const struct nfp_cpp_operations nfp6000_pcie_ops = {
828 .init = nfp6000_init,
829 .free = nfp6000_free,
831 .area_priv_size = sizeof(struct nfp6000_area_priv),
832 .area_init = nfp6000_area_init,
833 .area_acquire = nfp6000_area_acquire,
834 .area_release = nfp6000_area_release,
835 .area_mapped = nfp6000_area_mapped,
836 .area_read = nfp6000_area_read,
837 .area_write = nfp6000_area_write,
838 .area_iomem = nfp6000_area_iomem,
842 nfp_cpp_operations *nfp_cpp_transport_operations(void)
844 return &nfp6000_pcie_ops;