1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_ethdev_pci.h>
10 #include <rte_malloc.h>
12 #include <rte_mbuf_pool_ops.h>
13 #include <rte_mempool.h>
15 #include "otx2_ethdev.h"
18 otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)
20 RTE_SET_USED(eth_dev);
23 static inline uint64_t
24 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
26 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
28 if (otx2_dev_is_vf(dev))
29 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
34 static inline uint64_t
35 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
39 return NIX_TX_OFFLOAD_CAPA;
42 static const struct otx2_dev_ops otx2_dev_ops = {
43 .link_status_update = otx2_eth_dev_link_status_update,
44 .ptp_info_update = otx2_eth_dev_ptp_info_update
48 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
50 struct otx2_mbox *mbox = dev->mbox;
51 struct nix_lf_alloc_req *req;
52 struct nix_lf_alloc_rsp *rsp;
55 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
59 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
60 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
61 req->xqe_sz = NIX_XQESZ_W16;
62 req->rss_sz = dev->rss_info.rss_size;
63 req->rss_grps = NIX_RSS_GRPS;
64 req->npa_func = otx2_npa_pf_func_get();
65 req->sso_func = otx2_sso_pf_func_get();
66 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
67 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
68 DEV_RX_OFFLOAD_UDP_CKSUM)) {
69 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
70 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
73 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
77 dev->sqb_size = rsp->sqb_size;
78 dev->tx_chan_base = rsp->tx_chan_base;
79 dev->rx_chan_base = rsp->rx_chan_base;
80 dev->rx_chan_cnt = rsp->rx_chan_cnt;
81 dev->tx_chan_cnt = rsp->tx_chan_cnt;
82 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
83 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
84 dev->lf_tx_stats = rsp->lf_tx_stats;
85 dev->lf_rx_stats = rsp->lf_rx_stats;
86 dev->cints = rsp->cints;
87 dev->qints = rsp->qints;
88 dev->npc_flow.channel = dev->rx_chan_base;
94 nix_lf_free(struct otx2_eth_dev *dev)
96 struct otx2_mbox *mbox = dev->mbox;
97 struct nix_lf_free_req *req;
98 struct ndc_sync_op *ndc_req;
101 /* Sync NDC-NIX for LF */
102 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
103 ndc_req->nix_lf_tx_sync = 1;
104 ndc_req->nix_lf_rx_sync = 1;
105 rc = otx2_mbox_process(mbox);
107 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
109 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
110 /* Let AF driver free all this nix lf's
111 * NPC entries allocated using NPC MBOX.
115 return otx2_mbox_process(mbox);
119 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
121 struct otx2_mbox *mbox = dev->mbox;
123 if (otx2_dev_is_vf(dev))
126 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
128 return otx2_mbox_process(mbox);
132 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
134 struct otx2_mbox *mbox = dev->mbox;
136 if (otx2_dev_is_vf(dev))
139 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
141 return otx2_mbox_process(mbox);
145 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
151 static inline uint32_t
152 nix_qsize_to_val(enum nix_q_size_e qsize)
154 return (16UL << (qsize * 2));
157 static inline enum nix_q_size_e
158 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
162 if (otx2_ethdev_fixup_is_min_4k_q(dev))
167 for (; i < nix_q_size_max; i++)
168 if (val <= nix_qsize_to_val(i))
171 if (i >= nix_q_size_max)
172 i = nix_q_size_max - 1;
178 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
179 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
181 struct otx2_mbox *mbox = dev->mbox;
182 const struct rte_memzone *rz;
183 uint32_t ring_size, cq_size;
184 struct nix_aq_enq_req *aq;
189 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
190 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
191 NIX_CQ_ALIGN, dev->node);
193 otx2_err("Failed to allocate mem for cq hw ring");
197 memset(rz->addr, 0, rz->len);
198 rxq->desc = (uintptr_t)rz->addr;
199 rxq->qmask = cq_size - 1;
201 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
203 aq->ctype = NIX_AQ_CTYPE_CQ;
204 aq->op = NIX_AQ_INSTOP_INIT;
208 aq->cq.qsize = rxq->qsize;
209 aq->cq.base = rz->iova;
210 aq->cq.avg_level = 0xff;
211 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
212 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
214 /* TX pause frames enable flowctrl on RX side */
215 if (dev->fc_info.tx_pause) {
216 /* Single bpid is allocated for all rx channels for now */
217 aq->cq.bpid = dev->fc_info.bpid[0];
218 aq->cq.bp = NIX_CQ_BP_LEVEL;
222 /* Many to one reduction */
223 aq->cq.qint_idx = qid % dev->qints;
225 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
226 uint16_t min_rx_drop;
227 const float rx_cq_skid = 1024 * 256;
229 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
230 aq->cq.drop = min_rx_drop;
234 rc = otx2_mbox_process(mbox);
236 otx2_err("Failed to init cq context");
240 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
242 aq->ctype = NIX_AQ_CTYPE_RQ;
243 aq->op = NIX_AQ_INSTOP_INIT;
246 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
248 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
249 first_skip = (sizeof(struct rte_mbuf));
250 first_skip += RTE_PKTMBUF_HEADROOM;
251 first_skip += rte_pktmbuf_priv_size(mp);
252 rxq->data_off = first_skip;
254 first_skip /= 8; /* Expressed in number of dwords */
255 aq->rq.first_skip = first_skip;
256 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
257 aq->rq.flow_tagw = 32; /* 32-bits */
258 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
259 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
260 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
261 aq->rq.lpb_sizem1 /= 8;
262 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
264 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
265 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
266 aq->rq.rq_int_ena = 0;
267 /* Many to one reduction */
268 aq->rq.qint_idx = qid % dev->qints;
270 if (otx2_ethdev_fixup_is_limit_cq_full(dev))
271 aq->rq.xqe_drop_ena = 1;
273 rc = otx2_mbox_process(mbox);
275 otx2_err("Failed to init rq context");
285 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
286 struct otx2_eth_rxq *rxq, const bool enb)
288 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
289 struct otx2_mbox *mbox = dev->mbox;
290 struct nix_aq_enq_req *aq;
292 /* Pkts will be dropped silently if RQ is disabled */
293 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
295 aq->ctype = NIX_AQ_CTYPE_RQ;
296 aq->op = NIX_AQ_INSTOP_WRITE;
299 aq->rq_mask.ena = ~(aq->rq_mask.ena);
301 return otx2_mbox_process(mbox);
305 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
307 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
308 struct otx2_mbox *mbox = dev->mbox;
309 struct nix_aq_enq_req *aq;
312 /* RQ is already disabled */
314 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
316 aq->ctype = NIX_AQ_CTYPE_CQ;
317 aq->op = NIX_AQ_INSTOP_WRITE;
320 aq->cq_mask.ena = ~(aq->cq_mask.ena);
322 rc = otx2_mbox_process(mbox);
324 otx2_err("Failed to disable cq context");
332 nix_get_data_off(struct otx2_eth_dev *dev)
334 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
338 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
340 struct rte_mbuf mb_def;
343 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
344 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
345 offsetof(struct rte_mbuf, data_off) != 2);
346 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
347 offsetof(struct rte_mbuf, data_off) != 4);
348 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
349 offsetof(struct rte_mbuf, data_off) != 6);
351 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
352 mb_def.port = port_id;
353 rte_mbuf_refcnt_set(&mb_def, 1);
355 /* Prevent compiler reordering: rearm_data covers previous fields */
356 rte_compiler_barrier();
357 tmp = (uint64_t *)&mb_def.rearm_data;
363 otx2_nix_rx_queue_release(void *rx_queue)
365 struct otx2_eth_rxq *rxq = rx_queue;
370 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
371 nix_cq_rq_uninit(rxq->eth_dev, rxq);
376 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
377 uint16_t nb_desc, unsigned int socket,
378 const struct rte_eth_rxconf *rx_conf,
379 struct rte_mempool *mp)
381 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
382 struct rte_mempool_ops *ops;
383 struct otx2_eth_rxq *rxq;
384 const char *platform_ops;
385 enum nix_q_size_e qsize;
391 /* Compile time check to make sure all fast path elements in a CL */
392 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
395 if (rx_conf->rx_deferred_start == 1) {
396 otx2_err("Deferred Rx start is not supported");
400 platform_ops = rte_mbuf_platform_mempool_ops();
401 /* This driver needs octeontx2_npa mempool ops to work */
402 ops = rte_mempool_get_ops(mp->ops_index);
403 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
404 otx2_err("mempool ops should be of octeontx2_npa type");
408 if (mp->pool_id == 0) {
409 otx2_err("Invalid pool_id");
413 /* Free memory prior to re-allocation if needed */
414 if (eth_dev->data->rx_queues[rq] != NULL) {
415 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
416 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
417 eth_dev->data->rx_queues[rq] = NULL;
420 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
421 dev->rx_offloads |= offloads;
423 /* Find the CQ queue size */
424 qsize = nix_qsize_clampup_get(dev, nb_desc);
425 /* Allocate rxq memory */
426 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
428 otx2_err("Failed to allocate rq=%d", rq);
433 rxq->eth_dev = eth_dev;
435 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
436 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
437 rxq->wdata = (uint64_t)rq << 32;
438 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
439 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
440 eth_dev->data->port_id);
441 rxq->offloads = offloads;
443 rxq->qlen = nix_qsize_to_val(qsize);
445 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
446 rxq->tstamp = &dev->tstamp;
448 /* Alloc completion queue */
449 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
451 otx2_err("Failed to allocate rxq=%u", rq);
455 rxq->qconf.socket_id = socket;
456 rxq->qconf.nb_desc = nb_desc;
457 rxq->qconf.mempool = mp;
458 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
460 nix_rx_queue_reset(rxq);
461 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
462 rq, mp->name, qsize, nb_desc, rxq->qlen);
464 eth_dev->data->rx_queues[rq] = rxq;
465 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
469 otx2_nix_rx_queue_release(rxq);
474 static inline uint8_t
475 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
478 * Maximum three segments can be supported with W8, Choose
479 * NIX_MAXSQESZ_W16 for multi segment offload.
481 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
482 return NIX_MAXSQESZ_W16;
484 return NIX_MAXSQESZ_W8;
488 nix_sq_init(struct otx2_eth_txq *txq)
490 struct otx2_eth_dev *dev = txq->dev;
491 struct otx2_mbox *mbox = dev->mbox;
492 struct nix_aq_enq_req *sq;
497 if (txq->sqb_pool->pool_id == 0)
500 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
502 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
506 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
508 sq->ctype = NIX_AQ_CTYPE_SQ;
509 sq->op = NIX_AQ_INSTOP_INIT;
510 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
513 sq->sq.smq_rr_quantum = rr_quantum;
514 sq->sq.default_chan = dev->tx_chan_base;
515 sq->sq.sqe_stype = NIX_STYPE_STF;
517 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
518 sq->sq.sqe_stype = NIX_STYPE_STP;
520 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
521 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
522 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
523 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
524 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
526 /* Many to one reduction */
527 sq->sq.qint_idx = txq->sq % dev->qints;
529 return otx2_mbox_process(mbox);
533 nix_sq_uninit(struct otx2_eth_txq *txq)
535 struct otx2_eth_dev *dev = txq->dev;
536 struct otx2_mbox *mbox = dev->mbox;
537 struct ndc_sync_op *ndc_req;
538 struct nix_aq_enq_rsp *rsp;
539 struct nix_aq_enq_req *aq;
540 uint16_t sqes_per_sqb;
544 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
546 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
548 aq->ctype = NIX_AQ_CTYPE_SQ;
549 aq->op = NIX_AQ_INSTOP_READ;
551 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
555 /* Check if sq is already cleaned up */
560 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
562 aq->ctype = NIX_AQ_CTYPE_SQ;
563 aq->op = NIX_AQ_INSTOP_WRITE;
565 aq->sq_mask.ena = ~aq->sq_mask.ena;
568 rc = otx2_mbox_process(mbox);
572 /* Read SQ and free sqb's */
573 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
575 aq->ctype = NIX_AQ_CTYPE_SQ;
576 aq->op = NIX_AQ_INSTOP_READ;
578 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
583 otx2_err("SQ has pending sqe's");
585 count = aq->sq.sqb_count;
586 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
587 /* Free SQB's that are used */
588 sqb_buf = (void *)rsp->sq.head_sqb;
592 next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
593 nix_sq_max_sqe_sz(txq)));
594 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
600 /* Free next to use sqb */
601 if (rsp->sq.next_sqb)
602 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
605 /* Sync NDC-NIX-TX for LF */
606 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
607 ndc_req->nix_lf_tx_sync = 1;
608 rc = otx2_mbox_process(mbox);
610 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
616 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
618 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
619 struct npa_aq_enq_req *aura_req;
621 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
622 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
623 aura_req->ctype = NPA_AQ_CTYPE_AURA;
624 aura_req->op = NPA_AQ_INSTOP_WRITE;
626 aura_req->aura.limit = nb_sqb_bufs;
627 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
629 return otx2_mbox_process(npa_lf->mbox);
633 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
635 struct otx2_eth_dev *dev = txq->dev;
636 uint16_t sqes_per_sqb, nb_sqb_bufs;
637 char name[RTE_MEMPOOL_NAMESIZE];
638 struct rte_mempool_objsz sz;
639 struct npa_aura_s *aura;
640 uint32_t tmp, blk_sz;
642 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
643 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
644 blk_sz = dev->sqb_size;
646 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
647 sqes_per_sqb = (dev->sqb_size / 8) / 16;
649 sqes_per_sqb = (dev->sqb_size / 8) / 8;
651 nb_sqb_bufs = nb_desc / sqes_per_sqb;
652 /* Clamp up to devarg passed SQB count */
653 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
654 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
656 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
658 MEMPOOL_F_NO_SPREAD);
659 txq->nb_sqb_bufs = nb_sqb_bufs;
660 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
661 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
662 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
663 txq->nb_sqb_bufs_adj =
664 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
666 if (txq->sqb_pool == NULL) {
667 otx2_err("Failed to allocate sqe mempool");
671 memset(aura, 0, sizeof(*aura));
673 aura->fc_addr = txq->fc_iova;
674 aura->fc_hyst_bits = 0; /* Store count on all updates */
675 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
676 otx2_err("Failed to set ops for sqe mempool");
679 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
680 otx2_err("Failed to populate sqe mempool");
684 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
685 if (dev->sqb_size != sz.elt_size) {
686 otx2_err("sqe pool block size is not expected %d != %d",
691 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
699 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
701 struct nix_send_ext_s *send_hdr_ext;
702 struct nix_send_hdr_s *send_hdr;
703 struct nix_send_mem_s *send_mem;
704 union nix_send_sg_s *sg;
706 /* Initialize the fields based on basic single segment packet */
707 memset(&txq->cmd, 0, sizeof(txq->cmd));
709 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
710 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
711 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
712 send_hdr->w0.sizem1 = 2;
714 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
715 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
716 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
717 /* Default: one seg packet would have:
718 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
721 send_hdr->w0.sizem1 = 3;
722 send_hdr_ext->w0.tstmp = 1;
724 /* To calculate the offset for send_mem,
725 * send_hdr->w0.sizem1 * 2
727 send_mem = (struct nix_send_mem_s *)(txq->cmd +
728 (send_hdr->w0.sizem1 << 1));
729 send_mem->subdc = NIX_SUBDC_MEM;
731 send_mem->wmem = 0x1;
732 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
733 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
735 sg = (union nix_send_sg_s *)&txq->cmd[4];
737 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
738 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
739 send_hdr->w0.sizem1 = 1;
740 sg = (union nix_send_sg_s *)&txq->cmd[2];
743 send_hdr->w0.sq = txq->sq;
744 sg->subdc = NIX_SUBDC_SG;
746 sg->ld_type = NIX_SENDLDTYPE_LDD;
752 otx2_nix_tx_queue_release(void *_txq)
754 struct otx2_eth_txq *txq = _txq;
755 struct rte_eth_dev *eth_dev;
760 eth_dev = txq->dev->eth_dev;
762 otx2_nix_dbg("Releasing txq %u", txq->sq);
764 /* Flush and disable tm */
765 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
767 /* Free sqb's and disable sq */
771 rte_mempool_free(txq->sqb_pool);
772 txq->sqb_pool = NULL;
779 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
780 uint16_t nb_desc, unsigned int socket_id,
781 const struct rte_eth_txconf *tx_conf)
783 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
784 const struct rte_memzone *fc;
785 struct otx2_eth_txq *txq;
791 /* Compile time check to make sure all fast path elements in a CL */
792 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
794 if (tx_conf->tx_deferred_start) {
795 otx2_err("Tx deferred start is not supported");
799 /* Free memory prior to re-allocation if needed. */
800 if (eth_dev->data->tx_queues[sq] != NULL) {
801 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
802 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
803 eth_dev->data->tx_queues[sq] = NULL;
806 /* Find the expected offloads for this queue */
807 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
809 /* Allocating tx queue data structure */
810 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
811 OTX2_ALIGN, socket_id);
813 otx2_err("Failed to alloc txq=%d", sq);
819 txq->sqb_pool = NULL;
820 txq->offloads = offloads;
821 dev->tx_offloads |= offloads;
824 * Allocate memory for flow control updates from HW.
825 * Alloc one cache line, so that fits all FC_STYPE modes.
827 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
828 OTX2_ALIGN + sizeof(struct npa_aura_s),
829 OTX2_ALIGN, dev->node);
831 otx2_err("Failed to allocate mem for fcmem");
835 txq->fc_iova = fc->iova;
836 txq->fc_mem = fc->addr;
838 /* Initialize the aura sqb pool */
839 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
841 otx2_err("Failed to alloc sqe pool rc=%d", rc);
845 /* Initialize the SQ */
846 rc = nix_sq_init(txq);
848 otx2_err("Failed to init sq=%d context", sq);
852 txq->fc_cache_pkts = 0;
853 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
854 /* Evenly distribute LMT slot for each sq */
855 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
857 txq->qconf.socket_id = socket_id;
858 txq->qconf.nb_desc = nb_desc;
859 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
861 otx2_nix_form_default_desc(txq);
863 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
864 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
865 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
866 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
867 eth_dev->data->tx_queues[sq] = txq;
868 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
872 otx2_nix_tx_queue_release(txq);
878 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
880 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
881 struct otx2_eth_qconf *tx_qconf = NULL;
882 struct otx2_eth_qconf *rx_qconf = NULL;
883 struct otx2_eth_txq **txq;
884 struct otx2_eth_rxq **rxq;
885 int i, nb_rxq, nb_txq;
887 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
888 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
890 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
891 if (tx_qconf == NULL) {
892 otx2_err("Failed to allocate memory for tx_qconf");
896 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
897 if (rx_qconf == NULL) {
898 otx2_err("Failed to allocate memory for rx_qconf");
902 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
903 for (i = 0; i < nb_txq; i++) {
904 if (txq[i] == NULL) {
905 otx2_err("txq[%d] is already released", i);
908 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
909 otx2_nix_tx_queue_release(txq[i]);
910 eth_dev->data->tx_queues[i] = NULL;
913 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
914 for (i = 0; i < nb_rxq; i++) {
915 if (rxq[i] == NULL) {
916 otx2_err("rxq[%d] is already released", i);
919 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
920 otx2_nix_rx_queue_release(rxq[i]);
921 eth_dev->data->rx_queues[i] = NULL;
924 dev->tx_qconf = tx_qconf;
925 dev->rx_qconf = rx_qconf;
938 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
940 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
941 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
942 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
943 struct otx2_eth_txq **txq;
944 struct otx2_eth_rxq **rxq;
945 int rc, i, nb_rxq, nb_txq;
947 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
948 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
951 /* Setup tx & rx queues with previous configuration so
952 * that the queues can be functional in cases like ports
953 * are started without re configuring queues.
955 * Usual re config sequence is like below:
961 * queue_configure() {
968 * In some application's control path, queue_configure() would
969 * NOT be invoked for TXQs/RXQs in port_configure().
970 * In such cases, queues can be functional after start as the
971 * queues are already setup in port_configure().
973 for (i = 0; i < nb_txq; i++) {
974 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
975 tx_qconf[i].socket_id,
976 &tx_qconf[i].conf.tx);
978 otx2_err("Failed to setup tx queue rc=%d", rc);
979 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
980 for (i -= 1; i >= 0; i--)
981 otx2_nix_tx_queue_release(txq[i]);
986 free(tx_qconf); tx_qconf = NULL;
988 for (i = 0; i < nb_rxq; i++) {
989 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
990 rx_qconf[i].socket_id,
991 &rx_qconf[i].conf.rx,
992 rx_qconf[i].mempool);
994 otx2_err("Failed to setup rx queue rc=%d", rc);
995 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
996 for (i -= 1; i >= 0; i--)
997 otx2_nix_rx_queue_release(rxq[i]);
998 goto release_tx_queues;
1002 free(rx_qconf); rx_qconf = NULL;
1007 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1008 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1009 otx2_nix_tx_queue_release(txq[i]);
1020 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1022 RTE_SET_USED(queue);
1023 RTE_SET_USED(mbufs);
1030 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1032 /* These dummy functions are required for supporting
1033 * some applications which reconfigure queues without
1034 * stopping tx burst and rx burst threads(eg kni app)
1035 * When the queues context is saved, txq/rxqs are released
1036 * which caused app crash since rx/tx burst is still
1037 * on different lcores
1039 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1040 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1045 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1047 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1048 struct rte_eth_dev_data *data = eth_dev->data;
1049 struct rte_eth_conf *conf = &data->dev_conf;
1050 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1051 struct rte_eth_txmode *txmode = &conf->txmode;
1052 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1053 struct rte_ether_addr *ea;
1054 uint8_t nb_rxq, nb_txq;
1060 if (rte_eal_has_hugepages() == 0) {
1061 otx2_err("Huge page is not configured");
1065 if (rte_eal_iova_mode() != RTE_IOVA_VA) {
1066 otx2_err("iova mode should be va");
1070 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1071 otx2_err("Setting link speed/duplex not supported");
1075 if (conf->dcb_capability_en == 1) {
1076 otx2_err("dcb enable is not supported");
1080 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1081 otx2_err("Flow director is not supported");
1085 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1086 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1087 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1091 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1092 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1096 /* Free the resources allocated from the previous configure */
1097 if (dev->configured == 1) {
1098 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1099 otx2_nix_vlan_fini(eth_dev);
1100 oxt2_nix_unregister_queue_irqs(eth_dev);
1101 nix_set_nop_rxtx_function(eth_dev);
1102 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1105 otx2_nix_tm_fini(eth_dev);
1109 if (otx2_dev_is_A0(dev) &&
1110 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1111 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1112 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1113 otx2_err("Outer IP and SCTP checksum unsupported");
1118 dev->rx_offloads = rxmode->offloads;
1119 dev->tx_offloads = txmode->offloads;
1120 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1122 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1123 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1125 /* Alloc a nix lf */
1126 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1128 otx2_err("Failed to init nix_lf rc=%d", rc);
1133 rc = otx2_nix_rss_config(eth_dev);
1135 otx2_err("Failed to configure rss rc=%d", rc);
1139 /* Init the default TM scheduler hierarchy */
1140 rc = otx2_nix_tm_init_default(eth_dev);
1142 otx2_err("Failed to init traffic manager rc=%d", rc);
1146 rc = otx2_nix_vlan_offload_init(eth_dev);
1148 otx2_err("Failed to init vlan offload rc=%d", rc);
1152 /* Register queue IRQs */
1153 rc = oxt2_nix_register_queue_irqs(eth_dev);
1155 otx2_err("Failed to register queue interrupts rc=%d", rc);
1159 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1161 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1165 /* Enable PTP if it was requested by the app or if it is already
1166 * enabled in PF owning this VF
1168 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1169 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1170 otx2_ethdev_is_ptp_en(dev))
1171 otx2_nix_timesync_enable(eth_dev);
1173 otx2_nix_timesync_disable(eth_dev);
1176 * Restore queue config when reconfigure followed by
1177 * reconfigure and no queue configure invoked from application case.
1179 if (dev->configured == 1) {
1180 rc = nix_restore_queue_cfg(eth_dev);
1185 /* Update the mac address */
1186 ea = eth_dev->data->mac_addrs;
1187 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1188 if (rte_is_zero_ether_addr(ea))
1189 rte_eth_random_addr((uint8_t *)ea);
1191 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1193 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1194 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1195 " rx_flags=0x%x tx_flags=0x%x",
1196 eth_dev->data->port_id, ea_fmt, nb_rxq,
1197 nb_txq, dev->rx_offloads, dev->tx_offloads,
1198 dev->rx_offload_flags, dev->tx_offload_flags);
1201 dev->configured = 1;
1202 dev->configured_nb_rx_qs = data->nb_rx_queues;
1203 dev->configured_nb_tx_qs = data->nb_tx_queues;
1207 rc = nix_lf_free(dev);
1213 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1215 struct rte_eth_dev_data *data = eth_dev->data;
1216 struct otx2_eth_txq *txq;
1219 txq = eth_dev->data->tx_queues[qidx];
1221 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1224 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1226 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1231 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1238 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1240 struct rte_eth_dev_data *data = eth_dev->data;
1241 struct otx2_eth_txq *txq;
1244 txq = eth_dev->data->tx_queues[qidx];
1246 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1249 txq->fc_cache_pkts = 0;
1251 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1253 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1258 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1265 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1267 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1268 struct rte_eth_dev_data *data = eth_dev->data;
1271 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1274 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1276 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1280 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1287 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1289 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1290 struct rte_eth_dev_data *data = eth_dev->data;
1293 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1296 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1298 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1302 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1308 /* Initialize and register driver with DPDK Application */
1309 static const struct eth_dev_ops otx2_eth_dev_ops = {
1310 .dev_infos_get = otx2_nix_info_get,
1311 .dev_configure = otx2_nix_configure,
1312 .link_update = otx2_nix_link_update,
1313 .tx_queue_setup = otx2_nix_tx_queue_setup,
1314 .tx_queue_release = otx2_nix_tx_queue_release,
1315 .rx_queue_setup = otx2_nix_rx_queue_setup,
1316 .rx_queue_release = otx2_nix_rx_queue_release,
1317 .tx_queue_start = otx2_nix_tx_queue_start,
1318 .tx_queue_stop = otx2_nix_tx_queue_stop,
1319 .rx_queue_start = otx2_nix_rx_queue_start,
1320 .rx_queue_stop = otx2_nix_rx_queue_stop,
1321 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1322 .stats_get = otx2_nix_dev_stats_get,
1323 .stats_reset = otx2_nix_dev_stats_reset,
1324 .get_reg = otx2_nix_dev_get_reg,
1325 .mac_addr_add = otx2_nix_mac_addr_add,
1326 .mac_addr_remove = otx2_nix_mac_addr_del,
1327 .mac_addr_set = otx2_nix_mac_addr_set,
1328 .promiscuous_enable = otx2_nix_promisc_enable,
1329 .promiscuous_disable = otx2_nix_promisc_disable,
1330 .allmulticast_enable = otx2_nix_allmulticast_enable,
1331 .allmulticast_disable = otx2_nix_allmulticast_disable,
1332 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
1333 .reta_update = otx2_nix_dev_reta_update,
1334 .reta_query = otx2_nix_dev_reta_query,
1335 .rss_hash_update = otx2_nix_rss_hash_update,
1336 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
1337 .xstats_get = otx2_nix_xstats_get,
1338 .xstats_get_names = otx2_nix_xstats_get_names,
1339 .xstats_reset = otx2_nix_xstats_reset,
1340 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
1341 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
1342 .rxq_info_get = otx2_nix_rxq_info_get,
1343 .txq_info_get = otx2_nix_txq_info_get,
1344 .rx_queue_count = otx2_nix_rx_queue_count,
1345 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
1346 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
1347 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
1348 .pool_ops_supported = otx2_nix_pool_ops_supported,
1349 .filter_ctrl = otx2_nix_dev_filter_ctrl,
1350 .get_module_info = otx2_nix_get_module_info,
1351 .get_module_eeprom = otx2_nix_get_module_eeprom,
1352 .fw_version_get = otx2_nix_fw_version_get,
1353 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
1354 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
1355 .timesync_enable = otx2_nix_timesync_enable,
1356 .timesync_disable = otx2_nix_timesync_disable,
1357 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
1358 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
1359 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
1360 .timesync_read_time = otx2_nix_timesync_read_time,
1361 .timesync_write_time = otx2_nix_timesync_write_time,
1362 .vlan_offload_set = otx2_nix_vlan_offload_set,
1363 .vlan_filter_set = otx2_nix_vlan_filter_set,
1364 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
1365 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
1366 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
1370 nix_lf_attach(struct otx2_eth_dev *dev)
1372 struct otx2_mbox *mbox = dev->mbox;
1373 struct rsrc_attach_req *req;
1375 /* Attach NIX(lf) */
1376 req = otx2_mbox_alloc_msg_attach_resources(mbox);
1380 return otx2_mbox_process(mbox);
1384 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
1386 struct otx2_mbox *mbox = dev->mbox;
1387 struct msix_offset_rsp *msix_rsp;
1390 /* Get NPA and NIX MSIX vector offsets */
1391 otx2_mbox_alloc_msg_msix_offset(mbox);
1393 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
1395 dev->nix_msixoff = msix_rsp->nix_msixoff;
1401 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
1403 struct rsrc_detach_req *req;
1405 req = otx2_mbox_alloc_msg_detach_resources(mbox);
1407 /* Detach all except npa lf */
1408 req->partial = true;
1415 return otx2_mbox_process(mbox);
1419 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
1421 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1422 struct rte_pci_device *pci_dev;
1423 int rc, max_entries;
1425 eth_dev->dev_ops = &otx2_eth_dev_ops;
1427 /* For secondary processes, the primary has done all the work */
1428 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1429 /* Setup callbacks for secondary process */
1430 otx2_eth_set_tx_function(eth_dev);
1431 otx2_eth_set_rx_function(eth_dev);
1435 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1437 rte_eth_copy_pci_info(eth_dev, pci_dev);
1438 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1440 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
1441 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
1442 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
1444 /* Parse devargs string */
1445 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1447 otx2_err("Failed to parse devargs rc=%d", rc);
1451 if (!dev->mbox_active) {
1452 /* Initialize the base otx2_dev object
1453 * only if already present
1455 rc = otx2_dev_init(pci_dev, dev);
1457 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1461 /* Device generic callbacks */
1462 dev->ops = &otx2_dev_ops;
1463 dev->eth_dev = eth_dev;
1465 /* Grab the NPA LF if required */
1466 rc = otx2_npa_lf_init(pci_dev, dev);
1468 goto otx2_dev_uninit;
1470 dev->configured = 0;
1471 dev->drv_inited = true;
1472 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
1473 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1476 rc = nix_lf_attach(dev);
1478 goto otx2_npa_uninit;
1480 /* Get NIX MSIX offset */
1481 rc = nix_lf_get_msix_offset(dev);
1483 goto otx2_npa_uninit;
1485 /* Register LF irq handlers */
1486 rc = otx2_nix_register_irqs(eth_dev);
1490 /* Get maximum number of supported MAC entries */
1491 max_entries = otx2_cgx_mac_max_entries_get(dev);
1492 if (max_entries < 0) {
1493 otx2_err("Failed to get max entries for mac addr");
1495 goto unregister_irq;
1498 /* For VFs, returned max_entries will be 0. But to keep default MAC
1499 * address, one entry must be allocated. So setting up to 1.
1501 if (max_entries == 0)
1504 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
1505 RTE_ETHER_ADDR_LEN, 0);
1506 if (eth_dev->data->mac_addrs == NULL) {
1507 otx2_err("Failed to allocate memory for mac addr");
1509 goto unregister_irq;
1512 dev->max_mac_entries = max_entries;
1514 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
1516 goto free_mac_addrs;
1518 /* Update the mac address */
1519 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1521 /* Also sync same MAC address to CGX table */
1522 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
1524 /* Initialize the tm data structures */
1525 otx2_nix_tm_conf_init(eth_dev);
1527 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1528 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1530 if (otx2_dev_is_A0(dev)) {
1531 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
1532 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
1535 /* Initialize rte-flow */
1536 rc = otx2_flow_init(dev);
1538 goto free_mac_addrs;
1540 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
1541 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1542 eth_dev->data->port_id, dev->pf, dev->vf,
1543 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
1544 dev->rx_offload_capa, dev->tx_offload_capa);
1548 rte_free(eth_dev->data->mac_addrs);
1550 otx2_nix_unregister_irqs(eth_dev);
1552 otx2_eth_dev_lf_detach(dev->mbox);
1556 otx2_dev_fini(pci_dev, dev);
1558 otx2_err("Failed to init nix eth_dev rc=%d", rc);
1563 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
1565 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1566 struct rte_pci_device *pci_dev;
1569 /* Nothing to be done for secondary processes */
1570 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1573 /* Disable nix bpid config */
1574 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1576 /* Disable vlan offloads */
1577 otx2_nix_vlan_fini(eth_dev);
1579 /* Disable other rte_flow entries */
1580 otx2_flow_fini(dev);
1582 /* Disable PTP if already enabled */
1583 if (otx2_ethdev_is_ptp_en(dev))
1584 otx2_nix_timesync_disable(eth_dev);
1587 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1588 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
1589 eth_dev->data->tx_queues[i] = NULL;
1591 eth_dev->data->nb_tx_queues = 0;
1593 /* Free up RQ's and CQ's */
1594 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1595 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
1596 eth_dev->data->rx_queues[i] = NULL;
1598 eth_dev->data->nb_rx_queues = 0;
1600 /* Free tm resources */
1601 rc = otx2_nix_tm_fini(eth_dev);
1603 otx2_err("Failed to cleanup tm, rc=%d", rc);
1605 /* Unregister queue irqs */
1606 oxt2_nix_unregister_queue_irqs(eth_dev);
1608 rc = nix_lf_free(dev);
1610 otx2_err("Failed to free nix lf, rc=%d", rc);
1612 rc = otx2_npa_lf_fini();
1614 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
1616 rte_free(eth_dev->data->mac_addrs);
1617 eth_dev->data->mac_addrs = NULL;
1618 dev->drv_inited = false;
1620 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1621 otx2_nix_unregister_irqs(eth_dev);
1623 rc = otx2_eth_dev_lf_detach(dev->mbox);
1625 otx2_err("Failed to detach resources, rc=%d", rc);
1627 /* Check if mbox close is needed */
1631 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
1632 /* Will be freed later by PMD */
1633 eth_dev->data->dev_private = NULL;
1637 otx2_dev_fini(pci_dev, dev);
1642 nix_remove(struct rte_pci_device *pci_dev)
1644 struct rte_eth_dev *eth_dev;
1645 struct otx2_idev_cfg *idev;
1646 struct otx2_dev *otx2_dev;
1649 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1651 /* Cleanup eth dev */
1652 rc = otx2_eth_dev_uninit(eth_dev, true);
1656 rte_eth_dev_pci_release(eth_dev);
1659 /* Nothing to be done for secondary processes */
1660 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1663 /* Check for common resources */
1664 idev = otx2_intra_dev_get_cfg();
1665 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
1668 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
1670 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
1673 /* Safe to cleanup mbox as no more users */
1674 otx2_dev_fini(pci_dev, otx2_dev);
1679 otx2_info("%s: common resource in use by other devices", pci_dev->name);
1684 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1688 RTE_SET_USED(pci_drv);
1690 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
1693 /* On error on secondary, recheck if port exists in primary or
1694 * in mid of detach state.
1696 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1697 if (!rte_eth_dev_allocated(pci_dev->device.name))
1702 static const struct rte_pci_id pci_nix_map[] = {
1704 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
1707 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
1710 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1711 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
1718 static struct rte_pci_driver pci_nix = {
1719 .id_table = pci_nix_map,
1720 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
1721 RTE_PCI_DRV_INTR_LSC,
1723 .remove = nix_remove,
1726 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
1727 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
1728 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");