drivers/net/pfe/pfe_hal.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018-2019 NXP
   3  */
   4
   5 #include <arpa/inet.h>
   6
   7 #include "pfe_logs.h"
   8 #include "pfe_mod.h"
   9
  10 #define PFE_MTU_RESET_MASK      0xC000FFFF
  11
  12 void *cbus_base_addr;
  13 void *ddr_base_addr;
  14 unsigned long ddr_phys_base_addr;
  15 unsigned int ddr_size;
  16 static struct pe_info pe[MAX_PE];
  17
  18 /* Initializes the PFE library.
  19  * Must be called before using any of the library functions.
  20  *
  21  * @param[in] cbus_base         CBUS virtual base address (as mapped in
  22  * the host CPU address space)
  23  * @param[in] ddr_base          PFE DDR range virtual base address (as
  24  * mapped in the host CPU address space)
  25  * @param[in] ddr_phys_base     PFE DDR range physical base address (as
  26  * mapped in platform)
  27  * @param[in] size              PFE DDR range size (as defined by the host
  28  * software)
  29  */
  30 void
  31 pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,
  32                   unsigned int size)
  33 {
  34         cbus_base_addr = cbus_base;
  35         ddr_base_addr = ddr_base;
  36         ddr_phys_base_addr = ddr_phys_base;
  37         ddr_size = size;
  38
  39         pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0);
  40         pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0);
  41         pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE;
  42         pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
  43         pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
  44         pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
  45
  46         pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1);
  47         pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1);
  48         pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE;
  49         pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
  50         pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
  51         pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
  52
  53         pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2);
  54         pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2);
  55         pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE;
  56         pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
  57         pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
  58         pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
  59
  60         pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3);
  61         pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3);
  62         pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE;
  63         pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
  64         pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
  65         pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
  66
  67         pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4);
  68         pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4);
  69         pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE;
  70         pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
  71         pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
  72         pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
  73
  74         pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5);
  75         pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5);
  76         pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE;
  77         pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
  78         pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
  79         pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
  80
  81         pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0);
  82         pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0);
  83         pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE;
  84         pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
  85         pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
  86         pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
  87
  88         pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1);
  89         pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1);
  90         pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE;
  91         pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
  92         pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
  93         pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
  94
  95         pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3);
  96         pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3);
  97         pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE;
  98         pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
  99         pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
 100         pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
 101
 102 #if !defined(CONFIG_FSL_PFE_UTIL_DISABLED)
 103         pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR;
 104         pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA;
 105         pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR;
 106         pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA;
 107 #endif
 108 }
 109
 110 /**************************** MTIP GEMAC ***************************/
 111
 112 /* Enable Rx Checksum Engine. With this enabled, Frame with bad IP,
 113  *   TCP or UDP checksums are discarded
 114  *
 115  * @param[in] base      GEMAC base address.
 116  */
 117 void
 118 gemac_enable_rx_checksum_offload(__rte_unused void *base)
 119 {
 120         /*Do not find configuration to do this */
 121 }
 122
 123 /* Disable Rx Checksum Engine.
 124  *
 125  * @param[in] base      GEMAC base address.
 126  */
 127 void
 128 gemac_disable_rx_checksum_offload(__rte_unused void *base)
 129 {
 130         /*Do not find configuration to do this */
 131 }
 132
 133 /* GEMAC set speed.
 134  * @param[in] base      GEMAC base address
 135  * @param[in] speed     GEMAC speed (10, 100 or 1000 Mbps)
 136  */
 137 void
 138 gemac_set_speed(void *base, enum mac_speed gem_speed)
 139 {
 140         u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
 141         u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
 142
 143         switch (gem_speed) {
 144         case SPEED_10M:
 145                         rcr |= EMAC_RCNTRL_RMII_10T;
 146                         break;
 147
 148         case SPEED_1000M:
 149                         ecr |= EMAC_ECNTRL_SPEED;
 150                         break;
 151
 152         case SPEED_100M:
 153         default:
 154                         /*It is in 100M mode */
 155                         break;
 156         }
 157         writel(ecr, (base + EMAC_ECNTRL_REG));
 158         writel(rcr, (base + EMAC_RCNTRL_REG));
 159 }
 160
 161 /* GEMAC set duplex.
 162  * @param[in] base      GEMAC base address
 163  * @param[in] duplex    GEMAC duplex mode (Full, Half)
 164  */
 165 void
 166 gemac_set_duplex(void *base, int duplex)
 167 {
 168         if (duplex == DUPLEX_HALF) {
 169                 writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base
 170                         + EMAC_TCNTRL_REG);
 171                 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base
 172                         + EMAC_RCNTRL_REG));
 173         } else {
 174                 writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base
 175                         + EMAC_TCNTRL_REG);
 176                 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base
 177                         + EMAC_RCNTRL_REG));
 178         }
 179 }
 180
 181 /* GEMAC set mode.
 182  * @param[in] base      GEMAC base address
 183  * @param[in] mode      GEMAC operation mode (MII, RMII, RGMII, SGMII)
 184  */
 185 void
 186 gemac_set_mode(void *base, __rte_unused int mode)
 187 {
 188         u32 val = readl(base + EMAC_RCNTRL_REG);
 189
 190         /*Remove loopbank*/
 191         val &= ~EMAC_RCNTRL_LOOP;
 192
 193         /*Enable flow control and MII mode*/
 194         val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE | EMAC_RCNTRL_CRC_FWD);
 195
 196         writel(val, base + EMAC_RCNTRL_REG);
 197 }
 198
 199 /* GEMAC enable function.
 200  * @param[in] base      GEMAC base address
 201  */
 202 void
 203 gemac_enable(void *base)
 204 {
 205         writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base +
 206                 EMAC_ECNTRL_REG);
 207 }
 208
 209 /* GEMAC disable function.
 210  * @param[in] base      GEMAC base address
 211  */
 212 void
 213 gemac_disable(void *base)
 214 {
 215         writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base +
 216                 EMAC_ECNTRL_REG);
 217 }
 218
 219 /* GEMAC TX disable function.
 220  * @param[in] base      GEMAC base address
 221  */
 222 void
 223 gemac_tx_disable(void *base)
 224 {
 225         writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base +
 226                 EMAC_TCNTRL_REG);
 227 }
 228
 229 void
 230 gemac_tx_enable(void *base)
 231 {
 232         writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base +
 233                         EMAC_TCNTRL_REG);
 234 }
 235
 236 /* Sets the hash register of the MAC.
 237  * This register is used for matching unicast and multicast frames.
 238  *
 239  * @param[in] base      GEMAC base address.
 240  * @param[in] hash      64-bit hash to be configured.
 241  */
 242 void
 243 gemac_set_hash(void *base, struct pfe_mac_addr *hash)
 244 {
 245         writel(hash->bottom,  base + EMAC_GALR);
 246         writel(hash->top, base + EMAC_GAUR);
 247 }
 248
 249 void
 250 gemac_set_laddrN(void *base, struct pfe_mac_addr *address,
 251                       unsigned int entry_index)
 252 {
 253         if (entry_index < 1 || entry_index > EMAC_SPEC_ADDR_MAX)
 254                 return;
 255
 256         entry_index = entry_index - 1;
 257         if (entry_index < 1) {
 258                 writel(htonl(address->bottom),  base + EMAC_PHY_ADDR_LOW);
 259                 writel((htonl(address->top) | 0x8808), base +
 260                         EMAC_PHY_ADDR_HIGH);
 261         } else {
 262                 writel(htonl(address->bottom),  base + ((entry_index - 1) * 8)
 263                         + EMAC_SMAC_0_0);
 264                 writel((htonl(address->top) | 0x8808), base + ((entry_index -
 265                         1) * 8) + EMAC_SMAC_0_1);
 266         }
 267 }
 268
 269 void
 270 gemac_clear_laddrN(void *base, unsigned int entry_index)
 271 {
 272         if (entry_index < 1 || entry_index > EMAC_SPEC_ADDR_MAX)
 273                 return;
 274
 275         entry_index = entry_index - 1;
 276         if (entry_index < 1) {
 277                 writel(0, base + EMAC_PHY_ADDR_LOW);
 278                 writel(0, base + EMAC_PHY_ADDR_HIGH);
 279         } else {
 280                 writel(0,  base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0);
 281                 writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1);
 282         }
 283 }
 284
 285 /* Set the loopback mode of the MAC.  This can be either no loopback for
 286  * normal operation, local loopback through MAC internal loopback module or PHY
 287  *   loopback for external loopback through a PHY.  This asserts the external
 288  * loop pin.
 289  *
 290  * @param[in] base      GEMAC base address.
 291  * @param[in] gem_loop  Loopback mode to be enabled. LB_LOCAL - MAC
 292  * Loopback,
 293  *                      LB_EXT - PHY Loopback.
 294  */
 295 void
 296 gemac_set_loop(void *base, __rte_unused enum mac_loop gem_loop)
 297 {
 298         pr_info("%s()\n", __func__);
 299         writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base +
 300                 EMAC_RCNTRL_REG));
 301 }
 302
 303 /* GEMAC allow frames
 304  * @param[in] base      GEMAC base address
 305  */
 306 void
 307 gemac_enable_copy_all(void *base)
 308 {
 309         writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base +
 310                 EMAC_RCNTRL_REG));
 311 }
 312
 313 /* GEMAC do not allow frames
 314  * @param[in] base      GEMAC base address
 315  */
 316 void
 317 gemac_disable_copy_all(void *base)
 318 {
 319         writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base +
 320                 EMAC_RCNTRL_REG));
 321 }
 322
 323 /* GEMAC allow broadcast function.
 324  * @param[in] base      GEMAC base address
 325  */
 326 void
 327 gemac_allow_broadcast(void *base)
 328 {
 329         writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base +
 330                 EMAC_RCNTRL_REG);
 331 }
 332
 333 /* GEMAC no broadcast function.
 334  * @param[in] base      GEMAC base address
 335  */
 336 void
 337 gemac_no_broadcast(void *base)
 338 {
 339         writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base +
 340                 EMAC_RCNTRL_REG);
 341 }
 342
 343 /* GEMAC enable 1536 rx function.
 344  * @param[in]   base    GEMAC base address
 345  */
 346 void
 347 gemac_enable_1536_rx(void *base)
 348 {
 349         /* Set 1536 as Maximum frame length */
 350         writel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK)
 351                         | (1536 << 16),
 352                         base + EMAC_RCNTRL_REG);
 353 }
 354
 355 /* GEMAC set Max rx function.
 356  * @param[in]   base    GEMAC base address
 357  */
 358 int
 359 gemac_set_rx(void *base, int mtu)
 360 {
 361         if (mtu < HIF_RX_PKT_MIN_SIZE || mtu > JUMBO_FRAME_SIZE) {
 362                 PFE_PMD_ERR("Invalid or not support MTU size");
 363                 return -1;
 364         }
 365
 366         if (pfe_svr == SVR_LS1012A_REV1 &&
 367             mtu > (MAX_MTU_ON_REV1 + PFE_ETH_OVERHEAD)) {
 368                 PFE_PMD_ERR("Max supported MTU on Rev1 is %d", MAX_MTU_ON_REV1);
 369                 return -1;
 370         }
 371
 372         writel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK)
 373                         | (mtu << 16),
 374                         base + EMAC_RCNTRL_REG);
 375         return 0;
 376 }
 377
 378 /* GEMAC enable jumbo function.
 379  * @param[in]   base    GEMAC base address
 380  */
 381 void
 382 gemac_enable_rx_jmb(void *base)
 383 {
 384         if (pfe_svr == SVR_LS1012A_REV1) {
 385                 PFE_PMD_ERR("Jumbo not supported on Rev1");
 386                 return;
 387         }
 388
 389         writel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK) |
 390                         (JUMBO_FRAME_SIZE << 16), base + EMAC_RCNTRL_REG);
 391 }
 392
 393 /* GEMAC enable stacked vlan function.
 394  * @param[in]   base    GEMAC base address
 395  */
 396 void
 397 gemac_enable_stacked_vlan(__rte_unused void *base)
 398 {
 399         /* MTIP doesn't support stacked vlan */
 400 }
 401
 402 /* GEMAC enable pause rx function.
 403  * @param[in] base      GEMAC base address
 404  */
 405 void
 406 gemac_enable_pause_rx(void *base)
 407 {
 408         writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE,
 409                base + EMAC_RCNTRL_REG);
 410 }
 411
 412 /* GEMAC disable pause rx function.
 413  * @param[in] base      GEMAC base address
 414  */
 415 void
 416 gemac_disable_pause_rx(void *base)
 417 {
 418         writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE,
 419                base + EMAC_RCNTRL_REG);
 420 }
 421
 422 /* GEMAC enable pause tx function.
 423  * @param[in] base GEMAC base address
 424  */
 425 void
 426 gemac_enable_pause_tx(void *base)
 427 {
 428         writel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY);
 429 }
 430
 431 /* GEMAC disable pause tx function.
 432  * @param[in] base GEMAC base address
 433  */
 434 void
 435 gemac_disable_pause_tx(void *base)
 436 {
 437         writel(0x0, base + EMAC_RX_SECTION_EMPTY);
 438 }
 439
 440 /* GEMAC wol configuration
 441  * @param[in] base      GEMAC base address
 442  * @param[in] wol_conf  WoL register configuration
 443  */
 444 void
 445 gemac_set_wol(void *base, u32 wol_conf)
 446 {
 447         u32  val = readl(base + EMAC_ECNTRL_REG);
 448
 449         if (wol_conf)
 450                 val |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);
 451         else
 452                 val &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);
 453         writel(val, base + EMAC_ECNTRL_REG);
 454 }
 455
 456 /* Sets Gemac bus width to 64bit
 457  * @param[in] base       GEMAC base address
 458  * @param[in] width     gemac bus width to be set possible values are 32/64/128
 459  */
 460 void
 461 gemac_set_bus_width(__rte_unused void *base, __rte_unused int width)
 462 {
 463 }
 464
 465 /* Sets Gemac configuration.
 466  * @param[in] base      GEMAC base address
 467  * @param[in] cfg       GEMAC configuration
 468  */
 469 void
 470 gemac_set_config(void *base, struct gemac_cfg *cfg)
 471 {
 472         /*GEMAC config taken from VLSI */
 473         writel(0x00000004, base + EMAC_TFWR_STR_FWD);
 474         writel(0x00000005, base + EMAC_RX_SECTION_FULL);
 475
 476         if (pfe_svr == SVR_LS1012A_REV1)
 477                 writel(0x00000768, base + EMAC_TRUNC_FL);
 478         else
 479                 writel(0x00003fff, base + EMAC_TRUNC_FL);
 480
 481         writel(0x00000030, base + EMAC_TX_SECTION_EMPTY);
 482         writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG);
 483
 484         gemac_set_mode(base, cfg->mode);
 485
 486         gemac_set_speed(base, cfg->speed);
 487
 488         gemac_set_duplex(base, cfg->duplex);
 489 }
 490
 491 /**************************** GPI ***************************/
 492
 493 /* Initializes a GPI block.
 494  * @param[in] base      GPI base address
 495  * @param[in] cfg       GPI configuration
 496  */
 497 void
 498 gpi_init(void *base, struct gpi_cfg *cfg)
 499 {
 500         gpi_reset(base);
 501
 502         gpi_disable(base);
 503
 504         gpi_set_config(base, cfg);
 505 }
 506
 507 /* Resets a GPI block.
 508  * @param[in] base      GPI base address
 509  */
 510 void
 511 gpi_reset(void *base)
 512 {
 513         writel(CORE_SW_RESET, base + GPI_CTRL);
 514 }
 515
 516 /* Enables a GPI block.
 517  * @param[in] base      GPI base address
 518  */
 519 void
 520 gpi_enable(void *base)
 521 {
 522         writel(CORE_ENABLE, base + GPI_CTRL);
 523 }
 524
 525 /* Disables a GPI block.
 526  * @param[in] base      GPI base address
 527  */
 528 void
 529 gpi_disable(void *base)
 530 {
 531         writel(CORE_DISABLE, base + GPI_CTRL);
 532 }
 533
 534 /* Sets the configuration of a GPI block.
 535  * @param[in] base      GPI base address
 536  * @param[in] cfg       GPI configuration
 537  */
 538 void
 539 gpi_set_config(void *base, struct gpi_cfg *cfg)
 540 {
 541         writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL),       base
 542                 + GPI_LMEM_ALLOC_ADDR);
 543         writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL),        base
 544                 + GPI_LMEM_FREE_ADDR);
 545         writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL),       base
 546                 + GPI_DDR_ALLOC_ADDR);
 547         writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),        base
 548                 + GPI_DDR_FREE_ADDR);
 549         writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
 550         writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
 551         writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
 552         writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
 553         writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
 554         writel((DDR_HDR_SIZE << 16) |   LMEM_HDR_SIZE,  base + GPI_HDR_SIZE);
 555         writel((DDR_BUF_SIZE << 16) |   LMEM_BUF_SIZE,  base + GPI_BUF_SIZE);
 556
 557         writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |
 558                 GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
 559         writel(cfg->tmlf_txthres, base + GPI_TMLF_TX);
 560         writel(cfg->aseq_len,   base + GPI_DTX_ASEQ);
 561         writel(1, base + GPI_TOE_CHKSUM_EN);
 562
 563         if (cfg->mtip_pause_reg) {
 564                 writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG);
 565                 writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME);
 566         }
 567 }
 568
 569 /**************************** HIF ***************************/
 570 /* Initializes HIF copy block.
 571  *
 572  */
 573 void
 574 hif_init(void)
 575 {
 576         /*Initialize HIF registers*/
 577         writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE,
 578                HIF_POLL_CTRL);
 579 }
 580
 581 /* Enable hif tx DMA and interrupt
 582  *
 583  */
 584 void
 585 hif_tx_enable(void)
 586 {
 587         writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);
 588         writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN),
 589                HIF_INT_ENABLE);
 590 }
 591
 592 /* Disable hif tx DMA and interrupt
 593  *
 594  */
 595 void
 596 hif_tx_disable(void)
 597 {
 598         u32     hif_int;
 599
 600         writel(0, HIF_TX_CTRL);
 601
 602         hif_int = readl(HIF_INT_ENABLE);
 603         hif_int &= HIF_TXPKT_INT_EN;
 604         writel(hif_int, HIF_INT_ENABLE);
 605 }
 606
 607 /* Enable hif rx DMA and interrupt
 608  *
 609  */
 610 void
 611 hif_rx_enable(void)
 612 {
 613         hif_rx_dma_start();
 614         writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN),
 615                HIF_INT_ENABLE);
 616 }
 617
 618 /* Disable hif rx DMA and interrupt
 619  *
 620  */
 621 void
 622 hif_rx_disable(void)
 623 {
 624         u32     hif_int;
 625
 626         writel(0, HIF_RX_CTRL);
 627
 628         hif_int = readl(HIF_INT_ENABLE);
 629         hif_int &= HIF_RXPKT_INT_EN;
 630         writel(hif_int, HIF_INT_ENABLE);
 631 }