drivers/net/qede/base/bcm_osal.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include <rte_memzone.h>
   8 #include <rte_errno.h>
   9
  10 #include "bcm_osal.h"
  11 #include "ecore.h"
  12 #include "ecore_hw.h"
  13 #include "ecore_dev_api.h"
  14 #include "ecore_iov_api.h"
  15 #include "ecore_mcp_api.h"
  16 #include "ecore_l2_api.h"
  17
  18 /* Array of memzone pointers */
  19 static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE];
  20 /* Counter to track current memzone allocated */
  21 static uint16_t ecore_mz_count;
  22
  23 unsigned long qede_log2_align(unsigned long n)
  24 {
  25         unsigned long ret = n ? 1 : 0;
  26         unsigned long _n = n >> 1;
  27
  28         while (_n) {
  29                 _n >>= 1;
  30                 ret <<= 1;
  31         }
  32
  33         if (ret < n)
  34                 ret <<= 1;
  35
  36         return ret;
  37 }
  38
  39 u32 qede_osal_log2(u32 val)
  40 {
  41         u32 log = 0;
  42
  43         while (val >>= 1)
  44                 log++;
  45
  46         return log;
  47 }
  48
  49 inline void qede_set_bit(u32 nr, unsigned long *addr)
  50 {
  51         __sync_fetch_and_or(addr, (1UL << nr));
  52 }
  53
  54 inline void qede_clr_bit(u32 nr, unsigned long *addr)
  55 {
  56         __sync_fetch_and_and(addr, ~(1UL << nr));
  57 }
  58
  59 inline bool qede_test_bit(u32 nr, unsigned long *addr)
  60 {
  61         bool res;
  62
  63         rte_mb();
  64         res = ((*addr) & (1UL << nr)) != 0;
  65         rte_mb();
  66         return res;
  67 }
  68
  69 static inline u32 qede_ffb(unsigned long word)
  70 {
  71         unsigned long first_bit;
  72
  73         first_bit = __builtin_ffsl(word);
  74         return first_bit ? (first_bit - 1) : OSAL_BITS_PER_UL;
  75 }
  76
  77 inline u32 qede_find_first_bit(unsigned long *addr, u32 limit)
  78 {
  79         u32 i;
  80         u32 nwords = 0;
  81         OSAL_BUILD_BUG_ON(!limit);
  82         nwords = (limit - 1) / OSAL_BITS_PER_UL + 1;
  83         for (i = 0; i < nwords; i++)
  84                 if (addr[i] != 0)
  85                         break;
  86
  87         return (i == nwords) ? limit : i * OSAL_BITS_PER_UL + qede_ffb(addr[i]);
  88 }
  89
  90 static inline u32 qede_ffz(unsigned long word)
  91 {
  92         unsigned long first_zero;
  93
  94         first_zero = __builtin_ffsl(~word);
  95         return first_zero ? (first_zero - 1) : OSAL_BITS_PER_UL;
  96 }
  97
  98 inline u32 qede_find_first_zero_bit(unsigned long *addr, u32 limit)
  99 {
 100         u32 i;
 101         u32 nwords = 0;
 102         OSAL_BUILD_BUG_ON(!limit);
 103         nwords = (limit - 1) / OSAL_BITS_PER_UL + 1;
 104         for (i = 0; i < nwords && ~(addr[i]) == 0; i++);
 105         return (i == nwords) ? limit : i * OSAL_BITS_PER_UL + qede_ffz(addr[i]);
 106 }
 107
 108 void qede_vf_fill_driver_data(struct ecore_hwfn *hwfn,
 109                               __rte_unused struct vf_pf_resc_request *resc_req,
 110                               struct ecore_vf_acquire_sw_info *vf_sw_info)
 111 {
 112         vf_sw_info->os_type = VFPF_ACQUIRE_OS_LINUX_USERSPACE;
 113         vf_sw_info->override_fw_version = 1;
 114 }
 115
 116 void *osal_dma_alloc_coherent(struct ecore_dev *p_dev,
 117                               dma_addr_t *phys, size_t size)
 118 {
 119         const struct rte_memzone *mz;
 120         char mz_name[RTE_MEMZONE_NAMESIZE];
 121         uint32_t core_id = rte_lcore_id();
 122         unsigned int socket_id;
 123
 124         if (ecore_mz_count >= RTE_MAX_MEMZONE) {
 125                 DP_ERR(p_dev, "Memzone allocation count exceeds %u\n",
 126                        RTE_MAX_MEMZONE);
 127                 *phys = 0;
 128                 return OSAL_NULL;
 129         }
 130
 131         OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
 132         snprintf(mz_name, sizeof(mz_name), "%lx",
 133                                         (unsigned long)rte_get_timer_cycles());
 134         if (core_id == (unsigned int)LCORE_ID_ANY)
 135                 core_id = rte_get_master_lcore();
 136         socket_id = rte_lcore_to_socket_id(core_id);
 137         mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
 138                         RTE_MEMZONE_IOVA_CONTIG, RTE_CACHE_LINE_SIZE);
 139         if (!mz) {
 140                 DP_ERR(p_dev, "Unable to allocate DMA memory "
 141                        "of size %zu bytes - %s\n",
 142                        size, rte_strerror(rte_errno));
 143                 *phys = 0;
 144                 return OSAL_NULL;
 145         }
 146         *phys = mz->iova;
 147         ecore_mz_mapping[ecore_mz_count++] = mz;
 148         DP_VERBOSE(p_dev, ECORE_MSG_SP,
 149                    "Allocated dma memory size=%zu phys=0x%lx"
 150                    " virt=%p core=%d\n",
 151                    mz->len, (unsigned long)mz->iova, mz->addr, core_id);
 152         return mz->addr;
 153 }
 154
 155 void *osal_dma_alloc_coherent_aligned(struct ecore_dev *p_dev,
 156                                       dma_addr_t *phys, size_t size, int align)
 157 {
 158         const struct rte_memzone *mz;
 159         char mz_name[RTE_MEMZONE_NAMESIZE];
 160         uint32_t core_id = rte_lcore_id();
 161         unsigned int socket_id;
 162
 163         if (ecore_mz_count >= RTE_MAX_MEMZONE) {
 164                 DP_ERR(p_dev, "Memzone allocation count exceeds %u\n",
 165                        RTE_MAX_MEMZONE);
 166                 *phys = 0;
 167                 return OSAL_NULL;
 168         }
 169
 170         OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
 171         snprintf(mz_name, sizeof(mz_name), "%lx",
 172                                         (unsigned long)rte_get_timer_cycles());
 173         if (core_id == (unsigned int)LCORE_ID_ANY)
 174                 core_id = rte_get_master_lcore();
 175         socket_id = rte_lcore_to_socket_id(core_id);
 176         mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
 177                         RTE_MEMZONE_IOVA_CONTIG, align);
 178         if (!mz) {
 179                 DP_ERR(p_dev, "Unable to allocate DMA memory "
 180                        "of size %zu bytes - %s\n",
 181                        size, rte_strerror(rte_errno));
 182                 *phys = 0;
 183                 return OSAL_NULL;
 184         }
 185         *phys = mz->iova;
 186         ecore_mz_mapping[ecore_mz_count++] = mz;
 187         DP_VERBOSE(p_dev, ECORE_MSG_SP,
 188                    "Allocated aligned dma memory size=%zu phys=0x%lx"
 189                    " virt=%p core=%d\n",
 190                    mz->len, (unsigned long)mz->iova, mz->addr, core_id);
 191         return mz->addr;
 192 }
 193
 194 void osal_dma_free_mem(struct ecore_dev *p_dev, dma_addr_t phys)
 195 {
 196         uint16_t j;
 197
 198         for (j = 0 ; j < ecore_mz_count; j++) {
 199                 if (phys == ecore_mz_mapping[j]->iova) {
 200                         DP_VERBOSE(p_dev, ECORE_MSG_SP,
 201                                 "Free memzone %s\n", ecore_mz_mapping[j]->name);
 202                         rte_memzone_free(ecore_mz_mapping[j]);
 203                         while (j < ecore_mz_count - 1) {
 204                                 ecore_mz_mapping[j] = ecore_mz_mapping[j + 1];
 205                                 j++;
 206                         }
 207                         ecore_mz_count--;
 208                         return;
 209                 }
 210         }
 211
 212         DP_ERR(p_dev, "Unexpected memory free request\n");
 213 }
 214
 215 #ifdef CONFIG_ECORE_ZIPPED_FW
 216 u32 qede_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len,
 217                     u8 *input_buf, u32 max_size, u8 *unzip_buf)
 218 {
 219         int rc;
 220
 221         p_hwfn->stream->next_in = input_buf;
 222         p_hwfn->stream->avail_in = input_len;
 223         p_hwfn->stream->next_out = unzip_buf;
 224         p_hwfn->stream->avail_out = max_size;
 225
 226         rc = inflateInit2(p_hwfn->stream, MAX_WBITS);
 227
 228         if (rc != Z_OK) {
 229                 DP_ERR(p_hwfn,
 230                            "zlib init failed, rc = %d\n", rc);
 231                 return 0;
 232         }
 233
 234         rc = inflate(p_hwfn->stream, Z_FINISH);
 235         inflateEnd(p_hwfn->stream);
 236
 237         if (rc != Z_OK && rc != Z_STREAM_END) {
 238                 DP_ERR(p_hwfn,
 239                            "FW unzip error: %s, rc=%d\n", p_hwfn->stream->msg,
 240                            rc);
 241                 return 0;
 242         }
 243
 244         return p_hwfn->stream->total_out / 4;
 245 }
 246 #endif
 247
 248 void
 249 qede_get_mcp_proto_stats(struct ecore_dev *edev,
 250                          enum ecore_mcp_protocol_type type,
 251                          union ecore_mcp_protocol_stats *stats)
 252 {
 253         struct ecore_eth_stats lan_stats;
 254
 255         if (type == ECORE_MCP_LAN_STATS) {
 256                 ecore_get_vport_stats(edev, &lan_stats);
 257
 258                 /* @DPDK */
 259                 stats->lan_stats.ucast_rx_pkts = lan_stats.common.rx_ucast_pkts;
 260                 stats->lan_stats.ucast_tx_pkts = lan_stats.common.tx_ucast_pkts;
 261
 262                 stats->lan_stats.fcs_err = -1;
 263         } else {
 264                 DP_INFO(edev, "Statistics request type %d not supported\n",
 265                        type);
 266         }
 267 }
 268
 269 void
 270 qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)
 271 {
 272         char err_str[64];
 273
 274         switch (err_type) {
 275         case ECORE_HW_ERR_FAN_FAIL:
 276                 strcpy(err_str, "Fan Failure");
 277                 break;
 278         case ECORE_HW_ERR_MFW_RESP_FAIL:
 279                 strcpy(err_str, "MFW Response Failure");
 280                 break;
 281         case ECORE_HW_ERR_HW_ATTN:
 282                 strcpy(err_str, "HW Attention");
 283                 break;
 284         case ECORE_HW_ERR_DMAE_FAIL:
 285                 strcpy(err_str, "DMAE Failure");
 286                 break;
 287         case ECORE_HW_ERR_RAMROD_FAIL:
 288                 strcpy(err_str, "Ramrod Failure");
 289                 break;
 290         case ECORE_HW_ERR_FW_ASSERT:
 291                 strcpy(err_str, "FW Assertion");
 292                 break;
 293         default:
 294                 strcpy(err_str, "Unknown");
 295         }
 296
 297         DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str);
 298         ecore_int_attn_clr_enable(p_hwfn->p_dev, true);
 299 }
 300
 301 u32 qede_crc32(u32 crc, u8 *ptr, u32 length)
 302 {
 303         int i;
 304
 305         while (length--) {
 306                 crc ^= *ptr++;
 307                 for (i = 0; i < 8; i++)
 308                         crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
 309         }
 310         return crc;
 311 }