drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #undef CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define MAX_HWFNS_PER_DEVICE    2
  32 #define NAME_SIZE 128 /* @DPDK */
  33 #define ECORE_WFQ_UNIT  100
  34 #include "../qede_logs.h" /* @DPDK */
  35
  36 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  37 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  38 /* Constants */
  39 #define ECORE_WID_SIZE          (1024)
  40
  41 /* Configurable */
  42 #define ECORE_PF_DEMS_SIZE      (4)
  43
  44 /* cau states */
  45 enum ecore_coalescing_mode {
  46         ECORE_COAL_MODE_DISABLE,
  47         ECORE_COAL_MODE_ENABLE
  48 };
  49
  50 enum ecore_nvm_cmd {
  51         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  52         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  53         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  54         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  55         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  56         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  57         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  58         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  59         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  60         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  61         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  62 };
  63
  64 #ifndef LINUX_REMOVE
  65 #if !defined(CONFIG_ECORE_L2)
  66 #define CONFIG_ECORE_L2
  67 #define CONFIG_ECORE_SRIOV
  68 #endif
  69 #endif
  70
  71 /* helpers */
  72 #ifndef __EXTRACT__LINUX__
  73 #define MASK_FIELD(_name, _value)                                       \
  74                 ((_value) &= (_name##_MASK))
  75
  76 #define FIELD_VALUE(_name, _value)                                      \
  77                 ((_value & _name##_MASK) << _name##_SHIFT)
  78
  79 #define SET_FIELD(value, name, flag)                                    \
  80 do {                                                                    \
  81         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  82         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
  83 } while (0)
  84
  85 #define GET_FIELD(value, name)                                          \
  86         (((value) >> (name##_SHIFT)) & name##_MASK)
  87 #endif
  88
  89 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
  90 {
  91         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
  92                       (cid * ECORE_PF_DEMS_SIZE);
  93
  94         return db_addr;
  95 }
  96
  97 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
  98 {
  99         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 100                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 101
 102         return db_addr;
 103 }
 104
 105 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 106         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 107          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 108
 109 #ifndef LINUX_REMOVE
 110 #ifndef U64_HI
 111 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 112 #endif
 113
 114 #ifndef U64_LO
 115 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 116 #endif
 117 #endif
 118
 119 #ifndef __EXTRACT__LINUX__
 120 enum DP_LEVEL {
 121         ECORE_LEVEL_VERBOSE     = 0x0,
 122         ECORE_LEVEL_INFO        = 0x1,
 123         ECORE_LEVEL_NOTICE      = 0x2,
 124         ECORE_LEVEL_ERR         = 0x3,
 125 };
 126
 127 #define ECORE_LOG_LEVEL_SHIFT   (30)
 128 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 129 #define ECORE_LOG_INFO_MASK     (0x40000000)
 130 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 131
 132 enum DP_MODULE {
 133 #ifndef LINUX_REMOVE
 134         ECORE_MSG_DRV           = 0x0001,
 135         ECORE_MSG_PROBE         = 0x0002,
 136         ECORE_MSG_LINK          = 0x0004,
 137         ECORE_MSG_TIMER         = 0x0008,
 138         ECORE_MSG_IFDOWN        = 0x0010,
 139         ECORE_MSG_IFUP          = 0x0020,
 140         ECORE_MSG_RX_ERR        = 0x0040,
 141         ECORE_MSG_TX_ERR        = 0x0080,
 142         ECORE_MSG_TX_QUEUED     = 0x0100,
 143         ECORE_MSG_INTR          = 0x0200,
 144         ECORE_MSG_TX_DONE       = 0x0400,
 145         ECORE_MSG_RX_STATUS     = 0x0800,
 146         ECORE_MSG_PKTDATA       = 0x1000,
 147         ECORE_MSG_HW            = 0x2000,
 148         ECORE_MSG_WOL           = 0x4000,
 149 #endif
 150         ECORE_MSG_SPQ           = 0x10000,
 151         ECORE_MSG_STATS         = 0x20000,
 152         ECORE_MSG_DCB           = 0x40000,
 153         ECORE_MSG_IOV           = 0x80000,
 154         ECORE_MSG_SP            = 0x100000,
 155         ECORE_MSG_STORAGE       = 0x200000,
 156         ECORE_MSG_OOO           = 0x200000,
 157         ECORE_MSG_CXT           = 0x800000,
 158         ECORE_MSG_LL2           = 0x1000000,
 159         ECORE_MSG_ILT           = 0x2000000,
 160         ECORE_MSG_RDMA          = 0x4000000,
 161         ECORE_MSG_DEBUG         = 0x8000000,
 162         /* to be added...up to 0x8000000 */
 163 };
 164 #endif
 165
 166 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 167
 168 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 169         (val == (cond1) ? true1 : \
 170          (val == (cond2) ? true2 : def))
 171
 172 /* forward */
 173 struct ecore_ptt_pool;
 174 struct ecore_spq;
 175 struct ecore_sb_info;
 176 struct ecore_sb_attn_info;
 177 struct ecore_cxt_mngr;
 178 struct ecore_dma_mem;
 179 struct ecore_sb_sp_info;
 180 struct ecore_ll2_info;
 181 struct ecore_igu_info;
 182 struct ecore_mcp_info;
 183 struct ecore_dcbx_info;
 184
 185 struct ecore_rt_data {
 186         u32     *init_val;
 187         bool    *b_valid;
 188 };
 189
 190 enum ecore_tunn_mode {
 191         ECORE_MODE_L2GENEVE_TUNN,
 192         ECORE_MODE_IPGENEVE_TUNN,
 193         ECORE_MODE_L2GRE_TUNN,
 194         ECORE_MODE_IPGRE_TUNN,
 195         ECORE_MODE_VXLAN_TUNN,
 196 };
 197
 198 enum ecore_tunn_clss {
 199         ECORE_TUNN_CLSS_MAC_VLAN,
 200         ECORE_TUNN_CLSS_MAC_VNI,
 201         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 202         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 203         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 204         MAX_ECORE_TUNN_CLSS,
 205 };
 206
 207 struct ecore_tunn_update_type {
 208         bool b_update_mode;
 209         bool b_mode_enabled;
 210         enum ecore_tunn_clss tun_cls;
 211 };
 212
 213 struct ecore_tunn_update_udp_port {
 214         bool b_update_port;
 215         u16 port;
 216 };
 217
 218 struct ecore_tunnel_info {
 219         struct ecore_tunn_update_type vxlan;
 220         struct ecore_tunn_update_type l2_geneve;
 221         struct ecore_tunn_update_type ip_geneve;
 222         struct ecore_tunn_update_type l2_gre;
 223         struct ecore_tunn_update_type ip_gre;
 224
 225         struct ecore_tunn_update_udp_port vxlan_port;
 226         struct ecore_tunn_update_udp_port geneve_port;
 227
 228         bool b_update_rx_cls;
 229         bool b_update_tx_cls;
 230 };
 231
 232 /* The PCI personality is not quite synonymous to protocol ID:
 233  * 1. All personalities need CORE connections
 234  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 235  */
 236 enum ecore_pci_personality {
 237         ECORE_PCI_ETH,
 238         ECORE_PCI_FCOE,
 239         ECORE_PCI_ISCSI,
 240         ECORE_PCI_ETH_ROCE,
 241         ECORE_PCI_ETH_IWARP,
 242         ECORE_PCI_ETH_RDMA,
 243         ECORE_PCI_DEFAULT /* default in shmem */
 244 };
 245
 246 /* All VFs are symmetric, all counters are PF + all VFs */
 247 struct ecore_qm_iids {
 248         u32 cids;
 249         u32 vf_cids;
 250         u32 tids;
 251 };
 252
 253 #define MAX_PF_PER_PORT 8
 254
 255 /* HW / FW resources, output of features supported below, most information
 256  * is received from MFW.
 257  */
 258 enum ecore_resources {
 259         ECORE_SB,
 260         ECORE_L2_QUEUE,
 261         ECORE_VPORT,
 262         ECORE_RSS_ENG,
 263         ECORE_PQ,
 264         ECORE_RL,
 265         ECORE_MAC,
 266         ECORE_VLAN,
 267         ECORE_RDMA_CNQ_RAM,
 268         ECORE_ILT,
 269         ECORE_LL2_QUEUE,
 270         ECORE_CMDQS_CQS,
 271         ECORE_RDMA_STATS_QUEUE,
 272         ECORE_MAX_RESC,                 /* must be last */
 273 };
 274
 275 /* Features that require resources, given as input to the resource management
 276  * algorithm, the output are the resources above
 277  */
 278 enum ecore_feature {
 279         ECORE_PF_L2_QUE,
 280         ECORE_PF_TC,
 281         ECORE_VF,
 282         ECORE_EXTRA_VF_QUE,
 283         ECORE_VMQ,
 284         ECORE_RDMA_CNQ,
 285         ECORE_ISCSI_CQ,
 286         ECORE_FCOE_CQ,
 287         ECORE_VF_L2_QUE,
 288         ECORE_MAX_FEATURES,
 289 };
 290
 291 enum ecore_port_mode {
 292         ECORE_PORT_MODE_DE_2X40G,
 293         ECORE_PORT_MODE_DE_2X50G,
 294         ECORE_PORT_MODE_DE_1X100G,
 295         ECORE_PORT_MODE_DE_4X10G_F,
 296         ECORE_PORT_MODE_DE_4X10G_E,
 297         ECORE_PORT_MODE_DE_4X20G,
 298         ECORE_PORT_MODE_DE_1X40G,
 299         ECORE_PORT_MODE_DE_2X25G,
 300         ECORE_PORT_MODE_DE_1X25G,
 301         ECORE_PORT_MODE_DE_4X25G,
 302         ECORE_PORT_MODE_DE_2X10G,
 303 };
 304
 305 enum ecore_dev_cap {
 306         ECORE_DEV_CAP_ETH,
 307         ECORE_DEV_CAP_FCOE,
 308         ECORE_DEV_CAP_ISCSI,
 309         ECORE_DEV_CAP_ROCE,
 310         ECORE_DEV_CAP_IWARP
 311 };
 312
 313 #ifndef __EXTRACT__LINUX__
 314 enum ecore_hw_err_type {
 315         ECORE_HW_ERR_FAN_FAIL,
 316         ECORE_HW_ERR_MFW_RESP_FAIL,
 317         ECORE_HW_ERR_HW_ATTN,
 318         ECORE_HW_ERR_DMAE_FAIL,
 319         ECORE_HW_ERR_RAMROD_FAIL,
 320         ECORE_HW_ERR_FW_ASSERT,
 321 };
 322 #endif
 323
 324 struct ecore_hw_info {
 325         /* PCI personality */
 326         enum ecore_pci_personality personality;
 327 #define ECORE_IS_RDMA_PERSONALITY(dev)                      \
 328         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE ||  \
 329          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 330          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 331 #define ECORE_IS_ROCE_PERSONALITY(dev)                     \
 332         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 333          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 334 #define ECORE_IS_IWARP_PERSONALITY(dev)                     \
 335         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 336          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 337 #define ECORE_IS_L2_PERSONALITY(dev)                  \
 338         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 339          ECORE_IS_RDMA_PERSONALITY(dev))
 340
 341         /* Resource Allocation scheme results */
 342         u32 resc_start[ECORE_MAX_RESC];
 343         u32 resc_num[ECORE_MAX_RESC];
 344         u32 feat_num[ECORE_MAX_FEATURES];
 345
 346         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 347         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 348         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 349                                          RESC_NUM(_p_hwfn, resc))
 350         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 351
 352         /* Amount of traffic classes HW supports */
 353         u8 num_hw_tc;
 354
 355 /* Amount of TCs which should be active according to DCBx or upper layer driver
 356  * configuration
 357  */
 358
 359         u8 num_active_tc;
 360
 361         /* The traffic class used by PF for it's offloaded protocol */
 362         u8 offload_tc;
 363
 364         u32 concrete_fid;
 365         u16 opaque_fid;
 366         u16 ovlan;
 367         u32 part_num[4];
 368
 369         unsigned char hw_mac_addr[ETH_ALEN];
 370         u64 node_wwn; /* For FCoE only */
 371         u64 port_wwn; /* For FCoE only */
 372
 373         u16 num_iscsi_conns;
 374         u16 num_fcoe_conns;
 375
 376         struct ecore_igu_info *p_igu_info;
 377         /* Sriov */
 378         u8 max_chains_per_vf;
 379
 380         u32 port_mode;
 381         u32     hw_mode;
 382         unsigned long device_capabilities;
 383
 384         /* Default DCBX mode */
 385         u8 dcbx_mode;
 386
 387         u16 mtu;
 388 };
 389
 390 /* maximun size of read/write commands (HW limit) */
 391 #define DMAE_MAX_RW_SIZE        0x2000
 392
 393 struct ecore_dmae_info {
 394         /* Mutex for synchronizing access to functions */
 395         osal_mutex_t    mutex;
 396
 397         u8 channel;
 398
 399         dma_addr_t completion_word_phys_addr;
 400
 401         /* The memory location where the DMAE writes the completion
 402          * value when an operation is finished on this context.
 403          */
 404         u32 *p_completion_word;
 405
 406         dma_addr_t intermediate_buffer_phys_addr;
 407
 408         /* An intermediate buffer for DMAE operations that use virtual
 409          * addresses - data is DMA'd to/from this buffer and then
 410          * memcpy'd to/from the virtual address
 411          */
 412         u32 *p_intermediate_buffer;
 413
 414         dma_addr_t dmae_cmd_phys_addr;
 415         struct dmae_cmd *p_dmae_cmd;
 416 };
 417
 418 struct ecore_wfq_data {
 419         u32 default_min_speed; /* When wfq feature is not configured */
 420         u32 min_speed; /* when feature is configured for any 1 vport */
 421         bool configured;
 422 };
 423
 424 struct ecore_qm_info {
 425         struct init_qm_pq_params    *qm_pq_params;
 426         struct init_qm_vport_params *qm_vport_params;
 427         struct init_qm_port_params  *qm_port_params;
 428         u16                     start_pq;
 429         u8                      start_vport;
 430         u16                     pure_lb_pq;
 431         u16                     offload_pq;
 432         u16                     pure_ack_pq;
 433         u16                     ooo_pq;
 434         u16                     first_vf_pq;
 435         u16                     first_mcos_pq;
 436         u16                     first_rl_pq;
 437         u16                     num_pqs;
 438         u16                     num_vf_pqs;
 439         u8                      num_vports;
 440         u8                      max_phys_tcs_per_port;
 441         u8                      ooo_tc;
 442         bool                    pf_rl_en;
 443         bool                    pf_wfq_en;
 444         bool                    vport_rl_en;
 445         bool                    vport_wfq_en;
 446         u8                      pf_wfq;
 447         u32                     pf_rl;
 448         struct ecore_wfq_data   *wfq_data;
 449         u8                      num_pf_rls;
 450 };
 451
 452 struct storm_stats {
 453         u32 address;
 454         u32 len;
 455 };
 456
 457 struct ecore_fw_data {
 458 #ifdef CONFIG_ECORE_BINARY_FW
 459         struct fw_ver_info *fw_ver_info;
 460 #endif
 461         const u8 *modes_tree_buf;
 462         union init_op *init_ops;
 463         const u32 *arr_data;
 464         u32 init_ops_size;
 465 };
 466
 467 struct ecore_hwfn {
 468         struct ecore_dev                *p_dev;
 469         u8                              my_id;          /* ID inside the PF */
 470 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 471         u8                              rel_pf_id;      /* Relative to engine*/
 472         u8                              abs_pf_id;
 473         #define ECORE_PATH_ID(_p_hwfn) \
 474                 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 475         u8                              port_id;
 476         bool                            b_active;
 477
 478         u32                             dp_module;
 479         u8                              dp_level;
 480         char                            name[NAME_SIZE];
 481         void                            *dp_ctx;
 482
 483         bool                            first_on_engine;
 484         bool                            hw_init_done;
 485
 486         u8                              num_funcs_on_engine;
 487         u8                              enabled_func_idx;
 488
 489         /* BAR access */
 490         void OSAL_IOMEM                 *regview;
 491         void OSAL_IOMEM                 *doorbells;
 492         u64                             db_phys_addr;
 493         unsigned long                   db_size;
 494
 495         /* PTT pool */
 496         struct ecore_ptt_pool           *p_ptt_pool;
 497
 498         /* HW info */
 499         struct ecore_hw_info            hw_info;
 500
 501         /* rt_array (for init-tool) */
 502         struct ecore_rt_data            rt_data;
 503
 504         /* SPQ */
 505         struct ecore_spq                *p_spq;
 506
 507         /* EQ */
 508         struct ecore_eq                 *p_eq;
 509
 510         /* Consolidate Q*/
 511         struct ecore_consq              *p_consq;
 512
 513         /* Slow-Path definitions */
 514         osal_dpc_t                      sp_dpc;
 515         bool                            b_sp_dpc_enabled;
 516
 517         struct ecore_ptt                *p_main_ptt;
 518         struct ecore_ptt                *p_dpc_ptt;
 519
 520         struct ecore_sb_sp_info         *p_sp_sb;
 521         struct ecore_sb_attn_info       *p_sb_attn;
 522
 523         /* Protocol related */
 524         bool                            using_ll2;
 525         struct ecore_ll2_info           *p_ll2_info;
 526         struct ecore_ooo_info           *p_ooo_info;
 527         struct ecore_iscsi_info         *p_iscsi_info;
 528         struct ecore_fcoe_info          *p_fcoe_info;
 529         struct ecore_rdma_info          *p_rdma_info;
 530         struct ecore_pf_params          pf_params;
 531
 532         bool                            b_rdma_enabled_in_prs;
 533         u32                             rdma_prs_search_reg;
 534
 535         /* Array of sb_info of all status blocks */
 536         struct ecore_sb_info            *sbs_info[MAX_SB_PER_PF_MIMD];
 537         u16                             num_sbs;
 538
 539         struct ecore_cxt_mngr           *p_cxt_mngr;
 540
 541         /* Flag indicating whether interrupts are enabled or not*/
 542         bool                            b_int_enabled;
 543         bool                            b_int_requested;
 544
 545         /* True if the driver requests for the link */
 546         bool                            b_drv_link_init;
 547
 548         struct ecore_vf_iov             *vf_iov_info;
 549         struct ecore_pf_iov             *pf_iov_info;
 550         struct ecore_mcp_info           *mcp_info;
 551         struct ecore_dcbx_info          *p_dcbx_info;
 552
 553         struct ecore_dmae_info          dmae_info;
 554
 555         /* QM init */
 556         struct ecore_qm_info            qm_info;
 557
 558 #ifdef CONFIG_ECORE_ZIPPED_FW
 559         /* Buffer for unzipping firmware data */
 560         void *unzip_buf;
 561 #endif
 562
 563         struct dbg_tools_data           dbg_info;
 564
 565         struct z_stream_s               *stream;
 566
 567         /* PWM region specific data */
 568         u32                             dpi_size;
 569         u32                             dpi_count;
 570         u32                             dpi_start_offset; /* this is used to
 571                                                            * calculate th
 572                                                            * doorbell address
 573                                                            */
 574
 575         /* If one of the following is set then EDPM shouldn't be used */
 576         u8                              dcbx_no_edpm;
 577         u8                              db_bar_no_edpm;
 578 };
 579
 580 #ifndef __EXTRACT__LINUX__
 581 enum ecore_mf_mode {
 582         ECORE_MF_DEFAULT,
 583         ECORE_MF_OVLAN,
 584         ECORE_MF_NPAR,
 585 };
 586 #endif
 587
 588 /* @DPDK */
 589 struct ecore_dbg_feature {
 590         u8                              *dump_buf;
 591         u32                             buf_size;
 592         u32                             dumped_dwords;
 593 };
 594
 595 enum qed_dbg_features {
 596         DBG_FEATURE_BUS,
 597         DBG_FEATURE_GRC,
 598         DBG_FEATURE_IDLE_CHK,
 599         DBG_FEATURE_MCP_TRACE,
 600         DBG_FEATURE_REG_FIFO,
 601         DBG_FEATURE_PROTECTION_OVERRIDE,
 602         DBG_FEATURE_NUM
 603 };
 604
 605 struct ecore_dev {
 606         u32                             dp_module;
 607         u8                              dp_level;
 608         char                            name[NAME_SIZE];
 609         void                            *dp_ctx;
 610
 611         u8                              type;
 612 #define ECORE_DEV_TYPE_BB       (0 << 0)
 613 #define ECORE_DEV_TYPE_AH       (1 << 0)
 614 /* Translate type/revision combo into the proper conditions */
 615 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 616 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 617 #ifndef ASIC_ONLY
 618 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 619                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 620 #else
 621 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 622 #endif
 623 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 624 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 625
 626 #define ECORE_DEV_ID_MASK       0xff00
 627 #define ECORE_DEV_ID_MASK_BB    0x1600
 628 #define ECORE_DEV_ID_MASK_AH    0x8000
 629
 630         u16 vendor_id;
 631         u16 device_id;
 632
 633         u16                             chip_num;
 634         #define CHIP_NUM_MASK                   0xffff
 635         #define CHIP_NUM_SHIFT                  16
 636
 637         u16                             chip_rev;
 638         #define CHIP_REV_MASK                   0xf
 639         #define CHIP_REV_SHIFT                  12
 640 #ifndef ASIC_ONLY
 641         #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
 642         #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
 643         #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
 644         #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 645                                           CHIP_REV_IS_EMUL_B0(_p_dev))
 646         #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
 647         #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
 648         #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
 649                                           CHIP_REV_IS_FPGA_B0(_p_dev))
 650         #define CHIP_REV_IS_SLOW(_p_dev) \
 651                 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 652         #define CHIP_REV_IS_A0(_p_dev) \
 653                 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 654                  CHIP_REV_IS_FPGA_A0(_p_dev) || \
 655                  !(_p_dev)->chip_rev)
 656         #define CHIP_REV_IS_B0(_p_dev) \
 657                 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
 658                  CHIP_REV_IS_FPGA_B0(_p_dev) || \
 659                  (_p_dev)->chip_rev == 1)
 660         #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
 661 #else
 662         #define CHIP_REV_IS_A0(_p_dev)  (!(_p_dev)->chip_rev)
 663         #define CHIP_REV_IS_B0(_p_dev)  ((_p_dev)->chip_rev == 1)
 664 #endif
 665
 666         u16                             chip_metal;
 667         #define CHIP_METAL_MASK                 0xff
 668         #define CHIP_METAL_SHIFT                4
 669
 670         u16                             chip_bond_id;
 671         #define CHIP_BOND_ID_MASK               0xf
 672         #define CHIP_BOND_ID_SHIFT              0
 673
 674         u8                              num_engines;
 675         u8                              num_ports_in_engines;
 676         u8                              num_funcs_in_port;
 677
 678         u8                              path_id;
 679         enum ecore_mf_mode              mf_mode;
 680         #define IS_MF_DEFAULT(_p_hwfn)  \
 681                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 682         #define IS_MF_SI(_p_hwfn)       \
 683                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 684         #define IS_MF_SD(_p_hwfn)       \
 685                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 686
 687         int                             pcie_width;
 688         int                             pcie_speed;
 689
 690         /* Add MF related configuration */
 691         u8                              mcp_rev;
 692         u8                              boot_mode;
 693
 694         u8                              wol;
 695
 696         u32                             int_mode;
 697         enum ecore_coalescing_mode      int_coalescing_mode;
 698         u16                             rx_coalesce_usecs;
 699         u16                             tx_coalesce_usecs;
 700
 701         /* Start Bar offset of first hwfn */
 702         void OSAL_IOMEM                 *regview;
 703         void OSAL_IOMEM                 *doorbells;
 704         u64                             db_phys_addr;
 705         unsigned long                   db_size;
 706
 707         /* PCI */
 708         u8                              cache_shift;
 709
 710         /* Init */
 711         const struct iro                *iro_arr;
 712         #define IRO (p_hwfn->p_dev->iro_arr)
 713
 714         /* HW functions */
 715         u8                              num_hwfns;
 716         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 717
 718         /* SRIOV */
 719         struct ecore_hw_sriov_info      *p_iov_info;
 720 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 721         struct ecore_tunnel_info        tunnel;
 722         bool                            b_is_vf;
 723
 724         u32                             drv_type;
 725
 726         u32                             rdma_max_sge;
 727         u32                             rdma_max_inline;
 728         u32                             rdma_max_srq_sge;
 729
 730         struct ecore_eth_stats          *reset_stats;
 731         struct ecore_fw_data            *fw_data;
 732
 733         u32                             mcp_nvm_resp;
 734
 735         /* Recovery */
 736         bool                            recov_in_prog;
 737
 738 /* Indicates whether should prevent attentions from being reasserted */
 739
 740         bool                            attn_clr_en;
 741
 742         /* Indicates whether allowing the MFW to collect a crash dump */
 743         bool                            mdump_en;
 744
 745         /* Indicates if the reg_fifo is checked after any register access */
 746         bool                            chk_reg_fifo;
 747
 748 #ifndef ASIC_ONLY
 749         bool                            b_is_emul_full;
 750 #endif
 751
 752 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 753         void                            *firmware;
 754         u64                             fw_len;
 755 #endif
 756
 757         /* @DPDK */
 758         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 759         u8                              engine_for_debug;
 760 };
 761
 762 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 763                                                   : MAX_NUM_VFS_K2)
 764 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 765                                                   : MAX_NUM_L2_QUEUES_K2)
 766 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 767                                                   : MAX_NUM_PORTS_K2)
 768 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 769                                                   : MAX_SB_PER_PATH_K2)
 770 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 771                                                   : MAX_NUM_PFS_K2)
 772
 773 /**
 774  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 775  *        the concrete value.
 776  *
 777  * @param concrete_fid
 778  *
 779  * @return OSAL_INLINE u8
 780  */
 781 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
 782                                           u32 concrete_fid)
 783 {
 784         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 785         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 786         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 787         u8 sw_fid;
 788
 789         if (vf_valid)
 790                 sw_fid = vfid + MAX_NUM_PFS;
 791         else
 792                 sw_fid = pfid;
 793
 794         return sw_fid;
 795 }
 796
 797 #define PURE_LB_TC 8
 798 #define PKT_LB_TC 9
 799
 800 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 801 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 802                                            u32 min_pf_rate);
 803
 804 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 805 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 806 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 807 int ecore_device_num_engines(struct ecore_dev *p_dev);
 808 int ecore_device_num_ports(struct ecore_dev *p_dev);
 809 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 810                            u8 *mac);
 811
 812 /* Flags for indication of required queues */
 813 #define PQ_FLAGS_RLS    (1 << 0)
 814 #define PQ_FLAGS_MCOS   (1 << 1)
 815 #define PQ_FLAGS_LB     (1 << 2)
 816 #define PQ_FLAGS_OOO    (1 << 3)
 817 #define PQ_FLAGS_ACK    (1 << 4)
 818 #define PQ_FLAGS_OFLD   (1 << 5)
 819 #define PQ_FLAGS_VFS    (1 << 6)
 820
 821 /* physical queue index for cm context intialization */
 822 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 823 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 824 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 825 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
 826
 827 /* amount of resources used in qm init */
 828 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 829 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 830 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 831 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 832 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 833
 834 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 835
 836 #endif /* __ECORE_H */