drivers/net/qede/base/ecore.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef __ECORE_H
  10 #define __ECORE_H
  11
  12 /* @DPDK */
  13 #include <sys/stat.h>
  14 #include <fcntl.h>
  15 #include <unistd.h>
  16
  17 #define CONFIG_ECORE_BINARY_FW
  18 #undef CONFIG_ECORE_ZIPPED_FW
  19
  20 #ifdef CONFIG_ECORE_ZIPPED_FW
  21 #include <zlib.h>
  22 #endif
  23
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_hsi_debug_tools.h"
  26 #include "ecore_hsi_init_func.h"
  27 #include "ecore_hsi_init_tool.h"
  28 #include "ecore_proto_if.h"
  29 #include "mcp_public.h"
  30
  31 #define ECORE_MAJOR_VERSION             8
  32 #define ECORE_MINOR_VERSION             18
  33 #define ECORE_REVISION_VERSION          7
  34 #define ECORE_ENGINEERING_VERSION       0
  35
  36 #define ECORE_VERSION                                                   \
  37         ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) |    \
  38          (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
  39
  40 #define STORM_FW_VERSION                                                \
  41         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |  \
  42          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  43
  44 #define MAX_HWFNS_PER_DEVICE    2
  45 #define NAME_SIZE 128 /* @DPDK */
  46 #define ECORE_WFQ_UNIT  100
  47 #include "../qede_logs.h" /* @DPDK */
  48
  49 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  50 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  51 /* Constants */
  52 #define ECORE_WID_SIZE          (1024)
  53
  54 /* Configurable */
  55 #define ECORE_PF_DEMS_SIZE      (4)
  56
  57 /* cau states */
  58 enum ecore_coalescing_mode {
  59         ECORE_COAL_MODE_DISABLE,
  60         ECORE_COAL_MODE_ENABLE
  61 };
  62
  63 enum ecore_nvm_cmd {
  64         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  65         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  66         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  67         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  68         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  69         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  70         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  71         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  72         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  73         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  74         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  75 };
  76
  77 #ifndef LINUX_REMOVE
  78 #if !defined(CONFIG_ECORE_L2)
  79 #define CONFIG_ECORE_L2
  80 #define CONFIG_ECORE_SRIOV
  81 #endif
  82 #endif
  83
  84 /* helpers */
  85 #ifndef __EXTRACT__LINUX__
  86 #define MASK_FIELD(_name, _value)                                       \
  87                 ((_value) &= (_name##_MASK))
  88
  89 #define FIELD_VALUE(_name, _value)                                      \
  90                 ((_value & _name##_MASK) << _name##_SHIFT)
  91
  92 #define SET_FIELD(value, name, flag)                                    \
  93 do {                                                                    \
  94         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  95         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
  96 } while (0)
  97
  98 #define GET_FIELD(value, name)                                          \
  99         (((value) >> (name##_SHIFT)) & name##_MASK)
 100 #endif
 101
 102 #define ECORE_MFW_GET_FIELD(name, field)                                \
 103         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
 104
 105 #define ECORE_MFW_SET_FIELD(name, field, value)                         \
 106 do {                                                                    \
 107         (name) &= ~((field ## _MASK) << (field ## _SHIFT));             \
 108         (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));  \
 109 } while (0)
 110
 111 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 112 {
 113         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 114                       (cid * ECORE_PF_DEMS_SIZE);
 115
 116         return db_addr;
 117 }
 118
 119 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 120 {
 121         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 122                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 123
 124         return db_addr;
 125 }
 126
 127 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 128         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 129          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 130
 131 #ifndef LINUX_REMOVE
 132 #ifndef U64_HI
 133 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 134 #endif
 135
 136 #ifndef U64_LO
 137 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 138 #endif
 139 #endif
 140
 141 #ifndef __EXTRACT__LINUX__
 142 enum DP_LEVEL {
 143         ECORE_LEVEL_VERBOSE     = 0x0,
 144         ECORE_LEVEL_INFO        = 0x1,
 145         ECORE_LEVEL_NOTICE      = 0x2,
 146         ECORE_LEVEL_ERR         = 0x3,
 147 };
 148
 149 #define ECORE_LOG_LEVEL_SHIFT   (30)
 150 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 151 #define ECORE_LOG_INFO_MASK     (0x40000000)
 152 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 153
 154 enum DP_MODULE {
 155 #ifndef LINUX_REMOVE
 156         ECORE_MSG_DRV           = 0x0001,
 157         ECORE_MSG_PROBE         = 0x0002,
 158         ECORE_MSG_LINK          = 0x0004,
 159         ECORE_MSG_TIMER         = 0x0008,
 160         ECORE_MSG_IFDOWN        = 0x0010,
 161         ECORE_MSG_IFUP          = 0x0020,
 162         ECORE_MSG_RX_ERR        = 0x0040,
 163         ECORE_MSG_TX_ERR        = 0x0080,
 164         ECORE_MSG_TX_QUEUED     = 0x0100,
 165         ECORE_MSG_INTR          = 0x0200,
 166         ECORE_MSG_TX_DONE       = 0x0400,
 167         ECORE_MSG_RX_STATUS     = 0x0800,
 168         ECORE_MSG_PKTDATA       = 0x1000,
 169         ECORE_MSG_HW            = 0x2000,
 170         ECORE_MSG_WOL           = 0x4000,
 171 #endif
 172         ECORE_MSG_SPQ           = 0x10000,
 173         ECORE_MSG_STATS         = 0x20000,
 174         ECORE_MSG_DCB           = 0x40000,
 175         ECORE_MSG_IOV           = 0x80000,
 176         ECORE_MSG_SP            = 0x100000,
 177         ECORE_MSG_STORAGE       = 0x200000,
 178         ECORE_MSG_OOO           = 0x200000,
 179         ECORE_MSG_CXT           = 0x800000,
 180         ECORE_MSG_LL2           = 0x1000000,
 181         ECORE_MSG_ILT           = 0x2000000,
 182         ECORE_MSG_RDMA          = 0x4000000,
 183         ECORE_MSG_DEBUG         = 0x8000000,
 184         /* to be added...up to 0x8000000 */
 185 };
 186 #endif
 187
 188 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 189
 190 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 191         (val == (cond1) ? true1 : \
 192          (val == (cond2) ? true2 : def))
 193
 194 /* forward */
 195 struct ecore_ptt_pool;
 196 struct ecore_spq;
 197 struct ecore_sb_info;
 198 struct ecore_sb_attn_info;
 199 struct ecore_cxt_mngr;
 200 struct ecore_dma_mem;
 201 struct ecore_sb_sp_info;
 202 struct ecore_ll2_info;
 203 struct ecore_igu_info;
 204 struct ecore_mcp_info;
 205 struct ecore_dcbx_info;
 206
 207 struct ecore_rt_data {
 208         u32     *init_val;
 209         bool    *b_valid;
 210 };
 211
 212 enum ecore_tunn_mode {
 213         ECORE_MODE_L2GENEVE_TUNN,
 214         ECORE_MODE_IPGENEVE_TUNN,
 215         ECORE_MODE_L2GRE_TUNN,
 216         ECORE_MODE_IPGRE_TUNN,
 217         ECORE_MODE_VXLAN_TUNN,
 218 };
 219
 220 enum ecore_tunn_clss {
 221         ECORE_TUNN_CLSS_MAC_VLAN,
 222         ECORE_TUNN_CLSS_MAC_VNI,
 223         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 224         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 225         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 226         MAX_ECORE_TUNN_CLSS,
 227 };
 228
 229 struct ecore_tunn_update_type {
 230         bool b_update_mode;
 231         bool b_mode_enabled;
 232         enum ecore_tunn_clss tun_cls;
 233 };
 234
 235 struct ecore_tunn_update_udp_port {
 236         bool b_update_port;
 237         u16 port;
 238 };
 239
 240 struct ecore_tunnel_info {
 241         struct ecore_tunn_update_type vxlan;
 242         struct ecore_tunn_update_type l2_geneve;
 243         struct ecore_tunn_update_type ip_geneve;
 244         struct ecore_tunn_update_type l2_gre;
 245         struct ecore_tunn_update_type ip_gre;
 246
 247         struct ecore_tunn_update_udp_port vxlan_port;
 248         struct ecore_tunn_update_udp_port geneve_port;
 249
 250         bool b_update_rx_cls;
 251         bool b_update_tx_cls;
 252 };
 253
 254 /* The PCI personality is not quite synonymous to protocol ID:
 255  * 1. All personalities need CORE connections
 256  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 257  */
 258 enum ecore_pci_personality {
 259         ECORE_PCI_ETH,
 260         ECORE_PCI_FCOE,
 261         ECORE_PCI_ISCSI,
 262         ECORE_PCI_ETH_ROCE,
 263         ECORE_PCI_ETH_IWARP,
 264         ECORE_PCI_ETH_RDMA,
 265         ECORE_PCI_DEFAULT /* default in shmem */
 266 };
 267
 268 /* All VFs are symmetric, all counters are PF + all VFs */
 269 struct ecore_qm_iids {
 270         u32 cids;
 271         u32 vf_cids;
 272         u32 tids;
 273 };
 274
 275 #define MAX_PF_PER_PORT 8
 276
 277 /* HW / FW resources, output of features supported below, most information
 278  * is received from MFW.
 279  */
 280 enum ecore_resources {
 281         ECORE_SB,
 282         ECORE_L2_QUEUE,
 283         ECORE_VPORT,
 284         ECORE_RSS_ENG,
 285         ECORE_PQ,
 286         ECORE_RL,
 287         ECORE_MAC,
 288         ECORE_VLAN,
 289         ECORE_RDMA_CNQ_RAM,
 290         ECORE_ILT,
 291         ECORE_LL2_QUEUE,
 292         ECORE_CMDQS_CQS,
 293         ECORE_RDMA_STATS_QUEUE,
 294         ECORE_MAX_RESC,                 /* must be last */
 295 };
 296
 297 /* Features that require resources, given as input to the resource management
 298  * algorithm, the output are the resources above
 299  */
 300 enum ecore_feature {
 301         ECORE_PF_L2_QUE,
 302         ECORE_PF_TC,
 303         ECORE_VF,
 304         ECORE_EXTRA_VF_QUE,
 305         ECORE_VMQ,
 306         ECORE_RDMA_CNQ,
 307         ECORE_ISCSI_CQ,
 308         ECORE_FCOE_CQ,
 309         ECORE_VF_L2_QUE,
 310         ECORE_MAX_FEATURES,
 311 };
 312
 313 enum ecore_port_mode {
 314         ECORE_PORT_MODE_DE_2X40G,
 315         ECORE_PORT_MODE_DE_2X50G,
 316         ECORE_PORT_MODE_DE_1X100G,
 317         ECORE_PORT_MODE_DE_4X10G_F,
 318         ECORE_PORT_MODE_DE_4X10G_E,
 319         ECORE_PORT_MODE_DE_4X20G,
 320         ECORE_PORT_MODE_DE_1X40G,
 321         ECORE_PORT_MODE_DE_2X25G,
 322         ECORE_PORT_MODE_DE_1X25G,
 323         ECORE_PORT_MODE_DE_4X25G,
 324         ECORE_PORT_MODE_DE_2X10G,
 325 };
 326
 327 enum ecore_dev_cap {
 328         ECORE_DEV_CAP_ETH,
 329         ECORE_DEV_CAP_FCOE,
 330         ECORE_DEV_CAP_ISCSI,
 331         ECORE_DEV_CAP_ROCE,
 332         ECORE_DEV_CAP_IWARP
 333 };
 334
 335 #ifndef __EXTRACT__LINUX__
 336 enum ecore_hw_err_type {
 337         ECORE_HW_ERR_FAN_FAIL,
 338         ECORE_HW_ERR_MFW_RESP_FAIL,
 339         ECORE_HW_ERR_HW_ATTN,
 340         ECORE_HW_ERR_DMAE_FAIL,
 341         ECORE_HW_ERR_RAMROD_FAIL,
 342         ECORE_HW_ERR_FW_ASSERT,
 343 };
 344 #endif
 345
 346 struct ecore_hw_info {
 347         /* PCI personality */
 348         enum ecore_pci_personality personality;
 349 #define ECORE_IS_RDMA_PERSONALITY(dev)                      \
 350         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE ||  \
 351          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 352          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 353 #define ECORE_IS_ROCE_PERSONALITY(dev)                     \
 354         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 355          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 356 #define ECORE_IS_IWARP_PERSONALITY(dev)                     \
 357         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 358          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 359 #define ECORE_IS_L2_PERSONALITY(dev)                  \
 360         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 361          ECORE_IS_RDMA_PERSONALITY(dev))
 362
 363         /* Resource Allocation scheme results */
 364         u32 resc_start[ECORE_MAX_RESC];
 365         u32 resc_num[ECORE_MAX_RESC];
 366         u32 feat_num[ECORE_MAX_FEATURES];
 367
 368         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 369         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 370         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 371                                          RESC_NUM(_p_hwfn, resc))
 372         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 373
 374         /* Amount of traffic classes HW supports */
 375         u8 num_hw_tc;
 376
 377 /* Amount of TCs which should be active according to DCBx or upper layer driver
 378  * configuration
 379  */
 380
 381         u8 num_active_tc;
 382
 383         /* The traffic class used by PF for it's offloaded protocol */
 384         u8 offload_tc;
 385
 386         u32 concrete_fid;
 387         u16 opaque_fid;
 388         u16 ovlan;
 389         u32 part_num[4];
 390
 391         unsigned char hw_mac_addr[ETH_ALEN];
 392         u64 node_wwn; /* For FCoE only */
 393         u64 port_wwn; /* For FCoE only */
 394
 395         u16 num_iscsi_conns;
 396         u16 num_fcoe_conns;
 397
 398         struct ecore_igu_info *p_igu_info;
 399         /* Sriov */
 400         u8 max_chains_per_vf;
 401
 402         u32 port_mode;
 403         u32     hw_mode;
 404         unsigned long device_capabilities;
 405
 406         /* Default DCBX mode */
 407         u8 dcbx_mode;
 408
 409         u16 mtu;
 410 };
 411
 412 /* maximun size of read/write commands (HW limit) */
 413 #define DMAE_MAX_RW_SIZE        0x2000
 414
 415 struct ecore_dmae_info {
 416         /* Mutex for synchronizing access to functions */
 417         osal_mutex_t    mutex;
 418
 419         u8 channel;
 420
 421         dma_addr_t completion_word_phys_addr;
 422
 423         /* The memory location where the DMAE writes the completion
 424          * value when an operation is finished on this context.
 425          */
 426         u32 *p_completion_word;
 427
 428         dma_addr_t intermediate_buffer_phys_addr;
 429
 430         /* An intermediate buffer for DMAE operations that use virtual
 431          * addresses - data is DMA'd to/from this buffer and then
 432          * memcpy'd to/from the virtual address
 433          */
 434         u32 *p_intermediate_buffer;
 435
 436         dma_addr_t dmae_cmd_phys_addr;
 437         struct dmae_cmd *p_dmae_cmd;
 438 };
 439
 440 struct ecore_wfq_data {
 441         u32 default_min_speed; /* When wfq feature is not configured */
 442         u32 min_speed; /* when feature is configured for any 1 vport */
 443         bool configured;
 444 };
 445
 446 struct ecore_qm_info {
 447         struct init_qm_pq_params    *qm_pq_params;
 448         struct init_qm_vport_params *qm_vport_params;
 449         struct init_qm_port_params  *qm_port_params;
 450         u16                     start_pq;
 451         u8                      start_vport;
 452         u16                     pure_lb_pq;
 453         u16                     offload_pq;
 454         u16                     pure_ack_pq;
 455         u16                     ooo_pq;
 456         u16                     first_vf_pq;
 457         u16                     first_mcos_pq;
 458         u16                     first_rl_pq;
 459         u16                     num_pqs;
 460         u16                     num_vf_pqs;
 461         u8                      num_vports;
 462         u8                      max_phys_tcs_per_port;
 463         u8                      ooo_tc;
 464         bool                    pf_rl_en;
 465         bool                    pf_wfq_en;
 466         bool                    vport_rl_en;
 467         bool                    vport_wfq_en;
 468         u8                      pf_wfq;
 469         u32                     pf_rl;
 470         struct ecore_wfq_data   *wfq_data;
 471         u8                      num_pf_rls;
 472 };
 473
 474 struct storm_stats {
 475         u32 address;
 476         u32 len;
 477 };
 478
 479 struct ecore_fw_data {
 480 #ifdef CONFIG_ECORE_BINARY_FW
 481         struct fw_ver_info *fw_ver_info;
 482 #endif
 483         const u8 *modes_tree_buf;
 484         union init_op *init_ops;
 485         const u32 *arr_data;
 486         u32 init_ops_size;
 487 };
 488
 489 struct ecore_hwfn {
 490         struct ecore_dev                *p_dev;
 491         u8                              my_id;          /* ID inside the PF */
 492 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 493         u8                              rel_pf_id;      /* Relative to engine*/
 494         u8                              abs_pf_id;
 495         #define ECORE_PATH_ID(_p_hwfn) \
 496                 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 497         u8                              port_id;
 498         bool                            b_active;
 499
 500         u32                             dp_module;
 501         u8                              dp_level;
 502         char                            name[NAME_SIZE];
 503         void                            *dp_ctx;
 504
 505         bool                            first_on_engine;
 506         bool                            hw_init_done;
 507
 508         u8                              num_funcs_on_engine;
 509         u8                              enabled_func_idx;
 510
 511         /* BAR access */
 512         void OSAL_IOMEM                 *regview;
 513         void OSAL_IOMEM                 *doorbells;
 514         u64                             db_phys_addr;
 515         unsigned long                   db_size;
 516
 517         /* PTT pool */
 518         struct ecore_ptt_pool           *p_ptt_pool;
 519
 520         /* HW info */
 521         struct ecore_hw_info            hw_info;
 522
 523         /* rt_array (for init-tool) */
 524         struct ecore_rt_data            rt_data;
 525
 526         /* SPQ */
 527         struct ecore_spq                *p_spq;
 528
 529         /* EQ */
 530         struct ecore_eq                 *p_eq;
 531
 532         /* Consolidate Q*/
 533         struct ecore_consq              *p_consq;
 534
 535         /* Slow-Path definitions */
 536         osal_dpc_t                      sp_dpc;
 537         bool                            b_sp_dpc_enabled;
 538
 539         struct ecore_ptt                *p_main_ptt;
 540         struct ecore_ptt                *p_dpc_ptt;
 541
 542         struct ecore_sb_sp_info         *p_sp_sb;
 543         struct ecore_sb_attn_info       *p_sb_attn;
 544
 545         /* Protocol related */
 546         bool                            using_ll2;
 547         struct ecore_ll2_info           *p_ll2_info;
 548         struct ecore_ooo_info           *p_ooo_info;
 549         struct ecore_iscsi_info         *p_iscsi_info;
 550         struct ecore_fcoe_info          *p_fcoe_info;
 551         struct ecore_rdma_info          *p_rdma_info;
 552         struct ecore_pf_params          pf_params;
 553
 554         bool                            b_rdma_enabled_in_prs;
 555         u32                             rdma_prs_search_reg;
 556
 557         /* Array of sb_info of all status blocks */
 558         struct ecore_sb_info            *sbs_info[MAX_SB_PER_PF_MIMD];
 559         u16                             num_sbs;
 560
 561         struct ecore_cxt_mngr           *p_cxt_mngr;
 562
 563         /* Flag indicating whether interrupts are enabled or not*/
 564         bool                            b_int_enabled;
 565         bool                            b_int_requested;
 566
 567         /* True if the driver requests for the link */
 568         bool                            b_drv_link_init;
 569
 570         struct ecore_vf_iov             *vf_iov_info;
 571         struct ecore_pf_iov             *pf_iov_info;
 572         struct ecore_mcp_info           *mcp_info;
 573         struct ecore_dcbx_info          *p_dcbx_info;
 574
 575         struct ecore_dmae_info          dmae_info;
 576
 577         /* QM init */
 578         struct ecore_qm_info            qm_info;
 579
 580 #ifdef CONFIG_ECORE_ZIPPED_FW
 581         /* Buffer for unzipping firmware data */
 582         void *unzip_buf;
 583 #endif
 584
 585         struct dbg_tools_data           dbg_info;
 586
 587         struct z_stream_s               *stream;
 588
 589         /* PWM region specific data */
 590         u32                             dpi_size;
 591         u32                             dpi_count;
 592         u32                             dpi_start_offset; /* this is used to
 593                                                            * calculate th
 594                                                            * doorbell address
 595                                                            */
 596
 597         /* If one of the following is set then EDPM shouldn't be used */
 598         u8                              dcbx_no_edpm;
 599         u8                              db_bar_no_edpm;
 600 };
 601
 602 #ifndef __EXTRACT__LINUX__
 603 enum ecore_mf_mode {
 604         ECORE_MF_DEFAULT,
 605         ECORE_MF_OVLAN,
 606         ECORE_MF_NPAR,
 607 };
 608 #endif
 609
 610 /* @DPDK */
 611 struct ecore_dbg_feature {
 612         u8                              *dump_buf;
 613         u32                             buf_size;
 614         u32                             dumped_dwords;
 615 };
 616
 617 enum qed_dbg_features {
 618         DBG_FEATURE_BUS,
 619         DBG_FEATURE_GRC,
 620         DBG_FEATURE_IDLE_CHK,
 621         DBG_FEATURE_MCP_TRACE,
 622         DBG_FEATURE_REG_FIFO,
 623         DBG_FEATURE_PROTECTION_OVERRIDE,
 624         DBG_FEATURE_NUM
 625 };
 626
 627 struct ecore_dev {
 628         u32                             dp_module;
 629         u8                              dp_level;
 630         char                            name[NAME_SIZE];
 631         void                            *dp_ctx;
 632
 633         u8                              type;
 634 #define ECORE_DEV_TYPE_BB       (0 << 0)
 635 #define ECORE_DEV_TYPE_AH       (1 << 0)
 636 /* Translate type/revision combo into the proper conditions */
 637 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 638 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 639 #ifndef ASIC_ONLY
 640 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 641                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 642 #else
 643 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 644 #endif
 645 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 646 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 647
 648 #define ECORE_DEV_ID_MASK       0xff00
 649 #define ECORE_DEV_ID_MASK_BB    0x1600
 650 #define ECORE_DEV_ID_MASK_AH    0x8000
 651
 652         u16 vendor_id;
 653         u16 device_id;
 654
 655         u16                             chip_num;
 656         #define CHIP_NUM_MASK                   0xffff
 657         #define CHIP_NUM_SHIFT                  16
 658
 659         u16                             chip_rev;
 660         #define CHIP_REV_MASK                   0xf
 661         #define CHIP_REV_SHIFT                  12
 662 #ifndef ASIC_ONLY
 663         #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5)
 664         #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe)
 665         #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc)
 666         #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 667                                           CHIP_REV_IS_EMUL_B0(_p_dev))
 668         #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf)
 669         #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd)
 670         #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \
 671                                           CHIP_REV_IS_FPGA_B0(_p_dev))
 672         #define CHIP_REV_IS_SLOW(_p_dev) \
 673                 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 674         #define CHIP_REV_IS_A0(_p_dev) \
 675                 (CHIP_REV_IS_EMUL_A0(_p_dev) || \
 676                  CHIP_REV_IS_FPGA_A0(_p_dev) || \
 677                  !(_p_dev)->chip_rev)
 678         #define CHIP_REV_IS_B0(_p_dev) \
 679                 (CHIP_REV_IS_EMUL_B0(_p_dev) || \
 680                  CHIP_REV_IS_FPGA_B0(_p_dev) || \
 681                  (_p_dev)->chip_rev == 1)
 682         #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
 683 #else
 684         #define CHIP_REV_IS_A0(_p_dev)  (!(_p_dev)->chip_rev)
 685         #define CHIP_REV_IS_B0(_p_dev)  ((_p_dev)->chip_rev == 1)
 686 #endif
 687
 688         u16                             chip_metal;
 689         #define CHIP_METAL_MASK                 0xff
 690         #define CHIP_METAL_SHIFT                4
 691
 692         u16                             chip_bond_id;
 693         #define CHIP_BOND_ID_MASK               0xf
 694         #define CHIP_BOND_ID_SHIFT              0
 695
 696         u8                              num_engines;
 697         u8                              num_ports_in_engines;
 698         u8                              num_funcs_in_port;
 699
 700         u8                              path_id;
 701         enum ecore_mf_mode              mf_mode;
 702         #define IS_MF_DEFAULT(_p_hwfn)  \
 703                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 704         #define IS_MF_SI(_p_hwfn)       \
 705                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 706         #define IS_MF_SD(_p_hwfn)       \
 707                         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 708
 709         int                             pcie_width;
 710         int                             pcie_speed;
 711
 712         /* Add MF related configuration */
 713         u8                              mcp_rev;
 714         u8                              boot_mode;
 715
 716         u8                              wol;
 717
 718         u32                             int_mode;
 719         enum ecore_coalescing_mode      int_coalescing_mode;
 720         u16                             rx_coalesce_usecs;
 721         u16                             tx_coalesce_usecs;
 722
 723         /* Start Bar offset of first hwfn */
 724         void OSAL_IOMEM                 *regview;
 725         void OSAL_IOMEM                 *doorbells;
 726         u64                             db_phys_addr;
 727         unsigned long                   db_size;
 728
 729         /* PCI */
 730         u8                              cache_shift;
 731
 732         /* Init */
 733         const struct iro                *iro_arr;
 734         #define IRO (p_hwfn->p_dev->iro_arr)
 735
 736         /* HW functions */
 737         u8                              num_hwfns;
 738         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 739
 740         /* SRIOV */
 741         struct ecore_hw_sriov_info      *p_iov_info;
 742 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 743         struct ecore_tunnel_info        tunnel;
 744         bool                            b_is_vf;
 745
 746         u32                             drv_type;
 747
 748         u32                             rdma_max_sge;
 749         u32                             rdma_max_inline;
 750         u32                             rdma_max_srq_sge;
 751
 752         struct ecore_eth_stats          *reset_stats;
 753         struct ecore_fw_data            *fw_data;
 754
 755         u32                             mcp_nvm_resp;
 756
 757         /* Recovery */
 758         bool                            recov_in_prog;
 759
 760 /* Indicates whether should prevent attentions from being reasserted */
 761
 762         bool                            attn_clr_en;
 763
 764         /* Indicates whether allowing the MFW to collect a crash dump */
 765         bool                            mdump_en;
 766
 767         /* Indicates if the reg_fifo is checked after any register access */
 768         bool                            chk_reg_fifo;
 769
 770 #ifndef ASIC_ONLY
 771         bool                            b_is_emul_full;
 772 #endif
 773
 774 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 775         void                            *firmware;
 776         u64                             fw_len;
 777 #endif
 778
 779         /* @DPDK */
 780         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 781         u8                              engine_for_debug;
 782 };
 783
 784 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 785                                                   : MAX_NUM_VFS_K2)
 786 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 787                                                   : MAX_NUM_L2_QUEUES_K2)
 788 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 789                                                   : MAX_NUM_PORTS_K2)
 790 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 791                                                   : MAX_SB_PER_PATH_K2)
 792 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 793                                                   : MAX_NUM_PFS_K2)
 794
 795 /**
 796  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 797  *        the concrete value.
 798  *
 799  * @param concrete_fid
 800  *
 801  * @return OSAL_INLINE u8
 802  */
 803 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
 804                                           u32 concrete_fid)
 805 {
 806         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 807         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 808         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 809         u8 sw_fid;
 810
 811         if (vf_valid)
 812                 sw_fid = vfid + MAX_NUM_PFS;
 813         else
 814                 sw_fid = pfid;
 815
 816         return sw_fid;
 817 }
 818
 819 #define PURE_LB_TC 8
 820 #define PKT_LB_TC 9
 821
 822 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 823 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 824                                            u32 min_pf_rate);
 825
 826 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 827 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 828 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 829 int ecore_device_num_engines(struct ecore_dev *p_dev);
 830 int ecore_device_num_ports(struct ecore_dev *p_dev);
 831 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 832                            u8 *mac);
 833
 834 /* Flags for indication of required queues */
 835 #define PQ_FLAGS_RLS    (1 << 0)
 836 #define PQ_FLAGS_MCOS   (1 << 1)
 837 #define PQ_FLAGS_LB     (1 << 2)
 838 #define PQ_FLAGS_OOO    (1 << 3)
 839 #define PQ_FLAGS_ACK    (1 << 4)
 840 #define PQ_FLAGS_OFLD   (1 << 5)
 841 #define PQ_FLAGS_VFS    (1 << 6)
 842
 843 /* physical queue index for cm context intialization */
 844 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 845 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 846 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 847 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
 848
 849 /* amount of resources used in qm init */
 850 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 851 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 852 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 853 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 854 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 855
 856 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 857
 858 #endif /* __ECORE_H */