drivers/net/qede/base/ecore_cxt.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "bcm_osal.h"
   8 #include "reg_addr.h"
   9 #include "common_hsi.h"
  10 #include "ecore_hsi_common.h"
  11 #include "ecore_hsi_eth.h"
  12 #include "ecore_rt_defs.h"
  13 #include "ecore_status.h"
  14 #include "ecore.h"
  15 #include "ecore_init_ops.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_cxt.h"
  18 #include "ecore_hw.h"
  19 #include "ecore_dev_api.h"
  20 #include "ecore_sriov.h"
  21 #include "ecore_mcp.h"
  22
  23 /* Max number of connection types in HW (DQ/CDU etc.) */
  24 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  25 #define NUM_TASK_TYPES          2
  26 #define NUM_TASK_PF_SEGMENTS    4
  27 #define NUM_TASK_VF_SEGMENTS    1
  28
  29 /* Doorbell-Queue constants */
  30 #define DQ_RANGE_SHIFT  4
  31 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  32
  33 /* Searcher constants */
  34 #define SRC_MIN_NUM_ELEMS 256
  35
  36 /* Timers constants */
  37 #define TM_SHIFT        7
  38 #define TM_ALIGN        (1 << TM_SHIFT)
  39 #define TM_ELEM_SIZE    4
  40
  41 /* ILT constants */
  42 #define ILT_DEFAULT_HW_P_SIZE   4
  43
  44 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  45 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  46
  47 /* ILT entry structure */
  48 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  49 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  50 #define ILT_ENTRY_VALID_MASK            0x1ULL
  51 #define ILT_ENTRY_VALID_SHIFT           52
  52 #define ILT_ENTRY_IN_REGS               2
  53 #define ILT_REG_SIZE_IN_BYTES           4
  54
  55 /* connection context union */
  56 union conn_context {
  57         struct core_conn_context core_ctx;
  58         struct eth_conn_context eth_ctx;
  59 };
  60
  61 /* TYPE-0 task context - iSCSI, FCOE */
  62 union type0_task_context {
  63 };
  64
  65 /* TYPE-1 task context - ROCE */
  66 union type1_task_context {
  67         struct regpair reserved; /* @DPDK */
  68 };
  69
  70 struct src_ent {
  71         u8 opaque[56];
  72         u64 next;
  73 };
  74
  75 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  76 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  77
  78 #define CONN_CXT_SIZE(p_hwfn) \
  79         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  80
  81 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
  82
  83 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  84         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  85
  86 /* Alignment is inherent to the type1_task_context structure */
  87 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
  88
  89 /* PF per protocl configuration object */
  90 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
  91 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
  92
  93 struct ecore_tid_seg {
  94         u32 count;
  95         u8 type;
  96         bool has_fl_mem;
  97 };
  98
  99 struct ecore_conn_type_cfg {
 100         u32 cid_count;
 101         u32 cids_per_vf;
 102         struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
 103 };
 104
 105 /* ILT Client configuration,
 106  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 107  * 1 - for connection context (CDUC) and for each task context we need two
 108  * values, for regular task context and for force load memory
 109  */
 110 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 111 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 112 #define CDUC_BLK                (0)
 113 #define SRQ_BLK                 (0)
 114 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 115 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 116
 117 enum ilt_clients {
 118         ILT_CLI_CDUC,
 119         ILT_CLI_CDUT,
 120         ILT_CLI_QM,
 121         ILT_CLI_TM,
 122         ILT_CLI_SRC,
 123         ILT_CLI_TSDM,
 124         ILT_CLI_MAX
 125 };
 126
 127 struct ilt_cfg_pair {
 128         u32 reg;
 129         u32 val;
 130 };
 131
 132 struct ecore_ilt_cli_blk {
 133         u32 total_size;         /* 0 means not active */
 134         u32 real_size_in_page;
 135         u32 start_line;
 136         u32 dynamic_line_cnt;
 137 };
 138
 139 struct ecore_ilt_client_cfg {
 140         bool active;
 141
 142         /* ILT boundaries */
 143         struct ilt_cfg_pair first;
 144         struct ilt_cfg_pair last;
 145         struct ilt_cfg_pair p_size;
 146
 147         /* ILT client blocks for PF */
 148         struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 149         u32 pf_total_lines;
 150
 151         /* ILT client blocks for VFs */
 152         struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 153         u32 vf_total_lines;
 154 };
 155
 156 /* Per Path -
 157  *      ILT shadow table
 158  *      Protocol acquired CID lists
 159  *      PF start line in ILT
 160  */
 161 struct ecore_dma_mem {
 162         dma_addr_t p_phys;
 163         void *p_virt;
 164         osal_size_t size;
 165 };
 166
 167 #define MAP_WORD_SIZE           sizeof(unsigned long)
 168 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 169
 170 struct ecore_cid_acquired_map {
 171         u32 start_cid;
 172         u32 max_count;
 173         unsigned long *cid_map;
 174 };
 175
 176 struct ecore_cxt_mngr {
 177         /* Per protocl configuration */
 178         struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
 179
 180         /* computed ILT structure */
 181         struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
 182
 183         /* Task type sizes */
 184         u32 task_type_size[NUM_TASK_TYPES];
 185
 186         /* total number of VFs for this hwfn -
 187          * ALL VFs are symmetric in terms of HW resources
 188          */
 189         u32 vf_count;
 190
 191         /* Acquired CIDs */
 192         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 193         struct ecore_cid_acquired_map *acquired_vf[MAX_CONN_TYPES];
 194
 195         /* ILT  shadow table */
 196         struct ecore_dma_mem *ilt_shadow;
 197         u32 pf_start_line;
 198
 199         /* Mutex for a dynamic ILT allocation */
 200         osal_mutex_t mutex;
 201
 202         /* SRC T2 */
 203         struct ecore_dma_mem *t2;
 204         u32 t2_num_pages;
 205         u64 first_free;
 206         u64 last_free;
 207
 208         /* The infrastructure originally was very generic and context/task
 209          * oriented - per connection-type we would set how many of those
 210          * are needed, and later when determining how much memory we're
 211          * needing for a given block we'd iterate over all the relevant
 212          * connection-types.
 213          * But since then we've had some additional resources, some of which
 214          * require memory which is indepent of the general context/task
 215          * scheme. We add those here explicitly per-feature.
 216          */
 217
 218         /* total number of SRQ's for this hwfn */
 219         u32                             srq_count;
 220
 221         /* Maximal number of L2 steering filters */
 222         u32                             arfs_count;
 223
 224         /* TODO - VF arfs filters ? */
 225 };
 226
 227 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
 228 {
 229         return type == PROTOCOLID_TOE;
 230 }
 231
 232 static bool tm_tid_proto(enum protocol_type type)
 233 {
 234         return type == PROTOCOLID_FCOE;
 235 }
 236
 237 /* counts the iids for the CDU/CDUC ILT client configuration */
 238 struct ecore_cdu_iids {
 239         u32 pf_cids;
 240         u32 per_vf_cids;
 241 };
 242
 243 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
 244                                struct ecore_cdu_iids *iids)
 245 {
 246         u32 type;
 247
 248         for (type = 0; type < MAX_CONN_TYPES; type++) {
 249                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 250                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 251         }
 252 }
 253
 254 /* counts the iids for the Searcher block configuration */
 255 struct ecore_src_iids {
 256         u32 pf_cids;
 257         u32 per_vf_cids;
 258 };
 259
 260 static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
 261                                struct ecore_src_iids *iids)
 262 {
 263         u32 i;
 264
 265         for (i = 0; i < MAX_CONN_TYPES; i++) {
 266                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 267                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 268         }
 269
 270         /* Add L2 filtering filters in addition */
 271         iids->pf_cids += p_mngr->arfs_count;
 272 }
 273
 274 /* counts the iids for the Timers block configuration */
 275 struct ecore_tm_iids {
 276         u32 pf_cids;
 277         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 278         u32 pf_tids_total;
 279         u32 per_vf_cids;
 280         u32 per_vf_tids;
 281 };
 282
 283 static void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 284                               struct ecore_tm_iids *iids)
 285 {
 286         bool tm_vf_required = false;
 287         bool tm_required = false;
 288         u32 i, j;
 289
 290         for (i = 0; i < MAX_CONN_TYPES; i++) {
 291                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 292
 293                 if (tm_cid_proto(i) || tm_required) {
 294                         if (p_cfg->cid_count)
 295                                 tm_required = true;
 296
 297                         iids->pf_cids += p_cfg->cid_count;
 298                 }
 299
 300                 if (tm_cid_proto(i) || tm_vf_required) {
 301                         if (p_cfg->cids_per_vf)
 302                                 tm_vf_required = true;
 303
 304                 }
 305
 306                 if (tm_tid_proto(i)) {
 307                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 308
 309                         /* for each segment there is at most one
 310                          * protocol for which count is not 0.
 311                          */
 312                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 313                                 iids->pf_tids[j] += segs[j].count;
 314
 315                         /* The last array elelment is for the VFs. As for PF
 316                          * segments there can be only one protocol for
 317                          * which this value is not 0.
 318                          */
 319                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 320                 }
 321         }
 322
 323         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 324         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 325         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 326
 327         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 328                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 329                 iids->pf_tids_total += iids->pf_tids[j];
 330         }
 331 }
 332
 333 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
 334                               struct ecore_qm_iids *iids)
 335 {
 336         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 337         struct ecore_tid_seg *segs;
 338         u32 vf_cids = 0, type, j;
 339         u32 vf_tids = 0;
 340
 341         for (type = 0; type < MAX_CONN_TYPES; type++) {
 342                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 343                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 344
 345                 segs = p_mngr->conn_cfg[type].tid_seg;
 346                 /* for each segment there is at most one
 347                  * protocol for which count is not 0.
 348                  */
 349                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 350                         iids->tids += segs[j].count;
 351
 352                 /* The last array elelment is for the VFs. As for PF
 353                  * segments there can be only one protocol for
 354                  * which this value is not 0.
 355                  */
 356                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 357         }
 358
 359         iids->vf_cids += vf_cids * p_mngr->vf_count;
 360         iids->tids += vf_tids * p_mngr->vf_count;
 361
 362         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 363                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 364                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 365 }
 366
 367 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
 368                                                     u32 seg)
 369 {
 370         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 371         u32 i;
 372
 373         /* Find the protocol with tid count > 0 for this segment.
 374          * Note: there can only be one and this is already validated.
 375          */
 376         for (i = 0; i < MAX_CONN_TYPES; i++) {
 377                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 378                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 379         }
 380         return OSAL_NULL;
 381 }
 382
 383 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
 384 {
 385         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 386
 387         p_mgr->srq_count = num_srqs;
 388 }
 389
 390 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
 391 {
 392         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 393
 394         return p_mgr->srq_count;
 395 }
 396
 397 /* set the iids (cid/tid) count per protocol */
 398 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 399                                    enum protocol_type type,
 400                                    u32 cid_count, u32 vf_cid_cnt)
 401 {
 402         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 403         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 404
 405         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 406         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 407 }
 408
 409 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
 410                                   enum protocol_type type, u32 *vf_cid)
 411 {
 412         if (vf_cid)
 413                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 414
 415         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 416 }
 417
 418 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
 419                                   enum protocol_type type)
 420 {
 421         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 422 }
 423
 424 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 425                                          enum protocol_type type)
 426 {
 427         u32 cnt = 0;
 428         int i;
 429
 430         for (i = 0; i < TASK_SEGMENTS; i++)
 431                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 432
 433         return cnt;
 434 }
 435
 436 static OSAL_INLINE void
 437 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 438                               enum protocol_type proto,
 439                               u8 seg, u8 seg_type, u32 count, bool has_fl)
 440 {
 441         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 442         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 443
 444         p_seg->count = count;
 445         p_seg->has_fl_mem = has_fl;
 446         p_seg->type = seg_type;
 447 }
 448
 449 /* the *p_line parameter must be either 0 for the first invocation or the
 450  * value returned in the previous invocation.
 451  */
 452 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
 453                                    struct ecore_ilt_cli_blk *p_blk,
 454                                    u32 start_line,
 455                                    u32 total_size, u32 elem_size)
 456 {
 457         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 458
 459         /* verify that it's called once for each block */
 460         if (p_blk->total_size)
 461                 return;
 462
 463         p_blk->total_size = total_size;
 464         p_blk->real_size_in_page = 0;
 465         if (elem_size)
 466                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 467         p_blk->start_line = start_line;
 468 }
 469
 470 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
 471                                    struct ecore_ilt_client_cfg *p_cli,
 472                                    struct ecore_ilt_cli_blk *p_blk,
 473                                    u32 *p_line, enum ilt_clients client_id)
 474 {
 475         if (!p_blk->total_size)
 476                 return;
 477
 478         if (!p_cli->active)
 479                 p_cli->first.val = *p_line;
 480
 481         p_cli->active = true;
 482         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 483         p_cli->last.val = *p_line - 1;
 484
 485         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 486                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
 487                    " [Real %08x] Start line %d\n",
 488                    client_id, p_cli->first.val, p_cli->last.val,
 489                    p_blk->total_size, p_blk->real_size_in_page,
 490                    p_blk->start_line);
 491 }
 492
 493 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 494                                           enum ilt_clients ilt_client)
 495 {
 496         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 497         struct ecore_ilt_client_cfg *p_cli;
 498         u32 lines_to_skip = 0;
 499         u32 cxts_per_p;
 500
 501         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 502
 503         if (ilt_client == ILT_CLI_CDUC) {
 504                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 505
 506                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 507                     (u32)CONN_CXT_SIZE(p_hwfn);
 508
 509                 lines_to_skip = cid_count / cxts_per_p;
 510         }
 511
 512         return lines_to_skip;
 513 }
 514
 515 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
 516 {
 517         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 518         u32 curr_line, total, i, task_size, line;
 519         struct ecore_ilt_client_cfg *p_cli;
 520         struct ecore_ilt_cli_blk *p_blk;
 521         struct ecore_cdu_iids cdu_iids;
 522         struct ecore_src_iids src_iids;
 523         struct ecore_qm_iids qm_iids;
 524         struct ecore_tm_iids tm_iids;
 525         struct ecore_tid_seg *p_seg;
 526
 527         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 528         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 529         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 530         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 531
 532         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 533
 534         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 535                    "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
 536                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 537
 538         /* CDUC */
 539         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 540
 541         curr_line = p_mngr->pf_start_line;
 542
 543         /* CDUC PF */
 544         p_cli->pf_total_lines = 0;
 545
 546         /* get the counters for the CDUC,CDUC and QM clients  */
 547         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 548
 549         p_blk = &p_cli->pf_blks[CDUC_BLK];
 550
 551         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 552
 553         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 554                                total, CONN_CXT_SIZE(p_hwfn));
 555
 556         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 557         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 558
 559         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 560                                                                  ILT_CLI_CDUC);
 561
 562         /* CDUC VF */
 563         p_blk = &p_cli->vf_blks[CDUC_BLK];
 564         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 565
 566         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 567                                total, CONN_CXT_SIZE(p_hwfn));
 568
 569         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 570         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 571
 572         for (i = 1; i < p_mngr->vf_count; i++)
 573                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 574                                        ILT_CLI_CDUC);
 575
 576         /* CDUT PF */
 577         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 578         p_cli->first.val = curr_line;
 579
 580         /* first the 'working' task memory */
 581         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 582                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 583                 if (!p_seg || p_seg->count == 0)
 584                         continue;
 585
 586                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 587                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 588                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 589                                        p_mngr->task_type_size[p_seg->type]);
 590
 591                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 592                                        ILT_CLI_CDUT);
 593         }
 594
 595         /* next the 'init' task memory (forced load memory) */
 596         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 597                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 598                 if (!p_seg || p_seg->count == 0)
 599                         continue;
 600
 601                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 602
 603                 if (!p_seg->has_fl_mem) {
 604                         /* The segment is active (total size pf 'working'
 605                          * memory is > 0) but has no FL (forced-load, Init)
 606                          * memory. Thus:
 607                          *
 608                          * 1.   The total-size in the corrsponding FL block of
 609                          *      the ILT client is set to 0 - No ILT line are
 610                          *      provisioned and no ILT memory allocated.
 611                          *
 612                          * 2.   The start-line of said block is set to the
 613                          *      start line of the matching working memory
 614                          *      block in the ILT client. This is later used to
 615                          *      configure the CDU segment offset registers and
 616                          *      results in an FL command for TIDs of this
 617                          *      segment behaves as regular load commands
 618                          *      (loading TIDs from the working memory).
 619                          */
 620                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 621
 622                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 623                         continue;
 624                 }
 625                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 626
 627                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 628                                        curr_line, total,
 629                                        p_mngr->task_type_size[p_seg->type]);
 630
 631                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 632                                        ILT_CLI_CDUT);
 633         }
 634         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 635
 636         /* CDUT VF */
 637         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 638         if (p_seg && p_seg->count) {
 639                 /* Stricly speaking we need to iterate over all VF
 640                  * task segment types, but a VF has only 1 segment
 641                  */
 642
 643                 /* 'working' memory */
 644                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 645
 646                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 647                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 648                                        curr_line, total,
 649                                        p_mngr->task_type_size[p_seg->type]);
 650
 651                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 652                                        ILT_CLI_CDUT);
 653
 654                 /* 'init' memory */
 655                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 656                 if (!p_seg->has_fl_mem) {
 657                         /* see comment above */
 658                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 659                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 660                 } else {
 661                         task_size = p_mngr->task_type_size[p_seg->type];
 662                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 663                                                curr_line, total, task_size);
 664                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 665                                                ILT_CLI_CDUT);
 666                 }
 667                 p_cli->vf_total_lines = curr_line -
 668                     p_cli->vf_blks[0].start_line;
 669
 670                 /* Now for the rest of the VFs */
 671                 for (i = 1; i < p_mngr->vf_count; i++) {
 672                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 673                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 674                                                ILT_CLI_CDUT);
 675
 676                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 677                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 678                                                ILT_CLI_CDUT);
 679                 }
 680         }
 681
 682         /* QM */
 683         p_cli = &p_mngr->clients[ILT_CLI_QM];
 684         p_blk = &p_cli->pf_blks[0];
 685
 686         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 687         total = ecore_qm_pf_mem_size(qm_iids.cids,
 688                                      qm_iids.vf_cids, qm_iids.tids,
 689                                      p_hwfn->qm_info.num_pqs,
 690                                      p_hwfn->qm_info.num_vf_pqs);
 691
 692         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 693                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
 694                    " num_vf_pqs=%d, memory_size=%d)\n",
 695                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 696                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 697
 698         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 699                                QM_PQ_ELEMENT_SIZE);
 700
 701         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 702         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 703
 704         /* SRC */
 705         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 706         ecore_cxt_src_iids(p_mngr, &src_iids);
 707
 708         /* Both the PF and VFs searcher connections are stored in the per PF
 709          * database. Thus sum the PF searcher cids and all the VFs searcher
 710          * cids.
 711          */
 712         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 713         if (total) {
 714                 u32 local_max = OSAL_MAX_T(u32, total,
 715                                            SRC_MIN_NUM_ELEMS);
 716
 717                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 718
 719                 p_blk = &p_cli->pf_blks[0];
 720                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 721                                        total * sizeof(struct src_ent),
 722                                        sizeof(struct src_ent));
 723
 724                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 725                                        ILT_CLI_SRC);
 726                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 727         }
 728
 729         /* TM PF */
 730         p_cli = &p_mngr->clients[ILT_CLI_TM];
 731         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 732         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 733         if (total) {
 734                 p_blk = &p_cli->pf_blks[0];
 735                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 736                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 737
 738                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 739                                        ILT_CLI_TM);
 740                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 741         }
 742
 743         /* TM VF */
 744         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 745         if (total) {
 746                 p_blk = &p_cli->vf_blks[0];
 747                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 748                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 749
 750                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 751                                        ILT_CLI_TM);
 752
 753                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 754                 for (i = 1; i < p_mngr->vf_count; i++) {
 755                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 756                                                ILT_CLI_TM);
 757                 }
 758         }
 759
 760         /* TSDM (SRQ CONTEXT) */
 761         total = ecore_cxt_get_srq_count(p_hwfn);
 762
 763         if (total) {
 764                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 765                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 766                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 767                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 768
 769                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 770                                        ILT_CLI_TSDM);
 771                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 772         }
 773
 774         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 775             RESC_NUM(p_hwfn, ECORE_ILT)) {
 776                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 777                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 778                 return ECORE_INVAL;
 779         }
 780
 781         return ECORE_SUCCESS;
 782 }
 783
 784 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 785 {
 786         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 787         u32 i;
 788
 789         if (!p_mngr->t2)
 790                 return;
 791
 792         for (i = 0; i < p_mngr->t2_num_pages; i++)
 793                 if (p_mngr->t2[i].p_virt)
 794                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 795                                                p_mngr->t2[i].p_virt,
 796                                                p_mngr->t2[i].p_phys,
 797                                                p_mngr->t2[i].size);
 798
 799         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 800 }
 801
 802 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 803 {
 804         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 805         u32 conn_num, total_size, ent_per_page, psz, i;
 806         struct ecore_ilt_client_cfg *p_src;
 807         struct ecore_src_iids src_iids;
 808         struct ecore_dma_mem *p_t2;
 809         enum _ecore_status_t rc;
 810
 811         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 812
 813         /* if the SRC ILT client is inactive - there are no connection
 814          * requiring the searcer, leave.
 815          */
 816         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 817         if (!p_src->active)
 818                 return ECORE_SUCCESS;
 819
 820         ecore_cxt_src_iids(p_mngr, &src_iids);
 821         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 822         total_size = conn_num * sizeof(struct src_ent);
 823
 824         /* use the same page size as the SRC ILT client */
 825         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 826         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 827
 828         /* allocate t2 */
 829         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 830                                  p_mngr->t2_num_pages *
 831                                  sizeof(struct ecore_dma_mem));
 832         if (!p_mngr->t2) {
 833                 DP_NOTICE(p_hwfn, false, "Failed to allocate t2 table\n");
 834                 rc = ECORE_NOMEM;
 835                 goto t2_fail;
 836         }
 837
 838         /* allocate t2 pages */
 839         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 840                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 841                 void **p_virt = &p_mngr->t2[i].p_virt;
 842
 843                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 844                                                   &p_mngr->t2[i].p_phys, size);
 845                 if (!p_mngr->t2[i].p_virt) {
 846                         rc = ECORE_NOMEM;
 847                         goto t2_fail;
 848                 }
 849                 OSAL_MEM_ZERO(*p_virt, size);
 850                 p_mngr->t2[i].size = size;
 851                 total_size -= size;
 852         }
 853
 854         /* Set the t2 pointers */
 855
 856         /* entries per page - must be a power of two */
 857         ent_per_page = psz / sizeof(struct src_ent);
 858
 859         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 860
 861         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 862         p_mngr->last_free = (u64)p_t2->p_phys +
 863             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 864
 865         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 866                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
 867                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 868                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
 869                 u32 j;
 870
 871                 for (j = 0; j < ent_num - 1; j++) {
 872                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 873                         entries[j].next = OSAL_CPU_TO_BE64(val);
 874                 }
 875
 876                 if (i < p_mngr->t2_num_pages - 1)
 877                         val = (u64)p_mngr->t2[i + 1].p_phys;
 878                 else
 879                         val = 0;
 880                 entries[j].next = OSAL_CPU_TO_BE64(val);
 881
 882                 conn_num -= ent_num;
 883         }
 884
 885         return ECORE_SUCCESS;
 886
 887 t2_fail:
 888         ecore_cxt_src_t2_free(p_hwfn);
 889         return rc;
 890 }
 891
 892 #define for_each_ilt_valid_client(pos, clients)         \
 893         for (pos = 0; pos < ILT_CLI_MAX; pos++)         \
 894                 if (!clients[pos].active) {             \
 895                         continue;                       \
 896                 } else                                  \
 897
 898
 899 /* Total number of ILT lines used by this PF */
 900 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
 901 {
 902         u32 size = 0;
 903         u32 i;
 904
 905         for_each_ilt_valid_client(i, ilt_clients)
 906                 size += (ilt_clients[i].last.val -
 907                          ilt_clients[i].first.val + 1);
 908
 909         return size;
 910 }
 911
 912 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
 913 {
 914         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 915         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 916         u32 ilt_size, i;
 917
 918         if (p_mngr->ilt_shadow == OSAL_NULL)
 919                 return;
 920
 921         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
 922
 923         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 924                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 925
 926                 if (p_dma->p_virt)
 927                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 928                                                p_dma->p_virt,
 929                                                p_dma->p_phys, p_dma->size);
 930                 p_dma->p_virt = OSAL_NULL;
 931         }
 932         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
 933         p_mngr->ilt_shadow = OSAL_NULL;
 934 }
 935
 936 static enum _ecore_status_t
 937 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
 938                     struct ecore_ilt_cli_blk *p_blk,
 939                     enum ilt_clients ilt_client, u32 start_line_offset)
 940 {
 941         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 942         u32 lines, line, sz_left, lines_to_skip = 0;
 943
 944         /* Special handling for RoCE that supports dynamic allocation */
 945         if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
 946                 return ECORE_SUCCESS;
 947
 948         lines_to_skip = p_blk->dynamic_line_cnt;
 949
 950         if (!p_blk->total_size)
 951                 return ECORE_SUCCESS;
 952
 953         sz_left = p_blk->total_size;
 954         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 955         line = p_blk->start_line + start_line_offset -
 956             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 957
 958         for (; lines; lines--) {
 959                 dma_addr_t p_phys;
 960                 void *p_virt;
 961                 u32 size;
 962
 963                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
 964
 965 /* @DPDK */
 966 #define ILT_BLOCK_ALIGN_SIZE 0x1000
 967                 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
 968                                                          &p_phys, size,
 969                                                          ILT_BLOCK_ALIGN_SIZE);
 970                 if (!p_virt)
 971                         return ECORE_NOMEM;
 972                 OSAL_MEM_ZERO(p_virt, size);
 973
 974                 ilt_shadow[line].p_phys = p_phys;
 975                 ilt_shadow[line].p_virt = p_virt;
 976                 ilt_shadow[line].size = size;
 977
 978                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 979                            "ILT shadow: Line [%d] Physical 0x%lx"
 980                            " Virtual %p Size %d\n",
 981                            line, (unsigned long)p_phys, p_virt, size);
 982
 983                 sz_left -= size;
 984                 line++;
 985         }
 986
 987         return ECORE_SUCCESS;
 988 }
 989
 990 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
 991 {
 992         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 993         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
 994         struct ecore_ilt_cli_blk *p_blk;
 995         u32 size, i, j, k;
 996         enum _ecore_status_t rc;
 997
 998         size = ecore_cxt_ilt_shadow_size(clients);
 999         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1000                                          size * sizeof(struct ecore_dma_mem));
1001
1002         if (!p_mngr->ilt_shadow) {
1003                 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt shadow table\n");
1004                 rc = ECORE_NOMEM;
1005                 goto ilt_shadow_fail;
1006         }
1007
1008         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1009                    "Allocated 0x%x bytes for ilt shadow\n",
1010                    (u32)(size * sizeof(struct ecore_dma_mem)));
1011
1012         for_each_ilt_valid_client(i, clients) {
1013                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1014                         p_blk = &clients[i].pf_blks[j];
1015                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1016                         if (rc != ECORE_SUCCESS)
1017                                 goto ilt_shadow_fail;
1018                 }
1019                 for (k = 0; k < p_mngr->vf_count; k++) {
1020                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1021                                 u32 lines = clients[i].vf_total_lines * k;
1022
1023                                 p_blk = &clients[i].vf_blks[j];
1024                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1025                                                          i, lines);
1026                                 if (rc != ECORE_SUCCESS)
1027                                         goto ilt_shadow_fail;
1028                         }
1029                 }
1030         }
1031
1032         return ECORE_SUCCESS;
1033
1034 ilt_shadow_fail:
1035         ecore_ilt_shadow_free(p_hwfn);
1036         return rc;
1037 }
1038
1039 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1040 {
1041         u32 type, vf, max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
1042         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1043
1044         for (type = 0; type < MAX_CONN_TYPES; type++) {
1045                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1046                 p_mngr->acquired[type].cid_map = OSAL_NULL;
1047                 p_mngr->acquired[type].max_count = 0;
1048                 p_mngr->acquired[type].start_cid = 0;
1049
1050                 for (vf = 0; vf < max_num_vfs; vf++) {
1051                         OSAL_FREE(p_hwfn->p_dev,
1052                                   p_mngr->acquired_vf[type][vf].cid_map);
1053                         p_mngr->acquired_vf[type][vf].cid_map = OSAL_NULL;
1054                         p_mngr->acquired_vf[type][vf].max_count = 0;
1055                         p_mngr->acquired_vf[type][vf].start_cid = 0;
1056                 }
1057         }
1058 }
1059
1060 static enum _ecore_status_t
1061 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1062                            u32 cid_start, u32 cid_count,
1063                            struct ecore_cid_acquired_map *p_map)
1064 {
1065         u32 size;
1066
1067         if (!cid_count)
1068                 return ECORE_SUCCESS;
1069
1070         size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1071         p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1072         if (p_map->cid_map == OSAL_NULL)
1073                 return ECORE_NOMEM;
1074
1075         p_map->max_count = cid_count;
1076         p_map->start_cid = cid_start;
1077
1078         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1079                    "Type %08x start: %08x count %08x\n",
1080                    type, p_map->start_cid, p_map->max_count);
1081
1082         return ECORE_SUCCESS;
1083 }
1084
1085 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1086 {
1087         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1088         u32 max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
1089         u32 start_cid = 0, vf_start_cid = 0;
1090         u32 type, vf;
1091
1092         for (type = 0; type < MAX_CONN_TYPES; type++) {
1093                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1094                 struct ecore_cid_acquired_map *p_map;
1095
1096                 /* Handle PF maps */
1097                 p_map = &p_mngr->acquired[type];
1098                 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1099                                                p_cfg->cid_count, p_map))
1100                         goto cid_map_fail;
1101
1102                 /* Handle VF maps */
1103                 for (vf = 0; vf < max_num_vfs; vf++) {
1104                         p_map = &p_mngr->acquired_vf[type][vf];
1105                         if (ecore_cid_map_alloc_single(p_hwfn, type,
1106                                                        vf_start_cid,
1107                                                        p_cfg->cids_per_vf,
1108                                                        p_map))
1109                                 goto cid_map_fail;
1110                 }
1111
1112                 start_cid += p_cfg->cid_count;
1113                 vf_start_cid += p_cfg->cids_per_vf;
1114         }
1115
1116         return ECORE_SUCCESS;
1117
1118 cid_map_fail:
1119         ecore_cid_map_free(p_hwfn);
1120         return ECORE_NOMEM;
1121 }
1122
1123 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1124 {
1125         struct ecore_ilt_client_cfg *clients;
1126         struct ecore_cxt_mngr *p_mngr;
1127         u32 i;
1128
1129         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1130         if (!p_mngr) {
1131                 DP_NOTICE(p_hwfn, false, "Failed to allocate `struct ecore_cxt_mngr'\n");
1132                 return ECORE_NOMEM;
1133         }
1134
1135         /* Set the cxt mangr pointer prior to further allocations */
1136         p_hwfn->p_cxt_mngr = p_mngr;
1137
1138         /* Initialize ILT client registers */
1139         clients = p_mngr->clients;
1140         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1141         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1142         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1143
1144         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1145         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1146         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1147
1148         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1149         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1150         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1151
1152         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1153         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1154         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1155
1156         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1157         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1158         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1159
1160         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1161         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1162         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1163
1164         /* default ILT page size for all clients is 64K */
1165         for (i = 0; i < ILT_CLI_MAX; i++)
1166                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1167
1168         /* due to removal of ISCSI/FCoE files union type0_task_context
1169          * task_type_size will be 0. So hardcoded for now.
1170          */
1171         p_mngr->task_type_size[0] = 512; /* @DPDK */
1172         p_mngr->task_type_size[1] = 128; /* @DPDK */
1173
1174         if (p_hwfn->p_dev->p_iov_info)
1175                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1176
1177         /* Initialize the dynamic ILT allocation mutex */
1178 #ifdef CONFIG_ECORE_LOCK_ALLOC
1179         if (OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex)) {
1180                 DP_NOTICE(p_hwfn, false, "Failed to alloc p_mngr->mutex\n");
1181                 return ECORE_NOMEM;
1182         }
1183 #endif
1184         OSAL_MUTEX_INIT(&p_mngr->mutex);
1185
1186         return ECORE_SUCCESS;
1187 }
1188
1189 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1190 {
1191         enum _ecore_status_t rc;
1192
1193         /* Allocate the ILT shadow table */
1194         rc = ecore_ilt_shadow_alloc(p_hwfn);
1195         if (rc) {
1196                 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt memory\n");
1197                 goto tables_alloc_fail;
1198         }
1199
1200         /* Allocate the T2  table */
1201         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1202         if (rc) {
1203                 DP_NOTICE(p_hwfn, false, "Failed to allocate T2 memory\n");
1204                 goto tables_alloc_fail;
1205         }
1206
1207         /* Allocate and initialize the acquired cids bitmaps */
1208         rc = ecore_cid_map_alloc(p_hwfn);
1209         if (rc) {
1210                 DP_NOTICE(p_hwfn, false, "Failed to allocate cid maps\n");
1211                 goto tables_alloc_fail;
1212         }
1213
1214         return ECORE_SUCCESS;
1215
1216 tables_alloc_fail:
1217         ecore_cxt_mngr_free(p_hwfn);
1218         return rc;
1219 }
1220
1221 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1222 {
1223         if (!p_hwfn->p_cxt_mngr)
1224                 return;
1225
1226         ecore_cid_map_free(p_hwfn);
1227         ecore_cxt_src_t2_free(p_hwfn);
1228         ecore_ilt_shadow_free(p_hwfn);
1229 #ifdef CONFIG_ECORE_LOCK_ALLOC
1230         OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1231 #endif
1232         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1233 }
1234
1235 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1236 {
1237         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1238         u32 len, max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
1239         struct ecore_cid_acquired_map *p_map;
1240         struct ecore_conn_type_cfg *p_cfg;
1241         int type;
1242
1243         /* Reset acquired cids */
1244         for (type = 0; type < MAX_CONN_TYPES; type++) {
1245                 u32 vf;
1246
1247                 p_cfg = &p_mngr->conn_cfg[type];
1248                 if (p_cfg->cid_count) {
1249                         p_map = &p_mngr->acquired[type];
1250                         len = DIV_ROUND_UP(p_map->max_count,
1251                                            BITS_PER_MAP_WORD) *
1252                               MAP_WORD_SIZE;
1253                         OSAL_MEM_ZERO(p_map->cid_map, len);
1254                 }
1255
1256                 if (!p_cfg->cids_per_vf)
1257                         continue;
1258
1259                 for (vf = 0; vf < max_num_vfs; vf++) {
1260                         p_map = &p_mngr->acquired_vf[type][vf];
1261                         len = DIV_ROUND_UP(p_map->max_count,
1262                                            BITS_PER_MAP_WORD) *
1263                               MAP_WORD_SIZE;
1264                         OSAL_MEM_ZERO(p_map->cid_map, len);
1265                 }
1266         }
1267 }
1268
1269 /* HW initialization helper (per Block, per phase) */
1270
1271 /* CDU Common */
1272 #define CDUC_CXT_SIZE_SHIFT                                             \
1273         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1274
1275 #define CDUC_CXT_SIZE_MASK                                              \
1276         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1277
1278 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1279         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1280
1281 #define CDUC_BLOCK_WASTE_MASK                                           \
1282         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1283
1284 #define CDUC_NCIB_SHIFT                                                 \
1285         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1286
1287 #define CDUC_NCIB_MASK                                                  \
1288         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1289
1290 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1291         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1292
1293 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1294         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1295         CDUT_TYPE0_CXT_SIZE_SHIFT)
1296
1297 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1298         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1299
1300 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1301         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1302         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1303
1304 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1305         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1306
1307 #define CDUT_TYPE0_NCIB_MASK                                            \
1308         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1309         CDUT_TYPE0_NCIB_SHIFT)
1310
1311 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1312         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1313
1314 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1315         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1316         CDUT_TYPE1_CXT_SIZE_SHIFT)
1317
1318 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1319         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1320
1321 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1322         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1323         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1324
1325 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1326         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1327
1328 #define CDUT_TYPE1_NCIB_MASK                                            \
1329         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1330         CDUT_TYPE1_NCIB_SHIFT)
1331
1332 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1333 {
1334         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1335
1336         /* CDUC - connection configuration */
1337         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1338         cxt_size = CONN_CXT_SIZE(p_hwfn);
1339         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1340         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1341
1342         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1343         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1344         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1345         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1346
1347         /* CDUT - type-0 tasks configuration */
1348         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1349         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1350         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1351         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1352
1353         /* cxt size and block-waste are multipes of 8 */
1354         cdu_params = 0;
1355         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1356         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1357         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1358         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1359
1360         /* CDUT - type-1 tasks configuration */
1361         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1362         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1363         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1364
1365         /* cxt size and block-waste are multipes of 8 */
1366         cdu_params = 0;
1367         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1368         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1369         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1370         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1371 }
1372
1373 /* CDU PF */
1374 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1375 #define CDU_SEG_REG_TYPE_MASK           0x1
1376 #define CDU_SEG_REG_OFFSET_SHIFT        0
1377 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1378
1379 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1380 {
1381         struct ecore_ilt_client_cfg *p_cli;
1382         struct ecore_tid_seg *p_seg;
1383         u32 cdu_seg_params, offset;
1384         int i;
1385
1386         static const u32 rt_type_offset_arr[] = {
1387                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1388                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1389                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1390                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1391         };
1392
1393         static const u32 rt_type_offset_fl_arr[] = {
1394                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1395                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1396                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1397                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1398         };
1399
1400         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1401
1402         /* There are initializations only for CDUT during pf Phase */
1403         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1404                 /* Segment 0 */
1405                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1406                 if (!p_seg)
1407                         continue;
1408
1409                 /* Note: start_line is already adjusted for the CDU
1410                  * segment register granularity, so we just need to
1411                  * divide. Adjustment is implicit as we assume ILT
1412                  * Page size is larger than 32K!
1413                  */
1414                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1415                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1416                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1417
1418                 cdu_seg_params = 0;
1419                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1420                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1421                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1422
1423                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1424                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1425                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1426
1427                 cdu_seg_params = 0;
1428                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1429                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1430                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1431         }
1432 }
1433
1434 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1435                       bool is_pf_loading)
1436 {
1437         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1438         struct ecore_mcp_link_state *p_link;
1439         struct ecore_qm_iids iids;
1440
1441         OSAL_MEM_ZERO(&iids, sizeof(iids));
1442         ecore_cxt_qm_iids(p_hwfn, &iids);
1443
1444         p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output;
1445
1446         ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1447                             qm_info->max_phys_tcs_per_port,
1448                             is_pf_loading,
1449                             iids.cids, iids.vf_cids, iids.tids,
1450                             qm_info->start_pq,
1451                             qm_info->num_pqs - qm_info->num_vf_pqs,
1452                             qm_info->num_vf_pqs,
1453                             qm_info->start_vport,
1454                             qm_info->num_vports, qm_info->pf_wfq,
1455                             qm_info->pf_rl, p_link->speed,
1456                             p_hwfn->qm_info.qm_pq_params,
1457                             p_hwfn->qm_info.qm_vport_params);
1458 }
1459
1460 /* CM PF */
1461 static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1462 {
1463         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET,
1464                      ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1465 }
1466
1467 /* DQ PF */
1468 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1469 {
1470         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1471         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1472
1473         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1474         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1475
1476         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1477         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1478
1479         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1480         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1481
1482         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1483         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1484
1485         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1486         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1487
1488         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1489         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1490
1491         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1492         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1493
1494         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1495         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1496
1497         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1498         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1499
1500         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1501         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1502
1503         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1504         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1505
1506         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1507         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1508
1509         /* Connection types 6 & 7 are not in use, yet they must be configured
1510          * as the highest possible connection. Not configuring them means the
1511          * defaults will be  used, and with a large number of cids a bug may
1512          * occur, if the defaults will be smaller than dq_pf_max_cid /
1513          * dq_vf_max_cid.
1514          */
1515         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1516         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1517
1518         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1519         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1520 }
1521
1522 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1523 {
1524         struct ecore_ilt_client_cfg *ilt_clients;
1525         int i;
1526
1527         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1528         for_each_ilt_valid_client(i, ilt_clients) {
1529                 STORE_RT_REG(p_hwfn,
1530                              ilt_clients[i].first.reg,
1531                              ilt_clients[i].first.val);
1532                 STORE_RT_REG(p_hwfn,
1533                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1534                 STORE_RT_REG(p_hwfn,
1535                              ilt_clients[i].p_size.reg,
1536                              ilt_clients[i].p_size.val);
1537         }
1538 }
1539
1540 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1541 {
1542         struct ecore_ilt_client_cfg *p_cli;
1543         u32 blk_factor;
1544
1545         /* For simplicty  we set the 'block' to be an ILT page */
1546         if (p_hwfn->p_dev->p_iov_info) {
1547                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1548
1549                 STORE_RT_REG(p_hwfn,
1550                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1551                              p_iov->first_vf_in_pf);
1552                 STORE_RT_REG(p_hwfn,
1553                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1554                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1555         }
1556
1557         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1558         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1559         if (p_cli->active) {
1560                 STORE_RT_REG(p_hwfn,
1561                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1562                              blk_factor);
1563                 STORE_RT_REG(p_hwfn,
1564                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1565                              p_cli->pf_total_lines);
1566                 STORE_RT_REG(p_hwfn,
1567                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1568                              p_cli->vf_total_lines);
1569         }
1570
1571         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1572         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1573         if (p_cli->active) {
1574                 STORE_RT_REG(p_hwfn,
1575                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1576                              blk_factor);
1577                 STORE_RT_REG(p_hwfn,
1578                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1579                              p_cli->pf_total_lines);
1580                 STORE_RT_REG(p_hwfn,
1581                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1582                              p_cli->vf_total_lines);
1583         }
1584
1585         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1586         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1587         if (p_cli->active) {
1588                 STORE_RT_REG(p_hwfn,
1589                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1590                 STORE_RT_REG(p_hwfn,
1591                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1592                              p_cli->pf_total_lines);
1593                 STORE_RT_REG(p_hwfn,
1594                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1595                              p_cli->vf_total_lines);
1596         }
1597 }
1598
1599 /* ILT (PSWRQ2) PF */
1600 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1601 {
1602         struct ecore_ilt_client_cfg *clients;
1603         struct ecore_cxt_mngr *p_mngr;
1604         struct ecore_dma_mem *p_shdw;
1605         u32 line, rt_offst, i;
1606
1607         ecore_ilt_bounds_init(p_hwfn);
1608         ecore_ilt_vf_bounds_init(p_hwfn);
1609
1610         p_mngr = p_hwfn->p_cxt_mngr;
1611         p_shdw = p_mngr->ilt_shadow;
1612         clients = p_hwfn->p_cxt_mngr->clients;
1613
1614         for_each_ilt_valid_client(i, clients) {
1615                 /* Client's 1st val and RT array are absolute, ILT shadows'
1616                  * lines are relative.
1617                  */
1618                 line = clients[i].first.val - p_mngr->pf_start_line;
1619                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1620                     clients[i].first.val * ILT_ENTRY_IN_REGS;
1621
1622                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1623                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1624                         u64 ilt_hw_entry = 0;
1625
1626                         /** p_virt could be OSAL_NULL incase of dynamic
1627                          *  allocation
1628                          */
1629                         if (p_shdw[line].p_virt != OSAL_NULL) {
1630                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1631                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1632                                           (p_shdw[line].p_phys >> 12));
1633
1634                                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1635                                         "Setting RT[0x%08x] from"
1636                                         " ILT[0x%08x] [Client is %d] to"
1637                                         " Physical addr: 0x%lx\n",
1638                                         rt_offst, line, i,
1639                                         (unsigned long)(p_shdw[line].
1640                                                         p_phys >> 12));
1641                         }
1642
1643                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1644                 }
1645         }
1646 }
1647
1648 /* SRC (Searcher) PF */
1649 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1650 {
1651         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1652         u32 rounded_conn_num, conn_num, conn_max;
1653         struct ecore_src_iids src_iids;
1654
1655         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1656         ecore_cxt_src_iids(p_mngr, &src_iids);
1657         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1658         if (!conn_num)
1659                 return;
1660
1661         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1662         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1663
1664         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1665         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1666                      OSAL_LOG2(rounded_conn_num));
1667
1668         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1669                          p_hwfn->p_cxt_mngr->first_free);
1670         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1671                          p_hwfn->p_cxt_mngr->last_free);
1672         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1673                    "Configured SEARCHER for 0x%08x connections\n",
1674                    conn_num);
1675 }
1676
1677 /* Timers PF */
1678 #define TM_CFG_NUM_IDS_SHIFT            0
1679 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1680 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1681 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1682 #define TM_CFG_PARENT_PF_SHIFT          25
1683 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1684
1685 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1686 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1687
1688 #define TM_CFG_TID_OFFSET_SHIFT         30
1689 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1690 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1691 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1692
1693 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1694 {
1695         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1696         u32 active_seg_mask = 0, tm_offset, rt_reg;
1697         struct ecore_tm_iids tm_iids;
1698         u64 cfg_word;
1699         u8 i;
1700
1701         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1702         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1703
1704         /* @@@TBD No pre-scan for now */
1705
1706         /* Note: We assume consecutive VFs for a PF */
1707         for (i = 0; i < p_mngr->vf_count; i++) {
1708                 cfg_word = 0;
1709                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1710                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1711                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1712                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1713
1714                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1715                     (sizeof(cfg_word) / sizeof(u32)) *
1716                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1717                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1718         }
1719
1720         cfg_word = 0;
1721         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1722         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1723         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1724         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1725
1726         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1727             (sizeof(cfg_word) / sizeof(u32)) *
1728             (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1729         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1730
1731         /* enale scan */
1732         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1733                      tm_iids.pf_cids ? 0x1 : 0x0);
1734
1735         /* @@@TBD how to enable the scan for the VFs */
1736
1737         tm_offset = tm_iids.per_vf_cids;
1738
1739         /* Note: We assume consecutive VFs for a PF */
1740         for (i = 0; i < p_mngr->vf_count; i++) {
1741                 cfg_word = 0;
1742                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1743                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1744                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1745                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1746                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1747
1748                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1749                     (sizeof(cfg_word) / sizeof(u32)) *
1750                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1751
1752                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1753         }
1754
1755         tm_offset = tm_iids.pf_cids;
1756         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1757                 cfg_word = 0;
1758                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1759                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1760                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1761                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1762                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1763
1764                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1765                     (sizeof(cfg_word) / sizeof(u32)) *
1766                     (NUM_OF_VFS(p_hwfn->p_dev) +
1767                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1768
1769                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1770                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1771
1772                 tm_offset += tm_iids.pf_tids[i];
1773         }
1774
1775         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1776
1777         /* @@@TBD how to enable the scan for the VFs */
1778 }
1779
1780 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1781 {
1782         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1783         struct ecore_conn_type_cfg *p_fcoe;
1784         struct ecore_tid_seg *p_tid;
1785
1786         p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1787
1788         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1789         if (!p_fcoe->cid_count)
1790                 return;
1791
1792         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1793         STORE_RT_REG_AGG(p_hwfn,
1794                         PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1795                         p_tid->count);
1796 }
1797
1798 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1799 {
1800         /* CDU configuration */
1801         ecore_cdu_init_common(p_hwfn);
1802 }
1803
1804 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1805 {
1806         ecore_qm_init_pf(p_hwfn, p_ptt, true);
1807         ecore_cm_init_pf(p_hwfn);
1808         ecore_dq_init_pf(p_hwfn);
1809         ecore_cdu_init_pf(p_hwfn);
1810         ecore_ilt_init_pf(p_hwfn);
1811         ecore_src_init_pf(p_hwfn);
1812         ecore_tm_init_pf(p_hwfn);
1813         ecore_prs_init_pf(p_hwfn);
1814 }
1815
1816 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1817                                             enum protocol_type type,
1818                                             u32 *p_cid, u8 vfid)
1819 {
1820         u32 rel_cid, max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
1821         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1822         struct ecore_cid_acquired_map *p_map;
1823
1824         if (type >= MAX_CONN_TYPES) {
1825                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1826                 return ECORE_INVAL;
1827         }
1828
1829         if (vfid >= max_num_vfs && vfid != ECORE_CXT_PF_CID) {
1830                 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1831                 return ECORE_INVAL;
1832         }
1833
1834         /* Determine the right map to take this CID from */
1835         if (vfid == ECORE_CXT_PF_CID)
1836                 p_map = &p_mngr->acquired[type];
1837         else
1838                 p_map = &p_mngr->acquired_vf[type][vfid];
1839
1840         if (p_map->cid_map == OSAL_NULL) {
1841                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1842                 return ECORE_INVAL;
1843         }
1844
1845         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1846                                            p_map->max_count);
1847
1848         if (rel_cid >= p_map->max_count) {
1849                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1850                           type);
1851                 return ECORE_NORESOURCES;
1852         }
1853
1854         OSAL_SET_BIT(rel_cid, p_map->cid_map);
1855
1856         *p_cid = rel_cid + p_map->start_cid;
1857
1858         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1859                    "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1860                    *p_cid, rel_cid, vfid, type);
1861
1862         return ECORE_SUCCESS;
1863 }
1864
1865 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1866                                            enum protocol_type type,
1867                                            u32 *p_cid)
1868 {
1869         return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
1870 }
1871
1872 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1873                                         u32 cid, u8 vfid,
1874                                         enum protocol_type *p_type,
1875                                         struct ecore_cid_acquired_map **pp_map)
1876 {
1877         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1878         u32 rel_cid;
1879
1880         /* Iterate over protocols and find matching cid range */
1881         for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
1882                 if (vfid == ECORE_CXT_PF_CID)
1883                         *pp_map = &p_mngr->acquired[*p_type];
1884                 else
1885                         *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
1886
1887                 if (!((*pp_map)->cid_map))
1888                         continue;
1889                 if (cid >= (*pp_map)->start_cid &&
1890                     cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
1891                         break;
1892                 }
1893         }
1894         if (*p_type == MAX_CONN_TYPES) {
1895                 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
1896                 goto fail;
1897         }
1898
1899         rel_cid = cid - (*pp_map)->start_cid;
1900         if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
1901                 DP_NOTICE(p_hwfn, true,
1902                           "CID %d [vifd %02x] not acquired", cid, vfid);
1903                 goto fail;
1904         }
1905
1906         return true;
1907 fail:
1908         *p_type = MAX_CONN_TYPES;
1909         *pp_map = OSAL_NULL;
1910         return false;
1911 }
1912
1913 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
1914 {
1915         u32 rel_cid, max_num_vfs = NUM_OF_VFS(p_hwfn->p_dev);
1916         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1917         enum protocol_type type;
1918         bool b_acquired;
1919
1920         if (vfid != ECORE_CXT_PF_CID && vfid > max_num_vfs) {
1921                 DP_NOTICE(p_hwfn, true,
1922                           "Trying to return incorrect CID belonging to VF %02x\n",
1923                           vfid);
1924                 return;
1925         }
1926
1927         /* Test acquired and find matching per-protocol map */
1928         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
1929                                                  &type, &p_map);
1930
1931         if (!b_acquired)
1932                 return;
1933
1934         rel_cid = cid - p_map->start_cid;
1935         OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
1936
1937         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1938                    "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
1939                    cid, rel_cid, vfid, type);
1940 }
1941
1942 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1943 {
1944         _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
1945 }
1946
1947 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1948                                             struct ecore_cxt_info *p_info)
1949 {
1950         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1951         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
1952         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1953         enum protocol_type type;
1954         bool b_acquired;
1955
1956         /* Test acquired and find matching per-protocol map */
1957         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
1958                                                  ECORE_CXT_PF_CID,
1959                                                  &type, &p_map);
1960
1961         if (!b_acquired)
1962                 return ECORE_INVAL;
1963
1964         /* set the protocl type */
1965         p_info->type = type;
1966
1967         /* compute context virtual pointer */
1968         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1969
1970         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1971         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1972         line = p_info->iid / cxts_per_p;
1973
1974         /* Make sure context is allocated (dynamic allocation) */
1975         if (!p_mngr->ilt_shadow[line].p_virt)
1976                 return ECORE_INVAL;
1977
1978         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1979             p_info->iid % cxts_per_p * conn_cxt_size;
1980
1981         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1982                 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1983                 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1984
1985         return ECORE_SUCCESS;
1986 }
1987
1988 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1989 {
1990         /* Set the number of required CORE connections */
1991         u32 core_cids = 1;      /* SPQ */
1992
1993         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1994
1995         switch (p_hwfn->hw_info.personality) {
1996         case ECORE_PCI_ETH:
1997                 {
1998                 u32 count = 0;
1999
2000                 struct ecore_eth_pf_params *p_params =
2001                             &p_hwfn->pf_params.eth_pf_params;
2002
2003                 if (!p_params->num_vf_cons)
2004                         p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT;
2005                 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2006                                               p_params->num_cons,
2007                                               p_params->num_vf_cons);
2008
2009                 count = p_params->num_arfs_filters;
2010
2011                 if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS,
2012                                    &p_hwfn->p_dev->mf_bits))
2013                         p_hwfn->p_cxt_mngr->arfs_count = count;
2014
2015                 break;
2016                 }
2017         default:
2018                 return ECORE_INVAL;
2019         }
2020
2021         return ECORE_SUCCESS;
2022 }
2023
2024 /* This function is very RoCE oriented, if another protocol in the future
2025  * will want this feature we'll need to modify the function to be more generic
2026  */
2027 enum _ecore_status_t
2028 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2029                             enum ecore_cxt_elem_type elem_type,
2030                             u32 iid)
2031 {
2032         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2033         struct ecore_ilt_client_cfg *p_cli;
2034         struct ecore_ilt_cli_blk *p_blk;
2035         struct ecore_ptt *p_ptt;
2036         dma_addr_t p_phys;
2037         u64 ilt_hw_entry;
2038         void *p_virt;
2039         enum _ecore_status_t rc = ECORE_SUCCESS;
2040
2041         switch (elem_type) {
2042         case ECORE_ELEM_CXT:
2043                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2044                 elem_size = CONN_CXT_SIZE(p_hwfn);
2045                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2046                 break;
2047         case ECORE_ELEM_SRQ:
2048                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2049                 elem_size = SRQ_CXT_SIZE;
2050                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2051                 break;
2052         case ECORE_ELEM_TASK:
2053                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2054                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2055                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2056                 break;
2057         default:
2058                 DP_NOTICE(p_hwfn, false,
2059                           "ECORE_INVALID elem type = %d", elem_type);
2060                 return ECORE_INVAL;
2061         }
2062
2063         /* Calculate line in ilt */
2064         hw_p_size = p_cli->p_size.val;
2065         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2066         line = p_blk->start_line + (iid / elems_per_p);
2067         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2068
2069         /* If line is already allocated, do nothing, otherwise allocate it and
2070          * write it to the PSWRQ2 registers.
2071          * This section can be run in parallel from different contexts and thus
2072          * a mutex protection is needed.
2073          */
2074
2075         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2076
2077         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2078                 goto out0;
2079
2080         p_ptt = ecore_ptt_acquire(p_hwfn);
2081         if (!p_ptt) {
2082                 DP_NOTICE(p_hwfn, false,
2083                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2084                 rc = ECORE_TIMEOUT;
2085                 goto out0;
2086         }
2087
2088         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2089                                          &p_phys,
2090                                          p_blk->real_size_in_page);
2091         if (!p_virt) {
2092                 rc = ECORE_NOMEM;
2093                 goto out1;
2094         }
2095         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2096
2097         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2098         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2099         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2100                 p_blk->real_size_in_page;
2101
2102         /* compute absolute offset */
2103         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2104                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2105
2106         ilt_hw_entry = 0;
2107         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2108         SET_FIELD(ilt_hw_entry,
2109                   ILT_ENTRY_PHY_ADDR,
2110                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2111
2112 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2113
2114         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2115                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2116                             OSAL_NULL /* default parameters */);
2117
2118         if (elem_type == ECORE_ELEM_CXT) {
2119                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2120                                          elems_per_p;
2121
2122                 /* Update the relevant register in the parser */
2123                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2124                          last_cid_allocated - 1);
2125
2126                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2127                         /* Enable RoCE search */
2128                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2129                         p_hwfn->b_rdma_enabled_in_prs = true;
2130                 }
2131         }
2132
2133 out1:
2134         ecore_ptt_release(p_hwfn, p_ptt);
2135 out0:
2136         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2137
2138         return rc;
2139 }
2140
2141 /* This function is very RoCE oriented, if another protocol in the future
2142  * will want this feature we'll need to modify the function to be more generic
2143  */
2144 static enum _ecore_status_t
2145 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2146                          enum ecore_cxt_elem_type elem_type,
2147                          u32 start_iid, u32 count)
2148 {
2149         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2150         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2151         struct ecore_ilt_client_cfg *p_cli;
2152         struct ecore_ilt_cli_blk *p_blk;
2153         u32 end_iid = start_iid + count;
2154         struct ecore_ptt *p_ptt;
2155         u64 ilt_hw_entry = 0;
2156         u32 i;
2157
2158         switch (elem_type) {
2159         case ECORE_ELEM_CXT:
2160                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2161                 elem_size = CONN_CXT_SIZE(p_hwfn);
2162                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2163                 break;
2164         case ECORE_ELEM_SRQ:
2165                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2166                 elem_size = SRQ_CXT_SIZE;
2167                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2168                 break;
2169         case ECORE_ELEM_TASK:
2170                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2171                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2172                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2173                 break;
2174         default:
2175                 DP_NOTICE(p_hwfn, false,
2176                           "ECORE_INVALID elem type = %d", elem_type);
2177                 return ECORE_INVAL;
2178         }
2179
2180         /* Calculate line in ilt */
2181         hw_p_size = p_cli->p_size.val;
2182         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2183         start_line = p_blk->start_line + (start_iid / elems_per_p);
2184         end_line = p_blk->start_line + (end_iid / elems_per_p);
2185         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2186                 end_line--;
2187
2188         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2189         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2190
2191         p_ptt = ecore_ptt_acquire(p_hwfn);
2192         if (!p_ptt) {
2193                 DP_NOTICE(p_hwfn, false,
2194                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2195                 return ECORE_TIMEOUT;
2196         }
2197
2198         for (i = shadow_start_line; i < shadow_end_line; i++) {
2199                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2200                         continue;
2201
2202                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2203                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2204                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2205                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2206
2207                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2208                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2209                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2210
2211                 /* compute absolute offset */
2212                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2213                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2214                      ILT_ENTRY_IN_REGS);
2215
2216                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2217                  * wide-bus.
2218                  */
2219                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2220                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2221                                     reg_offset,
2222                                     sizeof(ilt_hw_entry) / sizeof(u32),
2223                                     OSAL_NULL /* default parameters */);
2224         }
2225
2226         ecore_ptt_release(p_hwfn, p_ptt);
2227
2228         return ECORE_SUCCESS;
2229 }