drivers/net/qede/base/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_hsi_common.h"
  12 #include "ecore_hsi_eth.h"
  13 #include "ecore_rt_defs.h"
  14 #include "ecore_status.h"
  15 #include "ecore.h"
  16 #include "ecore_init_ops.h"
  17 #include "ecore_init_fw_funcs.h"
  18 #include "ecore_cxt.h"
  19 #include "ecore_hw.h"
  20 #include "ecore_dev_api.h"
  21 #include "ecore_sriov.h"
  22
  23 /* Max number of connection types in HW (DQ/CDU etc.) */
  24 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  25 #define NUM_TASK_TYPES          2
  26 #define NUM_TASK_PF_SEGMENTS    4
  27 #define NUM_TASK_VF_SEGMENTS    1
  28
  29 /* Doorbell-Queue constants */
  30 #define DQ_RANGE_SHIFT  4
  31 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  32
  33 /* Searcher constants */
  34 #define SRC_MIN_NUM_ELEMS 256
  35
  36 /* Timers constants */
  37 #define TM_SHIFT        7
  38 #define TM_ALIGN        (1 << TM_SHIFT)
  39 #define TM_ELEM_SIZE    4
  40
  41 /* ILT constants */
  42 /* If for some reason, HW P size is modified to be less than 32K,
  43  * special handling needs to be made for CDU initialization
  44  */
  45 #define ILT_DEFAULT_HW_P_SIZE   3
  46
  47 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  48 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  49
  50 /* ILT entry structure */
  51 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  52 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  53 #define ILT_ENTRY_VALID_MASK            0x1ULL
  54 #define ILT_ENTRY_VALID_SHIFT           52
  55 #define ILT_ENTRY_IN_REGS               2
  56 #define ILT_REG_SIZE_IN_BYTES           4
  57
  58 /* connection context union */
  59 union conn_context {
  60         struct core_conn_context core_ctx;
  61         struct eth_conn_context eth_ctx;
  62 };
  63
  64 /* TYPE-0 task context - iSCSI, FCOE */
  65 union type0_task_context {
  66 };
  67
  68 /* TYPE-1 task context - ROCE */
  69 union type1_task_context {
  70 };
  71
  72 struct src_ent {
  73         u8 opaque[56];
  74         u64 next;
  75 };
  76
  77 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  78 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  79
  80 #define CONN_CXT_SIZE(p_hwfn) \
  81         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  82
  83 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
  84
  85 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  86         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  87
  88 /* Alignment is inherent to the type1_task_context structure */
  89 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
  90
  91 /* PF per protocl configuration object */
  92 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
  93 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
  94
  95 struct ecore_tid_seg {
  96         u32 count;
  97         u8 type;
  98         bool has_fl_mem;
  99 };
 100
 101 struct ecore_conn_type_cfg {
 102         u32 cid_count;
 103         u32 cid_start;
 104         u32 cids_per_vf;
 105         struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
 106 };
 107
 108 /* ILT Client configuration,
 109  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 110  * 1 - for connection context (CDUC) and for each task context we need two
 111  * values, for regular task context and for force load memory
 112  */
 113 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 114 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 115 #define CDUC_BLK                (0)
 116 #define SRQ_BLK                 (0)
 117 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 118 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 119
 120 enum ilt_clients {
 121         ILT_CLI_CDUC,
 122         ILT_CLI_CDUT,
 123         ILT_CLI_QM,
 124         ILT_CLI_TM,
 125         ILT_CLI_SRC,
 126         ILT_CLI_TSDM,
 127         ILT_CLI_MAX
 128 };
 129
 130 struct ilt_cfg_pair {
 131         u32 reg;
 132         u32 val;
 133 };
 134
 135 struct ecore_ilt_cli_blk {
 136         u32 total_size;         /* 0 means not active */
 137         u32 real_size_in_page;
 138         u32 start_line;
 139         u32 dynamic_line_cnt;
 140 };
 141
 142 struct ecore_ilt_client_cfg {
 143         bool active;
 144
 145         /* ILT boundaries */
 146         struct ilt_cfg_pair first;
 147         struct ilt_cfg_pair last;
 148         struct ilt_cfg_pair p_size;
 149
 150         /* ILT client blocks for PF */
 151         struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 152         u32 pf_total_lines;
 153
 154         /* ILT client blocks for VFs */
 155         struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 156         u32 vf_total_lines;
 157 };
 158
 159 /* Per Path -
 160  *      ILT shadow table
 161  *      Protocol acquired CID lists
 162  *      PF start line in ILT
 163  */
 164 struct ecore_dma_mem {
 165         dma_addr_t p_phys;
 166         void *p_virt;
 167         osal_size_t size;
 168 };
 169
 170 #define MAP_WORD_SIZE           sizeof(unsigned long)
 171 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 172
 173 struct ecore_cid_acquired_map {
 174         u32 start_cid;
 175         u32 max_count;
 176         unsigned long *cid_map;
 177 };
 178
 179 struct ecore_cxt_mngr {
 180         /* Per protocl configuration */
 181         struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
 182
 183         /* computed ILT structure */
 184         struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
 185
 186         /* Task type sizes */
 187         u32 task_type_size[NUM_TASK_TYPES];
 188
 189         /* total number of VFs for this hwfn -
 190          * ALL VFs are symmetric in terms of HW resources
 191          */
 192         u32 vf_count;
 193
 194         /* total number of SRQ's for this hwfn */
 195         u32                             srq_count;
 196
 197         /* Acquired CIDs */
 198         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 199
 200         /* ILT  shadow table */
 201         struct ecore_dma_mem *ilt_shadow;
 202         u32 pf_start_line;
 203
 204         /* Mutex for a dynamic ILT allocation */
 205         osal_mutex_t mutex;
 206
 207         /* SRC T2 */
 208         struct ecore_dma_mem *t2;
 209         u32 t2_num_pages;
 210         u64 first_free;
 211         u64 last_free;
 212 };
 213
 214 /* check if resources/configuration is required according to protocol type */
 215 static OSAL_INLINE bool src_proto(enum protocol_type type)
 216 {
 217         return type == PROTOCOLID_TOE;
 218 }
 219
 220 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
 221 {
 222         return type == PROTOCOLID_TOE;
 223 }
 224
 225 static bool tm_tid_proto(enum protocol_type type)
 226 {
 227         return type == PROTOCOLID_FCOE;
 228 }
 229
 230 /* counts the iids for the CDU/CDUC ILT client configuration */
 231 struct ecore_cdu_iids {
 232         u32 pf_cids;
 233         u32 per_vf_cids;
 234 };
 235
 236 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
 237                                struct ecore_cdu_iids *iids)
 238 {
 239         u32 type;
 240
 241         for (type = 0; type < MAX_CONN_TYPES; type++) {
 242                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 243                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 244         }
 245 }
 246
 247 /* counts the iids for the Searcher block configuration */
 248 struct ecore_src_iids {
 249         u32 pf_cids;
 250         u32 per_vf_cids;
 251 };
 252
 253 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
 254                                            struct ecore_src_iids *iids)
 255 {
 256         u32 i;
 257
 258         for (i = 0; i < MAX_CONN_TYPES; i++) {
 259                 if (!src_proto(i))
 260                         continue;
 261
 262                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 263                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 264         }
 265 }
 266
 267 /* counts the iids for the Timers block configuration */
 268 struct ecore_tm_iids {
 269         u32 pf_cids;
 270         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 271         u32 pf_tids_total;
 272         u32 per_vf_cids;
 273         u32 per_vf_tids;
 274 };
 275
 276 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 277                                           struct ecore_tm_iids *iids)
 278 {
 279         u32 i, j;
 280
 281         for (i = 0; i < MAX_CONN_TYPES; i++) {
 282                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 283
 284                 if (tm_cid_proto(i)) {
 285                         iids->pf_cids += p_cfg->cid_count;
 286                         iids->per_vf_cids += p_cfg->cids_per_vf;
 287                 }
 288
 289                 if (tm_tid_proto(i)) {
 290                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 291
 292                         /* for each segment there is at most one
 293                          * protocol for which count is not 0.
 294                          */
 295                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 296                                 iids->pf_tids[j] += segs[j].count;
 297
 298                         /* The last array elelment is for the VFs. As for PF
 299                          * segments there can be only one protocol for
 300                          * which this value is not 0.
 301                          */
 302                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 303                 }
 304         }
 305
 306         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 307         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 308         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 309
 310         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 311                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 312                 iids->pf_tids_total += iids->pf_tids[j];
 313         }
 314 }
 315
 316 void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
 317 {
 318         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 319         struct ecore_tid_seg *segs;
 320         u32 vf_cids = 0, type, j;
 321         u32 vf_tids = 0;
 322
 323         for (type = 0; type < MAX_CONN_TYPES; type++) {
 324                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 325                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 326
 327                 segs = p_mngr->conn_cfg[type].tid_seg;
 328                 /* for each segment there is at most one
 329                  * protocol for which count is not 0.
 330                  */
 331                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 332                         iids->tids += segs[j].count;
 333
 334                 /* The last array elelment is for the VFs. As for PF
 335                  * segments there can be only one protocol for
 336                  * which this value is not 0.
 337                  */
 338                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 339         }
 340
 341         iids->vf_cids += vf_cids * p_mngr->vf_count;
 342         iids->tids += vf_tids * p_mngr->vf_count;
 343
 344         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 345                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 346                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 347 }
 348
 349 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
 350                                                     u32 seg)
 351 {
 352         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 353         u32 i;
 354
 355         /* Find the protocol with tid count > 0 for this segment.
 356          * Note: there can only be one and this is already validated.
 357          */
 358         for (i = 0; i < MAX_CONN_TYPES; i++) {
 359                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 360                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 361         }
 362         return OSAL_NULL;
 363 }
 364
 365 /* set the iids (cid/tid) count per protocol */
 366 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 367                                    enum protocol_type type,
 368                                    u32 cid_count, u32 vf_cid_cnt)
 369 {
 370         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 371         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 372
 373         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 374         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 375 }
 376
 377 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
 378                                   enum protocol_type type, u32 *vf_cid)
 379 {
 380         if (vf_cid)
 381                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 382
 383         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 384 }
 385
 386 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
 387                                   enum protocol_type type)
 388 {
 389         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 390 }
 391
 392 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 393                                          enum protocol_type type)
 394 {
 395         u32 cnt = 0;
 396         int i;
 397
 398         for (i = 0; i < TASK_SEGMENTS; i++)
 399                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 400
 401         return cnt;
 402 }
 403
 404 static OSAL_INLINE void
 405 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 406                               enum protocol_type proto,
 407                               u8 seg, u8 seg_type, u32 count, bool has_fl)
 408 {
 409         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 410         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 411
 412         p_seg->count = count;
 413         p_seg->has_fl_mem = has_fl;
 414         p_seg->type = seg_type;
 415 }
 416
 417 /* the *p_line parameter must be either 0 for the first invocation or the
 418  * value returned in the previous invocation.
 419  */
 420 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
 421                                    struct ecore_ilt_cli_blk *p_blk,
 422                                    u32 start_line,
 423                                    u32 total_size, u32 elem_size)
 424 {
 425         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 426
 427         /* verify that it's called once for each block */
 428         if (p_blk->total_size)
 429                 return;
 430
 431         p_blk->total_size = total_size;
 432         p_blk->real_size_in_page = 0;
 433         if (elem_size)
 434                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 435         p_blk->start_line = start_line;
 436 }
 437
 438 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
 439                                    struct ecore_ilt_client_cfg *p_cli,
 440                                    struct ecore_ilt_cli_blk *p_blk,
 441                                    u32 *p_line, enum ilt_clients client_id)
 442 {
 443         if (!p_blk->total_size)
 444                 return;
 445
 446         if (!p_cli->active)
 447                 p_cli->first.val = *p_line;
 448
 449         p_cli->active = true;
 450         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 451         p_cli->last.val = *p_line - 1;
 452
 453         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 454                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
 455                    " [Real %08x] Start line %d\n",
 456                    client_id, p_cli->first.val, p_cli->last.val,
 457                    p_blk->total_size, p_blk->real_size_in_page,
 458                    p_blk->start_line);
 459 }
 460
 461 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 462                                           enum ilt_clients ilt_client)
 463 {
 464         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 465         struct ecore_ilt_client_cfg *p_cli;
 466         u32 lines_to_skip = 0;
 467         u32 cxts_per_p;
 468
 469         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 470
 471         if (ilt_client == ILT_CLI_CDUC) {
 472                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 473
 474                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 475                     (u32)CONN_CXT_SIZE(p_hwfn);
 476
 477                 lines_to_skip = cid_count / cxts_per_p;
 478         }
 479
 480         return lines_to_skip;
 481 }
 482
 483 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
 484 {
 485         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 486         u32 curr_line, total, i, task_size, line;
 487         struct ecore_ilt_client_cfg *p_cli;
 488         struct ecore_ilt_cli_blk *p_blk;
 489         struct ecore_cdu_iids cdu_iids;
 490         struct ecore_src_iids src_iids;
 491         struct ecore_qm_iids qm_iids;
 492         struct ecore_tm_iids tm_iids;
 493         struct ecore_tid_seg *p_seg;
 494
 495         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 496         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 497         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 498         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 499
 500         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 501
 502         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 503                    "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
 504                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 505
 506         /* CDUC */
 507         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 508
 509         curr_line = p_mngr->pf_start_line;
 510
 511         /* CDUC PF */
 512         p_cli->pf_total_lines = 0;
 513
 514         /* get the counters for the CDUC,CDUC and QM clients  */
 515         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 516
 517         p_blk = &p_cli->pf_blks[CDUC_BLK];
 518
 519         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 520
 521         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 522                                total, CONN_CXT_SIZE(p_hwfn));
 523
 524         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 525         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 526
 527         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 528                                                                  ILT_CLI_CDUC);
 529
 530         /* CDUC VF */
 531         p_blk = &p_cli->vf_blks[CDUC_BLK];
 532         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 533
 534         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 535                                total, CONN_CXT_SIZE(p_hwfn));
 536
 537         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 538         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 539
 540         for (i = 1; i < p_mngr->vf_count; i++)
 541                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 542                                        ILT_CLI_CDUC);
 543
 544         /* CDUT PF */
 545         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 546         p_cli->first.val = curr_line;
 547
 548         /* first the 'working' task memory */
 549         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 550                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 551                 if (!p_seg || p_seg->count == 0)
 552                         continue;
 553
 554                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 555                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 556                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 557                                        p_mngr->task_type_size[p_seg->type]);
 558
 559                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 560                                        ILT_CLI_CDUT);
 561         }
 562
 563         /* next the 'init' task memory (forced load memory) */
 564         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 565                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 566                 if (!p_seg || p_seg->count == 0)
 567                         continue;
 568
 569                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 570
 571                 if (!p_seg->has_fl_mem) {
 572                         /* The segment is active (total size pf 'working'
 573                          * memory is > 0) but has no FL (forced-load, Init)
 574                          * memory. Thus:
 575                          *
 576                          * 1.   The total-size in the corrsponding FL block of
 577                          *      the ILT client is set to 0 - No ILT line are
 578                          *      provisioned and no ILT memory allocated.
 579                          *
 580                          * 2.   The start-line of said block is set to the
 581                          *      start line of the matching working memory
 582                          *      block in the ILT client. This is later used to
 583                          *      configure the CDU segment offset registers and
 584                          *      results in an FL command for TIDs of this
 585                          *      segment behaves as regular load commands
 586                          *      (loading TIDs from the working memory).
 587                          */
 588                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 589
 590                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 591                         continue;
 592                 }
 593                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 594
 595                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 596                                        curr_line, total,
 597                                        p_mngr->task_type_size[p_seg->type]);
 598
 599                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 600                                        ILT_CLI_CDUT);
 601         }
 602         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 603
 604         /* CDUT VF */
 605         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 606         if (p_seg && p_seg->count) {
 607                 /* Stricly speaking we need to iterate over all VF
 608                  * task segment types, but a VF has only 1 segment
 609                  */
 610
 611                 /* 'working' memory */
 612                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 613
 614                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 615                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 616                                        curr_line, total,
 617                                        p_mngr->task_type_size[p_seg->type]);
 618
 619                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 620                                        ILT_CLI_CDUT);
 621
 622                 /* 'init' memory */
 623                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 624                 if (!p_seg->has_fl_mem) {
 625                         /* see comment above */
 626                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 627                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 628                 } else {
 629                         task_size = p_mngr->task_type_size[p_seg->type];
 630                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 631                                                curr_line, total, task_size);
 632                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 633                                                ILT_CLI_CDUT);
 634                 }
 635                 p_cli->vf_total_lines = curr_line -
 636                     p_cli->vf_blks[0].start_line;
 637
 638                 /* Now for the rest of the VFs */
 639                 for (i = 1; i < p_mngr->vf_count; i++) {
 640                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 641                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 642                                                ILT_CLI_CDUT);
 643
 644                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 645                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 646                                                ILT_CLI_CDUT);
 647                 }
 648         }
 649
 650         /* QM */
 651         p_cli = &p_mngr->clients[ILT_CLI_QM];
 652         p_blk = &p_cli->pf_blks[0];
 653
 654         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 655         total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 656                                      qm_iids.vf_cids, qm_iids.tids,
 657                                      p_hwfn->qm_info.num_pqs,
 658                                      p_hwfn->qm_info.num_vf_pqs);
 659
 660         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 661                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
 662                    " num_vf_pqs=%d, memory_size=%d)\n",
 663                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 664                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 665
 666         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 667                                QM_PQ_ELEMENT_SIZE);
 668
 669         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 670         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 671
 672         /* SRC */
 673         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 674         ecore_cxt_src_iids(p_mngr, &src_iids);
 675
 676         /* Both the PF and VFs searcher connections are stored in the per PF
 677          * database. Thus sum the PF searcher cids and all the VFs searcher
 678          * cids.
 679          */
 680         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 681         if (total) {
 682                 u32 local_max = OSAL_MAX_T(u32, total,
 683                                            SRC_MIN_NUM_ELEMS);
 684
 685                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 686
 687                 p_blk = &p_cli->pf_blks[0];
 688                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 689                                        total * sizeof(struct src_ent),
 690                                        sizeof(struct src_ent));
 691
 692                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 693                                        ILT_CLI_SRC);
 694                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 695         }
 696
 697         /* TM PF */
 698         p_cli = &p_mngr->clients[ILT_CLI_TM];
 699         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 700         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 701         if (total) {
 702                 p_blk = &p_cli->pf_blks[0];
 703                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 704                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 705
 706                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 707                                        ILT_CLI_TM);
 708                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 709         }
 710
 711         /* TM VF */
 712         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 713         if (total) {
 714                 p_blk = &p_cli->vf_blks[0];
 715                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 716                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 717
 718                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 719                                        ILT_CLI_TM);
 720
 721                 for (i = 1; i < p_mngr->vf_count; i++) {
 722                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 723                                                ILT_CLI_TM);
 724                 }
 725
 726                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 727         }
 728
 729         /* TSDM (SRQ CONTEXT) */
 730         total = ecore_cxt_get_srq_count(p_hwfn);
 731
 732         if (total) {
 733                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 734                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 735                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 736                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 737
 738                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 739                                        ILT_CLI_TSDM);
 740                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 741         }
 742
 743         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 744             RESC_NUM(p_hwfn, ECORE_ILT)) {
 745                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 746                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 747                 return ECORE_INVAL;
 748         }
 749
 750         return ECORE_SUCCESS;
 751 }
 752
 753 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 754 {
 755         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 756         u32 i;
 757
 758         if (!p_mngr->t2)
 759                 return;
 760
 761         for (i = 0; i < p_mngr->t2_num_pages; i++)
 762                 if (p_mngr->t2[i].p_virt)
 763                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 764                                                p_mngr->t2[i].p_virt,
 765                                                p_mngr->t2[i].p_phys,
 766                                                p_mngr->t2[i].size);
 767
 768         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 769 }
 770
 771 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 772 {
 773         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 774         u32 conn_num, total_size, ent_per_page, psz, i;
 775         struct ecore_ilt_client_cfg *p_src;
 776         struct ecore_src_iids src_iids;
 777         struct ecore_dma_mem *p_t2;
 778         enum _ecore_status_t rc;
 779
 780         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 781
 782         /* if the SRC ILT client is inactive - there are no connection
 783          * requiring the searcer, leave.
 784          */
 785         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 786         if (!p_src->active)
 787                 return ECORE_SUCCESS;
 788
 789         ecore_cxt_src_iids(p_mngr, &src_iids);
 790         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 791         total_size = conn_num * sizeof(struct src_ent);
 792
 793         /* use the same page size as the SRC ILT client */
 794         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 795         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 796
 797         /* allocate t2 */
 798         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 799                                  p_mngr->t2_num_pages *
 800                                  sizeof(struct ecore_dma_mem));
 801         if (!p_mngr->t2) {
 802                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 803                 rc = ECORE_NOMEM;
 804                 goto t2_fail;
 805         }
 806
 807         /* allocate t2 pages */
 808         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 809                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 810                 void **p_virt = &p_mngr->t2[i].p_virt;
 811
 812                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 813                                                   &p_mngr->t2[i].p_phys, size);
 814                 if (!p_mngr->t2[i].p_virt) {
 815                         rc = ECORE_NOMEM;
 816                         goto t2_fail;
 817                 }
 818                 OSAL_MEM_ZERO(*p_virt, size);
 819                 p_mngr->t2[i].size = size;
 820                 total_size -= size;
 821         }
 822
 823         /* Set the t2 pointers */
 824
 825         /* entries per page - must be a power of two */
 826         ent_per_page = psz / sizeof(struct src_ent);
 827
 828         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 829
 830         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 831         p_mngr->last_free = (u64)p_t2->p_phys +
 832             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 833
 834         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 835                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
 836                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 837                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
 838                 u32 j;
 839
 840                 for (j = 0; j < ent_num - 1; j++) {
 841                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 842                         entries[j].next = OSAL_CPU_TO_BE64(val);
 843                 }
 844
 845                 if (i < p_mngr->t2_num_pages - 1)
 846                         val = (u64)p_mngr->t2[i + 1].p_phys;
 847                 else
 848                         val = 0;
 849                 entries[j].next = OSAL_CPU_TO_BE64(val);
 850
 851                 conn_num -= ent_num;
 852         }
 853
 854         return ECORE_SUCCESS;
 855
 856 t2_fail:
 857         ecore_cxt_src_t2_free(p_hwfn);
 858         return rc;
 859 }
 860
 861 #define for_each_ilt_valid_client(pos, clients)         \
 862         for (pos = 0; pos < ILT_CLI_MAX; pos++)         \
 863                 if (!clients[pos].active) {             \
 864                         continue;                       \
 865                 } else                                  \
 866
 867
 868 /* Total number of ILT lines used by this PF */
 869 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
 870 {
 871         u32 size = 0;
 872         u32 i;
 873
 874         for_each_ilt_valid_client(i, ilt_clients)
 875                 size += (ilt_clients[i].last.val -
 876                          ilt_clients[i].first.val + 1);
 877
 878         return size;
 879 }
 880
 881 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
 882 {
 883         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 884         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 885         u32 ilt_size, i;
 886
 887         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
 888
 889         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 890                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 891
 892                 if (p_dma->p_virt)
 893                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 894                                                p_dma->p_virt,
 895                                                p_dma->p_phys, p_dma->size);
 896                 p_dma->p_virt = OSAL_NULL;
 897         }
 898         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
 899 }
 900
 901 static enum _ecore_status_t
 902 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
 903                     struct ecore_ilt_cli_blk *p_blk,
 904                     enum ilt_clients ilt_client, u32 start_line_offset)
 905 {
 906         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 907         u32 lines, line, sz_left, lines_to_skip = 0;
 908
 909         /* Special handling for RoCE that supports dynamic allocation */
 910         if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
 911                 return ECORE_SUCCESS;
 912
 913         lines_to_skip = p_blk->dynamic_line_cnt;
 914
 915         if (!p_blk->total_size)
 916                 return ECORE_SUCCESS;
 917
 918         sz_left = p_blk->total_size;
 919         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 920         line = p_blk->start_line + start_line_offset -
 921             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 922
 923         for (; lines; lines--) {
 924                 dma_addr_t p_phys;
 925                 void *p_virt;
 926                 u32 size;
 927
 928                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
 929
 930 /* @DPDK */
 931 #define ILT_BLOCK_ALIGN_SIZE 0x1000
 932                 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
 933                                                          &p_phys, size,
 934                                                          ILT_BLOCK_ALIGN_SIZE);
 935                 if (!p_virt)
 936                         return ECORE_NOMEM;
 937                 OSAL_MEM_ZERO(p_virt, size);
 938
 939                 ilt_shadow[line].p_phys = p_phys;
 940                 ilt_shadow[line].p_virt = p_virt;
 941                 ilt_shadow[line].size = size;
 942
 943                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 944                            "ILT shadow: Line [%d] Physical 0x%lx"
 945                            " Virtual %p Size %d\n",
 946                            line, (unsigned long)p_phys, p_virt, size);
 947
 948                 sz_left -= size;
 949                 line++;
 950         }
 951
 952         return ECORE_SUCCESS;
 953 }
 954
 955 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
 956 {
 957         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 958         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
 959         struct ecore_ilt_cli_blk *p_blk;
 960         u32 size, i, j, k;
 961         enum _ecore_status_t rc;
 962
 963         size = ecore_cxt_ilt_shadow_size(clients);
 964         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 965                                          size * sizeof(struct ecore_dma_mem));
 966
 967         if (!p_mngr->ilt_shadow) {
 968                 DP_NOTICE(p_hwfn, true,
 969                           "Failed to allocate ilt shadow table\n");
 970                 rc = ECORE_NOMEM;
 971                 goto ilt_shadow_fail;
 972         }
 973
 974         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 975                    "Allocated 0x%x bytes for ilt shadow\n",
 976                    (u32)(size * sizeof(struct ecore_dma_mem)));
 977
 978         for_each_ilt_valid_client(i, clients) {
 979                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
 980                         p_blk = &clients[i].pf_blks[j];
 981                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
 982                         if (rc != ECORE_SUCCESS)
 983                                 goto ilt_shadow_fail;
 984                 }
 985                 for (k = 0; k < p_mngr->vf_count; k++) {
 986                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
 987                                 u32 lines = clients[i].vf_total_lines * k;
 988
 989                                 p_blk = &clients[i].vf_blks[j];
 990                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
 991                                                          i, lines);
 992                                 if (rc != ECORE_SUCCESS)
 993                                         goto ilt_shadow_fail;
 994                         }
 995                 }
 996         }
 997
 998         return ECORE_SUCCESS;
 999
1000 ilt_shadow_fail:
1001         ecore_ilt_shadow_free(p_hwfn);
1002         return rc;
1003 }
1004
1005 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1006 {
1007         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1008         u32 type;
1009
1010         for (type = 0; type < MAX_CONN_TYPES; type++) {
1011                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1012                 p_mngr->acquired[type].max_count = 0;
1013                 p_mngr->acquired[type].start_cid = 0;
1014         }
1015 }
1016
1017 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1018 {
1019         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1020         u32 start_cid = 0;
1021         u32 type;
1022
1023         for (type = 0; type < MAX_CONN_TYPES; type++) {
1024                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1025                 u32 size;
1026
1027                 if (cid_cnt == 0)
1028                         continue;
1029
1030                 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD);
1031                 p_mngr->acquired[type].cid_map = OSAL_ZALLOC(p_hwfn->p_dev,
1032                                                              GFP_KERNEL, size);
1033                 if (!p_mngr->acquired[type].cid_map)
1034                         goto cid_map_fail;
1035
1036                 p_mngr->acquired[type].max_count = cid_cnt;
1037                 p_mngr->acquired[type].start_cid = start_cid;
1038
1039                 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1040
1041                 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1042                            "Type %08x start: %08x count %08x\n",
1043                            type, p_mngr->acquired[type].start_cid,
1044                            p_mngr->acquired[type].max_count);
1045                 start_cid += cid_cnt;
1046         }
1047
1048         return ECORE_SUCCESS;
1049
1050 cid_map_fail:
1051         ecore_cid_map_free(p_hwfn);
1052         return ECORE_NOMEM;
1053 }
1054
1055 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1056 {
1057         struct ecore_ilt_client_cfg *clients;
1058         struct ecore_cxt_mngr *p_mngr;
1059         u32 i;
1060
1061         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1062         if (!p_mngr) {
1063                 DP_NOTICE(p_hwfn, true,
1064                           "Failed to allocate `struct ecore_cxt_mngr'\n");
1065                 return ECORE_NOMEM;
1066         }
1067
1068         /* Initialize ILT client registers */
1069         clients = p_mngr->clients;
1070         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1071         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1072         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1073
1074         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1075         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1076         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1077
1078         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1079         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1080         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1081
1082         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1083         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1084         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1085
1086         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1087         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1088         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1089
1090         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1091         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1092         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1093
1094         /* default ILT page size for all clients is 32K */
1095         for (i = 0; i < ILT_CLI_MAX; i++)
1096                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1097
1098         /* due to removal of ISCSI/FCoE files union type0_task_context
1099          * task_type_size will be 0. So hardcoded for now.
1100          */
1101         p_mngr->task_type_size[0] = 512; /* @DPDK */
1102         p_mngr->task_type_size[1] = 128; /* @DPDK */
1103
1104         if (p_hwfn->p_dev->p_iov_info)
1105                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1106
1107         /* Initialize the dynamic ILT allocation mutex */
1108         OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1109         OSAL_MUTEX_INIT(&p_mngr->mutex);
1110
1111         /* Set the cxt mangr pointer priori to further allocations */
1112         p_hwfn->p_cxt_mngr = p_mngr;
1113
1114         return ECORE_SUCCESS;
1115 }
1116
1117 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1118 {
1119         enum _ecore_status_t rc;
1120
1121         /* Allocate the ILT shadow table */
1122         rc = ecore_ilt_shadow_alloc(p_hwfn);
1123         if (rc) {
1124                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1125                 goto tables_alloc_fail;
1126         }
1127
1128         /* Allocate the T2  table */
1129         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1130         if (rc) {
1131                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1132                 goto tables_alloc_fail;
1133         }
1134
1135         /* Allocate and initialize the acquired cids bitmaps */
1136         rc = ecore_cid_map_alloc(p_hwfn);
1137         if (rc) {
1138                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1139                 goto tables_alloc_fail;
1140         }
1141
1142         return ECORE_SUCCESS;
1143
1144 tables_alloc_fail:
1145         ecore_cxt_mngr_free(p_hwfn);
1146         return rc;
1147 }
1148
1149 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1150 {
1151         if (!p_hwfn->p_cxt_mngr)
1152                 return;
1153
1154         ecore_cid_map_free(p_hwfn);
1155         ecore_cxt_src_t2_free(p_hwfn);
1156         ecore_ilt_shadow_free(p_hwfn);
1157         OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1158         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1159 }
1160
1161 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1162 {
1163         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1164         int type;
1165
1166         /* Reset acquired cids */
1167         for (type = 0; type < MAX_CONN_TYPES; type++) {
1168                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1169                 u32 i;
1170
1171                 if (cid_cnt == 0)
1172                         continue;
1173
1174                 for (i = 0; i < DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD); i++)
1175                         p_mngr->acquired[type].cid_map[i] = 0;
1176         }
1177 }
1178
1179 /* HW initialization helper (per Block, per phase) */
1180
1181 /* CDU Common */
1182 #define CDUC_CXT_SIZE_SHIFT                                             \
1183         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1184
1185 #define CDUC_CXT_SIZE_MASK                                              \
1186         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1187
1188 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1189         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1190
1191 #define CDUC_BLOCK_WASTE_MASK                                           \
1192         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1193
1194 #define CDUC_NCIB_SHIFT                                                 \
1195         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1196
1197 #define CDUC_NCIB_MASK                                                  \
1198         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1199
1200 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1201         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1202
1203 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1204         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1205         CDUT_TYPE0_CXT_SIZE_SHIFT)
1206
1207 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1208         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1209
1210 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1211         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1212         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1213
1214 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1215         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1216
1217 #define CDUT_TYPE0_NCIB_MASK                                            \
1218         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1219         CDUT_TYPE0_NCIB_SHIFT)
1220
1221 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1222         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1223
1224 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1225         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1226         CDUT_TYPE1_CXT_SIZE_SHIFT)
1227
1228 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1229         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1230
1231 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1232         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1233         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1234
1235 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1236         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1237
1238 #define CDUT_TYPE1_NCIB_MASK                                            \
1239         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1240         CDUT_TYPE1_NCIB_SHIFT)
1241
1242 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1243 {
1244         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1245
1246         /* CDUC - connection configuration */
1247         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1248         cxt_size = CONN_CXT_SIZE(p_hwfn);
1249         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1250         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1251
1252         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1253         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1254         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1255         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1256
1257         /* CDUT - type-0 tasks configuration */
1258         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1259         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1260         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1261         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1262
1263         /* cxt size and block-waste are multipes of 8 */
1264         cdu_params = 0;
1265         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1266         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1267         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1268         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1269
1270         /* CDUT - type-1 tasks configuration */
1271         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1272         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1273         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1274
1275         /* cxt size and block-waste are multipes of 8 */
1276         cdu_params = 0;
1277         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1278         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1279         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1280         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1281 }
1282
1283 /* CDU PF */
1284 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1285 #define CDU_SEG_REG_TYPE_MASK           0x1
1286 #define CDU_SEG_REG_OFFSET_SHIFT        0
1287 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1288
1289 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1290 {
1291         struct ecore_ilt_client_cfg *p_cli;
1292         struct ecore_tid_seg *p_seg;
1293         u32 cdu_seg_params, offset;
1294         int i;
1295
1296         static const u32 rt_type_offset_arr[] = {
1297                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1298                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1299                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1300                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1301         };
1302
1303         static const u32 rt_type_offset_fl_arr[] = {
1304                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1305                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1306                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1307                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1308         };
1309
1310         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1311
1312         /* There are initializations only for CDUT during pf Phase */
1313         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1314                 /* Segment 0 */
1315                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1316                 if (!p_seg)
1317                         continue;
1318
1319                 /* Note: start_line is already adjusted for the CDU
1320                  * segment register granularity, so we just need to
1321                  * divide. Adjustment is implicit as we assume ILT
1322                  * Page size is larger than 32K!
1323                  */
1324                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1325                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1326                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1327
1328                 cdu_seg_params = 0;
1329                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1330                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1331                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1332
1333                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1334                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1335                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1336
1337                 cdu_seg_params = 0;
1338                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1339                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1340                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1341         }
1342 }
1343
1344 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1345 {
1346         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1347         struct ecore_qm_iids iids;
1348
1349         OSAL_MEM_ZERO(&iids, sizeof(iids));
1350         ecore_cxt_qm_iids(p_hwfn, &iids);
1351
1352         ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1353                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1354                             p_hwfn->first_on_engine,
1355                             iids.cids, iids.vf_cids, iids.tids,
1356                             qm_info->start_pq,
1357                             qm_info->num_pqs - qm_info->num_vf_pqs,
1358                             qm_info->num_vf_pqs,
1359                             qm_info->start_vport,
1360                             qm_info->num_vports, qm_info->pf_wfq,
1361                             qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1362                             p_hwfn->qm_info.qm_vport_params);
1363 }
1364
1365 /* CM PF */
1366 static enum _ecore_status_t ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1367 {
1368         union ecore_qm_pq_params pq_params;
1369         u16 pq;
1370
1371         /* XCM pure-LB queue */
1372         OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
1373         pq_params.core.tc = LB_TC;
1374         pq = ecore_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1375         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1376
1377         return ECORE_SUCCESS;
1378 }
1379
1380 /* DQ PF */
1381 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1382 {
1383         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1384         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1385
1386         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1387         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1388
1389         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1390         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1391
1392         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1393         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1394
1395         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1396         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1397
1398         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1399         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1400
1401         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1402         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1403
1404         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1405         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1406
1407         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1408         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1409
1410         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1411         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1412
1413         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1414         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1415
1416         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1417         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1418
1419         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1420         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1421
1422         /* Connection types 6 & 7 are not in use, yet they must be configured
1423          * as the highest possible connection. Not configuring them means the
1424          * defaults will be  used, and with a large number of cids a bug may
1425          * occur, if the defaults will be smaller than dq_pf_max_cid /
1426          * dq_vf_max_cid.
1427          */
1428         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1429         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1430
1431         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1432         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1433 }
1434
1435 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1436 {
1437         struct ecore_ilt_client_cfg *ilt_clients;
1438         int i;
1439
1440         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1441         for_each_ilt_valid_client(i, ilt_clients) {
1442                 STORE_RT_REG(p_hwfn,
1443                              ilt_clients[i].first.reg,
1444                              ilt_clients[i].first.val);
1445                 STORE_RT_REG(p_hwfn,
1446                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1447                 STORE_RT_REG(p_hwfn,
1448                              ilt_clients[i].p_size.reg,
1449                              ilt_clients[i].p_size.val);
1450         }
1451 }
1452
1453 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1454 {
1455         struct ecore_ilt_client_cfg *p_cli;
1456         u32 blk_factor;
1457
1458         /* For simplicty  we set the 'block' to be an ILT page */
1459         if (p_hwfn->p_dev->p_iov_info) {
1460                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1461
1462                 STORE_RT_REG(p_hwfn,
1463                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1464                              p_iov->first_vf_in_pf);
1465                 STORE_RT_REG(p_hwfn,
1466                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1467                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1468         }
1469
1470         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1471         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1472         if (p_cli->active) {
1473                 STORE_RT_REG(p_hwfn,
1474                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1475                              blk_factor);
1476                 STORE_RT_REG(p_hwfn,
1477                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1478                              p_cli->pf_total_lines);
1479                 STORE_RT_REG(p_hwfn,
1480                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1481                              p_cli->vf_total_lines);
1482         }
1483
1484         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1485         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1486         if (p_cli->active) {
1487                 STORE_RT_REG(p_hwfn,
1488                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1489                              blk_factor);
1490                 STORE_RT_REG(p_hwfn,
1491                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1492                              p_cli->pf_total_lines);
1493                 STORE_RT_REG(p_hwfn,
1494                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1495                              p_cli->vf_total_lines);
1496         }
1497
1498         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1499         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1500         if (p_cli->active) {
1501                 STORE_RT_REG(p_hwfn,
1502                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1503                 STORE_RT_REG(p_hwfn,
1504                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1505                              p_cli->pf_total_lines);
1506                 STORE_RT_REG(p_hwfn,
1507                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1508                              p_cli->vf_total_lines);
1509         }
1510 }
1511
1512 /* ILT (PSWRQ2) PF */
1513 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1514 {
1515         struct ecore_ilt_client_cfg *clients;
1516         struct ecore_cxt_mngr *p_mngr;
1517         struct ecore_dma_mem *p_shdw;
1518         u32 line, rt_offst, i;
1519
1520         ecore_ilt_bounds_init(p_hwfn);
1521         ecore_ilt_vf_bounds_init(p_hwfn);
1522
1523         p_mngr = p_hwfn->p_cxt_mngr;
1524         p_shdw = p_mngr->ilt_shadow;
1525         clients = p_hwfn->p_cxt_mngr->clients;
1526
1527         for_each_ilt_valid_client(i, clients) {
1528                 /* Client's 1st val and RT array are absolute, ILT shadows'
1529                  * lines are relative.
1530                  */
1531                 line = clients[i].first.val - p_mngr->pf_start_line;
1532                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1533                     clients[i].first.val * ILT_ENTRY_IN_REGS;
1534
1535                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1536                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1537                         u64 ilt_hw_entry = 0;
1538
1539                         /** p_virt could be OSAL_NULL incase of dynamic
1540                          *  allocation
1541                          */
1542                         if (p_shdw[line].p_virt != OSAL_NULL) {
1543                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1544                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1545                                           (p_shdw[line].p_phys >> 12));
1546
1547                                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1548                                         "Setting RT[0x%08x] from"
1549                                         " ILT[0x%08x] [Client is %d] to"
1550                                         " Physical addr: 0x%lx\n",
1551                                         rt_offst, line, i,
1552                                         (unsigned long)(p_shdw[line].
1553                                                         p_phys >> 12));
1554                         }
1555
1556                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1557                 }
1558         }
1559 }
1560
1561 /* SRC (Searcher) PF */
1562 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1563 {
1564         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1565         u32 rounded_conn_num, conn_num, conn_max;
1566         struct ecore_src_iids src_iids;
1567
1568         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1569         ecore_cxt_src_iids(p_mngr, &src_iids);
1570         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1571         if (!conn_num)
1572                 return;
1573
1574         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1575         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1576
1577         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1578         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1579                      OSAL_LOG2(rounded_conn_num));
1580
1581         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1582                          p_hwfn->p_cxt_mngr->first_free);
1583         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1584                          p_hwfn->p_cxt_mngr->last_free);
1585 }
1586
1587 /* Timers PF */
1588 #define TM_CFG_NUM_IDS_SHIFT            0
1589 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1590 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1591 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1592 #define TM_CFG_PARENT_PF_SHIFT          25
1593 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1594
1595 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1596 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1597
1598 #define TM_CFG_TID_OFFSET_SHIFT         30
1599 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1600 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1601 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1602
1603 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1604 {
1605         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1606         u32 active_seg_mask = 0, tm_offset, rt_reg;
1607         struct ecore_tm_iids tm_iids;
1608         u64 cfg_word;
1609         u8 i;
1610
1611         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1612         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1613
1614         /* @@@TBD No pre-scan for now */
1615
1616         /* Note: We assume consecutive VFs for a PF */
1617         for (i = 0; i < p_mngr->vf_count; i++) {
1618                 cfg_word = 0;
1619                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1620                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1621                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1622                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1623
1624                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1625                     (sizeof(cfg_word) / sizeof(u32)) *
1626                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1627                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1628         }
1629
1630         cfg_word = 0;
1631         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1632         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1633         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1634         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1635
1636         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1637             (sizeof(cfg_word) / sizeof(u32)) *
1638             (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1639         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1640
1641         /* enale scan */
1642         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1643                      tm_iids.pf_cids ? 0x1 : 0x0);
1644
1645         /* @@@TBD how to enable the scan for the VFs */
1646
1647         tm_offset = tm_iids.per_vf_cids;
1648
1649         /* Note: We assume consecutive VFs for a PF */
1650         for (i = 0; i < p_mngr->vf_count; i++) {
1651                 cfg_word = 0;
1652                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1653                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1654                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1655                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1656                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1657
1658                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1659                     (sizeof(cfg_word) / sizeof(u32)) *
1660                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1661
1662                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1663         }
1664
1665         tm_offset = tm_iids.pf_cids;
1666         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1667                 cfg_word = 0;
1668                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1669                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1670                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1671                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1672                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1673
1674                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1675                     (sizeof(cfg_word) / sizeof(u32)) *
1676                     (NUM_OF_VFS(p_hwfn->p_dev) +
1677                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1678
1679                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1680                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1681
1682                 tm_offset += tm_iids.pf_tids[i];
1683         }
1684
1685         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1686
1687         /* @@@TBD how to enable the scan for the VFs */
1688 }
1689
1690 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1691 {
1692         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1693         struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1694         struct ecore_tid_seg *p_tid;
1695
1696         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1697         if (!p_fcoe->cid_count)
1698                 return;
1699
1700         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1701         STORE_RT_REG_AGG(p_hwfn,
1702                         PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1703                         p_tid->count);
1704 }
1705
1706 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1707 {
1708         /* CDU configuration */
1709         ecore_cdu_init_common(p_hwfn);
1710 }
1711
1712 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1713 {
1714         ecore_qm_init_pf(p_hwfn);
1715         ecore_cm_init_pf(p_hwfn);
1716         ecore_dq_init_pf(p_hwfn);
1717         ecore_cdu_init_pf(p_hwfn);
1718         ecore_ilt_init_pf(p_hwfn);
1719         ecore_src_init_pf(p_hwfn);
1720         ecore_tm_init_pf(p_hwfn);
1721         ecore_prs_init_pf(p_hwfn);
1722 }
1723
1724 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1725                                            enum protocol_type type, u32 *p_cid)
1726 {
1727         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1728         u32 rel_cid;
1729
1730         if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1731                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1732                 return ECORE_INVAL;
1733         }
1734
1735         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_mngr->acquired[type].cid_map,
1736                                            p_mngr->acquired[type].max_count);
1737
1738         if (rel_cid >= p_mngr->acquired[type].max_count) {
1739                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1740                           type);
1741                 return ECORE_NORESOURCES;
1742         }
1743
1744         OSAL_SET_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1745
1746         *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1747
1748         return ECORE_SUCCESS;
1749 }
1750
1751 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1752                                         u32 cid, enum protocol_type *p_type)
1753 {
1754         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1755         struct ecore_cid_acquired_map *p_map;
1756         enum protocol_type p;
1757         u32 rel_cid;
1758
1759         /* Iterate over protocols and find matching cid range */
1760         for (p = 0; p < MAX_CONN_TYPES; p++) {
1761                 p_map = &p_mngr->acquired[p];
1762
1763                 if (!p_map->cid_map)
1764                         continue;
1765                 if (cid >= p_map->start_cid &&
1766                     cid < p_map->start_cid + p_map->max_count) {
1767                         break;
1768                 }
1769         }
1770         *p_type = p;
1771
1772         if (p == MAX_CONN_TYPES) {
1773                 DP_NOTICE(p_hwfn, true, "Invalid CID %d", cid);
1774                 return false;
1775         }
1776         rel_cid = cid - p_map->start_cid;
1777         if (!OSAL_TEST_BIT(rel_cid, p_map->cid_map)) {
1778                 DP_NOTICE(p_hwfn, true, "CID %d not acquired", cid);
1779                 return false;
1780         }
1781         return true;
1782 }
1783
1784 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1785 {
1786         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1787         enum protocol_type type;
1788         bool b_acquired;
1789         u32 rel_cid;
1790
1791         /* Test acquired and find matching per-protocol map */
1792         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, &type);
1793
1794         if (!b_acquired)
1795                 return;
1796
1797         rel_cid = cid - p_mngr->acquired[type].start_cid;
1798         OSAL_CLEAR_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1799 }
1800
1801 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1802                                             struct ecore_cxt_info *p_info)
1803 {
1804         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1805         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1806         enum protocol_type type;
1807         bool b_acquired;
1808
1809         /* Test acquired and find matching per-protocol map */
1810         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1811
1812         if (!b_acquired)
1813                 return ECORE_INVAL;
1814
1815         /* set the protocl type */
1816         p_info->type = type;
1817
1818         /* compute context virtual pointer */
1819         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1820
1821         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1822         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1823         line = p_info->iid / cxts_per_p;
1824
1825         /* Make sure context is allocated (dynamic allocation) */
1826         if (!p_mngr->ilt_shadow[line].p_virt)
1827                 return ECORE_INVAL;
1828
1829         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1830             p_info->iid % cxts_per_p * conn_cxt_size;
1831
1832         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1833                 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1834                 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1835
1836         return ECORE_SUCCESS;
1837 }
1838
1839 void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1840 {
1841         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1842
1843         p_mgr->srq_count = num_srqs;
1844 }
1845
1846 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1847 {
1848         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1849
1850         return p_mgr->srq_count;
1851 }
1852
1853 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1854 {
1855         /* Set the number of required CORE connections */
1856         u32 core_cids = 1;      /* SPQ */
1857
1858         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1859
1860         switch (p_hwfn->hw_info.personality) {
1861         case ECORE_PCI_ETH:
1862                 {
1863                         struct ecore_eth_pf_params *p_params =
1864                             &p_hwfn->pf_params.eth_pf_params;
1865
1866                         ecore_cxt_set_proto_cid_count(p_hwfn,
1867                                 PROTOCOLID_ETH,
1868                                 p_params->num_cons, 1); /* FIXME VF count... */
1869
1870                         break;
1871                 }
1872         default:
1873                 return ECORE_INVAL;
1874         }
1875
1876         return ECORE_SUCCESS;
1877 }
1878
1879 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1880                                                 struct ecore_tid_mem *p_info)
1881 {
1882         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1883         u32 proto, seg, total_lines, i, shadow_line;
1884         struct ecore_ilt_client_cfg *p_cli;
1885         struct ecore_ilt_cli_blk *p_fl_seg;
1886         struct ecore_tid_seg *p_seg_info;
1887
1888         /* Verify the personality */
1889         switch (p_hwfn->hw_info.personality) {
1890         default:
1891                 return ECORE_INVAL;
1892         }
1893
1894         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1895         if (!p_cli->active)
1896                 return ECORE_INVAL;
1897
1898         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1899         if (!p_seg_info->has_fl_mem)
1900                 return ECORE_INVAL;
1901
1902         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1903         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1904                                    p_fl_seg->real_size_in_page);
1905
1906         for (i = 0; i < total_lines; i++) {
1907                 shadow_line = i + p_fl_seg->start_line -
1908                     p_hwfn->p_cxt_mngr->pf_start_line;
1909                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1910         }
1911         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1912             p_fl_seg->real_size_in_page;
1913         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1914         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1915             p_info->tid_size;
1916
1917         return ECORE_SUCCESS;
1918 }
1919
1920 /* This function is very RoCE oriented, if another protocol in the future
1921  * will want this feature we'll need to modify the function to be more generic
1922  */
1923 enum _ecore_status_t
1924 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
1925                             enum ecore_cxt_elem_type elem_type,
1926                             u32 iid)
1927 {
1928         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
1929         struct ecore_ilt_client_cfg *p_cli;
1930         struct ecore_ilt_cli_blk *p_blk;
1931         struct ecore_ptt *p_ptt;
1932         dma_addr_t p_phys;
1933         u64 ilt_hw_entry;
1934         void *p_virt;
1935         enum _ecore_status_t rc = ECORE_SUCCESS;
1936
1937         switch (elem_type) {
1938         case ECORE_ELEM_CXT:
1939                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1940                 elem_size = CONN_CXT_SIZE(p_hwfn);
1941                 p_blk = &p_cli->pf_blks[CDUC_BLK];
1942                 break;
1943         case ECORE_ELEM_SRQ:
1944                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
1945                 elem_size = SRQ_CXT_SIZE;
1946                 p_blk = &p_cli->pf_blks[SRQ_BLK];
1947                 break;
1948         case ECORE_ELEM_TASK:
1949                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1950                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
1951                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
1952                 break;
1953         default:
1954                 DP_NOTICE(p_hwfn, false,
1955                           "ECORE_INVALID elem type = %d", elem_type);
1956                 return ECORE_INVAL;
1957         }
1958
1959         /* Calculate line in ilt */
1960         hw_p_size = p_cli->p_size.val;
1961         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1962         line = p_blk->start_line + (iid / elems_per_p);
1963         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
1964
1965         /* If line is already allocated, do nothing, otherwise allocate it and
1966          * write it to the PSWRQ2 registers.
1967          * This section can be run in parallel from different contexts and thus
1968          * a mutex protection is needed.
1969          */
1970
1971         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
1972
1973         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
1974                 goto out0;
1975
1976         p_ptt = ecore_ptt_acquire(p_hwfn);
1977         if (!p_ptt) {
1978                 DP_NOTICE(p_hwfn, false,
1979                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
1980                 rc = ECORE_TIMEOUT;
1981                 goto out0;
1982         }
1983
1984         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1985                                          &p_phys,
1986                                          p_blk->real_size_in_page);
1987         if (!p_virt) {
1988                 rc = ECORE_NOMEM;
1989                 goto out1;
1990         }
1991         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
1992
1993         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
1994         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
1995         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
1996                 p_blk->real_size_in_page;
1997
1998         /* compute absolute offset */
1999         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2000                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2001
2002         ilt_hw_entry = 0;
2003         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2004         SET_FIELD(ilt_hw_entry,
2005                   ILT_ENTRY_PHY_ADDR,
2006                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2007
2008 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2009
2010         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2011                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2012                             0 /* no flags */);
2013
2014         if (elem_type == ECORE_ELEM_CXT) {
2015                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2016                                          elems_per_p;
2017
2018                 /* Update the relevant register in the parser */
2019                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2020                          last_cid_allocated - 1);
2021
2022                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2023                         /* Enable RoCE search */
2024                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2025                         p_hwfn->b_rdma_enabled_in_prs = true;
2026                 }
2027         }
2028
2029 out1:
2030         ecore_ptt_release(p_hwfn, p_ptt);
2031 out0:
2032         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2033
2034         return rc;
2035 }
2036
2037 /* This function is very RoCE oriented, if another protocol in the future
2038  * will want this feature we'll need to modify the function to be more generic
2039  */
2040 static enum _ecore_status_t
2041 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2042                          enum ecore_cxt_elem_type elem_type,
2043                          u32 start_iid, u32 count)
2044 {
2045         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2046         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2047         struct ecore_ilt_client_cfg *p_cli;
2048         struct ecore_ilt_cli_blk *p_blk;
2049         u32 end_iid = start_iid + count;
2050         struct ecore_ptt *p_ptt;
2051         u64 ilt_hw_entry = 0;
2052         u32 i;
2053
2054         switch (elem_type) {
2055         case ECORE_ELEM_CXT:
2056                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2057                 elem_size = CONN_CXT_SIZE(p_hwfn);
2058                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2059                 break;
2060         case ECORE_ELEM_SRQ:
2061                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2062                 elem_size = SRQ_CXT_SIZE;
2063                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2064                 break;
2065         case ECORE_ELEM_TASK:
2066                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2067                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2068                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2069                 break;
2070         default:
2071                 DP_NOTICE(p_hwfn, false,
2072                           "ECORE_INVALID elem type = %d", elem_type);
2073                 return ECORE_INVAL;
2074         }
2075
2076         /* Calculate line in ilt */
2077         hw_p_size = p_cli->p_size.val;
2078         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2079         start_line = p_blk->start_line + (start_iid / elems_per_p);
2080         end_line = p_blk->start_line + (end_iid / elems_per_p);
2081         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2082                 end_line--;
2083
2084         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2085         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2086
2087         p_ptt = ecore_ptt_acquire(p_hwfn);
2088         if (!p_ptt) {
2089                 DP_NOTICE(p_hwfn, false,
2090                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2091                 return ECORE_TIMEOUT;
2092         }
2093
2094         for (i = shadow_start_line; i < shadow_end_line; i++) {
2095                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2096                         continue;
2097
2098                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2099                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2100                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2101                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2102
2103                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2104                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2105                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2106
2107                 /* compute absolute offset */
2108                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2109                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2110                      ILT_ENTRY_IN_REGS);
2111
2112                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2113                  * wide-bus.
2114                  */
2115                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2116                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2117                                     reg_offset,
2118                                     sizeof(ilt_hw_entry) / sizeof(u32),
2119                                     0 /* no flags */);
2120         }
2121
2122         ecore_ptt_release(p_hwfn, p_ptt);
2123
2124         return ECORE_SUCCESS;
2125 }
2126
2127 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2128                                               enum protocol_type proto)
2129 {
2130         enum _ecore_status_t rc;
2131         u32 cid;
2132
2133         /* Free Connection CXT */
2134         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2135                                       ecore_cxt_get_proto_cid_start(p_hwfn,
2136                                                                     proto),
2137                                       ecore_cxt_get_proto_cid_count(p_hwfn,
2138                                                                     proto,
2139                                                                     &cid));
2140
2141         if (rc)
2142                 return rc;
2143
2144         /* Free Task CXT */
2145         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2146                                       ecore_cxt_get_proto_tid_count(p_hwfn,
2147                                                                     proto));
2148         if (rc)
2149                 return rc;
2150
2151         /* Free TSDM CXT */
2152         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2153                                       ecore_cxt_get_srq_count(p_hwfn));
2154
2155         return rc;
2156 }
2157
2158 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2159                                             u32 tid,
2160                                             u8 ctx_type, void **pp_task_ctx)
2161 {
2162         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2163         struct ecore_ilt_client_cfg *p_cli;
2164         struct ecore_ilt_cli_blk *p_seg;
2165         struct ecore_tid_seg *p_seg_info;
2166         u32 proto, seg;
2167         u32 total_lines;
2168         u32 tid_size, ilt_idx;
2169         u32 num_tids_per_block;
2170
2171         /* Verify the personality */
2172         switch (p_hwfn->hw_info.personality) {
2173         default:
2174                 return ECORE_INVAL;
2175         }
2176
2177         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2178         if (!p_cli->active)
2179                 return ECORE_INVAL;
2180
2181         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2182
2183         if (ctx_type == ECORE_CTX_WORKING_MEM) {
2184                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2185         } else if (ctx_type == ECORE_CTX_FL_MEM) {
2186                 if (!p_seg_info->has_fl_mem)
2187                         return ECORE_INVAL;
2188                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2189         } else {
2190                 return ECORE_INVAL;
2191         }
2192         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2193         tid_size = p_mngr->task_type_size[p_seg_info->type];
2194         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2195
2196         if (total_lines < tid / num_tids_per_block)
2197                 return ECORE_INVAL;
2198
2199         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2200             p_mngr->pf_start_line;
2201         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2202             (tid % num_tids_per_block) * tid_size;
2203
2204         return ECORE_SUCCESS;
2205 }