drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73         if (val)
  74                 return 1 << (val + 15);
  75
  76         /* The above registers were updated in the past only in CMT mode. Since
  77          * they were found to be useful MFW started updating them from 8.7.7.0.
  78          * In older MFW versions they are set to 0 which means disabled.
  79          */
  80         if (p_hwfn->p_dev->num_hwfns > 1) {
  81                 DP_NOTICE(p_hwfn, false,
  82                           "BAR size not configured. Assuming BAR size of 256kB"
  83                           " for GRC and 512kB for DB\n");
  84                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85         } else {
  86                 DP_NOTICE(p_hwfn, false,
  87                           "BAR size not configured. Assuming BAR size of 512kB"
  88                           " for GRC and 512kB for DB\n");
  89                 val = 512 * 1024;
  90         }
  91
  92         return val;
  93 }
  94
  95 void ecore_init_dp(struct ecore_dev *p_dev,
  96                    u32 dp_module, u8 dp_level, void *dp_ctx)
  97 {
  98         u32 i;
  99
 100         p_dev->dp_level = dp_level;
 101         p_dev->dp_module = dp_module;
 102         p_dev->dp_ctx = dp_ctx;
 103         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 104                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 105
 106                 p_hwfn->dp_level = dp_level;
 107                 p_hwfn->dp_module = dp_module;
 108                 p_hwfn->dp_ctx = dp_ctx;
 109         }
 110 }
 111
 112 void ecore_init_struct(struct ecore_dev *p_dev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 118
 119                 p_hwfn->p_dev = p_dev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 124                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 125         }
 126
 127         /* hwfn 0 is always active */
 128         p_dev->hwfns[0].b_active = true;
 129
 130         /* set the default cache alignment to 128 (may be overridden later) */
 131         p_dev->cache_shift = 7;
 132 }
 133
 134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 135 {
 136         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 137
 138         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 142 }
 143
 144 void ecore_resc_free(struct ecore_dev *p_dev)
 145 {
 146         int i;
 147
 148         if (IS_VF(p_dev))
 149                 return;
 150
 151         OSAL_FREE(p_dev, p_dev->fw_data);
 152
 153         OSAL_FREE(p_dev, p_dev->reset_stats);
 154
 155         for_each_hwfn(p_dev, i) {
 156                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 157
 158                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 159                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 160         }
 161
 162         for_each_hwfn(p_dev, i) {
 163                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 164
 165                 ecore_cxt_mngr_free(p_hwfn);
 166                 ecore_qm_info_free(p_hwfn);
 167                 ecore_spq_free(p_hwfn);
 168                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 169                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 170                 ecore_int_free(p_hwfn);
 171 #ifdef CONFIG_ECORE_LL2
 172                 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 173 #endif
 174                 ecore_iov_free(p_hwfn);
 175                 ecore_dmae_info_free(p_hwfn);
 176                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 177                 /* @@@TBD Flush work-queue ? */
 178         }
 179 }
 180
 181 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 182                                                bool b_sleepable)
 183 {
 184         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
 185         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 186         struct init_qm_port_params *p_qm_port;
 187         bool init_rdma_offload_pq = false;
 188         bool init_pure_ack_pq = false;
 189         bool init_ooo_pq = false;
 190         u16 num_pqs, protocol_pqs;
 191         u16 num_pf_rls = 0;
 192         u16 num_vfs = 0;
 193         u32 pf_rl;
 194         u8 pf_wfq;
 195
 196         /* @TMP - saving the existing min/max bw config before resetting the
 197          * qm_info to restore them.
 198          */
 199         pf_rl = qm_info->pf_rl;
 200         pf_wfq = qm_info->pf_wfq;
 201
 202 #ifdef CONFIG_ECORE_SRIOV
 203         if (p_hwfn->p_dev->p_iov_info)
 204                 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
 205 #endif
 206         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 207
 208 #ifndef ASIC_ONLY
 209         /* @TMP - Don't allocate QM queues for VFs on emulation */
 210         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 211                 DP_NOTICE(p_hwfn, false,
 212                           "Emulation - skip configuring QM queues for VFs\n");
 213                 num_vfs = 0;
 214         }
 215 #endif
 216
 217         /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
 218          * active, we want physical queues allocated for all of them, since we
 219          * don't have a good recycle flow. Non ethernet PFs require only a
 220          * single physical queue.
 221          */
 222         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 223             p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 224             p_hwfn->hw_info.personality == ECORE_PCI_ETH)
 225                 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
 226         else
 227                 protocol_pqs = 1;
 228
 229         num_pqs = protocol_pqs + num_vfs + 1;   /* The '1' is for pure-LB */
 230         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 231
 232         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 233                 num_pqs++;      /* for RoCE queue */
 234                 init_rdma_offload_pq = true;
 235                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
 236                         /* Due to FW assumption that rl==vport, we limit the
 237                          * number of rate limiters by the minimum between its
 238                          * allocated number and the allocated number of vports.
 239                          * Another limitation is the number of supported qps
 240                          * with rate limiters in FW.
 241                          */
 242                         num_pf_rls =
 243                             (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 244                                              RESC_NUM(p_hwfn, ECORE_VPORT));
 245
 246                         /* we subtract num_vfs because each one requires a rate
 247                          * limiter, and one default rate limiter.
 248                          */
 249                         if (num_pf_rls < num_vfs + 1) {
 250                                 DP_ERR(p_hwfn, "No RL for DCQCN");
 251                                 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
 252                                        num_pf_rls, num_vfs);
 253                                 return ECORE_INVAL;
 254                         }
 255                         num_pf_rls -= num_vfs + 1;
 256                 }
 257
 258                 num_pqs += num_pf_rls;
 259                 qm_info->num_pf_rls = (u8)num_pf_rls;
 260         }
 261
 262         if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
 263                 num_pqs += 3;   /* for iwarp queue / pure-ack / ooo */
 264                 init_rdma_offload_pq = true;
 265                 init_pure_ack_pq = true;
 266                 init_ooo_pq = true;
 267         }
 268
 269         if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 270                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 271                 init_pure_ack_pq = true;
 272                 init_ooo_pq = true;
 273         }
 274
 275         /* Sanity checking that setup requires legal number of resources */
 276         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 277                 DP_ERR(p_hwfn,
 278                        "Need too many Physical queues - 0x%04x avail %04x",
 279                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 280                 return ECORE_INVAL;
 281         }
 282
 283         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 284          * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
 285          */
 286         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 287                                             b_sleepable ? GFP_KERNEL :
 288                                             GFP_ATOMIC,
 289                                             sizeof(struct init_qm_pq_params) *
 290                                             num_pqs);
 291         if (!qm_info->qm_pq_params)
 292                 goto alloc_err;
 293
 294         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 295                                                b_sleepable ? GFP_KERNEL :
 296                                                GFP_ATOMIC,
 297                                                sizeof(struct
 298                                                       init_qm_vport_params) *
 299                                                num_vports);
 300         if (!qm_info->qm_vport_params)
 301                 goto alloc_err;
 302
 303         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 304                                               b_sleepable ? GFP_KERNEL :
 305                                               GFP_ATOMIC,
 306                                               sizeof(struct init_qm_port_params)
 307                                               * MAX_NUM_PORTS);
 308         if (!qm_info->qm_port_params)
 309                 goto alloc_err;
 310
 311         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 312                                         b_sleepable ? GFP_KERNEL :
 313                                         GFP_ATOMIC,
 314                                         sizeof(struct ecore_wfq_data) *
 315                                         num_vports);
 316
 317         if (!qm_info->wfq_data)
 318                 goto alloc_err;
 319
 320         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 321
 322         /* First init rate limited queues ( Due to RoCE assumption of
 323          * qpid=rlid )
 324          */
 325         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 326                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 327                 qm_info->qm_pq_params[curr_queue].tc_id =
 328                     p_hwfn->hw_info.offload_tc;
 329                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 330                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 331         };
 332
 333         /* Protocol PQs */
 334         for (i = 0; i < protocol_pqs; i++) {
 335                 struct init_qm_pq_params *params =
 336                     &qm_info->qm_pq_params[curr_queue++];
 337
 338                 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 339                     p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 340                     p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
 341                         params->vport_id = vport_id;
 342                         params->tc_id = i;
 343                         /* Note: this assumes that if we had a configuration
 344                          * with N tcs and subsequently another configuration
 345                          * With Fewer TCs, the in flight traffic (in QM queues,
 346                          * in FW, from driver to FW) will still trickle out and
 347                          * not get "stuck" in the QM. This is determined by the
 348                          * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
 349                          * supposed to be cleared in this map, allowing traffic
 350                          * to flush out. If this is not the case, we would need
 351                          * to set the TC of unused queues to 0, and reconfigure
 352                          * QM every time num of TCs changes. Unused queues in
 353                          * this context would mean those intended for TCs where
 354                          * tc_id > hw_info.num_active_tcs.
 355                          */
 356                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 357                 } else {
 358                         params->vport_id = vport_id;
 359                         params->tc_id = p_hwfn->hw_info.offload_tc;
 360                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 361                 }
 362         }
 363
 364         /* Then init pure-LB PQ */
 365         qm_info->pure_lb_pq = curr_queue;
 366         qm_info->qm_pq_params[curr_queue].vport_id =
 367             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 368         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 369         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 370         curr_queue++;
 371
 372         qm_info->offload_pq = 0;        /* Already initialized for iSCSI/FCoE */
 373         if (init_rdma_offload_pq) {
 374                 qm_info->offload_pq = curr_queue;
 375                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 376                 qm_info->qm_pq_params[curr_queue].tc_id =
 377                     p_hwfn->hw_info.offload_tc;
 378                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 379                 curr_queue++;
 380         }
 381
 382         if (init_pure_ack_pq) {
 383                 qm_info->pure_ack_pq = curr_queue;
 384                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 385                 qm_info->qm_pq_params[curr_queue].tc_id =
 386                     p_hwfn->hw_info.offload_tc;
 387                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 388                 curr_queue++;
 389         }
 390
 391         if (init_ooo_pq) {
 392                 qm_info->ooo_pq = curr_queue;
 393                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 394                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 395                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 396                 curr_queue++;
 397         }
 398
 399         /* Then init per-VF PQs */
 400         vf_offset = curr_queue;
 401         for (i = 0; i < num_vfs; i++) {
 402                 /* First vport is used by the PF */
 403                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 404                 /* @@@TBD VF Multi-cos */
 405                 qm_info->qm_pq_params[curr_queue].tc_id = 0;
 406                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 407                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 408                 curr_queue++;
 409         };
 410
 411         qm_info->vf_queues_offset = vf_offset;
 412         qm_info->num_pqs = num_pqs;
 413         qm_info->num_vports = num_vports;
 414
 415         /* Initialize qm port parameters */
 416         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 417         for (i = 0; i < num_ports; i++) {
 418                 p_qm_port = &qm_info->qm_port_params[i];
 419                 p_qm_port->active = 1;
 420                 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
 421                  * be in place
 422                  */
 423                 if (num_ports == 4)
 424                         p_qm_port->active_phys_tcs = 0xf;
 425                 else
 426                         p_qm_port->active_phys_tcs = 0x9f;
 427                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 428                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 429         }
 430
 431         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 432                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 433         else
 434                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 435
 436         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 437
 438         qm_info->num_vf_pqs = num_vfs;
 439         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 440
 441         for (i = 0; i < qm_info->num_vports; i++)
 442                 qm_info->qm_vport_params[i].vport_wfq = 1;
 443
 444         qm_info->vport_rl_en = 1;
 445         qm_info->vport_wfq_en = 1;
 446         qm_info->pf_rl = pf_rl;
 447         qm_info->pf_wfq = pf_wfq;
 448
 449         return ECORE_SUCCESS;
 450
 451  alloc_err:
 452         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 453         ecore_qm_info_free(p_hwfn);
 454         return ECORE_NOMEM;
 455 }
 456
 457 /* This function reconfigures the QM pf on the fly.
 458  * For this purpose we:
 459  * 1. reconfigure the QM database
 460  * 2. set new values to runtime arrat
 461  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 462  * 4. activate init tool in QM_PF stage
 463  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 464  */
 465 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 466                                      struct ecore_ptt *p_ptt)
 467 {
 468         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 469         bool b_rc;
 470         enum _ecore_status_t rc;
 471
 472         /* qm_info is allocated in ecore_init_qm_info() which is already called
 473          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 474          * The allocated size may change each init, so we free it before next
 475          * allocation.
 476          */
 477         ecore_qm_info_free(p_hwfn);
 478
 479         /* initialize ecore's qm data structure */
 480         rc = ecore_init_qm_info(p_hwfn, false);
 481         if (rc != ECORE_SUCCESS)
 482                 return rc;
 483
 484         /* stop PF's qm queues */
 485         OSAL_SPIN_LOCK(&qm_lock);
 486         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 487                                       qm_info->start_pq, qm_info->num_pqs);
 488         OSAL_SPIN_UNLOCK(&qm_lock);
 489         if (!b_rc)
 490                 return ECORE_INVAL;
 491
 492         /* clear the QM_PF runtime phase leftovers from previous init */
 493         ecore_init_clear_rt_data(p_hwfn);
 494
 495         /* prepare QM portion of runtime array */
 496         ecore_qm_init_pf(p_hwfn);
 497
 498         /* activate init tool on runtime array */
 499         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 500                             p_hwfn->hw_info.hw_mode);
 501         if (rc != ECORE_SUCCESS)
 502                 return rc;
 503
 504         /* start PF's qm queues */
 505         OSAL_SPIN_LOCK(&qm_lock);
 506         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 507                                       qm_info->start_pq, qm_info->num_pqs);
 508         OSAL_SPIN_UNLOCK(&qm_lock);
 509         if (!b_rc)
 510                 return ECORE_INVAL;
 511
 512         return ECORE_SUCCESS;
 513 }
 514
 515 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 516 {
 517         struct ecore_consq *p_consq;
 518         struct ecore_eq *p_eq;
 519 #ifdef  CONFIG_ECORE_LL2
 520         struct ecore_ll2_info *p_ll2_info;
 521 #endif
 522         enum _ecore_status_t rc = ECORE_SUCCESS;
 523         int i;
 524
 525         if (IS_VF(p_dev))
 526                 return rc;
 527
 528         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 529                                      sizeof(*p_dev->fw_data));
 530         if (!p_dev->fw_data)
 531                 return ECORE_NOMEM;
 532
 533         /* Allocate Memory for the Queue->CID mapping */
 534         for_each_hwfn(p_dev, i) {
 535                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 536                 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 537                 int tx_size, rx_size;
 538
 539                 /* @@@TMP - resc management, change to actual required size */
 540                 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
 541                         num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
 542                 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
 543                 rx_size = sizeof(struct ecore_hw_cid_data) *
 544                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 545
 546                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 547                                                 tx_size);
 548                 if (!p_hwfn->p_tx_cids) {
 549                         DP_NOTICE(p_hwfn, true,
 550                                   "Failed to allocate memory for Tx Cids\n");
 551                         goto alloc_no_mem;
 552                 }
 553
 554                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 555                                                 rx_size);
 556                 if (!p_hwfn->p_rx_cids) {
 557                         DP_NOTICE(p_hwfn, true,
 558                                   "Failed to allocate memory for Rx Cids\n");
 559                         goto alloc_no_mem;
 560                 }
 561         }
 562
 563         for_each_hwfn(p_dev, i) {
 564                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 565                 u32 n_eqes, num_cons;
 566
 567                 /* First allocate the context manager structure */
 568                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 569                 if (rc)
 570                         goto alloc_err;
 571
 572                 /* Set the HW cid/tid numbers (in the contest manager)
 573                  * Must be done prior to any further computations.
 574                  */
 575                 rc = ecore_cxt_set_pf_params(p_hwfn);
 576                 if (rc)
 577                         goto alloc_err;
 578
 579                 /* Prepare and process QM requirements */
 580                 rc = ecore_init_qm_info(p_hwfn, true);
 581                 if (rc)
 582                         goto alloc_err;
 583
 584                 /* Compute the ILT client partition */
 585                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 586                 if (rc)
 587                         goto alloc_err;
 588
 589                 /* CID map / ILT shadow table / T2
 590                  * The talbes sizes are determined by the computations above
 591                  */
 592                 rc = ecore_cxt_tables_alloc(p_hwfn);
 593                 if (rc)
 594                         goto alloc_err;
 595
 596                 /* SPQ, must follow ILT because initializes SPQ context */
 597                 rc = ecore_spq_alloc(p_hwfn);
 598                 if (rc)
 599                         goto alloc_err;
 600
 601                 /* SP status block allocation */
 602                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 603                                                            RESERVED_PTT_DPC);
 604
 605                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 606                 if (rc)
 607                         goto alloc_err;
 608
 609                 rc = ecore_iov_alloc(p_hwfn);
 610                 if (rc)
 611                         goto alloc_err;
 612
 613                 /* EQ */
 614                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 615                 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
 616                     (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
 617                         /* Calculate the EQ size
 618                          * ---------------------
 619                          * Each ICID may generate up to one event at a time i.e.
 620                          * the event must be handled/cleared before a new one
 621                          * can be generated. We calculate the sum of events per
 622                          * protocol and create an EQ deep enough to handle the
 623                          * worst case:
 624                          * - Core - according to SPQ.
 625                          * - RoCE - per QP there are a couple of ICIDs, one
 626                          *          responder and one requester, each can
 627                          *          generate an EQE => n_eqes_qp = 2 * n_qp.
 628                          *          Each CQ can generate an EQE. There are 2 CQs
 629                          *          per QP => n_eqes_cq = 2 * n_qp.
 630                          *          Hence the RoCE total is 4 * n_qp or
 631                          *          2 * num_cons.
 632                          * - ENet - There can be up to two events per VF. One
 633                          *          for VF-PF channel and another for VF FLR
 634                          *          initial cleanup. The number of VFs is
 635                          *          bounded by MAX_NUM_VFS_BB, and is much
 636                          *          smaller than RoCE's so we avoid exact
 637                          *          calculation.
 638                          */
 639                         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 640                                 num_cons =
 641                                     ecore_cxt_get_proto_cid_count(
 642                                                 p_hwfn,
 643                                                 PROTOCOLID_ROCE,
 644                                                 OSAL_NULL);
 645                                 num_cons *= 2;
 646                         } else {
 647                                 num_cons = ecore_cxt_get_proto_cid_count(
 648                                                 p_hwfn,
 649                                                 PROTOCOLID_IWARP,
 650                                                 OSAL_NULL);
 651                         }
 652                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 653                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 654                         num_cons =
 655                             ecore_cxt_get_proto_cid_count(p_hwfn,
 656                                                           PROTOCOLID_ISCSI,
 657                                                           OSAL_NULL);
 658                         n_eqes += 2 * num_cons;
 659                 }
 660
 661                 if (n_eqes > 0xFFFF) {
 662                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 663                                        "The maximum of a u16 chain is 0x%x\n",
 664                                n_eqes, 0xFFFF);
 665                         goto alloc_no_mem;
 666                 }
 667
 668                 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 669                 if (!p_eq)
 670                         goto alloc_no_mem;
 671                 p_hwfn->p_eq = p_eq;
 672
 673                 p_consq = ecore_consq_alloc(p_hwfn);
 674                 if (!p_consq)
 675                         goto alloc_no_mem;
 676                 p_hwfn->p_consq = p_consq;
 677
 678 #ifdef CONFIG_ECORE_LL2
 679                 if (p_hwfn->using_ll2) {
 680                         p_ll2_info = ecore_ll2_alloc(p_hwfn);
 681                         if (!p_ll2_info)
 682                                 goto alloc_no_mem;
 683                         p_hwfn->p_ll2_info = p_ll2_info;
 684                 }
 685 #endif
 686
 687                 /* DMA info initialization */
 688                 rc = ecore_dmae_info_alloc(p_hwfn);
 689                 if (rc) {
 690                         DP_NOTICE(p_hwfn, true,
 691                                   "Failed to allocate memory for dmae_info structure\n");
 692                         goto alloc_err;
 693                 }
 694
 695                 /* DCBX initialization */
 696                 rc = ecore_dcbx_info_alloc(p_hwfn);
 697                 if (rc) {
 698                         DP_NOTICE(p_hwfn, true,
 699                                   "Failed to allocate memory for dcbx structure\n");
 700                         goto alloc_err;
 701                 }
 702         }
 703
 704         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 705                                          sizeof(*p_dev->reset_stats));
 706         if (!p_dev->reset_stats) {
 707                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 708                 goto alloc_no_mem;
 709         }
 710
 711         return ECORE_SUCCESS;
 712
 713  alloc_no_mem:
 714         rc = ECORE_NOMEM;
 715  alloc_err:
 716         ecore_resc_free(p_dev);
 717         return rc;
 718 }
 719
 720 void ecore_resc_setup(struct ecore_dev *p_dev)
 721 {
 722         int i;
 723
 724         if (IS_VF(p_dev))
 725                 return;
 726
 727         for_each_hwfn(p_dev, i) {
 728                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 729
 730                 ecore_cxt_mngr_setup(p_hwfn);
 731                 ecore_spq_setup(p_hwfn);
 732                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 733                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 734
 735                 /* Read shadow of current MFW mailbox */
 736                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 737                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 738                             p_hwfn->mcp_info->mfw_mb_cur,
 739                             p_hwfn->mcp_info->mfw_mb_length);
 740
 741                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 742
 743                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 744 #ifdef CONFIG_ECORE_LL2
 745                 if (p_hwfn->using_ll2)
 746                         ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
 747 #endif
 748         }
 749 }
 750
 751 #define FINAL_CLEANUP_POLL_CNT  (100)
 752 #define FINAL_CLEANUP_POLL_TIME (10)
 753 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 754                                          struct ecore_ptt *p_ptt,
 755                                          u16 id, bool is_vf)
 756 {
 757         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 758         enum _ecore_status_t rc = ECORE_TIMEOUT;
 759
 760 #ifndef ASIC_ONLY
 761         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 762             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 763                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 764                 return ECORE_SUCCESS;
 765         }
 766 #endif
 767
 768         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 769             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 770
 771         if (is_vf)
 772                 id += 0x10;
 773
 774         command |= X_FINAL_CLEANUP_AGG_INT <<
 775             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 776         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 777         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 778         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 779
 780 /* Make sure notification is not set before initiating final cleanup */
 781
 782         if (REG_RD(p_hwfn, addr)) {
 783                 DP_NOTICE(p_hwfn, false,
 784                           "Unexpected; Found final cleanup notification");
 785                 DP_NOTICE(p_hwfn, false,
 786                           " before initiating final cleanup\n");
 787                 REG_WR(p_hwfn, addr, 0);
 788         }
 789
 790         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 791                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 792                    id, command);
 793
 794         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
 795
 796         /* Poll until completion */
 797         while (!REG_RD(p_hwfn, addr) && count--)
 798                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 799
 800         if (REG_RD(p_hwfn, addr))
 801                 rc = ECORE_SUCCESS;
 802         else
 803                 DP_NOTICE(p_hwfn, true,
 804                           "Failed to receive FW final cleanup notification\n");
 805
 806         /* Cleanup afterwards */
 807         REG_WR(p_hwfn, addr, 0);
 808
 809         return rc;
 810 }
 811
 812 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 813 {
 814         int hw_mode = 0;
 815
 816         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
 817                 hw_mode |= 1 << MODE_BB_B0;
 818         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
 819                 hw_mode |= 1 << MODE_K2;
 820         } else {
 821                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
 822                           p_hwfn->p_dev->type);
 823                 return ECORE_INVAL;
 824         }
 825
 826         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 827         switch (p_hwfn->p_dev->num_ports_in_engines) {
 828         case 1:
 829                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 830                 break;
 831         case 2:
 832                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 833                 break;
 834         case 4:
 835                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 836                 break;
 837         default:
 838                 DP_NOTICE(p_hwfn, true,
 839                           "num_ports_in_engine = %d not supported\n",
 840                           p_hwfn->p_dev->num_ports_in_engines);
 841                 return ECORE_INVAL;
 842         }
 843
 844         switch (p_hwfn->p_dev->mf_mode) {
 845         case ECORE_MF_DEFAULT:
 846         case ECORE_MF_NPAR:
 847                 hw_mode |= 1 << MODE_MF_SI;
 848                 break;
 849         case ECORE_MF_OVLAN:
 850                 hw_mode |= 1 << MODE_MF_SD;
 851                 break;
 852         default:
 853                 DP_NOTICE(p_hwfn, true,
 854                           "Unsupported MF mode, init as DEFAULT\n");
 855                 hw_mode |= 1 << MODE_MF_SI;
 856         }
 857
 858 #ifndef ASIC_ONLY
 859         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 860                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 861                         hw_mode |= 1 << MODE_FPGA;
 862                 } else {
 863                         if (p_hwfn->p_dev->b_is_emul_full)
 864                                 hw_mode |= 1 << MODE_EMUL_FULL;
 865                         else
 866                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 867                 }
 868         } else
 869 #endif
 870                 hw_mode |= 1 << MODE_ASIC;
 871
 872         if (p_hwfn->p_dev->num_hwfns > 1)
 873                 hw_mode |= 1 << MODE_100G;
 874
 875         p_hwfn->hw_info.hw_mode = hw_mode;
 876
 877         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 878                    "Configuring function for hw_mode: 0x%08x\n",
 879                    p_hwfn->hw_info.hw_mode);
 880
 881         return ECORE_SUCCESS;
 882 }
 883
 884 #ifndef ASIC_ONLY
 885 /* MFW-replacement initializations for non-ASIC */
 886 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 887                                                struct ecore_ptt *p_ptt)
 888 {
 889         u32 pl_hv = 1;
 890         int i;
 891
 892         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 893                 pl_hv |= 0x600;
 894
 895         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 896
 897         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 898                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
 899
 900         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 901         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 902         if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
 903                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
 904
 905         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
 906                 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 907                 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 908                          (p_hwfn->p_dev->num_ports_in_engines >> 1));
 909
 910                 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 911                          p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
 912         }
 913
 914         /* Poll on RBC */
 915         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 916         for (i = 0; i < 100; i++) {
 917                 OSAL_UDELAY(50);
 918                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 919                         break;
 920         }
 921         if (i == 100)
 922                 DP_NOTICE(p_hwfn, true,
 923                           "RBC done failed to complete in PSWRQ2\n");
 924
 925         return ECORE_SUCCESS;
 926 }
 927 #endif
 928
 929 /* Init run time data for all PFs and their VFs on an engine.
 930  * TBD - for VFs - Once we have parent PF info for each VF in
 931  * shmem available as CAU requires knowledge of parent PF for each VF.
 932  */
 933 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 934 {
 935         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 936         int i, sb_id;
 937
 938         for_each_hwfn(p_dev, i) {
 939                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 940                 struct ecore_igu_info *p_igu_info;
 941                 struct ecore_igu_block *p_block;
 942                 struct cau_sb_entry sb_entry;
 943
 944                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 945
 946                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 947                      sb_id++) {
 948                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 949
 950                         if (!p_block->is_pf)
 951                                 continue;
 952
 953                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 954                                                 p_block->function_id, 0, 0);
 955                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 956                 }
 957         }
 958 }
 959
 960 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 961                                                  struct ecore_ptt *p_ptt,
 962                                                  int hw_mode)
 963 {
 964         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 965         struct ecore_dev *p_dev = p_hwfn->p_dev;
 966         u8 vf_id, max_num_vfs;
 967         u16 num_pfs, pf_id;
 968         u32 concrete_fid;
 969         enum _ecore_status_t rc = ECORE_SUCCESS;
 970
 971         ecore_init_cau_rt_data(p_dev);
 972
 973         /* Program GTT windows */
 974         ecore_gtt_init(p_hwfn);
 975
 976 #ifndef ASIC_ONLY
 977         if (CHIP_REV_IS_EMUL(p_dev)) {
 978                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 979                 if (rc != ECORE_SUCCESS)
 980                         return rc;
 981         }
 982 #endif
 983
 984         if (p_hwfn->mcp_info) {
 985                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 986                         qm_info->pf_rl_en = 1;
 987                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 988                         qm_info->pf_wfq_en = 1;
 989         }
 990
 991         ecore_qm_common_rt_init(p_hwfn,
 992                                 p_dev->num_ports_in_engines,
 993                                 qm_info->max_phys_tcs_per_port,
 994                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
 995                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
 996                                 qm_info->qm_port_params);
 997
 998         ecore_cxt_hw_init_common(p_hwfn);
 999
1000         /* Close gate from NIG to BRB/Storm; By default they are open, but
1001          * we close them to prevent NIG from passing data to reset blocks.
1002          * Should have been done in the ENGINE phase, but init-tool lacks
1003          * proper port-pretend capabilities.
1004          */
1005         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1006         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1007         ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1008         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1009         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1010         ecore_port_unpretend(p_hwfn, p_ptt);
1011
1012         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1013         if (rc != ECORE_SUCCESS)
1014                 return rc;
1015
1016         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1017          * need to decide with which value, maybe runtime
1018          */
1019         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1020         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1021
1022         if (ECORE_IS_BB(p_dev)) {
1023                 /* Workaround clears ROCE search for all functions to prevent
1024                  * involving non initialized function in processing ROCE packet.
1025                  */
1026                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1027                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1028                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1029                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1030                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1031                 }
1032                 /* pretend to original PF */
1033                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1034         }
1035
1036         /* Workaround for avoiding CCFC execution error when getting packets
1037          * with CRC errors, and allowing instead the invoking of the FW error
1038          * handler.
1039          * This is not done inside the init tool since it currently can't
1040          * perform a pretending to VFs.
1041          */
1042         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1043         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1044                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1045                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1046                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1047                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1048                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1049                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1050         }
1051         /* pretend to original PF */
1052         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1053
1054         return rc;
1055 }
1056
1057 #ifndef ASIC_ONLY
1058 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1059 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1060
1061 #define PMEG_IF_BYTE_COUNT      8
1062
1063 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1064                              struct ecore_ptt *p_ptt,
1065                              u32 addr, u64 data, u8 reg_type, u8 port)
1066 {
1067         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1068                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1069                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
1070                    (8 << PMEG_IF_BYTE_COUNT),
1071                    (reg_type << 25) | (addr << 8) | port,
1072                    (u32)((data >> 32) & 0xffffffff),
1073                    (u32)(data & 0xffffffff));
1074
1075         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
1076                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
1077                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1078         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
1079                  (reg_type << 25) | (addr << 8) | port);
1080         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1081                  data & 0xffffffff);
1082         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1083                  (data >> 32) & 0xffffffff);
1084 }
1085
1086 #define XLPORT_MODE_REG (0x20a)
1087 #define XLPORT_MAC_CONTROL (0x210)
1088 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1089 #define XLPORT_ENABLE_REG (0x20b)
1090
1091 #define XLMAC_CTRL (0x600)
1092 #define XLMAC_MODE (0x601)
1093 #define XLMAC_RX_MAX_SIZE (0x608)
1094 #define XLMAC_TX_CTRL (0x604)
1095 #define XLMAC_PAUSE_CTRL (0x60d)
1096 #define XLMAC_PFC_CTRL (0x60e)
1097
1098 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
1099                                     struct ecore_ptt *p_ptt)
1100 {
1101         u8 port = p_hwfn->port_id;
1102         u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
1103
1104         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
1105                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
1106                  (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
1107                  | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
1108
1109         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
1110                  1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
1111
1112         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
1113                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
1114
1115         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
1116                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
1117
1118         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
1119                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
1120
1121         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
1122                  (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
1123                  (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
1124
1125         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
1126 }
1127
1128 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1129                                  struct ecore_ptt *p_ptt)
1130 {
1131         u8 loopback = 0, port = p_hwfn->port_id * 2;
1132
1133         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1134
1135         if (ECORE_IS_AH(p_hwfn->p_dev)) {
1136                 ecore_emul_link_init_ah(p_hwfn, p_ptt);
1137                 return;
1138         }
1139
1140         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1141         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1142                          port);
1143         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1144         /* XLMAC: SOFT RESET */
1145         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1146         /* XLMAC: Port Speed >= 10Gbps */
1147         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1148         /* XLMAC: Max Size */
1149         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1150         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1151                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1152                          0, port);
1153         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1154         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1155                          0x30ffffc000ULL, 0, port);
1156         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1157                          port); /* XLMAC: TX_EN, RX_EN */
1158         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1159         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1160                          0x1003 | (loopback << 2), 0, port);
1161         /* Enabled Parallel PFC interface */
1162         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1163
1164         /* XLPORT port enable */
1165         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1166 }
1167
1168 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
1169                             struct ecore_ptt *p_ptt, u8 port)
1170 {
1171         int port_offset = port ? 0x800 : 0;
1172         u32 xmac_rxctrl = 0;
1173
1174         /* Reset of XMAC */
1175         /* FIXME: move to common start */
1176         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1177                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1178         OSAL_MSLEEP(1);
1179         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1180                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1181
1182         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1183
1184         /* Set the number of ports on the Warp Core to 10G */
1185         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1186
1187         /* Soft reset of XMAC */
1188         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1189                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1190         OSAL_MSLEEP(1);
1191         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1192                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1193
1194         /* FIXME: move to common end */
1195         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1196                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
1197
1198         /* Set Max packet size: initialize XMAC block register for port 0 */
1199         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
1200
1201         /* CRC append for Tx packets: init XMAC block register for port 1 */
1202         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
1203
1204         /* Enable TX and RX: initialize XMAC block register for port 1 */
1205         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
1206                  XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
1207         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
1208         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
1209         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1210 }
1211 #endif
1212
1213 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1214                                                struct ecore_ptt *p_ptt,
1215                                                int hw_mode)
1216 {
1217         enum _ecore_status_t rc = ECORE_SUCCESS;
1218
1219         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1220                             hw_mode);
1221         if (rc != ECORE_SUCCESS)
1222                 return rc;
1223 #ifndef ASIC_ONLY
1224         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1225                 return ECORE_SUCCESS;
1226
1227         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1228                 if (ECORE_IS_AH(p_hwfn->p_dev))
1229                         return ECORE_SUCCESS;
1230                 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1231         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1232                 if (p_hwfn->p_dev->num_hwfns > 1) {
1233                         /* Activate OPTE in CMT */
1234                         u32 val;
1235
1236                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1237                         val |= 0x10;
1238                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1239                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1240                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1241                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1242                         ecore_wr(p_hwfn, p_ptt,
1243                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1244                         ecore_wr(p_hwfn, p_ptt,
1245                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1246                         ecore_wr(p_hwfn, p_ptt,
1247                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1248                                  0x55555555);
1249                 }
1250
1251                 ecore_emul_link_init(p_hwfn, p_ptt);
1252         } else {
1253                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1254         }
1255 #endif
1256
1257         return rc;
1258 }
1259
1260 static enum _ecore_status_t
1261 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1262                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1263 {
1264         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1265         u32 dpi_bit_shift, dpi_count;
1266         u32 min_dpis;
1267
1268         /* Calculate DPI size
1269          * ------------------
1270          * The PWM region contains Doorbell Pages. The first is reserverd for
1271          * the kernel for, e.g, L2. The others are free to be used by non-
1272          * trusted applications, typically from user space. Each page, called a
1273          * doorbell page is sectioned into windows that allow doorbells to be
1274          * issued in parallel by the kernel/application. The size of such a
1275          * window (a.k.a. WID) is 1kB.
1276          * Summary:
1277          *    1kB WID x N WIDS = DPI page size
1278          *    DPI page size x N DPIs = PWM region size
1279          * Notes:
1280          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1281          * in order to ensure that two applications won't share the same page.
1282          * It also must contain at least one WID per CPU to allow parallelism.
1283          * It also must be a power of 2, since it is stored as a bit shift.
1284          *
1285          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1286          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1287          * containing 4 WIDs.
1288          */
1289         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1290         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1291         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1292         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1293         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1294
1295         dpi_count = pwm_region_size / dpi_page_size;
1296
1297         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1298         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1299
1300         /* Update hwfn */
1301         p_hwfn->dpi_size = dpi_page_size;
1302         p_hwfn->dpi_count = dpi_count;
1303
1304         /* Update registers */
1305         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1306
1307         if (dpi_count < min_dpis)
1308                 return ECORE_NORESOURCES;
1309
1310         return ECORE_SUCCESS;
1311 }
1312
1313 enum ECORE_ROCE_EDPM_MODE {
1314         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1315         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1316         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1317 };
1318
1319 static enum _ecore_status_t
1320 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1321                               struct ecore_ptt *p_ptt)
1322 {
1323         u32 pwm_regsize, norm_regsize;
1324         u32 non_pwm_conn, min_addr_reg1;
1325         u32 db_bar_size, n_cpus;
1326         u32 roce_edpm_mode;
1327         u32 pf_dems_shift;
1328         int rc = ECORE_SUCCESS;
1329         u8 cond;
1330
1331         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1332         if (p_hwfn->p_dev->num_hwfns > 1)
1333                 db_bar_size /= 2;
1334
1335         /* Calculate doorbell regions
1336          * -----------------------------------
1337          * The doorbell BAR is made of two regions. The first is called normal
1338          * region and the second is called PWM region. In the normal region
1339          * each ICID has its own set of addresses so that writing to that
1340          * specific address identifies the ICID. In the Process Window Mode
1341          * region the ICID is given in the data written to the doorbell. The
1342          * above per PF register denotes the offset in the doorbell BAR in which
1343          * the PWM region begins.
1344          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1345          * non-PWM connection. The calculation below computes the total non-PWM
1346          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1347          * in units of 4,096 bytes.
1348          */
1349         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1350             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1351                                           OSAL_NULL) +
1352             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1353         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1354         min_addr_reg1 = norm_regsize / 4096;
1355         pwm_regsize = db_bar_size - norm_regsize;
1356
1357         /* Check that the normal and PWM sizes are valid */
1358         if (db_bar_size < norm_regsize) {
1359                 DP_ERR(p_hwfn->p_dev,
1360                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1361                        db_bar_size, norm_regsize);
1362                 return ECORE_NORESOURCES;
1363         }
1364         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1365                 DP_ERR(p_hwfn->p_dev,
1366                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1367                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1368                        norm_regsize);
1369                 return ECORE_NORESOURCES;
1370         }
1371
1372         /* Calculate number of DPIs */
1373         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1374         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1375             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1376                 /* Either EDPM is mandatory, or we are attempting to allocate a
1377                  * WID per CPU.
1378                  */
1379                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1380                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1381         }
1382
1383         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1384             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1385         if (cond || p_hwfn->dcbx_no_edpm) {
1386                 /* Either EDPM is disabled from user configuration, or it is
1387                  * disabled via DCBx, or it is not mandatory and we failed to
1388                  * allocated a WID per CPU.
1389                  */
1390                 n_cpus = 1;
1391                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1392
1393                 /* If we entered this flow due to DCBX then the DPM register is
1394                  * already configured.
1395                  */
1396         }
1397
1398         DP_INFO(p_hwfn,
1399                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1400                 norm_regsize, pwm_regsize);
1401         DP_INFO(p_hwfn,
1402                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1403                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1404                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1405                 "disabled" : "enabled");
1406
1407         /* Check return codes from above calls */
1408         if (rc) {
1409                 DP_ERR(p_hwfn,
1410                        "Failed to allocate enough DPIs\n");
1411                 return ECORE_NORESOURCES;
1412         }
1413
1414         /* Update hwfn */
1415         p_hwfn->dpi_start_offset = norm_regsize;
1416
1417         /* Update registers */
1418         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1419         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1420         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1421         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1422
1423         return ECORE_SUCCESS;
1424 }
1425
1426 static enum _ecore_status_t
1427 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1428                  struct ecore_ptt *p_ptt,
1429                  struct ecore_tunn_start_params *p_tunn,
1430                  int hw_mode,
1431                  bool b_hw_start,
1432                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1433 {
1434         u8 rel_pf_id = p_hwfn->rel_pf_id;
1435         u32 prs_reg;
1436         enum _ecore_status_t rc = ECORE_SUCCESS;
1437         u16 ctrl;
1438         int pos;
1439
1440         if (p_hwfn->mcp_info) {
1441                 struct ecore_mcp_function_info *p_info;
1442
1443                 p_info = &p_hwfn->mcp_info->func_info;
1444                 if (p_info->bandwidth_min)
1445                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1446
1447                 /* Update rate limit once we'll actually have a link */
1448                 p_hwfn->qm_info.pf_rl = 100000;
1449         }
1450         ecore_cxt_hw_init_pf(p_hwfn);
1451
1452         ecore_int_igu_init_rt(p_hwfn);
1453
1454         /* Set VLAN in NIG if needed */
1455         if (hw_mode & (1 << MODE_MF_SD)) {
1456                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1457                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1458                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1459                              p_hwfn->hw_info.ovlan);
1460         }
1461
1462         /* Enable classification by MAC if needed */
1463         if (hw_mode & (1 << MODE_MF_SI)) {
1464                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1465                            "Configuring TAGMAC_CLS_TYPE\n");
1466                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1467                              1);
1468         }
1469
1470         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1471         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1472                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1473         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1474                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1475         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1476
1477         /* perform debug configuration when chip is out of reset */
1478         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1479
1480         /* Cleanup chip from previous driver if such remains exist */
1481         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1482         if (rc != ECORE_SUCCESS) {
1483                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1484                 return rc;
1485         }
1486
1487         /* PF Init sequence */
1488         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1489         if (rc)
1490                 return rc;
1491
1492         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1493         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1494         if (rc)
1495                 return rc;
1496
1497         /* Pure runtime initializations - directly to the HW  */
1498         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1499
1500         /* PCI relaxed ordering causes a decrease in the performance on some
1501          * systems. Till a root cause is found, disable this attribute in the
1502          * PCI config space.
1503          */
1504         /* Not in use @DPDK
1505         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1506         * if (!pos) {
1507         *       DP_NOTICE(p_hwfn, true,
1508         *                 "Failed to find the PCIe Cap\n");
1509         *       return ECORE_IO;
1510         * }
1511         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1512         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1513         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1514         */
1515
1516         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1517         if (rc)
1518                 return rc;
1519         if (b_hw_start) {
1520                 /* enable interrupts */
1521                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1522                 if (rc != ECORE_SUCCESS)
1523                         return rc;
1524
1525                 /* send function start command */
1526                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1527                                        allow_npar_tx_switch);
1528                 if (rc) {
1529                         DP_NOTICE(p_hwfn, true,
1530                                   "Function start ramrod failed\n");
1531                 } else {
1532                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1533                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1534                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1535
1536                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1537                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1538                                          (1 << 2));
1539                                 ecore_wr(p_hwfn, p_ptt,
1540                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1541                                     0x100);
1542                         }
1543                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1544                                    "PRS_REG_SEARCH registers after start PFn\n");
1545                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1546                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1547                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1548                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1549                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1550                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1551                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1552                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1553                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1554                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1555                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1556                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1557                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1558                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1559                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1560                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1561                                    prs_reg);
1562                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1563                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1564                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1565                 }
1566         }
1567         return rc;
1568 }
1569
1570 static enum _ecore_status_t
1571 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1572                       struct ecore_ptt *p_ptt, u8 enable)
1573 {
1574         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1575
1576         /* Change PF in PXP */
1577         ecore_wr(p_hwfn, p_ptt,
1578                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1579
1580         /* wait until value is set - try for 1 second every 50us */
1581         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1582                 val = ecore_rd(p_hwfn, p_ptt,
1583                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1584                 if (val == set_val)
1585                         break;
1586
1587                 OSAL_UDELAY(50);
1588         }
1589
1590         if (val != set_val) {
1591                 DP_NOTICE(p_hwfn, true,
1592                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1593                 return ECORE_UNKNOWN_ERROR;
1594         }
1595
1596         return ECORE_SUCCESS;
1597 }
1598
1599 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1600                                   struct ecore_ptt *p_main_ptt)
1601 {
1602         /* Read shadow of current MFW mailbox */
1603         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1604         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1605                     p_hwfn->mcp_info->mfw_mb_cur,
1606                     p_hwfn->mcp_info->mfw_mb_length);
1607 }
1608
1609 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1610                                    struct ecore_hw_init_params *p_params)
1611 {
1612         enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1613         u32 load_code, param, drv_mb_param;
1614         struct ecore_hwfn *p_hwfn;
1615         int i;
1616
1617         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1618             (p_dev->num_hwfns > 1)) {
1619                 DP_NOTICE(p_dev, false,
1620                           "MSI mode is not supported for CMT devices\n");
1621                 return ECORE_INVAL;
1622         }
1623
1624         if (IS_PF(p_dev)) {
1625                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1626                 if (rc != ECORE_SUCCESS)
1627                         return rc;
1628         }
1629
1630         for_each_hwfn(p_dev, i) {
1631                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1632
1633                 if (IS_VF(p_dev)) {
1634                         p_hwfn->b_int_enabled = 1;
1635                         continue;
1636                 }
1637
1638                 /* Enable DMAE in PXP */
1639                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1640                 if (rc != ECORE_SUCCESS)
1641                         return rc;
1642
1643                 rc = ecore_calc_hw_mode(p_hwfn);
1644                 if (rc != ECORE_SUCCESS)
1645                         return rc;
1646
1647                 /* @@@TBD need to add here:
1648                  * Check for fan failure
1649                  * Prev_unload
1650                  */
1651                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1652                 if (rc) {
1653                         DP_NOTICE(p_hwfn, true,
1654                                   "Failed sending LOAD_REQ command\n");
1655                         return rc;
1656                 }
1657
1658                 /* CQ75580:
1659                  * When coming back from hiberbate state, the registers from
1660                  * which shadow is read initially are not initialized. It turns
1661                  * out that these registers get initialized during the call to
1662                  * ecore_mcp_load_req request. So we need to reread them here
1663                  * to get the proper shadow register value.
1664                  * Note: This is a workaround for the missinginig MFW
1665                  * initialization. It may be removed once the implementation
1666                  * is done.
1667                  */
1668                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1669
1670                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1671                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1672                            rc, load_code);
1673
1674                 /* Only relevant for recovery:
1675                  * Clear the indication after the LOAD_REQ command is responded
1676                  * by the MFW.
1677                  */
1678                 p_dev->recov_in_prog = false;
1679
1680                 p_hwfn->first_on_engine = (load_code ==
1681                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1682
1683                 if (!qm_lock_init) {
1684                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1685                         qm_lock_init = true;
1686                 }
1687
1688                 switch (load_code) {
1689                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1690                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1691                                                   p_hwfn->hw_info.hw_mode);
1692                         if (rc)
1693                                 break;
1694                         /* Fall into */
1695                 case FW_MSG_CODE_DRV_LOAD_PORT:
1696                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1697                                                 p_hwfn->hw_info.hw_mode);
1698                         if (rc)
1699                                 break;
1700                         /* Fall into */
1701                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1702                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1703                                               p_params->p_tunn,
1704                                               p_hwfn->hw_info.hw_mode,
1705                                               p_params->b_hw_start,
1706                                               p_params->int_mode,
1707                                               p_params->allow_npar_tx_switch);
1708                         break;
1709                 default:
1710                         rc = ECORE_NOTIMPL;
1711                         break;
1712                 }
1713
1714                 if (rc != ECORE_SUCCESS)
1715                         DP_NOTICE(p_hwfn, true,
1716                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1717                                   load_code, rc);
1718
1719                 /* ACK mfw regardless of success or failure of initialization */
1720                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1721                                        DRV_MSG_CODE_LOAD_DONE,
1722                                        0, &load_code, &param);
1723                 if (rc != ECORE_SUCCESS)
1724                         return rc;
1725                 if (mfw_rc != ECORE_SUCCESS) {
1726                         DP_NOTICE(p_hwfn, true,
1727                                   "Failed sending LOAD_DONE command\n");
1728                         return mfw_rc;
1729                 }
1730
1731                 /* send DCBX attention request command */
1732                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1733                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1734                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1735                                        DRV_MSG_CODE_SET_DCBX,
1736                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1737                                        &load_code, &param);
1738                 if (mfw_rc != ECORE_SUCCESS) {
1739                         DP_NOTICE(p_hwfn, true,
1740                                   "Failed to send DCBX attention request\n");
1741                         return mfw_rc;
1742                 }
1743
1744                 p_hwfn->hw_init_done = true;
1745         }
1746
1747         if (IS_PF(p_dev)) {
1748                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
1749                 drv_mb_param = (FW_MAJOR_VERSION << 24) |
1750                                (FW_MINOR_VERSION << 16) |
1751                                (FW_REVISION_VERSION << 8) |
1752                                (FW_ENGINEERING_VERSION);
1753                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1754                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1755                                    drv_mb_param, &load_code, &param);
1756                 if (rc != ECORE_SUCCESS) {
1757                         DP_ERR(p_hwfn, "Failed to send firmware version\n");
1758                         return rc;
1759                 }
1760
1761                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
1762                                                       p_hwfn->p_main_ptt,
1763                                                 ECORE_OV_DRIVER_STATE_DISABLED);
1764         }
1765
1766         return rc;
1767 }
1768
1769 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1770 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1771                                  struct ecore_hwfn *p_hwfn,
1772                                  struct ecore_ptt *p_ptt)
1773 {
1774         int i;
1775
1776         /* close timers */
1777         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1778         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1779         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1780                                                                         i++) {
1781                 if ((!ecore_rd(p_hwfn, p_ptt,
1782                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1783                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1784                         break;
1785
1786                 /* Dependent on number of connection/tasks, possibly
1787                  * 1ms sleep is required between polls
1788                  */
1789                 OSAL_MSLEEP(1);
1790         }
1791
1792         if (i < ECORE_HW_STOP_RETRY_LIMIT)
1793                 return;
1794
1795         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
1796                   " [Connection %02x Tasks %02x]\n",
1797                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1798                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1799 }
1800
1801 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1802 {
1803         int j;
1804
1805         for_each_hwfn(p_dev, j) {
1806                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1807                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1808
1809                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1810         }
1811 }
1812
1813 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1814 {
1815         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1816         int j;
1817
1818         for_each_hwfn(p_dev, j) {
1819                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1820                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1821
1822                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1823
1824                 if (IS_VF(p_dev)) {
1825                         ecore_vf_pf_int_cleanup(p_hwfn);
1826                         continue;
1827                 }
1828
1829                 /* mark the hw as uninitialized... */
1830                 p_hwfn->hw_init_done = false;
1831
1832                 rc = ecore_sp_pf_stop(p_hwfn);
1833                 if (rc)
1834                         DP_NOTICE(p_hwfn, true,
1835                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1836
1837                 /* perform debug action after PF stop was sent */
1838                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1839
1840                 /* close NIG to BRB gate */
1841                 ecore_wr(p_hwfn, p_ptt,
1842                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1843
1844                 /* close parser */
1845                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1846                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1847                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1848                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1849                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1850
1851                 /* @@@TBD - clean transmission queues (5.b) */
1852                 /* @@@TBD - clean BTB (5.c) */
1853
1854                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1855
1856                 /* @@@TBD - verify DMAE requests are done (8) */
1857
1858                 /* Disable Attention Generation */
1859                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1860                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1861                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1862                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1863                 /* Need to wait 1ms to guarantee SBs are cleared */
1864                 OSAL_MSLEEP(1);
1865         }
1866
1867         if (IS_PF(p_dev)) {
1868                 /* Disable DMAE in PXP - in CMT, this should only be done for
1869                  * first hw-function, and only after all transactions have
1870                  * stopped for all active hw-functions.
1871                  */
1872                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1873                                              p_dev->hwfns[0].p_main_ptt, false);
1874                 if (t_rc != ECORE_SUCCESS)
1875                         rc = t_rc;
1876         }
1877
1878         return rc;
1879 }
1880
1881 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1882 {
1883         int j;
1884
1885         for_each_hwfn(p_dev, j) {
1886                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1887                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1888
1889                 if (IS_VF(p_dev)) {
1890                         ecore_vf_pf_int_cleanup(p_hwfn);
1891                         continue;
1892                 }
1893
1894                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1895                            "Shutting down the fastpath\n");
1896
1897                 ecore_wr(p_hwfn, p_ptt,
1898                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1899
1900                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1901                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1902                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1903                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1904                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1905
1906                 /* @@@TBD - clean transmission queues (5.b) */
1907                 /* @@@TBD - clean BTB (5.c) */
1908
1909                 /* @@@TBD - verify DMAE requests are done (8) */
1910
1911                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1912                 /* Need to wait 1ms to guarantee SBs are cleared */
1913                 OSAL_MSLEEP(1);
1914         }
1915 }
1916
1917 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1918 {
1919         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1920
1921         if (IS_VF(p_hwfn->p_dev))
1922                 return;
1923
1924         /* If roce info is allocated it means roce is initialized and should
1925          * be enabled in searcher.
1926          */
1927         if (p_hwfn->p_rdma_info) {
1928                 if (p_hwfn->b_rdma_enabled_in_prs)
1929                         ecore_wr(p_hwfn, p_ptt,
1930                                  p_hwfn->rdma_prs_search_reg, 0x1);
1931                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1932         }
1933
1934         /* Re-open incoming traffic */
1935         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1936                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1937 }
1938
1939 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1940                                              struct ecore_ptt *p_ptt, u32 reg,
1941                                              bool expected)
1942 {
1943         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1944
1945         if (assert_val != expected) {
1946                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1947                           reg, expected);
1948                 return ECORE_UNKNOWN_ERROR;
1949         }
1950
1951         return 0;
1952 }
1953
1954 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1955 {
1956         enum _ecore_status_t rc = ECORE_SUCCESS;
1957         u32 unload_resp, unload_param;
1958         int i;
1959
1960         for_each_hwfn(p_dev, i) {
1961                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1962
1963                 if (IS_VF(p_dev)) {
1964                         rc = ecore_vf_pf_reset(p_hwfn);
1965                         if (rc)
1966                                 return rc;
1967                         continue;
1968                 }
1969
1970                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1971
1972                 /* Check for incorrect states */
1973                 if (!p_dev->recov_in_prog) {
1974                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1975                                          QM_REG_USG_CNT_PF_TX, 0);
1976                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1977                                          QM_REG_USG_CNT_PF_OTHER, 0);
1978                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1979                 }
1980
1981                 /* Disable PF in HW blocks */
1982                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1983                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1984
1985                 if (p_dev->recov_in_prog) {
1986                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1987                                    "Recovery is in progress -> skip sending unload_req/done\n");
1988                         break;
1989                 }
1990
1991                 /* Send unload command to MCP */
1992                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1993                                    DRV_MSG_CODE_UNLOAD_REQ,
1994                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
1995                                    &unload_resp, &unload_param);
1996                 if (rc != ECORE_SUCCESS) {
1997                         DP_NOTICE(p_hwfn, true,
1998                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
1999                         /* @@TBD - what to do? for now, assume ENG. */
2000                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2001                 }
2002
2003                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2004                                    DRV_MSG_CODE_UNLOAD_DONE,
2005                                    0, &unload_resp, &unload_param);
2006                 if (rc != ECORE_SUCCESS) {
2007                         DP_NOTICE(p_hwfn,
2008                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2009                         /* @@@TBD - Should it really ASSERT here ? */
2010                         return rc;
2011                 }
2012         }
2013
2014         return rc;
2015 }
2016
2017 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2018 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2019 {
2020         ecore_ptt_pool_free(p_hwfn);
2021         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2022 }
2023
2024 /* Setup bar access */
2025 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2026 {
2027         /* clear indirect access */
2028         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2029                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2030                          PGLUE_B_REG_PGL_ADDR_E8_F0, 0);
2031                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2032                          PGLUE_B_REG_PGL_ADDR_EC_F0, 0);
2033                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2034                          PGLUE_B_REG_PGL_ADDR_F0_F0, 0);
2035                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2036                          PGLUE_B_REG_PGL_ADDR_F4_F0, 0);
2037         } else {
2038                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2039                          PGLUE_B_REG_PGL_ADDR_88_F0, 0);
2040                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2041                          PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
2042                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2043                          PGLUE_B_REG_PGL_ADDR_90_F0, 0);
2044                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2045                          PGLUE_B_REG_PGL_ADDR_94_F0, 0);
2046         }
2047
2048         /* Clean Previous errors if such exist */
2049         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2050                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2051
2052         /* enable internal target-read */
2053         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2054                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2055 }
2056
2057 static void get_function_id(struct ecore_hwfn *p_hwfn)
2058 {
2059         /* ME Register */
2060         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2061                                                   PXP_PF_ME_OPAQUE_ADDR);
2062
2063         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2064
2065         /* Bits 16-19 from the ME registers are the pf_num */
2066         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2067         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2068                                       PXP_CONCRETE_FID_PFID);
2069         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2070                                     PXP_CONCRETE_FID_PORT);
2071
2072         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2073                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2074                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2075 }
2076
2077 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2078 {
2079         u32 *feat_num = p_hwfn->hw_info.feat_num;
2080         struct ecore_sb_cnt_info sb_cnt_info;
2081         int num_features = 1;
2082
2083         /* L2 Queues require each: 1 status block. 1 L2 queue */
2084         feat_num[ECORE_PF_L2_QUE] =
2085             OSAL_MIN_T(u32,
2086                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2087                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2088
2089         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2090         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2091         feat_num[ECORE_VF_L2_QUE] =
2092                 OSAL_MIN_T(u32,
2093                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2094                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2095                            sb_cnt_info.sb_iov_cnt);
2096
2097         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2098                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2099                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2100                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2101                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2102                    RESC_NUM(p_hwfn, ECORE_SB),
2103                    num_features);
2104 }
2105
2106 static enum resource_id_enum
2107 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2108 {
2109         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2110
2111         switch (res_id) {
2112         case ECORE_SB:
2113                 mfw_res_id = RESOURCE_NUM_SB_E;
2114                 break;
2115         case ECORE_L2_QUEUE:
2116                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2117                 break;
2118         case ECORE_VPORT:
2119                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2120                 break;
2121         case ECORE_RSS_ENG:
2122                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2123                 break;
2124         case ECORE_PQ:
2125                 mfw_res_id = RESOURCE_NUM_PQ_E;
2126                 break;
2127         case ECORE_RL:
2128                 mfw_res_id = RESOURCE_NUM_RL_E;
2129                 break;
2130         case ECORE_MAC:
2131         case ECORE_VLAN:
2132                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2133                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2134                 break;
2135         case ECORE_ILT:
2136                 mfw_res_id = RESOURCE_ILT_E;
2137                 break;
2138         case ECORE_LL2_QUEUE:
2139                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2140                 break;
2141         case ECORE_RDMA_CNQ_RAM:
2142         case ECORE_CMDQS_CQS:
2143                 /* CNQ/CMDQS are the same resource */
2144                 mfw_res_id = RESOURCE_CQS_E;
2145                 break;
2146         case ECORE_RDMA_STATS_QUEUE:
2147                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2148                 break;
2149         default:
2150                 break;
2151         }
2152
2153         return mfw_res_id;
2154 }
2155
2156 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2157                                       enum ecore_resources res_id)
2158 {
2159         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2160         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2161         struct ecore_sb_cnt_info sb_cnt_info;
2162         u32 dflt_resc_num = 0;
2163
2164         switch (res_id) {
2165         case ECORE_SB:
2166                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2167                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2168                 dflt_resc_num = sb_cnt_info.sb_cnt;
2169                 break;
2170         case ECORE_L2_QUEUE:
2171                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2172                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2173                 break;
2174         case ECORE_VPORT:
2175                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2176                                  MAX_NUM_VPORTS_BB) / num_funcs;
2177                 break;
2178         case ECORE_RSS_ENG:
2179                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2180                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2181                 break;
2182         case ECORE_PQ:
2183                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2184                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2185                 break;
2186         case ECORE_RL:
2187                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2188                 break;
2189         case ECORE_MAC:
2190         case ECORE_VLAN:
2191                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2192                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2193                 break;
2194         case ECORE_ILT:
2195                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2196                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2197                 break;
2198         case ECORE_LL2_QUEUE:
2199                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2200                 break;
2201         case ECORE_RDMA_CNQ_RAM:
2202         case ECORE_CMDQS_CQS:
2203                 /* CNQ/CMDQS are the same resource */
2204                 /* @DPDK */
2205                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2206                 break;
2207         case ECORE_RDMA_STATS_QUEUE:
2208                 /* @DPDK */
2209                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2210                                  MAX_NUM_VPORTS_BB) / num_funcs;
2211                 break;
2212         default:
2213                 break;
2214         }
2215
2216         return dflt_resc_num;
2217 }
2218
2219 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2220 {
2221         switch (res_id) {
2222         case ECORE_SB:
2223                 return "SB";
2224         case ECORE_L2_QUEUE:
2225                 return "L2_QUEUE";
2226         case ECORE_VPORT:
2227                 return "VPORT";
2228         case ECORE_RSS_ENG:
2229                 return "RSS_ENG";
2230         case ECORE_PQ:
2231                 return "PQ";
2232         case ECORE_RL:
2233                 return "RL";
2234         case ECORE_MAC:
2235                 return "MAC";
2236         case ECORE_VLAN:
2237                 return "VLAN";
2238         case ECORE_RDMA_CNQ_RAM:
2239                 return "RDMA_CNQ_RAM";
2240         case ECORE_ILT:
2241                 return "ILT";
2242         case ECORE_LL2_QUEUE:
2243                 return "LL2_QUEUE";
2244         case ECORE_CMDQS_CQS:
2245                 return "CMDQS_CQS";
2246         case ECORE_RDMA_STATS_QUEUE:
2247                 return "RDMA_STATS_QUEUE";
2248         default:
2249                 return "UNKNOWN_RESOURCE";
2250         }
2251 }
2252
2253 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2254                                                    enum ecore_resources res_id,
2255                                                    bool drv_resc_alloc)
2256 {
2257         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2258         u32 *p_resc_num, *p_resc_start;
2259         struct resource_info resc_info;
2260         enum _ecore_status_t rc;
2261
2262         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2263         p_resc_start = &RESC_START(p_hwfn, res_id);
2264
2265         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2266         if (!dflt_resc_num) {
2267                 DP_ERR(p_hwfn,
2268                        "Failed to get default amount for resource %d [%s]\n",
2269                         res_id, ecore_hw_get_resc_name(res_id));
2270                 return ECORE_INVAL;
2271         }
2272         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2273
2274 #ifndef ASIC_ONLY
2275         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2276                 *p_resc_num = dflt_resc_num;
2277                 *p_resc_start = dflt_resc_start;
2278                 goto out;
2279         }
2280 #endif
2281
2282         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2283         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2284         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2285                 DP_ERR(p_hwfn,
2286                        "Failed to match resource %d with MFW resources\n",
2287                        res_id);
2288                 return ECORE_INVAL;
2289         }
2290
2291         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2292                                      &mcp_resp, &mcp_param);
2293         if (rc != ECORE_SUCCESS) {
2294                 DP_NOTICE(p_hwfn, true,
2295                           "MFW response failure for an allocation request for"
2296                           " resource %d [%s]\n",
2297                           res_id, ecore_hw_get_resc_name(res_id));
2298                 return rc;
2299         }
2300
2301         /* Default driver values are applied in the following cases:
2302          * - The resource allocation MB command is not supported by the MFW
2303          * - There is an internal error in the MFW while processing the request
2304          * - The resource ID is unknown to the MFW
2305          */
2306         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2307             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2308                 /* @DPDK */
2309                 DP_INFO(p_hwfn,
2310                         "Resource %d [%s]: No allocation info was received"
2311                         " [mcp_resp 0x%x]. Applying default values"
2312                         " [num %d, start %d].\n",
2313                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2314                         dflt_resc_num, dflt_resc_start);
2315
2316                 *p_resc_num = dflt_resc_num;
2317                 *p_resc_start = dflt_resc_start;
2318                 goto out;
2319         }
2320
2321         /* TBD - remove this when revising the handling of the SB resource */
2322         if (res_id == ECORE_SB) {
2323                 /* Excluding the slowpath SB */
2324                 resc_info.size -= 1;
2325                 resc_info.offset -= p_hwfn->enabled_func_idx;
2326         }
2327
2328         *p_resc_num = resc_info.size;
2329         *p_resc_start = resc_info.offset;
2330
2331         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2332                 DP_INFO(p_hwfn,
2333                         "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2334                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2335                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2336                         drv_resc_alloc ? " - Applying default values" : "");
2337                 if (drv_resc_alloc) {
2338                         *p_resc_num = dflt_resc_num;
2339                         *p_resc_start = dflt_resc_start;
2340                 }
2341         }
2342  out:
2343         return ECORE_SUCCESS;
2344 }
2345
2346 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2347                                               bool drv_resc_alloc)
2348 {
2349         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2350         enum _ecore_status_t rc;
2351         u8 res_id;
2352 #ifndef ASIC_ONLY
2353         u32 *resc_start = p_hwfn->hw_info.resc_start;
2354         u32 *resc_num = p_hwfn->hw_info.resc_num;
2355         /* For AH, an equal share of the ILT lines between the maximal number of
2356          * PFs is not enough for RoCE. This would be solved by the future
2357          * resource allocation scheme, but isn't currently present for
2358          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2359          * to work - the BB number of ILT lines divided by its max PFs number.
2360          */
2361         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2362 #endif
2363
2364         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2365                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2366                 if (rc != ECORE_SUCCESS)
2367                         return rc;
2368         }
2369
2370 #ifndef ASIC_ONLY
2371         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2372                 /* Reduced build contains less PQs */
2373                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2374                         resc_num[ECORE_PQ] = 32;
2375                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2376                             p_hwfn->enabled_func_idx;
2377                 }
2378
2379                 /* For AH emulation, since we have a possible maximal number of
2380                  * 16 enabled PFs, in case there are not enough ILT lines -
2381                  * allocate only first PF as RoCE and have all the other ETH
2382                  * only with less ILT lines.
2383                  */
2384                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2385                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2386                                                          resc_num[ECORE_ILT],
2387                                                          roce_min_ilt_lines);
2388         }
2389
2390         /* Correct the common ILT calculation if PF0 has more */
2391         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2392             p_hwfn->p_dev->b_is_emul_full &&
2393             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2394                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2395                     resc_num[ECORE_ILT];
2396 #endif
2397
2398         /* Sanity for ILT */
2399         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2400             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2401                 DP_NOTICE(p_hwfn, true,
2402                           "Can't assign ILT pages [%08x,...,%08x]\n",
2403                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2404                                                                   ECORE_ILT) -
2405                           1);
2406                 return ECORE_INVAL;
2407         }
2408
2409         ecore_hw_set_feat(p_hwfn);
2410
2411         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2412                    "The numbers for each resource are:\n");
2413         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2414                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2415                            ecore_hw_get_resc_name(res_id),
2416                            RESC_NUM(p_hwfn, res_id),
2417                            RESC_START(p_hwfn, res_id));
2418
2419         return ECORE_SUCCESS;
2420 }
2421
2422 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2423                                                   struct ecore_ptt *p_ptt)
2424 {
2425         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2426         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2427         struct ecore_mcp_link_params *link;
2428
2429         /* Read global nvm_cfg address */
2430         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2431
2432         /* Verify MCP has initialized it */
2433         if (!nvm_cfg_addr) {
2434                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2435                 return ECORE_INVAL;
2436         }
2437
2438 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2439
2440         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2441
2442         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2443             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2444                                                        core_cfg);
2445
2446         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2447
2448         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2449                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2450         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2451                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2452                 break;
2453         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2454                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2455                 break;
2456         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2457                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2458                 break;
2459         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2460                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2461                 break;
2462         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2463                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2464                 break;
2465         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2466                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2467                 break;
2468         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2469                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2470                 break;
2471         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2472                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2473                 break;
2474         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2475                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2476                 break;
2477         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2478                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2479                 break;
2480         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2481                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2482                 break;
2483         default:
2484                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2485                           core_cfg);
2486                 break;
2487         }
2488
2489         /* Read DCBX configuration */
2490         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2491                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2492         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2493                              port_cfg_addr +
2494                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2495         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2496                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2497         switch (dcbx_mode) {
2498         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2499                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2500                 break;
2501         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2502                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2503                 break;
2504         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2505                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2506                 break;
2507         default:
2508                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2509         }
2510
2511         /* Read default link configuration */
2512         link = &p_hwfn->mcp_info->link_input;
2513         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2514             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2515         link_temp = ecore_rd(p_hwfn, p_ptt,
2516                              port_cfg_addr +
2517                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2518         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2519         link->speed.advertised_speeds = link_temp;
2520
2521         link_temp = link->speed.advertised_speeds;
2522         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2523
2524         link_temp = ecore_rd(p_hwfn, p_ptt,
2525                              port_cfg_addr +
2526                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2527         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2528                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2529         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2530                 link->speed.autoneg = true;
2531                 break;
2532         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2533                 link->speed.forced_speed = 1000;
2534                 break;
2535         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2536                 link->speed.forced_speed = 10000;
2537                 break;
2538         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2539                 link->speed.forced_speed = 25000;
2540                 break;
2541         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2542                 link->speed.forced_speed = 40000;
2543                 break;
2544         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2545                 link->speed.forced_speed = 50000;
2546                 break;
2547         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2548                 link->speed.forced_speed = 100000;
2549                 break;
2550         default:
2551                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2552         }
2553
2554         p_hwfn->mcp_info->link_capabilities.default_speed =
2555             link->speed.forced_speed;
2556         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2557             link->speed.autoneg;
2558
2559         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2560         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2561         link->pause.autoneg = !!(link_temp &
2562                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2563         link->pause.forced_rx = !!(link_temp &
2564                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2565         link->pause.forced_tx = !!(link_temp &
2566                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2567         link->loopback_mode = 0;
2568
2569         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2570                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2571                    link->speed.forced_speed, link->speed.advertised_speeds,
2572                    link->speed.autoneg, link->pause.autoneg);
2573
2574         /* Read Multi-function information from shmem */
2575         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2576             OFFSETOF(struct nvm_cfg1, glob) +
2577             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2578
2579         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2580
2581         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2582             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2583
2584         switch (mf_mode) {
2585         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2586                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2587                 break;
2588         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2589                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2590                 break;
2591         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2592                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2593                 break;
2594         }
2595         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2596                 p_hwfn->p_dev->mf_mode);
2597
2598         /* Read Multi-function information from shmem */
2599         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2600             OFFSETOF(struct nvm_cfg1, glob) +
2601             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2602
2603         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2604         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2605                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2606                              &p_hwfn->hw_info.device_capabilities);
2607         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2608                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2609                              &p_hwfn->hw_info.device_capabilities);
2610         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2611                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2612                              &p_hwfn->hw_info.device_capabilities);
2613         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2614                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2615                              &p_hwfn->hw_info.device_capabilities);
2616         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2617                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2618                              &p_hwfn->hw_info.device_capabilities);
2619
2620         return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2621 }
2622
2623 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2624                                 struct ecore_ptt *p_ptt)
2625 {
2626         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2627         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2628         struct ecore_dev *p_dev = p_hwfn->p_dev;
2629
2630         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2631
2632         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2633          * in the other bits are selected.
2634          * Bits 1-15 are for functions 1-15, respectively, and their value is
2635          * '0' only for enabled functions (function 0 always exists and
2636          * enabled).
2637          * In case of CMT in BB, only the "even" functions are enabled, and thus
2638          * the number of functions for both hwfns is learnt from the same bits.
2639          */
2640         reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2641
2642         if (reg_function_hide & 0x1) {
2643                 if (ECORE_IS_BB(p_dev)) {
2644                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2645                                 num_funcs = 0;
2646                                 eng_mask = 0xaaaa;
2647                         } else {
2648                                 num_funcs = 1;
2649                                 eng_mask = 0x5554;
2650                         }
2651                 } else {
2652                         num_funcs = 1;
2653                         eng_mask = 0xfffe;
2654                 }
2655
2656                 /* Get the number of the enabled functions on the engine */
2657                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2658                 while (tmp) {
2659                         if (tmp & 0x1)
2660                                 num_funcs++;
2661                         tmp >>= 0x1;
2662                 }
2663
2664                 /* Get the PF index within the enabled functions */
2665                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2666                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2667                 while (tmp) {
2668                         if (tmp & 0x1)
2669                                 enabled_func_idx--;
2670                         tmp >>= 0x1;
2671                 }
2672         }
2673
2674         p_hwfn->num_funcs_on_engine = num_funcs;
2675         p_hwfn->enabled_func_idx = enabled_func_idx;
2676
2677 #ifndef ASIC_ONLY
2678         if (CHIP_REV_IS_FPGA(p_dev)) {
2679                 DP_NOTICE(p_hwfn, false,
2680                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2681                 p_hwfn->num_funcs_on_engine = 4;
2682         }
2683 #endif
2684
2685         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2686                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2687                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2688                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2689 }
2690
2691 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2692                                       struct ecore_ptt *p_ptt)
2693 {
2694         u32 port_mode;
2695
2696 #ifndef ASIC_ONLY
2697         /* Read the port mode */
2698         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2699                 port_mode = 4;
2700         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2701                  (p_hwfn->p_dev->num_hwfns > 1))
2702                 /* In CMT on emulation, assume 1 port */
2703                 port_mode = 1;
2704         else
2705 #endif
2706                 port_mode = ecore_rd(p_hwfn, p_ptt,
2707                                      CNIG_REG_NW_PORT_MODE_BB_B0);
2708
2709         if (port_mode < 3) {
2710                 p_hwfn->p_dev->num_ports_in_engines = 1;
2711         } else if (port_mode <= 5) {
2712                 p_hwfn->p_dev->num_ports_in_engines = 2;
2713         } else {
2714                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2715                           p_hwfn->p_dev->num_ports_in_engines);
2716
2717                 /* Default num_ports_in_engines to something */
2718                 p_hwfn->p_dev->num_ports_in_engines = 1;
2719         }
2720 }
2721
2722 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2723                                       struct ecore_ptt *p_ptt)
2724 {
2725         u32 port;
2726         int i;
2727
2728         p_hwfn->p_dev->num_ports_in_engines = 0;
2729
2730 #ifndef ASIC_ONLY
2731         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2732                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2733                 switch ((port & 0xf000) >> 12) {
2734                 case 1:
2735                         p_hwfn->p_dev->num_ports_in_engines = 1;
2736                         break;
2737                 case 3:
2738                         p_hwfn->p_dev->num_ports_in_engines = 2;
2739                         break;
2740                 case 0xf:
2741                         p_hwfn->p_dev->num_ports_in_engines = 4;
2742                         break;
2743                 default:
2744                         DP_NOTICE(p_hwfn, false,
2745                                   "Unknown port mode in ECO_RESERVED %08x\n",
2746                                   port);
2747                 }
2748         } else
2749 #endif
2750                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2751                         port = ecore_rd(p_hwfn, p_ptt,
2752                                         CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2753                         if (port & 1)
2754                                 p_hwfn->p_dev->num_ports_in_engines++;
2755                 }
2756 }
2757
2758 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2759                                    struct ecore_ptt *p_ptt)
2760 {
2761         if (ECORE_IS_BB(p_hwfn->p_dev))
2762                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2763         else
2764                 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2765 }
2766
2767 static enum _ecore_status_t
2768 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2769                   enum ecore_pci_personality personality, bool drv_resc_alloc)
2770 {
2771         enum _ecore_status_t rc;
2772
2773         /* Since all information is common, only first hwfns should do this */
2774         if (IS_LEAD_HWFN(p_hwfn)) {
2775                 rc = ecore_iov_hw_info(p_hwfn);
2776                 if (rc != ECORE_SUCCESS)
2777                         return rc;
2778         }
2779
2780         /* TODO In get_hw_info, amoungst others:
2781          * Get MCP FW revision and determine according to it the supported
2782          * featrues (e.g. DCB)
2783          * Get boot mode
2784          * ecore_get_pcie_width_speed, WOL capability.
2785          * Number of global CQ-s (for storage
2786          */
2787         ecore_hw_info_port_num(p_hwfn, p_ptt);
2788
2789 #ifndef ASIC_ONLY
2790         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2791 #endif
2792         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2793         if (rc != ECORE_SUCCESS)
2794                 return rc;
2795 #ifndef ASIC_ONLY
2796         }
2797 #endif
2798
2799         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2800         if (rc != ECORE_SUCCESS)
2801                 return rc;
2802
2803 #ifndef ASIC_ONLY
2804         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2805 #endif
2806                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2807                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2808 #ifndef ASIC_ONLY
2809         } else {
2810                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2811
2812                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2813                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2814         }
2815 #endif
2816
2817         if (ecore_mcp_is_init(p_hwfn)) {
2818                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2819                         p_hwfn->hw_info.ovlan =
2820                             p_hwfn->mcp_info->func_info.ovlan;
2821
2822                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2823         }
2824
2825         if (personality != ECORE_PCI_DEFAULT) {
2826                 p_hwfn->hw_info.personality = personality;
2827         } else if (ecore_mcp_is_init(p_hwfn)) {
2828                 enum ecore_pci_personality protocol;
2829
2830                 protocol = p_hwfn->mcp_info->func_info.protocol;
2831                 p_hwfn->hw_info.personality = protocol;
2832         }
2833
2834 #ifndef ASIC_ONLY
2835         /* To overcome ILT lack for emulation, until at least until we'll have
2836          * a definite answer from system about it, allow only PF0 to be RoCE.
2837          */
2838         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2839                 if (!p_hwfn->rel_pf_id)
2840                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2841                 else
2842                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2843         }
2844 #endif
2845
2846         /* although in BB some constellations may support more than 4 tcs,
2847          * that can result in performance penalty in some cases. 4
2848          * represents a good tradeoff between performance and flexibility.
2849          */
2850         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2851
2852         /* start out with a single active tc. This can be increased either
2853          * by dcbx negotiation or by upper layer driver
2854          */
2855         p_hwfn->hw_info.num_active_tc = 1;
2856
2857         ecore_get_num_funcs(p_hwfn, p_ptt);
2858
2859         /* In case of forcing the driver's default resource allocation, calling
2860          * ecore_hw_get_resc() should come after initializing the personality
2861          * and after getting the number of functions, since the calculation of
2862          * the resources/features depends on them.
2863          * This order is not harmful if not forcing.
2864          */
2865         return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2866 }
2867
2868 #define ECORE_DEV_ID_MASK       0xff00
2869 #define ECORE_DEV_ID_MASK_BB    0x1600
2870 #define ECORE_DEV_ID_MASK_AH    0x8000
2871
2872 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2873 {
2874         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2875         u32 tmp;
2876
2877         /* Read Vendor Id / Device Id */
2878         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2879                                   &p_dev->vendor_id);
2880         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2881                                   &p_dev->device_id);
2882
2883         /* Determine type */
2884         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2885                 p_dev->type = ECORE_DEV_TYPE_AH;
2886         else
2887                 p_dev->type = ECORE_DEV_TYPE_BB;
2888
2889         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2890                                          MISCS_REG_CHIP_NUM);
2891         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2892                                          MISCS_REG_CHIP_REV);
2893
2894         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2895
2896         /* Learn number of HW-functions */
2897         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2898                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2899
2900         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2901                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2902                 p_dev->num_hwfns = 2;
2903         } else {
2904                 p_dev->num_hwfns = 1;
2905         }
2906
2907 #ifndef ASIC_ONLY
2908         if (CHIP_REV_IS_EMUL(p_dev)) {
2909                 /* For some reason we have problems with this register
2910                  * in B0 emulation; Simply assume no CMT
2911                  */
2912                 DP_NOTICE(p_dev->hwfns, false,
2913                           "device on emul - assume no CMT\n");
2914                 p_dev->num_hwfns = 1;
2915         }
2916 #endif
2917
2918         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2919                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2920         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2921         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2922                                            MISCS_REG_CHIP_METAL);
2923         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2924         DP_INFO(p_dev->hwfns,
2925                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2926                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2927                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
2928                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2929                 p_dev->chip_metal);
2930
2931         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2932                 DP_NOTICE(p_dev->hwfns, false,
2933                           "The chip type/rev (BB A0) is not supported!\n");
2934                 return ECORE_ABORTED;
2935         }
2936 #ifndef ASIC_ONLY
2937         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2938                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2939                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2940
2941         if (CHIP_REV_IS_EMUL(p_dev)) {
2942                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2943                                MISCS_REG_ECO_RESERVED);
2944                 if (tmp & (1 << 29)) {
2945                         DP_NOTICE(p_hwfn, false,
2946                                   "Emulation: Running on a FULL build\n");
2947                         p_dev->b_is_emul_full = true;
2948                 } else {
2949                         DP_NOTICE(p_hwfn, false,
2950                                   "Emulation: Running on a REDUCED build\n");
2951                 }
2952         }
2953 #endif
2954
2955         return ECORE_SUCCESS;
2956 }
2957
2958 #ifndef LINUX_REMOVE
2959 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2960 {
2961         int j;
2962
2963         if (IS_VF(p_dev))
2964                 return;
2965
2966         for_each_hwfn(p_dev, j) {
2967                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2968
2969                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2970                            "Mark hw/fw uninitialized\n");
2971
2972                 p_hwfn->hw_init_done = false;
2973                 p_hwfn->first_on_engine = false;
2974
2975                 ecore_ptt_invalidate(p_hwfn);
2976         }
2977 }
2978 #endif
2979
2980 static enum _ecore_status_t
2981 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2982                         void OSAL_IOMEM * p_regview,
2983                         void OSAL_IOMEM * p_doorbells,
2984                         struct ecore_hw_prepare_params *p_params)
2985 {
2986         struct ecore_dev *p_dev = p_hwfn->p_dev;
2987         struct ecore_mdump_info mdump_info;
2988         enum _ecore_status_t rc = ECORE_SUCCESS;
2989
2990         /* Split PCI bars evenly between hwfns */
2991         p_hwfn->regview = p_regview;
2992         p_hwfn->doorbells = p_doorbells;
2993
2994         if (IS_VF(p_dev))
2995                 return ecore_vf_hw_prepare(p_hwfn);
2996
2997         /* Validate that chip access is feasible */
2998         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2999                 DP_ERR(p_hwfn,
3000                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3001                 return ECORE_INVAL;
3002         }
3003
3004         get_function_id(p_hwfn);
3005
3006         /* Allocate PTT pool */
3007         rc = ecore_ptt_pool_alloc(p_hwfn);
3008         if (rc) {
3009                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3010                 goto err0;
3011         }
3012
3013         /* Allocate the main PTT */
3014         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3015
3016         /* First hwfn learns basic information, e.g., number of hwfns */
3017         if (!p_hwfn->my_id) {
3018                 rc = ecore_get_dev_info(p_dev);
3019                 if (rc != ECORE_SUCCESS)
3020                         goto err1;
3021         }
3022
3023         ecore_hw_hwfn_prepare(p_hwfn);
3024
3025         /* Initialize MCP structure */
3026         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3027         if (rc) {
3028                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3029                 goto err1;
3030         }
3031
3032         /* Read the device configuration information from the HW and SHMEM */
3033         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3034                                p_params->personality, p_params->drv_resc_alloc);
3035         if (rc) {
3036                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3037                 goto err2;
3038         }
3039
3040         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3041          * called, since among others it sets the ports number in an engine.
3042          */
3043         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3044             !p_dev->recov_in_prog) {
3045                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3046                 if (rc != ECORE_SUCCESS)
3047                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3048         }
3049
3050         /* Check if mdump logs are present and update the epoch value */
3051         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3052                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3053                                               &mdump_info);
3054                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3055                         DP_NOTICE(p_hwfn, false,
3056                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3057                 }
3058
3059                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3060                                            p_params->epoch);
3061         }
3062
3063         /* Allocate the init RT array and initialize the init-ops engine */
3064         rc = ecore_init_alloc(p_hwfn);
3065         if (rc) {
3066                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3067                 goto err2;
3068         }
3069 #ifndef ASIC_ONLY
3070         if (CHIP_REV_IS_FPGA(p_dev)) {
3071                 DP_NOTICE(p_hwfn, false,
3072                           "FPGA: workaround; Prevent DMAE parities\n");
3073                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
3074
3075                 DP_NOTICE(p_hwfn, false,
3076                           "FPGA: workaround: Set VF bar0 size\n");
3077                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3078                          PGLUE_B_REG_VF_BAR0_SIZE, 4);
3079         }
3080 #endif
3081
3082         return rc;
3083  err2:
3084         if (IS_LEAD_HWFN(p_hwfn))
3085                 ecore_iov_free_hw_info(p_dev);
3086         ecore_mcp_free(p_hwfn);
3087  err1:
3088         ecore_hw_hwfn_free(p_hwfn);
3089  err0:
3090         return rc;
3091 }
3092
3093 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3094                                       struct ecore_hw_prepare_params *p_params)
3095 {
3096         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3097         enum _ecore_status_t rc;
3098
3099         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3100
3101         /* Store the precompiled init data ptrs */
3102         if (IS_PF(p_dev))
3103                 ecore_init_iro_array(p_dev);
3104
3105         /* Initialize the first hwfn - will learn number of hwfns */
3106         rc = ecore_hw_prepare_single(p_hwfn,
3107                                      p_dev->regview,
3108                                      p_dev->doorbells, p_params);
3109         if (rc != ECORE_SUCCESS)
3110                 return rc;
3111
3112         p_params->personality = p_hwfn->hw_info.personality;
3113
3114         /* initilalize 2nd hwfn if necessary */
3115         if (p_dev->num_hwfns > 1) {
3116                 void OSAL_IOMEM *p_regview, *p_doorbell;
3117                 u8 OSAL_IOMEM *addr;
3118
3119                 /* adjust bar offset for second engine */
3120                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3121                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3122                 p_regview = (void OSAL_IOMEM *)addr;
3123
3124                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3125                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3126                 p_doorbell = (void OSAL_IOMEM *)addr;
3127
3128                 /* prepare second hw function */
3129                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3130                                              p_doorbell, p_params);
3131
3132                 /* in case of error, need to free the previously
3133                  * initiliazed hwfn 0.
3134                  */
3135                 if (rc != ECORE_SUCCESS) {
3136                         if (IS_PF(p_dev)) {
3137                                 ecore_init_free(p_hwfn);
3138                                 ecore_mcp_free(p_hwfn);
3139                                 ecore_hw_hwfn_free(p_hwfn);
3140                         } else {
3141                                 DP_NOTICE(p_dev, true,
3142                                           "What do we need to free when VF hwfn1 init fails\n");
3143                         }
3144                         return rc;
3145                 }
3146         }
3147
3148         return rc;
3149 }
3150
3151 void ecore_hw_remove(struct ecore_dev *p_dev)
3152 {
3153         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3154         int i;
3155
3156         if (IS_PF(p_dev))
3157                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3158                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3159
3160         for_each_hwfn(p_dev, i) {
3161                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3162
3163                 if (IS_VF(p_dev)) {
3164                         ecore_vf_pf_release(p_hwfn);
3165                         continue;
3166                 }
3167
3168                 ecore_init_free(p_hwfn);
3169                 ecore_hw_hwfn_free(p_hwfn);
3170                 ecore_mcp_free(p_hwfn);
3171
3172                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3173         }
3174
3175         ecore_iov_free_hw_info(p_dev);
3176 }
3177
3178 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3179                                       struct ecore_chain *p_chain)
3180 {
3181         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3182         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3183         struct ecore_chain_next *p_next;
3184         u32 size, i;
3185
3186         if (!p_virt)
3187                 return;
3188
3189         size = p_chain->elem_size * p_chain->usable_per_page;
3190
3191         for (i = 0; i < p_chain->page_cnt; i++) {
3192                 if (!p_virt)
3193                         break;
3194
3195                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3196                 p_virt_next = p_next->next_virt;
3197                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3198
3199                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3200                                        ECORE_CHAIN_PAGE_SIZE);
3201
3202                 p_virt = p_virt_next;
3203                 p_phys = p_phys_next;
3204         }
3205 }
3206
3207 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3208                                     struct ecore_chain *p_chain)
3209 {
3210         if (!p_chain->p_virt_addr)
3211                 return;
3212
3213         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3214                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3215 }
3216
3217 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3218                                  struct ecore_chain *p_chain)
3219 {
3220         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3221         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3222         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3223
3224         if (!pp_virt_addr_tbl)
3225                 return;
3226
3227         if (!p_chain->pbl.p_virt_table)
3228                 goto out;
3229
3230         for (i = 0; i < page_cnt; i++) {
3231                 if (!pp_virt_addr_tbl[i])
3232                         break;
3233
3234                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3235                                        *(dma_addr_t *)p_pbl_virt,
3236                                        ECORE_CHAIN_PAGE_SIZE);
3237
3238                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3239         }
3240
3241         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3242
3243         if (!p_chain->pbl.external)
3244                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3245                                        p_chain->pbl.p_phys_table, pbl_size);
3246  out:
3247         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3248 }
3249
3250 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3251 {
3252         switch (p_chain->mode) {
3253         case ECORE_CHAIN_MODE_NEXT_PTR:
3254                 ecore_chain_free_next_ptr(p_dev, p_chain);
3255                 break;
3256         case ECORE_CHAIN_MODE_SINGLE:
3257                 ecore_chain_free_single(p_dev, p_chain);
3258                 break;
3259         case ECORE_CHAIN_MODE_PBL:
3260                 ecore_chain_free_pbl(p_dev, p_chain);
3261                 break;
3262         }
3263 }
3264
3265 static enum _ecore_status_t
3266 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3267                                enum ecore_chain_cnt_type cnt_type,
3268                                osal_size_t elem_size, u32 page_cnt)
3269 {
3270         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3271
3272         /* The actual chain size can be larger than the maximal possible value
3273          * after rounding up the requested elements number to pages, and after
3274          * taking into acount the unusuable elements (next-ptr elements).
3275          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3276          * size/capacity fields are of a u32 type.
3277          */
3278         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3279              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3280             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3281              chain_size > ECORE_U32_MAX)) {
3282                 DP_NOTICE(p_dev, true,
3283                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3284                           (unsigned long)chain_size);
3285                 return ECORE_INVAL;
3286         }
3287
3288         return ECORE_SUCCESS;
3289 }
3290
3291 static enum _ecore_status_t
3292 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3293 {
3294         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3295         dma_addr_t p_phys = 0;
3296         u32 i;
3297
3298         for (i = 0; i < p_chain->page_cnt; i++) {
3299                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3300                                                  ECORE_CHAIN_PAGE_SIZE);
3301                 if (!p_virt) {
3302                         DP_NOTICE(p_dev, true,
3303                                   "Failed to allocate chain memory\n");
3304                         return ECORE_NOMEM;
3305                 }
3306
3307                 if (i == 0) {
3308                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3309                         ecore_chain_reset(p_chain);
3310                 } else {
3311                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3312                                                        p_virt, p_phys);
3313                 }
3314
3315                 p_virt_prev = p_virt;
3316         }
3317         /* Last page's next element should point to the beginning of the
3318          * chain.
3319          */
3320         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3321                                        p_chain->p_virt_addr,
3322                                        p_chain->p_phys_addr);
3323
3324         return ECORE_SUCCESS;
3325 }
3326
3327 static enum _ecore_status_t
3328 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3329 {
3330         dma_addr_t p_phys = 0;
3331         void *p_virt = OSAL_NULL;
3332
3333         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3334         if (!p_virt) {
3335                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3336                 return ECORE_NOMEM;
3337         }
3338
3339         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3340         ecore_chain_reset(p_chain);
3341
3342         return ECORE_SUCCESS;
3343 }
3344
3345 static enum _ecore_status_t
3346 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3347                       struct ecore_chain *p_chain,
3348                       struct ecore_chain_ext_pbl *ext_pbl)
3349 {
3350         void *p_virt = OSAL_NULL;
3351         u8 *p_pbl_virt = OSAL_NULL;
3352         void **pp_virt_addr_tbl = OSAL_NULL;
3353         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3354         u32 page_cnt = p_chain->page_cnt, size, i;
3355
3356         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3357         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3358         if (!pp_virt_addr_tbl) {
3359                 DP_NOTICE(p_dev, true,
3360                           "Failed to allocate memory for the chain virtual addresses table\n");
3361                 return ECORE_NOMEM;
3362         }
3363         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3364
3365         /* The allocation of the PBL table is done with its full size, since it
3366          * is expected to be successive.
3367          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3368          * failure, since pp_virt_addr_tbl was previously allocated, and it
3369          * should be saved to allow its freeing during the error flow.
3370          */
3371         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3372
3373         if (ext_pbl == OSAL_NULL) {
3374                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3375         } else {
3376                 p_pbl_virt = ext_pbl->p_pbl_virt;
3377                 p_pbl_phys = ext_pbl->p_pbl_phys;
3378                 p_chain->pbl.external = true;
3379         }
3380
3381         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3382                                  pp_virt_addr_tbl);
3383         if (!p_pbl_virt) {
3384                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3385                 return ECORE_NOMEM;
3386         }
3387
3388         for (i = 0; i < page_cnt; i++) {
3389                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3390                                                  ECORE_CHAIN_PAGE_SIZE);
3391                 if (!p_virt) {
3392                         DP_NOTICE(p_dev, true,
3393                                   "Failed to allocate chain memory\n");
3394                         return ECORE_NOMEM;
3395                 }
3396
3397                 if (i == 0) {
3398                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3399                         ecore_chain_reset(p_chain);
3400                 }
3401
3402                 /* Fill the PBL table with the physical address of the page */
3403                 *(dma_addr_t *)p_pbl_virt = p_phys;
3404                 /* Keep the virtual address of the page */
3405                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3406
3407                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3408         }
3409
3410         return ECORE_SUCCESS;
3411 }
3412
3413 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3414                                        enum ecore_chain_use_mode intended_use,
3415                                        enum ecore_chain_mode mode,
3416                                        enum ecore_chain_cnt_type cnt_type,
3417                                        u32 num_elems, osal_size_t elem_size,
3418                                        struct ecore_chain *p_chain,
3419                                        struct ecore_chain_ext_pbl *ext_pbl)
3420 {
3421         u32 page_cnt;
3422         enum _ecore_status_t rc = ECORE_SUCCESS;
3423
3424         if (mode == ECORE_CHAIN_MODE_SINGLE)
3425                 page_cnt = 1;
3426         else
3427                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3428
3429         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3430                                             page_cnt);
3431         if (rc) {
3432                 DP_NOTICE(p_dev, true,
3433                           "Cannot allocate a chain with the given arguments:\n"
3434                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3435                           intended_use, mode, cnt_type, num_elems, elem_size);
3436                 return rc;
3437         }
3438
3439         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3440                                 mode, cnt_type, p_dev->dp_ctx);
3441
3442         switch (mode) {
3443         case ECORE_CHAIN_MODE_NEXT_PTR:
3444                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3445                 break;
3446         case ECORE_CHAIN_MODE_SINGLE:
3447                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3448                 break;
3449         case ECORE_CHAIN_MODE_PBL:
3450                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3451                 break;
3452         }
3453         if (rc)
3454                 goto nomem;
3455
3456         return ECORE_SUCCESS;
3457
3458  nomem:
3459         ecore_chain_free(p_dev, p_chain);
3460         return rc;
3461 }
3462
3463 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3464                                        u16 src_id, u16 *dst_id)
3465 {
3466         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3467                 u16 min, max;
3468
3469                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3470                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3471                 DP_NOTICE(p_hwfn, true,
3472                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3473                           src_id, min, max);
3474
3475                 return ECORE_INVAL;
3476         }
3477
3478         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3479
3480         return ECORE_SUCCESS;
3481 }
3482
3483 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3484                                     u8 src_id, u8 *dst_id)
3485 {
3486         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3487                 u8 min, max;
3488
3489                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3490                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3491                 DP_NOTICE(p_hwfn, true,
3492                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3493                           src_id, min, max);
3494
3495                 return ECORE_INVAL;
3496         }
3497
3498         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3499
3500         return ECORE_SUCCESS;
3501 }
3502
3503 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3504                                       u8 src_id, u8 *dst_id)
3505 {
3506         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3507                 u8 min, max;
3508
3509                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3510                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3511                 DP_NOTICE(p_hwfn, true,
3512                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3513                           src_id, min, max);
3514
3515                 return ECORE_INVAL;
3516         }
3517
3518         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3519
3520         return ECORE_SUCCESS;
3521 }
3522
3523 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3524                                               struct ecore_ptt *p_ptt,
3525                                               u8 *p_filter)
3526 {
3527         u32 high, low, en;
3528         int i;
3529
3530         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3531                 return ECORE_SUCCESS;
3532
3533         high = p_filter[1] | (p_filter[0] << 8);
3534         low = p_filter[5] | (p_filter[4] << 8) |
3535             (p_filter[3] << 16) | (p_filter[2] << 24);
3536
3537         /* Find a free entry and utilize it */
3538         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3539                 en = ecore_rd(p_hwfn, p_ptt,
3540                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3541                 if (en)
3542                         continue;
3543                 ecore_wr(p_hwfn, p_ptt,
3544                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3545                          2 * i * sizeof(u32), low);
3546                 ecore_wr(p_hwfn, p_ptt,
3547                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3548                          (2 * i + 1) * sizeof(u32), high);
3549                 ecore_wr(p_hwfn, p_ptt,
3550                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3551                 ecore_wr(p_hwfn, p_ptt,
3552                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3553                          i * sizeof(u32), 0);
3554                 ecore_wr(p_hwfn, p_ptt,
3555                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3556                 break;
3557         }
3558         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3559                 DP_NOTICE(p_hwfn, false,
3560                           "Failed to find an empty LLH filter to utilize\n");
3561                 return ECORE_INVAL;
3562         }
3563
3564         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3565                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3566                    p_filter[0], p_filter[1], p_filter[2],
3567                    p_filter[3], p_filter[4], p_filter[5], i);
3568
3569         return ECORE_SUCCESS;
3570 }
3571
3572 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3573                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3574 {
3575         u32 high, low;
3576         int i;
3577
3578         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3579                 return;
3580
3581         high = p_filter[1] | (p_filter[0] << 8);
3582         low = p_filter[5] | (p_filter[4] << 8) |
3583             (p_filter[3] << 16) | (p_filter[2] << 24);
3584
3585         /* Find the entry and clean it */
3586         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3587                 if (ecore_rd(p_hwfn, p_ptt,
3588                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3589                              2 * i * sizeof(u32)) != low)
3590                         continue;
3591                 if (ecore_rd(p_hwfn, p_ptt,
3592                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3593                              (2 * i + 1) * sizeof(u32)) != high)
3594                         continue;
3595
3596                 ecore_wr(p_hwfn, p_ptt,
3597                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3598                 ecore_wr(p_hwfn, p_ptt,
3599                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3600                          2 * i * sizeof(u32), 0);
3601                 ecore_wr(p_hwfn, p_ptt,
3602                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3603                          (2 * i + 1) * sizeof(u32), 0);
3604                 break;
3605         }
3606         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3607                 DP_NOTICE(p_hwfn, false,
3608                           "Tried to remove a non-configured filter\n");
3609 }
3610
3611 enum _ecore_status_t
3612 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3613                               struct ecore_ptt *p_ptt,
3614                               u16 source_port_or_eth_type,
3615                               u16 dest_port,
3616                               enum ecore_llh_port_filter_type_t type)
3617 {
3618         u32 high, low, en;
3619         int i;
3620
3621         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3622                 return ECORE_SUCCESS;
3623
3624         high = 0;
3625         low = 0;
3626         switch (type) {
3627         case ECORE_LLH_FILTER_ETHERTYPE:
3628                 high = source_port_or_eth_type;
3629                 break;
3630         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3631         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3632                 low = source_port_or_eth_type << 16;
3633                 break;
3634         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3635         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3636                 low = dest_port;
3637                 break;
3638         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3639         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3640                 low = (source_port_or_eth_type << 16) | dest_port;
3641                 break;
3642         default:
3643                 DP_NOTICE(p_hwfn, true,
3644                           "Non valid LLH protocol filter type %d\n", type);
3645                 return ECORE_INVAL;
3646         }
3647         /* Find a free entry and utilize it */
3648         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3649                 en = ecore_rd(p_hwfn, p_ptt,
3650                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3651                 if (en)
3652                         continue;
3653                 ecore_wr(p_hwfn, p_ptt,
3654                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3655                          2 * i * sizeof(u32), low);
3656                 ecore_wr(p_hwfn, p_ptt,
3657                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3658                          (2 * i + 1) * sizeof(u32), high);
3659                 ecore_wr(p_hwfn, p_ptt,
3660                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3661                 ecore_wr(p_hwfn, p_ptt,
3662                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3663                          i * sizeof(u32), 1 << type);
3664                 ecore_wr(p_hwfn, p_ptt,
3665                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3666                 break;
3667         }
3668         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3669                 DP_NOTICE(p_hwfn, false,
3670                           "Failed to find an empty LLH filter to utilize\n");
3671                 return ECORE_NORESOURCES;
3672         }
3673         switch (type) {
3674         case ECORE_LLH_FILTER_ETHERTYPE:
3675                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3676                            "ETH type %x is added at %d\n",
3677                            source_port_or_eth_type, i);
3678                 break;
3679         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3680                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3681                            "TCP src port %x is added at %d\n",
3682                            source_port_or_eth_type, i);
3683                 break;
3684         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3685                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3686                            "UDP src port %x is added at %d\n",
3687                            source_port_or_eth_type, i);
3688                 break;
3689         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3690                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3691                            "TCP dst port %x is added at %d\n", dest_port, i);
3692                 break;
3693         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3694                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3695                            "UDP dst port %x is added at %d\n", dest_port, i);
3696                 break;
3697         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3698                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3699                            "TCP src/dst ports %x/%x are added at %d\n",
3700                            source_port_or_eth_type, dest_port, i);
3701                 break;
3702         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3703                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3704                            "UDP src/dst ports %x/%x are added at %d\n",
3705                            source_port_or_eth_type, dest_port, i);
3706                 break;
3707         }
3708         return ECORE_SUCCESS;
3709 }
3710
3711 void
3712 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3713                                  struct ecore_ptt *p_ptt,
3714                                  u16 source_port_or_eth_type,
3715                                  u16 dest_port,
3716                                  enum ecore_llh_port_filter_type_t type)
3717 {
3718         u32 high, low;
3719         int i;
3720
3721         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3722                 return;
3723
3724         high = 0;
3725         low = 0;
3726         switch (type) {
3727         case ECORE_LLH_FILTER_ETHERTYPE:
3728                 high = source_port_or_eth_type;
3729                 break;
3730         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3731         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3732                 low = source_port_or_eth_type << 16;
3733                 break;
3734         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3735         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3736                 low = dest_port;
3737                 break;
3738         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3739         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3740                 low = (source_port_or_eth_type << 16) | dest_port;
3741                 break;
3742         default:
3743                 DP_NOTICE(p_hwfn, true,
3744                           "Non valid LLH protocol filter type %d\n", type);
3745                 return;
3746         }
3747
3748         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3749                 if (!ecore_rd(p_hwfn, p_ptt,
3750                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3751                         continue;
3752                 if (!ecore_rd(p_hwfn, p_ptt,
3753                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3754                         continue;
3755                 if (!(ecore_rd(p_hwfn, p_ptt,
3756                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3757                                i * sizeof(u32)) & (1 << type)))
3758                         continue;
3759                 if (ecore_rd(p_hwfn, p_ptt,
3760                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3761                              2 * i * sizeof(u32)) != low)
3762                         continue;
3763                 if (ecore_rd(p_hwfn, p_ptt,
3764                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3765                              (2 * i + 1) * sizeof(u32)) != high)
3766                         continue;
3767
3768                 ecore_wr(p_hwfn, p_ptt,
3769                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3770                 ecore_wr(p_hwfn, p_ptt,
3771                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3772                 ecore_wr(p_hwfn, p_ptt,
3773                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3774                          i * sizeof(u32), 0);
3775                 ecore_wr(p_hwfn, p_ptt,
3776                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3777                          2 * i * sizeof(u32), 0);
3778                 ecore_wr(p_hwfn, p_ptt,
3779                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3780                          (2 * i + 1) * sizeof(u32), 0);
3781                 break;
3782         }
3783
3784         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3785                 DP_NOTICE(p_hwfn, false,
3786                           "Tried to remove a non-configured filter\n");
3787 }
3788
3789 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3790                                  struct ecore_ptt *p_ptt)
3791 {
3792         int i;
3793
3794         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3795                 return;
3796
3797         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3798                 ecore_wr(p_hwfn, p_ptt,
3799                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3800                 ecore_wr(p_hwfn, p_ptt,
3801                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3802                          2 * i * sizeof(u32), 0);
3803                 ecore_wr(p_hwfn, p_ptt,
3804                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3805                          (2 * i + 1) * sizeof(u32), 0);
3806         }
3807 }
3808
3809 enum _ecore_status_t
3810 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3811                                   struct ecore_ptt *p_ptt)
3812 {
3813         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3814                 ecore_wr(p_hwfn, p_ptt,
3815                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3816                          1 << p_hwfn->abs_pf_id / 2);
3817                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3818                 return ECORE_SUCCESS;
3819         }
3820
3821         DP_NOTICE(p_hwfn, false,
3822                   "This function can't be set as default\n");
3823         return ECORE_INVAL;
3824 }
3825
3826 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3827                                                struct ecore_ptt *p_ptt,
3828                                                u32 hw_addr, void *p_eth_qzone,
3829                                                osal_size_t eth_qzone_size,
3830                                                u8 timeset)
3831 {
3832         struct coalescing_timeset *p_coal_timeset;
3833
3834         if (IS_VF(p_hwfn->p_dev)) {
3835                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3836                 return ECORE_INVAL;
3837         }
3838
3839         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3840                 DP_NOTICE(p_hwfn, true,
3841                           "Coalescing configuration not enabled\n");
3842                 return ECORE_INVAL;
3843         }
3844
3845         p_coal_timeset = p_eth_qzone;
3846         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3847         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3848         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3849         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3850
3851         return ECORE_SUCCESS;
3852 }
3853
3854 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3855                                             struct ecore_ptt *p_ptt,
3856                                             u16 coalesce, u8 qid, u16 sb_id)
3857 {
3858         struct ustorm_eth_queue_zone eth_qzone;
3859         u8 timeset, timer_res;
3860         u16 fw_qid = 0;
3861         u32 address;
3862         enum _ecore_status_t rc;
3863
3864         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3865         if (coalesce <= 0x7F) {
3866                 timer_res = 0;
3867         } else if (coalesce <= 0xFF) {
3868                 timer_res = 1;
3869         } else if (coalesce <= 0x1FF) {
3870                 timer_res = 2;
3871         } else {
3872                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3873                 return ECORE_INVAL;
3874         }
3875         timeset = (u8)(coalesce >> timer_res);
3876
3877         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3878         if (rc != ECORE_SUCCESS)
3879                 return rc;
3880
3881         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3882         if (rc != ECORE_SUCCESS)
3883                 goto out;
3884
3885         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3886
3887         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3888                                 sizeof(struct ustorm_eth_queue_zone), timeset);
3889         if (rc != ECORE_SUCCESS)
3890                 goto out;
3891
3892         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3893  out:
3894         return rc;
3895 }
3896
3897 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3898                                             struct ecore_ptt *p_ptt,
3899                                             u16 coalesce, u8 qid, u16 sb_id)
3900 {
3901         struct xstorm_eth_queue_zone eth_qzone;
3902         u8 timeset, timer_res;
3903         u16 fw_qid = 0;
3904         u32 address;
3905         enum _ecore_status_t rc;
3906
3907         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3908         if (coalesce <= 0x7F) {
3909                 timer_res = 0;
3910         } else if (coalesce <= 0xFF) {
3911                 timer_res = 1;
3912         } else if (coalesce <= 0x1FF) {
3913                 timer_res = 2;
3914         } else {
3915                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3916                 return ECORE_INVAL;
3917         }
3918
3919         timeset = (u8)(coalesce >> timer_res);
3920
3921         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3922         if (rc != ECORE_SUCCESS)
3923                 return rc;
3924
3925         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3926         if (rc != ECORE_SUCCESS)
3927                 goto out;
3928
3929         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3930
3931         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3932                                 sizeof(struct xstorm_eth_queue_zone), timeset);
3933         if (rc != ECORE_SUCCESS)
3934                 goto out;
3935
3936         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3937  out:
3938         return rc;
3939 }
3940
3941 /* Calculate final WFQ values for all vports and configure it.
3942  * After this configuration each vport must have
3943  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3944  */
3945 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3946                                                struct ecore_ptt *p_ptt,
3947                                                u32 min_pf_rate)
3948 {
3949         struct init_qm_vport_params *vport_params;
3950         int i;
3951
3952         vport_params = p_hwfn->qm_info.qm_vport_params;
3953
3954         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3955                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3956
3957                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3958                     min_pf_rate;
3959                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3960                                      vport_params[i].first_tx_pq_id,
3961                                      vport_params[i].vport_wfq);
3962         }
3963 }
3964
3965 static void
3966 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3967 {
3968         int i;
3969
3970         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3971                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3972 }
3973
3974 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3975                                              struct ecore_ptt *p_ptt,
3976                                              u32 min_pf_rate)
3977 {
3978         struct init_qm_vport_params *vport_params;
3979         int i;
3980
3981         vport_params = p_hwfn->qm_info.qm_vport_params;
3982
3983         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3984                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3985                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3986                                      vport_params[i].first_tx_pq_id,
3987                                      vport_params[i].vport_wfq);
3988         }
3989 }
3990
3991 /* This function performs several validations for WFQ
3992  * configuration and required min rate for a given vport
3993  * 1. req_rate must be greater than one percent of min_pf_rate.
3994  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3995  *    rates to get less than one percent of min_pf_rate.
3996  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3997  */
3998 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3999                                                  u16 vport_id, u32 req_rate,
4000                                                  u32 min_pf_rate)
4001 {
4002         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4003         int non_requested_count = 0, req_count = 0, i, num_vports;
4004
4005         num_vports = p_hwfn->qm_info.num_vports;
4006
4007 /* Accounting for the vports which are configured for WFQ explicitly */
4008
4009         for (i = 0; i < num_vports; i++) {
4010                 u32 tmp_speed;
4011
4012                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4013                         req_count++;
4014                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4015                         total_req_min_rate += tmp_speed;
4016                 }
4017         }
4018
4019         /* Include current vport data as well */
4020         req_count++;
4021         total_req_min_rate += req_rate;
4022         non_requested_count = num_vports - req_count;
4023
4024         /* validate possible error cases */
4025         if (req_rate > min_pf_rate) {
4026                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4027                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4028                            vport_id, req_rate, min_pf_rate);
4029                 return ECORE_INVAL;
4030         }
4031
4032         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4033                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4034                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4035                            vport_id, req_rate, min_pf_rate);
4036                 return ECORE_INVAL;
4037         }
4038
4039         /* TBD - for number of vports greater than 100 */
4040         if (num_vports > ECORE_WFQ_UNIT) {
4041                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4042                            "Number of vports is greater than %d\n",
4043                            ECORE_WFQ_UNIT);
4044                 return ECORE_INVAL;
4045         }
4046
4047         if (total_req_min_rate > min_pf_rate) {
4048                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4049                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4050                            total_req_min_rate, min_pf_rate);
4051                 return ECORE_INVAL;
4052         }
4053
4054         /* Data left for non requested vports */
4055         total_left_rate = min_pf_rate - total_req_min_rate;
4056         left_rate_per_vp = total_left_rate / non_requested_count;
4057
4058         /* validate if non requested get < 1% of min bw */
4059         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4060                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4061                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4062                            left_rate_per_vp, min_pf_rate);
4063                 return ECORE_INVAL;
4064         }
4065
4066         /* now req_rate for given vport passes all scenarios.
4067          * assign final wfq rates to all vports.
4068          */
4069         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4070         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4071
4072         for (i = 0; i < num_vports; i++) {
4073                 if (p_hwfn->qm_info.wfq_data[i].configured)
4074                         continue;
4075
4076                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4077         }
4078
4079         return ECORE_SUCCESS;
4080 }
4081
4082 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4083                                        struct ecore_ptt *p_ptt,
4084                                        u16 vp_id, u32 rate)
4085 {
4086         struct ecore_mcp_link_state *p_link;
4087         int rc = ECORE_SUCCESS;
4088
4089         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4090
4091         if (!p_link->min_pf_rate) {
4092                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4093                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4094                 return rc;
4095         }
4096
4097         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4098
4099         if (rc == ECORE_SUCCESS)
4100                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4101                                                    p_link->min_pf_rate);
4102         else
4103                 DP_NOTICE(p_hwfn, false,
4104                           "Validation failed while configuring min rate\n");
4105
4106         return rc;
4107 }
4108
4109 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4110                                                    struct ecore_ptt *p_ptt,
4111                                                    u32 min_pf_rate)
4112 {
4113         bool use_wfq = false;
4114         int rc = ECORE_SUCCESS;
4115         u16 i;
4116
4117         /* Validate all pre configured vports for wfq */
4118         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4119                 u32 rate;
4120
4121                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4122                         continue;
4123
4124                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4125                 use_wfq = true;
4126
4127                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4128                 if (rc != ECORE_SUCCESS) {
4129                         DP_NOTICE(p_hwfn, false,
4130                                   "WFQ validation failed while configuring min rate\n");
4131                         break;
4132                 }
4133         }
4134
4135         if (rc == ECORE_SUCCESS && use_wfq)
4136                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4137         else
4138                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4139
4140         return rc;
4141 }
4142
4143 /* Main API for ecore clients to configure vport min rate.
4144  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4145  * rate - Speed in Mbps needs to be assigned to a given vport.
4146  */
4147 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4148 {
4149         int i, rc = ECORE_INVAL;
4150
4151         /* TBD - for multiple hardware functions - that is 100 gig */
4152         if (p_dev->num_hwfns > 1) {
4153                 DP_NOTICE(p_dev, false,
4154                           "WFQ configuration is not supported for this device\n");
4155                 return rc;
4156         }
4157
4158         for_each_hwfn(p_dev, i) {
4159                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4160                 struct ecore_ptt *p_ptt;
4161
4162                 p_ptt = ecore_ptt_acquire(p_hwfn);
4163                 if (!p_ptt)
4164                         return ECORE_TIMEOUT;
4165
4166                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4167
4168                 if (rc != ECORE_SUCCESS) {
4169                         ecore_ptt_release(p_hwfn, p_ptt);
4170                         return rc;
4171                 }
4172
4173                 ecore_ptt_release(p_hwfn, p_ptt);
4174         }
4175
4176         return rc;
4177 }
4178
4179 /* API to configure WFQ from mcp link change */
4180 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4181                                            u32 min_pf_rate)
4182 {
4183         int i;
4184
4185         /* TBD - for multiple hardware functions - that is 100 gig */
4186         if (p_dev->num_hwfns > 1) {
4187                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4188                            "WFQ configuration is not supported for this device\n");
4189                 return;
4190         }
4191
4192         for_each_hwfn(p_dev, i) {
4193                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4194
4195                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4196                                                         p_hwfn->p_dpc_ptt,
4197                                                         min_pf_rate);
4198         }
4199 }
4200
4201 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4202                                        struct ecore_ptt *p_ptt,
4203                                        struct ecore_mcp_link_state *p_link,
4204                                        u8 max_bw)
4205 {
4206         int rc = ECORE_SUCCESS;
4207
4208         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4209
4210         if (!p_link->line_speed && (max_bw != 100))
4211                 return rc;
4212
4213         p_link->speed = (p_link->line_speed * max_bw) / 100;
4214         p_hwfn->qm_info.pf_rl = p_link->speed;
4215
4216         /* Since the limiter also affects Tx-switched traffic, we don't want it
4217          * to limit such traffic in case there's no actual limit.
4218          * In that case, set limit to imaginary high boundary.
4219          */
4220         if (max_bw == 100)
4221                 p_hwfn->qm_info.pf_rl = 100000;
4222
4223         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4224                               p_hwfn->qm_info.pf_rl);
4225
4226         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4227                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4228                    p_link->speed);
4229
4230         return rc;
4231 }
4232
4233 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4234 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4235 {
4236         int i, rc = ECORE_INVAL;
4237
4238         if (max_bw < 1 || max_bw > 100) {
4239                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4240                 return rc;
4241         }
4242
4243         for_each_hwfn(p_dev, i) {
4244                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4245                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4246                 struct ecore_mcp_link_state *p_link;
4247                 struct ecore_ptt *p_ptt;
4248
4249                 p_link = &p_lead->mcp_info->link_output;
4250
4251                 p_ptt = ecore_ptt_acquire(p_hwfn);
4252                 if (!p_ptt)
4253                         return ECORE_TIMEOUT;
4254
4255                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4256                                                         p_link, max_bw);
4257
4258                 ecore_ptt_release(p_hwfn, p_ptt);
4259
4260                 if (rc != ECORE_SUCCESS)
4261                         break;
4262         }
4263
4264         return rc;
4265 }
4266
4267 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4268                                        struct ecore_ptt *p_ptt,
4269                                        struct ecore_mcp_link_state *p_link,
4270                                        u8 min_bw)
4271 {
4272         int rc = ECORE_SUCCESS;
4273
4274         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4275         p_hwfn->qm_info.pf_wfq = min_bw;
4276
4277         if (!p_link->line_speed)
4278                 return rc;
4279
4280         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4281
4282         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4283
4284         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4285                    "Configured MIN bandwidth to be %d Mb/sec\n",
4286                    p_link->min_pf_rate);
4287
4288         return rc;
4289 }
4290
4291 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4292 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4293 {
4294         int i, rc = ECORE_INVAL;
4295
4296         if (min_bw < 1 || min_bw > 100) {
4297                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4298                 return rc;
4299         }
4300
4301         for_each_hwfn(p_dev, i) {
4302                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4303                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4304                 struct ecore_mcp_link_state *p_link;
4305                 struct ecore_ptt *p_ptt;
4306
4307                 p_link = &p_lead->mcp_info->link_output;
4308
4309                 p_ptt = ecore_ptt_acquire(p_hwfn);
4310                 if (!p_ptt)
4311                         return ECORE_TIMEOUT;
4312
4313                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4314                                                         p_link, min_bw);
4315                 if (rc != ECORE_SUCCESS) {
4316                         ecore_ptt_release(p_hwfn, p_ptt);
4317                         return rc;
4318                 }
4319
4320                 if (p_link->min_pf_rate) {
4321                         u32 min_rate = p_link->min_pf_rate;
4322
4323                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4324                                                                      p_ptt,
4325                                                                      min_rate);
4326                 }
4327
4328                 ecore_ptt_release(p_hwfn, p_ptt);
4329         }
4330
4331         return rc;
4332 }
4333
4334 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4335 {
4336         struct ecore_mcp_link_state *p_link;
4337
4338         p_link = &p_hwfn->mcp_info->link_output;
4339
4340         if (p_link->min_pf_rate)
4341                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4342                                                  p_link->min_pf_rate);
4343
4344         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4345                     sizeof(*p_hwfn->qm_info.wfq_data) *
4346                     p_hwfn->qm_info.num_vports);
4347 }
4348
4349 int ecore_device_num_engines(struct ecore_dev *p_dev)
4350 {
4351         return ECORE_IS_BB(p_dev) ? 2 : 1;
4352 }
4353
4354 int ecore_device_num_ports(struct ecore_dev *p_dev)
4355 {
4356         /* in CMT always only one port */
4357         if (p_dev->num_hwfns > 1)
4358                 return 1;
4359
4360         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4361 }
4362
4363 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4364                           __le16 *fw_mid,
4365                           __le16 *fw_lsb,
4366                           u8 *mac)
4367 {
4368         ((u8 *)fw_msb)[0] = mac[1];
4369         ((u8 *)fw_msb)[1] = mac[0];
4370         ((u8 *)fw_mid)[0] = mac[3];
4371         ((u8 *)fw_mid)[1] = mac[2];
4372         ((u8 *)fw_lsb)[0] = mac[5];
4373         ((u8 *)fw_lsb)[1] = mac[4];
4374 }