drivers/net/qede/base/ecore_dev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "bcm_osal.h"
   8 #include "reg_addr.h"
   9 #include "ecore_gtt_reg_addr.h"
  10 #include "ecore.h"
  11 #include "ecore_chain.h"
  12 #include "ecore_status.h"
  13 #include "ecore_hw.h"
  14 #include "ecore_rt_defs.h"
  15 #include "ecore_init_ops.h"
  16 #include "ecore_int.h"
  17 #include "ecore_cxt.h"
  18 #include "ecore_spq.h"
  19 #include "ecore_init_fw_funcs.h"
  20 #include "ecore_sp_commands.h"
  21 #include "ecore_dev_api.h"
  22 #include "ecore_sriov.h"
  23 #include "ecore_vf.h"
  24 #include "ecore_mcp.h"
  25 #include "ecore_hw_defs.h"
  26 #include "mcp_public.h"
  27 #include "ecore_iro.h"
  28 #include "nvm_cfg.h"
  29 #include "ecore_dcbx.h"
  30 #include "ecore_l2.h"
  31
  32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  33  * registers involved are not split and thus configuration is a race where
  34  * some of the PFs configuration might be lost.
  35  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  36  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  37  * there's more than a single compiled ecore component in system].
  38  */
  39 static osal_spinlock_t qm_lock;
  40 static u32 qm_lock_ref_cnt;
  41
  42 /******************** Doorbell Recovery *******************/
  43 /* The doorbell recovery mechanism consists of a list of entries which represent
  44  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  45  * entity needs to register with the mechanism and provide the parameters
  46  * describing it's doorbell, including a location where last used doorbell data
  47  * can be found. The doorbell execute function will traverse the list and
  48  * doorbell all of the registered entries.
  49  */
  50 struct ecore_db_recovery_entry {
  51         osal_list_entry_t       list_entry;
  52         void OSAL_IOMEM         *db_addr;
  53         void                    *db_data;
  54         enum ecore_db_rec_width db_width;
  55         enum ecore_db_rec_space db_space;
  56         u8                      hwfn_idx;
  57 };
  58
  59 /* display a single doorbell recovery entry */
  60 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  61                                 struct ecore_db_recovery_entry *db_entry,
  62                                 const char *action)
  63 {
  64         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  65                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  66                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  67                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  68                    db_entry->hwfn_idx);
  69 }
  70
  71 /* doorbell address sanity (address within doorbell bar range) */
  72 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  73                          void *db_data)
  74 {
  75         /* make sure doorbell address  is within the doorbell bar */
  76         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  77                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  78                 OSAL_WARN(true,
  79                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  80                           db_addr, p_dev->doorbells,
  81                           (u8 *)p_dev->doorbells + p_dev->db_size);
  82                 return false;
  83         }
  84
  85         /* make sure doorbell data pointer is not null */
  86         if (!db_data) {
  87                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  88                 return false;
  89         }
  90
  91         return true;
  92 }
  93
  94 /* find hwfn according to the doorbell address */
  95 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  96                                           void OSAL_IOMEM *db_addr)
  97 {
  98         struct ecore_hwfn *p_hwfn;
  99
 100         /* In CMT doorbell bar is split down the middle between engine 0 and
 101          * enigne 1
 102          */
 103         if (ECORE_IS_CMT(p_dev))
 104                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 105                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 106         else
 107                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 108
 109         return p_hwfn;
 110 }
 111
 112 /* add a new entry to the doorbell recovery mechanism */
 113 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 114                                            void OSAL_IOMEM *db_addr,
 115                                            void *db_data,
 116                                            enum ecore_db_rec_width db_width,
 117                                            enum ecore_db_rec_space db_space)
 118 {
 119         struct ecore_db_recovery_entry *db_entry;
 120         struct ecore_hwfn *p_hwfn;
 121
 122         /* shortcircuit VFs, for now */
 123         if (IS_VF(p_dev)) {
 124                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 125                 return ECORE_SUCCESS;
 126         }
 127
 128         /* sanitize doorbell address */
 129         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 130                 return ECORE_INVAL;
 131
 132         /* obtain hwfn from doorbell address */
 133         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 134
 135         /* create entry */
 136         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 137         if (!db_entry) {
 138                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 139                 return ECORE_NOMEM;
 140         }
 141
 142         /* populate entry */
 143         db_entry->db_addr = db_addr;
 144         db_entry->db_data = db_data;
 145         db_entry->db_width = db_width;
 146         db_entry->db_space = db_space;
 147         db_entry->hwfn_idx = p_hwfn->my_id;
 148
 149         /* display */
 150         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 151
 152         /* protect the list */
 153         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 154         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 155                             &p_hwfn->db_recovery_info.list);
 156         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 157
 158         return ECORE_SUCCESS;
 159 }
 160
 161 /* remove an entry from the doorbell recovery mechanism */
 162 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 163                                            void OSAL_IOMEM *db_addr,
 164                                            void *db_data)
 165 {
 166         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 167         enum _ecore_status_t rc = ECORE_INVAL;
 168         struct ecore_hwfn *p_hwfn;
 169
 170         /* shortcircuit VFs, for now */
 171         if (IS_VF(p_dev)) {
 172                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 173                 return ECORE_SUCCESS;
 174         }
 175
 176         /* sanitize doorbell address */
 177         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 178                 return ECORE_INVAL;
 179
 180         /* obtain hwfn from doorbell address */
 181         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 182
 183         /* protect the list */
 184         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 185         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 186                                  &p_hwfn->db_recovery_info.list,
 187                                  list_entry,
 188                                  struct ecore_db_recovery_entry) {
 189                 /* search according to db_data addr since db_addr is not unique
 190                  * (roce)
 191                  */
 192                 if (db_entry->db_data == db_data) {
 193                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 194                                                    "Deleting");
 195                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 196                                                &p_hwfn->db_recovery_info.list);
 197                         rc = ECORE_SUCCESS;
 198                         break;
 199                 }
 200         }
 201
 202         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 203
 204         if (rc == ECORE_INVAL)
 205                 /*OSAL_WARN(true,*/
 206                 DP_NOTICE(p_hwfn, false,
 207                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 208                           db_data, db_addr);
 209         else
 210                 OSAL_FREE(p_dev, db_entry);
 211
 212         return rc;
 213 }
 214
 215 /* initialize the doorbell recovery mechanism */
 216 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 217 {
 218         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 219
 220         /* make sure db_size was set in p_dev */
 221         if (!p_hwfn->p_dev->db_size) {
 222                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 223                 return ECORE_INVAL;
 224         }
 225
 226         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 227 #ifdef CONFIG_ECORE_LOCK_ALLOC
 228         if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
 229                 return ECORE_NOMEM;
 230 #endif
 231         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 232         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 233
 234         return ECORE_SUCCESS;
 235 }
 236
 237 /* destroy the doorbell recovery mechanism */
 238 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 239 {
 240         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 241
 242         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 243         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 244                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 245                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 246                         db_entry = OSAL_LIST_FIRST_ENTRY(
 247                                                 &p_hwfn->db_recovery_info.list,
 248                                                 struct ecore_db_recovery_entry,
 249                                                 list_entry);
 250                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 251                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 252                                                &p_hwfn->db_recovery_info.list);
 253                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 254                 }
 255         }
 256 #ifdef CONFIG_ECORE_LOCK_ALLOC
 257         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 258 #endif
 259         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 260 }
 261
 262 /* print the content of the doorbell recovery mechanism */
 263 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 264 {
 265         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 266
 267         DP_NOTICE(p_hwfn, false,
 268                   "Dispalying doorbell recovery database. Counter was %d\n",
 269                   p_hwfn->db_recovery_info.db_recovery_counter);
 270
 271         /* protect the list */
 272         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 273         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 274                                  &p_hwfn->db_recovery_info.list,
 275                                  list_entry,
 276                                  struct ecore_db_recovery_entry) {
 277                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 278         }
 279
 280         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 281 }
 282
 283 /* ring the doorbell of a single doorbell recovery entry */
 284 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 285                             struct ecore_db_recovery_entry *db_entry,
 286                             enum ecore_db_rec_exec db_exec)
 287 {
 288         /* Print according to width */
 289         if (db_entry->db_width == DB_REC_WIDTH_32B)
 290                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 291                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 292                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 293         else
 294                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 295                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 296                            db_entry->db_addr,
 297                            *(unsigned long *)(db_entry->db_data));
 298
 299         /* Sanity */
 300         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 301                                  db_entry->db_data))
 302                 return;
 303
 304         /* Flush the write combined buffer. Since there are multiple doorbelling
 305          * entities using the same address, if we don't flush, a transaction
 306          * could be lost.
 307          */
 308         OSAL_WMB(p_hwfn->p_dev);
 309
 310         /* Ring the doorbell */
 311         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 312                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 313                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 314                                       *(u32 *)(db_entry->db_data));
 315                 else
 316                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 317                                         *(u64 *)(db_entry->db_data));
 318         }
 319
 320         /* Flush the write combined buffer. Next doorbell may come from a
 321          * different entity to the same address...
 322          */
 323         OSAL_WMB(p_hwfn->p_dev);
 324 }
 325
 326 /* traverse the doorbell recovery entry list and ring all the doorbells */
 327 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 328                                enum ecore_db_rec_exec db_exec)
 329 {
 330         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 331
 332         if (db_exec != DB_REC_ONCE) {
 333                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 334                           p_hwfn->db_recovery_info.db_recovery_counter);
 335
 336                 /* track amount of times recovery was executed */
 337                 p_hwfn->db_recovery_info.db_recovery_counter++;
 338         }
 339
 340         /* protect the list */
 341         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 342         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 343                                  &p_hwfn->db_recovery_info.list,
 344                                  list_entry,
 345                                  struct ecore_db_recovery_entry) {
 346                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 347                 if (db_exec == DB_REC_ONCE)
 348                         break;
 349         }
 350
 351         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 352 }
 353 /******************** Doorbell Recovery end ****************/
 354
 355 /* Configurable */
 356 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
 357                                          * load the driver. The number was
 358                                          * arbitrarily set.
 359                                          */
 360
 361 /* Derived */
 362 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
 363
 364 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
 365                              struct ecore_ptt *p_ptt,
 366                              enum BAR_ID bar_id)
 367 {
 368         u32 bar_reg = (bar_id == BAR_ID_0 ?
 369                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 370         u32 val;
 371
 372         if (IS_VF(p_hwfn->p_dev))
 373                 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
 374
 375         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
 376         if (val)
 377                 return 1 << (val + 15);
 378
 379         /* The above registers were updated in the past only in CMT mode. Since
 380          * they were found to be useful MFW started updating them from 8.7.7.0.
 381          * In older MFW versions they are set to 0 which means disabled.
 382          */
 383         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
 384                 DP_INFO(p_hwfn,
 385                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 386                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 387         } else {
 388                 DP_INFO(p_hwfn,
 389                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 390                 val = 512 * 1024;
 391         }
 392
 393         return val;
 394 }
 395
 396 void ecore_init_dp(struct ecore_dev *p_dev,
 397                    u32 dp_module, u8 dp_level, void *dp_ctx)
 398 {
 399         u32 i;
 400
 401         p_dev->dp_level = dp_level;
 402         p_dev->dp_module = dp_module;
 403         p_dev->dp_ctx = dp_ctx;
 404         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 405                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 406
 407                 p_hwfn->dp_level = dp_level;
 408                 p_hwfn->dp_module = dp_module;
 409                 p_hwfn->dp_ctx = dp_ctx;
 410         }
 411 }
 412
 413 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
 414 {
 415         u8 i;
 416
 417         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 418                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 419
 420                 p_hwfn->p_dev = p_dev;
 421                 p_hwfn->my_id = i;
 422                 p_hwfn->b_active = false;
 423
 424 #ifdef CONFIG_ECORE_LOCK_ALLOC
 425                 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
 426                         goto handle_err;
 427 #endif
 428                 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
 429         }
 430
 431         /* hwfn 0 is always active */
 432         p_dev->hwfns[0].b_active = true;
 433
 434         /* set the default cache alignment to 128 (may be overridden later) */
 435         p_dev->cache_shift = 7;
 436         return ECORE_SUCCESS;
 437 #ifdef CONFIG_ECORE_LOCK_ALLOC
 438 handle_err:
 439         while (--i) {
 440                 struct ecore_hwfn *p_hwfn = OSAL_NULL;
 441
 442                 p_hwfn = &p_dev->hwfns[i];
 443                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
 444         }
 445         return ECORE_NOMEM;
 446 #endif
 447 }
 448
 449 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 450 {
 451         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 452
 453         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 454         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 455         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 456         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 457 }
 458
 459 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
 460 {
 461         OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
 462         p_hwfn->dbg_user_info = OSAL_NULL;
 463 }
 464
 465 void ecore_resc_free(struct ecore_dev *p_dev)
 466 {
 467         int i;
 468
 469         if (IS_VF(p_dev)) {
 470                 for_each_hwfn(p_dev, i)
 471                         ecore_l2_free(&p_dev->hwfns[i]);
 472                 return;
 473         }
 474
 475         OSAL_FREE(p_dev, p_dev->fw_data);
 476
 477         OSAL_FREE(p_dev, p_dev->reset_stats);
 478
 479         for_each_hwfn(p_dev, i) {
 480                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 481
 482                 ecore_cxt_mngr_free(p_hwfn);
 483                 ecore_qm_info_free(p_hwfn);
 484                 ecore_spq_free(p_hwfn);
 485                 ecore_eq_free(p_hwfn);
 486                 ecore_consq_free(p_hwfn);
 487                 ecore_int_free(p_hwfn);
 488                 ecore_iov_free(p_hwfn);
 489                 ecore_l2_free(p_hwfn);
 490                 ecore_dmae_info_free(p_hwfn);
 491                 ecore_dcbx_info_free(p_hwfn);
 492                 ecore_dbg_user_data_free(p_hwfn);
 493                 /* @@@TBD Flush work-queue ? */
 494
 495                 /* destroy doorbell recovery mechanism */
 496                 ecore_db_recovery_teardown(p_hwfn);
 497         }
 498 }
 499
 500 /******************** QM initialization *******************/
 501
 502 /* bitmaps for indicating active traffic classes.
 503  * Special case for Arrowhead 4 port
 504  */
 505 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 506 #define ACTIVE_TCS_BMAP 0x9f
 507 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 508 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 509
 510 /* determines the physical queue flags for a given PF. */
 511 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 512 {
 513         u32 flags;
 514
 515         /* common flags */
 516         flags = PQ_FLAGS_LB;
 517
 518         /* feature flags */
 519         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 520                 flags |= PQ_FLAGS_VFS;
 521         if (IS_ECORE_PACING(p_hwfn))
 522                 flags |= PQ_FLAGS_RLS;
 523
 524         /* protocol flags */
 525         switch (p_hwfn->hw_info.personality) {
 526         case ECORE_PCI_ETH:
 527                 if (!IS_ECORE_PACING(p_hwfn))
 528                         flags |= PQ_FLAGS_MCOS;
 529                 break;
 530         case ECORE_PCI_FCOE:
 531                 flags |= PQ_FLAGS_OFLD;
 532                 break;
 533         case ECORE_PCI_ISCSI:
 534                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 535                 break;
 536         case ECORE_PCI_ETH_ROCE:
 537                 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 538                 if (!IS_ECORE_PACING(p_hwfn))
 539                         flags |= PQ_FLAGS_MCOS;
 540                 break;
 541         case ECORE_PCI_ETH_IWARP:
 542                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 543                 if (!IS_ECORE_PACING(p_hwfn))
 544                         flags |= PQ_FLAGS_MCOS;
 545                 break;
 546         default:
 547                 DP_ERR(p_hwfn, "unknown personality %d\n",
 548                        p_hwfn->hw_info.personality);
 549                 return 0;
 550         }
 551         return flags;
 552 }
 553
 554 /* Getters for resource amounts necessary for qm initialization */
 555 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 556 {
 557         return p_hwfn->hw_info.num_hw_tc;
 558 }
 559
 560 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 561 {
 562         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 563                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 564 }
 565
 566 #define NUM_DEFAULT_RLS 1
 567
 568 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 569 {
 570         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 571
 572         /* num RLs can't exceed resource amount of rls or vports or the
 573          * dcqcn qps
 574          */
 575         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 576                                      RESC_NUM(p_hwfn, ECORE_VPORT));
 577
 578         /* make sure after we reserve the default and VF rls we'll have
 579          * something left
 580          */
 581         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 582                 DP_NOTICE(p_hwfn, false,
 583                           "no rate limiters left for PF rate limiting"
 584                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 585                 return 0;
 586         }
 587
 588         /* subtract rls necessary for VFs and one default one for the PF */
 589         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 590
 591         return num_pf_rls;
 592 }
 593
 594 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 595 {
 596         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 597
 598         /* all pqs share the same vport (hence the 1 below), except for vfs
 599          * and pf_rl pqs
 600          */
 601         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 602                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 603                (!!(PQ_FLAGS_VFS & pq_flags)) *
 604                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 605 }
 606
 607 /* calc amount of PQs according to the requested flags */
 608 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 609 {
 610         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 611
 612         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 613                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 614                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 615                 ecore_init_qm_get_num_tcs(p_hwfn) +
 616                (!!(PQ_FLAGS_LB & pq_flags)) +
 617                (!!(PQ_FLAGS_OOO & pq_flags)) +
 618                (!!(PQ_FLAGS_ACK & pq_flags)) +
 619                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 620                (!!(PQ_FLAGS_VFS & pq_flags)) *
 621                 ecore_init_qm_get_num_vfs(p_hwfn);
 622 }
 623
 624 /* initialize the top level QM params */
 625 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 626 {
 627         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 628         bool four_port;
 629
 630         /* pq and vport bases for this PF */
 631         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 632         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 633
 634         /* rate limiting and weighted fair queueing are always enabled */
 635         qm_info->vport_rl_en = 1;
 636         qm_info->vport_wfq_en = 1;
 637
 638         /* TC config is different for AH 4 port */
 639         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 640
 641         /* in AH 4 port we have fewer TCs per port */
 642         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 643                                                      NUM_OF_PHYS_TCS;
 644
 645         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 646          * 4 otherwise
 647          */
 648         if (!qm_info->ooo_tc)
 649                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 650                                               DCBX_TCP_OOO_TC;
 651 }
 652
 653 /* initialize qm vport params */
 654 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 655 {
 656         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 657         u8 i;
 658
 659         /* all vports participate in weighted fair queueing */
 660         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 661                 qm_info->qm_vport_params[i].vport_wfq = 1;
 662 }
 663
 664 /* initialize qm port params */
 665 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 666 {
 667         /* Initialize qm port parameters */
 668         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
 669
 670         /* indicate how ooo and high pri traffic is dealt with */
 671         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 672                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 673
 674         for (i = 0; i < num_ports; i++) {
 675                 struct init_qm_port_params *p_qm_port =
 676                         &p_hwfn->qm_info.qm_port_params[i];
 677
 678                 p_qm_port->active = 1;
 679                 p_qm_port->active_phys_tcs = active_phys_tcs;
 680                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
 681                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 682         }
 683 }
 684
 685 /* Reset the params which must be reset for qm init. QM init may be called as
 686  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 687  * params may be affected by the init but would simply recalculate to the same
 688  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 689  * affected as these amounts stay the same.
 690  */
 691 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 692 {
 693         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 694
 695         qm_info->num_pqs = 0;
 696         qm_info->num_vports = 0;
 697         qm_info->num_pf_rls = 0;
 698         qm_info->num_vf_pqs = 0;
 699         qm_info->first_vf_pq = 0;
 700         qm_info->first_mcos_pq = 0;
 701         qm_info->first_rl_pq = 0;
 702 }
 703
 704 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 705 {
 706         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 707
 708         qm_info->num_vports++;
 709
 710         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 711                 DP_ERR(p_hwfn,
 712                        "vport overflow! qm_info->num_vports %d,"
 713                        " qm_init_get_num_vports() %d\n",
 714                        qm_info->num_vports,
 715                        ecore_init_qm_get_num_vports(p_hwfn));
 716 }
 717
 718 /* initialize a single pq and manage qm_info resources accounting.
 719  * The pq_init_flags param determines whether the PQ is rate limited
 720  * (for VF or PF)
 721  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 722  * shared)
 723  */
 724
 725 /* flags for pq init */
 726 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 727 #define PQ_INIT_PF_RL           (1 << 1)
 728 #define PQ_INIT_VF_RL           (1 << 2)
 729
 730 /* defines for pq init */
 731 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 732 #define PQ_INIT_DEFAULT_TC              0
 733 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 734
 735 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 736                              struct ecore_qm_info *qm_info,
 737                              u8 tc, u32 pq_init_flags)
 738 {
 739         u16 pq_idx = qm_info->num_pqs, max_pq =
 740                                         ecore_init_qm_get_num_pqs(p_hwfn);
 741
 742         if (pq_idx > max_pq)
 743                 DP_ERR(p_hwfn,
 744                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 745
 746         /* init pq params */
 747         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
 748         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 749                                                  qm_info->num_vports;
 750         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 751         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 752         qm_info->qm_pq_params[pq_idx].rl_valid =
 753                 (pq_init_flags & PQ_INIT_PF_RL ||
 754                  pq_init_flags & PQ_INIT_VF_RL);
 755
 756         /* qm params accounting */
 757         qm_info->num_pqs++;
 758         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 759                 qm_info->num_vports++;
 760
 761         if (pq_init_flags & PQ_INIT_PF_RL)
 762                 qm_info->num_pf_rls++;
 763
 764         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 765                 DP_ERR(p_hwfn,
 766                        "vport overflow! qm_info->num_vports %d,"
 767                        " qm_init_get_num_vports() %d\n",
 768                        qm_info->num_vports,
 769                        ecore_init_qm_get_num_vports(p_hwfn));
 770
 771         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 772                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 773                        " qm_init_get_num_pf_rls() %d\n",
 774                        qm_info->num_pf_rls,
 775                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 776 }
 777
 778 /* get pq index according to PQ_FLAGS */
 779 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 780                                              u32 pq_flags)
 781 {
 782         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 783
 784         /* Can't have multiple flags set here */
 785         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 786                                 sizeof(pq_flags)) > 1)
 787                 goto err;
 788
 789         switch (pq_flags) {
 790         case PQ_FLAGS_RLS:
 791                 return &qm_info->first_rl_pq;
 792         case PQ_FLAGS_MCOS:
 793                 return &qm_info->first_mcos_pq;
 794         case PQ_FLAGS_LB:
 795                 return &qm_info->pure_lb_pq;
 796         case PQ_FLAGS_OOO:
 797                 return &qm_info->ooo_pq;
 798         case PQ_FLAGS_ACK:
 799                 return &qm_info->pure_ack_pq;
 800         case PQ_FLAGS_OFLD:
 801                 return &qm_info->offload_pq;
 802         case PQ_FLAGS_VFS:
 803                 return &qm_info->first_vf_pq;
 804         default:
 805                 goto err;
 806         }
 807
 808 err:
 809         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 810         return OSAL_NULL;
 811 }
 812
 813 /* save pq index in qm info */
 814 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 815                                   u32 pq_flags, u16 pq_val)
 816 {
 817         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 818
 819         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 820 }
 821
 822 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 823 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 824 {
 825         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 826
 827         return *base_pq_idx + CM_TX_PQ_BASE;
 828 }
 829
 830 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 831 {
 832         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 833
 834         if (tc > max_tc)
 835                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 836
 837         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
 838 }
 839
 840 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 841 {
 842         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 843
 844         if (vf > max_vf)
 845                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 846
 847         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
 848 }
 849
 850 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
 851 {
 852         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 853
 854         /* for rate limiters, it is okay to use the modulo behavior - no
 855          * DP_ERR
 856          */
 857         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl);
 858 }
 859
 860 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
 861 {
 862         u16 start_pq, pq, qm_pq_idx;
 863
 864         pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
 865         start_pq = p_hwfn->qm_info.start_pq;
 866         qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
 867
 868         if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
 869                 DP_ERR(p_hwfn,
 870                        "qm_pq_idx %d must be smaller than %d\n",
 871                         qm_pq_idx, p_hwfn->qm_info.num_pqs);
 872         }
 873
 874         return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
 875 }
 876
 877 /* Functions for creating specific types of pqs */
 878 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 879 {
 880         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 881
 882         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 883                 return;
 884
 885         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 886         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 887 }
 888
 889 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 890 {
 891         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 892
 893         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 894                 return;
 895
 896         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 897         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 898 }
 899
 900 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 901 {
 902         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 903
 904         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 905                 return;
 906
 907         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 908         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 909 }
 910
 911 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 912 {
 913         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 914
 915         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 916                 return;
 917
 918         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 919         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 920 }
 921
 922 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 923 {
 924         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 925         u8 tc_idx;
 926
 927         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 928                 return;
 929
 930         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 931         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 932                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 933 }
 934
 935 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 936 {
 937         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 938         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 939
 940         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 941                 return;
 942
 943         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 944
 945         qm_info->num_vf_pqs = num_vfs;
 946         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 947                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 948                                  PQ_INIT_VF_RL);
 949 }
 950
 951 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 952 {
 953         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 954         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 955
 956         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 957                 return;
 958
 959         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 960         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 961                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 962                                  PQ_INIT_PF_RL);
 963 }
 964
 965 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 966 {
 967         /* rate limited pqs, must come first (FW assumption) */
 968         ecore_init_qm_rl_pqs(p_hwfn);
 969
 970         /* pqs for multi cos */
 971         ecore_init_qm_mcos_pqs(p_hwfn);
 972
 973         /* pure loopback pq */
 974         ecore_init_qm_lb_pq(p_hwfn);
 975
 976         /* out of order pq */
 977         ecore_init_qm_ooo_pq(p_hwfn);
 978
 979         /* pure ack pq */
 980         ecore_init_qm_pure_ack_pq(p_hwfn);
 981
 982         /* pq for offloaded protocol */
 983         ecore_init_qm_offload_pq(p_hwfn);
 984
 985         /* done sharing vports */
 986         ecore_init_qm_advance_vport(p_hwfn);
 987
 988         /* pqs for vfs */
 989         ecore_init_qm_vf_pqs(p_hwfn);
 990 }
 991
 992 /* compare values of getters against resources amounts */
 993 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 994 {
 995         if (ecore_init_qm_get_num_vports(p_hwfn) >
 996             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 997                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 998                 return ECORE_INVAL;
 999         }
1000
1001         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
1002                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1003                 return ECORE_INVAL;
1004         }
1005
1006         return ECORE_SUCCESS;
1007 }
1008
1009 /*
1010  * Function for verbose printing of the qm initialization results
1011  */
1012 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
1013 {
1014         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1015         struct init_qm_vport_params *vport;
1016         struct init_qm_port_params *port;
1017         struct init_qm_pq_params *pq;
1018         int i, tc;
1019
1020         /* top level params */
1021         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1022                    "qm init top level params: start_pq %d, start_vport %d,"
1023                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
1024                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
1025                    qm_info->offload_pq, qm_info->pure_ack_pq);
1026         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1027                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
1028                    " num_vports %d, max_phys_tcs_per_port %d\n",
1029                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1030                    qm_info->num_vf_pqs, qm_info->num_vports,
1031                    qm_info->max_phys_tcs_per_port);
1032         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1033                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1034                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1035                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1036                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1037                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1038
1039         /* port table */
1040         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1041                 port = &qm_info->qm_port_params[i];
1042                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1043                            "port idx %d, active %d, active_phys_tcs %d,"
1044                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1045                            " reserved %d\n",
1046                            i, port->active, port->active_phys_tcs,
1047                            port->num_pbf_cmd_lines, port->num_btb_blocks,
1048                            port->reserved);
1049         }
1050
1051         /* vport table */
1052         for (i = 0; i < qm_info->num_vports; i++) {
1053                 vport = &qm_info->qm_vport_params[i];
1054                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1055                            "vport idx %d, vport_rl %d, wfq %d,"
1056                            " first_tx_pq_id [ ",
1057                            qm_info->start_vport + i, vport->vport_rl,
1058                            vport->vport_wfq);
1059                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1060                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1061                                    vport->first_tx_pq_id[tc]);
1062                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1063         }
1064
1065         /* pq table */
1066         for (i = 0; i < qm_info->num_pqs; i++) {
1067                 pq = &qm_info->qm_pq_params[i];
1068                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1069                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1070                            qm_info->start_pq + i, pq->port_id, pq->vport_id,
1071                            pq->tc_id, pq->wrr_group, pq->rl_valid);
1072         }
1073 }
1074
1075 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1076 {
1077         /* reset params required for init run */
1078         ecore_init_qm_reset_params(p_hwfn);
1079
1080         /* init QM top level params */
1081         ecore_init_qm_params(p_hwfn);
1082
1083         /* init QM port params */
1084         ecore_init_qm_port_params(p_hwfn);
1085
1086         /* init QM vport params */
1087         ecore_init_qm_vport_params(p_hwfn);
1088
1089         /* init QM physical queue params */
1090         ecore_init_qm_pq_params(p_hwfn);
1091
1092         /* display all that init */
1093         ecore_dp_init_qm_params(p_hwfn);
1094 }
1095
1096 /* This function reconfigures the QM pf on the fly.
1097  * For this purpose we:
1098  * 1. reconfigure the QM database
1099  * 2. set new values to runtime array
1100  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1101  * 4. activate init tool in QM_PF stage
1102  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1103  */
1104 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1105                                      struct ecore_ptt *p_ptt)
1106 {
1107         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1108         bool b_rc;
1109         enum _ecore_status_t rc;
1110
1111         /* initialize ecore's qm data structure */
1112         ecore_init_qm_info(p_hwfn);
1113
1114         /* stop PF's qm queues */
1115         OSAL_SPIN_LOCK(&qm_lock);
1116         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1117                                       qm_info->start_pq, qm_info->num_pqs);
1118         OSAL_SPIN_UNLOCK(&qm_lock);
1119         if (!b_rc)
1120                 return ECORE_INVAL;
1121
1122         /* clear the QM_PF runtime phase leftovers from previous init */
1123         ecore_init_clear_rt_data(p_hwfn);
1124
1125         /* prepare QM portion of runtime array */
1126         ecore_qm_init_pf(p_hwfn, p_ptt, false);
1127
1128         /* activate init tool on runtime array */
1129         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1130                             p_hwfn->hw_info.hw_mode);
1131         if (rc != ECORE_SUCCESS)
1132                 return rc;
1133
1134         /* start PF's qm queues */
1135         OSAL_SPIN_LOCK(&qm_lock);
1136         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1137                                       qm_info->start_pq, qm_info->num_pqs);
1138         OSAL_SPIN_UNLOCK(&qm_lock);
1139         if (!b_rc)
1140                 return ECORE_INVAL;
1141
1142         return ECORE_SUCCESS;
1143 }
1144
1145 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1146 {
1147         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1148         enum _ecore_status_t rc;
1149
1150         rc = ecore_init_qm_sanity(p_hwfn);
1151         if (rc != ECORE_SUCCESS)
1152                 goto alloc_err;
1153
1154         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1155                                             sizeof(struct init_qm_pq_params) *
1156                                             ecore_init_qm_get_num_pqs(p_hwfn));
1157         if (!qm_info->qm_pq_params)
1158                 goto alloc_err;
1159
1160         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1161                                        sizeof(struct init_qm_vport_params) *
1162                                        ecore_init_qm_get_num_vports(p_hwfn));
1163         if (!qm_info->qm_vport_params)
1164                 goto alloc_err;
1165
1166         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1167                                       sizeof(struct init_qm_port_params) *
1168                                       p_hwfn->p_dev->num_ports_in_engine);
1169         if (!qm_info->qm_port_params)
1170                 goto alloc_err;
1171
1172         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1173                                         sizeof(struct ecore_wfq_data) *
1174                                         ecore_init_qm_get_num_vports(p_hwfn));
1175         if (!qm_info->wfq_data)
1176                 goto alloc_err;
1177
1178         return ECORE_SUCCESS;
1179
1180 alloc_err:
1181         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1182         ecore_qm_info_free(p_hwfn);
1183         return ECORE_NOMEM;
1184 }
1185 /******************** End QM initialization ***************/
1186
1187 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1188 {
1189         enum _ecore_status_t rc = ECORE_SUCCESS;
1190         int i;
1191
1192         if (IS_VF(p_dev)) {
1193                 for_each_hwfn(p_dev, i) {
1194                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1195                         if (rc != ECORE_SUCCESS)
1196                                 return rc;
1197                 }
1198                 return rc;
1199         }
1200
1201         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1202                                      sizeof(*p_dev->fw_data));
1203         if (!p_dev->fw_data)
1204                 return ECORE_NOMEM;
1205
1206         for_each_hwfn(p_dev, i) {
1207                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1208                 u32 n_eqes, num_cons;
1209
1210                 /* initialize the doorbell recovery mechanism */
1211                 rc = ecore_db_recovery_setup(p_hwfn);
1212                 if (rc)
1213                         goto alloc_err;
1214
1215                 /* First allocate the context manager structure */
1216                 rc = ecore_cxt_mngr_alloc(p_hwfn);
1217                 if (rc)
1218                         goto alloc_err;
1219
1220                 /* Set the HW cid/tid numbers (in the context manager)
1221                  * Must be done prior to any further computations.
1222                  */
1223                 rc = ecore_cxt_set_pf_params(p_hwfn);
1224                 if (rc)
1225                         goto alloc_err;
1226
1227                 rc = ecore_alloc_qm_data(p_hwfn);
1228                 if (rc)
1229                         goto alloc_err;
1230
1231                 /* init qm info */
1232                 ecore_init_qm_info(p_hwfn);
1233
1234                 /* Compute the ILT client partition */
1235                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1236                 if (rc)
1237                         goto alloc_err;
1238
1239                 /* CID map / ILT shadow table / T2
1240                  * The talbes sizes are determined by the computations above
1241                  */
1242                 rc = ecore_cxt_tables_alloc(p_hwfn);
1243                 if (rc)
1244                         goto alloc_err;
1245
1246                 /* SPQ, must follow ILT because initializes SPQ context */
1247                 rc = ecore_spq_alloc(p_hwfn);
1248                 if (rc)
1249                         goto alloc_err;
1250
1251                 /* SP status block allocation */
1252                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1253                                                            RESERVED_PTT_DPC);
1254
1255                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1256                 if (rc)
1257                         goto alloc_err;
1258
1259                 rc = ecore_iov_alloc(p_hwfn);
1260                 if (rc)
1261                         goto alloc_err;
1262
1263                 /* EQ */
1264                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1265                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1266                         /* Calculate the EQ size
1267                          * ---------------------
1268                          * Each ICID may generate up to one event at a time i.e.
1269                          * the event must be handled/cleared before a new one
1270                          * can be generated. We calculate the sum of events per
1271                          * protocol and create an EQ deep enough to handle the
1272                          * worst case:
1273                          * - Core - according to SPQ.
1274                          * - RoCE - per QP there are a couple of ICIDs, one
1275                          *        responder and one requester, each can
1276                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
1277                          *        Each CQ can generate an EQE. There are 2 CQs
1278                          *        per QP => n_eqes_cq = 2 * n_qp.
1279                          *        Hence the RoCE total is 4 * n_qp or
1280                          *        2 * num_cons.
1281                          * - ENet - There can be up to two events per VF. One
1282                          *        for VF-PF channel and another for VF FLR
1283                          *        initial cleanup. The number of VFs is
1284                          *        bounded by MAX_NUM_VFS_BB, and is much
1285                          *        smaller than RoCE's so we avoid exact
1286                          *        calculation.
1287                          */
1288                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1289                                 num_cons =
1290                                     ecore_cxt_get_proto_cid_count(
1291                                                 p_hwfn,
1292                                                 PROTOCOLID_ROCE,
1293                                                 OSAL_NULL);
1294                                 num_cons *= 2;
1295                         } else {
1296                                 num_cons = ecore_cxt_get_proto_cid_count(
1297                                                 p_hwfn,
1298                                                 PROTOCOLID_IWARP,
1299                                                 OSAL_NULL);
1300                         }
1301                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1302                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1303                         num_cons =
1304                             ecore_cxt_get_proto_cid_count(p_hwfn,
1305                                                           PROTOCOLID_ISCSI,
1306                                                           OSAL_NULL);
1307                         n_eqes += 2 * num_cons;
1308                 }
1309
1310                 if (n_eqes > 0xFFFF) {
1311                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1312                                        "The maximum of a u16 chain is 0x%x\n",
1313                                n_eqes, 0xFFFF);
1314                         goto alloc_no_mem;
1315                 }
1316
1317                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1318                 if (rc)
1319                         goto alloc_err;
1320
1321                 rc = ecore_consq_alloc(p_hwfn);
1322                 if (rc)
1323                         goto alloc_err;
1324
1325                 rc = ecore_l2_alloc(p_hwfn);
1326                 if (rc != ECORE_SUCCESS)
1327                         goto alloc_err;
1328
1329                 /* DMA info initialization */
1330                 rc = ecore_dmae_info_alloc(p_hwfn);
1331                 if (rc) {
1332                         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
1333                         goto alloc_err;
1334                 }
1335
1336                 /* DCBX initialization */
1337                 rc = ecore_dcbx_info_alloc(p_hwfn);
1338                 if (rc) {
1339                         DP_NOTICE(p_hwfn, false,
1340                                   "Failed to allocate memory for dcbx structure\n");
1341                         goto alloc_err;
1342                 }
1343
1344                 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
1345                 if (rc) {
1346                         DP_NOTICE(p_hwfn, false,
1347                                   "Failed to allocate dbg user info structure\n");
1348                         goto alloc_err;
1349                 }
1350         } /* hwfn loop */
1351
1352         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1353                                          sizeof(*p_dev->reset_stats));
1354         if (!p_dev->reset_stats) {
1355                 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
1356                 goto alloc_no_mem;
1357         }
1358
1359         return ECORE_SUCCESS;
1360
1361 alloc_no_mem:
1362         rc = ECORE_NOMEM;
1363 alloc_err:
1364         ecore_resc_free(p_dev);
1365         return rc;
1366 }
1367
1368 void ecore_resc_setup(struct ecore_dev *p_dev)
1369 {
1370         int i;
1371
1372         if (IS_VF(p_dev)) {
1373                 for_each_hwfn(p_dev, i)
1374                         ecore_l2_setup(&p_dev->hwfns[i]);
1375                 return;
1376         }
1377
1378         for_each_hwfn(p_dev, i) {
1379                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1380
1381                 ecore_cxt_mngr_setup(p_hwfn);
1382                 ecore_spq_setup(p_hwfn);
1383                 ecore_eq_setup(p_hwfn);
1384                 ecore_consq_setup(p_hwfn);
1385
1386                 /* Read shadow of current MFW mailbox */
1387                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1388                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1389                             p_hwfn->mcp_info->mfw_mb_cur,
1390                             p_hwfn->mcp_info->mfw_mb_length);
1391
1392                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1393
1394                 ecore_l2_setup(p_hwfn);
1395                 ecore_iov_setup(p_hwfn);
1396         }
1397 }
1398
1399 #define FINAL_CLEANUP_POLL_CNT  (100)
1400 #define FINAL_CLEANUP_POLL_TIME (10)
1401 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1402                                          struct ecore_ptt *p_ptt,
1403                                          u16 id, bool is_vf)
1404 {
1405         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1406         enum _ecore_status_t rc = ECORE_TIMEOUT;
1407
1408 #ifndef ASIC_ONLY
1409         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1410             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1411                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1412                 return ECORE_SUCCESS;
1413         }
1414 #endif
1415
1416         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1417             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1418
1419         if (is_vf)
1420                 id += 0x10;
1421
1422         command |= X_FINAL_CLEANUP_AGG_INT <<
1423             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1424         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1425         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1426         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1427
1428 /* Make sure notification is not set before initiating final cleanup */
1429
1430         if (REG_RD(p_hwfn, addr)) {
1431                 DP_NOTICE(p_hwfn, false,
1432                           "Unexpected; Found final cleanup notification");
1433                 DP_NOTICE(p_hwfn, false,
1434                           " before initiating final cleanup\n");
1435                 REG_WR(p_hwfn, addr, 0);
1436         }
1437
1438         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1439                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1440                    id, command);
1441
1442         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1443
1444         /* Poll until completion */
1445         while (!REG_RD(p_hwfn, addr) && count--)
1446                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1447
1448         if (REG_RD(p_hwfn, addr))
1449                 rc = ECORE_SUCCESS;
1450         else
1451                 DP_NOTICE(p_hwfn, true,
1452                           "Failed to receive FW final cleanup notification\n");
1453
1454         /* Cleanup afterwards */
1455         REG_WR(p_hwfn, addr, 0);
1456
1457         return rc;
1458 }
1459
1460 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1461 {
1462         int hw_mode = 0;
1463
1464         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1465                 hw_mode |= 1 << MODE_BB;
1466         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1467                 hw_mode |= 1 << MODE_K2;
1468         } else {
1469                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1470                           p_hwfn->p_dev->type);
1471                 return ECORE_INVAL;
1472         }
1473
1474         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1475         switch (p_hwfn->p_dev->num_ports_in_engine) {
1476         case 1:
1477                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1478                 break;
1479         case 2:
1480                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1481                 break;
1482         case 4:
1483                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1484                 break;
1485         default:
1486                 DP_NOTICE(p_hwfn, true,
1487                           "num_ports_in_engine = %d not supported\n",
1488                           p_hwfn->p_dev->num_ports_in_engine);
1489                 return ECORE_INVAL;
1490         }
1491
1492         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1493                           &p_hwfn->p_dev->mf_bits))
1494                 hw_mode |= 1 << MODE_MF_SD;
1495         else
1496                 hw_mode |= 1 << MODE_MF_SI;
1497
1498 #ifndef ASIC_ONLY
1499         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1500                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1501                         hw_mode |= 1 << MODE_FPGA;
1502                 } else {
1503                         if (p_hwfn->p_dev->b_is_emul_full)
1504                                 hw_mode |= 1 << MODE_EMUL_FULL;
1505                         else
1506                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1507                 }
1508         } else
1509 #endif
1510                 hw_mode |= 1 << MODE_ASIC;
1511
1512         if (ECORE_IS_CMT(p_hwfn->p_dev))
1513                 hw_mode |= 1 << MODE_100G;
1514
1515         p_hwfn->hw_info.hw_mode = hw_mode;
1516
1517         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1518                    "Configuring function for hw_mode: 0x%08x\n",
1519                    p_hwfn->hw_info.hw_mode);
1520
1521         return ECORE_SUCCESS;
1522 }
1523
1524 #ifndef ASIC_ONLY
1525 /* MFW-replacement initializations for non-ASIC */
1526 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1527                                                struct ecore_ptt *p_ptt)
1528 {
1529         struct ecore_dev *p_dev = p_hwfn->p_dev;
1530         u32 pl_hv = 1;
1531         int i;
1532
1533         if (CHIP_REV_IS_EMUL(p_dev)) {
1534                 if (ECORE_IS_AH(p_dev))
1535                         pl_hv |= 0x600;
1536         }
1537
1538         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1539
1540         if (CHIP_REV_IS_EMUL(p_dev) &&
1541             (ECORE_IS_AH(p_dev)))
1542                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1543                          0x3ffffff);
1544
1545         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1546         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1547         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1548                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1549
1550         if (CHIP_REV_IS_EMUL(p_dev)) {
1551                 if (ECORE_IS_AH(p_dev)) {
1552                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1553                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1554                                  (p_dev->num_ports_in_engine >> 1));
1555
1556                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1557                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
1558                 }
1559         }
1560
1561         /* Poll on RBC */
1562         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1563         for (i = 0; i < 100; i++) {
1564                 OSAL_UDELAY(50);
1565                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1566                         break;
1567         }
1568         if (i == 100)
1569                 DP_NOTICE(p_hwfn, true,
1570                           "RBC done failed to complete in PSWRQ2\n");
1571
1572         return ECORE_SUCCESS;
1573 }
1574 #endif
1575
1576 /* Init run time data for all PFs and their VFs on an engine.
1577  * TBD - for VFs - Once we have parent PF info for each VF in
1578  * shmem available as CAU requires knowledge of parent PF for each VF.
1579  */
1580 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1581 {
1582         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1583         int i, igu_sb_id;
1584
1585         for_each_hwfn(p_dev, i) {
1586                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1587                 struct ecore_igu_info *p_igu_info;
1588                 struct ecore_igu_block *p_block;
1589                 struct cau_sb_entry sb_entry;
1590
1591                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1592
1593                 for (igu_sb_id = 0;
1594                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1595                      igu_sb_id++) {
1596                         p_block = &p_igu_info->entry[igu_sb_id];
1597
1598                         if (!p_block->is_pf)
1599                                 continue;
1600
1601                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1602                                                 p_block->function_id, 0, 0);
1603                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1604                                          sb_entry);
1605                 }
1606         }
1607 }
1608
1609 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1610                                        struct ecore_ptt *p_ptt)
1611 {
1612         u32 val, wr_mbs, cache_line_size;
1613
1614         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1615         switch (val) {
1616         case 0:
1617                 wr_mbs = 128;
1618                 break;
1619         case 1:
1620                 wr_mbs = 256;
1621                 break;
1622         case 2:
1623                 wr_mbs = 512;
1624                 break;
1625         default:
1626                 DP_INFO(p_hwfn,
1627                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1628                         val);
1629                 return;
1630         }
1631
1632         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1633         switch (cache_line_size) {
1634         case 32:
1635                 val = 0;
1636                 break;
1637         case 64:
1638                 val = 1;
1639                 break;
1640         case 128:
1641                 val = 2;
1642                 break;
1643         case 256:
1644                 val = 3;
1645                 break;
1646         default:
1647                 DP_INFO(p_hwfn,
1648                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1649                         cache_line_size);
1650         }
1651
1652         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1653                 DP_INFO(p_hwfn,
1654                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1655                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1656
1657         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1658         if (val > 0) {
1659                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1660                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1661         }
1662 }
1663
1664 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1665                                                  struct ecore_ptt *p_ptt,
1666                                                  int hw_mode)
1667 {
1668         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1669         struct ecore_dev *p_dev = p_hwfn->p_dev;
1670         u8 vf_id, max_num_vfs;
1671         u16 num_pfs, pf_id;
1672         u32 concrete_fid;
1673         enum _ecore_status_t rc = ECORE_SUCCESS;
1674
1675         ecore_init_cau_rt_data(p_dev);
1676
1677         /* Program GTT windows */
1678         ecore_gtt_init(p_hwfn, p_ptt);
1679
1680 #ifndef ASIC_ONLY
1681         if (CHIP_REV_IS_EMUL(p_dev)) {
1682                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1683                 if (rc != ECORE_SUCCESS)
1684                         return rc;
1685         }
1686 #endif
1687
1688         if (p_hwfn->mcp_info) {
1689                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1690                         qm_info->pf_rl_en = 1;
1691                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1692                         qm_info->pf_wfq_en = 1;
1693         }
1694
1695         ecore_qm_common_rt_init(p_hwfn,
1696                                 p_dev->num_ports_in_engine,
1697                                 qm_info->max_phys_tcs_per_port,
1698                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1699                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1700                                 qm_info->qm_port_params);
1701
1702         ecore_cxt_hw_init_common(p_hwfn);
1703
1704         ecore_init_cache_line_size(p_hwfn, p_ptt);
1705
1706         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
1707                             hw_mode);
1708         if (rc != ECORE_SUCCESS)
1709                 return rc;
1710
1711         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1712          * need to decide with which value, maybe runtime
1713          */
1714         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1715         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1716
1717         if (ECORE_IS_BB(p_dev)) {
1718                 /* Workaround clears ROCE search for all functions to prevent
1719                  * involving non initialized function in processing ROCE packet.
1720                  */
1721                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1722                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1723                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1724                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1725                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1726                 }
1727                 /* pretend to original PF */
1728                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1729         }
1730
1731         /* Workaround for avoiding CCFC execution error when getting packets
1732          * with CRC errors, and allowing instead the invoking of the FW error
1733          * handler.
1734          * This is not done inside the init tool since it currently can't
1735          * perform a pretending to VFs.
1736          */
1737         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1738         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1739                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1740                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1741                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1742                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1743                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1744                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1745         }
1746         /* pretend to original PF */
1747         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1748
1749         return rc;
1750 }
1751
1752 #ifndef ASIC_ONLY
1753 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1754 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1755
1756 #define PMEG_IF_BYTE_COUNT      8
1757
1758 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1759                              struct ecore_ptt *p_ptt,
1760                              u32 addr, u64 data, u8 reg_type, u8 port)
1761 {
1762         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1763                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1764                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1765                    (8 << PMEG_IF_BYTE_COUNT),
1766                    (reg_type << 25) | (addr << 8) | port,
1767                    (u32)((data >> 32) & 0xffffffff),
1768                    (u32)(data & 0xffffffff));
1769
1770         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1771                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1772                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1773         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1774                  (reg_type << 25) | (addr << 8) | port);
1775         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1776         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1777                  (data >> 32) & 0xffffffff);
1778 }
1779
1780 #define XLPORT_MODE_REG (0x20a)
1781 #define XLPORT_MAC_CONTROL (0x210)
1782 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1783 #define XLPORT_ENABLE_REG (0x20b)
1784
1785 #define XLMAC_CTRL (0x600)
1786 #define XLMAC_MODE (0x601)
1787 #define XLMAC_RX_MAX_SIZE (0x608)
1788 #define XLMAC_TX_CTRL (0x604)
1789 #define XLMAC_PAUSE_CTRL (0x60d)
1790 #define XLMAC_PFC_CTRL (0x60e)
1791
1792 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1793                                     struct ecore_ptt *p_ptt)
1794 {
1795         u8 loopback = 0, port = p_hwfn->port_id * 2;
1796
1797         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1798
1799         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1800         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1801                          port);
1802         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1803         /* XLMAC: SOFT RESET */
1804         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1805         /* XLMAC: Port Speed >= 10Gbps */
1806         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1807         /* XLMAC: Max Size */
1808         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1809         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1810                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1811                          0, port);
1812         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1813         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1814                          0x30ffffc000ULL, 0, port);
1815         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1816                          port); /* XLMAC: TX_EN, RX_EN */
1817         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1818         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1819                          0x1003 | (loopback << 2), 0, port);
1820         /* Enabled Parallel PFC interface */
1821         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1822
1823         /* XLPORT port enable */
1824         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1825 }
1826
1827 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1828                                        struct ecore_ptt *p_ptt)
1829 {
1830         u8 port = p_hwfn->port_id;
1831         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1832
1833         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1834
1835         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1836                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1837                  (port <<
1838                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1839                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1840
1841         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1842                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1843
1844         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1845                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1846
1847         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1848                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1849
1850         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1851                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1852
1853         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1854                  (0xA <<
1855                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1856                  (8 <<
1857                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1858
1859         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1860                  0xa853);
1861 }
1862
1863 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1864                                  struct ecore_ptt *p_ptt)
1865 {
1866         if (ECORE_IS_AH(p_hwfn->p_dev))
1867                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1868         else /* BB */
1869                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1870 }
1871
1872 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1873                                struct ecore_ptt *p_ptt,  u8 port)
1874 {
1875         int port_offset = port ? 0x800 : 0;
1876         u32 xmac_rxctrl = 0;
1877
1878         /* Reset of XMAC */
1879         /* FIXME: move to common start */
1880         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1881                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1882         OSAL_MSLEEP(1);
1883         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1884                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1885
1886         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1887
1888         /* Set the number of ports on the Warp Core to 10G */
1889         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1890
1891         /* Soft reset of XMAC */
1892         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1893                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1894         OSAL_MSLEEP(1);
1895         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1896                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1897
1898         /* FIXME: move to common end */
1899         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1900                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1901
1902         /* Set Max packet size: initialize XMAC block register for port 0 */
1903         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1904
1905         /* CRC append for Tx packets: init XMAC block register for port 1 */
1906         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1907
1908         /* Enable TX and RX: initialize XMAC block register for port 1 */
1909         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1910                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1911         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1912                                XMAC_REG_RX_CTRL_BB + port_offset);
1913         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1914         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1915 }
1916 #endif
1917
1918 static enum _ecore_status_t
1919 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1920                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1921 {
1922         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1923         u32 min_dpis;
1924         u32 n_wids;
1925
1926         /* Calculate DPI size
1927          * ------------------
1928          * The PWM region contains Doorbell Pages. The first is reserverd for
1929          * the kernel for, e.g, L2. The others are free to be used by non-
1930          * trusted applications, typically from user space. Each page, called a
1931          * doorbell page is sectioned into windows that allow doorbells to be
1932          * issued in parallel by the kernel/application. The size of such a
1933          * window (a.k.a. WID) is 1kB.
1934          * Summary:
1935          *    1kB WID x N WIDS = DPI page size
1936          *    DPI page size x N DPIs = PWM region size
1937          * Notes:
1938          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1939          * in order to ensure that two applications won't share the same page.
1940          * It also must contain at least one WID per CPU to allow parallelism.
1941          * It also must be a power of 2, since it is stored as a bit shift.
1942          *
1943          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1944          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1945          * containing 4 WIDs.
1946          */
1947         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1948         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1949         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1950                         ~(OSAL_PAGE_SIZE - 1);
1951         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1952         dpi_count = pwm_region_size / dpi_page_size;
1953
1954         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1955         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1956
1957         /* Update hwfn */
1958         p_hwfn->dpi_size = dpi_page_size;
1959         p_hwfn->dpi_count = dpi_count;
1960
1961         /* Update registers */
1962         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1963
1964         if (dpi_count < min_dpis)
1965                 return ECORE_NORESOURCES;
1966
1967         return ECORE_SUCCESS;
1968 }
1969
1970 enum ECORE_ROCE_EDPM_MODE {
1971         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1972         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1973         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1974 };
1975
1976 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn)
1977 {
1978         if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
1979                 return false;
1980
1981         return true;
1982 }
1983
1984 static enum _ecore_status_t
1985 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1986                               struct ecore_ptt *p_ptt)
1987 {
1988         u32 pwm_regsize, norm_regsize;
1989         u32 non_pwm_conn, min_addr_reg1;
1990         u32 db_bar_size, n_cpus;
1991         u32 roce_edpm_mode;
1992         u32 pf_dems_shift;
1993         enum _ecore_status_t rc = ECORE_SUCCESS;
1994         u8 cond;
1995
1996         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1997         if (ECORE_IS_CMT(p_hwfn->p_dev))
1998                 db_bar_size /= 2;
1999
2000         /* Calculate doorbell regions
2001          * -----------------------------------
2002          * The doorbell BAR is made of two regions. The first is called normal
2003          * region and the second is called PWM region. In the normal region
2004          * each ICID has its own set of addresses so that writing to that
2005          * specific address identifies the ICID. In the Process Window Mode
2006          * region the ICID is given in the data written to the doorbell. The
2007          * above per PF register denotes the offset in the doorbell BAR in which
2008          * the PWM region begins.
2009          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
2010          * non-PWM connection. The calculation below computes the total non-PWM
2011          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
2012          * in units of 4,096 bytes.
2013          */
2014         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2015             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2016                                           OSAL_NULL) +
2017             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
2018         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
2019                                OSAL_PAGE_SIZE);
2020         min_addr_reg1 = norm_regsize / 4096;
2021         pwm_regsize = db_bar_size - norm_regsize;
2022
2023         /* Check that the normal and PWM sizes are valid */
2024         if (db_bar_size < norm_regsize) {
2025                 DP_ERR(p_hwfn->p_dev,
2026                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2027                        db_bar_size, norm_regsize);
2028                 return ECORE_NORESOURCES;
2029         }
2030         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
2031                 DP_ERR(p_hwfn->p_dev,
2032                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2033                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
2034                        norm_regsize);
2035                 return ECORE_NORESOURCES;
2036         }
2037
2038         /* Calculate number of DPIs */
2039         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2040         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
2041             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2042                 /* Either EDPM is mandatory, or we are attempting to allocate a
2043                  * WID per CPU.
2044                  */
2045                 n_cpus = OSAL_NUM_CPUS();
2046                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2047         }
2048
2049         cond = ((rc != ECORE_SUCCESS) &&
2050                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2051                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2052         if (cond || p_hwfn->dcbx_no_edpm) {
2053                 /* Either EDPM is disabled from user configuration, or it is
2054                  * disabled via DCBx, or it is not mandatory and we failed to
2055                  * allocated a WID per CPU.
2056                  */
2057                 n_cpus = 1;
2058                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2059
2060                 /* If we entered this flow due to DCBX then the DPM register is
2061                  * already configured.
2062                  */
2063         }
2064
2065         DP_INFO(p_hwfn,
2066                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2067                 norm_regsize, pwm_regsize);
2068         DP_INFO(p_hwfn,
2069                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2070                 p_hwfn->dpi_size, p_hwfn->dpi_count,
2071                 (!ecore_edpm_enabled(p_hwfn)) ?
2072                 "disabled" : "enabled");
2073
2074         /* Check return codes from above calls */
2075         if (rc != ECORE_SUCCESS) {
2076                 DP_ERR(p_hwfn,
2077                        "Failed to allocate enough DPIs\n");
2078                 return ECORE_NORESOURCES;
2079         }
2080
2081         /* Update hwfn */
2082         p_hwfn->dpi_start_offset = norm_regsize;
2083
2084         /* Update registers */
2085         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2086         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2087         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2088         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2089
2090         return ECORE_SUCCESS;
2091 }
2092
2093 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2094                                                struct ecore_ptt *p_ptt,
2095                                                int hw_mode)
2096 {
2097         u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2098         u32 val;
2099         enum _ecore_status_t rc = ECORE_SUCCESS;
2100         u8 i;
2101
2102         /* In CMT for non-RoCE packets - use connection based classification */
2103         val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2104         for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2105                 ppf_to_eng_sel[i] = val;
2106         STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2107                          ppf_to_eng_sel);
2108
2109         /* In CMT the gate should be cleared by the 2nd hwfn */
2110         if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2111                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2112
2113         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2114                             hw_mode);
2115         if (rc != ECORE_SUCCESS)
2116                 return rc;
2117
2118         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2119
2120 #ifndef ASIC_ONLY
2121         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2122                 return ECORE_SUCCESS;
2123
2124         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2125                 if (ECORE_IS_AH(p_hwfn->p_dev))
2126                         return ECORE_SUCCESS;
2127                 else if (ECORE_IS_BB(p_hwfn->p_dev))
2128                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2129         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2130                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2131                         /* Activate OPTE in CMT */
2132                         u32 val;
2133
2134                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2135                         val |= 0x10;
2136                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2137                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2138                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2139                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2140                         ecore_wr(p_hwfn, p_ptt,
2141                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2142                         ecore_wr(p_hwfn, p_ptt,
2143                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2144                         ecore_wr(p_hwfn, p_ptt,
2145                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2146                                  0x55555555);
2147                 }
2148
2149                 ecore_emul_link_init(p_hwfn, p_ptt);
2150         } else {
2151                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2152         }
2153 #endif
2154
2155         return rc;
2156 }
2157
2158 static enum _ecore_status_t
2159 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2160                  struct ecore_ptt *p_ptt,
2161                  struct ecore_tunnel_info *p_tunn,
2162                  int hw_mode,
2163                  bool b_hw_start,
2164                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2165 {
2166         u8 rel_pf_id = p_hwfn->rel_pf_id;
2167         u32 prs_reg;
2168         enum _ecore_status_t rc = ECORE_SUCCESS;
2169         u16 ctrl;
2170         int pos;
2171
2172         if (p_hwfn->mcp_info) {
2173                 struct ecore_mcp_function_info *p_info;
2174
2175                 p_info = &p_hwfn->mcp_info->func_info;
2176                 if (p_info->bandwidth_min)
2177                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2178
2179                 /* Update rate limit once we'll actually have a link */
2180                 p_hwfn->qm_info.pf_rl = 100000;
2181         }
2182         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2183
2184         ecore_int_igu_init_rt(p_hwfn);
2185
2186         /* Set VLAN in NIG if needed */
2187         if (hw_mode & (1 << MODE_MF_SD)) {
2188                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2189                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2190                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2191                              p_hwfn->hw_info.ovlan);
2192
2193                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2194                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2195                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2196                              1);
2197         }
2198
2199         /* Enable classification by MAC if needed */
2200         if (hw_mode & (1 << MODE_MF_SI)) {
2201                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2202                            "Configuring TAGMAC_CLS_TYPE\n");
2203                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2204                              1);
2205         }
2206
2207         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
2208         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2209                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2210         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2211                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2212         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2213
2214         /* perform debug configuration when chip is out of reset */
2215         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2216
2217         /* Sanity check before the PF init sequence that uses DMAE */
2218         rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2219         if (rc)
2220                 return rc;
2221
2222         /* PF Init sequence */
2223         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2224         if (rc)
2225                 return rc;
2226
2227         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2228         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2229         if (rc)
2230                 return rc;
2231
2232         /* Pure runtime initializations - directly to the HW  */
2233         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2234
2235         /* PCI relaxed ordering causes a decrease in the performance on some
2236          * systems. Till a root cause is found, disable this attribute in the
2237          * PCI config space.
2238          */
2239         /* Not in use @DPDK
2240         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2241         * if (!pos) {
2242         *       DP_NOTICE(p_hwfn, true,
2243         *                 "Failed to find the PCIe Cap\n");
2244         *       return ECORE_IO;
2245         * }
2246         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2247         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2248         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2249         */
2250
2251         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2252         if (rc)
2253                 return rc;
2254         if (b_hw_start) {
2255                 /* enable interrupts */
2256                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2257                 if (rc != ECORE_SUCCESS)
2258                         return rc;
2259
2260                 /* send function start command */
2261                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2262                                        allow_npar_tx_switch);
2263                 if (rc) {
2264                         DP_NOTICE(p_hwfn, true,
2265                                   "Function start ramrod failed\n");
2266                 } else {
2267                         return rc;
2268                 }
2269                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2270                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2271                                 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2272
2273                 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2274                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2275                                         (1 << 2));
2276                         ecore_wr(p_hwfn, p_ptt,
2277                                  PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2278                                  0x100);
2279                 }
2280                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2281                                 "PRS_REG_SEARCH registers after start PFn\n");
2282                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2283                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2284                                 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2285                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2286                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2287                                 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2288                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2289                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2290                                 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2291                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2292                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2293                                 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2294                 prs_reg = ecore_rd(p_hwfn, p_ptt,
2295                                 PRS_REG_SEARCH_TCP_FIRST_FRAG);
2296                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2297                                 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2298                                 prs_reg);
2299                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2300                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2301                                 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2302         }
2303         return ECORE_SUCCESS;
2304 }
2305
2306 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2307                                                   struct ecore_ptt *p_ptt,
2308                                                   bool b_enable)
2309 {
2310         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2311
2312         /* Configure the PF's internal FID_enable for master transactions */
2313         ecore_wr(p_hwfn, p_ptt,
2314                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2315
2316         /* Wait until value is set - try for 1 second every 50us */
2317         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2318                 val = ecore_rd(p_hwfn, p_ptt,
2319                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2320                 if (val == set_val)
2321                         break;
2322
2323                 OSAL_UDELAY(50);
2324         }
2325
2326         if (val != set_val) {
2327                 DP_NOTICE(p_hwfn, true,
2328                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2329                 return ECORE_UNKNOWN_ERROR;
2330         }
2331
2332         return ECORE_SUCCESS;
2333 }
2334
2335 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2336                                   struct ecore_ptt *p_main_ptt)
2337 {
2338         /* Read shadow of current MFW mailbox */
2339         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2340         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2341                     p_hwfn->mcp_info->mfw_mb_cur,
2342                     p_hwfn->mcp_info->mfw_mb_length);
2343 }
2344
2345 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2346                                    struct ecore_ptt *p_ptt)
2347 {
2348         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2349                  1 << p_hwfn->abs_pf_id);
2350 }
2351
2352 static enum _ecore_status_t
2353 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
2354                            struct ecore_load_req_params *p_load_req,
2355                            struct ecore_drv_load_params *p_drv_load)
2356 {
2357         /* Make sure that if ecore-client didn't provide inputs, all the
2358          * expected defaults are indeed zero.
2359          */
2360         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2361         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2362         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2363
2364         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2365
2366         if (p_drv_load == OSAL_NULL)
2367                 goto out;
2368
2369         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2370                                ECORE_DRV_ROLE_KDUMP :
2371                                ECORE_DRV_ROLE_OS;
2372         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2373         p_load_req->override_force_load = p_drv_load->override_force_load;
2374
2375         /* Old MFW versions don't support timeout values other than default and
2376          * none, so these values are replaced according to the fall-back action.
2377          */
2378
2379         if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
2380             p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
2381             (p_hwfn->mcp_info->capabilities &
2382              FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
2383                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2384                 goto out;
2385         }
2386
2387         switch (p_drv_load->mfw_timeout_fallback) {
2388         case ECORE_TO_FALLBACK_TO_NONE:
2389                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
2390                 break;
2391         case ECORE_TO_FALLBACK_TO_DEFAULT:
2392                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
2393                 break;
2394         case ECORE_TO_FALLBACK_FAIL_LOAD:
2395                 DP_NOTICE(p_hwfn, false,
2396                           "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
2397                           p_drv_load->mfw_timeout_val,
2398                           ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
2399                           ECORE_LOAD_REQ_LOCK_TO_NONE);
2400                 return ECORE_ABORTED;
2401         }
2402
2403         DP_INFO(p_hwfn,
2404                 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
2405                 p_drv_load->mfw_timeout_val,
2406                 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
2407                 "default" : "none",
2408                 p_load_req->timeout_val);
2409 out:
2410         return ECORE_SUCCESS;
2411 }
2412
2413 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2414                                     struct ecore_hw_init_params *p_params)
2415 {
2416         if (p_params->p_tunn) {
2417                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2418                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2419         }
2420
2421         p_hwfn->b_int_enabled = 1;
2422
2423         return ECORE_SUCCESS;
2424 }
2425
2426 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2427                                    struct ecore_hw_init_params *p_params)
2428 {
2429         struct ecore_load_req_params load_req_params;
2430         u32 load_code, resp, param, drv_mb_param;
2431         bool b_default_mtu = true;
2432         struct ecore_hwfn *p_hwfn;
2433         enum _ecore_status_t rc = ECORE_SUCCESS;
2434         u16 ether_type;
2435         int i;
2436
2437         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2438                 DP_NOTICE(p_dev, false,
2439                           "MSI mode is not supported for CMT devices\n");
2440                 return ECORE_INVAL;
2441         }
2442
2443         if (IS_PF(p_dev)) {
2444                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2445                 if (rc != ECORE_SUCCESS)
2446                         return rc;
2447         }
2448
2449         for_each_hwfn(p_dev, i) {
2450                 p_hwfn = &p_dev->hwfns[i];
2451
2452                 /* If management didn't provide a default, set one of our own */
2453                 if (!p_hwfn->hw_info.mtu) {
2454                         p_hwfn->hw_info.mtu = 1500;
2455                         b_default_mtu = false;
2456                 }
2457
2458                 if (IS_VF(p_dev)) {
2459                         ecore_vf_start(p_hwfn, p_params);
2460                         continue;
2461                 }
2462
2463                 rc = ecore_calc_hw_mode(p_hwfn);
2464                 if (rc != ECORE_SUCCESS)
2465                         return rc;
2466
2467                 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
2468                                                    &p_dev->mf_bits) ||
2469                                      OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
2470                                                    &p_dev->mf_bits))) {
2471                         if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
2472                                           &p_dev->mf_bits))
2473                                 ether_type = ETHER_TYPE_VLAN;
2474                         else
2475                                 ether_type = ETHER_TYPE_QINQ;
2476                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2477                                      ether_type);
2478                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2479                                      ether_type);
2480                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2481                                      ether_type);
2482                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
2483                                      ether_type);
2484                 }
2485
2486                 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
2487
2488                 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
2489                                                 p_params->p_drv_load_params);
2490                 if (rc != ECORE_SUCCESS)
2491                         return rc;
2492
2493                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2494                                         &load_req_params);
2495                 if (rc != ECORE_SUCCESS) {
2496                         DP_NOTICE(p_hwfn, false,
2497                                   "Failed sending a LOAD_REQ command\n");
2498                         return rc;
2499                 }
2500
2501                 load_code = load_req_params.load_code;
2502                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2503                            "Load request was sent. Load code: 0x%x\n",
2504                            load_code);
2505
2506                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2507
2508                 /* CQ75580:
2509                  * When coming back from hiberbate state, the registers from
2510                  * which shadow is read initially are not initialized. It turns
2511                  * out that these registers get initialized during the call to
2512                  * ecore_mcp_load_req request. So we need to reread them here
2513                  * to get the proper shadow register value.
2514                  * Note: This is a workaround for the missing MFW
2515                  * initialization. It may be removed once the implementation
2516                  * is done.
2517                  */
2518                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2519
2520                 /* Only relevant for recovery:
2521                  * Clear the indication after the LOAD_REQ command is responded
2522                  * by the MFW.
2523                  */
2524                 p_dev->recov_in_prog = false;
2525
2526                 p_hwfn->first_on_engine = (load_code ==
2527                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2528
2529                 if (!qm_lock_ref_cnt) {
2530 #ifdef CONFIG_ECORE_LOCK_ALLOC
2531                         rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
2532                         if (rc) {
2533                                 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
2534                                 goto qm_lock_fail;
2535                         }
2536 #endif
2537                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2538                 }
2539                 ++qm_lock_ref_cnt;
2540
2541                 /* Clean up chip from previous driver if such remains exist.
2542                  * This is not needed when the PF is the first one on the
2543                  * engine, since afterwards we are going to init the FW.
2544                  */
2545                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2546                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2547                                                  p_hwfn->rel_pf_id, false);
2548                         if (rc != ECORE_SUCCESS) {
2549                                 ecore_hw_err_notify(p_hwfn,
2550                                                     ECORE_HW_ERR_RAMROD_FAIL);
2551                                 goto load_err;
2552                         }
2553                 }
2554
2555                 /* Log and clear previous pglue_b errors if such exist */
2556                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
2557
2558                 /* Enable the PF's internal FID_enable in the PXP */
2559                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2560                                                   true);
2561                 if (rc != ECORE_SUCCESS)
2562                         goto load_err;
2563
2564                 /* Clear the pglue_b was_error indication.
2565                  * In E4 it must be done after the BME and the internal
2566                  * FID_enable for the PF are set, since VDMs may cause the
2567                  * indication to be set again.
2568                  */
2569                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2570
2571                 switch (load_code) {
2572                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2573                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2574                                                   p_hwfn->hw_info.hw_mode);
2575                         if (rc != ECORE_SUCCESS)
2576                                 break;
2577                         /* Fall into */
2578                 case FW_MSG_CODE_DRV_LOAD_PORT:
2579                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2580                                                 p_hwfn->hw_info.hw_mode);
2581                         if (rc != ECORE_SUCCESS)
2582                                 break;
2583                         /* Fall into */
2584                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2585                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2586                                               p_params->p_tunn,
2587                                               p_hwfn->hw_info.hw_mode,
2588                                               p_params->b_hw_start,
2589                                               p_params->int_mode,
2590                                               p_params->allow_npar_tx_switch);
2591                         break;
2592                 default:
2593                         DP_NOTICE(p_hwfn, false,
2594                                   "Unexpected load code [0x%08x]", load_code);
2595                         rc = ECORE_NOTIMPL;
2596                         break;
2597                 }
2598
2599                 if (rc != ECORE_SUCCESS) {
2600                         DP_NOTICE(p_hwfn, false,
2601                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2602                                   load_code, rc);
2603                         goto load_err;
2604                 }
2605
2606                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2607                 if (rc != ECORE_SUCCESS) {
2608                         DP_NOTICE(p_hwfn, false,
2609                                   "Sending load done failed, rc = %d\n", rc);
2610                         if (rc == ECORE_NOMEM) {
2611                                 DP_NOTICE(p_hwfn, false,
2612                                           "Sending load done was failed due to memory allocation failure\n");
2613                                 goto load_err;
2614                         }
2615                         return rc;
2616                 }
2617
2618                 /* send DCBX attention request command */
2619                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2620                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2621                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2622                                    DRV_MSG_CODE_SET_DCBX,
2623                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2624                                    &param);
2625                 if (rc != ECORE_SUCCESS) {
2626                         DP_NOTICE(p_hwfn, false,
2627                                   "Failed to send DCBX attention request\n");
2628                         return rc;
2629                 }
2630
2631                 p_hwfn->hw_init_done = true;
2632         }
2633
2634         if (IS_PF(p_dev)) {
2635                 /* Get pre-negotiated values for stag, bandwidth etc. */
2636                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2637                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
2638                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
2639                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2640                                    DRV_MSG_CODE_GET_OEM_UPDATES,
2641                                    1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
2642                                    &resp, &param);
2643                 if (rc != ECORE_SUCCESS)
2644                         DP_NOTICE(p_hwfn, false,
2645                                   "Failed to send GET_OEM_UPDATES attention request\n");
2646         }
2647
2648         if (IS_PF(p_dev)) {
2649                 /* Get pre-negotiated values for stag, bandwidth etc. */
2650                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2651                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
2652                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
2653                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2654                                    DRV_MSG_CODE_GET_OEM_UPDATES,
2655                                    1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
2656                                    &resp, &param);
2657                 if (rc != ECORE_SUCCESS)
2658                         DP_NOTICE(p_hwfn, false,
2659                                   "Failed to send GET_OEM_UPDATES attention request\n");
2660         }
2661
2662         if (IS_PF(p_dev)) {
2663                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2664                 drv_mb_param = STORM_FW_VERSION;
2665                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2666                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2667                                    drv_mb_param, &resp, &param);
2668                 if (rc != ECORE_SUCCESS)
2669                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2670
2671                 if (!b_default_mtu) {
2672                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2673                                                       p_hwfn->hw_info.mtu);
2674                         if (rc != ECORE_SUCCESS)
2675                                 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2676                 }
2677
2678                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2679                                                       p_hwfn->p_main_ptt,
2680                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2681                 if (rc != ECORE_SUCCESS)
2682                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2683
2684                 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
2685                                                  ECORE_OV_ESWITCH_NONE);
2686                 if (rc != ECORE_SUCCESS)
2687                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
2688         }
2689
2690         return rc;
2691
2692 load_err:
2693         --qm_lock_ref_cnt;
2694 #ifdef CONFIG_ECORE_LOCK_ALLOC
2695         if (!qm_lock_ref_cnt)
2696                 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2697 qm_lock_fail:
2698 #endif
2699         /* The MFW load lock should be released regardless of success or failure
2700          * of initialization.
2701          * TODO: replace this with an attempt to send cancel_load.
2702          */
2703         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2704         return rc;
2705 }
2706
2707 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2708 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2709                                  struct ecore_hwfn *p_hwfn,
2710                                  struct ecore_ptt *p_ptt)
2711 {
2712         int i;
2713
2714         /* close timers */
2715         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2716         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2717         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2718                                                                         i++) {
2719                 if ((!ecore_rd(p_hwfn, p_ptt,
2720                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2721                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2722                         break;
2723
2724                 /* Dependent on number of connection/tasks, possibly
2725                  * 1ms sleep is required between polls
2726                  */
2727                 OSAL_MSLEEP(1);
2728         }
2729
2730         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2731                 return;
2732
2733         DP_NOTICE(p_hwfn, false,
2734                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
2735                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2736                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2737 }
2738
2739 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2740 {
2741         int j;
2742
2743         for_each_hwfn(p_dev, j) {
2744                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2745                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2746
2747                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2748         }
2749 }
2750
2751 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2752                                                  struct ecore_ptt *p_ptt,
2753                                                  u32 addr, u32 expected_val)
2754 {
2755         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2756
2757         if (val != expected_val) {
2758                 DP_NOTICE(p_hwfn, true,
2759                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2760                           addr, val, expected_val);
2761                 return ECORE_UNKNOWN_ERROR;
2762         }
2763
2764         return ECORE_SUCCESS;
2765 }
2766
2767 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2768 {
2769         struct ecore_hwfn *p_hwfn;
2770         struct ecore_ptt *p_ptt;
2771         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2772         int j;
2773
2774         for_each_hwfn(p_dev, j) {
2775                 p_hwfn = &p_dev->hwfns[j];
2776                 p_ptt = p_hwfn->p_main_ptt;
2777
2778                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2779
2780                 if (IS_VF(p_dev)) {
2781                         ecore_vf_pf_int_cleanup(p_hwfn);
2782                         rc = ecore_vf_pf_reset(p_hwfn);
2783                         if (rc != ECORE_SUCCESS) {
2784                                 DP_NOTICE(p_hwfn, true,
2785                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2786                                           rc);
2787                                 rc2 = ECORE_UNKNOWN_ERROR;
2788                         }
2789                         continue;
2790                 }
2791
2792                 /* mark the hw as uninitialized... */
2793                 p_hwfn->hw_init_done = false;
2794
2795                 /* Send unload command to MCP */
2796                 if (!p_dev->recov_in_prog) {
2797                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2798                         if (rc != ECORE_SUCCESS) {
2799                                 DP_NOTICE(p_hwfn, false,
2800                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2801                                           rc);
2802                                 rc2 = ECORE_UNKNOWN_ERROR;
2803                         }
2804                 }
2805
2806                 OSAL_DPC_SYNC(p_hwfn);
2807
2808                 /* After this point no MFW attentions are expected, e.g. prevent
2809                  * race between pf stop and dcbx pf update.
2810                  */
2811
2812                 rc = ecore_sp_pf_stop(p_hwfn);
2813                 if (rc != ECORE_SUCCESS) {
2814                         DP_NOTICE(p_hwfn, false,
2815                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2816                                   rc);
2817                         rc2 = ECORE_UNKNOWN_ERROR;
2818                 }
2819
2820                 OSAL_DPC_SYNC(p_hwfn);
2821
2822                 /* After this point we don't expect the FW to send us async
2823                  * events
2824                  */
2825
2826                 /* perform debug action after PF stop was sent */
2827                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2828
2829                 /* close NIG to BRB gate */
2830                 ecore_wr(p_hwfn, p_ptt,
2831                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2832
2833                 /* close parser */
2834                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2835                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2836                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2837                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2838                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2839
2840                 /* @@@TBD - clean transmission queues (5.b) */
2841                 /* @@@TBD - clean BTB (5.c) */
2842
2843                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2844
2845                 /* @@@TBD - verify DMAE requests are done (8) */
2846
2847                 /* Disable Attention Generation */
2848                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2849                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2850                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2851                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2852                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2853                 if (rc != ECORE_SUCCESS) {
2854                         DP_NOTICE(p_hwfn, true,
2855                                   "Failed to return IGU CAM to default\n");
2856                         rc2 = ECORE_UNKNOWN_ERROR;
2857                 }
2858
2859                 /* Need to wait 1ms to guarantee SBs are cleared */
2860                 OSAL_MSLEEP(1);
2861
2862                 if (!p_dev->recov_in_prog) {
2863                         ecore_verify_reg_val(p_hwfn, p_ptt,
2864                                              QM_REG_USG_CNT_PF_TX, 0);
2865                         ecore_verify_reg_val(p_hwfn, p_ptt,
2866                                              QM_REG_USG_CNT_PF_OTHER, 0);
2867                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2868                 }
2869
2870                 /* Disable PF in HW blocks */
2871                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2872                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2873
2874                 --qm_lock_ref_cnt;
2875 #ifdef CONFIG_ECORE_LOCK_ALLOC
2876                 if (!qm_lock_ref_cnt)
2877                         OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2878 #endif
2879
2880                 if (!p_dev->recov_in_prog) {
2881                         rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2882                         if (rc == ECORE_NOMEM) {
2883                                 DP_NOTICE(p_hwfn, false,
2884                                          "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
2885                                 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2886                         }
2887                         if (rc != ECORE_SUCCESS) {
2888                                 DP_NOTICE(p_hwfn, false,
2889                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2890                                           rc);
2891                                 rc2 = ECORE_UNKNOWN_ERROR;
2892                         }
2893                 }
2894         } /* hwfn loop */
2895
2896         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2897                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2898                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2899
2900                  /* Clear the PF's internal FID_enable in the PXP.
2901                   * In CMT this should only be done for first hw-function, and
2902                   * only after all transactions have stopped for all active
2903                   * hw-functions.
2904                   */
2905                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2906                                                   false);
2907                 if (rc != ECORE_SUCCESS) {
2908                         DP_NOTICE(p_hwfn, true,
2909                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2910                                   rc);
2911                         rc2 = ECORE_UNKNOWN_ERROR;
2912                 }
2913         }
2914
2915         return rc2;
2916 }
2917
2918 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2919 {
2920         int j;
2921
2922         for_each_hwfn(p_dev, j) {
2923                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2924                 struct ecore_ptt *p_ptt;
2925
2926                 if (IS_VF(p_dev)) {
2927                         ecore_vf_pf_int_cleanup(p_hwfn);
2928                         continue;
2929                 }
2930                 p_ptt = ecore_ptt_acquire(p_hwfn);
2931                 if (!p_ptt)
2932                         return ECORE_AGAIN;
2933
2934                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2935                            "Shutting down the fastpath\n");
2936
2937                 ecore_wr(p_hwfn, p_ptt,
2938                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2939
2940                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2941                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2942                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2943                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2944                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2945
2946                 /* @@@TBD - clean transmission queues (5.b) */
2947                 /* @@@TBD - clean BTB (5.c) */
2948
2949                 /* @@@TBD - verify DMAE requests are done (8) */
2950
2951                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2952                 /* Need to wait 1ms to guarantee SBs are cleared */
2953                 OSAL_MSLEEP(1);
2954                 ecore_ptt_release(p_hwfn, p_ptt);
2955         }
2956
2957         return ECORE_SUCCESS;
2958 }
2959
2960 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2961 {
2962         struct ecore_ptt *p_ptt;
2963
2964         if (IS_VF(p_hwfn->p_dev))
2965                 return ECORE_SUCCESS;
2966
2967         p_ptt = ecore_ptt_acquire(p_hwfn);
2968         if (!p_ptt)
2969                 return ECORE_AGAIN;
2970
2971         /* If roce info is allocated it means roce is initialized and should
2972          * be enabled in searcher.
2973          */
2974         if (p_hwfn->p_rdma_info) {
2975                 if (p_hwfn->b_rdma_enabled_in_prs)
2976                         ecore_wr(p_hwfn, p_ptt,
2977                                  p_hwfn->rdma_prs_search_reg, 0x1);
2978                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2979         }
2980
2981         /* Re-open incoming traffic */
2982         ecore_wr(p_hwfn, p_ptt,
2983                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2984         ecore_ptt_release(p_hwfn, p_ptt);
2985
2986         return ECORE_SUCCESS;
2987 }
2988
2989 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2990 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2991 {
2992         ecore_ptt_pool_free(p_hwfn);
2993         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2994 }
2995
2996 /* Setup bar access */
2997 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2998 {
2999         /* clear indirect access */
3000         if (ECORE_IS_AH(p_hwfn->p_dev)) {
3001                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3002                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
3003                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3004                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
3005                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3006                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
3007                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3008                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
3009         } else {
3010                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3011                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
3012                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3013                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3014                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3015                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3016                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3017                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3018         }
3019
3020         /* Clean previous pglue_b errors if such exist */
3021         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3022
3023         /* enable internal target-read */
3024         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3025                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3026 }
3027
3028 static void get_function_id(struct ecore_hwfn *p_hwfn)
3029 {
3030         /* ME Register */
3031         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
3032                                                   PXP_PF_ME_OPAQUE_ADDR);
3033
3034         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3035
3036         /* Bits 16-19 from the ME registers are the pf_num */
3037         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3038         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3039                                       PXP_CONCRETE_FID_PFID);
3040         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3041                                     PXP_CONCRETE_FID_PORT);
3042
3043         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3044                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3045                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3046 }
3047
3048 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
3049 {
3050         u32 *feat_num = p_hwfn->hw_info.feat_num;
3051         struct ecore_sb_cnt_info sb_cnt;
3052         u32 non_l2_sbs = 0;
3053
3054         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
3055         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
3056
3057         /* L2 Queues require each: 1 status block. 1 L2 queue */
3058         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
3059                 /* Start by allocating VF queues, then PF's */
3060                 feat_num[ECORE_VF_L2_QUE] =
3061                         OSAL_MIN_T(u32,
3062                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
3063                                    sb_cnt.iov_cnt);
3064                 feat_num[ECORE_PF_L2_QUE] =
3065                         OSAL_MIN_T(u32,
3066                                    sb_cnt.cnt - non_l2_sbs,
3067                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
3068                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
3069         }
3070
3071         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
3072             ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) {
3073                 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ?
3074                                       &feat_num[ECORE_FCOE_CQ] :
3075                                       &feat_num[ECORE_ISCSI_CQ];
3076                 u32 limit = sb_cnt.cnt;
3077
3078                 /* The number of queues should not exceed the number of FP SBs.
3079                  * In storage target, the queues are divided into pairs of a CQ
3080                  * and a CmdQ, and each pair uses a single SB. The limit in
3081                  * this case should allow a max ratio of 2:1 instead of 1:1.
3082                  */
3083                 if (p_hwfn->p_dev->b_is_target)
3084                         limit *= 2;
3085                 *p_storage_feat = OSAL_MIN_T(u32, limit,
3086                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
3087
3088                 /* @DPDK */
3089                 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init
3090                  * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2".
3091                  */
3092                 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat,
3093                                              (NUM_OF_GLOBAL_QUEUES / 2));
3094         }
3095
3096         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3097                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
3098                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
3099                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
3100                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
3101                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
3102                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
3103                    (int)sb_cnt.cnt);
3104 }
3105
3106 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
3107 {
3108         switch (res_id) {
3109         case ECORE_L2_QUEUE:
3110                 return "L2_QUEUE";
3111         case ECORE_VPORT:
3112                 return "VPORT";
3113         case ECORE_RSS_ENG:
3114                 return "RSS_ENG";
3115         case ECORE_PQ:
3116                 return "PQ";
3117         case ECORE_RL:
3118                 return "RL";
3119         case ECORE_MAC:
3120                 return "MAC";
3121         case ECORE_VLAN:
3122                 return "VLAN";
3123         case ECORE_RDMA_CNQ_RAM:
3124                 return "RDMA_CNQ_RAM";
3125         case ECORE_ILT:
3126                 return "ILT";
3127         case ECORE_LL2_QUEUE:
3128                 return "LL2_QUEUE";
3129         case ECORE_CMDQS_CQS:
3130                 return "CMDQS_CQS";
3131         case ECORE_RDMA_STATS_QUEUE:
3132                 return "RDMA_STATS_QUEUE";
3133         case ECORE_BDQ:
3134                 return "BDQ";
3135         case ECORE_SB:
3136                 return "SB";
3137         default:
3138                 return "UNKNOWN_RESOURCE";
3139         }
3140 }
3141
3142 static enum _ecore_status_t
3143 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3144                               struct ecore_ptt *p_ptt,
3145                               enum ecore_resources res_id,
3146                               u32 resc_max_val,
3147                               u32 *p_mcp_resp)
3148 {
3149         enum _ecore_status_t rc;
3150
3151         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3152                                         resc_max_val, p_mcp_resp);
3153         if (rc != ECORE_SUCCESS) {
3154                 DP_NOTICE(p_hwfn, false,
3155                           "MFW response failure for a max value setting of resource %d [%s]\n",
3156                           res_id, ecore_hw_get_resc_name(res_id));
3157                 return rc;
3158         }
3159
3160         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3161                 DP_INFO(p_hwfn,
3162                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3163                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
3164
3165         return ECORE_SUCCESS;
3166 }
3167
3168 static enum _ecore_status_t
3169 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3170                             struct ecore_ptt *p_ptt)
3171 {
3172         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3173         u32 resc_max_val, mcp_resp;
3174         u8 res_id;
3175         enum _ecore_status_t rc;
3176
3177         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3178                 /* @DPDK */
3179                 switch (res_id) {
3180                 case ECORE_LL2_QUEUE:
3181                 case ECORE_RDMA_CNQ_RAM:
3182                 case ECORE_RDMA_STATS_QUEUE:
3183                 case ECORE_BDQ:
3184                         resc_max_val = 0;
3185                         break;
3186                 default:
3187                         continue;
3188                 }
3189
3190                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3191                                                    resc_max_val, &mcp_resp);
3192                 if (rc != ECORE_SUCCESS)
3193                         return rc;
3194
3195                 /* There's no point to continue to the next resource if the
3196                  * command is not supported by the MFW.
3197                  * We do continue if the command is supported but the resource
3198                  * is unknown to the MFW. Such a resource will be later
3199                  * configured with the default allocation values.
3200                  */
3201                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3202                         return ECORE_NOTIMPL;
3203         }
3204
3205         return ECORE_SUCCESS;
3206 }
3207
3208 static
3209 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3210                                             enum ecore_resources res_id,
3211                                             u32 *p_resc_num, u32 *p_resc_start)
3212 {
3213         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3214         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3215
3216         switch (res_id) {
3217         case ECORE_L2_QUEUE:
3218                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3219                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
3220                 break;
3221         case ECORE_VPORT:
3222                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3223                                  MAX_NUM_VPORTS_BB) / num_funcs;
3224                 break;
3225         case ECORE_RSS_ENG:
3226                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3227                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3228                 break;
3229         case ECORE_PQ:
3230                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3231                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
3232                 break;
3233         case ECORE_RL:
3234                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3235                 break;
3236         case ECORE_MAC:
3237         case ECORE_VLAN:
3238                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3239                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3240                 break;
3241         case ECORE_ILT:
3242                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3243                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3244                 break;
3245         case ECORE_LL2_QUEUE:
3246                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3247                 break;
3248         case ECORE_RDMA_CNQ_RAM:
3249         case ECORE_CMDQS_CQS:
3250                 /* CNQ/CMDQS are the same resource */
3251                 /* @DPDK */
3252                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3253                 break;
3254         case ECORE_RDMA_STATS_QUEUE:
3255                 /* @DPDK */
3256                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3257                                  MAX_NUM_VPORTS_BB) / num_funcs;
3258                 break;
3259         case ECORE_BDQ:
3260                 /* @DPDK */
3261                 *p_resc_num = 0;
3262                 break;
3263         default:
3264                 break;
3265         }
3266
3267
3268         switch (res_id) {
3269         case ECORE_BDQ:
3270                 if (!*p_resc_num)
3271                         *p_resc_start = 0;
3272                 break;
3273         case ECORE_SB:
3274                 /* Since we want its value to reflect whether MFW supports
3275                  * the new scheme, have a default of 0.
3276                  */
3277                 *p_resc_num = 0;
3278                 break;
3279         default:
3280                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3281                 break;
3282         }
3283
3284         return ECORE_SUCCESS;
3285 }
3286
3287 static enum _ecore_status_t
3288 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3289                          bool drv_resc_alloc)
3290 {
3291         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3292         u32 mcp_resp, *p_resc_num, *p_resc_start;
3293         enum _ecore_status_t rc;
3294
3295         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3296         p_resc_start = &RESC_START(p_hwfn, res_id);
3297
3298         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3299                                     &dflt_resc_start);
3300         if (rc != ECORE_SUCCESS) {
3301                 DP_ERR(p_hwfn,
3302                        "Failed to get default amount for resource %d [%s]\n",
3303                         res_id, ecore_hw_get_resc_name(res_id));
3304                 return rc;
3305         }
3306
3307 #ifndef ASIC_ONLY
3308         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3309                 *p_resc_num = dflt_resc_num;
3310                 *p_resc_start = dflt_resc_start;
3311                 goto out;
3312         }
3313 #endif
3314
3315         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3316                                      &mcp_resp, p_resc_num, p_resc_start);
3317         if (rc != ECORE_SUCCESS) {
3318                 DP_NOTICE(p_hwfn, true,
3319                           "MFW response failure for an allocation request for"
3320                           " resource %d [%s]\n",
3321                           res_id, ecore_hw_get_resc_name(res_id));
3322                 return rc;
3323         }
3324
3325         /* Default driver values are applied in the following cases:
3326          * - The resource allocation MB command is not supported by the MFW
3327          * - There is an internal error in the MFW while processing the request
3328          * - The resource ID is unknown to the MFW
3329          */
3330         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3331                 DP_INFO(p_hwfn,
3332                         "Failed to receive allocation info for resource %d [%s]."
3333                         " mcp_resp = 0x%x. Applying default values"
3334                         " [%d,%d].\n",
3335                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3336                         dflt_resc_num, dflt_resc_start);
3337
3338                 *p_resc_num = dflt_resc_num;
3339                 *p_resc_start = dflt_resc_start;
3340                 goto out;
3341         }
3342
3343         if ((*p_resc_num != dflt_resc_num ||
3344              *p_resc_start != dflt_resc_start) &&
3345             res_id != ECORE_SB) {
3346                 DP_INFO(p_hwfn,
3347                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3348                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3349                         *p_resc_start, dflt_resc_num, dflt_resc_start,
3350                         drv_resc_alloc ? " - Applying default values" : "");
3351                 if (drv_resc_alloc) {
3352                         *p_resc_num = dflt_resc_num;
3353                         *p_resc_start = dflt_resc_start;
3354                 }
3355         }
3356 out:
3357         return ECORE_SUCCESS;
3358 }
3359
3360 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3361                                                    bool drv_resc_alloc)
3362 {
3363         enum _ecore_status_t rc;
3364         u8 res_id;
3365
3366         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3367                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3368                 if (rc != ECORE_SUCCESS)
3369                         return rc;
3370         }
3371
3372         return ECORE_SUCCESS;
3373 }
3374
3375 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3376                                               struct ecore_ptt *p_ptt,
3377                                               bool drv_resc_alloc)
3378 {
3379         struct ecore_resc_unlock_params resc_unlock_params;
3380         struct ecore_resc_lock_params resc_lock_params;
3381         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3382         u8 res_id;
3383         enum _ecore_status_t rc;
3384 #ifndef ASIC_ONLY
3385         u32 *resc_start = p_hwfn->hw_info.resc_start;
3386         u32 *resc_num = p_hwfn->hw_info.resc_num;
3387         /* For AH, an equal share of the ILT lines between the maximal number of
3388          * PFs is not enough for RoCE. This would be solved by the future
3389          * resource allocation scheme, but isn't currently present for
3390          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3391          * to work - the BB number of ILT lines divided by its max PFs number.
3392          */
3393         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3394 #endif
3395
3396         /* Setting the max values of the soft resources and the following
3397          * resources allocation queries should be atomic. Since several PFs can
3398          * run in parallel - a resource lock is needed.
3399          * If either the resource lock or resource set value commands are not
3400          * supported - skip the max values setting, release the lock if
3401          * needed, and proceed to the queries. Other failures, including a
3402          * failure to acquire the lock, will cause this function to fail.
3403          * Old drivers that don't acquire the lock can run in parallel, and
3404          * their allocation values won't be affected by the updated max values.
3405          */
3406         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3407                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
3408
3409         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3410         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3411                 return rc;
3412         } else if (rc == ECORE_NOTIMPL) {
3413                 DP_INFO(p_hwfn,
3414                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3415         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3416                 DP_NOTICE(p_hwfn, false,
3417                           "Failed to acquire the resource lock for the resource allocation commands\n");
3418                 rc = ECORE_BUSY;
3419                 goto unlock_and_exit;
3420         } else {
3421                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3422                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3423                         DP_NOTICE(p_hwfn, false,
3424                                   "Failed to set the max values of the soft resources\n");
3425                         goto unlock_and_exit;
3426                 } else if (rc == ECORE_NOTIMPL) {
3427                         DP_INFO(p_hwfn,
3428                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3429                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3430                                                    &resc_unlock_params);
3431                         if (rc != ECORE_SUCCESS)
3432                                 DP_INFO(p_hwfn,
3433                                         "Failed to release the resource lock for the resource allocation commands\n");
3434                 }
3435         }
3436
3437         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3438         if (rc != ECORE_SUCCESS)
3439                 goto unlock_and_exit;
3440
3441         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3442                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3443                                            &resc_unlock_params);
3444                 if (rc != ECORE_SUCCESS)
3445                         DP_INFO(p_hwfn,
3446                                 "Failed to release the resource lock for the resource allocation commands\n");
3447         }
3448
3449 #ifndef ASIC_ONLY
3450         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3451                 /* Reduced build contains less PQs */
3452                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3453                         resc_num[ECORE_PQ] = 32;
3454                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3455                             p_hwfn->enabled_func_idx;
3456                 }
3457
3458                 /* For AH emulation, since we have a possible maximal number of
3459                  * 16 enabled PFs, in case there are not enough ILT lines -
3460                  * allocate only first PF as RoCE and have all the other ETH
3461                  * only with less ILT lines.
3462                  */
3463                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3464                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3465                                                          resc_num[ECORE_ILT],
3466                                                          roce_min_ilt_lines);
3467         }
3468
3469         /* Correct the common ILT calculation if PF0 has more */
3470         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3471             p_hwfn->p_dev->b_is_emul_full &&
3472             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3473                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3474                     resc_num[ECORE_ILT];
3475 #endif
3476
3477         /* Sanity for ILT */
3478         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3479             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3480                 DP_NOTICE(p_hwfn, true,
3481                           "Can't assign ILT pages [%08x,...,%08x]\n",
3482                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3483                                                                   ECORE_ILT) -
3484                           1);
3485                 return ECORE_INVAL;
3486         }
3487
3488         /* This will also learn the number of SBs from MFW */
3489         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3490                 return ECORE_INVAL;
3491
3492         ecore_hw_set_feat(p_hwfn);
3493
3494         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3495                    "The numbers for each resource are:\n");
3496         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3497                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3498                            ecore_hw_get_resc_name(res_id),
3499                            RESC_NUM(p_hwfn, res_id),
3500                            RESC_START(p_hwfn, res_id));
3501
3502         return ECORE_SUCCESS;
3503
3504 unlock_and_exit:
3505         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3506                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3507                                       &resc_unlock_params);
3508         return rc;
3509 }
3510
3511 static enum _ecore_status_t
3512 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3513                       struct ecore_ptt *p_ptt,
3514                       struct ecore_hw_prepare_params *p_params)
3515 {
3516         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3517         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3518         struct ecore_mcp_link_capabilities *p_caps;
3519         struct ecore_mcp_link_params *link;
3520         enum _ecore_status_t rc;
3521
3522         /* Read global nvm_cfg address */
3523         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3524
3525         /* Verify MCP has initialized it */
3526         if (!nvm_cfg_addr) {
3527                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3528                 if (p_params->b_relaxed_probe)
3529                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3530                 return ECORE_INVAL;
3531         }
3532
3533 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3534
3535         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3536
3537         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3538                    OFFSETOF(struct nvm_cfg1, glob) +
3539                    OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3540
3541         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3542
3543         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3544                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3545         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3546                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3547                 break;
3548         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3549                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3550                 break;
3551         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3552                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3553                 break;
3554         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3555                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3556                 break;
3557         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3558                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3559                 break;
3560         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3561                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3562                 break;
3563         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3564                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3565                 break;
3566         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3567                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3568                 break;
3569         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3570                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3571                 break;
3572         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3573                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3574                 break;
3575         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3576                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3577                 break;
3578         default:
3579                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3580                           core_cfg);
3581                 break;
3582         }
3583
3584         /* Read DCBX configuration */
3585         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3586                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3587         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3588                              port_cfg_addr +
3589                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3590         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3591                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3592         switch (dcbx_mode) {
3593         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3594                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3595                 break;
3596         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3597                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3598                 break;
3599         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3600                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3601                 break;
3602         default:
3603                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3604         }
3605
3606         /* Read default link configuration */
3607         link = &p_hwfn->mcp_info->link_input;
3608         p_caps = &p_hwfn->mcp_info->link_capabilities;
3609         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3610             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3611         link_temp = ecore_rd(p_hwfn, p_ptt,
3612                              port_cfg_addr +
3613                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3614         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3615         link->speed.advertised_speeds = link_temp;
3616         p_caps->speed_capabilities = link->speed.advertised_speeds;
3617
3618         link_temp = ecore_rd(p_hwfn, p_ptt,
3619                                  port_cfg_addr +
3620                                  OFFSETOF(struct nvm_cfg1_port, link_settings));
3621         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3622                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3623         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3624                 link->speed.autoneg = true;
3625                 break;
3626         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3627                 link->speed.forced_speed = 1000;
3628                 break;
3629         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3630                 link->speed.forced_speed = 10000;
3631                 break;
3632         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3633                 link->speed.forced_speed = 25000;
3634                 break;
3635         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3636                 link->speed.forced_speed = 40000;
3637                 break;
3638         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3639                 link->speed.forced_speed = 50000;
3640                 break;
3641         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3642                 link->speed.forced_speed = 100000;
3643                 break;
3644         default:
3645                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3646         }
3647
3648         p_caps->default_speed = link->speed.forced_speed;
3649         p_caps->default_speed_autoneg = link->speed.autoneg;
3650
3651         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3652         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3653         link->pause.autoneg = !!(link_temp &
3654                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3655         link->pause.forced_rx = !!(link_temp &
3656                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3657         link->pause.forced_tx = !!(link_temp &
3658                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3659         link->loopback_mode = 0;
3660
3661         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3662                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3663                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3664                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3665                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3666                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3667                 link->eee.enable = true;
3668                 switch (link_temp) {
3669                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3670                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3671                         link->eee.enable = false;
3672                         break;
3673                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3674                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3675                         break;
3676                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3677                         p_caps->eee_lpi_timer =
3678                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3679                         break;
3680                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3681                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3682                         break;
3683                 }
3684
3685                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3686                 link->eee.tx_lpi_enable = link->eee.enable;
3687                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3688         } else {
3689                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3690         }
3691
3692         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3693                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3694                    link->speed.forced_speed, link->speed.advertised_speeds,
3695                    link->speed.autoneg, link->pause.autoneg,
3696                    p_caps->default_eee, p_caps->eee_lpi_timer);
3697
3698         /* Read Multi-function information from shmem */
3699         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3700                    OFFSETOF(struct nvm_cfg1, glob) +
3701                    OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3702
3703         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3704
3705         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3706             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3707
3708         switch (mf_mode) {
3709         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3710                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3711                 break;
3712         case NVM_CFG1_GLOB_MF_MODE_UFP:
3713                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3714                                          1 << ECORE_MF_UFP_SPECIFIC |
3715                                          1 << ECORE_MF_8021Q_TAGGING;
3716                 break;
3717         case NVM_CFG1_GLOB_MF_MODE_BD:
3718                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3719                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3720                                          1 << ECORE_MF_8021AD_TAGGING |
3721                                          1 << ECORE_MF_FIP_SPECIAL;
3722                 break;
3723         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3724                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3725                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3726                                          1 << ECORE_MF_LL2_NON_UNICAST |
3727                                          1 << ECORE_MF_INTER_PF_SWITCH |
3728                                          1 << ECORE_MF_DISABLE_ARFS;
3729                 break;
3730         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3731                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3732                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3733                                          1 << ECORE_MF_LL2_NON_UNICAST;
3734                 if (ECORE_IS_BB(p_hwfn->p_dev))
3735                         p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3736                 break;
3737         }
3738         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3739                 p_hwfn->p_dev->mf_bits);
3740
3741         if (ECORE_IS_CMT(p_hwfn->p_dev))
3742                 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3743
3744         /* It's funny since we have another switch, but it's easier
3745          * to throw this away in linux this way. Long term, it might be
3746          * better to have have getters for needed ECORE_MF_* fields,
3747          * convert client code and eliminate this.
3748          */
3749         switch (mf_mode) {
3750         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3751         case NVM_CFG1_GLOB_MF_MODE_BD:
3752                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3753                 break;
3754         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3755                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3756                 break;
3757         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3758                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3759                 break;
3760         case NVM_CFG1_GLOB_MF_MODE_UFP:
3761                 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3762                 break;
3763         }
3764
3765         /* Read Multi-function information from shmem */
3766         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3767                    OFFSETOF(struct nvm_cfg1, glob) +
3768                    OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3769
3770         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3771         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3772                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3773                                 &p_hwfn->hw_info.device_capabilities);
3774         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3775                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3776                                 &p_hwfn->hw_info.device_capabilities);
3777         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3778                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3779                                 &p_hwfn->hw_info.device_capabilities);
3780         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3781                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3782                                 &p_hwfn->hw_info.device_capabilities);
3783         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3784                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3785                                 &p_hwfn->hw_info.device_capabilities);
3786
3787         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3788         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3789                 rc = ECORE_SUCCESS;
3790                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3791         }
3792
3793         return rc;
3794 }
3795
3796 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3797                                 struct ecore_ptt *p_ptt)
3798 {
3799         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3800         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3801         struct ecore_dev *p_dev = p_hwfn->p_dev;
3802
3803         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3804
3805         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3806          * in the other bits are selected.
3807          * Bits 1-15 are for functions 1-15, respectively, and their value is
3808          * '0' only for enabled functions (function 0 always exists and
3809          * enabled).
3810          * In case of CMT in BB, only the "even" functions are enabled, and thus
3811          * the number of functions for both hwfns is learnt from the same bits.
3812          */
3813         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3814                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3815                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3816         } else { /* E5 */
3817                 reg_function_hide = 0;
3818         }
3819
3820         if (reg_function_hide & 0x1) {
3821                 if (ECORE_IS_BB(p_dev)) {
3822                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3823                                 num_funcs = 0;
3824                                 eng_mask = 0xaaaa;
3825                         } else {
3826                                 num_funcs = 1;
3827                                 eng_mask = 0x5554;
3828                         }
3829                 } else {
3830                         num_funcs = 1;
3831                         eng_mask = 0xfffe;
3832                 }
3833
3834                 /* Get the number of the enabled functions on the engine */
3835                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3836                 while (tmp) {
3837                         if (tmp & 0x1)
3838                                 num_funcs++;
3839                         tmp >>= 0x1;
3840                 }
3841
3842                 /* Get the PF index within the enabled functions */
3843                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3844                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3845                 while (tmp) {
3846                         if (tmp & 0x1)
3847                                 enabled_func_idx--;
3848                         tmp >>= 0x1;
3849                 }
3850         }
3851
3852         p_hwfn->num_funcs_on_engine = num_funcs;
3853         p_hwfn->enabled_func_idx = enabled_func_idx;
3854
3855 #ifndef ASIC_ONLY
3856         if (CHIP_REV_IS_FPGA(p_dev)) {
3857                 DP_NOTICE(p_hwfn, false,
3858                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3859                 p_hwfn->num_funcs_on_engine = 4;
3860         }
3861 #endif
3862
3863         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3864                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3865                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3866                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3867 }
3868
3869 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3870                                       struct ecore_ptt *p_ptt)
3871 {
3872         struct ecore_dev *p_dev = p_hwfn->p_dev;
3873         u32 port_mode;
3874
3875 #ifndef ASIC_ONLY
3876         /* Read the port mode */
3877         if (CHIP_REV_IS_FPGA(p_dev))
3878                 port_mode = 4;
3879         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3880                 /* In CMT on emulation, assume 1 port */
3881                 port_mode = 1;
3882         else
3883 #endif
3884         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3885
3886         if (port_mode < 3) {
3887                 p_dev->num_ports_in_engine = 1;
3888         } else if (port_mode <= 5) {
3889                 p_dev->num_ports_in_engine = 2;
3890         } else {
3891                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3892                           p_dev->num_ports_in_engine);
3893
3894                 /* Default num_ports_in_engine to something */
3895                 p_dev->num_ports_in_engine = 1;
3896         }
3897 }
3898
3899 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3900                                          struct ecore_ptt *p_ptt)
3901 {
3902         struct ecore_dev *p_dev = p_hwfn->p_dev;
3903         u32 port;
3904         int i;
3905
3906         p_dev->num_ports_in_engine = 0;
3907
3908 #ifndef ASIC_ONLY
3909         if (CHIP_REV_IS_EMUL(p_dev)) {
3910                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3911                 switch ((port & 0xf000) >> 12) {
3912                 case 1:
3913                         p_dev->num_ports_in_engine = 1;
3914                         break;
3915                 case 3:
3916                         p_dev->num_ports_in_engine = 2;
3917                         break;
3918                 case 0xf:
3919                         p_dev->num_ports_in_engine = 4;
3920                         break;
3921                 default:
3922                         DP_NOTICE(p_hwfn, false,
3923                                   "Unknown port mode in ECO_RESERVED %08x\n",
3924                                   port);
3925                 }
3926         } else
3927 #endif
3928                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3929                         port = ecore_rd(p_hwfn, p_ptt,
3930                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3931                                         (i * 4));
3932                         if (port & 1)
3933                                 p_dev->num_ports_in_engine++;
3934                 }
3935
3936         if (!p_dev->num_ports_in_engine) {
3937                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3938
3939                 /* Default num_ports_in_engine to something */
3940                 p_dev->num_ports_in_engine = 1;
3941         }
3942 }
3943
3944 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3945                                    struct ecore_ptt *p_ptt)
3946 {
3947         struct ecore_dev *p_dev = p_hwfn->p_dev;
3948
3949         /* Determine the number of ports per engine */
3950         if (ECORE_IS_BB(p_dev))
3951                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3952         else
3953                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3954
3955         /* Get the total number of ports of the device */
3956         if (ECORE_IS_CMT(p_dev)) {
3957                 /* In CMT there is always only one port */
3958                 p_dev->num_ports = 1;
3959 #ifndef ASIC_ONLY
3960         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3961                 p_dev->num_ports = p_dev->num_ports_in_engine *
3962                                    ecore_device_num_engines(p_dev);
3963 #endif
3964         } else {
3965                 u32 addr, global_offsize, global_addr;
3966
3967                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3968                                             PUBLIC_GLOBAL);
3969                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3970                 global_addr = SECTION_ADDR(global_offsize, 0);
3971                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3972                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3973         }
3974 }
3975
3976 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3977                                    struct ecore_ptt *p_ptt)
3978 {
3979         struct ecore_mcp_link_capabilities *p_caps;
3980         u32 eee_status;
3981
3982         p_caps = &p_hwfn->mcp_info->link_capabilities;
3983         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3984                 return;
3985
3986         p_caps->eee_speed_caps = 0;
3987         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3988                               OFFSETOF(struct public_port, eee_status));
3989         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3990                         EEE_SUPPORTED_SPEED_OFFSET;
3991         if (eee_status & EEE_1G_SUPPORTED)
3992                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3993         if (eee_status & EEE_10G_ADV)
3994                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3995 }
3996
3997 static enum _ecore_status_t
3998 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3999                   enum ecore_pci_personality personality,
4000                   struct ecore_hw_prepare_params *p_params)
4001 {
4002         bool drv_resc_alloc = p_params->drv_resc_alloc;
4003         enum _ecore_status_t rc;
4004
4005         if (IS_ECORE_PACING(p_hwfn)) {
4006                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
4007                            "Skipping IOV as packet pacing is requested\n");
4008         }
4009
4010         /* Since all information is common, only first hwfns should do this */
4011         if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
4012                 rc = ecore_iov_hw_info(p_hwfn);
4013                 if (rc != ECORE_SUCCESS) {
4014                         if (p_params->b_relaxed_probe)
4015                                 p_params->p_relaxed_res =
4016                                                 ECORE_HW_PREPARE_BAD_IOV;
4017                         else
4018                                 return rc;
4019                 }
4020         }
4021
4022         if (IS_LEAD_HWFN(p_hwfn))
4023                 ecore_hw_info_port_num(p_hwfn, p_ptt);
4024
4025         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
4026
4027 #ifndef ASIC_ONLY
4028         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
4029 #endif
4030         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
4031         if (rc != ECORE_SUCCESS)
4032                 return rc;
4033 #ifndef ASIC_ONLY
4034         }
4035 #endif
4036
4037         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
4038         if (rc != ECORE_SUCCESS) {
4039                 if (p_params->b_relaxed_probe)
4040                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
4041                 else
4042                         return rc;
4043         }
4044
4045 #ifndef ASIC_ONLY
4046         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
4047 #endif
4048                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
4049                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
4050 #ifndef ASIC_ONLY
4051         } else {
4052                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
4053
4054                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
4055                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
4056         }
4057 #endif
4058
4059         if (ecore_mcp_is_init(p_hwfn)) {
4060                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
4061                         p_hwfn->hw_info.ovlan =
4062                             p_hwfn->mcp_info->func_info.ovlan;
4063
4064                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
4065
4066                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
4067
4068                 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
4069         }
4070
4071         if (personality != ECORE_PCI_DEFAULT) {
4072                 p_hwfn->hw_info.personality = personality;
4073         } else if (ecore_mcp_is_init(p_hwfn)) {
4074                 enum ecore_pci_personality protocol;
4075
4076                 protocol = p_hwfn->mcp_info->func_info.protocol;
4077                 p_hwfn->hw_info.personality = protocol;
4078         }
4079
4080 #ifndef ASIC_ONLY
4081         /* To overcome ILT lack for emulation, until at least until we'll have
4082          * a definite answer from system about it, allow only PF0 to be RoCE.
4083          */
4084         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
4085                 if (!p_hwfn->rel_pf_id)
4086                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
4087                 else
4088                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
4089         }
4090 #endif
4091
4092         /* although in BB some constellations may support more than 4 tcs,
4093          * that can result in performance penalty in some cases. 4
4094          * represents a good tradeoff between performance and flexibility.
4095          */
4096         if (IS_ECORE_PACING(p_hwfn))
4097                 p_hwfn->hw_info.num_hw_tc = 1;
4098         else
4099                 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4100
4101         /* start out with a single active tc. This can be increased either
4102          * by dcbx negotiation or by upper layer driver
4103          */
4104         p_hwfn->hw_info.num_active_tc = 1;
4105
4106         ecore_get_num_funcs(p_hwfn, p_ptt);
4107
4108         if (ecore_mcp_is_init(p_hwfn))
4109                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4110
4111         /* In case of forcing the driver's default resource allocation, calling
4112          * ecore_hw_get_resc() should come after initializing the personality
4113          * and after getting the number of functions, since the calculation of
4114          * the resources/features depends on them.
4115          * This order is not harmful if not forcing.
4116          */
4117         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
4118         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
4119                 rc = ECORE_SUCCESS;
4120                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
4121         }
4122
4123         return rc;
4124 }
4125
4126 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
4127                                                struct ecore_ptt *p_ptt)
4128 {
4129         struct ecore_dev *p_dev = p_hwfn->p_dev;
4130         u16 device_id_mask;
4131         u32 tmp;
4132
4133         /* Read Vendor Id / Device Id */
4134         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
4135                                   &p_dev->vendor_id);
4136         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
4137                                   &p_dev->device_id);
4138
4139         /* Determine type */
4140         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
4141         switch (device_id_mask) {
4142         case ECORE_DEV_ID_MASK_BB:
4143                 p_dev->type = ECORE_DEV_TYPE_BB;
4144                 break;
4145         case ECORE_DEV_ID_MASK_AH:
4146                 p_dev->type = ECORE_DEV_TYPE_AH;
4147                 break;
4148         default:
4149                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
4150                           p_dev->device_id);
4151                 return ECORE_ABORTED;
4152         }
4153
4154         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4155         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
4156         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4157         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
4158
4159         /* Learn number of HW-functions */
4160         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4161
4162         if (tmp & (1 << p_hwfn->rel_pf_id)) {
4163                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
4164                 p_dev->num_hwfns = 2;
4165         } else {
4166                 p_dev->num_hwfns = 1;
4167         }
4168
4169 #ifndef ASIC_ONLY
4170         if (CHIP_REV_IS_EMUL(p_dev)) {
4171                 /* For some reason we have problems with this register
4172                  * in B0 emulation; Simply assume no CMT
4173                  */
4174                 DP_NOTICE(p_dev->hwfns, false,
4175                           "device on emul - assume no CMT\n");
4176                 p_dev->num_hwfns = 1;
4177         }
4178 #endif
4179
4180         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
4181         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
4182         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4183         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
4184
4185         DP_INFO(p_dev->hwfns,
4186                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
4187                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
4188                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
4189                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
4190                 p_dev->chip_metal);
4191
4192         if (ECORE_IS_BB_A0(p_dev)) {
4193                 DP_NOTICE(p_dev->hwfns, false,
4194                           "The chip type/rev (BB A0) is not supported!\n");
4195                 return ECORE_ABORTED;
4196         }
4197 #ifndef ASIC_ONLY
4198         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
4199                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
4200
4201         if (CHIP_REV_IS_EMUL(p_dev)) {
4202                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
4203                 if (tmp & (1 << 29)) {
4204                         DP_NOTICE(p_hwfn, false,
4205                                   "Emulation: Running on a FULL build\n");
4206                         p_dev->b_is_emul_full = true;
4207                 } else {
4208                         DP_NOTICE(p_hwfn, false,
4209                                   "Emulation: Running on a REDUCED build\n");
4210                 }
4211         }
4212 #endif
4213
4214         return ECORE_SUCCESS;
4215 }
4216
4217 #ifndef LINUX_REMOVE
4218 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
4219 {
4220         int j;
4221
4222         if (IS_VF(p_dev))
4223                 return;
4224
4225         for_each_hwfn(p_dev, j) {
4226                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4227
4228                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4229                            "Mark hw/fw uninitialized\n");
4230
4231                 p_hwfn->hw_init_done = false;
4232
4233                 ecore_ptt_invalidate(p_hwfn);
4234         }
4235 }
4236 #endif
4237
4238 static enum _ecore_status_t
4239 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4240                         void OSAL_IOMEM * p_regview,
4241                         void OSAL_IOMEM * p_doorbells,
4242                         struct ecore_hw_prepare_params *p_params)
4243 {
4244         struct ecore_mdump_retain_data mdump_retain;
4245         struct ecore_dev *p_dev = p_hwfn->p_dev;
4246         struct ecore_mdump_info mdump_info;
4247         enum _ecore_status_t rc = ECORE_SUCCESS;
4248
4249         /* Split PCI bars evenly between hwfns */
4250         p_hwfn->regview = p_regview;
4251         p_hwfn->doorbells = p_doorbells;
4252
4253         if (IS_VF(p_dev))
4254                 return ecore_vf_hw_prepare(p_hwfn);
4255
4256         /* Validate that chip access is feasible */
4257         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4258                 DP_ERR(p_hwfn,
4259                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4260                 if (p_params->b_relaxed_probe)
4261                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4262                 return ECORE_INVAL;
4263         }
4264
4265         get_function_id(p_hwfn);
4266
4267         /* Allocate PTT pool */
4268         rc = ecore_ptt_pool_alloc(p_hwfn);
4269         if (rc) {
4270                 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
4271                 if (p_params->b_relaxed_probe)
4272                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4273                 goto err0;
4274         }
4275
4276         /* Allocate the main PTT */
4277         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4278
4279         /* First hwfn learns basic information, e.g., number of hwfns */
4280         if (!p_hwfn->my_id) {
4281                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4282                 if (rc != ECORE_SUCCESS) {
4283                         if (p_params->b_relaxed_probe)
4284                                 p_params->p_relaxed_res =
4285                                         ECORE_HW_PREPARE_FAILED_DEV;
4286                         goto err1;
4287                 }
4288         }
4289
4290         ecore_hw_hwfn_prepare(p_hwfn);
4291
4292         /* Initialize MCP structure */
4293         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4294         if (rc) {
4295                 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
4296                 if (p_params->b_relaxed_probe)
4297                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4298                 goto err1;
4299         }
4300
4301         /* Read the device configuration information from the HW and SHMEM */
4302         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4303                                p_params->personality, p_params);
4304         if (rc) {
4305                 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
4306                 goto err2;
4307         }
4308
4309         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4310          * called, since among others it sets the ports number in an engine.
4311          */
4312         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4313             !p_dev->recov_in_prog) {
4314                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4315                 if (rc != ECORE_SUCCESS)
4316                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4317
4318                 /* Workaround for MFW issue where PF FLR does not cleanup
4319                  * IGU block
4320                  */
4321                 if (!(p_hwfn->mcp_info->capabilities &
4322                       FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
4323                         ecore_pf_flr_igu_cleanup(p_hwfn);
4324         }
4325
4326         /* Check if mdump logs/data are present and update the epoch value */
4327         if (IS_LEAD_HWFN(p_hwfn)) {
4328 #ifndef ASIC_ONLY
4329                 if (!CHIP_REV_IS_EMUL(p_dev)) {
4330 #endif
4331                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4332                                               &mdump_info);
4333                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4334                         DP_NOTICE(p_hwfn, false,
4335                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4336
4337                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4338                                                 &mdump_retain);
4339                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4340                         DP_NOTICE(p_hwfn, false,
4341                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4342                                   mdump_retain.epoch, mdump_retain.pf,
4343                                   mdump_retain.status);
4344
4345                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4346                                            p_params->epoch);
4347 #ifndef ASIC_ONLY
4348                 }
4349 #endif
4350         }
4351
4352         /* Allocate the init RT array and initialize the init-ops engine */
4353         rc = ecore_init_alloc(p_hwfn);
4354         if (rc) {
4355                 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
4356                 if (p_params->b_relaxed_probe)
4357                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4358                 goto err2;
4359         }
4360 #ifndef ASIC_ONLY
4361         if (CHIP_REV_IS_FPGA(p_dev)) {
4362                 DP_NOTICE(p_hwfn, false,
4363                           "FPGA: workaround; Prevent DMAE parities\n");
4364                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4365                          7);
4366
4367                 DP_NOTICE(p_hwfn, false,
4368                           "FPGA: workaround: Set VF bar0 size\n");
4369                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4370                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4371         }
4372 #endif
4373
4374         return rc;
4375 err2:
4376         if (IS_LEAD_HWFN(p_hwfn))
4377                 ecore_iov_free_hw_info(p_dev);
4378         ecore_mcp_free(p_hwfn);
4379 err1:
4380         ecore_hw_hwfn_free(p_hwfn);
4381 err0:
4382         return rc;
4383 }
4384
4385 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4386                                       struct ecore_hw_prepare_params *p_params)
4387 {
4388         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4389         enum _ecore_status_t rc;
4390
4391         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4392         p_dev->allow_mdump = p_params->allow_mdump;
4393         p_hwfn->b_en_pacing = p_params->b_en_pacing;
4394         p_dev->b_is_target = p_params->b_is_target;
4395
4396         if (p_params->b_relaxed_probe)
4397                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4398
4399         /* Store the precompiled init data ptrs */
4400         if (IS_PF(p_dev))
4401                 ecore_init_iro_array(p_dev);
4402
4403         /* Initialize the first hwfn - will learn number of hwfns */
4404         rc = ecore_hw_prepare_single(p_hwfn,
4405                                      p_dev->regview,
4406                                      p_dev->doorbells, p_params);
4407         if (rc != ECORE_SUCCESS)
4408                 return rc;
4409
4410         p_params->personality = p_hwfn->hw_info.personality;
4411
4412         /* initilalize 2nd hwfn if necessary */
4413         if (ECORE_IS_CMT(p_dev)) {
4414                 void OSAL_IOMEM *p_regview, *p_doorbell;
4415                 u8 OSAL_IOMEM *addr;
4416
4417                 /* adjust bar offset for second engine */
4418                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4419                                         ecore_hw_bar_size(p_hwfn,
4420                                                           p_hwfn->p_main_ptt,
4421                                                           BAR_ID_0) / 2;
4422                 p_regview = (void OSAL_IOMEM *)addr;
4423
4424                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4425                                         ecore_hw_bar_size(p_hwfn,
4426                                                           p_hwfn->p_main_ptt,
4427                                                           BAR_ID_1) / 2;
4428                 p_doorbell = (void OSAL_IOMEM *)addr;
4429
4430                 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
4431                 /* prepare second hw function */
4432                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4433                                              p_doorbell, p_params);
4434
4435                 /* in case of error, need to free the previously
4436                  * initiliazed hwfn 0.
4437                  */
4438                 if (rc != ECORE_SUCCESS) {
4439                         if (p_params->b_relaxed_probe)
4440                                 p_params->p_relaxed_res =
4441                                                 ECORE_HW_PREPARE_FAILED_ENG2;
4442
4443                         if (IS_PF(p_dev)) {
4444                                 ecore_init_free(p_hwfn);
4445                                 ecore_mcp_free(p_hwfn);
4446                                 ecore_hw_hwfn_free(p_hwfn);
4447                         } else {
4448                                 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
4449                         }
4450                         return rc;
4451                 }
4452         }
4453
4454         return rc;
4455 }
4456
4457 void ecore_hw_remove(struct ecore_dev *p_dev)
4458 {
4459         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4460         int i;
4461
4462         if (IS_PF(p_dev))
4463                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4464                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
4465
4466         for_each_hwfn(p_dev, i) {
4467                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4468
4469                 if (IS_VF(p_dev)) {
4470                         ecore_vf_pf_release(p_hwfn);
4471                         continue;
4472                 }
4473
4474                 ecore_init_free(p_hwfn);
4475                 ecore_hw_hwfn_free(p_hwfn);
4476                 ecore_mcp_free(p_hwfn);
4477
4478 #ifdef CONFIG_ECORE_LOCK_ALLOC
4479                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
4480 #endif
4481         }
4482
4483         ecore_iov_free_hw_info(p_dev);
4484 }
4485
4486 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4487                                       struct ecore_chain *p_chain)
4488 {
4489         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4490         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4491         struct ecore_chain_next *p_next;
4492         u32 size, i;
4493
4494         if (!p_virt)
4495                 return;
4496
4497         size = p_chain->elem_size * p_chain->usable_per_page;
4498
4499         for (i = 0; i < p_chain->page_cnt; i++) {
4500                 if (!p_virt)
4501                         break;
4502
4503                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4504                 p_virt_next = p_next->next_virt;
4505                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4506
4507                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4508                                        ECORE_CHAIN_PAGE_SIZE);
4509
4510                 p_virt = p_virt_next;
4511                 p_phys = p_phys_next;
4512         }
4513 }
4514
4515 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4516                                     struct ecore_chain *p_chain)
4517 {
4518         if (!p_chain->p_virt_addr)
4519                 return;
4520
4521         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4522                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4523 }
4524
4525 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4526                                  struct ecore_chain *p_chain)
4527 {
4528         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4529         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4530         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4531
4532         if (!pp_virt_addr_tbl)
4533                 return;
4534
4535         if (!p_pbl_virt)
4536                 goto out;
4537
4538         for (i = 0; i < page_cnt; i++) {
4539                 if (!pp_virt_addr_tbl[i])
4540                         break;
4541
4542                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4543                                        *(dma_addr_t *)p_pbl_virt,
4544                                        ECORE_CHAIN_PAGE_SIZE);
4545
4546                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4547         }
4548
4549         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4550
4551         if (!p_chain->b_external_pbl)
4552                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4553                                        p_chain->pbl_sp.p_phys_table, pbl_size);
4554 out:
4555         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4556 }
4557
4558 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4559 {
4560         switch (p_chain->mode) {
4561         case ECORE_CHAIN_MODE_NEXT_PTR:
4562                 ecore_chain_free_next_ptr(p_dev, p_chain);
4563                 break;
4564         case ECORE_CHAIN_MODE_SINGLE:
4565                 ecore_chain_free_single(p_dev, p_chain);
4566                 break;
4567         case ECORE_CHAIN_MODE_PBL:
4568                 ecore_chain_free_pbl(p_dev, p_chain);
4569                 break;
4570         }
4571 }
4572
4573 static enum _ecore_status_t
4574 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4575                                enum ecore_chain_cnt_type cnt_type,
4576                                osal_size_t elem_size, u32 page_cnt)
4577 {
4578         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4579
4580         /* The actual chain size can be larger than the maximal possible value
4581          * after rounding up the requested elements number to pages, and after
4582          * taking into acount the unusuable elements (next-ptr elements).
4583          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4584          * size/capacity fields are of a u32 type.
4585          */
4586         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4587              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4588             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4589              chain_size > ECORE_U32_MAX)) {
4590                 DP_NOTICE(p_dev, true,
4591                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4592                           (unsigned long)chain_size);
4593                 return ECORE_INVAL;
4594         }
4595
4596         return ECORE_SUCCESS;
4597 }
4598
4599 static enum _ecore_status_t
4600 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4601 {
4602         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4603         dma_addr_t p_phys = 0;
4604         u32 i;
4605
4606         for (i = 0; i < p_chain->page_cnt; i++) {
4607                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4608                                                  ECORE_CHAIN_PAGE_SIZE);
4609                 if (!p_virt) {
4610                         DP_NOTICE(p_dev, false,
4611                                   "Failed to allocate chain memory\n");
4612                         return ECORE_NOMEM;
4613                 }
4614
4615                 if (i == 0) {
4616                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4617                         ecore_chain_reset(p_chain);
4618                 } else {
4619                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4620                                                        p_virt, p_phys);
4621                 }
4622
4623                 p_virt_prev = p_virt;
4624         }
4625         /* Last page's next element should point to the beginning of the
4626          * chain.
4627          */
4628         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4629                                        p_chain->p_virt_addr,
4630                                        p_chain->p_phys_addr);
4631
4632         return ECORE_SUCCESS;
4633 }
4634
4635 static enum _ecore_status_t
4636 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4637 {
4638         dma_addr_t p_phys = 0;
4639         void *p_virt = OSAL_NULL;
4640
4641         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4642         if (!p_virt) {
4643                 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
4644                 return ECORE_NOMEM;
4645         }
4646
4647         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4648         ecore_chain_reset(p_chain);
4649
4650         return ECORE_SUCCESS;
4651 }
4652
4653 static enum _ecore_status_t
4654 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4655                       struct ecore_chain *p_chain,
4656                       struct ecore_chain_ext_pbl *ext_pbl)
4657 {
4658         u32 page_cnt = p_chain->page_cnt, size, i;
4659         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4660         void **pp_virt_addr_tbl = OSAL_NULL;
4661         u8 *p_pbl_virt = OSAL_NULL;
4662         void *p_virt = OSAL_NULL;
4663
4664         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4665         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4666         if (!pp_virt_addr_tbl) {
4667                 DP_NOTICE(p_dev, false,
4668                           "Failed to allocate memory for the chain virtual addresses table\n");
4669                 return ECORE_NOMEM;
4670         }
4671
4672         /* The allocation of the PBL table is done with its full size, since it
4673          * is expected to be successive.
4674          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4675          * failure, since pp_virt_addr_tbl was previously allocated, and it
4676          * should be saved to allow its freeing during the error flow.
4677          */
4678         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4679
4680         if (ext_pbl == OSAL_NULL) {
4681                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4682         } else {
4683                 p_pbl_virt = ext_pbl->p_pbl_virt;
4684                 p_pbl_phys = ext_pbl->p_pbl_phys;
4685                 p_chain->b_external_pbl = true;
4686         }
4687
4688         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4689                                  pp_virt_addr_tbl);
4690         if (!p_pbl_virt) {
4691                 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
4692                 return ECORE_NOMEM;
4693         }
4694
4695         for (i = 0; i < page_cnt; i++) {
4696                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4697                                                  ECORE_CHAIN_PAGE_SIZE);
4698                 if (!p_virt) {
4699                         DP_NOTICE(p_dev, false,
4700                                   "Failed to allocate chain memory\n");
4701                         return ECORE_NOMEM;
4702                 }
4703
4704                 if (i == 0) {
4705                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4706                         ecore_chain_reset(p_chain);
4707                 }
4708
4709                 /* Fill the PBL table with the physical address of the page */
4710                 *(dma_addr_t *)p_pbl_virt = p_phys;
4711                 /* Keep the virtual address of the page */
4712                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4713
4714                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4715         }
4716
4717         return ECORE_SUCCESS;
4718 }
4719
4720 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4721                                        enum ecore_chain_use_mode intended_use,
4722                                        enum ecore_chain_mode mode,
4723                                        enum ecore_chain_cnt_type cnt_type,
4724                                        u32 num_elems, osal_size_t elem_size,
4725                                        struct ecore_chain *p_chain,
4726                                        struct ecore_chain_ext_pbl *ext_pbl)
4727 {
4728         u32 page_cnt;
4729         enum _ecore_status_t rc = ECORE_SUCCESS;
4730
4731         if (mode == ECORE_CHAIN_MODE_SINGLE)
4732                 page_cnt = 1;
4733         else
4734                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4735
4736         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4737                                             page_cnt);
4738         if (rc) {
4739                 DP_NOTICE(p_dev, false,
4740                           "Cannot allocate a chain with the given arguments:\n"
4741                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4742                           intended_use, mode, cnt_type, num_elems, elem_size);
4743                 return rc;
4744         }
4745
4746         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4747                                 mode, cnt_type, p_dev->dp_ctx);
4748
4749         switch (mode) {
4750         case ECORE_CHAIN_MODE_NEXT_PTR:
4751                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4752                 break;
4753         case ECORE_CHAIN_MODE_SINGLE:
4754                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4755                 break;
4756         case ECORE_CHAIN_MODE_PBL:
4757                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4758                 break;
4759         }
4760         if (rc)
4761                 goto nomem;
4762
4763         return ECORE_SUCCESS;
4764
4765 nomem:
4766         ecore_chain_free(p_dev, p_chain);
4767         return rc;
4768 }
4769
4770 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4771                                        u16 src_id, u16 *dst_id)
4772 {
4773         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4774                 u16 min, max;
4775
4776                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4777                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4778                 DP_NOTICE(p_hwfn, true,
4779                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4780                           src_id, min, max);
4781
4782                 return ECORE_INVAL;
4783         }
4784
4785         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4786
4787         return ECORE_SUCCESS;
4788 }
4789
4790 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4791                                     u8 src_id, u8 *dst_id)
4792 {
4793         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4794                 u8 min, max;
4795
4796                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4797                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4798                 DP_NOTICE(p_hwfn, true,
4799                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4800                           src_id, min, max);
4801
4802                 return ECORE_INVAL;
4803         }
4804
4805         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4806
4807         return ECORE_SUCCESS;
4808 }
4809
4810 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4811                                       u8 src_id, u8 *dst_id)
4812 {
4813         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4814                 u8 min, max;
4815
4816                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4817                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4818                 DP_NOTICE(p_hwfn, true,
4819                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4820                           src_id, min, max);
4821
4822                 return ECORE_INVAL;
4823         }
4824
4825         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4826
4827         return ECORE_SUCCESS;
4828 }
4829
4830 static enum _ecore_status_t
4831 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4832                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4833                                u32 *p_entry_num)
4834 {
4835         u32 en;
4836         int i;
4837
4838         /* Find a free entry and utilize it */
4839         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4840                 en = ecore_rd(p_hwfn, p_ptt,
4841                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4842                               i * sizeof(u32));
4843                 if (en)
4844                         continue;
4845                 ecore_wr(p_hwfn, p_ptt,
4846                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4847                          2 * i * sizeof(u32), low);
4848                 ecore_wr(p_hwfn, p_ptt,
4849                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4850                          (2 * i + 1) * sizeof(u32), high);
4851                 ecore_wr(p_hwfn, p_ptt,
4852                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4853                          i * sizeof(u32), 0);
4854                 ecore_wr(p_hwfn, p_ptt,
4855                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4856                          i * sizeof(u32), 0);
4857                 ecore_wr(p_hwfn, p_ptt,
4858                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4859                          i * sizeof(u32), 1);
4860                 break;
4861         }
4862
4863         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4864                 return ECORE_NORESOURCES;
4865
4866         *p_entry_num = i;
4867
4868         return ECORE_SUCCESS;
4869 }
4870
4871 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4872                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4873 {
4874         u32 high, low, entry_num;
4875         enum _ecore_status_t rc = ECORE_SUCCESS;
4876
4877         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4878                            &p_hwfn->p_dev->mf_bits))
4879                 return ECORE_SUCCESS;
4880
4881         high = p_filter[1] | (p_filter[0] << 8);
4882         low = p_filter[5] | (p_filter[4] << 8) |
4883               (p_filter[3] << 16) | (p_filter[2] << 24);
4884
4885         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4886                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4887                                                     &entry_num);
4888         if (rc != ECORE_SUCCESS) {
4889                 DP_NOTICE(p_hwfn, false,
4890                           "Failed to find an empty LLH filter to utilize\n");
4891                 return rc;
4892         }
4893
4894         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4895                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4896                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4897                    p_filter[4], p_filter[5], entry_num);
4898
4899         return rc;
4900 }
4901
4902 static enum _ecore_status_t
4903 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4904                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4905                                   u32 *p_entry_num)
4906 {
4907         int i;
4908
4909         /* Find the entry and clean it */
4910         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4911                 if (ecore_rd(p_hwfn, p_ptt,
4912                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4913                              2 * i * sizeof(u32)) != low)
4914                         continue;
4915                 if (ecore_rd(p_hwfn, p_ptt,
4916                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4917                              (2 * i + 1) * sizeof(u32)) != high)
4918                         continue;
4919
4920                 ecore_wr(p_hwfn, p_ptt,
4921                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4922                 ecore_wr(p_hwfn, p_ptt,
4923                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4924                          2 * i * sizeof(u32), 0);
4925                 ecore_wr(p_hwfn, p_ptt,
4926                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4927                          (2 * i + 1) * sizeof(u32), 0);
4928                 break;
4929         }
4930
4931         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4932                 return ECORE_INVAL;
4933
4934         *p_entry_num = i;
4935
4936         return ECORE_SUCCESS;
4937 }
4938
4939 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4940                              struct ecore_ptt *p_ptt, u8 *p_filter)
4941 {
4942         u32 high, low, entry_num;
4943         enum _ecore_status_t rc = ECORE_SUCCESS;
4944
4945         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4946                            &p_hwfn->p_dev->mf_bits))
4947                 return;
4948
4949         high = p_filter[1] | (p_filter[0] << 8);
4950         low = p_filter[5] | (p_filter[4] << 8) |
4951               (p_filter[3] << 16) | (p_filter[2] << 24);
4952
4953         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4954                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4955                                                        low, &entry_num);
4956         if (rc != ECORE_SUCCESS) {
4957                 DP_NOTICE(p_hwfn, false,
4958                           "Tried to remove a non-configured filter\n");
4959                 return;
4960         }
4961
4962
4963         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4964                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4965                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4966                    p_filter[4], p_filter[5], entry_num);
4967 }
4968
4969 static enum _ecore_status_t
4970 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4971                                     struct ecore_ptt *p_ptt,
4972                                     enum ecore_llh_port_filter_type_t type,
4973                                     u32 high, u32 low, u32 *p_entry_num)
4974 {
4975         u32 en;
4976         int i;
4977
4978         /* Find a free entry and utilize it */
4979         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4980                 en = ecore_rd(p_hwfn, p_ptt,
4981                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4982                               i * sizeof(u32));
4983                 if (en)
4984                         continue;
4985                 ecore_wr(p_hwfn, p_ptt,
4986                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4987                          2 * i * sizeof(u32), low);
4988                 ecore_wr(p_hwfn, p_ptt,
4989                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4990                          (2 * i + 1) * sizeof(u32), high);
4991                 ecore_wr(p_hwfn, p_ptt,
4992                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4993                          i * sizeof(u32), 1);
4994                 ecore_wr(p_hwfn, p_ptt,
4995                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4996                          i * sizeof(u32), 1 << type);
4997                 ecore_wr(p_hwfn, p_ptt,
4998                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4999                 break;
5000         }
5001
5002         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
5003                 return ECORE_NORESOURCES;
5004
5005         *p_entry_num = i;
5006
5007         return ECORE_SUCCESS;
5008 }
5009
5010 enum _ecore_status_t
5011 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
5012                               struct ecore_ptt *p_ptt,
5013                               u16 source_port_or_eth_type,
5014                               u16 dest_port,
5015                               enum ecore_llh_port_filter_type_t type)
5016 {
5017         u32 high, low, entry_num;
5018         enum _ecore_status_t rc = ECORE_SUCCESS;
5019
5020         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5021                            &p_hwfn->p_dev->mf_bits))
5022                 return rc;
5023
5024         high = 0;
5025         low = 0;
5026
5027         switch (type) {
5028         case ECORE_LLH_FILTER_ETHERTYPE:
5029                 high = source_port_or_eth_type;
5030                 break;
5031         case ECORE_LLH_FILTER_TCP_SRC_PORT:
5032         case ECORE_LLH_FILTER_UDP_SRC_PORT:
5033                 low = source_port_or_eth_type << 16;
5034                 break;
5035         case ECORE_LLH_FILTER_TCP_DEST_PORT:
5036         case ECORE_LLH_FILTER_UDP_DEST_PORT:
5037                 low = dest_port;
5038                 break;
5039         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5040         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5041                 low = (source_port_or_eth_type << 16) | dest_port;
5042                 break;
5043         default:
5044                 DP_NOTICE(p_hwfn, true,
5045                           "Non valid LLH protocol filter type %d\n", type);
5046                 return ECORE_INVAL;
5047         }
5048
5049         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5050                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5051                                                          high, low, &entry_num);
5052         if (rc != ECORE_SUCCESS) {
5053                 DP_NOTICE(p_hwfn, false,
5054                           "Failed to find an empty LLH filter to utilize\n");
5055                 return rc;
5056         }
5057         switch (type) {
5058         case ECORE_LLH_FILTER_ETHERTYPE:
5059                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5060                            "ETH type %x is added at %d\n",
5061                            source_port_or_eth_type, entry_num);
5062                 break;
5063         case ECORE_LLH_FILTER_TCP_SRC_PORT:
5064                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5065                            "TCP src port %x is added at %d\n",
5066                            source_port_or_eth_type, entry_num);
5067                 break;
5068         case ECORE_LLH_FILTER_UDP_SRC_PORT:
5069                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5070                            "UDP src port %x is added at %d\n",
5071                            source_port_or_eth_type, entry_num);
5072                 break;
5073         case ECORE_LLH_FILTER_TCP_DEST_PORT:
5074                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5075                            "TCP dst port %x is added at %d\n", dest_port,
5076                            entry_num);
5077                 break;
5078         case ECORE_LLH_FILTER_UDP_DEST_PORT:
5079                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5080                            "UDP dst port %x is added at %d\n", dest_port,
5081                            entry_num);
5082                 break;
5083         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5084                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5085                            "TCP src/dst ports %x/%x are added at %d\n",
5086                            source_port_or_eth_type, dest_port, entry_num);
5087                 break;
5088         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5089                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5090                            "UDP src/dst ports %x/%x are added at %d\n",
5091                            source_port_or_eth_type, dest_port, entry_num);
5092                 break;
5093         }
5094
5095         return rc;
5096 }
5097
5098 static enum _ecore_status_t
5099 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
5100                                        struct ecore_ptt *p_ptt,
5101                                        enum ecore_llh_port_filter_type_t type,
5102                                        u32 high, u32 low, u32 *p_entry_num)
5103 {
5104         int i;
5105
5106         /* Find the entry and clean it */
5107         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5108                 if (!ecore_rd(p_hwfn, p_ptt,
5109                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
5110                               i * sizeof(u32)))
5111                         continue;
5112                 if (!ecore_rd(p_hwfn, p_ptt,
5113                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5114                               i * sizeof(u32)))
5115                         continue;
5116                 if (!(ecore_rd(p_hwfn, p_ptt,
5117                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5118                                i * sizeof(u32)) & (1 << type)))
5119                         continue;
5120                 if (ecore_rd(p_hwfn, p_ptt,
5121                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5122                              2 * i * sizeof(u32)) != low)
5123                         continue;
5124                 if (ecore_rd(p_hwfn, p_ptt,
5125                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5126                              (2 * i + 1) * sizeof(u32)) != high)
5127                         continue;
5128
5129                 ecore_wr(p_hwfn, p_ptt,
5130                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
5131                 ecore_wr(p_hwfn, p_ptt,
5132                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5133                          i * sizeof(u32), 0);
5134                 ecore_wr(p_hwfn, p_ptt,
5135                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5136                          i * sizeof(u32), 0);
5137                 ecore_wr(p_hwfn, p_ptt,
5138                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5139                          2 * i * sizeof(u32), 0);
5140                 ecore_wr(p_hwfn, p_ptt,
5141                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5142                          (2 * i + 1) * sizeof(u32), 0);
5143                 break;
5144         }
5145
5146         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
5147                 return ECORE_INVAL;
5148
5149         *p_entry_num = i;
5150
5151         return ECORE_SUCCESS;
5152 }
5153
5154 void
5155 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
5156                                  struct ecore_ptt *p_ptt,
5157                                  u16 source_port_or_eth_type,
5158                                  u16 dest_port,
5159                                  enum ecore_llh_port_filter_type_t type)
5160 {
5161         u32 high, low, entry_num;
5162         enum _ecore_status_t rc = ECORE_SUCCESS;
5163
5164         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5165                            &p_hwfn->p_dev->mf_bits))
5166                 return;
5167
5168         high = 0;
5169         low = 0;
5170
5171         switch (type) {
5172         case ECORE_LLH_FILTER_ETHERTYPE:
5173                 high = source_port_or_eth_type;
5174                 break;
5175         case ECORE_LLH_FILTER_TCP_SRC_PORT:
5176         case ECORE_LLH_FILTER_UDP_SRC_PORT:
5177                 low = source_port_or_eth_type << 16;
5178                 break;
5179         case ECORE_LLH_FILTER_TCP_DEST_PORT:
5180         case ECORE_LLH_FILTER_UDP_DEST_PORT:
5181                 low = dest_port;
5182                 break;
5183         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5184         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5185                 low = (source_port_or_eth_type << 16) | dest_port;
5186                 break;
5187         default:
5188                 DP_NOTICE(p_hwfn, true,
5189                           "Non valid LLH protocol filter type %d\n", type);
5190                 return;
5191         }
5192
5193         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5194                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5195                                                             high, low,
5196                                                             &entry_num);
5197         if (rc != ECORE_SUCCESS) {
5198                 DP_NOTICE(p_hwfn, false,
5199                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
5200                           type, source_port_or_eth_type, dest_port);
5201                 return;
5202         }
5203
5204         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5205                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
5206                    type, source_port_or_eth_type, dest_port, entry_num);
5207 }
5208
5209 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
5210                                               struct ecore_ptt *p_ptt)
5211 {
5212         int i;
5213
5214         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
5215                 return;
5216
5217         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5218                 ecore_wr(p_hwfn, p_ptt,
5219                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
5220                          i * sizeof(u32), 0);
5221                 ecore_wr(p_hwfn, p_ptt,
5222                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5223                          2 * i * sizeof(u32), 0);
5224                 ecore_wr(p_hwfn, p_ptt,
5225                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5226                          (2 * i + 1) * sizeof(u32), 0);
5227         }
5228 }
5229
5230 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
5231                              struct ecore_ptt *p_ptt)
5232 {
5233         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5234                            &p_hwfn->p_dev->mf_bits) &&
5235             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5236                            &p_hwfn->p_dev->mf_bits))
5237                 return;
5238
5239         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5240                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5241 }
5242
5243 enum _ecore_status_t
5244 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5245                                   struct ecore_ptt *p_ptt)
5246 {
5247         if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5248                 ecore_wr(p_hwfn, p_ptt,
5249                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5250                          1 << p_hwfn->abs_pf_id / 2);
5251                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5252                 return ECORE_SUCCESS;
5253         }
5254
5255         DP_NOTICE(p_hwfn, false,
5256                   "This function can't be set as default\n");
5257         return ECORE_INVAL;
5258 }
5259
5260 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5261                                                struct ecore_ptt *p_ptt,
5262                                                u32 hw_addr, void *p_eth_qzone,
5263                                                osal_size_t eth_qzone_size,
5264                                                u8 timeset)
5265 {
5266         struct coalescing_timeset *p_coal_timeset;
5267
5268         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5269                 DP_NOTICE(p_hwfn, true,
5270                           "Coalescing configuration not enabled\n");
5271                 return ECORE_INVAL;
5272         }
5273
5274         p_coal_timeset = p_eth_qzone;
5275         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5276         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5277         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5278         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5279
5280         return ECORE_SUCCESS;
5281 }
5282
5283 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5284                                               u16 rx_coal, u16 tx_coal,
5285                                               void *p_handle)
5286 {
5287         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5288         enum _ecore_status_t rc = ECORE_SUCCESS;
5289         struct ecore_ptt *p_ptt;
5290
5291         /* TODO - Configuring a single queue's coalescing but
5292          * claiming all queues are abiding same configuration
5293          * for PF and VF both.
5294          */
5295
5296         if (IS_VF(p_hwfn->p_dev))
5297                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5298                                                 tx_coal, p_cid);
5299
5300         p_ptt = ecore_ptt_acquire(p_hwfn);
5301         if (!p_ptt)
5302                 return ECORE_AGAIN;
5303
5304         if (rx_coal) {
5305                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5306                 if (rc)
5307                         goto out;
5308                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5309         }
5310
5311         if (tx_coal) {
5312                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5313                 if (rc)
5314                         goto out;
5315                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5316         }
5317 out:
5318         ecore_ptt_release(p_hwfn, p_ptt);
5319
5320         return rc;
5321 }
5322
5323 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5324                                             struct ecore_ptt *p_ptt,
5325                                             u16 coalesce,
5326                                             struct ecore_queue_cid *p_cid)
5327 {
5328         struct ustorm_eth_queue_zone eth_qzone;
5329         u8 timeset, timer_res;
5330         u32 address;
5331         enum _ecore_status_t rc;
5332
5333         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5334         if (coalesce <= 0x7F) {
5335                 timer_res = 0;
5336         } else if (coalesce <= 0xFF) {
5337                 timer_res = 1;
5338         } else if (coalesce <= 0x1FF) {
5339                 timer_res = 2;
5340         } else {
5341                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5342                 return ECORE_INVAL;
5343         }
5344         timeset = (u8)(coalesce >> timer_res);
5345
5346         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5347                                      p_cid->sb_igu_id, false);
5348         if (rc != ECORE_SUCCESS)
5349                 goto out;
5350
5351         address = BAR0_MAP_REG_USDM_RAM +
5352                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5353
5354         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5355                                 sizeof(struct ustorm_eth_queue_zone), timeset);
5356         if (rc != ECORE_SUCCESS)
5357                 goto out;
5358
5359 out:
5360         return rc;
5361 }
5362
5363 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5364                                             struct ecore_ptt *p_ptt,
5365                                             u16 coalesce,
5366                                             struct ecore_queue_cid *p_cid)
5367 {
5368         struct xstorm_eth_queue_zone eth_qzone;
5369         u8 timeset, timer_res;
5370         u32 address;
5371         enum _ecore_status_t rc;
5372
5373         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5374         if (coalesce <= 0x7F) {
5375                 timer_res = 0;
5376         } else if (coalesce <= 0xFF) {
5377                 timer_res = 1;
5378         } else if (coalesce <= 0x1FF) {
5379                 timer_res = 2;
5380         } else {
5381                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5382                 return ECORE_INVAL;
5383         }
5384
5385         timeset = (u8)(coalesce >> timer_res);
5386
5387         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5388                                      p_cid->sb_igu_id, true);
5389         if (rc != ECORE_SUCCESS)
5390                 goto out;
5391
5392         address = BAR0_MAP_REG_XSDM_RAM +
5393                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5394
5395         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5396                                 sizeof(struct xstorm_eth_queue_zone), timeset);
5397 out:
5398         return rc;
5399 }
5400
5401 /* Calculate final WFQ values for all vports and configure it.
5402  * After this configuration each vport must have
5403  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5404  */
5405 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5406                                                struct ecore_ptt *p_ptt,
5407                                                u32 min_pf_rate)
5408 {
5409         struct init_qm_vport_params *vport_params;
5410         int i;
5411
5412         vport_params = p_hwfn->qm_info.qm_vport_params;
5413
5414         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5415                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5416
5417                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5418                     min_pf_rate;
5419                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5420                                      vport_params[i].first_tx_pq_id,
5421                                      vport_params[i].vport_wfq);
5422         }
5423 }
5424
5425 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5426 {
5427         int i;
5428
5429         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5430                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5431 }
5432
5433 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5434                                              struct ecore_ptt *p_ptt)
5435 {
5436         struct init_qm_vport_params *vport_params;
5437         int i;
5438
5439         vport_params = p_hwfn->qm_info.qm_vport_params;
5440
5441         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5442                 ecore_init_wfq_default_param(p_hwfn);
5443                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5444                                      vport_params[i].first_tx_pq_id,
5445                                      vport_params[i].vport_wfq);
5446         }
5447 }
5448
5449 /* This function performs several validations for WFQ
5450  * configuration and required min rate for a given vport
5451  * 1. req_rate must be greater than one percent of min_pf_rate.
5452  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5453  *    rates to get less than one percent of min_pf_rate.
5454  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5455  */
5456 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5457                                                  u16 vport_id, u32 req_rate,
5458                                                  u32 min_pf_rate)
5459 {
5460         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5461         int non_requested_count = 0, req_count = 0, i, num_vports;
5462
5463         num_vports = p_hwfn->qm_info.num_vports;
5464
5465 /* Accounting for the vports which are configured for WFQ explicitly */
5466
5467         for (i = 0; i < num_vports; i++) {
5468                 u32 tmp_speed;
5469
5470                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5471                         req_count++;
5472                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5473                         total_req_min_rate += tmp_speed;
5474                 }
5475         }
5476
5477         /* Include current vport data as well */
5478         req_count++;
5479         total_req_min_rate += req_rate;
5480         non_requested_count = num_vports - req_count;
5481
5482         /* validate possible error cases */
5483         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5484                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5485                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5486                            vport_id, req_rate, min_pf_rate);
5487                 return ECORE_INVAL;
5488         }
5489
5490         /* TBD - for number of vports greater than 100 */
5491         if (num_vports > ECORE_WFQ_UNIT) {
5492                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5493                            "Number of vports is greater than %d\n",
5494                            ECORE_WFQ_UNIT);
5495                 return ECORE_INVAL;
5496         }
5497
5498         if (total_req_min_rate > min_pf_rate) {
5499                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5500                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5501                            total_req_min_rate, min_pf_rate);
5502                 return ECORE_INVAL;
5503         }
5504
5505         /* Data left for non requested vports */
5506         total_left_rate = min_pf_rate - total_req_min_rate;
5507         left_rate_per_vp = total_left_rate / non_requested_count;
5508
5509         /* validate if non requested get < 1% of min bw */
5510         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5511                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5512                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5513                            left_rate_per_vp, min_pf_rate);
5514                 return ECORE_INVAL;
5515         }
5516
5517         /* now req_rate for given vport passes all scenarios.
5518          * assign final wfq rates to all vports.
5519          */
5520         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5521         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5522
5523         for (i = 0; i < num_vports; i++) {
5524                 if (p_hwfn->qm_info.wfq_data[i].configured)
5525                         continue;
5526
5527                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5528         }
5529
5530         return ECORE_SUCCESS;
5531 }
5532
5533 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5534                                        struct ecore_ptt *p_ptt,
5535                                        u16 vp_id, u32 rate)
5536 {
5537         struct ecore_mcp_link_state *p_link;
5538         int rc = ECORE_SUCCESS;
5539
5540         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5541
5542         if (!p_link->min_pf_rate) {
5543                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5544                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5545                 return rc;
5546         }
5547
5548         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5549
5550         if (rc == ECORE_SUCCESS)
5551                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5552                                                    p_link->min_pf_rate);
5553         else
5554                 DP_NOTICE(p_hwfn, false,
5555                           "Validation failed while configuring min rate\n");
5556
5557         return rc;
5558 }
5559
5560 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5561                                                    struct ecore_ptt *p_ptt,
5562                                                    u32 min_pf_rate)
5563 {
5564         bool use_wfq = false;
5565         int rc = ECORE_SUCCESS;
5566         u16 i;
5567
5568         /* Validate all pre configured vports for wfq */
5569         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5570                 u32 rate;
5571
5572                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5573                         continue;
5574
5575                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5576                 use_wfq = true;
5577
5578                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5579                 if (rc != ECORE_SUCCESS) {
5580                         DP_NOTICE(p_hwfn, false,
5581                                   "WFQ validation failed while configuring min rate\n");
5582                         break;
5583                 }
5584         }
5585
5586         if (rc == ECORE_SUCCESS && use_wfq)
5587                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5588         else
5589                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5590
5591         return rc;
5592 }
5593
5594 /* Main API for ecore clients to configure vport min rate.
5595  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5596  * rate - Speed in Mbps needs to be assigned to a given vport.
5597  */
5598 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5599 {
5600         int i, rc = ECORE_INVAL;
5601
5602         /* TBD - for multiple hardware functions - that is 100 gig */
5603         if (ECORE_IS_CMT(p_dev)) {
5604                 DP_NOTICE(p_dev, false,
5605                           "WFQ configuration is not supported for this device\n");
5606                 return rc;
5607         }
5608
5609         for_each_hwfn(p_dev, i) {
5610                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5611                 struct ecore_ptt *p_ptt;
5612
5613                 p_ptt = ecore_ptt_acquire(p_hwfn);
5614                 if (!p_ptt)
5615                         return ECORE_TIMEOUT;
5616
5617                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5618
5619                 if (rc != ECORE_SUCCESS) {
5620                         ecore_ptt_release(p_hwfn, p_ptt);
5621                         return rc;
5622                 }
5623
5624                 ecore_ptt_release(p_hwfn, p_ptt);
5625         }
5626
5627         return rc;
5628 }
5629
5630 /* API to configure WFQ from mcp link change */
5631 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5632                                            struct ecore_ptt *p_ptt,
5633                                            u32 min_pf_rate)
5634 {
5635         int i;
5636
5637         /* TBD - for multiple hardware functions - that is 100 gig */
5638         if (ECORE_IS_CMT(p_dev)) {
5639                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5640                            "WFQ configuration is not supported for this device\n");
5641                 return;
5642         }
5643
5644         for_each_hwfn(p_dev, i) {
5645                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5646
5647                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5648                                                         min_pf_rate);
5649         }
5650 }
5651
5652 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5653                                        struct ecore_ptt *p_ptt,
5654                                        struct ecore_mcp_link_state *p_link,
5655                                        u8 max_bw)
5656 {
5657         int rc = ECORE_SUCCESS;
5658
5659         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5660
5661         if (!p_link->line_speed && (max_bw != 100))
5662                 return rc;
5663
5664         p_link->speed = (p_link->line_speed * max_bw) / 100;
5665         p_hwfn->qm_info.pf_rl = p_link->speed;
5666
5667         /* Since the limiter also affects Tx-switched traffic, we don't want it
5668          * to limit such traffic in case there's no actual limit.
5669          * In that case, set limit to imaginary high boundary.
5670          */
5671         if (max_bw == 100)
5672                 p_hwfn->qm_info.pf_rl = 100000;
5673
5674         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5675                               p_hwfn->qm_info.pf_rl);
5676
5677         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5678                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5679                    p_link->speed);
5680
5681         return rc;
5682 }
5683
5684 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5685 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5686 {
5687         int i, rc = ECORE_INVAL;
5688
5689         if (max_bw < 1 || max_bw > 100) {
5690                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5691                 return rc;
5692         }
5693
5694         for_each_hwfn(p_dev, i) {
5695                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5696                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5697                 struct ecore_mcp_link_state *p_link;
5698                 struct ecore_ptt *p_ptt;
5699
5700                 p_link = &p_lead->mcp_info->link_output;
5701
5702                 p_ptt = ecore_ptt_acquire(p_hwfn);
5703                 if (!p_ptt)
5704                         return ECORE_TIMEOUT;
5705
5706                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5707                                                         p_link, max_bw);
5708
5709                 ecore_ptt_release(p_hwfn, p_ptt);
5710
5711                 if (rc != ECORE_SUCCESS)
5712                         break;
5713         }
5714
5715         return rc;
5716 }
5717
5718 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5719                                        struct ecore_ptt *p_ptt,
5720                                        struct ecore_mcp_link_state *p_link,
5721                                        u8 min_bw)
5722 {
5723         int rc = ECORE_SUCCESS;
5724
5725         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5726         p_hwfn->qm_info.pf_wfq = min_bw;
5727
5728         if (!p_link->line_speed)
5729                 return rc;
5730
5731         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5732
5733         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5734
5735         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5736                    "Configured MIN bandwidth to be %d Mb/sec\n",
5737                    p_link->min_pf_rate);
5738
5739         return rc;
5740 }
5741
5742 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5743 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5744 {
5745         int i, rc = ECORE_INVAL;
5746
5747         if (min_bw < 1 || min_bw > 100) {
5748                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5749                 return rc;
5750         }
5751
5752         for_each_hwfn(p_dev, i) {
5753                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5754                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5755                 struct ecore_mcp_link_state *p_link;
5756                 struct ecore_ptt *p_ptt;
5757
5758                 p_link = &p_lead->mcp_info->link_output;
5759
5760                 p_ptt = ecore_ptt_acquire(p_hwfn);
5761                 if (!p_ptt)
5762                         return ECORE_TIMEOUT;
5763
5764                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5765                                                         p_link, min_bw);
5766                 if (rc != ECORE_SUCCESS) {
5767                         ecore_ptt_release(p_hwfn, p_ptt);
5768                         return rc;
5769                 }
5770
5771                 if (p_link->min_pf_rate) {
5772                         u32 min_rate = p_link->min_pf_rate;
5773
5774                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5775                                                                      p_ptt,
5776                                                                      min_rate);
5777                 }
5778
5779                 ecore_ptt_release(p_hwfn, p_ptt);
5780         }
5781
5782         return rc;
5783 }
5784
5785 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5786 {
5787         struct ecore_mcp_link_state *p_link;
5788
5789         p_link = &p_hwfn->mcp_info->link_output;
5790
5791         if (p_link->min_pf_rate)
5792                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5793
5794         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5795                     sizeof(*p_hwfn->qm_info.wfq_data) *
5796                     p_hwfn->qm_info.num_vports);
5797 }
5798
5799 int ecore_device_num_engines(struct ecore_dev *p_dev)
5800 {
5801         return ECORE_IS_BB(p_dev) ? 2 : 1;
5802 }
5803
5804 int ecore_device_num_ports(struct ecore_dev *p_dev)
5805 {
5806         return p_dev->num_ports;
5807 }
5808
5809 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5810                           __le16 *fw_mid,
5811                           __le16 *fw_lsb,
5812                           u8 *mac)
5813 {
5814         ((u8 *)fw_msb)[0] = mac[1];
5815         ((u8 *)fw_msb)[1] = mac[0];
5816         ((u8 *)fw_mid)[0] = mac[3];
5817         ((u8 *)fw_mid)[1] = mac[2];
5818         ((u8 *)fw_lsb)[0] = mac[5];
5819         ((u8 *)fw_lsb)[1] = mac[4];
5820 }
5821
5822 bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
5823 {
5824         return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
5825 }