drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /* Configurable */
  46 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  47                                          * load the driver. The number was
  48                                          * arbitrarily set.
  49                                          */
  50
  51 /* Derived */
  52 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  53
  54 enum BAR_ID {
  55         BAR_ID_0,               /* used for GRC */
  56         BAR_ID_1                /* Used for doorbells */
  57 };
  58
  59 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  60 {
  61         u32 bar_reg = (bar_id == BAR_ID_0 ?
  62                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  63         u32 val;
  64
  65         if (IS_VF(p_hwfn->p_dev)) {
  66                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  67                  * read from actual register, but we're currently not using
  68                  * it for actual doorbelling.
  69                  */
  70                 return 1 << 17;
  71         }
  72
  73         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  74         if (val)
  75                 return 1 << (val + 15);
  76
  77         /* The above registers were updated in the past only in CMT mode. Since
  78          * they were found to be useful MFW started updating them from 8.7.7.0.
  79          * In older MFW versions they are set to 0 which means disabled.
  80          */
  81         if (p_hwfn->p_dev->num_hwfns > 1) {
  82                 DP_NOTICE(p_hwfn, false,
  83                           "BAR size not configured. Assuming BAR size of 256kB"
  84                           " for GRC and 512kB for DB\n");
  85                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  86         } else {
  87                 DP_NOTICE(p_hwfn, false,
  88                           "BAR size not configured. Assuming BAR size of 512kB"
  89                           " for GRC and 512kB for DB\n");
  90                 val = 512 * 1024;
  91         }
  92
  93         return val;
  94 }
  95
  96 void ecore_init_dp(struct ecore_dev *p_dev,
  97                    u32 dp_module, u8 dp_level, void *dp_ctx)
  98 {
  99         u32 i;
 100
 101         p_dev->dp_level = dp_level;
 102         p_dev->dp_module = dp_module;
 103         p_dev->dp_ctx = dp_ctx;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109                 p_hwfn->dp_ctx = dp_ctx;
 110         }
 111 }
 112
 113 void ecore_init_struct(struct ecore_dev *p_dev)
 114 {
 115         u8 i;
 116
 117         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 118                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 119
 120                 p_hwfn->p_dev = p_dev;
 121                 p_hwfn->my_id = i;
 122                 p_hwfn->b_active = false;
 123
 124                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 125                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 126         }
 127
 128         /* hwfn 0 is always active */
 129         p_dev->hwfns[0].b_active = true;
 130
 131         /* set the default cache alignment to 128 (may be overridden later) */
 132         p_dev->cache_shift = 7;
 133 }
 134
 135 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 136 {
 137         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 138
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 142         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 143 }
 144
 145 void ecore_resc_free(struct ecore_dev *p_dev)
 146 {
 147         int i;
 148
 149         if (IS_VF(p_dev))
 150                 return;
 151
 152         OSAL_FREE(p_dev, p_dev->fw_data);
 153
 154         OSAL_FREE(p_dev, p_dev->reset_stats);
 155
 156         for_each_hwfn(p_dev, i) {
 157                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 158
 159                 ecore_cxt_mngr_free(p_hwfn);
 160                 ecore_qm_info_free(p_hwfn);
 161                 ecore_spq_free(p_hwfn);
 162                 ecore_eq_free(p_hwfn);
 163                 ecore_consq_free(p_hwfn);
 164                 ecore_int_free(p_hwfn);
 165                 ecore_iov_free(p_hwfn);
 166                 ecore_dmae_info_free(p_hwfn);
 167                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 168                 /* @@@TBD Flush work-queue ? */
 169         }
 170 }
 171
 172 /******************** QM initialization *******************/
 173
 174 /* bitmaps for indicating active traffic classes.
 175  * Special case for Arrowhead 4 port
 176  */
 177 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 178 #define ACTIVE_TCS_BMAP 0x9f
 179 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 180 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 181
 182 /* determines the physical queue flags for a given PF. */
 183 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 184 {
 185         u32 flags;
 186
 187         /* common flags */
 188         flags = PQ_FLAGS_LB;
 189
 190         /* feature flags */
 191         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 192                 flags |= PQ_FLAGS_VFS;
 193
 194         /* protocol flags */
 195         switch (p_hwfn->hw_info.personality) {
 196         case ECORE_PCI_ETH:
 197                 flags |= PQ_FLAGS_MCOS;
 198                 break;
 199         case ECORE_PCI_FCOE:
 200                 flags |= PQ_FLAGS_OFLD;
 201                 break;
 202         case ECORE_PCI_ISCSI:
 203                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 204                 break;
 205         case ECORE_PCI_ETH_ROCE:
 206                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 207                 break;
 208         case ECORE_PCI_ETH_IWARP:
 209                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 210                          PQ_FLAGS_OFLD;
 211                 break;
 212         default:
 213                 DP_ERR(p_hwfn, "unknown personality %d\n",
 214                        p_hwfn->hw_info.personality);
 215                 return 0;
 216         }
 217         return flags;
 218 }
 219
 220 /* Getters for resource amounts necessary for qm initialization */
 221 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 222 {
 223         return p_hwfn->hw_info.num_hw_tc;
 224 }
 225
 226 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 227 {
 228         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 229                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 230 }
 231
 232 #define NUM_DEFAULT_RLS 1
 233
 234 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 235 {
 236         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 237
 238         /* @DPDK */
 239         /* num RLs can't exceed resource amount of rls or vports or the
 240          * dcqcn qps
 241          */
 242         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 243                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 244
 245         /* make sure after we reserve the default and VF rls we'll have
 246          * something left
 247          */
 248         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 249                 DP_NOTICE(p_hwfn, false,
 250                           "no rate limiters left for PF rate limiting"
 251                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 252                 return 0;
 253         }
 254
 255         /* subtract rls necessary for VFs and one default one for the PF */
 256         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 257
 258         return num_pf_rls;
 259 }
 260
 261 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 262 {
 263         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 264
 265         /* all pqs share the same vport (hence the 1 below), except for vfs
 266          * and pf_rl pqs
 267          */
 268         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 269                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 270                (!!(PQ_FLAGS_VFS & pq_flags)) *
 271                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 272 }
 273
 274 /* calc amount of PQs according to the requested flags */
 275 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 276 {
 277         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 278
 279         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 280                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 281                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 282                 ecore_init_qm_get_num_tcs(p_hwfn) +
 283                (!!(PQ_FLAGS_LB & pq_flags)) +
 284                (!!(PQ_FLAGS_OOO & pq_flags)) +
 285                (!!(PQ_FLAGS_ACK & pq_flags)) +
 286                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 287                (!!(PQ_FLAGS_VFS & pq_flags)) *
 288                 ecore_init_qm_get_num_vfs(p_hwfn);
 289 }
 290
 291 /* initialize the top level QM params */
 292 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 293 {
 294         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 295         bool four_port;
 296
 297         /* pq and vport bases for this PF */
 298         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 299         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 300
 301         /* rate limiting and weighted fair queueing are always enabled */
 302         qm_info->vport_rl_en = 1;
 303         qm_info->vport_wfq_en = 1;
 304
 305         /* TC config is different for AH 4 port */
 306         four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
 307
 308         /* in AH 4 port we have fewer TCs per port */
 309         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 310                                                      NUM_OF_PHYS_TCS;
 311
 312         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 313          * 4 otherwise
 314          */
 315         if (!qm_info->ooo_tc)
 316                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 317                                               DCBX_TCP_OOO_TC;
 318 }
 319
 320 /* initialize qm vport params */
 321 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 322 {
 323         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 324         u8 i;
 325
 326         /* all vports participate in weighted fair queueing */
 327         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 328                 qm_info->qm_vport_params[i].vport_wfq = 1;
 329 }
 330
 331 /* initialize qm port params */
 332 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 333 {
 334         /* Initialize qm port parameters */
 335         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
 336
 337         /* indicate how ooo and high pri traffic is dealt with */
 338         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 339                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 340
 341         for (i = 0; i < num_ports; i++) {
 342                 struct init_qm_port_params *p_qm_port =
 343                         &p_hwfn->qm_info.qm_port_params[i];
 344
 345                 p_qm_port->active = 1;
 346                 p_qm_port->active_phys_tcs = active_phys_tcs;
 347                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 348                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 349         }
 350 }
 351
 352 /* Reset the params which must be reset for qm init. QM init may be called as
 353  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 354  * params may be affected by the init but would simply recalculate to the same
 355  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 356  * affected as these amounts stay the same.
 357  */
 358 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 359 {
 360         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 361
 362         qm_info->num_pqs = 0;
 363         qm_info->num_vports = 0;
 364         qm_info->num_pf_rls = 0;
 365         qm_info->num_vf_pqs = 0;
 366         qm_info->first_vf_pq = 0;
 367         qm_info->first_mcos_pq = 0;
 368         qm_info->first_rl_pq = 0;
 369 }
 370
 371 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 372 {
 373         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 374
 375         qm_info->num_vports++;
 376
 377         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 378                 DP_ERR(p_hwfn,
 379                        "vport overflow! qm_info->num_vports %d,"
 380                        " qm_init_get_num_vports() %d\n",
 381                        qm_info->num_vports,
 382                        ecore_init_qm_get_num_vports(p_hwfn));
 383 }
 384
 385 /* initialize a single pq and manage qm_info resources accounting.
 386  * The pq_init_flags param determines whether the PQ is rate limited
 387  * (for VF or PF)
 388  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 389  * shared)
 390  */
 391
 392 /* flags for pq init */
 393 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 394 #define PQ_INIT_PF_RL           (1 << 1)
 395 #define PQ_INIT_VF_RL           (1 << 2)
 396
 397 /* defines for pq init */
 398 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 399 #define PQ_INIT_DEFAULT_TC              0
 400 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 401
 402 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 403                              struct ecore_qm_info *qm_info,
 404                              u8 tc, u32 pq_init_flags)
 405 {
 406         u16 pq_idx = qm_info->num_pqs, max_pq =
 407                                         ecore_init_qm_get_num_pqs(p_hwfn);
 408
 409         if (pq_idx > max_pq)
 410                 DP_ERR(p_hwfn,
 411                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 412
 413         /* init pq params */
 414         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 415                                                  qm_info->num_vports;
 416         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 417         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 418         qm_info->qm_pq_params[pq_idx].rl_valid =
 419                 (pq_init_flags & PQ_INIT_PF_RL ||
 420                  pq_init_flags & PQ_INIT_VF_RL);
 421
 422         /* qm params accounting */
 423         qm_info->num_pqs++;
 424         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 425                 qm_info->num_vports++;
 426
 427         if (pq_init_flags & PQ_INIT_PF_RL)
 428                 qm_info->num_pf_rls++;
 429
 430         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 431                 DP_ERR(p_hwfn,
 432                        "vport overflow! qm_info->num_vports %d,"
 433                        " qm_init_get_num_vports() %d\n",
 434                        qm_info->num_vports,
 435                        ecore_init_qm_get_num_vports(p_hwfn));
 436
 437         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 438                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 439                        " qm_init_get_num_pf_rls() %d\n",
 440                        qm_info->num_pf_rls,
 441                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 442 }
 443
 444 /* get pq index according to PQ_FLAGS */
 445 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 446                                              u32 pq_flags)
 447 {
 448         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 449
 450         /* Can't have multiple flags set here */
 451         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 452                                 sizeof(pq_flags)) > 1)
 453                 goto err;
 454
 455         switch (pq_flags) {
 456         case PQ_FLAGS_RLS:
 457                 return &qm_info->first_rl_pq;
 458         case PQ_FLAGS_MCOS:
 459                 return &qm_info->first_mcos_pq;
 460         case PQ_FLAGS_LB:
 461                 return &qm_info->pure_lb_pq;
 462         case PQ_FLAGS_OOO:
 463                 return &qm_info->ooo_pq;
 464         case PQ_FLAGS_ACK:
 465                 return &qm_info->pure_ack_pq;
 466         case PQ_FLAGS_OFLD:
 467                 return &qm_info->offload_pq;
 468         case PQ_FLAGS_VFS:
 469                 return &qm_info->first_vf_pq;
 470         default:
 471                 goto err;
 472         }
 473
 474 err:
 475         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 476         return OSAL_NULL;
 477 }
 478
 479 /* save pq index in qm info */
 480 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 481                                   u32 pq_flags, u16 pq_val)
 482 {
 483         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 484
 485         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 486 }
 487
 488 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 489 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 490 {
 491         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 492
 493         return *base_pq_idx + CM_TX_PQ_BASE;
 494 }
 495
 496 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 497 {
 498         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 499
 500         if (tc > max_tc)
 501                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 502
 503         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 504 }
 505
 506 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 507 {
 508         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 509
 510         if (vf > max_vf)
 511                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 512
 513         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 514 }
 515
 516 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 517 {
 518         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 519
 520         if (rl > max_rl)
 521                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 522
 523         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 524 }
 525
 526 /* Functions for creating specific types of pqs */
 527 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 528 {
 529         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 530
 531         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 532                 return;
 533
 534         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 535         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 536 }
 537
 538 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 539 {
 540         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 541
 542         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 543                 return;
 544
 545         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 546         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 547 }
 548
 549 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 550 {
 551         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 552
 553         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 554                 return;
 555
 556         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 557         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 558 }
 559
 560 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 561 {
 562         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 563
 564         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 565                 return;
 566
 567         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 568         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 569 }
 570
 571 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 572 {
 573         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 574         u8 tc_idx;
 575
 576         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 577                 return;
 578
 579         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 580         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 581                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 582 }
 583
 584 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 585 {
 586         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 587         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 588
 589         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 590                 return;
 591
 592         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 593
 594         qm_info->num_vf_pqs = num_vfs;
 595         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 596                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 597                                  PQ_INIT_VF_RL);
 598 }
 599
 600 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 601 {
 602         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 603         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 604
 605         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 606                 return;
 607
 608         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 609         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 610                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 611                                  PQ_INIT_PF_RL);
 612 }
 613
 614 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 615 {
 616         /* rate limited pqs, must come first (FW assumption) */
 617         ecore_init_qm_rl_pqs(p_hwfn);
 618
 619         /* pqs for multi cos */
 620         ecore_init_qm_mcos_pqs(p_hwfn);
 621
 622         /* pure loopback pq */
 623         ecore_init_qm_lb_pq(p_hwfn);
 624
 625         /* out of order pq */
 626         ecore_init_qm_ooo_pq(p_hwfn);
 627
 628         /* pure ack pq */
 629         ecore_init_qm_pure_ack_pq(p_hwfn);
 630
 631         /* pq for offloaded protocol */
 632         ecore_init_qm_offload_pq(p_hwfn);
 633
 634         /* done sharing vports */
 635         ecore_init_qm_advance_vport(p_hwfn);
 636
 637         /* pqs for vfs */
 638         ecore_init_qm_vf_pqs(p_hwfn);
 639 }
 640
 641 /* compare values of getters against resources amounts */
 642 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 643 {
 644         if (ecore_init_qm_get_num_vports(p_hwfn) >
 645             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 646                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 647                 return ECORE_INVAL;
 648         }
 649
 650         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 651                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 652                 return ECORE_INVAL;
 653         }
 654
 655         return ECORE_SUCCESS;
 656 }
 657
 658 /*
 659  * Function for verbose printing of the qm initialization results
 660  */
 661 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 662 {
 663         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 664         struct init_qm_vport_params *vport;
 665         struct init_qm_port_params *port;
 666         struct init_qm_pq_params *pq;
 667         int i, tc;
 668
 669         /* top level params */
 670         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 671                    "qm init top level params: start_pq %d, start_vport %d,"
 672                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 673                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 674                    qm_info->offload_pq, qm_info->pure_ack_pq);
 675         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 676                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 677                    " num_vports %d, max_phys_tcs_per_port %d\n",
 678                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 679                    qm_info->num_vf_pqs, qm_info->num_vports,
 680                    qm_info->max_phys_tcs_per_port);
 681         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 682                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 683                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 684                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 685                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 686                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 687
 688         /* port table */
 689         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
 690                 port = &qm_info->qm_port_params[i];
 691                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 692                            "port idx %d, active %d, active_phys_tcs %d,"
 693                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
 694                            " reserved %d\n",
 695                            i, port->active, port->active_phys_tcs,
 696                            port->num_pbf_cmd_lines, port->num_btb_blocks,
 697                            port->reserved);
 698         }
 699
 700         /* vport table */
 701         for (i = 0; i < qm_info->num_vports; i++) {
 702                 vport = &qm_info->qm_vport_params[i];
 703                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 704                            "vport idx %d, vport_rl %d, wfq %d,"
 705                            " first_tx_pq_id [ ",
 706                            qm_info->start_vport + i, vport->vport_rl,
 707                            vport->vport_wfq);
 708                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 709                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
 710                                    vport->first_tx_pq_id[tc]);
 711                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
 712         }
 713
 714         /* pq table */
 715         for (i = 0; i < qm_info->num_pqs; i++) {
 716                 pq = &qm_info->qm_pq_params[i];
 717                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 718                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
 719                            " rl_valid %d\n",
 720                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
 721                            pq->wrr_group, pq->rl_valid);
 722         }
 723 }
 724
 725 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
 726 {
 727         /* reset params required for init run */
 728         ecore_init_qm_reset_params(p_hwfn);
 729
 730         /* init QM top level params */
 731         ecore_init_qm_params(p_hwfn);
 732
 733         /* init QM port params */
 734         ecore_init_qm_port_params(p_hwfn);
 735
 736         /* init QM vport params */
 737         ecore_init_qm_vport_params(p_hwfn);
 738
 739         /* init QM physical queue params */
 740         ecore_init_qm_pq_params(p_hwfn);
 741
 742         /* display all that init */
 743         ecore_dp_init_qm_params(p_hwfn);
 744 }
 745
 746 /* This function reconfigures the QM pf on the fly.
 747  * For this purpose we:
 748  * 1. reconfigure the QM database
 749  * 2. set new values to runtime array
 750  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 751  * 4. activate init tool in QM_PF stage
 752  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 753  */
 754 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 755                                      struct ecore_ptt *p_ptt)
 756 {
 757         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 758         enum _ecore_status_t rc;
 759         bool b_rc;
 760
 761         /* initialize ecore's qm data structure */
 762         ecore_init_qm_info(p_hwfn);
 763
 764         /* stop PF's qm queues */
 765         OSAL_SPIN_LOCK(&qm_lock);
 766         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 767                                       qm_info->start_pq, qm_info->num_pqs);
 768         OSAL_SPIN_UNLOCK(&qm_lock);
 769         if (!b_rc)
 770                 return ECORE_INVAL;
 771
 772         /* clear the QM_PF runtime phase leftovers from previous init */
 773         ecore_init_clear_rt_data(p_hwfn);
 774
 775         /* prepare QM portion of runtime array */
 776         ecore_qm_init_pf(p_hwfn);
 777
 778         /* activate init tool on runtime array */
 779         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 780                             p_hwfn->hw_info.hw_mode);
 781         if (rc != ECORE_SUCCESS)
 782                 return rc;
 783
 784         /* start PF's qm queues */
 785         OSAL_SPIN_LOCK(&qm_lock);
 786         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 787                                       qm_info->start_pq, qm_info->num_pqs);
 788         OSAL_SPIN_UNLOCK(&qm_lock);
 789         if (!b_rc)
 790                 return ECORE_INVAL;
 791
 792         return ECORE_SUCCESS;
 793 }
 794
 795 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
 796 {
 797         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 798         enum _ecore_status_t rc;
 799
 800         rc = ecore_init_qm_sanity(p_hwfn);
 801         if (rc != ECORE_SUCCESS)
 802                 goto alloc_err;
 803
 804         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 805                                             sizeof(struct init_qm_pq_params) *
 806                                             ecore_init_qm_get_num_pqs(p_hwfn));
 807         if (!qm_info->qm_pq_params)
 808                 goto alloc_err;
 809
 810         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 811                                        sizeof(struct init_qm_vport_params) *
 812                                        ecore_init_qm_get_num_vports(p_hwfn));
 813         if (!qm_info->qm_vport_params)
 814                 goto alloc_err;
 815
 816         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 817                                       sizeof(struct init_qm_port_params) *
 818                                       p_hwfn->p_dev->num_ports_in_engines);
 819         if (!qm_info->qm_port_params)
 820                 goto alloc_err;
 821
 822         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 823                                         sizeof(struct ecore_wfq_data) *
 824                                         ecore_init_qm_get_num_vports(p_hwfn));
 825         if (!qm_info->wfq_data)
 826                 goto alloc_err;
 827
 828         return ECORE_SUCCESS;
 829
 830 alloc_err:
 831         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 832         ecore_qm_info_free(p_hwfn);
 833         return ECORE_NOMEM;
 834 }
 835 /******************** End QM initialization ***************/
 836
 837 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 838 {
 839         enum _ecore_status_t rc = ECORE_SUCCESS;
 840         int i;
 841
 842         if (IS_VF(p_dev))
 843                 return rc;
 844
 845         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 846                                      sizeof(*p_dev->fw_data));
 847         if (!p_dev->fw_data)
 848                 return ECORE_NOMEM;
 849
 850         for_each_hwfn(p_dev, i) {
 851                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 852                 u32 n_eqes, num_cons;
 853
 854                 /* First allocate the context manager structure */
 855                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 856                 if (rc)
 857                         goto alloc_err;
 858
 859                 /* Set the HW cid/tid numbers (in the contest manager)
 860                  * Must be done prior to any further computations.
 861                  */
 862                 rc = ecore_cxt_set_pf_params(p_hwfn);
 863                 if (rc)
 864                         goto alloc_err;
 865
 866                 rc = ecore_alloc_qm_data(p_hwfn);
 867                 if (rc)
 868                         goto alloc_err;
 869
 870                 /* init qm info */
 871                 ecore_init_qm_info(p_hwfn);
 872
 873                 /* Compute the ILT client partition */
 874                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 875                 if (rc)
 876                         goto alloc_err;
 877
 878                 /* CID map / ILT shadow table / T2
 879                  * The talbes sizes are determined by the computations above
 880                  */
 881                 rc = ecore_cxt_tables_alloc(p_hwfn);
 882                 if (rc)
 883                         goto alloc_err;
 884
 885                 /* SPQ, must follow ILT because initializes SPQ context */
 886                 rc = ecore_spq_alloc(p_hwfn);
 887                 if (rc)
 888                         goto alloc_err;
 889
 890                 /* SP status block allocation */
 891                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 892                                                            RESERVED_PTT_DPC);
 893
 894                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 895                 if (rc)
 896                         goto alloc_err;
 897
 898                 rc = ecore_iov_alloc(p_hwfn);
 899                 if (rc)
 900                         goto alloc_err;
 901
 902                 /* EQ */
 903                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 904                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 905                         /* Calculate the EQ size
 906                          * ---------------------
 907                          * Each ICID may generate up to one event at a time i.e.
 908                          * the event must be handled/cleared before a new one
 909                          * can be generated. We calculate the sum of events per
 910                          * protocol and create an EQ deep enough to handle the
 911                          * worst case:
 912                          * - Core - according to SPQ.
 913                          * - RoCE - per QP there are a couple of ICIDs, one
 914                          *        responder and one requester, each can
 915                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
 916                          *        Each CQ can generate an EQE. There are 2 CQs
 917                          *        per QP => n_eqes_cq = 2 * n_qp.
 918                          *        Hence the RoCE total is 4 * n_qp or
 919                          *        2 * num_cons.
 920                          * - ENet - There can be up to two events per VF. One
 921                          *        for VF-PF channel and another for VF FLR
 922                          *        initial cleanup. The number of VFs is
 923                          *        bounded by MAX_NUM_VFS_BB, and is much
 924                          *        smaller than RoCE's so we avoid exact
 925                          *        calculation.
 926                          */
 927                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 928                                 num_cons =
 929                                     ecore_cxt_get_proto_cid_count(
 930                                                 p_hwfn,
 931                                                 PROTOCOLID_ROCE,
 932                                                 OSAL_NULL);
 933                                 num_cons *= 2;
 934                         } else {
 935                                 num_cons = ecore_cxt_get_proto_cid_count(
 936                                                 p_hwfn,
 937                                                 PROTOCOLID_IWARP,
 938                                                 OSAL_NULL);
 939                         }
 940                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 941                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 942                         num_cons =
 943                             ecore_cxt_get_proto_cid_count(p_hwfn,
 944                                                           PROTOCOLID_ISCSI,
 945                                                           OSAL_NULL);
 946                         n_eqes += 2 * num_cons;
 947                 }
 948
 949                 if (n_eqes > 0xFFFF) {
 950                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 951                                        "The maximum of a u16 chain is 0x%x\n",
 952                                n_eqes, 0xFFFF);
 953                         goto alloc_no_mem;
 954                 }
 955
 956                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 957                 if (rc)
 958                         goto alloc_err;
 959
 960                 rc = ecore_consq_alloc(p_hwfn);
 961                 if (rc)
 962                         goto alloc_err;
 963
 964                 /* DMA info initialization */
 965                 rc = ecore_dmae_info_alloc(p_hwfn);
 966                 if (rc) {
 967                         DP_NOTICE(p_hwfn, true,
 968                                   "Failed to allocate memory for dmae_info"
 969                                   " structure\n");
 970                         goto alloc_err;
 971                 }
 972
 973                 /* DCBX initialization */
 974                 rc = ecore_dcbx_info_alloc(p_hwfn);
 975                 if (rc) {
 976                         DP_NOTICE(p_hwfn, true,
 977                                   "Failed to allocate memory for dcbx structure\n");
 978                         goto alloc_err;
 979                 }
 980         }
 981
 982         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 983                                          sizeof(*p_dev->reset_stats));
 984         if (!p_dev->reset_stats) {
 985                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 986                 goto alloc_no_mem;
 987         }
 988
 989         return ECORE_SUCCESS;
 990
 991 alloc_no_mem:
 992         rc = ECORE_NOMEM;
 993 alloc_err:
 994         ecore_resc_free(p_dev);
 995         return rc;
 996 }
 997
 998 void ecore_resc_setup(struct ecore_dev *p_dev)
 999 {
1000         int i;
1001
1002         if (IS_VF(p_dev))
1003                 return;
1004
1005         for_each_hwfn(p_dev, i) {
1006                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1007
1008                 ecore_cxt_mngr_setup(p_hwfn);
1009                 ecore_spq_setup(p_hwfn);
1010                 ecore_eq_setup(p_hwfn);
1011                 ecore_consq_setup(p_hwfn);
1012
1013                 /* Read shadow of current MFW mailbox */
1014                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1015                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1016                             p_hwfn->mcp_info->mfw_mb_cur,
1017                             p_hwfn->mcp_info->mfw_mb_length);
1018
1019                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1020
1021                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1022         }
1023 }
1024
1025 #define FINAL_CLEANUP_POLL_CNT  (100)
1026 #define FINAL_CLEANUP_POLL_TIME (10)
1027 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1028                                          struct ecore_ptt *p_ptt,
1029                                          u16 id, bool is_vf)
1030 {
1031         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1032         enum _ecore_status_t rc = ECORE_TIMEOUT;
1033
1034 #ifndef ASIC_ONLY
1035         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1036             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1037                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1038                 return ECORE_SUCCESS;
1039         }
1040 #endif
1041
1042         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1043             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1044
1045         if (is_vf)
1046                 id += 0x10;
1047
1048         command |= X_FINAL_CLEANUP_AGG_INT <<
1049             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1050         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1051         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1052         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1053
1054 /* Make sure notification is not set before initiating final cleanup */
1055
1056         if (REG_RD(p_hwfn, addr)) {
1057                 DP_NOTICE(p_hwfn, false,
1058                           "Unexpected; Found final cleanup notification");
1059                 DP_NOTICE(p_hwfn, false,
1060                           " before initiating final cleanup\n");
1061                 REG_WR(p_hwfn, addr, 0);
1062         }
1063
1064         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1065                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1066                    id, command);
1067
1068         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1069
1070         /* Poll until completion */
1071         while (!REG_RD(p_hwfn, addr) && count--)
1072                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1073
1074         if (REG_RD(p_hwfn, addr))
1075                 rc = ECORE_SUCCESS;
1076         else
1077                 DP_NOTICE(p_hwfn, true,
1078                           "Failed to receive FW final cleanup notification\n");
1079
1080         /* Cleanup afterwards */
1081         REG_WR(p_hwfn, addr, 0);
1082
1083         return rc;
1084 }
1085
1086 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1087 {
1088         int hw_mode = 0;
1089
1090         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1091                 hw_mode |= 1 << MODE_BB;
1092         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1093                 hw_mode |= 1 << MODE_K2;
1094         } else {
1095                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1096                           p_hwfn->p_dev->type);
1097                 return ECORE_INVAL;
1098         }
1099
1100         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1101         switch (p_hwfn->p_dev->num_ports_in_engines) {
1102         case 1:
1103                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1104                 break;
1105         case 2:
1106                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1107                 break;
1108         case 4:
1109                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1110                 break;
1111         default:
1112                 DP_NOTICE(p_hwfn, true,
1113                           "num_ports_in_engine = %d not supported\n",
1114                           p_hwfn->p_dev->num_ports_in_engines);
1115                 return ECORE_INVAL;
1116         }
1117
1118         switch (p_hwfn->p_dev->mf_mode) {
1119         case ECORE_MF_DEFAULT:
1120         case ECORE_MF_NPAR:
1121                 hw_mode |= 1 << MODE_MF_SI;
1122                 break;
1123         case ECORE_MF_OVLAN:
1124                 hw_mode |= 1 << MODE_MF_SD;
1125                 break;
1126         default:
1127                 DP_NOTICE(p_hwfn, true,
1128                           "Unsupported MF mode, init as DEFAULT\n");
1129                 hw_mode |= 1 << MODE_MF_SI;
1130         }
1131
1132 #ifndef ASIC_ONLY
1133         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1134                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1135                         hw_mode |= 1 << MODE_FPGA;
1136                 } else {
1137                         if (p_hwfn->p_dev->b_is_emul_full)
1138                                 hw_mode |= 1 << MODE_EMUL_FULL;
1139                         else
1140                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1141                 }
1142         } else
1143 #endif
1144                 hw_mode |= 1 << MODE_ASIC;
1145
1146         if (p_hwfn->p_dev->num_hwfns > 1)
1147                 hw_mode |= 1 << MODE_100G;
1148
1149         p_hwfn->hw_info.hw_mode = hw_mode;
1150
1151         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1152                    "Configuring function for hw_mode: 0x%08x\n",
1153                    p_hwfn->hw_info.hw_mode);
1154
1155         return ECORE_SUCCESS;
1156 }
1157
1158 #ifndef ASIC_ONLY
1159 /* MFW-replacement initializations for non-ASIC */
1160 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1161                                                struct ecore_ptt *p_ptt)
1162 {
1163         struct ecore_dev *p_dev = p_hwfn->p_dev;
1164         u32 pl_hv = 1;
1165         int i;
1166
1167         if (CHIP_REV_IS_EMUL(p_dev)) {
1168                 if (ECORE_IS_AH(p_dev))
1169                         pl_hv |= 0x600;
1170         }
1171
1172         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1173
1174         if (CHIP_REV_IS_EMUL(p_dev) &&
1175             (ECORE_IS_AH(p_dev)))
1176                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1177                          0x3ffffff);
1178
1179         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1180         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1181         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1182                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1183
1184         if (CHIP_REV_IS_EMUL(p_dev)) {
1185                 if (ECORE_IS_AH(p_dev)) {
1186                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1187                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1188                                  (p_dev->num_ports_in_engines >> 1));
1189
1190                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1191                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
1192                 }
1193         }
1194
1195         /* Poll on RBC */
1196         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1197         for (i = 0; i < 100; i++) {
1198                 OSAL_UDELAY(50);
1199                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1200                         break;
1201         }
1202         if (i == 100)
1203                 DP_NOTICE(p_hwfn, true,
1204                           "RBC done failed to complete in PSWRQ2\n");
1205
1206         return ECORE_SUCCESS;
1207 }
1208 #endif
1209
1210 /* Init run time data for all PFs and their VFs on an engine.
1211  * TBD - for VFs - Once we have parent PF info for each VF in
1212  * shmem available as CAU requires knowledge of parent PF for each VF.
1213  */
1214 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1215 {
1216         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1217         int i, sb_id;
1218
1219         for_each_hwfn(p_dev, i) {
1220                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1221                 struct ecore_igu_info *p_igu_info;
1222                 struct ecore_igu_block *p_block;
1223                 struct cau_sb_entry sb_entry;
1224
1225                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1226
1227                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1228                      sb_id++) {
1229                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1230
1231                         if (!p_block->is_pf)
1232                                 continue;
1233
1234                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1235                                                 p_block->function_id, 0, 0);
1236                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1237                 }
1238         }
1239 }
1240
1241 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1242                                                  struct ecore_ptt *p_ptt,
1243                                                  int hw_mode)
1244 {
1245         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1246         struct ecore_dev *p_dev = p_hwfn->p_dev;
1247         u8 vf_id, max_num_vfs;
1248         u16 num_pfs, pf_id;
1249         u32 concrete_fid;
1250         enum _ecore_status_t rc = ECORE_SUCCESS;
1251
1252         ecore_init_cau_rt_data(p_dev);
1253
1254         /* Program GTT windows */
1255         ecore_gtt_init(p_hwfn);
1256
1257 #ifndef ASIC_ONLY
1258         if (CHIP_REV_IS_EMUL(p_dev)) {
1259                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1260                 if (rc != ECORE_SUCCESS)
1261                         return rc;
1262         }
1263 #endif
1264
1265         if (p_hwfn->mcp_info) {
1266                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1267                         qm_info->pf_rl_en = 1;
1268                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1269                         qm_info->pf_wfq_en = 1;
1270         }
1271
1272         ecore_qm_common_rt_init(p_hwfn,
1273                                 p_dev->num_ports_in_engines,
1274                                 qm_info->max_phys_tcs_per_port,
1275                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1276                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1277                                 qm_info->qm_port_params);
1278
1279         ecore_cxt_hw_init_common(p_hwfn);
1280
1281         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1282         if (rc != ECORE_SUCCESS)
1283                 return rc;
1284
1285         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1286          * need to decide with which value, maybe runtime
1287          */
1288         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1289         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1290
1291         if (ECORE_IS_BB(p_dev)) {
1292                 /* Workaround clears ROCE search for all functions to prevent
1293                  * involving non initialized function in processing ROCE packet.
1294                  */
1295                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1296                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1297                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1298                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1299                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1300                 }
1301                 /* pretend to original PF */
1302                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1303         }
1304
1305         /* Workaround for avoiding CCFC execution error when getting packets
1306          * with CRC errors, and allowing instead the invoking of the FW error
1307          * handler.
1308          * This is not done inside the init tool since it currently can't
1309          * perform a pretending to VFs.
1310          */
1311         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1312         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1313                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1314                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1315                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1316                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1317                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1318                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1319         }
1320         /* pretend to original PF */
1321         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1322
1323         return rc;
1324 }
1325
1326 #ifndef ASIC_ONLY
1327 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1328 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1329
1330 #define PMEG_IF_BYTE_COUNT      8
1331
1332 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1333                              struct ecore_ptt *p_ptt,
1334                              u32 addr, u64 data, u8 reg_type, u8 port)
1335 {
1336         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1337                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1338                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1339                    (8 << PMEG_IF_BYTE_COUNT),
1340                    (reg_type << 25) | (addr << 8) | port,
1341                    (u32)((data >> 32) & 0xffffffff),
1342                    (u32)(data & 0xffffffff));
1343
1344         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1345                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1346                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1347         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1348                  (reg_type << 25) | (addr << 8) | port);
1349         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1350         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1351                  (data >> 32) & 0xffffffff);
1352 }
1353
1354 #define XLPORT_MODE_REG (0x20a)
1355 #define XLPORT_MAC_CONTROL (0x210)
1356 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1357 #define XLPORT_ENABLE_REG (0x20b)
1358
1359 #define XLMAC_CTRL (0x600)
1360 #define XLMAC_MODE (0x601)
1361 #define XLMAC_RX_MAX_SIZE (0x608)
1362 #define XLMAC_TX_CTRL (0x604)
1363 #define XLMAC_PAUSE_CTRL (0x60d)
1364 #define XLMAC_PFC_CTRL (0x60e)
1365
1366 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1367                                     struct ecore_ptt *p_ptt)
1368 {
1369         u8 loopback = 0, port = p_hwfn->port_id * 2;
1370
1371         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1372
1373         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1374         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1375                          port);
1376         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1377         /* XLMAC: SOFT RESET */
1378         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1379         /* XLMAC: Port Speed >= 10Gbps */
1380         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1381         /* XLMAC: Max Size */
1382         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1383         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1384                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1385                          0, port);
1386         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1387         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1388                          0x30ffffc000ULL, 0, port);
1389         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1390                          port); /* XLMAC: TX_EN, RX_EN */
1391         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1392         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1393                          0x1003 | (loopback << 2), 0, port);
1394         /* Enabled Parallel PFC interface */
1395         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1396
1397         /* XLPORT port enable */
1398         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1399 }
1400
1401 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1402                                        struct ecore_ptt *p_ptt)
1403 {
1404         u8 port = p_hwfn->port_id;
1405         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1406
1407         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1408
1409         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1410                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1411                  (port <<
1412                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1413                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1414
1415         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1416                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1417
1418         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1419                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1420
1421         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1422                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1423
1424         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1425                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1426
1427         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1428                  (0xA <<
1429                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1430                  (8 <<
1431                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1432
1433         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1434                  0xa853);
1435 }
1436
1437 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1438                                  struct ecore_ptt *p_ptt)
1439 {
1440         if (ECORE_IS_AH(p_hwfn->p_dev))
1441                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1442         else /* BB */
1443                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1444 }
1445
1446 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1447                                struct ecore_ptt *p_ptt,  u8 port)
1448 {
1449         int port_offset = port ? 0x800 : 0;
1450         u32 xmac_rxctrl = 0;
1451
1452         /* Reset of XMAC */
1453         /* FIXME: move to common start */
1454         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1455                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1456         OSAL_MSLEEP(1);
1457         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1458                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1459
1460         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1461
1462         /* Set the number of ports on the Warp Core to 10G */
1463         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1464
1465         /* Soft reset of XMAC */
1466         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1467                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1468         OSAL_MSLEEP(1);
1469         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1470                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1471
1472         /* FIXME: move to common end */
1473         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1474                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1475
1476         /* Set Max packet size: initialize XMAC block register for port 0 */
1477         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1478
1479         /* CRC append for Tx packets: init XMAC block register for port 1 */
1480         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1481
1482         /* Enable TX and RX: initialize XMAC block register for port 1 */
1483         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1484                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1485         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1486                                XMAC_REG_RX_CTRL_BB + port_offset);
1487         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1488         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1489 }
1490 #endif
1491
1492 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1493                                                struct ecore_ptt *p_ptt,
1494                                                int hw_mode)
1495 {
1496         enum _ecore_status_t rc = ECORE_SUCCESS;
1497
1498         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1499                             hw_mode);
1500         if (rc != ECORE_SUCCESS)
1501                 return rc;
1502 #ifndef ASIC_ONLY
1503         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1504                 return ECORE_SUCCESS;
1505
1506         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1507                 if (ECORE_IS_AH(p_hwfn->p_dev))
1508                         return ECORE_SUCCESS;
1509                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1510                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1511         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1512                 if (p_hwfn->p_dev->num_hwfns > 1) {
1513                         /* Activate OPTE in CMT */
1514                         u32 val;
1515
1516                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1517                         val |= 0x10;
1518                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1519                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1520                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1521                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1522                         ecore_wr(p_hwfn, p_ptt,
1523                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1524                         ecore_wr(p_hwfn, p_ptt,
1525                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1526                         ecore_wr(p_hwfn, p_ptt,
1527                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1528                                  0x55555555);
1529                 }
1530
1531                 ecore_emul_link_init(p_hwfn, p_ptt);
1532         } else {
1533                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1534         }
1535 #endif
1536
1537         return rc;
1538 }
1539
1540 static enum _ecore_status_t
1541 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1542                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1543 {
1544         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1545         u32 dpi_bit_shift, dpi_count;
1546         u32 min_dpis;
1547
1548         /* Calculate DPI size
1549          * ------------------
1550          * The PWM region contains Doorbell Pages. The first is reserverd for
1551          * the kernel for, e.g, L2. The others are free to be used by non-
1552          * trusted applications, typically from user space. Each page, called a
1553          * doorbell page is sectioned into windows that allow doorbells to be
1554          * issued in parallel by the kernel/application. The size of such a
1555          * window (a.k.a. WID) is 1kB.
1556          * Summary:
1557          *    1kB WID x N WIDS = DPI page size
1558          *    DPI page size x N DPIs = PWM region size
1559          * Notes:
1560          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1561          * in order to ensure that two applications won't share the same page.
1562          * It also must contain at least one WID per CPU to allow parallelism.
1563          * It also must be a power of 2, since it is stored as a bit shift.
1564          *
1565          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1566          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1567          * containing 4 WIDs.
1568          */
1569         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1570         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1571         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1572         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1573         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1574
1575         dpi_count = pwm_region_size / dpi_page_size;
1576
1577         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1578         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1579
1580         /* Update hwfn */
1581         p_hwfn->dpi_size = dpi_page_size;
1582         p_hwfn->dpi_count = dpi_count;
1583
1584         /* Update registers */
1585         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1586
1587         if (dpi_count < min_dpis)
1588                 return ECORE_NORESOURCES;
1589
1590         return ECORE_SUCCESS;
1591 }
1592
1593 enum ECORE_ROCE_EDPM_MODE {
1594         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1595         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1596         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1597 };
1598
1599 static enum _ecore_status_t
1600 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1601                               struct ecore_ptt *p_ptt)
1602 {
1603         u32 pwm_regsize, norm_regsize;
1604         u32 non_pwm_conn, min_addr_reg1;
1605         u32 db_bar_size, n_cpus;
1606         u32 roce_edpm_mode;
1607         u32 pf_dems_shift;
1608         int rc = ECORE_SUCCESS;
1609         u8 cond;
1610
1611         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1612         if (p_hwfn->p_dev->num_hwfns > 1)
1613                 db_bar_size /= 2;
1614
1615         /* Calculate doorbell regions
1616          * -----------------------------------
1617          * The doorbell BAR is made of two regions. The first is called normal
1618          * region and the second is called PWM region. In the normal region
1619          * each ICID has its own set of addresses so that writing to that
1620          * specific address identifies the ICID. In the Process Window Mode
1621          * region the ICID is given in the data written to the doorbell. The
1622          * above per PF register denotes the offset in the doorbell BAR in which
1623          * the PWM region begins.
1624          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1625          * non-PWM connection. The calculation below computes the total non-PWM
1626          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1627          * in units of 4,096 bytes.
1628          */
1629         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1630             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1631                                           OSAL_NULL) +
1632             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1633         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1634         min_addr_reg1 = norm_regsize / 4096;
1635         pwm_regsize = db_bar_size - norm_regsize;
1636
1637         /* Check that the normal and PWM sizes are valid */
1638         if (db_bar_size < norm_regsize) {
1639                 DP_ERR(p_hwfn->p_dev,
1640                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1641                        db_bar_size, norm_regsize);
1642                 return ECORE_NORESOURCES;
1643         }
1644         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1645                 DP_ERR(p_hwfn->p_dev,
1646                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1647                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1648                        norm_regsize);
1649                 return ECORE_NORESOURCES;
1650         }
1651
1652         /* Calculate number of DPIs */
1653         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1654         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1655             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1656                 /* Either EDPM is mandatory, or we are attempting to allocate a
1657                  * WID per CPU.
1658                  */
1659                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1660                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1661         }
1662
1663         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1664             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1665         if (cond || p_hwfn->dcbx_no_edpm) {
1666                 /* Either EDPM is disabled from user configuration, or it is
1667                  * disabled via DCBx, or it is not mandatory and we failed to
1668                  * allocated a WID per CPU.
1669                  */
1670                 n_cpus = 1;
1671                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1672
1673                 /* If we entered this flow due to DCBX then the DPM register is
1674                  * already configured.
1675                  */
1676         }
1677
1678         DP_INFO(p_hwfn,
1679                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1680                 norm_regsize, pwm_regsize);
1681         DP_INFO(p_hwfn,
1682                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1683                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1684                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1685                 "disabled" : "enabled");
1686
1687         /* Check return codes from above calls */
1688         if (rc) {
1689                 DP_ERR(p_hwfn,
1690                        "Failed to allocate enough DPIs\n");
1691                 return ECORE_NORESOURCES;
1692         }
1693
1694         /* Update hwfn */
1695         p_hwfn->dpi_start_offset = norm_regsize;
1696
1697         /* Update registers */
1698         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1699         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1700         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1701         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1702
1703         return ECORE_SUCCESS;
1704 }
1705
1706 static enum _ecore_status_t
1707 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1708                  struct ecore_ptt *p_ptt,
1709                  struct ecore_tunnel_info *p_tunn,
1710                  int hw_mode,
1711                  bool b_hw_start,
1712                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1713 {
1714         u8 rel_pf_id = p_hwfn->rel_pf_id;
1715         u32 prs_reg;
1716         enum _ecore_status_t rc = ECORE_SUCCESS;
1717         u16 ctrl;
1718         int pos;
1719
1720         if (p_hwfn->mcp_info) {
1721                 struct ecore_mcp_function_info *p_info;
1722
1723                 p_info = &p_hwfn->mcp_info->func_info;
1724                 if (p_info->bandwidth_min)
1725                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1726
1727                 /* Update rate limit once we'll actually have a link */
1728                 p_hwfn->qm_info.pf_rl = 100000;
1729         }
1730         ecore_cxt_hw_init_pf(p_hwfn);
1731
1732         ecore_int_igu_init_rt(p_hwfn);
1733
1734         /* Set VLAN in NIG if needed */
1735         if (hw_mode & (1 << MODE_MF_SD)) {
1736                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1737                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1738                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1739                              p_hwfn->hw_info.ovlan);
1740         }
1741
1742         /* Enable classification by MAC if needed */
1743         if (hw_mode & (1 << MODE_MF_SI)) {
1744                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1745                            "Configuring TAGMAC_CLS_TYPE\n");
1746                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1747                              1);
1748         }
1749
1750         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1751         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1752                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1753         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1754                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1755         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1756
1757         /* perform debug configuration when chip is out of reset */
1758         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1759
1760         /* Cleanup chip from previous driver if such remains exist */
1761         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1762         if (rc != ECORE_SUCCESS) {
1763                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1764                 return rc;
1765         }
1766
1767         /* PF Init sequence */
1768         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1769         if (rc)
1770                 return rc;
1771
1772         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1773         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1774         if (rc)
1775                 return rc;
1776
1777         /* Pure runtime initializations - directly to the HW  */
1778         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1779
1780         /* PCI relaxed ordering causes a decrease in the performance on some
1781          * systems. Till a root cause is found, disable this attribute in the
1782          * PCI config space.
1783          */
1784         /* Not in use @DPDK
1785         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1786         * if (!pos) {
1787         *       DP_NOTICE(p_hwfn, true,
1788         *                 "Failed to find the PCIe Cap\n");
1789         *       return ECORE_IO;
1790         * }
1791         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1792         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1793         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1794         */
1795
1796         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1797         if (rc)
1798                 return rc;
1799         if (b_hw_start) {
1800                 /* enable interrupts */
1801                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1802                 if (rc != ECORE_SUCCESS)
1803                         return rc;
1804
1805                 /* send function start command */
1806                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1807                                        allow_npar_tx_switch);
1808                 if (rc) {
1809                         DP_NOTICE(p_hwfn, true,
1810                                   "Function start ramrod failed\n");
1811                 } else {
1812                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1813                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1814                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1815
1816                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1817                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1818                                          (1 << 2));
1819                                 ecore_wr(p_hwfn, p_ptt,
1820                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1821                                     0x100);
1822                         }
1823                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1824                                    "PRS_REG_SEARCH registers after start PFn\n");
1825                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1826                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1827                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1828                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1829                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1830                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1831                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1832                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1833                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1834                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1835                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1836                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1837                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1838                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1839                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1840                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1841                                    prs_reg);
1842                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1843                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1844                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1845                 }
1846         }
1847         return rc;
1848 }
1849
1850 static enum _ecore_status_t
1851 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1852                       struct ecore_ptt *p_ptt, u8 enable)
1853 {
1854         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1855
1856         /* Change PF in PXP */
1857         ecore_wr(p_hwfn, p_ptt,
1858                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1859
1860         /* wait until value is set - try for 1 second every 50us */
1861         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1862                 val = ecore_rd(p_hwfn, p_ptt,
1863                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1864                 if (val == set_val)
1865                         break;
1866
1867                 OSAL_UDELAY(50);
1868         }
1869
1870         if (val != set_val) {
1871                 DP_NOTICE(p_hwfn, true,
1872                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1873                 return ECORE_UNKNOWN_ERROR;
1874         }
1875
1876         return ECORE_SUCCESS;
1877 }
1878
1879 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1880                                   struct ecore_ptt *p_main_ptt)
1881 {
1882         /* Read shadow of current MFW mailbox */
1883         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1884         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1885                     p_hwfn->mcp_info->mfw_mb_cur,
1886                     p_hwfn->mcp_info->mfw_mb_length);
1887 }
1888
1889 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1890                                     struct ecore_hw_init_params *p_params)
1891 {
1892         if (p_params->p_tunn) {
1893                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1894                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1895         }
1896
1897         p_hwfn->b_int_enabled = 1;
1898
1899         return ECORE_SUCCESS;
1900 }
1901
1902 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1903                                    struct ecore_hw_init_params *p_params)
1904 {
1905         struct ecore_load_req_params load_req_params;
1906         u32 load_code, param, drv_mb_param;
1907         struct ecore_hwfn *p_hwfn;
1908         bool b_default_mtu = true;
1909         enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1910         int i;
1911
1912         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1913             (p_dev->num_hwfns > 1)) {
1914                 DP_NOTICE(p_dev, false,
1915                           "MSI mode is not supported for CMT devices\n");
1916                 return ECORE_INVAL;
1917         }
1918
1919         if (IS_PF(p_dev)) {
1920                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1921                 if (rc != ECORE_SUCCESS)
1922                         return rc;
1923         }
1924
1925         for_each_hwfn(p_dev, i) {
1926                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1927
1928                 /* If management didn't provide a default, set one of our own */
1929                 if (!p_hwfn->hw_info.mtu) {
1930                         p_hwfn->hw_info.mtu = 1500;
1931                         b_default_mtu = false;
1932                 }
1933
1934                 if (IS_VF(p_dev)) {
1935                         ecore_vf_start(p_hwfn, p_params);
1936                         continue;
1937                 }
1938
1939                 /* Enable DMAE in PXP */
1940                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1941                 if (rc != ECORE_SUCCESS)
1942                         return rc;
1943
1944                 rc = ecore_calc_hw_mode(p_hwfn);
1945                 if (rc != ECORE_SUCCESS)
1946                         return rc;
1947
1948                 OSAL_MEM_ZERO(&load_req_params, sizeof(load_req_params));
1949                 load_req_params.drv_role = p_params->is_crash_kernel ?
1950                                            ECORE_DRV_ROLE_KDUMP :
1951                                            ECORE_DRV_ROLE_OS;
1952                 load_req_params.timeout_val = p_params->mfw_timeout_val;
1953                 load_req_params.avoid_eng_reset = p_params->avoid_eng_reset;
1954                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1955                                         &load_req_params);
1956                 if (rc != ECORE_SUCCESS) {
1957                         DP_NOTICE(p_hwfn, true,
1958                                   "Failed sending a LOAD_REQ command\n");
1959                         return rc;
1960                 }
1961
1962                 load_code = load_req_params.load_code;
1963                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1964                            "Load request was sent. Load code: 0x%x\n",
1965                            load_code);
1966
1967                 /* CQ75580:
1968                  * When coming back from hiberbate state, the registers from
1969                  * which shadow is read initially are not initialized. It turns
1970                  * out that these registers get initialized during the call to
1971                  * ecore_mcp_load_req request. So we need to reread them here
1972                  * to get the proper shadow register value.
1973                  * Note: This is a workaround for the missing MFW
1974                  * initialization. It may be removed once the implementation
1975                  * is done.
1976                  */
1977                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1978
1979                 /* Only relevant for recovery:
1980                  * Clear the indication after the LOAD_REQ command is responded
1981                  * by the MFW.
1982                  */
1983                 p_dev->recov_in_prog = false;
1984
1985                 p_hwfn->first_on_engine = (load_code ==
1986                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1987
1988                 if (!qm_lock_init) {
1989                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1990                         qm_lock_init = true;
1991                 }
1992
1993                 switch (load_code) {
1994                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1995                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1996                                                   p_hwfn->hw_info.hw_mode);
1997                         if (rc != ECORE_SUCCESS)
1998                                 break;
1999                         /* Fall into */
2000                 case FW_MSG_CODE_DRV_LOAD_PORT:
2001                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2002                                                 p_hwfn->hw_info.hw_mode);
2003                         if (rc != ECORE_SUCCESS)
2004                                 break;
2005                         /* Fall into */
2006                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2007                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2008                                               p_params->p_tunn,
2009                                               p_hwfn->hw_info.hw_mode,
2010                                               p_params->b_hw_start,
2011                                               p_params->int_mode,
2012                                               p_params->allow_npar_tx_switch);
2013                         break;
2014                 default:
2015                         DP_NOTICE(p_hwfn, false,
2016                                   "Unexpected load code [0x%08x]", load_code);
2017                         rc = ECORE_NOTIMPL;
2018                         break;
2019                 }
2020
2021                 if (rc != ECORE_SUCCESS)
2022                         DP_NOTICE(p_hwfn, true,
2023                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2024                                   load_code, rc);
2025
2026                 /* ACK mfw regardless of success or failure of initialization */
2027                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2028                                        DRV_MSG_CODE_LOAD_DONE,
2029                                        0, &load_code, &param);
2030                 if (rc != ECORE_SUCCESS)
2031                         return rc;
2032
2033                 if (mfw_rc != ECORE_SUCCESS) {
2034                         DP_NOTICE(p_hwfn, true,
2035                                   "Failed sending LOAD_DONE command\n");
2036                         return mfw_rc;
2037                 }
2038
2039                 /* send DCBX attention request command */
2040                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2041                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2042                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2043                                        DRV_MSG_CODE_SET_DCBX,
2044                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2045                                        &load_code, &param);
2046                 if (mfw_rc != ECORE_SUCCESS) {
2047                         DP_NOTICE(p_hwfn, true,
2048                                   "Failed to send DCBX attention request\n");
2049                         return mfw_rc;
2050                 }
2051
2052                 p_hwfn->hw_init_done = true;
2053         }
2054
2055         if (IS_PF(p_dev)) {
2056                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2057                 drv_mb_param = STORM_FW_VERSION;
2058                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2059                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2060                                    drv_mb_param, &load_code, &param);
2061                 if (rc != ECORE_SUCCESS)
2062                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2063
2064                 if (!b_default_mtu)
2065                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2066                                                       p_hwfn->hw_info.mtu);
2067                 if (rc != ECORE_SUCCESS)
2068                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2069
2070                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2071                                                       p_hwfn->p_main_ptt,
2072                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2073                 if (rc != ECORE_SUCCESS)
2074                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2075         }
2076
2077         return rc;
2078 }
2079
2080 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2081 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2082                                  struct ecore_hwfn *p_hwfn,
2083                                  struct ecore_ptt *p_ptt)
2084 {
2085         int i;
2086
2087         /* close timers */
2088         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2089         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2090         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2091                                                                         i++) {
2092                 if ((!ecore_rd(p_hwfn, p_ptt,
2093                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2094                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2095                         break;
2096
2097                 /* Dependent on number of connection/tasks, possibly
2098                  * 1ms sleep is required between polls
2099                  */
2100                 OSAL_MSLEEP(1);
2101         }
2102
2103         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2104                 return;
2105
2106         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2107                   " [Connection %02x Tasks %02x]\n",
2108                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2109                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2110 }
2111
2112 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2113 {
2114         int j;
2115
2116         for_each_hwfn(p_dev, j) {
2117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2118                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2119
2120                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2121         }
2122 }
2123
2124 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2125 {
2126         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
2127         int j;
2128
2129         for_each_hwfn(p_dev, j) {
2130                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2131                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2132
2133                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2134
2135                 if (IS_VF(p_dev)) {
2136                         ecore_vf_pf_int_cleanup(p_hwfn);
2137                         continue;
2138                 }
2139
2140                 /* mark the hw as uninitialized... */
2141                 p_hwfn->hw_init_done = false;
2142
2143                 rc = ecore_sp_pf_stop(p_hwfn);
2144                 if (rc)
2145                         DP_NOTICE(p_hwfn, true,
2146                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
2147
2148                 /* perform debug action after PF stop was sent */
2149                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
2150
2151                 /* close NIG to BRB gate */
2152                 ecore_wr(p_hwfn, p_ptt,
2153                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2154
2155                 /* close parser */
2156                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2157                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2158                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2159                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2160                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2161
2162                 /* @@@TBD - clean transmission queues (5.b) */
2163                 /* @@@TBD - clean BTB (5.c) */
2164
2165                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2166
2167                 /* @@@TBD - verify DMAE requests are done (8) */
2168
2169                 /* Disable Attention Generation */
2170                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2171                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2172                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2173                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2174                 /* Need to wait 1ms to guarantee SBs are cleared */
2175                 OSAL_MSLEEP(1);
2176         }
2177
2178         if (IS_PF(p_dev)) {
2179                 /* Disable DMAE in PXP - in CMT, this should only be done for
2180                  * first hw-function, and only after all transactions have
2181                  * stopped for all active hw-functions.
2182                  */
2183                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
2184                                              p_dev->hwfns[0].p_main_ptt, false);
2185                 if (t_rc != ECORE_SUCCESS)
2186                         rc = t_rc;
2187         }
2188
2189         return rc;
2190 }
2191
2192 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2193 {
2194         int j;
2195
2196         for_each_hwfn(p_dev, j) {
2197                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2198                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2199
2200                 if (IS_VF(p_dev)) {
2201                         ecore_vf_pf_int_cleanup(p_hwfn);
2202                         continue;
2203                 }
2204
2205                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2206                            "Shutting down the fastpath\n");
2207
2208                 ecore_wr(p_hwfn, p_ptt,
2209                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2210
2211                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2212                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2213                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2214                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2215                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2216
2217                 /* @@@TBD - clean transmission queues (5.b) */
2218                 /* @@@TBD - clean BTB (5.c) */
2219
2220                 /* @@@TBD - verify DMAE requests are done (8) */
2221
2222                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2223                 /* Need to wait 1ms to guarantee SBs are cleared */
2224                 OSAL_MSLEEP(1);
2225         }
2226 }
2227
2228 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2229 {
2230         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2231
2232         if (IS_VF(p_hwfn->p_dev))
2233                 return;
2234
2235         /* If roce info is allocated it means roce is initialized and should
2236          * be enabled in searcher.
2237          */
2238         if (p_hwfn->p_rdma_info) {
2239                 if (p_hwfn->b_rdma_enabled_in_prs)
2240                         ecore_wr(p_hwfn, p_ptt,
2241                                  p_hwfn->rdma_prs_search_reg, 0x1);
2242                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2243         }
2244
2245         /* Re-open incoming traffic */
2246         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2247                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2248 }
2249
2250 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
2251                                              struct ecore_ptt *p_ptt, u32 reg,
2252                                              bool expected)
2253 {
2254         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
2255
2256         if (assert_val != expected) {
2257                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
2258                           reg, expected);
2259                 return ECORE_UNKNOWN_ERROR;
2260         }
2261
2262         return 0;
2263 }
2264
2265 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
2266 {
2267         enum _ecore_status_t rc = ECORE_SUCCESS;
2268         u32 unload_resp, unload_param;
2269         int i;
2270
2271         for_each_hwfn(p_dev, i) {
2272                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2273
2274                 if (IS_VF(p_dev)) {
2275                         rc = ecore_vf_pf_reset(p_hwfn);
2276                         if (rc)
2277                                 return rc;
2278                         continue;
2279                 }
2280
2281                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
2282
2283                 /* Check for incorrect states */
2284                 if (!p_dev->recov_in_prog) {
2285                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2286                                          QM_REG_USG_CNT_PF_TX, 0);
2287                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2288                                          QM_REG_USG_CNT_PF_OTHER, 0);
2289                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2290                 }
2291
2292                 /* Disable PF in HW blocks */
2293                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2294                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2295
2296                 if (p_dev->recov_in_prog) {
2297                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2298                                    "Recovery is in progress -> skip sending unload_req/done\n");
2299                         break;
2300                 }
2301
2302                 /* Send unload command to MCP */
2303                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2304                                    DRV_MSG_CODE_UNLOAD_REQ,
2305                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
2306                                    &unload_resp, &unload_param);
2307                 if (rc != ECORE_SUCCESS) {
2308                         DP_NOTICE(p_hwfn, true,
2309                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
2310                         /* @@TBD - what to do? for now, assume ENG. */
2311                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2312                 }
2313
2314                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2315                                    DRV_MSG_CODE_UNLOAD_DONE,
2316                                    0, &unload_resp, &unload_param);
2317                 if (rc != ECORE_SUCCESS) {
2318                         DP_NOTICE(p_hwfn,
2319                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2320                         /* @@@TBD - Should it really ASSERT here ? */
2321                         return rc;
2322                 }
2323         }
2324
2325         return rc;
2326 }
2327
2328 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2329 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2330 {
2331         ecore_ptt_pool_free(p_hwfn);
2332         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2333 }
2334
2335 /* Setup bar access */
2336 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2337 {
2338         /* clear indirect access */
2339         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2340                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2341                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2342                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2343                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2344                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2345                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2346                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2347                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2348         } else {
2349                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2350                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2351                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2352                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2353                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2354                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2355                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2356                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2357         }
2358
2359         /* Clean Previous errors if such exist */
2360         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2361                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2362
2363         /* enable internal target-read */
2364         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2365                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2366 }
2367
2368 static void get_function_id(struct ecore_hwfn *p_hwfn)
2369 {
2370         /* ME Register */
2371         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2372                                                   PXP_PF_ME_OPAQUE_ADDR);
2373
2374         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2375
2376         /* Bits 16-19 from the ME registers are the pf_num */
2377         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2378         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2379                                       PXP_CONCRETE_FID_PFID);
2380         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2381                                     PXP_CONCRETE_FID_PORT);
2382
2383         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2384                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2385                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2386 }
2387
2388 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2389 {
2390         u32 *feat_num = p_hwfn->hw_info.feat_num;
2391         struct ecore_sb_cnt_info sb_cnt_info;
2392         int num_features = 1;
2393
2394         /* L2 Queues require each: 1 status block. 1 L2 queue */
2395         feat_num[ECORE_PF_L2_QUE] =
2396             OSAL_MIN_T(u32,
2397                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2398                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2399
2400         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2401         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2402         feat_num[ECORE_VF_L2_QUE] =
2403                 OSAL_MIN_T(u32,
2404                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2405                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2406                            sb_cnt_info.sb_iov_cnt);
2407
2408         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2409                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2410         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2411                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2412
2413         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2414                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2415                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2416                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2417                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2418                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2419                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2420                    RESC_NUM(p_hwfn, ECORE_SB));
2421 }
2422
2423 static enum resource_id_enum
2424 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2425 {
2426         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2427
2428         switch (res_id) {
2429         case ECORE_SB:
2430                 mfw_res_id = RESOURCE_NUM_SB_E;
2431                 break;
2432         case ECORE_L2_QUEUE:
2433                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2434                 break;
2435         case ECORE_VPORT:
2436                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2437                 break;
2438         case ECORE_RSS_ENG:
2439                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2440                 break;
2441         case ECORE_PQ:
2442                 mfw_res_id = RESOURCE_NUM_PQ_E;
2443                 break;
2444         case ECORE_RL:
2445                 mfw_res_id = RESOURCE_NUM_RL_E;
2446                 break;
2447         case ECORE_MAC:
2448         case ECORE_VLAN:
2449                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2450                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2451                 break;
2452         case ECORE_ILT:
2453                 mfw_res_id = RESOURCE_ILT_E;
2454                 break;
2455         case ECORE_LL2_QUEUE:
2456                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2457                 break;
2458         case ECORE_RDMA_CNQ_RAM:
2459         case ECORE_CMDQS_CQS:
2460                 /* CNQ/CMDQS are the same resource */
2461                 mfw_res_id = RESOURCE_CQS_E;
2462                 break;
2463         case ECORE_RDMA_STATS_QUEUE:
2464                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2465                 break;
2466         default:
2467                 break;
2468         }
2469
2470         return mfw_res_id;
2471 }
2472
2473 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2474                                       enum ecore_resources res_id)
2475 {
2476         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2477         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2478         struct ecore_sb_cnt_info sb_cnt_info;
2479         u32 dflt_resc_num = 0;
2480
2481         switch (res_id) {
2482         case ECORE_SB:
2483                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2484                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2485                 dflt_resc_num = sb_cnt_info.sb_cnt;
2486                 break;
2487         case ECORE_L2_QUEUE:
2488                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2489                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2490                 break;
2491         case ECORE_VPORT:
2492                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2493                                  MAX_NUM_VPORTS_BB) / num_funcs;
2494                 break;
2495         case ECORE_RSS_ENG:
2496                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2497                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2498                 break;
2499         case ECORE_PQ:
2500                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2501                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2502                 break;
2503         case ECORE_RL:
2504                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2505                 break;
2506         case ECORE_MAC:
2507         case ECORE_VLAN:
2508                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2509                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2510                 break;
2511         case ECORE_ILT:
2512                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2513                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2514                 break;
2515         case ECORE_LL2_QUEUE:
2516                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2517                 break;
2518         case ECORE_RDMA_CNQ_RAM:
2519         case ECORE_CMDQS_CQS:
2520                 /* CNQ/CMDQS are the same resource */
2521                 /* @DPDK */
2522                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2523                 break;
2524         case ECORE_RDMA_STATS_QUEUE:
2525                 /* @DPDK */
2526                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2527                                  MAX_NUM_VPORTS_BB) / num_funcs;
2528                 break;
2529         default:
2530                 break;
2531         }
2532
2533         return dflt_resc_num;
2534 }
2535
2536 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2537 {
2538         switch (res_id) {
2539         case ECORE_SB:
2540                 return "SB";
2541         case ECORE_L2_QUEUE:
2542                 return "L2_QUEUE";
2543         case ECORE_VPORT:
2544                 return "VPORT";
2545         case ECORE_RSS_ENG:
2546                 return "RSS_ENG";
2547         case ECORE_PQ:
2548                 return "PQ";
2549         case ECORE_RL:
2550                 return "RL";
2551         case ECORE_MAC:
2552                 return "MAC";
2553         case ECORE_VLAN:
2554                 return "VLAN";
2555         case ECORE_RDMA_CNQ_RAM:
2556                 return "RDMA_CNQ_RAM";
2557         case ECORE_ILT:
2558                 return "ILT";
2559         case ECORE_LL2_QUEUE:
2560                 return "LL2_QUEUE";
2561         case ECORE_CMDQS_CQS:
2562                 return "CMDQS_CQS";
2563         case ECORE_RDMA_STATS_QUEUE:
2564                 return "RDMA_STATS_QUEUE";
2565         default:
2566                 return "UNKNOWN_RESOURCE";
2567         }
2568 }
2569
2570 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2571                                                    enum ecore_resources res_id,
2572                                                    bool drv_resc_alloc)
2573 {
2574         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2575         u32 *p_resc_num, *p_resc_start;
2576         struct resource_info resc_info;
2577         enum _ecore_status_t rc;
2578
2579         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2580         p_resc_start = &RESC_START(p_hwfn, res_id);
2581
2582         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2583         if (!dflt_resc_num) {
2584                 DP_ERR(p_hwfn,
2585                        "Failed to get default amount for resource %d [%s]\n",
2586                         res_id, ecore_hw_get_resc_name(res_id));
2587                 return ECORE_INVAL;
2588         }
2589         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2590
2591 #ifndef ASIC_ONLY
2592         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2593                 *p_resc_num = dflt_resc_num;
2594                 *p_resc_start = dflt_resc_start;
2595                 goto out;
2596         }
2597 #endif
2598
2599         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2600         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2601         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2602                 DP_ERR(p_hwfn,
2603                        "Failed to match resource %d with MFW resources\n",
2604                        res_id);
2605                 return ECORE_INVAL;
2606         }
2607
2608         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2609                                      &mcp_resp, &mcp_param);
2610         if (rc != ECORE_SUCCESS) {
2611                 DP_NOTICE(p_hwfn, true,
2612                           "MFW response failure for an allocation request for"
2613                           " resource %d [%s]\n",
2614                           res_id, ecore_hw_get_resc_name(res_id));
2615                 return rc;
2616         }
2617
2618         /* Default driver values are applied in the following cases:
2619          * - The resource allocation MB command is not supported by the MFW
2620          * - There is an internal error in the MFW while processing the request
2621          * - The resource ID is unknown to the MFW
2622          */
2623         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2624             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2625                 /* @DPDK */
2626                 DP_INFO(p_hwfn,
2627                         "Resource %d [%s]: No allocation info was received"
2628                         " [mcp_resp 0x%x]. Applying default values"
2629                         " [num %d, start %d].\n",
2630                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2631                         dflt_resc_num, dflt_resc_start);
2632
2633                 *p_resc_num = dflt_resc_num;
2634                 *p_resc_start = dflt_resc_start;
2635                 goto out;
2636         }
2637
2638         /* TBD - remove this when revising the handling of the SB resource */
2639         if (res_id == ECORE_SB) {
2640                 /* Excluding the slowpath SB */
2641                 resc_info.size -= 1;
2642                 resc_info.offset -= p_hwfn->enabled_func_idx;
2643         }
2644
2645         *p_resc_num = resc_info.size;
2646         *p_resc_start = resc_info.offset;
2647
2648         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2649                 DP_INFO(p_hwfn,
2650                         "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2651                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2652                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2653                         drv_resc_alloc ? " - Applying default values" : "");
2654                 if (drv_resc_alloc) {
2655                         *p_resc_num = dflt_resc_num;
2656                         *p_resc_start = dflt_resc_start;
2657                 }
2658         }
2659 out:
2660         return ECORE_SUCCESS;
2661 }
2662
2663 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2664                                               bool drv_resc_alloc)
2665 {
2666         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2667         enum _ecore_status_t rc;
2668         u8 res_id;
2669 #ifndef ASIC_ONLY
2670         u32 *resc_start = p_hwfn->hw_info.resc_start;
2671         u32 *resc_num = p_hwfn->hw_info.resc_num;
2672         /* For AH, an equal share of the ILT lines between the maximal number of
2673          * PFs is not enough for RoCE. This would be solved by the future
2674          * resource allocation scheme, but isn't currently present for
2675          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2676          * to work - the BB number of ILT lines divided by its max PFs number.
2677          */
2678         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2679 #endif
2680
2681         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2682                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2683                 if (rc != ECORE_SUCCESS)
2684                         return rc;
2685         }
2686
2687 #ifndef ASIC_ONLY
2688         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2689                 /* Reduced build contains less PQs */
2690                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2691                         resc_num[ECORE_PQ] = 32;
2692                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2693                             p_hwfn->enabled_func_idx;
2694                 }
2695
2696                 /* For AH emulation, since we have a possible maximal number of
2697                  * 16 enabled PFs, in case there are not enough ILT lines -
2698                  * allocate only first PF as RoCE and have all the other ETH
2699                  * only with less ILT lines.
2700                  */
2701                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2702                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2703                                                          resc_num[ECORE_ILT],
2704                                                          roce_min_ilt_lines);
2705         }
2706
2707         /* Correct the common ILT calculation if PF0 has more */
2708         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2709             p_hwfn->p_dev->b_is_emul_full &&
2710             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2711                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2712                     resc_num[ECORE_ILT];
2713 #endif
2714
2715         /* Sanity for ILT */
2716         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2717             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2718                 DP_NOTICE(p_hwfn, true,
2719                           "Can't assign ILT pages [%08x,...,%08x]\n",
2720                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2721                                                                   ECORE_ILT) -
2722                           1);
2723                 return ECORE_INVAL;
2724         }
2725
2726         ecore_hw_set_feat(p_hwfn);
2727
2728         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2729                    "The numbers for each resource are:\n");
2730         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2731                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2732                            ecore_hw_get_resc_name(res_id),
2733                            RESC_NUM(p_hwfn, res_id),
2734                            RESC_START(p_hwfn, res_id));
2735
2736         return ECORE_SUCCESS;
2737 }
2738
2739 static enum _ecore_status_t
2740 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2741                       struct ecore_ptt *p_ptt,
2742                       struct ecore_hw_prepare_params *p_params)
2743 {
2744         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2745         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2746         struct ecore_mcp_link_params *link;
2747         enum _ecore_status_t rc;
2748
2749         /* Read global nvm_cfg address */
2750         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2751
2752         /* Verify MCP has initialized it */
2753         if (!nvm_cfg_addr) {
2754                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2755                 if (p_params->b_relaxed_probe)
2756                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2757                 return ECORE_INVAL;
2758         }
2759
2760 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2761
2762         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2763
2764         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2765             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2766                                                        core_cfg);
2767
2768         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2769
2770         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2771                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2772         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2773                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2774                 break;
2775         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2776                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2777                 break;
2778         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2779                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2780                 break;
2781         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2782                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2783                 break;
2784         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2785                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2786                 break;
2787         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2788                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2789                 break;
2790         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2791                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2792                 break;
2793         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2794                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2795                 break;
2796         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2797                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2798                 break;
2799         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2800                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2801                 break;
2802         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2803                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2804                 break;
2805         default:
2806                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2807                           core_cfg);
2808                 break;
2809         }
2810
2811         /* Read DCBX configuration */
2812         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2813                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2814         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2815                              port_cfg_addr +
2816                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2817         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2818                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2819         switch (dcbx_mode) {
2820         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2821                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2822                 break;
2823         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2824                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2825                 break;
2826         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2827                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2828                 break;
2829         default:
2830                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2831         }
2832
2833         /* Read default link configuration */
2834         link = &p_hwfn->mcp_info->link_input;
2835         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2836             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2837         link_temp = ecore_rd(p_hwfn, p_ptt,
2838                              port_cfg_addr +
2839                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2840         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2841         link->speed.advertised_speeds = link_temp;
2842
2843         link_temp = link->speed.advertised_speeds;
2844         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2845
2846         link_temp = ecore_rd(p_hwfn, p_ptt,
2847                              port_cfg_addr +
2848                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2849         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2850                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2851         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2852                 link->speed.autoneg = true;
2853                 break;
2854         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2855                 link->speed.forced_speed = 1000;
2856                 break;
2857         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2858                 link->speed.forced_speed = 10000;
2859                 break;
2860         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2861                 link->speed.forced_speed = 25000;
2862                 break;
2863         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2864                 link->speed.forced_speed = 40000;
2865                 break;
2866         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2867                 link->speed.forced_speed = 50000;
2868                 break;
2869         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2870                 link->speed.forced_speed = 100000;
2871                 break;
2872         default:
2873                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2874         }
2875
2876         p_hwfn->mcp_info->link_capabilities.default_speed =
2877             link->speed.forced_speed;
2878         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2879             link->speed.autoneg;
2880
2881         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2882         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2883         link->pause.autoneg = !!(link_temp &
2884                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2885         link->pause.forced_rx = !!(link_temp &
2886                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2887         link->pause.forced_tx = !!(link_temp &
2888                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2889         link->loopback_mode = 0;
2890
2891         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2892                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2893                    link->speed.forced_speed, link->speed.advertised_speeds,
2894                    link->speed.autoneg, link->pause.autoneg);
2895
2896         /* Read Multi-function information from shmem */
2897         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2898             OFFSETOF(struct nvm_cfg1, glob) +
2899             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2900
2901         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2902
2903         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2904             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2905
2906         switch (mf_mode) {
2907         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2908                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2909                 break;
2910         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2911                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2912                 break;
2913         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2914                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2915                 break;
2916         }
2917         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2918                 p_hwfn->p_dev->mf_mode);
2919
2920         /* Read Multi-function information from shmem */
2921         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2922             OFFSETOF(struct nvm_cfg1, glob) +
2923             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2924
2925         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2926         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2927                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2928                              &p_hwfn->hw_info.device_capabilities);
2929         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2930                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2931                              &p_hwfn->hw_info.device_capabilities);
2932         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2933                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2934                              &p_hwfn->hw_info.device_capabilities);
2935         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2936                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2937                              &p_hwfn->hw_info.device_capabilities);
2938         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2939                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2940                              &p_hwfn->hw_info.device_capabilities);
2941
2942         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2943         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2944                 rc = ECORE_SUCCESS;
2945                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2946         }
2947
2948         return rc;
2949 }
2950
2951 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2952                                 struct ecore_ptt *p_ptt)
2953 {
2954         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2955         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2956         struct ecore_dev *p_dev = p_hwfn->p_dev;
2957
2958         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2959
2960         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2961          * in the other bits are selected.
2962          * Bits 1-15 are for functions 1-15, respectively, and their value is
2963          * '0' only for enabled functions (function 0 always exists and
2964          * enabled).
2965          * In case of CMT in BB, only the "even" functions are enabled, and thus
2966          * the number of functions for both hwfns is learnt from the same bits.
2967          */
2968         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
2969                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
2970                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
2971         } else { /* E5 */
2972                 reg_function_hide = 0;
2973         }
2974
2975         if (reg_function_hide & 0x1) {
2976                 if (ECORE_IS_BB(p_dev)) {
2977                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2978                                 num_funcs = 0;
2979                                 eng_mask = 0xaaaa;
2980                         } else {
2981                                 num_funcs = 1;
2982                                 eng_mask = 0x5554;
2983                         }
2984                 } else {
2985                         num_funcs = 1;
2986                         eng_mask = 0xfffe;
2987                 }
2988
2989                 /* Get the number of the enabled functions on the engine */
2990                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2991                 while (tmp) {
2992                         if (tmp & 0x1)
2993                                 num_funcs++;
2994                         tmp >>= 0x1;
2995                 }
2996
2997                 /* Get the PF index within the enabled functions */
2998                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2999                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3000                 while (tmp) {
3001                         if (tmp & 0x1)
3002                                 enabled_func_idx--;
3003                         tmp >>= 0x1;
3004                 }
3005         }
3006
3007         p_hwfn->num_funcs_on_engine = num_funcs;
3008         p_hwfn->enabled_func_idx = enabled_func_idx;
3009
3010 #ifndef ASIC_ONLY
3011         if (CHIP_REV_IS_FPGA(p_dev)) {
3012                 DP_NOTICE(p_hwfn, false,
3013                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3014                 p_hwfn->num_funcs_on_engine = 4;
3015         }
3016 #endif
3017
3018         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3019                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3020                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3021                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3022 }
3023
3024 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3025                                       struct ecore_ptt *p_ptt)
3026 {
3027         u32 port_mode;
3028
3029 #ifndef ASIC_ONLY
3030         /* Read the port mode */
3031         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3032                 port_mode = 4;
3033         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3034                  (p_hwfn->p_dev->num_hwfns > 1))
3035                 /* In CMT on emulation, assume 1 port */
3036                 port_mode = 1;
3037         else
3038 #endif
3039         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3040
3041         if (port_mode < 3) {
3042                 p_hwfn->p_dev->num_ports_in_engines = 1;
3043         } else if (port_mode <= 5) {
3044                 p_hwfn->p_dev->num_ports_in_engines = 2;
3045         } else {
3046                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3047                           p_hwfn->p_dev->num_ports_in_engines);
3048
3049                 /* Default num_ports_in_engines to something */
3050                 p_hwfn->p_dev->num_ports_in_engines = 1;
3051         }
3052 }
3053
3054 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3055                                          struct ecore_ptt *p_ptt)
3056 {
3057         u32 port;
3058         int i;
3059
3060         p_hwfn->p_dev->num_ports_in_engines = 0;
3061
3062 #ifndef ASIC_ONLY
3063         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3064                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3065                 switch ((port & 0xf000) >> 12) {
3066                 case 1:
3067                         p_hwfn->p_dev->num_ports_in_engines = 1;
3068                         break;
3069                 case 3:
3070                         p_hwfn->p_dev->num_ports_in_engines = 2;
3071                         break;
3072                 case 0xf:
3073                         p_hwfn->p_dev->num_ports_in_engines = 4;
3074                         break;
3075                 default:
3076                         DP_NOTICE(p_hwfn, false,
3077                                   "Unknown port mode in ECO_RESERVED %08x\n",
3078                                   port);
3079                 }
3080         } else
3081 #endif
3082                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3083                         port = ecore_rd(p_hwfn, p_ptt,
3084                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3085                                         (i * 4));
3086                         if (port & 1)
3087                                 p_hwfn->p_dev->num_ports_in_engines++;
3088                 }
3089 }
3090
3091 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3092                                    struct ecore_ptt *p_ptt)
3093 {
3094         if (ECORE_IS_BB(p_hwfn->p_dev))
3095                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3096         else
3097                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3098 }
3099
3100 static enum _ecore_status_t
3101 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3102                   enum ecore_pci_personality personality,
3103                   struct ecore_hw_prepare_params *p_params)
3104 {
3105         bool drv_resc_alloc = p_params->drv_resc_alloc;
3106         enum _ecore_status_t rc;
3107
3108         /* Since all information is common, only first hwfns should do this */
3109         if (IS_LEAD_HWFN(p_hwfn)) {
3110                 rc = ecore_iov_hw_info(p_hwfn);
3111                 if (rc != ECORE_SUCCESS) {
3112                         if (p_params->b_relaxed_probe)
3113                                 p_params->p_relaxed_res =
3114                                                 ECORE_HW_PREPARE_BAD_IOV;
3115                         else
3116                                 return rc;
3117                 }
3118         }
3119
3120         /* TODO In get_hw_info, amoungst others:
3121          * Get MCP FW revision and determine according to it the supported
3122          * featrues (e.g. DCB)
3123          * Get boot mode
3124          * ecore_get_pcie_width_speed, WOL capability.
3125          * Number of global CQ-s (for storage
3126          */
3127         ecore_hw_info_port_num(p_hwfn, p_ptt);
3128
3129 #ifndef ASIC_ONLY
3130         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3131 #endif
3132         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3133         if (rc != ECORE_SUCCESS)
3134                 return rc;
3135 #ifndef ASIC_ONLY
3136         }
3137 #endif
3138
3139         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3140         if (rc != ECORE_SUCCESS) {
3141                 if (p_params->b_relaxed_probe)
3142                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3143                 else
3144                         return rc;
3145         }
3146
3147 #ifndef ASIC_ONLY
3148         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3149 #endif
3150                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3151                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3152 #ifndef ASIC_ONLY
3153         } else {
3154                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3155
3156                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3157                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3158         }
3159 #endif
3160
3161         if (ecore_mcp_is_init(p_hwfn)) {
3162                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3163                         p_hwfn->hw_info.ovlan =
3164                             p_hwfn->mcp_info->func_info.ovlan;
3165
3166                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3167         }
3168
3169         if (personality != ECORE_PCI_DEFAULT) {
3170                 p_hwfn->hw_info.personality = personality;
3171         } else if (ecore_mcp_is_init(p_hwfn)) {
3172                 enum ecore_pci_personality protocol;
3173
3174                 protocol = p_hwfn->mcp_info->func_info.protocol;
3175                 p_hwfn->hw_info.personality = protocol;
3176         }
3177
3178 #ifndef ASIC_ONLY
3179         /* To overcome ILT lack for emulation, until at least until we'll have
3180          * a definite answer from system about it, allow only PF0 to be RoCE.
3181          */
3182         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3183                 if (!p_hwfn->rel_pf_id)
3184                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3185                 else
3186                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3187         }
3188 #endif
3189
3190         /* although in BB some constellations may support more than 4 tcs,
3191          * that can result in performance penalty in some cases. 4
3192          * represents a good tradeoff between performance and flexibility.
3193          */
3194         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3195
3196         /* start out with a single active tc. This can be increased either
3197          * by dcbx negotiation or by upper layer driver
3198          */
3199         p_hwfn->hw_info.num_active_tc = 1;
3200
3201         ecore_get_num_funcs(p_hwfn, p_ptt);
3202
3203         if (ecore_mcp_is_init(p_hwfn))
3204                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3205
3206         /* In case of forcing the driver's default resource allocation, calling
3207          * ecore_hw_get_resc() should come after initializing the personality
3208          * and after getting the number of functions, since the calculation of
3209          * the resources/features depends on them.
3210          * This order is not harmful if not forcing.
3211          */
3212         rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3213         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3214                 rc = ECORE_SUCCESS;
3215                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3216         }
3217
3218         return rc;
3219 }
3220
3221 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3222 {
3223         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3224         u32 tmp;
3225
3226         /* Read Vendor Id / Device Id */
3227         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3228                                   &p_dev->vendor_id);
3229         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3230                                   &p_dev->device_id);
3231
3232         /* Determine type */
3233         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3234                 p_dev->type = ECORE_DEV_TYPE_AH;
3235         else
3236                 p_dev->type = ECORE_DEV_TYPE_BB;
3237
3238         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3239                                          MISCS_REG_CHIP_NUM);
3240         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3241                                          MISCS_REG_CHIP_REV);
3242
3243         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3244
3245         /* Learn number of HW-functions */
3246         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3247                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
3248
3249         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3250                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3251                 p_dev->num_hwfns = 2;
3252         } else {
3253                 p_dev->num_hwfns = 1;
3254         }
3255
3256 #ifndef ASIC_ONLY
3257         if (CHIP_REV_IS_EMUL(p_dev)) {
3258                 /* For some reason we have problems with this register
3259                  * in B0 emulation; Simply assume no CMT
3260                  */
3261                 DP_NOTICE(p_dev->hwfns, false,
3262                           "device on emul - assume no CMT\n");
3263                 p_dev->num_hwfns = 1;
3264         }
3265 #endif
3266
3267         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3268                                        MISCS_REG_CHIP_TEST_REG) >> 4;
3269         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3270         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3271                                            MISCS_REG_CHIP_METAL);
3272         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3273         DP_INFO(p_dev->hwfns,
3274                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3275                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3276                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3277                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3278                 p_dev->chip_metal);
3279
3280         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3281                 DP_NOTICE(p_dev->hwfns, false,
3282                           "The chip type/rev (BB A0) is not supported!\n");
3283                 return ECORE_ABORTED;
3284         }
3285 #ifndef ASIC_ONLY
3286         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3287                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3288                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3289
3290         if (CHIP_REV_IS_EMUL(p_dev)) {
3291                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3292                                MISCS_REG_ECO_RESERVED);
3293                 if (tmp & (1 << 29)) {
3294                         DP_NOTICE(p_hwfn, false,
3295                                   "Emulation: Running on a FULL build\n");
3296                         p_dev->b_is_emul_full = true;
3297                 } else {
3298                         DP_NOTICE(p_hwfn, false,
3299                                   "Emulation: Running on a REDUCED build\n");
3300                 }
3301         }
3302 #endif
3303
3304         return ECORE_SUCCESS;
3305 }
3306
3307 #ifndef LINUX_REMOVE
3308 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3309 {
3310         int j;
3311
3312         if (IS_VF(p_dev))
3313                 return;
3314
3315         for_each_hwfn(p_dev, j) {
3316                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3317
3318                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3319                            "Mark hw/fw uninitialized\n");
3320
3321                 p_hwfn->hw_init_done = false;
3322                 p_hwfn->first_on_engine = false;
3323
3324                 ecore_ptt_invalidate(p_hwfn);
3325         }
3326 }
3327 #endif
3328
3329 static enum _ecore_status_t
3330 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3331                         void OSAL_IOMEM * p_regview,
3332                         void OSAL_IOMEM * p_doorbells,
3333                         struct ecore_hw_prepare_params *p_params)
3334 {
3335         struct ecore_dev *p_dev = p_hwfn->p_dev;
3336         struct ecore_mdump_info mdump_info;
3337         enum _ecore_status_t rc = ECORE_SUCCESS;
3338
3339         /* Split PCI bars evenly between hwfns */
3340         p_hwfn->regview = p_regview;
3341         p_hwfn->doorbells = p_doorbells;
3342
3343         if (IS_VF(p_dev))
3344                 return ecore_vf_hw_prepare(p_hwfn);
3345
3346         /* Validate that chip access is feasible */
3347         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3348                 DP_ERR(p_hwfn,
3349                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3350                 if (p_params->b_relaxed_probe)
3351                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3352                 return ECORE_INVAL;
3353         }
3354
3355         get_function_id(p_hwfn);
3356
3357         /* Allocate PTT pool */
3358         rc = ecore_ptt_pool_alloc(p_hwfn);
3359         if (rc) {
3360                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3361                 if (p_params->b_relaxed_probe)
3362                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3363                 goto err0;
3364         }
3365
3366         /* Allocate the main PTT */
3367         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3368
3369         /* First hwfn learns basic information, e.g., number of hwfns */
3370         if (!p_hwfn->my_id) {
3371                 rc = ecore_get_dev_info(p_dev);
3372                 if (rc != ECORE_SUCCESS) {
3373                         if (p_params->b_relaxed_probe)
3374                                 p_params->p_relaxed_res =
3375                                         ECORE_HW_PREPARE_FAILED_DEV;
3376                         goto err1;
3377                 }
3378         }
3379
3380         ecore_hw_hwfn_prepare(p_hwfn);
3381
3382         /* Initialize MCP structure */
3383         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3384         if (rc) {
3385                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3386                 if (p_params->b_relaxed_probe)
3387                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3388                 goto err1;
3389         }
3390
3391         /* Read the device configuration information from the HW and SHMEM */
3392         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3393                                p_params->personality, p_params);
3394         if (rc) {
3395                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3396                 goto err2;
3397         }
3398
3399         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3400          * called, since among others it sets the ports number in an engine.
3401          */
3402         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3403             !p_dev->recov_in_prog) {
3404                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3405                 if (rc != ECORE_SUCCESS)
3406                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3407         }
3408
3409         /* Check if mdump logs are present and update the epoch value */
3410         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3411                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3412                                               &mdump_info);
3413                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3414                         DP_NOTICE(p_hwfn, false,
3415                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3416                 }
3417
3418                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3419                                            p_params->epoch);
3420         }
3421
3422         /* Allocate the init RT array and initialize the init-ops engine */
3423         rc = ecore_init_alloc(p_hwfn);
3424         if (rc) {
3425                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3426                 if (p_params->b_relaxed_probe)
3427                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3428                 goto err2;
3429         }
3430 #ifndef ASIC_ONLY
3431         if (CHIP_REV_IS_FPGA(p_dev)) {
3432                 DP_NOTICE(p_hwfn, false,
3433                           "FPGA: workaround; Prevent DMAE parities\n");
3434                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3435                          7);
3436
3437                 DP_NOTICE(p_hwfn, false,
3438                           "FPGA: workaround: Set VF bar0 size\n");
3439                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3440                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3441         }
3442 #endif
3443
3444         return rc;
3445 err2:
3446         if (IS_LEAD_HWFN(p_hwfn))
3447                 ecore_iov_free_hw_info(p_dev);
3448         ecore_mcp_free(p_hwfn);
3449 err1:
3450         ecore_hw_hwfn_free(p_hwfn);
3451 err0:
3452         return rc;
3453 }
3454
3455 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3456                                       struct ecore_hw_prepare_params *p_params)
3457 {
3458         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3459         enum _ecore_status_t rc;
3460
3461         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3462
3463         if (p_params->b_relaxed_probe)
3464                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3465
3466         /* Store the precompiled init data ptrs */
3467         if (IS_PF(p_dev))
3468                 ecore_init_iro_array(p_dev);
3469
3470         /* Initialize the first hwfn - will learn number of hwfns */
3471         rc = ecore_hw_prepare_single(p_hwfn,
3472                                      p_dev->regview,
3473                                      p_dev->doorbells, p_params);
3474         if (rc != ECORE_SUCCESS)
3475                 return rc;
3476
3477         p_params->personality = p_hwfn->hw_info.personality;
3478
3479         /* initilalize 2nd hwfn if necessary */
3480         if (p_dev->num_hwfns > 1) {
3481                 void OSAL_IOMEM *p_regview, *p_doorbell;
3482                 u8 OSAL_IOMEM *addr;
3483
3484                 /* adjust bar offset for second engine */
3485                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3486                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3487                 p_regview = (void OSAL_IOMEM *)addr;
3488
3489                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3490                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3491                 p_doorbell = (void OSAL_IOMEM *)addr;
3492
3493                 /* prepare second hw function */
3494                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3495                                              p_doorbell, p_params);
3496
3497                 /* in case of error, need to free the previously
3498                  * initiliazed hwfn 0.
3499                  */
3500                 if (rc != ECORE_SUCCESS) {
3501                         if (p_params->b_relaxed_probe)
3502                                 p_params->p_relaxed_res =
3503                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3504
3505                         if (IS_PF(p_dev)) {
3506                                 ecore_init_free(p_hwfn);
3507                                 ecore_mcp_free(p_hwfn);
3508                                 ecore_hw_hwfn_free(p_hwfn);
3509                         } else {
3510                                 DP_NOTICE(p_dev, true,
3511                                           "What do we need to free when VF hwfn1 init fails\n");
3512                         }
3513                         return rc;
3514                 }
3515         }
3516
3517         return rc;
3518 }
3519
3520 void ecore_hw_remove(struct ecore_dev *p_dev)
3521 {
3522         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3523         int i;
3524
3525         if (IS_PF(p_dev))
3526                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3527                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3528
3529         for_each_hwfn(p_dev, i) {
3530                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3531
3532                 if (IS_VF(p_dev)) {
3533                         ecore_vf_pf_release(p_hwfn);
3534                         continue;
3535                 }
3536
3537                 ecore_init_free(p_hwfn);
3538                 ecore_hw_hwfn_free(p_hwfn);
3539                 ecore_mcp_free(p_hwfn);
3540
3541                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3542         }
3543
3544         ecore_iov_free_hw_info(p_dev);
3545 }
3546
3547 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3548                                       struct ecore_chain *p_chain)
3549 {
3550         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3551         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3552         struct ecore_chain_next *p_next;
3553         u32 size, i;
3554
3555         if (!p_virt)
3556                 return;
3557
3558         size = p_chain->elem_size * p_chain->usable_per_page;
3559
3560         for (i = 0; i < p_chain->page_cnt; i++) {
3561                 if (!p_virt)
3562                         break;
3563
3564                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3565                 p_virt_next = p_next->next_virt;
3566                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3567
3568                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3569                                        ECORE_CHAIN_PAGE_SIZE);
3570
3571                 p_virt = p_virt_next;
3572                 p_phys = p_phys_next;
3573         }
3574 }
3575
3576 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3577                                     struct ecore_chain *p_chain)
3578 {
3579         if (!p_chain->p_virt_addr)
3580                 return;
3581
3582         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3583                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3584 }
3585
3586 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3587                                  struct ecore_chain *p_chain)
3588 {
3589         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3590         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3591         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3592
3593         if (!pp_virt_addr_tbl)
3594                 return;
3595
3596         if (!p_pbl_virt)
3597                 goto out;
3598
3599         for (i = 0; i < page_cnt; i++) {
3600                 if (!pp_virt_addr_tbl[i])
3601                         break;
3602
3603                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3604                                        *(dma_addr_t *)p_pbl_virt,
3605                                        ECORE_CHAIN_PAGE_SIZE);
3606
3607                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3608         }
3609
3610         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3611
3612         if (!p_chain->b_external_pbl)
3613                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3614                                        p_chain->pbl_sp.p_phys_table, pbl_size);
3615  out:
3616         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3617 }
3618
3619 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3620 {
3621         switch (p_chain->mode) {
3622         case ECORE_CHAIN_MODE_NEXT_PTR:
3623                 ecore_chain_free_next_ptr(p_dev, p_chain);
3624                 break;
3625         case ECORE_CHAIN_MODE_SINGLE:
3626                 ecore_chain_free_single(p_dev, p_chain);
3627                 break;
3628         case ECORE_CHAIN_MODE_PBL:
3629                 ecore_chain_free_pbl(p_dev, p_chain);
3630                 break;
3631         }
3632 }
3633
3634 static enum _ecore_status_t
3635 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3636                                enum ecore_chain_cnt_type cnt_type,
3637                                osal_size_t elem_size, u32 page_cnt)
3638 {
3639         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3640
3641         /* The actual chain size can be larger than the maximal possible value
3642          * after rounding up the requested elements number to pages, and after
3643          * taking into acount the unusuable elements (next-ptr elements).
3644          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3645          * size/capacity fields are of a u32 type.
3646          */
3647         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3648              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3649             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3650              chain_size > ECORE_U32_MAX)) {
3651                 DP_NOTICE(p_dev, true,
3652                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3653                           (unsigned long)chain_size);
3654                 return ECORE_INVAL;
3655         }
3656
3657         return ECORE_SUCCESS;
3658 }
3659
3660 static enum _ecore_status_t
3661 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3662 {
3663         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3664         dma_addr_t p_phys = 0;
3665         u32 i;
3666
3667         for (i = 0; i < p_chain->page_cnt; i++) {
3668                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3669                                                  ECORE_CHAIN_PAGE_SIZE);
3670                 if (!p_virt) {
3671                         DP_NOTICE(p_dev, true,
3672                                   "Failed to allocate chain memory\n");
3673                         return ECORE_NOMEM;
3674                 }
3675
3676                 if (i == 0) {
3677                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3678                         ecore_chain_reset(p_chain);
3679                 } else {
3680                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3681                                                        p_virt, p_phys);
3682                 }
3683
3684                 p_virt_prev = p_virt;
3685         }
3686         /* Last page's next element should point to the beginning of the
3687          * chain.
3688          */
3689         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3690                                        p_chain->p_virt_addr,
3691                                        p_chain->p_phys_addr);
3692
3693         return ECORE_SUCCESS;
3694 }
3695
3696 static enum _ecore_status_t
3697 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3698 {
3699         dma_addr_t p_phys = 0;
3700         void *p_virt = OSAL_NULL;
3701
3702         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3703         if (!p_virt) {
3704                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3705                 return ECORE_NOMEM;
3706         }
3707
3708         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3709         ecore_chain_reset(p_chain);
3710
3711         return ECORE_SUCCESS;
3712 }
3713
3714 static enum _ecore_status_t
3715 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3716                       struct ecore_chain *p_chain,
3717                       struct ecore_chain_ext_pbl *ext_pbl)
3718 {
3719         void *p_virt = OSAL_NULL;
3720         u8 *p_pbl_virt = OSAL_NULL;
3721         void **pp_virt_addr_tbl = OSAL_NULL;
3722         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3723         u32 page_cnt = p_chain->page_cnt, size, i;
3724
3725         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3726         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
3727         if (!pp_virt_addr_tbl) {
3728                 DP_NOTICE(p_dev, true,
3729                           "Failed to allocate memory for the chain virtual addresses table\n");
3730                 return ECORE_NOMEM;
3731         }
3732
3733         /* The allocation of the PBL table is done with its full size, since it
3734          * is expected to be successive.
3735          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3736          * failure, since pp_virt_addr_tbl was previously allocated, and it
3737          * should be saved to allow its freeing during the error flow.
3738          */
3739         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3740
3741         if (ext_pbl == OSAL_NULL) {
3742                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3743         } else {
3744                 p_pbl_virt = ext_pbl->p_pbl_virt;
3745                 p_pbl_phys = ext_pbl->p_pbl_phys;
3746                 p_chain->b_external_pbl = true;
3747         }
3748
3749         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3750                                  pp_virt_addr_tbl);
3751         if (!p_pbl_virt) {
3752                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3753                 return ECORE_NOMEM;
3754         }
3755
3756         for (i = 0; i < page_cnt; i++) {
3757                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3758                                                  ECORE_CHAIN_PAGE_SIZE);
3759                 if (!p_virt) {
3760                         DP_NOTICE(p_dev, true,
3761                                   "Failed to allocate chain memory\n");
3762                         return ECORE_NOMEM;
3763                 }
3764
3765                 if (i == 0) {
3766                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3767                         ecore_chain_reset(p_chain);
3768                 }
3769
3770                 /* Fill the PBL table with the physical address of the page */
3771                 *(dma_addr_t *)p_pbl_virt = p_phys;
3772                 /* Keep the virtual address of the page */
3773                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3774
3775                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3776         }
3777
3778         return ECORE_SUCCESS;
3779 }
3780
3781 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3782                                        enum ecore_chain_use_mode intended_use,
3783                                        enum ecore_chain_mode mode,
3784                                        enum ecore_chain_cnt_type cnt_type,
3785                                        u32 num_elems, osal_size_t elem_size,
3786                                        struct ecore_chain *p_chain,
3787                                        struct ecore_chain_ext_pbl *ext_pbl)
3788 {
3789         u32 page_cnt;
3790         enum _ecore_status_t rc = ECORE_SUCCESS;
3791
3792         if (mode == ECORE_CHAIN_MODE_SINGLE)
3793                 page_cnt = 1;
3794         else
3795                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3796
3797         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3798                                             page_cnt);
3799         if (rc) {
3800                 DP_NOTICE(p_dev, true,
3801                           "Cannot allocate a chain with the given arguments:\n"
3802                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3803                           intended_use, mode, cnt_type, num_elems, elem_size);
3804                 return rc;
3805         }
3806
3807         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3808                                 mode, cnt_type, p_dev->dp_ctx);
3809
3810         switch (mode) {
3811         case ECORE_CHAIN_MODE_NEXT_PTR:
3812                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3813                 break;
3814         case ECORE_CHAIN_MODE_SINGLE:
3815                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3816                 break;
3817         case ECORE_CHAIN_MODE_PBL:
3818                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3819                 break;
3820         }
3821         if (rc)
3822                 goto nomem;
3823
3824         return ECORE_SUCCESS;
3825
3826 nomem:
3827         ecore_chain_free(p_dev, p_chain);
3828         return rc;
3829 }
3830
3831 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3832                                        u16 src_id, u16 *dst_id)
3833 {
3834         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3835                 u16 min, max;
3836
3837                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3838                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3839                 DP_NOTICE(p_hwfn, true,
3840                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3841                           src_id, min, max);
3842
3843                 return ECORE_INVAL;
3844         }
3845
3846         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3847
3848         return ECORE_SUCCESS;
3849 }
3850
3851 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3852                                     u8 src_id, u8 *dst_id)
3853 {
3854         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3855                 u8 min, max;
3856
3857                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3858                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3859                 DP_NOTICE(p_hwfn, true,
3860                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3861                           src_id, min, max);
3862
3863                 return ECORE_INVAL;
3864         }
3865
3866         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3867
3868         return ECORE_SUCCESS;
3869 }
3870
3871 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3872                                       u8 src_id, u8 *dst_id)
3873 {
3874         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3875                 u8 min, max;
3876
3877                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3878                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3879                 DP_NOTICE(p_hwfn, true,
3880                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3881                           src_id, min, max);
3882
3883                 return ECORE_INVAL;
3884         }
3885
3886         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3887
3888         return ECORE_SUCCESS;
3889 }
3890
3891 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3892                                               struct ecore_ptt *p_ptt,
3893                                               u8 *p_filter)
3894 {
3895         u32 high, low, en;
3896         int i;
3897
3898         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3899                 return ECORE_SUCCESS;
3900
3901         high = p_filter[1] | (p_filter[0] << 8);
3902         low = p_filter[5] | (p_filter[4] << 8) |
3903             (p_filter[3] << 16) | (p_filter[2] << 24);
3904
3905         /* Find a free entry and utilize it */
3906         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3907                 en = ecore_rd(p_hwfn, p_ptt,
3908                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3909                 if (en)
3910                         continue;
3911                 ecore_wr(p_hwfn, p_ptt,
3912                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3913                          2 * i * sizeof(u32), low);
3914                 ecore_wr(p_hwfn, p_ptt,
3915                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3916                          (2 * i + 1) * sizeof(u32), high);
3917                 ecore_wr(p_hwfn, p_ptt,
3918                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3919                 ecore_wr(p_hwfn, p_ptt,
3920                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3921                          i * sizeof(u32), 0);
3922                 ecore_wr(p_hwfn, p_ptt,
3923                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3924                 break;
3925         }
3926         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3927                 DP_NOTICE(p_hwfn, false,
3928                           "Failed to find an empty LLH filter to utilize\n");
3929                 return ECORE_INVAL;
3930         }
3931
3932         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3933                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3934                    p_filter[0], p_filter[1], p_filter[2],
3935                    p_filter[3], p_filter[4], p_filter[5], i);
3936
3937         return ECORE_SUCCESS;
3938 }
3939
3940 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3941                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3942 {
3943         u32 high, low;
3944         int i;
3945
3946         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3947                 return;
3948
3949         high = p_filter[1] | (p_filter[0] << 8);
3950         low = p_filter[5] | (p_filter[4] << 8) |
3951             (p_filter[3] << 16) | (p_filter[2] << 24);
3952
3953         /* Find the entry and clean it */
3954         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3955                 if (ecore_rd(p_hwfn, p_ptt,
3956                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3957                              2 * i * sizeof(u32)) != low)
3958                         continue;
3959                 if (ecore_rd(p_hwfn, p_ptt,
3960                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3961                              (2 * i + 1) * sizeof(u32)) != high)
3962                         continue;
3963
3964                 ecore_wr(p_hwfn, p_ptt,
3965                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3966                 ecore_wr(p_hwfn, p_ptt,
3967                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3968                          2 * i * sizeof(u32), 0);
3969                 ecore_wr(p_hwfn, p_ptt,
3970                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3971                          (2 * i + 1) * sizeof(u32), 0);
3972                 break;
3973         }
3974         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3975                 DP_NOTICE(p_hwfn, false,
3976                           "Tried to remove a non-configured filter\n");
3977 }
3978
3979 enum _ecore_status_t
3980 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3981                               struct ecore_ptt *p_ptt,
3982                               u16 source_port_or_eth_type,
3983                               u16 dest_port,
3984                               enum ecore_llh_port_filter_type_t type)
3985 {
3986         u32 high, low, en;
3987         int i;
3988
3989         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3990                 return ECORE_SUCCESS;
3991
3992         high = 0;
3993         low = 0;
3994         switch (type) {
3995         case ECORE_LLH_FILTER_ETHERTYPE:
3996                 high = source_port_or_eth_type;
3997                 break;
3998         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3999         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4000                 low = source_port_or_eth_type << 16;
4001                 break;
4002         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4003         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4004                 low = dest_port;
4005                 break;
4006         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4007         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4008                 low = (source_port_or_eth_type << 16) | dest_port;
4009                 break;
4010         default:
4011                 DP_NOTICE(p_hwfn, true,
4012                           "Non valid LLH protocol filter type %d\n", type);
4013                 return ECORE_INVAL;
4014         }
4015         /* Find a free entry and utilize it */
4016         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4017                 en = ecore_rd(p_hwfn, p_ptt,
4018                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4019                 if (en)
4020                         continue;
4021                 ecore_wr(p_hwfn, p_ptt,
4022                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4023                          2 * i * sizeof(u32), low);
4024                 ecore_wr(p_hwfn, p_ptt,
4025                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4026                          (2 * i + 1) * sizeof(u32), high);
4027                 ecore_wr(p_hwfn, p_ptt,
4028                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4029                 ecore_wr(p_hwfn, p_ptt,
4030                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4031                          i * sizeof(u32), 1 << type);
4032                 ecore_wr(p_hwfn, p_ptt,
4033                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4034                 break;
4035         }
4036         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4037                 DP_NOTICE(p_hwfn, false,
4038                           "Failed to find an empty LLH filter to utilize\n");
4039                 return ECORE_NORESOURCES;
4040         }
4041         switch (type) {
4042         case ECORE_LLH_FILTER_ETHERTYPE:
4043                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4044                            "ETH type %x is added at %d\n",
4045                            source_port_or_eth_type, i);
4046                 break;
4047         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4048                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4049                            "TCP src port %x is added at %d\n",
4050                            source_port_or_eth_type, i);
4051                 break;
4052         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4053                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4054                            "UDP src port %x is added at %d\n",
4055                            source_port_or_eth_type, i);
4056                 break;
4057         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4058                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4059                            "TCP dst port %x is added at %d\n", dest_port, i);
4060                 break;
4061         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4062                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4063                            "UDP dst port %x is added at %d\n", dest_port, i);
4064                 break;
4065         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4066                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4067                            "TCP src/dst ports %x/%x are added at %d\n",
4068                            source_port_or_eth_type, dest_port, i);
4069                 break;
4070         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4071                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4072                            "UDP src/dst ports %x/%x are added at %d\n",
4073                            source_port_or_eth_type, dest_port, i);
4074                 break;
4075         }
4076         return ECORE_SUCCESS;
4077 }
4078
4079 void
4080 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4081                                  struct ecore_ptt *p_ptt,
4082                                  u16 source_port_or_eth_type,
4083                                  u16 dest_port,
4084                                  enum ecore_llh_port_filter_type_t type)
4085 {
4086         u32 high, low;
4087         int i;
4088
4089         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4090                 return;
4091
4092         high = 0;
4093         low = 0;
4094         switch (type) {
4095         case ECORE_LLH_FILTER_ETHERTYPE:
4096                 high = source_port_or_eth_type;
4097                 break;
4098         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4099         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4100                 low = source_port_or_eth_type << 16;
4101                 break;
4102         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4103         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4104                 low = dest_port;
4105                 break;
4106         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4107         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4108                 low = (source_port_or_eth_type << 16) | dest_port;
4109                 break;
4110         default:
4111                 DP_NOTICE(p_hwfn, true,
4112                           "Non valid LLH protocol filter type %d\n", type);
4113                 return;
4114         }
4115
4116         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4117                 if (!ecore_rd(p_hwfn, p_ptt,
4118                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4119                         continue;
4120                 if (!ecore_rd(p_hwfn, p_ptt,
4121                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4122                         continue;
4123                 if (!(ecore_rd(p_hwfn, p_ptt,
4124                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4125                                i * sizeof(u32)) & (1 << type)))
4126                         continue;
4127                 if (ecore_rd(p_hwfn, p_ptt,
4128                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4129                              2 * i * sizeof(u32)) != low)
4130                         continue;
4131                 if (ecore_rd(p_hwfn, p_ptt,
4132                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4133                              (2 * i + 1) * sizeof(u32)) != high)
4134                         continue;
4135
4136                 ecore_wr(p_hwfn, p_ptt,
4137                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4138                 ecore_wr(p_hwfn, p_ptt,
4139                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4140                 ecore_wr(p_hwfn, p_ptt,
4141                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4142                          i * sizeof(u32), 0);
4143                 ecore_wr(p_hwfn, p_ptt,
4144                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4145                          2 * i * sizeof(u32), 0);
4146                 ecore_wr(p_hwfn, p_ptt,
4147                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4148                          (2 * i + 1) * sizeof(u32), 0);
4149                 break;
4150         }
4151
4152         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4153                 DP_NOTICE(p_hwfn, false,
4154                           "Tried to remove a non-configured filter\n");
4155 }
4156
4157 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4158                                  struct ecore_ptt *p_ptt)
4159 {
4160         int i;
4161
4162         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4163                 return;
4164
4165         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4166                 ecore_wr(p_hwfn, p_ptt,
4167                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4168                 ecore_wr(p_hwfn, p_ptt,
4169                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4170                          2 * i * sizeof(u32), 0);
4171                 ecore_wr(p_hwfn, p_ptt,
4172                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4173                          (2 * i + 1) * sizeof(u32), 0);
4174         }
4175 }
4176
4177 enum _ecore_status_t
4178 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4179                                   struct ecore_ptt *p_ptt)
4180 {
4181         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4182                 ecore_wr(p_hwfn, p_ptt,
4183                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4184                          1 << p_hwfn->abs_pf_id / 2);
4185                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4186                 return ECORE_SUCCESS;
4187         }
4188
4189         DP_NOTICE(p_hwfn, false,
4190                   "This function can't be set as default\n");
4191         return ECORE_INVAL;
4192 }
4193
4194 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4195                                                struct ecore_ptt *p_ptt,
4196                                                u32 hw_addr, void *p_eth_qzone,
4197                                                osal_size_t eth_qzone_size,
4198                                                u8 timeset)
4199 {
4200         struct coalescing_timeset *p_coal_timeset;
4201
4202         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4203                 DP_NOTICE(p_hwfn, true,
4204                           "Coalescing configuration not enabled\n");
4205                 return ECORE_INVAL;
4206         }
4207
4208         p_coal_timeset = p_eth_qzone;
4209         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4210         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4211         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4212         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4213
4214         return ECORE_SUCCESS;
4215 }
4216
4217 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4218                                               u16 rx_coal, u16 tx_coal,
4219                                               void *p_handle)
4220 {
4221         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4222         enum _ecore_status_t rc = ECORE_SUCCESS;
4223         struct ecore_ptt *p_ptt;
4224
4225         /* TODO - Configuring a single queue's coalescing but
4226          * claiming all queues are abiding same configuration
4227          * for PF and VF both.
4228          */
4229
4230         if (IS_VF(p_hwfn->p_dev))
4231                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4232                                                 tx_coal, p_cid);
4233
4234         p_ptt = ecore_ptt_acquire(p_hwfn);
4235         if (!p_ptt)
4236                 return ECORE_AGAIN;
4237
4238         if (rx_coal) {
4239                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4240                 if (rc)
4241                         goto out;
4242                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
4243         }
4244
4245         if (tx_coal) {
4246                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4247                 if (rc)
4248                         goto out;
4249                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
4250         }
4251 out:
4252         ecore_ptt_release(p_hwfn, p_ptt);
4253
4254         return rc;
4255 }
4256
4257 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4258                                             struct ecore_ptt *p_ptt,
4259                                             u16 coalesce,
4260                                             struct ecore_queue_cid *p_cid)
4261 {
4262         struct ustorm_eth_queue_zone eth_qzone;
4263         u8 timeset, timer_res;
4264         u32 address;
4265         enum _ecore_status_t rc;
4266
4267         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4268         if (coalesce <= 0x7F) {
4269                 timer_res = 0;
4270         } else if (coalesce <= 0xFF) {
4271                 timer_res = 1;
4272         } else if (coalesce <= 0x1FF) {
4273                 timer_res = 2;
4274         } else {
4275                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4276                 return ECORE_INVAL;
4277         }
4278         timeset = (u8)(coalesce >> timer_res);
4279
4280         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4281                                      p_cid->abs.sb_idx, false);
4282         if (rc != ECORE_SUCCESS)
4283                 goto out;
4284
4285         address = BAR0_MAP_REG_USDM_RAM +
4286                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4287
4288         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4289                                 sizeof(struct ustorm_eth_queue_zone), timeset);
4290         if (rc != ECORE_SUCCESS)
4291                 goto out;
4292
4293  out:
4294         return rc;
4295 }
4296
4297 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4298                                             struct ecore_ptt *p_ptt,
4299                                             u16 coalesce,
4300                                             struct ecore_queue_cid *p_cid)
4301 {
4302         struct xstorm_eth_queue_zone eth_qzone;
4303         u8 timeset, timer_res;
4304         u32 address;
4305         enum _ecore_status_t rc;
4306
4307         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4308         if (coalesce <= 0x7F) {
4309                 timer_res = 0;
4310         } else if (coalesce <= 0xFF) {
4311                 timer_res = 1;
4312         } else if (coalesce <= 0x1FF) {
4313                 timer_res = 2;
4314         } else {
4315                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4316                 return ECORE_INVAL;
4317         }
4318
4319         timeset = (u8)(coalesce >> timer_res);
4320
4321         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4322                                      p_cid->abs.sb_idx, true);
4323         if (rc != ECORE_SUCCESS)
4324                 goto out;
4325
4326         address = BAR0_MAP_REG_XSDM_RAM +
4327                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4328
4329         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4330                                 sizeof(struct xstorm_eth_queue_zone), timeset);
4331  out:
4332         return rc;
4333 }
4334
4335 /* Calculate final WFQ values for all vports and configure it.
4336  * After this configuration each vport must have
4337  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4338  */
4339 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4340                                                struct ecore_ptt *p_ptt,
4341                                                u32 min_pf_rate)
4342 {
4343         struct init_qm_vport_params *vport_params;
4344         int i;
4345
4346         vport_params = p_hwfn->qm_info.qm_vport_params;
4347
4348         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4349                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4350
4351                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4352                     min_pf_rate;
4353                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4354                                      vport_params[i].first_tx_pq_id,
4355                                      vport_params[i].vport_wfq);
4356         }
4357 }
4358
4359 static void
4360 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4361 {
4362         int i;
4363
4364         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4365                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4366 }
4367
4368 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4369                                              struct ecore_ptt *p_ptt,
4370                                              u32 min_pf_rate)
4371 {
4372         struct init_qm_vport_params *vport_params;
4373         int i;
4374
4375         vport_params = p_hwfn->qm_info.qm_vport_params;
4376
4377         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4378                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4379                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4380                                      vport_params[i].first_tx_pq_id,
4381                                      vport_params[i].vport_wfq);
4382         }
4383 }
4384
4385 /* This function performs several validations for WFQ
4386  * configuration and required min rate for a given vport
4387  * 1. req_rate must be greater than one percent of min_pf_rate.
4388  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4389  *    rates to get less than one percent of min_pf_rate.
4390  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4391  */
4392 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4393                                                  u16 vport_id, u32 req_rate,
4394                                                  u32 min_pf_rate)
4395 {
4396         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4397         int non_requested_count = 0, req_count = 0, i, num_vports;
4398
4399         num_vports = p_hwfn->qm_info.num_vports;
4400
4401 /* Accounting for the vports which are configured for WFQ explicitly */
4402
4403         for (i = 0; i < num_vports; i++) {
4404                 u32 tmp_speed;
4405
4406                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4407                         req_count++;
4408                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4409                         total_req_min_rate += tmp_speed;
4410                 }
4411         }
4412
4413         /* Include current vport data as well */
4414         req_count++;
4415         total_req_min_rate += req_rate;
4416         non_requested_count = num_vports - req_count;
4417
4418         /* validate possible error cases */
4419         if (req_rate > min_pf_rate) {
4420                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4421                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4422                            vport_id, req_rate, min_pf_rate);
4423                 return ECORE_INVAL;
4424         }
4425
4426         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4427                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4428                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4429                            vport_id, req_rate, min_pf_rate);
4430                 return ECORE_INVAL;
4431         }
4432
4433         /* TBD - for number of vports greater than 100 */
4434         if (num_vports > ECORE_WFQ_UNIT) {
4435                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4436                            "Number of vports is greater than %d\n",
4437                            ECORE_WFQ_UNIT);
4438                 return ECORE_INVAL;
4439         }
4440
4441         if (total_req_min_rate > min_pf_rate) {
4442                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4443                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4444                            total_req_min_rate, min_pf_rate);
4445                 return ECORE_INVAL;
4446         }
4447
4448         /* Data left for non requested vports */
4449         total_left_rate = min_pf_rate - total_req_min_rate;
4450         left_rate_per_vp = total_left_rate / non_requested_count;
4451
4452         /* validate if non requested get < 1% of min bw */
4453         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4454                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4455                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4456                            left_rate_per_vp, min_pf_rate);
4457                 return ECORE_INVAL;
4458         }
4459
4460         /* now req_rate for given vport passes all scenarios.
4461          * assign final wfq rates to all vports.
4462          */
4463         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4464         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4465
4466         for (i = 0; i < num_vports; i++) {
4467                 if (p_hwfn->qm_info.wfq_data[i].configured)
4468                         continue;
4469
4470                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4471         }
4472
4473         return ECORE_SUCCESS;
4474 }
4475
4476 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4477                                        struct ecore_ptt *p_ptt,
4478                                        u16 vp_id, u32 rate)
4479 {
4480         struct ecore_mcp_link_state *p_link;
4481         int rc = ECORE_SUCCESS;
4482
4483         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4484
4485         if (!p_link->min_pf_rate) {
4486                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4487                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4488                 return rc;
4489         }
4490
4491         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4492
4493         if (rc == ECORE_SUCCESS)
4494                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4495                                                    p_link->min_pf_rate);
4496         else
4497                 DP_NOTICE(p_hwfn, false,
4498                           "Validation failed while configuring min rate\n");
4499
4500         return rc;
4501 }
4502
4503 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4504                                                    struct ecore_ptt *p_ptt,
4505                                                    u32 min_pf_rate)
4506 {
4507         bool use_wfq = false;
4508         int rc = ECORE_SUCCESS;
4509         u16 i;
4510
4511         /* Validate all pre configured vports for wfq */
4512         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4513                 u32 rate;
4514
4515                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4516                         continue;
4517
4518                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4519                 use_wfq = true;
4520
4521                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4522                 if (rc != ECORE_SUCCESS) {
4523                         DP_NOTICE(p_hwfn, false,
4524                                   "WFQ validation failed while configuring min rate\n");
4525                         break;
4526                 }
4527         }
4528
4529         if (rc == ECORE_SUCCESS && use_wfq)
4530                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4531         else
4532                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4533
4534         return rc;
4535 }
4536
4537 /* Main API for ecore clients to configure vport min rate.
4538  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4539  * rate - Speed in Mbps needs to be assigned to a given vport.
4540  */
4541 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4542 {
4543         int i, rc = ECORE_INVAL;
4544
4545         /* TBD - for multiple hardware functions - that is 100 gig */
4546         if (p_dev->num_hwfns > 1) {
4547                 DP_NOTICE(p_dev, false,
4548                           "WFQ configuration is not supported for this device\n");
4549                 return rc;
4550         }
4551
4552         for_each_hwfn(p_dev, i) {
4553                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4554                 struct ecore_ptt *p_ptt;
4555
4556                 p_ptt = ecore_ptt_acquire(p_hwfn);
4557                 if (!p_ptt)
4558                         return ECORE_TIMEOUT;
4559
4560                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4561
4562                 if (rc != ECORE_SUCCESS) {
4563                         ecore_ptt_release(p_hwfn, p_ptt);
4564                         return rc;
4565                 }
4566
4567                 ecore_ptt_release(p_hwfn, p_ptt);
4568         }
4569
4570         return rc;
4571 }
4572
4573 /* API to configure WFQ from mcp link change */
4574 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4575                                            u32 min_pf_rate)
4576 {
4577         int i;
4578
4579         /* TBD - for multiple hardware functions - that is 100 gig */
4580         if (p_dev->num_hwfns > 1) {
4581                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4582                            "WFQ configuration is not supported for this device\n");
4583                 return;
4584         }
4585
4586         for_each_hwfn(p_dev, i) {
4587                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4588
4589                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4590                                                         p_hwfn->p_dpc_ptt,
4591                                                         min_pf_rate);
4592         }
4593 }
4594
4595 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4596                                        struct ecore_ptt *p_ptt,
4597                                        struct ecore_mcp_link_state *p_link,
4598                                        u8 max_bw)
4599 {
4600         int rc = ECORE_SUCCESS;
4601
4602         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4603
4604         if (!p_link->line_speed && (max_bw != 100))
4605                 return rc;
4606
4607         p_link->speed = (p_link->line_speed * max_bw) / 100;
4608         p_hwfn->qm_info.pf_rl = p_link->speed;
4609
4610         /* Since the limiter also affects Tx-switched traffic, we don't want it
4611          * to limit such traffic in case there's no actual limit.
4612          * In that case, set limit to imaginary high boundary.
4613          */
4614         if (max_bw == 100)
4615                 p_hwfn->qm_info.pf_rl = 100000;
4616
4617         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4618                               p_hwfn->qm_info.pf_rl);
4619
4620         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4621                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4622                    p_link->speed);
4623
4624         return rc;
4625 }
4626
4627 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4628 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4629 {
4630         int i, rc = ECORE_INVAL;
4631
4632         if (max_bw < 1 || max_bw > 100) {
4633                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4634                 return rc;
4635         }
4636
4637         for_each_hwfn(p_dev, i) {
4638                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4639                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4640                 struct ecore_mcp_link_state *p_link;
4641                 struct ecore_ptt *p_ptt;
4642
4643                 p_link = &p_lead->mcp_info->link_output;
4644
4645                 p_ptt = ecore_ptt_acquire(p_hwfn);
4646                 if (!p_ptt)
4647                         return ECORE_TIMEOUT;
4648
4649                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4650                                                         p_link, max_bw);
4651
4652                 ecore_ptt_release(p_hwfn, p_ptt);
4653
4654                 if (rc != ECORE_SUCCESS)
4655                         break;
4656         }
4657
4658         return rc;
4659 }
4660
4661 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4662                                        struct ecore_ptt *p_ptt,
4663                                        struct ecore_mcp_link_state *p_link,
4664                                        u8 min_bw)
4665 {
4666         int rc = ECORE_SUCCESS;
4667
4668         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4669         p_hwfn->qm_info.pf_wfq = min_bw;
4670
4671         if (!p_link->line_speed)
4672                 return rc;
4673
4674         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4675
4676         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4677
4678         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4679                    "Configured MIN bandwidth to be %d Mb/sec\n",
4680                    p_link->min_pf_rate);
4681
4682         return rc;
4683 }
4684
4685 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4686 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4687 {
4688         int i, rc = ECORE_INVAL;
4689
4690         if (min_bw < 1 || min_bw > 100) {
4691                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4692                 return rc;
4693         }
4694
4695         for_each_hwfn(p_dev, i) {
4696                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4697                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4698                 struct ecore_mcp_link_state *p_link;
4699                 struct ecore_ptt *p_ptt;
4700
4701                 p_link = &p_lead->mcp_info->link_output;
4702
4703                 p_ptt = ecore_ptt_acquire(p_hwfn);
4704                 if (!p_ptt)
4705                         return ECORE_TIMEOUT;
4706
4707                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4708                                                         p_link, min_bw);
4709                 if (rc != ECORE_SUCCESS) {
4710                         ecore_ptt_release(p_hwfn, p_ptt);
4711                         return rc;
4712                 }
4713
4714                 if (p_link->min_pf_rate) {
4715                         u32 min_rate = p_link->min_pf_rate;
4716
4717                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4718                                                                      p_ptt,
4719                                                                      min_rate);
4720                 }
4721
4722                 ecore_ptt_release(p_hwfn, p_ptt);
4723         }
4724
4725         return rc;
4726 }
4727
4728 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4729 {
4730         struct ecore_mcp_link_state *p_link;
4731
4732         p_link = &p_hwfn->mcp_info->link_output;
4733
4734         if (p_link->min_pf_rate)
4735                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4736                                                  p_link->min_pf_rate);
4737
4738         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4739                     sizeof(*p_hwfn->qm_info.wfq_data) *
4740                     p_hwfn->qm_info.num_vports);
4741 }
4742
4743 int ecore_device_num_engines(struct ecore_dev *p_dev)
4744 {
4745         return ECORE_IS_BB(p_dev) ? 2 : 1;
4746 }
4747
4748 int ecore_device_num_ports(struct ecore_dev *p_dev)
4749 {
4750         /* in CMT always only one port */
4751         if (p_dev->num_hwfns > 1)
4752                 return 1;
4753
4754         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4755 }
4756
4757 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4758                           __le16 *fw_mid,
4759                           __le16 *fw_lsb,
4760                           u8 *mac)
4761 {
4762         ((u8 *)fw_msb)[0] = mac[1];
4763         ((u8 *)fw_msb)[1] = mac[0];
4764         ((u8 *)fw_mid)[0] = mac[3];
4765         ((u8 *)fw_mid)[1] = mac[2];
4766         ((u8 *)fw_lsb)[0] = mac[5];
4767         ((u8 *)fw_lsb)[1] = mac[4];
4768 }