drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /* Configurable */
  46 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  47                                          * load the driver. The number was
  48                                          * arbitrarily set.
  49                                          */
  50
  51 /* Derived */
  52 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  53
  54 enum BAR_ID {
  55         BAR_ID_0,               /* used for GRC */
  56         BAR_ID_1                /* Used for doorbells */
  57 };
  58
  59 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
  60                              struct ecore_ptt *p_ptt,
  61                              enum BAR_ID bar_id)
  62 {
  63         u32 bar_reg = (bar_id == BAR_ID_0 ?
  64                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  65         u32 val;
  66
  67         if (IS_VF(p_hwfn->p_dev)) {
  68                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  69                  * read from actual register, but we're currently not using
  70                  * it for actual doorbelling.
  71                  */
  72                 return 1 << 17;
  73         }
  74
  75         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
  76         if (val)
  77                 return 1 << (val + 15);
  78
  79         /* The above registers were updated in the past only in CMT mode. Since
  80          * they were found to be useful MFW started updating them from 8.7.7.0.
  81          * In older MFW versions they are set to 0 which means disabled.
  82          */
  83         if (p_hwfn->p_dev->num_hwfns > 1) {
  84                 DP_INFO(p_hwfn,
  85                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  86                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  87         } else {
  88                 DP_INFO(p_hwfn,
  89                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  90                 val = 512 * 1024;
  91         }
  92
  93         return val;
  94 }
  95
  96 void ecore_init_dp(struct ecore_dev *p_dev,
  97                    u32 dp_module, u8 dp_level, void *dp_ctx)
  98 {
  99         u32 i;
 100
 101         p_dev->dp_level = dp_level;
 102         p_dev->dp_module = dp_module;
 103         p_dev->dp_ctx = dp_ctx;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109                 p_hwfn->dp_ctx = dp_ctx;
 110         }
 111 }
 112
 113 void ecore_init_struct(struct ecore_dev *p_dev)
 114 {
 115         u8 i;
 116
 117         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 118                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 119
 120                 p_hwfn->p_dev = p_dev;
 121                 p_hwfn->my_id = i;
 122                 p_hwfn->b_active = false;
 123
 124                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 125                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 126         }
 127
 128         /* hwfn 0 is always active */
 129         p_dev->hwfns[0].b_active = true;
 130
 131         /* set the default cache alignment to 128 (may be overridden later) */
 132         p_dev->cache_shift = 7;
 133 }
 134
 135 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 136 {
 137         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 138
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 142         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 143 }
 144
 145 void ecore_resc_free(struct ecore_dev *p_dev)
 146 {
 147         int i;
 148
 149         if (IS_VF(p_dev)) {
 150                 for_each_hwfn(p_dev, i)
 151                         ecore_l2_free(&p_dev->hwfns[i]);
 152                 return;
 153         }
 154
 155         OSAL_FREE(p_dev, p_dev->fw_data);
 156
 157         OSAL_FREE(p_dev, p_dev->reset_stats);
 158
 159         for_each_hwfn(p_dev, i) {
 160                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 161
 162                 ecore_cxt_mngr_free(p_hwfn);
 163                 ecore_qm_info_free(p_hwfn);
 164                 ecore_spq_free(p_hwfn);
 165                 ecore_eq_free(p_hwfn);
 166                 ecore_consq_free(p_hwfn);
 167                 ecore_int_free(p_hwfn);
 168                 ecore_iov_free(p_hwfn);
 169                 ecore_l2_free(p_hwfn);
 170                 ecore_dmae_info_free(p_hwfn);
 171                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 172                 /* @@@TBD Flush work-queue ? */
 173         }
 174 }
 175
 176 /******************** QM initialization *******************/
 177
 178 /* bitmaps for indicating active traffic classes.
 179  * Special case for Arrowhead 4 port
 180  */
 181 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 182 #define ACTIVE_TCS_BMAP 0x9f
 183 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 184 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 185
 186 /* determines the physical queue flags for a given PF. */
 187 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 188 {
 189         u32 flags;
 190
 191         /* common flags */
 192         flags = PQ_FLAGS_LB;
 193
 194         /* feature flags */
 195         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 196                 flags |= PQ_FLAGS_VFS;
 197
 198         /* protocol flags */
 199         switch (p_hwfn->hw_info.personality) {
 200         case ECORE_PCI_ETH:
 201                 flags |= PQ_FLAGS_MCOS;
 202                 break;
 203         case ECORE_PCI_FCOE:
 204                 flags |= PQ_FLAGS_OFLD;
 205                 break;
 206         case ECORE_PCI_ISCSI:
 207                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 208                 break;
 209         case ECORE_PCI_ETH_ROCE:
 210                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 211                 break;
 212         case ECORE_PCI_ETH_IWARP:
 213                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 214                          PQ_FLAGS_OFLD;
 215                 break;
 216         default:
 217                 DP_ERR(p_hwfn, "unknown personality %d\n",
 218                        p_hwfn->hw_info.personality);
 219                 return 0;
 220         }
 221         return flags;
 222 }
 223
 224 /* Getters for resource amounts necessary for qm initialization */
 225 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 226 {
 227         return p_hwfn->hw_info.num_hw_tc;
 228 }
 229
 230 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 231 {
 232         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 233                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 234 }
 235
 236 #define NUM_DEFAULT_RLS 1
 237
 238 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 239 {
 240         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 241
 242         /* @DPDK */
 243         /* num RLs can't exceed resource amount of rls or vports or the
 244          * dcqcn qps
 245          */
 246         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 247                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 248
 249         /* make sure after we reserve the default and VF rls we'll have
 250          * something left
 251          */
 252         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 253                 DP_NOTICE(p_hwfn, false,
 254                           "no rate limiters left for PF rate limiting"
 255                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 256                 return 0;
 257         }
 258
 259         /* subtract rls necessary for VFs and one default one for the PF */
 260         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 261
 262         return num_pf_rls;
 263 }
 264
 265 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 266 {
 267         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 268
 269         /* all pqs share the same vport (hence the 1 below), except for vfs
 270          * and pf_rl pqs
 271          */
 272         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 273                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 274                (!!(PQ_FLAGS_VFS & pq_flags)) *
 275                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 276 }
 277
 278 /* calc amount of PQs according to the requested flags */
 279 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 280 {
 281         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 282
 283         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 284                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 285                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 286                 ecore_init_qm_get_num_tcs(p_hwfn) +
 287                (!!(PQ_FLAGS_LB & pq_flags)) +
 288                (!!(PQ_FLAGS_OOO & pq_flags)) +
 289                (!!(PQ_FLAGS_ACK & pq_flags)) +
 290                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 291                (!!(PQ_FLAGS_VFS & pq_flags)) *
 292                 ecore_init_qm_get_num_vfs(p_hwfn);
 293 }
 294
 295 /* initialize the top level QM params */
 296 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 297 {
 298         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 299         bool four_port;
 300
 301         /* pq and vport bases for this PF */
 302         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 303         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 304
 305         /* rate limiting and weighted fair queueing are always enabled */
 306         qm_info->vport_rl_en = 1;
 307         qm_info->vport_wfq_en = 1;
 308
 309         /* TC config is different for AH 4 port */
 310         four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
 311
 312         /* in AH 4 port we have fewer TCs per port */
 313         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 314                                                      NUM_OF_PHYS_TCS;
 315
 316         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 317          * 4 otherwise
 318          */
 319         if (!qm_info->ooo_tc)
 320                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 321                                               DCBX_TCP_OOO_TC;
 322 }
 323
 324 /* initialize qm vport params */
 325 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 326 {
 327         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 328         u8 i;
 329
 330         /* all vports participate in weighted fair queueing */
 331         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 332                 qm_info->qm_vport_params[i].vport_wfq = 1;
 333 }
 334
 335 /* initialize qm port params */
 336 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 337 {
 338         /* Initialize qm port parameters */
 339         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
 340
 341         /* indicate how ooo and high pri traffic is dealt with */
 342         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 343                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 344
 345         for (i = 0; i < num_ports; i++) {
 346                 struct init_qm_port_params *p_qm_port =
 347                         &p_hwfn->qm_info.qm_port_params[i];
 348
 349                 p_qm_port->active = 1;
 350                 p_qm_port->active_phys_tcs = active_phys_tcs;
 351                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 352                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 353         }
 354 }
 355
 356 /* Reset the params which must be reset for qm init. QM init may be called as
 357  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 358  * params may be affected by the init but would simply recalculate to the same
 359  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 360  * affected as these amounts stay the same.
 361  */
 362 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 363 {
 364         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 365
 366         qm_info->num_pqs = 0;
 367         qm_info->num_vports = 0;
 368         qm_info->num_pf_rls = 0;
 369         qm_info->num_vf_pqs = 0;
 370         qm_info->first_vf_pq = 0;
 371         qm_info->first_mcos_pq = 0;
 372         qm_info->first_rl_pq = 0;
 373 }
 374
 375 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 376 {
 377         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 378
 379         qm_info->num_vports++;
 380
 381         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 382                 DP_ERR(p_hwfn,
 383                        "vport overflow! qm_info->num_vports %d,"
 384                        " qm_init_get_num_vports() %d\n",
 385                        qm_info->num_vports,
 386                        ecore_init_qm_get_num_vports(p_hwfn));
 387 }
 388
 389 /* initialize a single pq and manage qm_info resources accounting.
 390  * The pq_init_flags param determines whether the PQ is rate limited
 391  * (for VF or PF)
 392  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 393  * shared)
 394  */
 395
 396 /* flags for pq init */
 397 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 398 #define PQ_INIT_PF_RL           (1 << 1)
 399 #define PQ_INIT_VF_RL           (1 << 2)
 400
 401 /* defines for pq init */
 402 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 403 #define PQ_INIT_DEFAULT_TC              0
 404 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 405
 406 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 407                              struct ecore_qm_info *qm_info,
 408                              u8 tc, u32 pq_init_flags)
 409 {
 410         u16 pq_idx = qm_info->num_pqs, max_pq =
 411                                         ecore_init_qm_get_num_pqs(p_hwfn);
 412
 413         if (pq_idx > max_pq)
 414                 DP_ERR(p_hwfn,
 415                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 416
 417         /* init pq params */
 418         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 419                                                  qm_info->num_vports;
 420         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 421         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 422         qm_info->qm_pq_params[pq_idx].rl_valid =
 423                 (pq_init_flags & PQ_INIT_PF_RL ||
 424                  pq_init_flags & PQ_INIT_VF_RL);
 425
 426         /* qm params accounting */
 427         qm_info->num_pqs++;
 428         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 429                 qm_info->num_vports++;
 430
 431         if (pq_init_flags & PQ_INIT_PF_RL)
 432                 qm_info->num_pf_rls++;
 433
 434         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 435                 DP_ERR(p_hwfn,
 436                        "vport overflow! qm_info->num_vports %d,"
 437                        " qm_init_get_num_vports() %d\n",
 438                        qm_info->num_vports,
 439                        ecore_init_qm_get_num_vports(p_hwfn));
 440
 441         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 442                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 443                        " qm_init_get_num_pf_rls() %d\n",
 444                        qm_info->num_pf_rls,
 445                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 446 }
 447
 448 /* get pq index according to PQ_FLAGS */
 449 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 450                                              u32 pq_flags)
 451 {
 452         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 453
 454         /* Can't have multiple flags set here */
 455         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 456                                 sizeof(pq_flags)) > 1)
 457                 goto err;
 458
 459         switch (pq_flags) {
 460         case PQ_FLAGS_RLS:
 461                 return &qm_info->first_rl_pq;
 462         case PQ_FLAGS_MCOS:
 463                 return &qm_info->first_mcos_pq;
 464         case PQ_FLAGS_LB:
 465                 return &qm_info->pure_lb_pq;
 466         case PQ_FLAGS_OOO:
 467                 return &qm_info->ooo_pq;
 468         case PQ_FLAGS_ACK:
 469                 return &qm_info->pure_ack_pq;
 470         case PQ_FLAGS_OFLD:
 471                 return &qm_info->offload_pq;
 472         case PQ_FLAGS_VFS:
 473                 return &qm_info->first_vf_pq;
 474         default:
 475                 goto err;
 476         }
 477
 478 err:
 479         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 480         return OSAL_NULL;
 481 }
 482
 483 /* save pq index in qm info */
 484 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 485                                   u32 pq_flags, u16 pq_val)
 486 {
 487         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 488
 489         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 490 }
 491
 492 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 493 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 494 {
 495         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 496
 497         return *base_pq_idx + CM_TX_PQ_BASE;
 498 }
 499
 500 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 501 {
 502         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 503
 504         if (tc > max_tc)
 505                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 506
 507         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 508 }
 509
 510 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 511 {
 512         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 513
 514         if (vf > max_vf)
 515                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 516
 517         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 518 }
 519
 520 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 521 {
 522         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 523
 524         if (rl > max_rl)
 525                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 526
 527         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 528 }
 529
 530 /* Functions for creating specific types of pqs */
 531 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 532 {
 533         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 534
 535         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 536                 return;
 537
 538         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 539         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 540 }
 541
 542 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 543 {
 544         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 545
 546         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 547                 return;
 548
 549         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 550         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 551 }
 552
 553 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 554 {
 555         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 556
 557         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 558                 return;
 559
 560         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 561         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 562 }
 563
 564 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 565 {
 566         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 567
 568         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 569                 return;
 570
 571         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 572         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 573 }
 574
 575 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 576 {
 577         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 578         u8 tc_idx;
 579
 580         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 581                 return;
 582
 583         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 584         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 585                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 586 }
 587
 588 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 589 {
 590         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 591         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 592
 593         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 594                 return;
 595
 596         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 597
 598         qm_info->num_vf_pqs = num_vfs;
 599         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 600                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 601                                  PQ_INIT_VF_RL);
 602 }
 603
 604 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 605 {
 606         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 607         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 608
 609         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 610                 return;
 611
 612         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 613         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 614                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 615                                  PQ_INIT_PF_RL);
 616 }
 617
 618 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 619 {
 620         /* rate limited pqs, must come first (FW assumption) */
 621         ecore_init_qm_rl_pqs(p_hwfn);
 622
 623         /* pqs for multi cos */
 624         ecore_init_qm_mcos_pqs(p_hwfn);
 625
 626         /* pure loopback pq */
 627         ecore_init_qm_lb_pq(p_hwfn);
 628
 629         /* out of order pq */
 630         ecore_init_qm_ooo_pq(p_hwfn);
 631
 632         /* pure ack pq */
 633         ecore_init_qm_pure_ack_pq(p_hwfn);
 634
 635         /* pq for offloaded protocol */
 636         ecore_init_qm_offload_pq(p_hwfn);
 637
 638         /* done sharing vports */
 639         ecore_init_qm_advance_vport(p_hwfn);
 640
 641         /* pqs for vfs */
 642         ecore_init_qm_vf_pqs(p_hwfn);
 643 }
 644
 645 /* compare values of getters against resources amounts */
 646 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 647 {
 648         if (ecore_init_qm_get_num_vports(p_hwfn) >
 649             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 650                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 651                 return ECORE_INVAL;
 652         }
 653
 654         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 655                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 656                 return ECORE_INVAL;
 657         }
 658
 659         return ECORE_SUCCESS;
 660 }
 661
 662 /*
 663  * Function for verbose printing of the qm initialization results
 664  */
 665 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 666 {
 667         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 668         struct init_qm_vport_params *vport;
 669         struct init_qm_port_params *port;
 670         struct init_qm_pq_params *pq;
 671         int i, tc;
 672
 673         /* top level params */
 674         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 675                    "qm init top level params: start_pq %d, start_vport %d,"
 676                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 677                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 678                    qm_info->offload_pq, qm_info->pure_ack_pq);
 679         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 680                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 681                    " num_vports %d, max_phys_tcs_per_port %d\n",
 682                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 683                    qm_info->num_vf_pqs, qm_info->num_vports,
 684                    qm_info->max_phys_tcs_per_port);
 685         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 686                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 687                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 688                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 689                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 690                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 691
 692         /* port table */
 693         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
 694                 port = &qm_info->qm_port_params[i];
 695                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 696                            "port idx %d, active %d, active_phys_tcs %d,"
 697                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
 698                            " reserved %d\n",
 699                            i, port->active, port->active_phys_tcs,
 700                            port->num_pbf_cmd_lines, port->num_btb_blocks,
 701                            port->reserved);
 702         }
 703
 704         /* vport table */
 705         for (i = 0; i < qm_info->num_vports; i++) {
 706                 vport = &qm_info->qm_vport_params[i];
 707                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 708                            "vport idx %d, vport_rl %d, wfq %d,"
 709                            " first_tx_pq_id [ ",
 710                            qm_info->start_vport + i, vport->vport_rl,
 711                            vport->vport_wfq);
 712                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 713                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
 714                                    vport->first_tx_pq_id[tc]);
 715                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
 716         }
 717
 718         /* pq table */
 719         for (i = 0; i < qm_info->num_pqs; i++) {
 720                 pq = &qm_info->qm_pq_params[i];
 721                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 722                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
 723                            " rl_valid %d\n",
 724                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
 725                            pq->wrr_group, pq->rl_valid);
 726         }
 727 }
 728
 729 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
 730 {
 731         /* reset params required for init run */
 732         ecore_init_qm_reset_params(p_hwfn);
 733
 734         /* init QM top level params */
 735         ecore_init_qm_params(p_hwfn);
 736
 737         /* init QM port params */
 738         ecore_init_qm_port_params(p_hwfn);
 739
 740         /* init QM vport params */
 741         ecore_init_qm_vport_params(p_hwfn);
 742
 743         /* init QM physical queue params */
 744         ecore_init_qm_pq_params(p_hwfn);
 745
 746         /* display all that init */
 747         ecore_dp_init_qm_params(p_hwfn);
 748 }
 749
 750 /* This function reconfigures the QM pf on the fly.
 751  * For this purpose we:
 752  * 1. reconfigure the QM database
 753  * 2. set new values to runtime array
 754  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 755  * 4. activate init tool in QM_PF stage
 756  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 757  */
 758 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 759                                      struct ecore_ptt *p_ptt)
 760 {
 761         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 762         bool b_rc;
 763         enum _ecore_status_t rc;
 764
 765         /* initialize ecore's qm data structure */
 766         ecore_init_qm_info(p_hwfn);
 767
 768         /* stop PF's qm queues */
 769         OSAL_SPIN_LOCK(&qm_lock);
 770         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 771                                       qm_info->start_pq, qm_info->num_pqs);
 772         OSAL_SPIN_UNLOCK(&qm_lock);
 773         if (!b_rc)
 774                 return ECORE_INVAL;
 775
 776         /* clear the QM_PF runtime phase leftovers from previous init */
 777         ecore_init_clear_rt_data(p_hwfn);
 778
 779         /* prepare QM portion of runtime array */
 780         ecore_qm_init_pf(p_hwfn, p_ptt);
 781
 782         /* activate init tool on runtime array */
 783         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 784                             p_hwfn->hw_info.hw_mode);
 785         if (rc != ECORE_SUCCESS)
 786                 return rc;
 787
 788         /* start PF's qm queues */
 789         OSAL_SPIN_LOCK(&qm_lock);
 790         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 791                                       qm_info->start_pq, qm_info->num_pqs);
 792         OSAL_SPIN_UNLOCK(&qm_lock);
 793         if (!b_rc)
 794                 return ECORE_INVAL;
 795
 796         return ECORE_SUCCESS;
 797 }
 798
 799 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
 800 {
 801         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 802         enum _ecore_status_t rc;
 803
 804         rc = ecore_init_qm_sanity(p_hwfn);
 805         if (rc != ECORE_SUCCESS)
 806                 goto alloc_err;
 807
 808         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 809                                             sizeof(struct init_qm_pq_params) *
 810                                             ecore_init_qm_get_num_pqs(p_hwfn));
 811         if (!qm_info->qm_pq_params)
 812                 goto alloc_err;
 813
 814         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 815                                        sizeof(struct init_qm_vport_params) *
 816                                        ecore_init_qm_get_num_vports(p_hwfn));
 817         if (!qm_info->qm_vport_params)
 818                 goto alloc_err;
 819
 820         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 821                                       sizeof(struct init_qm_port_params) *
 822                                       p_hwfn->p_dev->num_ports_in_engines);
 823         if (!qm_info->qm_port_params)
 824                 goto alloc_err;
 825
 826         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 827                                         sizeof(struct ecore_wfq_data) *
 828                                         ecore_init_qm_get_num_vports(p_hwfn));
 829         if (!qm_info->wfq_data)
 830                 goto alloc_err;
 831
 832         return ECORE_SUCCESS;
 833
 834 alloc_err:
 835         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 836         ecore_qm_info_free(p_hwfn);
 837         return ECORE_NOMEM;
 838 }
 839 /******************** End QM initialization ***************/
 840
 841 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 842 {
 843         enum _ecore_status_t rc = ECORE_SUCCESS;
 844         int i;
 845
 846         if (IS_VF(p_dev)) {
 847                 for_each_hwfn(p_dev, i) {
 848                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
 849                         if (rc != ECORE_SUCCESS)
 850                                 return rc;
 851                 }
 852                 return rc;
 853         }
 854
 855         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 856                                      sizeof(*p_dev->fw_data));
 857         if (!p_dev->fw_data)
 858                 return ECORE_NOMEM;
 859
 860         for_each_hwfn(p_dev, i) {
 861                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 862                 u32 n_eqes, num_cons;
 863
 864                 /* First allocate the context manager structure */
 865                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 866                 if (rc)
 867                         goto alloc_err;
 868
 869                 /* Set the HW cid/tid numbers (in the contest manager)
 870                  * Must be done prior to any further computations.
 871                  */
 872                 rc = ecore_cxt_set_pf_params(p_hwfn);
 873                 if (rc)
 874                         goto alloc_err;
 875
 876                 rc = ecore_alloc_qm_data(p_hwfn);
 877                 if (rc)
 878                         goto alloc_err;
 879
 880                 /* init qm info */
 881                 ecore_init_qm_info(p_hwfn);
 882
 883                 /* Compute the ILT client partition */
 884                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 885                 if (rc)
 886                         goto alloc_err;
 887
 888                 /* CID map / ILT shadow table / T2
 889                  * The talbes sizes are determined by the computations above
 890                  */
 891                 rc = ecore_cxt_tables_alloc(p_hwfn);
 892                 if (rc)
 893                         goto alloc_err;
 894
 895                 /* SPQ, must follow ILT because initializes SPQ context */
 896                 rc = ecore_spq_alloc(p_hwfn);
 897                 if (rc)
 898                         goto alloc_err;
 899
 900                 /* SP status block allocation */
 901                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 902                                                            RESERVED_PTT_DPC);
 903
 904                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 905                 if (rc)
 906                         goto alloc_err;
 907
 908                 rc = ecore_iov_alloc(p_hwfn);
 909                 if (rc)
 910                         goto alloc_err;
 911
 912                 /* EQ */
 913                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 914                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 915                         /* Calculate the EQ size
 916                          * ---------------------
 917                          * Each ICID may generate up to one event at a time i.e.
 918                          * the event must be handled/cleared before a new one
 919                          * can be generated. We calculate the sum of events per
 920                          * protocol and create an EQ deep enough to handle the
 921                          * worst case:
 922                          * - Core - according to SPQ.
 923                          * - RoCE - per QP there are a couple of ICIDs, one
 924                          *        responder and one requester, each can
 925                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
 926                          *        Each CQ can generate an EQE. There are 2 CQs
 927                          *        per QP => n_eqes_cq = 2 * n_qp.
 928                          *        Hence the RoCE total is 4 * n_qp or
 929                          *        2 * num_cons.
 930                          * - ENet - There can be up to two events per VF. One
 931                          *        for VF-PF channel and another for VF FLR
 932                          *        initial cleanup. The number of VFs is
 933                          *        bounded by MAX_NUM_VFS_BB, and is much
 934                          *        smaller than RoCE's so we avoid exact
 935                          *        calculation.
 936                          */
 937                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 938                                 num_cons =
 939                                     ecore_cxt_get_proto_cid_count(
 940                                                 p_hwfn,
 941                                                 PROTOCOLID_ROCE,
 942                                                 OSAL_NULL);
 943                                 num_cons *= 2;
 944                         } else {
 945                                 num_cons = ecore_cxt_get_proto_cid_count(
 946                                                 p_hwfn,
 947                                                 PROTOCOLID_IWARP,
 948                                                 OSAL_NULL);
 949                         }
 950                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 951                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 952                         num_cons =
 953                             ecore_cxt_get_proto_cid_count(p_hwfn,
 954                                                           PROTOCOLID_ISCSI,
 955                                                           OSAL_NULL);
 956                         n_eqes += 2 * num_cons;
 957                 }
 958
 959                 if (n_eqes > 0xFFFF) {
 960                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 961                                        "The maximum of a u16 chain is 0x%x\n",
 962                                n_eqes, 0xFFFF);
 963                         goto alloc_no_mem;
 964                 }
 965
 966                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 967                 if (rc)
 968                         goto alloc_err;
 969
 970                 rc = ecore_consq_alloc(p_hwfn);
 971                 if (rc)
 972                         goto alloc_err;
 973
 974                 rc = ecore_l2_alloc(p_hwfn);
 975                 if (rc != ECORE_SUCCESS)
 976                         goto alloc_err;
 977
 978                 /* DMA info initialization */
 979                 rc = ecore_dmae_info_alloc(p_hwfn);
 980                 if (rc) {
 981                         DP_NOTICE(p_hwfn, true,
 982                                   "Failed to allocate memory for dmae_info"
 983                                   " structure\n");
 984                         goto alloc_err;
 985                 }
 986
 987                 /* DCBX initialization */
 988                 rc = ecore_dcbx_info_alloc(p_hwfn);
 989                 if (rc) {
 990                         DP_NOTICE(p_hwfn, true,
 991                                   "Failed to allocate memory for dcbx structure\n");
 992                         goto alloc_err;
 993                 }
 994         }
 995
 996         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 997                                          sizeof(*p_dev->reset_stats));
 998         if (!p_dev->reset_stats) {
 999                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1000                 goto alloc_no_mem;
1001         }
1002
1003         return ECORE_SUCCESS;
1004
1005 alloc_no_mem:
1006         rc = ECORE_NOMEM;
1007 alloc_err:
1008         ecore_resc_free(p_dev);
1009         return rc;
1010 }
1011
1012 void ecore_resc_setup(struct ecore_dev *p_dev)
1013 {
1014         int i;
1015
1016         if (IS_VF(p_dev)) {
1017                 for_each_hwfn(p_dev, i)
1018                         ecore_l2_setup(&p_dev->hwfns[i]);
1019                 return;
1020         }
1021
1022         for_each_hwfn(p_dev, i) {
1023                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1024
1025                 ecore_cxt_mngr_setup(p_hwfn);
1026                 ecore_spq_setup(p_hwfn);
1027                 ecore_eq_setup(p_hwfn);
1028                 ecore_consq_setup(p_hwfn);
1029
1030                 /* Read shadow of current MFW mailbox */
1031                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1032                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1033                             p_hwfn->mcp_info->mfw_mb_cur,
1034                             p_hwfn->mcp_info->mfw_mb_length);
1035
1036                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1037
1038                 ecore_l2_setup(p_hwfn);
1039                 ecore_iov_setup(p_hwfn);
1040         }
1041 }
1042
1043 #define FINAL_CLEANUP_POLL_CNT  (100)
1044 #define FINAL_CLEANUP_POLL_TIME (10)
1045 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1046                                          struct ecore_ptt *p_ptt,
1047                                          u16 id, bool is_vf)
1048 {
1049         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1050         enum _ecore_status_t rc = ECORE_TIMEOUT;
1051
1052 #ifndef ASIC_ONLY
1053         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1054             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1055                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1056                 return ECORE_SUCCESS;
1057         }
1058 #endif
1059
1060         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1061             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1062
1063         if (is_vf)
1064                 id += 0x10;
1065
1066         command |= X_FINAL_CLEANUP_AGG_INT <<
1067             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1068         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1069         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1070         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1071
1072 /* Make sure notification is not set before initiating final cleanup */
1073
1074         if (REG_RD(p_hwfn, addr)) {
1075                 DP_NOTICE(p_hwfn, false,
1076                           "Unexpected; Found final cleanup notification");
1077                 DP_NOTICE(p_hwfn, false,
1078                           " before initiating final cleanup\n");
1079                 REG_WR(p_hwfn, addr, 0);
1080         }
1081
1082         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1083                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1084                    id, command);
1085
1086         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1087
1088         /* Poll until completion */
1089         while (!REG_RD(p_hwfn, addr) && count--)
1090                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1091
1092         if (REG_RD(p_hwfn, addr))
1093                 rc = ECORE_SUCCESS;
1094         else
1095                 DP_NOTICE(p_hwfn, true,
1096                           "Failed to receive FW final cleanup notification\n");
1097
1098         /* Cleanup afterwards */
1099         REG_WR(p_hwfn, addr, 0);
1100
1101         return rc;
1102 }
1103
1104 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1105 {
1106         int hw_mode = 0;
1107
1108         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1109                 hw_mode |= 1 << MODE_BB;
1110         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1111                 hw_mode |= 1 << MODE_K2;
1112         } else {
1113                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1114                           p_hwfn->p_dev->type);
1115                 return ECORE_INVAL;
1116         }
1117
1118         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1119         switch (p_hwfn->p_dev->num_ports_in_engines) {
1120         case 1:
1121                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1122                 break;
1123         case 2:
1124                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1125                 break;
1126         case 4:
1127                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1128                 break;
1129         default:
1130                 DP_NOTICE(p_hwfn, true,
1131                           "num_ports_in_engine = %d not supported\n",
1132                           p_hwfn->p_dev->num_ports_in_engines);
1133                 return ECORE_INVAL;
1134         }
1135
1136         switch (p_hwfn->p_dev->mf_mode) {
1137         case ECORE_MF_DEFAULT:
1138         case ECORE_MF_NPAR:
1139                 hw_mode |= 1 << MODE_MF_SI;
1140                 break;
1141         case ECORE_MF_OVLAN:
1142                 hw_mode |= 1 << MODE_MF_SD;
1143                 break;
1144         default:
1145                 DP_NOTICE(p_hwfn, true,
1146                           "Unsupported MF mode, init as DEFAULT\n");
1147                 hw_mode |= 1 << MODE_MF_SI;
1148         }
1149
1150 #ifndef ASIC_ONLY
1151         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1152                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1153                         hw_mode |= 1 << MODE_FPGA;
1154                 } else {
1155                         if (p_hwfn->p_dev->b_is_emul_full)
1156                                 hw_mode |= 1 << MODE_EMUL_FULL;
1157                         else
1158                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1159                 }
1160         } else
1161 #endif
1162                 hw_mode |= 1 << MODE_ASIC;
1163
1164         if (p_hwfn->p_dev->num_hwfns > 1)
1165                 hw_mode |= 1 << MODE_100G;
1166
1167         p_hwfn->hw_info.hw_mode = hw_mode;
1168
1169         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1170                    "Configuring function for hw_mode: 0x%08x\n",
1171                    p_hwfn->hw_info.hw_mode);
1172
1173         return ECORE_SUCCESS;
1174 }
1175
1176 #ifndef ASIC_ONLY
1177 /* MFW-replacement initializations for non-ASIC */
1178 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1179                                                struct ecore_ptt *p_ptt)
1180 {
1181         struct ecore_dev *p_dev = p_hwfn->p_dev;
1182         u32 pl_hv = 1;
1183         int i;
1184
1185         if (CHIP_REV_IS_EMUL(p_dev)) {
1186                 if (ECORE_IS_AH(p_dev))
1187                         pl_hv |= 0x600;
1188         }
1189
1190         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1191
1192         if (CHIP_REV_IS_EMUL(p_dev) &&
1193             (ECORE_IS_AH(p_dev)))
1194                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1195                          0x3ffffff);
1196
1197         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1198         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1199         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1200                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1201
1202         if (CHIP_REV_IS_EMUL(p_dev)) {
1203                 if (ECORE_IS_AH(p_dev)) {
1204                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1205                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1206                                  (p_dev->num_ports_in_engines >> 1));
1207
1208                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1209                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
1210                 }
1211         }
1212
1213         /* Poll on RBC */
1214         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1215         for (i = 0; i < 100; i++) {
1216                 OSAL_UDELAY(50);
1217                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1218                         break;
1219         }
1220         if (i == 100)
1221                 DP_NOTICE(p_hwfn, true,
1222                           "RBC done failed to complete in PSWRQ2\n");
1223
1224         return ECORE_SUCCESS;
1225 }
1226 #endif
1227
1228 /* Init run time data for all PFs and their VFs on an engine.
1229  * TBD - for VFs - Once we have parent PF info for each VF in
1230  * shmem available as CAU requires knowledge of parent PF for each VF.
1231  */
1232 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1233 {
1234         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1235         int i, igu_sb_id;
1236
1237         for_each_hwfn(p_dev, i) {
1238                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1239                 struct ecore_igu_info *p_igu_info;
1240                 struct ecore_igu_block *p_block;
1241                 struct cau_sb_entry sb_entry;
1242
1243                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1244
1245                 for (igu_sb_id = 0;
1246                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1247                      igu_sb_id++) {
1248                         p_block = &p_igu_info->entry[igu_sb_id];
1249
1250                         if (!p_block->is_pf)
1251                                 continue;
1252
1253                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1254                                                 p_block->function_id, 0, 0);
1255                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1256                                          sb_entry);
1257                 }
1258         }
1259 }
1260
1261 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1262                                        struct ecore_ptt *p_ptt)
1263 {
1264         u32 val, wr_mbs, cache_line_size;
1265
1266         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1267         switch (val) {
1268         case 0:
1269                 wr_mbs = 128;
1270                 break;
1271         case 1:
1272                 wr_mbs = 256;
1273                 break;
1274         case 2:
1275                 wr_mbs = 512;
1276                 break;
1277         default:
1278                 DP_INFO(p_hwfn,
1279                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1280                         val);
1281                 return;
1282         }
1283
1284         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1285         switch (cache_line_size) {
1286         case 32:
1287                 val = 0;
1288                 break;
1289         case 64:
1290                 val = 1;
1291                 break;
1292         case 128:
1293                 val = 2;
1294                 break;
1295         case 256:
1296                 val = 3;
1297                 break;
1298         default:
1299                 DP_INFO(p_hwfn,
1300                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1301                         cache_line_size);
1302         }
1303
1304         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1305                 DP_INFO(p_hwfn,
1306                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1307                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1308
1309         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1310         if (val > 0) {
1311                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1312                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1313         }
1314 }
1315
1316 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1317                                                  struct ecore_ptt *p_ptt,
1318                                                  int hw_mode)
1319 {
1320         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1321         struct ecore_dev *p_dev = p_hwfn->p_dev;
1322         u8 vf_id, max_num_vfs;
1323         u16 num_pfs, pf_id;
1324         u32 concrete_fid;
1325         enum _ecore_status_t rc = ECORE_SUCCESS;
1326
1327         ecore_init_cau_rt_data(p_dev);
1328
1329         /* Program GTT windows */
1330         ecore_gtt_init(p_hwfn, p_ptt);
1331
1332 #ifndef ASIC_ONLY
1333         if (CHIP_REV_IS_EMUL(p_dev)) {
1334                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1335                 if (rc != ECORE_SUCCESS)
1336                         return rc;
1337         }
1338 #endif
1339
1340         if (p_hwfn->mcp_info) {
1341                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1342                         qm_info->pf_rl_en = 1;
1343                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1344                         qm_info->pf_wfq_en = 1;
1345         }
1346
1347         ecore_qm_common_rt_init(p_hwfn,
1348                                 p_dev->num_ports_in_engines,
1349                                 qm_info->max_phys_tcs_per_port,
1350                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1351                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1352                                 qm_info->qm_port_params);
1353
1354         ecore_cxt_hw_init_common(p_hwfn);
1355
1356         ecore_init_cache_line_size(p_hwfn, p_ptt);
1357
1358         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1359         if (rc != ECORE_SUCCESS)
1360                 return rc;
1361
1362         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1363          * need to decide with which value, maybe runtime
1364          */
1365         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1366         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1367
1368         if (ECORE_IS_BB(p_dev)) {
1369                 /* Workaround clears ROCE search for all functions to prevent
1370                  * involving non initialized function in processing ROCE packet.
1371                  */
1372                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1373                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1374                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1375                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1376                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1377                 }
1378                 /* pretend to original PF */
1379                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1380         }
1381
1382         /* Workaround for avoiding CCFC execution error when getting packets
1383          * with CRC errors, and allowing instead the invoking of the FW error
1384          * handler.
1385          * This is not done inside the init tool since it currently can't
1386          * perform a pretending to VFs.
1387          */
1388         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1389         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1390                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1391                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1392                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1393                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1394                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1395                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1396         }
1397         /* pretend to original PF */
1398         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1399
1400         return rc;
1401 }
1402
1403 #ifndef ASIC_ONLY
1404 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1405 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1406
1407 #define PMEG_IF_BYTE_COUNT      8
1408
1409 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1410                              struct ecore_ptt *p_ptt,
1411                              u32 addr, u64 data, u8 reg_type, u8 port)
1412 {
1413         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1414                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1415                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1416                    (8 << PMEG_IF_BYTE_COUNT),
1417                    (reg_type << 25) | (addr << 8) | port,
1418                    (u32)((data >> 32) & 0xffffffff),
1419                    (u32)(data & 0xffffffff));
1420
1421         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1422                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1423                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1424         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1425                  (reg_type << 25) | (addr << 8) | port);
1426         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1427         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1428                  (data >> 32) & 0xffffffff);
1429 }
1430
1431 #define XLPORT_MODE_REG (0x20a)
1432 #define XLPORT_MAC_CONTROL (0x210)
1433 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1434 #define XLPORT_ENABLE_REG (0x20b)
1435
1436 #define XLMAC_CTRL (0x600)
1437 #define XLMAC_MODE (0x601)
1438 #define XLMAC_RX_MAX_SIZE (0x608)
1439 #define XLMAC_TX_CTRL (0x604)
1440 #define XLMAC_PAUSE_CTRL (0x60d)
1441 #define XLMAC_PFC_CTRL (0x60e)
1442
1443 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1444                                     struct ecore_ptt *p_ptt)
1445 {
1446         u8 loopback = 0, port = p_hwfn->port_id * 2;
1447
1448         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1449
1450         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1451         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1452                          port);
1453         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1454         /* XLMAC: SOFT RESET */
1455         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1456         /* XLMAC: Port Speed >= 10Gbps */
1457         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1458         /* XLMAC: Max Size */
1459         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1460         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1461                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1462                          0, port);
1463         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1464         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1465                          0x30ffffc000ULL, 0, port);
1466         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1467                          port); /* XLMAC: TX_EN, RX_EN */
1468         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1469         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1470                          0x1003 | (loopback << 2), 0, port);
1471         /* Enabled Parallel PFC interface */
1472         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1473
1474         /* XLPORT port enable */
1475         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1476 }
1477
1478 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1479                                        struct ecore_ptt *p_ptt)
1480 {
1481         u8 port = p_hwfn->port_id;
1482         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1483
1484         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1485
1486         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1487                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1488                  (port <<
1489                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1490                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1491
1492         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1493                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1494
1495         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1496                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1497
1498         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1499                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1500
1501         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1502                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1503
1504         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1505                  (0xA <<
1506                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1507                  (8 <<
1508                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1509
1510         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1511                  0xa853);
1512 }
1513
1514 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1515                                  struct ecore_ptt *p_ptt)
1516 {
1517         if (ECORE_IS_AH(p_hwfn->p_dev))
1518                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1519         else /* BB */
1520                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1521 }
1522
1523 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1524                                struct ecore_ptt *p_ptt,  u8 port)
1525 {
1526         int port_offset = port ? 0x800 : 0;
1527         u32 xmac_rxctrl = 0;
1528
1529         /* Reset of XMAC */
1530         /* FIXME: move to common start */
1531         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1532                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1533         OSAL_MSLEEP(1);
1534         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1535                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1536
1537         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1538
1539         /* Set the number of ports on the Warp Core to 10G */
1540         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1541
1542         /* Soft reset of XMAC */
1543         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1544                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1545         OSAL_MSLEEP(1);
1546         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1547                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1548
1549         /* FIXME: move to common end */
1550         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1551                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1552
1553         /* Set Max packet size: initialize XMAC block register for port 0 */
1554         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1555
1556         /* CRC append for Tx packets: init XMAC block register for port 1 */
1557         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1558
1559         /* Enable TX and RX: initialize XMAC block register for port 1 */
1560         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1561                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1562         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1563                                XMAC_REG_RX_CTRL_BB + port_offset);
1564         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1565         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1566 }
1567 #endif
1568
1569 static enum _ecore_status_t
1570 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1571                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1572 {
1573         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1574         u32 dpi_bit_shift, dpi_count;
1575         u32 min_dpis;
1576
1577         /* Calculate DPI size
1578          * ------------------
1579          * The PWM region contains Doorbell Pages. The first is reserverd for
1580          * the kernel for, e.g, L2. The others are free to be used by non-
1581          * trusted applications, typically from user space. Each page, called a
1582          * doorbell page is sectioned into windows that allow doorbells to be
1583          * issued in parallel by the kernel/application. The size of such a
1584          * window (a.k.a. WID) is 1kB.
1585          * Summary:
1586          *    1kB WID x N WIDS = DPI page size
1587          *    DPI page size x N DPIs = PWM region size
1588          * Notes:
1589          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1590          * in order to ensure that two applications won't share the same page.
1591          * It also must contain at least one WID per CPU to allow parallelism.
1592          * It also must be a power of 2, since it is stored as a bit shift.
1593          *
1594          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1595          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1596          * containing 4 WIDs.
1597          */
1598         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1599         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1600         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1601         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1602         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1603
1604         dpi_count = pwm_region_size / dpi_page_size;
1605
1606         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1607         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1608
1609         /* Update hwfn */
1610         p_hwfn->dpi_size = dpi_page_size;
1611         p_hwfn->dpi_count = dpi_count;
1612
1613         /* Update registers */
1614         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1615
1616         if (dpi_count < min_dpis)
1617                 return ECORE_NORESOURCES;
1618
1619         return ECORE_SUCCESS;
1620 }
1621
1622 enum ECORE_ROCE_EDPM_MODE {
1623         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1624         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1625         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1626 };
1627
1628 static enum _ecore_status_t
1629 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1630                               struct ecore_ptt *p_ptt)
1631 {
1632         u32 pwm_regsize, norm_regsize;
1633         u32 non_pwm_conn, min_addr_reg1;
1634         u32 db_bar_size, n_cpus;
1635         u32 roce_edpm_mode;
1636         u32 pf_dems_shift;
1637         enum _ecore_status_t rc = ECORE_SUCCESS;
1638         u8 cond;
1639
1640         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1641         if (p_hwfn->p_dev->num_hwfns > 1)
1642                 db_bar_size /= 2;
1643
1644         /* Calculate doorbell regions
1645          * -----------------------------------
1646          * The doorbell BAR is made of two regions. The first is called normal
1647          * region and the second is called PWM region. In the normal region
1648          * each ICID has its own set of addresses so that writing to that
1649          * specific address identifies the ICID. In the Process Window Mode
1650          * region the ICID is given in the data written to the doorbell. The
1651          * above per PF register denotes the offset in the doorbell BAR in which
1652          * the PWM region begins.
1653          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1654          * non-PWM connection. The calculation below computes the total non-PWM
1655          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1656          * in units of 4,096 bytes.
1657          */
1658         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1659             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1660                                           OSAL_NULL) +
1661             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1662         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1663         min_addr_reg1 = norm_regsize / 4096;
1664         pwm_regsize = db_bar_size - norm_regsize;
1665
1666         /* Check that the normal and PWM sizes are valid */
1667         if (db_bar_size < norm_regsize) {
1668                 DP_ERR(p_hwfn->p_dev,
1669                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1670                        db_bar_size, norm_regsize);
1671                 return ECORE_NORESOURCES;
1672         }
1673         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1674                 DP_ERR(p_hwfn->p_dev,
1675                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1676                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1677                        norm_regsize);
1678                 return ECORE_NORESOURCES;
1679         }
1680
1681         /* Calculate number of DPIs */
1682         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1683         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1684             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1685                 /* Either EDPM is mandatory, or we are attempting to allocate a
1686                  * WID per CPU.
1687                  */
1688                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1689                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1690         }
1691
1692         cond = ((rc != ECORE_SUCCESS) &&
1693                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1694                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1695         if (cond || p_hwfn->dcbx_no_edpm) {
1696                 /* Either EDPM is disabled from user configuration, or it is
1697                  * disabled via DCBx, or it is not mandatory and we failed to
1698                  * allocated a WID per CPU.
1699                  */
1700                 n_cpus = 1;
1701                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1702
1703                 /* If we entered this flow due to DCBX then the DPM register is
1704                  * already configured.
1705                  */
1706         }
1707
1708         DP_INFO(p_hwfn,
1709                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1710                 norm_regsize, pwm_regsize);
1711         DP_INFO(p_hwfn,
1712                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1713                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1714                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1715                 "disabled" : "enabled");
1716
1717         /* Check return codes from above calls */
1718         if (rc != ECORE_SUCCESS) {
1719                 DP_ERR(p_hwfn,
1720                        "Failed to allocate enough DPIs\n");
1721                 return ECORE_NORESOURCES;
1722         }
1723
1724         /* Update hwfn */
1725         p_hwfn->dpi_start_offset = norm_regsize;
1726
1727         /* Update registers */
1728         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1729         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1730         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1731         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1732
1733         return ECORE_SUCCESS;
1734 }
1735
1736 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1737                                                struct ecore_ptt *p_ptt,
1738                                                int hw_mode)
1739 {
1740         enum _ecore_status_t rc = ECORE_SUCCESS;
1741
1742         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1743                             hw_mode);
1744         if (rc != ECORE_SUCCESS)
1745                 return rc;
1746
1747         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1748
1749 #ifndef ASIC_ONLY
1750         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1751                 return ECORE_SUCCESS;
1752
1753         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1754                 if (ECORE_IS_AH(p_hwfn->p_dev))
1755                         return ECORE_SUCCESS;
1756                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1757                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1758         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1759                 if (p_hwfn->p_dev->num_hwfns > 1) {
1760                         /* Activate OPTE in CMT */
1761                         u32 val;
1762
1763                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1764                         val |= 0x10;
1765                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1766                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1767                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1768                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1769                         ecore_wr(p_hwfn, p_ptt,
1770                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1771                         ecore_wr(p_hwfn, p_ptt,
1772                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1773                         ecore_wr(p_hwfn, p_ptt,
1774                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1775                                  0x55555555);
1776                 }
1777
1778                 ecore_emul_link_init(p_hwfn, p_ptt);
1779         } else {
1780                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1781         }
1782 #endif
1783
1784         return rc;
1785 }
1786
1787 static enum _ecore_status_t
1788 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1789                  struct ecore_ptt *p_ptt,
1790                  struct ecore_tunnel_info *p_tunn,
1791                  int hw_mode,
1792                  bool b_hw_start,
1793                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1794 {
1795         u8 rel_pf_id = p_hwfn->rel_pf_id;
1796         u32 prs_reg;
1797         enum _ecore_status_t rc = ECORE_SUCCESS;
1798         u16 ctrl;
1799         int pos;
1800
1801         if (p_hwfn->mcp_info) {
1802                 struct ecore_mcp_function_info *p_info;
1803
1804                 p_info = &p_hwfn->mcp_info->func_info;
1805                 if (p_info->bandwidth_min)
1806                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1807
1808                 /* Update rate limit once we'll actually have a link */
1809                 p_hwfn->qm_info.pf_rl = 100000;
1810         }
1811         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
1812
1813         ecore_int_igu_init_rt(p_hwfn);
1814
1815         /* Set VLAN in NIG if needed */
1816         if (hw_mode & (1 << MODE_MF_SD)) {
1817                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1818                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1819                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1820                              p_hwfn->hw_info.ovlan);
1821         }
1822
1823         /* Enable classification by MAC if needed */
1824         if (hw_mode & (1 << MODE_MF_SI)) {
1825                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1826                            "Configuring TAGMAC_CLS_TYPE\n");
1827                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1828                              1);
1829         }
1830
1831         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1832         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1833                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1834         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1835                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1836         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1837
1838         /* perform debug configuration when chip is out of reset */
1839         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1840
1841         /* PF Init sequence */
1842         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1843         if (rc)
1844                 return rc;
1845
1846         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1847         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1848         if (rc)
1849                 return rc;
1850
1851         /* Pure runtime initializations - directly to the HW  */
1852         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1853
1854         /* PCI relaxed ordering causes a decrease in the performance on some
1855          * systems. Till a root cause is found, disable this attribute in the
1856          * PCI config space.
1857          */
1858         /* Not in use @DPDK
1859         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1860         * if (!pos) {
1861         *       DP_NOTICE(p_hwfn, true,
1862         *                 "Failed to find the PCIe Cap\n");
1863         *       return ECORE_IO;
1864         * }
1865         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1866         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1867         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1868         */
1869
1870         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1871         if (rc)
1872                 return rc;
1873         if (b_hw_start) {
1874                 /* enable interrupts */
1875                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1876                 if (rc != ECORE_SUCCESS)
1877                         return rc;
1878
1879                 /* send function start command */
1880                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1881                                        p_hwfn->p_dev->mf_mode,
1882                                        allow_npar_tx_switch);
1883                 if (rc) {
1884                         DP_NOTICE(p_hwfn, true,
1885                                   "Function start ramrod failed\n");
1886                 } else {
1887                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1888                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1889                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1890
1891                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1892                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1893                                          (1 << 2));
1894                                 ecore_wr(p_hwfn, p_ptt,
1895                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1896                                     0x100);
1897                         }
1898                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1899                                    "PRS_REG_SEARCH registers after start PFn\n");
1900                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1901                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1902                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1903                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1904                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1905                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1906                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1907                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1908                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1909                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1910                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1911                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1912                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1913                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1914                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1915                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1916                                    prs_reg);
1917                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1918                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1919                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1920                 }
1921         }
1922         return rc;
1923 }
1924
1925 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
1926                                                   struct ecore_ptt *p_ptt,
1927                                                   bool b_enable)
1928 {
1929         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
1930
1931         /* Configure the PF's internal FID_enable for master transactions */
1932         ecore_wr(p_hwfn, p_ptt,
1933                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1934
1935         /* Wait until value is set - try for 1 second every 50us */
1936         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1937                 val = ecore_rd(p_hwfn, p_ptt,
1938                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1939                 if (val == set_val)
1940                         break;
1941
1942                 OSAL_UDELAY(50);
1943         }
1944
1945         if (val != set_val) {
1946                 DP_NOTICE(p_hwfn, true,
1947                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1948                 return ECORE_UNKNOWN_ERROR;
1949         }
1950
1951         return ECORE_SUCCESS;
1952 }
1953
1954 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1955                                   struct ecore_ptt *p_main_ptt)
1956 {
1957         /* Read shadow of current MFW mailbox */
1958         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1959         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1960                     p_hwfn->mcp_info->mfw_mb_cur,
1961                     p_hwfn->mcp_info->mfw_mb_length);
1962 }
1963
1964 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1965                                     struct ecore_hw_init_params *p_params)
1966 {
1967         if (p_params->p_tunn) {
1968                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1969                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1970         }
1971
1972         p_hwfn->b_int_enabled = 1;
1973
1974         return ECORE_SUCCESS;
1975 }
1976
1977 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
1978                                      struct ecore_ptt *p_ptt)
1979 {
1980         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1981                  1 << p_hwfn->abs_pf_id);
1982 }
1983
1984 static void
1985 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
1986                            struct ecore_drv_load_params *p_drv_load)
1987 {
1988         /* Make sure that if ecore-client didn't provide inputs, all the
1989          * expected defaults are indeed zero.
1990          */
1991         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
1992         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
1993         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
1994
1995         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
1996
1997         if (p_drv_load != OSAL_NULL) {
1998                 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1999                                        ECORE_DRV_ROLE_KDUMP :
2000                                        ECORE_DRV_ROLE_OS;
2001                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2002                 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2003                 p_load_req->override_force_load =
2004                         p_drv_load->override_force_load;
2005         }
2006 }
2007
2008 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2009                                    struct ecore_hw_init_params *p_params)
2010 {
2011         struct ecore_load_req_params load_req_params;
2012         u32 load_code, resp, param, drv_mb_param;
2013         bool b_default_mtu = true;
2014         struct ecore_hwfn *p_hwfn;
2015         enum _ecore_status_t rc = ECORE_SUCCESS;
2016         int i;
2017
2018         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
2019             (p_dev->num_hwfns > 1)) {
2020                 DP_NOTICE(p_dev, false,
2021                           "MSI mode is not supported for CMT devices\n");
2022                 return ECORE_INVAL;
2023         }
2024
2025         if (IS_PF(p_dev)) {
2026                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2027                 if (rc != ECORE_SUCCESS)
2028                         return rc;
2029         }
2030
2031         for_each_hwfn(p_dev, i) {
2032                 p_hwfn = &p_dev->hwfns[i];
2033
2034                 /* If management didn't provide a default, set one of our own */
2035                 if (!p_hwfn->hw_info.mtu) {
2036                         p_hwfn->hw_info.mtu = 1500;
2037                         b_default_mtu = false;
2038                 }
2039
2040                 if (IS_VF(p_dev)) {
2041                         ecore_vf_start(p_hwfn, p_params);
2042                         continue;
2043                 }
2044
2045                 rc = ecore_calc_hw_mode(p_hwfn);
2046                 if (rc != ECORE_SUCCESS)
2047                         return rc;
2048
2049                 ecore_fill_load_req_params(&load_req_params,
2050                                            p_params->p_drv_load_params);
2051                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2052                                         &load_req_params);
2053                 if (rc != ECORE_SUCCESS) {
2054                         DP_NOTICE(p_hwfn, true,
2055                                   "Failed sending a LOAD_REQ command\n");
2056                         return rc;
2057                 }
2058
2059                 load_code = load_req_params.load_code;
2060                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2061                            "Load request was sent. Load code: 0x%x\n",
2062                            load_code);
2063
2064                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2065
2066                 /* CQ75580:
2067                  * When coming back from hiberbate state, the registers from
2068                  * which shadow is read initially are not initialized. It turns
2069                  * out that these registers get initialized during the call to
2070                  * ecore_mcp_load_req request. So we need to reread them here
2071                  * to get the proper shadow register value.
2072                  * Note: This is a workaround for the missing MFW
2073                  * initialization. It may be removed once the implementation
2074                  * is done.
2075                  */
2076                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2077
2078                 /* Only relevant for recovery:
2079                  * Clear the indication after the LOAD_REQ command is responded
2080                  * by the MFW.
2081                  */
2082                 p_dev->recov_in_prog = false;
2083
2084                 p_hwfn->first_on_engine = (load_code ==
2085                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2086
2087                 if (!qm_lock_init) {
2088                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2089                         qm_lock_init = true;
2090                 }
2091
2092                 /* Clean up chip from previous driver if such remains exist.
2093                  * This is not needed when the PF is the first one on the
2094                  * engine, since afterwards we are going to init the FW.
2095                  */
2096                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2097                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2098                                                  p_hwfn->rel_pf_id, false);
2099                         if (rc != ECORE_SUCCESS) {
2100                                 ecore_hw_err_notify(p_hwfn,
2101                                                     ECORE_HW_ERR_RAMROD_FAIL);
2102                                 goto load_err;
2103                         }
2104                 }
2105
2106                 /* Log and clean previous pglue_b errors if such exist */
2107                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2108                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2109
2110                 /* Enable the PF's internal FID_enable in the PXP */
2111                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2112                                                   true);
2113                 if (rc != ECORE_SUCCESS)
2114                         goto load_err;
2115
2116                 switch (load_code) {
2117                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2118                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2119                                                   p_hwfn->hw_info.hw_mode);
2120                         if (rc != ECORE_SUCCESS)
2121                                 break;
2122                         /* Fall into */
2123                 case FW_MSG_CODE_DRV_LOAD_PORT:
2124                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2125                                                 p_hwfn->hw_info.hw_mode);
2126                         if (rc != ECORE_SUCCESS)
2127                                 break;
2128                         /* Fall into */
2129                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2130                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2131                                               p_params->p_tunn,
2132                                               p_hwfn->hw_info.hw_mode,
2133                                               p_params->b_hw_start,
2134                                               p_params->int_mode,
2135                                               p_params->allow_npar_tx_switch);
2136                         break;
2137                 default:
2138                         DP_NOTICE(p_hwfn, false,
2139                                   "Unexpected load code [0x%08x]", load_code);
2140                         rc = ECORE_NOTIMPL;
2141                         break;
2142                 }
2143
2144                 if (rc != ECORE_SUCCESS) {
2145                         DP_NOTICE(p_hwfn, true,
2146                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2147                                   load_code, rc);
2148                         goto load_err;
2149                 }
2150
2151                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2152                 if (rc != ECORE_SUCCESS)
2153                         return rc;
2154
2155                 /* send DCBX attention request command */
2156                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2157                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2158                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2159                                    DRV_MSG_CODE_SET_DCBX,
2160                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, &resp,
2161                                    &param);
2162                 if (rc != ECORE_SUCCESS) {
2163                         DP_NOTICE(p_hwfn, true,
2164                                   "Failed to send DCBX attention request\n");
2165                         return rc;
2166                 }
2167
2168                 p_hwfn->hw_init_done = true;
2169         }
2170
2171         if (IS_PF(p_dev)) {
2172                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2173                 drv_mb_param = STORM_FW_VERSION;
2174                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2175                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2176                                    drv_mb_param, &resp, &param);
2177                 if (rc != ECORE_SUCCESS)
2178                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2179
2180                 if (!b_default_mtu)
2181                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2182                                                       p_hwfn->hw_info.mtu);
2183                 if (rc != ECORE_SUCCESS)
2184                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2185
2186                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2187                                                       p_hwfn->p_main_ptt,
2188                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2189                 if (rc != ECORE_SUCCESS)
2190                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2191         }
2192
2193         return rc;
2194
2195 load_err:
2196         /* The MFW load lock should be released regardless of success or failure
2197          * of initialization.
2198          * TODO: replace this with an attempt to send cancel_load.
2199          */
2200         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2201         return rc;
2202 }
2203
2204 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2205 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2206                                  struct ecore_hwfn *p_hwfn,
2207                                  struct ecore_ptt *p_ptt)
2208 {
2209         int i;
2210
2211         /* close timers */
2212         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2213         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2214         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2215                                                                         i++) {
2216                 if ((!ecore_rd(p_hwfn, p_ptt,
2217                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2218                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2219                         break;
2220
2221                 /* Dependent on number of connection/tasks, possibly
2222                  * 1ms sleep is required between polls
2223                  */
2224                 OSAL_MSLEEP(1);
2225         }
2226
2227         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2228                 return;
2229
2230         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2231                   " [Connection %02x Tasks %02x]\n",
2232                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2233                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2234 }
2235
2236 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2237 {
2238         int j;
2239
2240         for_each_hwfn(p_dev, j) {
2241                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2242                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2243
2244                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2245         }
2246 }
2247
2248 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2249                                                  struct ecore_ptt *p_ptt,
2250                                                  u32 addr, u32 expected_val)
2251 {
2252         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2253
2254         if (val != expected_val) {
2255                 DP_NOTICE(p_hwfn, true,
2256                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2257                           addr, val, expected_val);
2258                 return ECORE_UNKNOWN_ERROR;
2259         }
2260
2261         return ECORE_SUCCESS;
2262 }
2263
2264 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2265 {
2266         struct ecore_hwfn *p_hwfn;
2267         struct ecore_ptt *p_ptt;
2268         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2269         int j;
2270
2271         for_each_hwfn(p_dev, j) {
2272                 p_hwfn = &p_dev->hwfns[j];
2273                 p_ptt = p_hwfn->p_main_ptt;
2274
2275                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2276
2277                 if (IS_VF(p_dev)) {
2278                         ecore_vf_pf_int_cleanup(p_hwfn);
2279                         rc = ecore_vf_pf_reset(p_hwfn);
2280                         if (rc != ECORE_SUCCESS) {
2281                                 DP_NOTICE(p_hwfn, true,
2282                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2283                                           rc);
2284                                 rc2 = ECORE_UNKNOWN_ERROR;
2285                         }
2286                         continue;
2287                 }
2288
2289                 /* mark the hw as uninitialized... */
2290                 p_hwfn->hw_init_done = false;
2291
2292                 /* Send unload command to MCP */
2293                 if (!p_dev->recov_in_prog) {
2294                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2295                         if (rc != ECORE_SUCCESS) {
2296                                 DP_NOTICE(p_hwfn, true,
2297                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2298                                           rc);
2299                                 rc2 = ECORE_UNKNOWN_ERROR;
2300                         }
2301                 }
2302
2303                 OSAL_DPC_SYNC(p_hwfn);
2304
2305                 /* After this point no MFW attentions are expected, e.g. prevent
2306                  * race between pf stop and dcbx pf update.
2307                  */
2308
2309                 rc = ecore_sp_pf_stop(p_hwfn);
2310                 if (rc != ECORE_SUCCESS) {
2311                         DP_NOTICE(p_hwfn, true,
2312                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2313                                   rc);
2314                         rc2 = ECORE_UNKNOWN_ERROR;
2315                 }
2316
2317                 /* perform debug action after PF stop was sent */
2318                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2319
2320                 /* close NIG to BRB gate */
2321                 ecore_wr(p_hwfn, p_ptt,
2322                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2323
2324                 /* close parser */
2325                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2326                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2327                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2328                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2329                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2330
2331                 /* @@@TBD - clean transmission queues (5.b) */
2332                 /* @@@TBD - clean BTB (5.c) */
2333
2334                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2335
2336                 /* @@@TBD - verify DMAE requests are done (8) */
2337
2338                 /* Disable Attention Generation */
2339                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2340                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2341                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2342                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2343                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2344                 if (rc != ECORE_SUCCESS) {
2345                         DP_NOTICE(p_hwfn, true,
2346                                   "Failed to return IGU CAM to default\n");
2347                         rc2 = ECORE_UNKNOWN_ERROR;
2348                 }
2349
2350                 /* Need to wait 1ms to guarantee SBs are cleared */
2351                 OSAL_MSLEEP(1);
2352
2353                 if (!p_dev->recov_in_prog) {
2354                         ecore_verify_reg_val(p_hwfn, p_ptt,
2355                                              QM_REG_USG_CNT_PF_TX, 0);
2356                         ecore_verify_reg_val(p_hwfn, p_ptt,
2357                                              QM_REG_USG_CNT_PF_OTHER, 0);
2358                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2359                 }
2360
2361                 /* Disable PF in HW blocks */
2362                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2363                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2364
2365                 if (!p_dev->recov_in_prog) {
2366                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2367                         if (rc != ECORE_SUCCESS) {
2368                                 DP_NOTICE(p_hwfn, true,
2369                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2370                                           rc);
2371                                 rc2 = ECORE_UNKNOWN_ERROR;
2372                         }
2373                 }
2374         } /* hwfn loop */
2375
2376         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2377                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2378                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2379
2380                  /* Clear the PF's internal FID_enable in the PXP.
2381                   * In CMT this should only be done for first hw-function, and
2382                   * only after all transactions have stopped for all active
2383                   * hw-functions.
2384                   */
2385                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2386                                                   false);
2387                 if (rc != ECORE_SUCCESS) {
2388                         DP_NOTICE(p_hwfn, true,
2389                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2390                                   rc);
2391                         rc2 = ECORE_UNKNOWN_ERROR;
2392                 }
2393         }
2394
2395         return rc2;
2396 }
2397
2398 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2399 {
2400         int j;
2401
2402         for_each_hwfn(p_dev, j) {
2403                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2404                 struct ecore_ptt *p_ptt;
2405
2406                 if (IS_VF(p_dev)) {
2407                         ecore_vf_pf_int_cleanup(p_hwfn);
2408                         continue;
2409                 }
2410                 p_ptt = ecore_ptt_acquire(p_hwfn);
2411                 if (!p_ptt)
2412                         return ECORE_AGAIN;
2413
2414                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2415                            "Shutting down the fastpath\n");
2416
2417                 ecore_wr(p_hwfn, p_ptt,
2418                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2419
2420                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2421                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2422                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2423                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2424                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2425
2426                 /* @@@TBD - clean transmission queues (5.b) */
2427                 /* @@@TBD - clean BTB (5.c) */
2428
2429                 /* @@@TBD - verify DMAE requests are done (8) */
2430
2431                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2432                 /* Need to wait 1ms to guarantee SBs are cleared */
2433                 OSAL_MSLEEP(1);
2434                 ecore_ptt_release(p_hwfn, p_ptt);
2435         }
2436
2437         return ECORE_SUCCESS;
2438 }
2439
2440 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2441 {
2442         struct ecore_ptt *p_ptt;
2443
2444         if (IS_VF(p_hwfn->p_dev))
2445                 return ECORE_SUCCESS;
2446
2447         p_ptt = ecore_ptt_acquire(p_hwfn);
2448         if (!p_ptt)
2449                 return ECORE_AGAIN;
2450
2451         /* If roce info is allocated it means roce is initialized and should
2452          * be enabled in searcher.
2453          */
2454         if (p_hwfn->p_rdma_info) {
2455                 if (p_hwfn->b_rdma_enabled_in_prs)
2456                         ecore_wr(p_hwfn, p_ptt,
2457                                  p_hwfn->rdma_prs_search_reg, 0x1);
2458                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2459         }
2460
2461         /* Re-open incoming traffic */
2462         ecore_wr(p_hwfn, p_ptt,
2463                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2464         ecore_ptt_release(p_hwfn, p_ptt);
2465
2466         return ECORE_SUCCESS;
2467 }
2468
2469 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2470 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2471 {
2472         ecore_ptt_pool_free(p_hwfn);
2473         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2474 }
2475
2476 /* Setup bar access */
2477 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2478 {
2479         /* clear indirect access */
2480         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2481                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2482                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2483                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2484                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2485                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2486                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2487                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2488                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2489         } else {
2490                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2491                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2492                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2493                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2494                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2495                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2496                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2497                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2498         }
2499
2500         /* Clean previous pglue_b errors if such exist */
2501         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2502
2503         /* enable internal target-read */
2504         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2505                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2506 }
2507
2508 static void get_function_id(struct ecore_hwfn *p_hwfn)
2509 {
2510         /* ME Register */
2511         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2512                                                   PXP_PF_ME_OPAQUE_ADDR);
2513
2514         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2515
2516         /* Bits 16-19 from the ME registers are the pf_num */
2517         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2518         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2519                                       PXP_CONCRETE_FID_PFID);
2520         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2521                                     PXP_CONCRETE_FID_PORT);
2522
2523         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2524                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2525                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2526 }
2527
2528 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2529 {
2530         u32 *feat_num = p_hwfn->hw_info.feat_num;
2531         struct ecore_sb_cnt_info sb_cnt;
2532         u32 non_l2_sbs = 0;
2533
2534         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2535         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2536
2537         /* L2 Queues require each: 1 status block. 1 L2 queue */
2538         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2539                 /* Start by allocating VF queues, then PF's */
2540                 feat_num[ECORE_VF_L2_QUE] =
2541                         OSAL_MIN_T(u32,
2542                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2543                                    sb_cnt.iov_cnt);
2544                 feat_num[ECORE_PF_L2_QUE] =
2545                         OSAL_MIN_T(u32,
2546                                    sb_cnt.cnt - non_l2_sbs,
2547                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2548                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2549         }
2550
2551         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2552                                              RESC_NUM(p_hwfn,
2553                                                       ECORE_CMDQS_CQS));
2554         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2555                                               RESC_NUM(p_hwfn,
2556                                                        ECORE_CMDQS_CQS));
2557
2558         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2559                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2560                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2561                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2562                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2563                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2564                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2565                    (int)sb_cnt.cnt);
2566 }
2567
2568 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2569 {
2570         switch (res_id) {
2571         case ECORE_L2_QUEUE:
2572                 return "L2_QUEUE";
2573         case ECORE_VPORT:
2574                 return "VPORT";
2575         case ECORE_RSS_ENG:
2576                 return "RSS_ENG";
2577         case ECORE_PQ:
2578                 return "PQ";
2579         case ECORE_RL:
2580                 return "RL";
2581         case ECORE_MAC:
2582                 return "MAC";
2583         case ECORE_VLAN:
2584                 return "VLAN";
2585         case ECORE_RDMA_CNQ_RAM:
2586                 return "RDMA_CNQ_RAM";
2587         case ECORE_ILT:
2588                 return "ILT";
2589         case ECORE_LL2_QUEUE:
2590                 return "LL2_QUEUE";
2591         case ECORE_CMDQS_CQS:
2592                 return "CMDQS_CQS";
2593         case ECORE_RDMA_STATS_QUEUE:
2594                 return "RDMA_STATS_QUEUE";
2595         case ECORE_BDQ:
2596                 return "BDQ";
2597         case ECORE_SB:
2598                 return "SB";
2599         default:
2600                 return "UNKNOWN_RESOURCE";
2601         }
2602 }
2603
2604 static enum _ecore_status_t
2605 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2606                               struct ecore_ptt *p_ptt,
2607                               enum ecore_resources res_id,
2608                               u32 resc_max_val,
2609                               u32 *p_mcp_resp)
2610 {
2611         enum _ecore_status_t rc;
2612
2613         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2614                                         resc_max_val, p_mcp_resp);
2615         if (rc != ECORE_SUCCESS) {
2616                 DP_NOTICE(p_hwfn, true,
2617                           "MFW response failure for a max value setting of resource %d [%s]\n",
2618                           res_id, ecore_hw_get_resc_name(res_id));
2619                 return rc;
2620         }
2621
2622         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2623                 DP_INFO(p_hwfn,
2624                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2625                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2626
2627         return ECORE_SUCCESS;
2628 }
2629
2630 static enum _ecore_status_t
2631 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2632                             struct ecore_ptt *p_ptt)
2633 {
2634         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2635         u32 resc_max_val, mcp_resp;
2636         u8 res_id;
2637         enum _ecore_status_t rc;
2638
2639         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2640                 /* @DPDK */
2641                 switch (res_id) {
2642                 case ECORE_LL2_QUEUE:
2643                 case ECORE_RDMA_CNQ_RAM:
2644                 case ECORE_RDMA_STATS_QUEUE:
2645                 case ECORE_BDQ:
2646                         resc_max_val = 0;
2647                         break;
2648                 default:
2649                         continue;
2650                 }
2651
2652                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2653                                                    resc_max_val, &mcp_resp);
2654                 if (rc != ECORE_SUCCESS)
2655                         return rc;
2656
2657                 /* There's no point to continue to the next resource if the
2658                  * command is not supported by the MFW.
2659                  * We do continue if the command is supported but the resource
2660                  * is unknown to the MFW. Such a resource will be later
2661                  * configured with the default allocation values.
2662                  */
2663                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2664                         return ECORE_NOTIMPL;
2665         }
2666
2667         return ECORE_SUCCESS;
2668 }
2669
2670 static
2671 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2672                                             enum ecore_resources res_id,
2673                                             u32 *p_resc_num, u32 *p_resc_start)
2674 {
2675         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2676         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2677
2678         switch (res_id) {
2679         case ECORE_L2_QUEUE:
2680                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2681                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2682                 break;
2683         case ECORE_VPORT:
2684                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2685                                  MAX_NUM_VPORTS_BB) / num_funcs;
2686                 break;
2687         case ECORE_RSS_ENG:
2688                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2689                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2690                 break;
2691         case ECORE_PQ:
2692                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2693                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2694                 break;
2695         case ECORE_RL:
2696                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2697                 break;
2698         case ECORE_MAC:
2699         case ECORE_VLAN:
2700                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2701                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2702                 break;
2703         case ECORE_ILT:
2704                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2705                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2706                 break;
2707         case ECORE_LL2_QUEUE:
2708                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2709                 break;
2710         case ECORE_RDMA_CNQ_RAM:
2711         case ECORE_CMDQS_CQS:
2712                 /* CNQ/CMDQS are the same resource */
2713                 /* @DPDK */
2714                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2715                 break;
2716         case ECORE_RDMA_STATS_QUEUE:
2717                 /* @DPDK */
2718                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2719                                  MAX_NUM_VPORTS_BB) / num_funcs;
2720                 break;
2721         case ECORE_BDQ:
2722                 /* @DPDK */
2723                 *p_resc_num = 0;
2724                 break;
2725         default:
2726                 break;
2727         }
2728
2729
2730         switch (res_id) {
2731         case ECORE_BDQ:
2732                 if (!*p_resc_num)
2733                         *p_resc_start = 0;
2734                 break;
2735         case ECORE_SB:
2736                 /* Since we want its value to reflect whether MFW supports
2737                  * the new scheme, have a default of 0.
2738                  */
2739                 *p_resc_num = 0;
2740                 break;
2741         default:
2742                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2743                 break;
2744         }
2745
2746         return ECORE_SUCCESS;
2747 }
2748
2749 static enum _ecore_status_t
2750 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
2751                          bool drv_resc_alloc)
2752 {
2753         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2754         u32 mcp_resp, *p_resc_num, *p_resc_start;
2755         enum _ecore_status_t rc;
2756
2757         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2758         p_resc_start = &RESC_START(p_hwfn, res_id);
2759
2760         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2761                                     &dflt_resc_start);
2762         if (rc != ECORE_SUCCESS) {
2763                 DP_ERR(p_hwfn,
2764                        "Failed to get default amount for resource %d [%s]\n",
2765                         res_id, ecore_hw_get_resc_name(res_id));
2766                 return rc;
2767         }
2768
2769 #ifndef ASIC_ONLY
2770         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2771                 *p_resc_num = dflt_resc_num;
2772                 *p_resc_start = dflt_resc_start;
2773                 goto out;
2774         }
2775 #endif
2776
2777         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2778                                      &mcp_resp, p_resc_num, p_resc_start);
2779         if (rc != ECORE_SUCCESS) {
2780                 DP_NOTICE(p_hwfn, true,
2781                           "MFW response failure for an allocation request for"
2782                           " resource %d [%s]\n",
2783                           res_id, ecore_hw_get_resc_name(res_id));
2784                 return rc;
2785         }
2786
2787         /* Default driver values are applied in the following cases:
2788          * - The resource allocation MB command is not supported by the MFW
2789          * - There is an internal error in the MFW while processing the request
2790          * - The resource ID is unknown to the MFW
2791          */
2792         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2793                 DP_INFO(p_hwfn,
2794                         "Failed to receive allocation info for resource %d [%s]."
2795                         " mcp_resp = 0x%x. Applying default values"
2796                         " [%d,%d].\n",
2797                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2798                         dflt_resc_num, dflt_resc_start);
2799
2800                 *p_resc_num = dflt_resc_num;
2801                 *p_resc_start = dflt_resc_start;
2802                 goto out;
2803         }
2804
2805         if ((*p_resc_num != dflt_resc_num ||
2806              *p_resc_start != dflt_resc_start) &&
2807             res_id != ECORE_SB) {
2808                 DP_INFO(p_hwfn,
2809                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
2810                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2811                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2812                         drv_resc_alloc ? " - Applying default values" : "");
2813                 if (drv_resc_alloc) {
2814                         *p_resc_num = dflt_resc_num;
2815                         *p_resc_start = dflt_resc_start;
2816                 }
2817         }
2818 out:
2819         return ECORE_SUCCESS;
2820 }
2821
2822 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2823                                                    bool drv_resc_alloc)
2824 {
2825         enum _ecore_status_t rc;
2826         u8 res_id;
2827
2828         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2829                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2830                 if (rc != ECORE_SUCCESS)
2831                         return rc;
2832         }
2833
2834         return ECORE_SUCCESS;
2835 }
2836
2837 #define ECORE_RESC_ALLOC_LOCK_RETRY_CNT         10
2838 #define ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US    10000 /* 10 msec */
2839
2840 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2841                                               struct ecore_ptt *p_ptt,
2842                                               bool drv_resc_alloc)
2843 {
2844         struct ecore_resc_unlock_params resc_unlock_params;
2845         struct ecore_resc_lock_params resc_lock_params;
2846         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2847         u8 res_id;
2848         enum _ecore_status_t rc;
2849 #ifndef ASIC_ONLY
2850         u32 *resc_start = p_hwfn->hw_info.resc_start;
2851         u32 *resc_num = p_hwfn->hw_info.resc_num;
2852         /* For AH, an equal share of the ILT lines between the maximal number of
2853          * PFs is not enough for RoCE. This would be solved by the future
2854          * resource allocation scheme, but isn't currently present for
2855          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2856          * to work - the BB number of ILT lines divided by its max PFs number.
2857          */
2858         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2859 #endif
2860
2861         /* Setting the max values of the soft resources and the following
2862          * resources allocation queries should be atomic. Since several PFs can
2863          * run in parallel - a resource lock is needed.
2864          * If either the resource lock or resource set value commands are not
2865          * supported - skip the the max values setting, release the lock if
2866          * needed, and proceed to the queries. Other failures, including a
2867          * failure to acquire the lock, will cause this function to fail.
2868          * Old drivers that don't acquire the lock can run in parallel, and
2869          * their allocation values won't be affected by the updated max values.
2870          */
2871         OSAL_MEM_ZERO(&resc_lock_params, sizeof(resc_lock_params));
2872         resc_lock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2873         resc_lock_params.retry_num = ECORE_RESC_ALLOC_LOCK_RETRY_CNT;
2874         resc_lock_params.retry_interval = ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2875         resc_lock_params.sleep_b4_retry = true;
2876         OSAL_MEM_ZERO(&resc_unlock_params, sizeof(resc_unlock_params));
2877         resc_unlock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2878
2879         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2880         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2881                 return rc;
2882         } else if (rc == ECORE_NOTIMPL) {
2883                 DP_INFO(p_hwfn,
2884                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2885         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
2886                 DP_NOTICE(p_hwfn, false,
2887                           "Failed to acquire the resource lock for the resource allocation commands\n");
2888                 rc = ECORE_BUSY;
2889                 goto unlock_and_exit;
2890         } else {
2891                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
2892                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2893                         DP_NOTICE(p_hwfn, false,
2894                                   "Failed to set the max values of the soft resources\n");
2895                         goto unlock_and_exit;
2896                 } else if (rc == ECORE_NOTIMPL) {
2897                         DP_INFO(p_hwfn,
2898                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2899                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
2900                                                    &resc_unlock_params);
2901                         if (rc != ECORE_SUCCESS)
2902                                 DP_INFO(p_hwfn,
2903                                         "Failed to release the resource lock for the resource allocation commands\n");
2904                 }
2905         }
2906
2907         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
2908         if (rc != ECORE_SUCCESS)
2909                 goto unlock_and_exit;
2910
2911         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2912                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
2913                                            &resc_unlock_params);
2914                 if (rc != ECORE_SUCCESS)
2915                         DP_INFO(p_hwfn,
2916                                 "Failed to release the resource lock for the resource allocation commands\n");
2917         }
2918
2919 #ifndef ASIC_ONLY
2920         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2921                 /* Reduced build contains less PQs */
2922                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2923                         resc_num[ECORE_PQ] = 32;
2924                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2925                             p_hwfn->enabled_func_idx;
2926                 }
2927
2928                 /* For AH emulation, since we have a possible maximal number of
2929                  * 16 enabled PFs, in case there are not enough ILT lines -
2930                  * allocate only first PF as RoCE and have all the other ETH
2931                  * only with less ILT lines.
2932                  */
2933                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2934                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2935                                                          resc_num[ECORE_ILT],
2936                                                          roce_min_ilt_lines);
2937         }
2938
2939         /* Correct the common ILT calculation if PF0 has more */
2940         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2941             p_hwfn->p_dev->b_is_emul_full &&
2942             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2943                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2944                     resc_num[ECORE_ILT];
2945 #endif
2946
2947         /* Sanity for ILT */
2948         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2949             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2950                 DP_NOTICE(p_hwfn, true,
2951                           "Can't assign ILT pages [%08x,...,%08x]\n",
2952                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2953                                                                   ECORE_ILT) -
2954                           1);
2955                 return ECORE_INVAL;
2956         }
2957
2958         /* This will also learn the number of SBs from MFW */
2959         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
2960                 return ECORE_INVAL;
2961
2962         ecore_hw_set_feat(p_hwfn);
2963
2964         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2965                    "The numbers for each resource are:\n");
2966         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2967                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2968                            ecore_hw_get_resc_name(res_id),
2969                            RESC_NUM(p_hwfn, res_id),
2970                            RESC_START(p_hwfn, res_id));
2971
2972         return ECORE_SUCCESS;
2973
2974 unlock_and_exit:
2975         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2976                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
2977                                       &resc_unlock_params);
2978         return rc;
2979 }
2980
2981 static enum _ecore_status_t
2982 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2983                       struct ecore_ptt *p_ptt,
2984                       struct ecore_hw_prepare_params *p_params)
2985 {
2986         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2987         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2988         struct ecore_mcp_link_capabilities *p_caps;
2989         struct ecore_mcp_link_params *link;
2990         enum _ecore_status_t rc;
2991
2992         /* Read global nvm_cfg address */
2993         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2994
2995         /* Verify MCP has initialized it */
2996         if (!nvm_cfg_addr) {
2997                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2998                 if (p_params->b_relaxed_probe)
2999                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3000                 return ECORE_INVAL;
3001         }
3002
3003 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3004
3005         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3006
3007         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3008             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
3009                                                        core_cfg);
3010
3011         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3012
3013         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3014                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3015         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3016                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3017                 break;
3018         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3019                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3020                 break;
3021         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3022                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3023                 break;
3024         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3025                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3026                 break;
3027         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3028                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3029                 break;
3030         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3031                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3032                 break;
3033         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3034                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3035                 break;
3036         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3037                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3038                 break;
3039         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3040                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3041                 break;
3042         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3043                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3044                 break;
3045         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3046                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3047                 break;
3048         default:
3049                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3050                           core_cfg);
3051                 break;
3052         }
3053
3054         /* Read DCBX configuration */
3055         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3056                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3057         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3058                              port_cfg_addr +
3059                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3060         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3061                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3062         switch (dcbx_mode) {
3063         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3064                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3065                 break;
3066         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3067                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3068                 break;
3069         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3070                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3071                 break;
3072         default:
3073                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3074         }
3075
3076         /* Read default link configuration */
3077         link = &p_hwfn->mcp_info->link_input;
3078         p_caps = &p_hwfn->mcp_info->link_capabilities;
3079         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3080             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3081         link_temp = ecore_rd(p_hwfn, p_ptt,
3082                              port_cfg_addr +
3083                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3084         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3085         link->speed.advertised_speeds = link_temp;
3086         p_caps->speed_capabilities = link->speed.advertised_speeds;
3087
3088         link_temp = ecore_rd(p_hwfn, p_ptt,
3089                              port_cfg_addr +
3090                              OFFSETOF(struct nvm_cfg1_port, link_settings));
3091         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3092                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3093         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3094                 link->speed.autoneg = true;
3095                 break;
3096         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3097                 link->speed.forced_speed = 1000;
3098                 break;
3099         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3100                 link->speed.forced_speed = 10000;
3101                 break;
3102         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3103                 link->speed.forced_speed = 25000;
3104                 break;
3105         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3106                 link->speed.forced_speed = 40000;
3107                 break;
3108         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3109                 link->speed.forced_speed = 50000;
3110                 break;
3111         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3112                 link->speed.forced_speed = 100000;
3113                 break;
3114         default:
3115                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3116         }
3117
3118         p_caps->default_speed = link->speed.forced_speed;
3119         p_caps->default_speed_autoneg = link->speed.autoneg;
3120
3121         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3122         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3123         link->pause.autoneg = !!(link_temp &
3124                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3125         link->pause.forced_rx = !!(link_temp &
3126                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3127         link->pause.forced_tx = !!(link_temp &
3128                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3129         link->loopback_mode = 0;
3130
3131         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3132                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3133                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3134                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3135                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3136                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3137                 link->eee.enable = true;
3138                 switch (link_temp) {
3139                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3140                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3141                         link->eee.enable = false;
3142                         break;
3143                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3144                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3145                         break;
3146                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3147                         p_caps->eee_lpi_timer =
3148                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3149                         break;
3150                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3151                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3152                         break;
3153                 }
3154
3155                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3156                 link->eee.tx_lpi_enable = link->eee.enable;
3157                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3158         } else {
3159                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3160         }
3161
3162         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3163                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3164                    link->speed.forced_speed, link->speed.advertised_speeds,
3165                    link->speed.autoneg, link->pause.autoneg,
3166                    p_caps->default_eee, p_caps->eee_lpi_timer);
3167
3168         /* Read Multi-function information from shmem */
3169         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3170             OFFSETOF(struct nvm_cfg1, glob) +
3171             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3172
3173         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3174
3175         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3176             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3177
3178         switch (mf_mode) {
3179         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3180                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3181                 break;
3182         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3183                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3184                 break;
3185         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3186                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3187                 break;
3188         }
3189         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3190                 p_hwfn->p_dev->mf_mode);
3191
3192         /* Read Multi-function information from shmem */
3193         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3194             OFFSETOF(struct nvm_cfg1, glob) +
3195             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3196
3197         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3198         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3199                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3200                              &p_hwfn->hw_info.device_capabilities);
3201         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3202                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3203                              &p_hwfn->hw_info.device_capabilities);
3204         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3205                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3206                              &p_hwfn->hw_info.device_capabilities);
3207         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3208                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3209                              &p_hwfn->hw_info.device_capabilities);
3210         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3211                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3212                              &p_hwfn->hw_info.device_capabilities);
3213
3214         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3215         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3216                 rc = ECORE_SUCCESS;
3217                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3218         }
3219
3220         return rc;
3221 }
3222
3223 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3224                                 struct ecore_ptt *p_ptt)
3225 {
3226         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3227         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3228         struct ecore_dev *p_dev = p_hwfn->p_dev;
3229
3230         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3231
3232         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3233          * in the other bits are selected.
3234          * Bits 1-15 are for functions 1-15, respectively, and their value is
3235          * '0' only for enabled functions (function 0 always exists and
3236          * enabled).
3237          * In case of CMT in BB, only the "even" functions are enabled, and thus
3238          * the number of functions for both hwfns is learnt from the same bits.
3239          */
3240         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3241                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3242                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3243         } else { /* E5 */
3244                 reg_function_hide = 0;
3245         }
3246
3247         if (reg_function_hide & 0x1) {
3248                 if (ECORE_IS_BB(p_dev)) {
3249                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3250                                 num_funcs = 0;
3251                                 eng_mask = 0xaaaa;
3252                         } else {
3253                                 num_funcs = 1;
3254                                 eng_mask = 0x5554;
3255                         }
3256                 } else {
3257                         num_funcs = 1;
3258                         eng_mask = 0xfffe;
3259                 }
3260
3261                 /* Get the number of the enabled functions on the engine */
3262                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3263                 while (tmp) {
3264                         if (tmp & 0x1)
3265                                 num_funcs++;
3266                         tmp >>= 0x1;
3267                 }
3268
3269                 /* Get the PF index within the enabled functions */
3270                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3271                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3272                 while (tmp) {
3273                         if (tmp & 0x1)
3274                                 enabled_func_idx--;
3275                         tmp >>= 0x1;
3276                 }
3277         }
3278
3279         p_hwfn->num_funcs_on_engine = num_funcs;
3280         p_hwfn->enabled_func_idx = enabled_func_idx;
3281
3282 #ifndef ASIC_ONLY
3283         if (CHIP_REV_IS_FPGA(p_dev)) {
3284                 DP_NOTICE(p_hwfn, false,
3285                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3286                 p_hwfn->num_funcs_on_engine = 4;
3287         }
3288 #endif
3289
3290         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3291                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3292                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3293                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3294 }
3295
3296 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3297                                       struct ecore_ptt *p_ptt)
3298 {
3299         u32 port_mode;
3300
3301 #ifndef ASIC_ONLY
3302         /* Read the port mode */
3303         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3304                 port_mode = 4;
3305         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3306                  (p_hwfn->p_dev->num_hwfns > 1))
3307                 /* In CMT on emulation, assume 1 port */
3308                 port_mode = 1;
3309         else
3310 #endif
3311         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3312
3313         if (port_mode < 3) {
3314                 p_hwfn->p_dev->num_ports_in_engines = 1;
3315         } else if (port_mode <= 5) {
3316                 p_hwfn->p_dev->num_ports_in_engines = 2;
3317         } else {
3318                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3319                           p_hwfn->p_dev->num_ports_in_engines);
3320
3321                 /* Default num_ports_in_engines to something */
3322                 p_hwfn->p_dev->num_ports_in_engines = 1;
3323         }
3324 }
3325
3326 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3327                                          struct ecore_ptt *p_ptt)
3328 {
3329         u32 port;
3330         int i;
3331
3332         p_hwfn->p_dev->num_ports_in_engines = 0;
3333
3334 #ifndef ASIC_ONLY
3335         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3336                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3337                 switch ((port & 0xf000) >> 12) {
3338                 case 1:
3339                         p_hwfn->p_dev->num_ports_in_engines = 1;
3340                         break;
3341                 case 3:
3342                         p_hwfn->p_dev->num_ports_in_engines = 2;
3343                         break;
3344                 case 0xf:
3345                         p_hwfn->p_dev->num_ports_in_engines = 4;
3346                         break;
3347                 default:
3348                         DP_NOTICE(p_hwfn, false,
3349                                   "Unknown port mode in ECO_RESERVED %08x\n",
3350                                   port);
3351                 }
3352         } else
3353 #endif
3354                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3355                         port = ecore_rd(p_hwfn, p_ptt,
3356                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3357                                         (i * 4));
3358                         if (port & 1)
3359                                 p_hwfn->p_dev->num_ports_in_engines++;
3360                 }
3361 }
3362
3363 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3364                                    struct ecore_ptt *p_ptt)
3365 {
3366         if (ECORE_IS_BB(p_hwfn->p_dev))
3367                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3368         else
3369                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3370 }
3371
3372 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3373                                    struct ecore_ptt *p_ptt)
3374 {
3375         struct ecore_mcp_link_capabilities *p_caps;
3376         u32 eee_status;
3377
3378         p_caps = &p_hwfn->mcp_info->link_capabilities;
3379         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3380                 return;
3381
3382         p_caps->eee_speed_caps = 0;
3383         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3384                               OFFSETOF(struct public_port, eee_status));
3385         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3386                         EEE_SUPPORTED_SPEED_OFFSET;
3387         if (eee_status & EEE_1G_SUPPORTED)
3388                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3389         if (eee_status & EEE_10G_ADV)
3390                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3391 }
3392
3393 static enum _ecore_status_t
3394 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3395                   enum ecore_pci_personality personality,
3396                   struct ecore_hw_prepare_params *p_params)
3397 {
3398         bool drv_resc_alloc = p_params->drv_resc_alloc;
3399         enum _ecore_status_t rc;
3400
3401         /* Since all information is common, only first hwfns should do this */
3402         if (IS_LEAD_HWFN(p_hwfn)) {
3403                 rc = ecore_iov_hw_info(p_hwfn);
3404                 if (rc != ECORE_SUCCESS) {
3405                         if (p_params->b_relaxed_probe)
3406                                 p_params->p_relaxed_res =
3407                                                 ECORE_HW_PREPARE_BAD_IOV;
3408                         else
3409                                 return rc;
3410                 }
3411         }
3412
3413         /* TODO In get_hw_info, amoungst others:
3414          * Get MCP FW revision and determine according to it the supported
3415          * featrues (e.g. DCB)
3416          * Get boot mode
3417          * ecore_get_pcie_width_speed, WOL capability.
3418          * Number of global CQ-s (for storage
3419          */
3420         ecore_hw_info_port_num(p_hwfn, p_ptt);
3421
3422         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3423
3424 #ifndef ASIC_ONLY
3425         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3426 #endif
3427         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3428         if (rc != ECORE_SUCCESS)
3429                 return rc;
3430 #ifndef ASIC_ONLY
3431         }
3432 #endif
3433
3434         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3435         if (rc != ECORE_SUCCESS) {
3436                 if (p_params->b_relaxed_probe)
3437                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3438                 else
3439                         return rc;
3440         }
3441
3442 #ifndef ASIC_ONLY
3443         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3444 #endif
3445                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3446                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3447 #ifndef ASIC_ONLY
3448         } else {
3449                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3450
3451                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3452                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3453         }
3454 #endif
3455
3456         if (ecore_mcp_is_init(p_hwfn)) {
3457                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3458                         p_hwfn->hw_info.ovlan =
3459                             p_hwfn->mcp_info->func_info.ovlan;
3460
3461                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3462
3463                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3464         }
3465
3466         if (personality != ECORE_PCI_DEFAULT) {
3467                 p_hwfn->hw_info.personality = personality;
3468         } else if (ecore_mcp_is_init(p_hwfn)) {
3469                 enum ecore_pci_personality protocol;
3470
3471                 protocol = p_hwfn->mcp_info->func_info.protocol;
3472                 p_hwfn->hw_info.personality = protocol;
3473         }
3474
3475 #ifndef ASIC_ONLY
3476         /* To overcome ILT lack for emulation, until at least until we'll have
3477          * a definite answer from system about it, allow only PF0 to be RoCE.
3478          */
3479         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3480                 if (!p_hwfn->rel_pf_id)
3481                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3482                 else
3483                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3484         }
3485 #endif
3486
3487         /* although in BB some constellations may support more than 4 tcs,
3488          * that can result in performance penalty in some cases. 4
3489          * represents a good tradeoff between performance and flexibility.
3490          */
3491         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3492
3493         /* start out with a single active tc. This can be increased either
3494          * by dcbx negotiation or by upper layer driver
3495          */
3496         p_hwfn->hw_info.num_active_tc = 1;
3497
3498         ecore_get_num_funcs(p_hwfn, p_ptt);
3499
3500         if (ecore_mcp_is_init(p_hwfn))
3501                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3502
3503         /* In case of forcing the driver's default resource allocation, calling
3504          * ecore_hw_get_resc() should come after initializing the personality
3505          * and after getting the number of functions, since the calculation of
3506          * the resources/features depends on them.
3507          * This order is not harmful if not forcing.
3508          */
3509         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3510         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3511                 rc = ECORE_SUCCESS;
3512                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3513         }
3514
3515         return rc;
3516 }
3517
3518 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3519                                                struct ecore_ptt *p_ptt)
3520 {
3521         struct ecore_dev *p_dev = p_hwfn->p_dev;
3522         u16 device_id_mask;
3523         u32 tmp;
3524
3525         /* Read Vendor Id / Device Id */
3526         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3527                                   &p_dev->vendor_id);
3528         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3529                                   &p_dev->device_id);
3530
3531         /* Determine type */
3532         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3533         switch (device_id_mask) {
3534         case ECORE_DEV_ID_MASK_BB:
3535                 p_dev->type = ECORE_DEV_TYPE_BB;
3536                 break;
3537         case ECORE_DEV_ID_MASK_AH:
3538                 p_dev->type = ECORE_DEV_TYPE_AH;
3539                 break;
3540         default:
3541                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3542                           p_dev->device_id);
3543                 return ECORE_ABORTED;
3544         }
3545
3546         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_ptt,
3547                                                 MISCS_REG_CHIP_NUM);
3548         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_ptt,
3549                                                 MISCS_REG_CHIP_REV);
3550
3551         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3552
3553         /* Learn number of HW-functions */
3554         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3555
3556         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3557                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3558                 p_dev->num_hwfns = 2;
3559         } else {
3560                 p_dev->num_hwfns = 1;
3561         }
3562
3563 #ifndef ASIC_ONLY
3564         if (CHIP_REV_IS_EMUL(p_dev)) {
3565                 /* For some reason we have problems with this register
3566                  * in B0 emulation; Simply assume no CMT
3567                  */
3568                 DP_NOTICE(p_dev->hwfns, false,
3569                           "device on emul - assume no CMT\n");
3570                 p_dev->num_hwfns = 1;
3571         }
3572 #endif
3573
3574         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_ptt,
3575                                        MISCS_REG_CHIP_TEST_REG) >> 4;
3576         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3577         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_ptt,
3578                                            MISCS_REG_CHIP_METAL);
3579         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3580         DP_INFO(p_dev->hwfns,
3581                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3582                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3583                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3584                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3585                 p_dev->chip_metal);
3586
3587         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3588                 DP_NOTICE(p_dev->hwfns, false,
3589                           "The chip type/rev (BB A0) is not supported!\n");
3590                 return ECORE_ABORTED;
3591         }
3592 #ifndef ASIC_ONLY
3593         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3594                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3595
3596         if (CHIP_REV_IS_EMUL(p_dev)) {
3597                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3598                 if (tmp & (1 << 29)) {
3599                         DP_NOTICE(p_hwfn, false,
3600                                   "Emulation: Running on a FULL build\n");
3601                         p_dev->b_is_emul_full = true;
3602                 } else {
3603                         DP_NOTICE(p_hwfn, false,
3604                                   "Emulation: Running on a REDUCED build\n");
3605                 }
3606         }
3607 #endif
3608
3609         return ECORE_SUCCESS;
3610 }
3611
3612 #ifndef LINUX_REMOVE
3613 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3614 {
3615         int j;
3616
3617         if (IS_VF(p_dev))
3618                 return;
3619
3620         for_each_hwfn(p_dev, j) {
3621                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3622
3623                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3624                            "Mark hw/fw uninitialized\n");
3625
3626                 p_hwfn->hw_init_done = false;
3627                 p_hwfn->first_on_engine = false;
3628
3629                 ecore_ptt_invalidate(p_hwfn);
3630         }
3631 }
3632 #endif
3633
3634 static enum _ecore_status_t
3635 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3636                         void OSAL_IOMEM * p_regview,
3637                         void OSAL_IOMEM * p_doorbells,
3638                         struct ecore_hw_prepare_params *p_params)
3639 {
3640         struct ecore_mdump_retain_data mdump_retain;
3641         struct ecore_dev *p_dev = p_hwfn->p_dev;
3642         struct ecore_mdump_info mdump_info;
3643         enum _ecore_status_t rc = ECORE_SUCCESS;
3644
3645         /* Split PCI bars evenly between hwfns */
3646         p_hwfn->regview = p_regview;
3647         p_hwfn->doorbells = p_doorbells;
3648
3649         if (IS_VF(p_dev))
3650                 return ecore_vf_hw_prepare(p_hwfn);
3651
3652         /* Validate that chip access is feasible */
3653         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3654                 DP_ERR(p_hwfn,
3655                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3656                 if (p_params->b_relaxed_probe)
3657                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3658                 return ECORE_INVAL;
3659         }
3660
3661         get_function_id(p_hwfn);
3662
3663         /* Allocate PTT pool */
3664         rc = ecore_ptt_pool_alloc(p_hwfn);
3665         if (rc) {
3666                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3667                 if (p_params->b_relaxed_probe)
3668                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3669                 goto err0;
3670         }
3671
3672         /* Allocate the main PTT */
3673         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3674
3675         /* First hwfn learns basic information, e.g., number of hwfns */
3676         if (!p_hwfn->my_id) {
3677                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3678                 if (rc != ECORE_SUCCESS) {
3679                         if (p_params->b_relaxed_probe)
3680                                 p_params->p_relaxed_res =
3681                                         ECORE_HW_PREPARE_FAILED_DEV;
3682                         goto err1;
3683                 }
3684         }
3685
3686         ecore_hw_hwfn_prepare(p_hwfn);
3687
3688         /* Initialize MCP structure */
3689         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3690         if (rc) {
3691                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3692                 if (p_params->b_relaxed_probe)
3693                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3694                 goto err1;
3695         }
3696
3697         /* Read the device configuration information from the HW and SHMEM */
3698         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3699                                p_params->personality, p_params);
3700         if (rc) {
3701                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3702                 goto err2;
3703         }
3704
3705         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3706          * called, since among others it sets the ports number in an engine.
3707          */
3708         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
3709             !p_dev->recov_in_prog) {
3710                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3711                 if (rc != ECORE_SUCCESS)
3712                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3713         }
3714
3715         /* Check if mdump logs/data are present and update the epoch value */
3716         if (IS_LEAD_HWFN(p_hwfn)) {
3717 #ifndef ASIC_ONLY
3718                 if (!CHIP_REV_IS_EMUL(p_dev)) {
3719 #endif
3720                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3721                                               &mdump_info);
3722                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
3723                         DP_NOTICE(p_hwfn, false,
3724                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3725
3726                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
3727                                                 &mdump_retain);
3728                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
3729                         DP_NOTICE(p_hwfn, false,
3730                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
3731                                   mdump_retain.epoch, mdump_retain.pf,
3732                                   mdump_retain.status);
3733
3734                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3735                                            p_params->epoch);
3736 #ifndef ASIC_ONLY
3737                 }
3738 #endif
3739         }
3740
3741         /* Allocate the init RT array and initialize the init-ops engine */
3742         rc = ecore_init_alloc(p_hwfn);
3743         if (rc) {
3744                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3745                 if (p_params->b_relaxed_probe)
3746                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3747                 goto err2;
3748         }
3749 #ifndef ASIC_ONLY
3750         if (CHIP_REV_IS_FPGA(p_dev)) {
3751                 DP_NOTICE(p_hwfn, false,
3752                           "FPGA: workaround; Prevent DMAE parities\n");
3753                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3754                          7);
3755
3756                 DP_NOTICE(p_hwfn, false,
3757                           "FPGA: workaround: Set VF bar0 size\n");
3758                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3759                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3760         }
3761 #endif
3762
3763         return rc;
3764 err2:
3765         if (IS_LEAD_HWFN(p_hwfn))
3766                 ecore_iov_free_hw_info(p_dev);
3767         ecore_mcp_free(p_hwfn);
3768 err1:
3769         ecore_hw_hwfn_free(p_hwfn);
3770 err0:
3771         return rc;
3772 }
3773
3774 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3775                                       struct ecore_hw_prepare_params *p_params)
3776 {
3777         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3778         enum _ecore_status_t rc;
3779
3780         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3781         p_dev->allow_mdump = p_params->allow_mdump;
3782
3783         if (p_params->b_relaxed_probe)
3784                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3785
3786         /* Store the precompiled init data ptrs */
3787         if (IS_PF(p_dev))
3788                 ecore_init_iro_array(p_dev);
3789
3790         /* Initialize the first hwfn - will learn number of hwfns */
3791         rc = ecore_hw_prepare_single(p_hwfn,
3792                                      p_dev->regview,
3793                                      p_dev->doorbells, p_params);
3794         if (rc != ECORE_SUCCESS)
3795                 return rc;
3796
3797         p_params->personality = p_hwfn->hw_info.personality;
3798
3799         /* initilalize 2nd hwfn if necessary */
3800         if (p_dev->num_hwfns > 1) {
3801                 void OSAL_IOMEM *p_regview, *p_doorbell;
3802                 u8 OSAL_IOMEM *addr;
3803
3804                 /* adjust bar offset for second engine */
3805                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3806                                         ecore_hw_bar_size(p_hwfn,
3807                                                           p_hwfn->p_main_ptt,
3808                                                           BAR_ID_0) / 2;
3809                 p_regview = (void OSAL_IOMEM *)addr;
3810
3811                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3812                                         ecore_hw_bar_size(p_hwfn,
3813                                                           p_hwfn->p_main_ptt,
3814                                                           BAR_ID_1) / 2;
3815                 p_doorbell = (void OSAL_IOMEM *)addr;
3816
3817                 /* prepare second hw function */
3818                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3819                                              p_doorbell, p_params);
3820
3821                 /* in case of error, need to free the previously
3822                  * initiliazed hwfn 0.
3823                  */
3824                 if (rc != ECORE_SUCCESS) {
3825                         if (p_params->b_relaxed_probe)
3826                                 p_params->p_relaxed_res =
3827                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3828
3829                         if (IS_PF(p_dev)) {
3830                                 ecore_init_free(p_hwfn);
3831                                 ecore_mcp_free(p_hwfn);
3832                                 ecore_hw_hwfn_free(p_hwfn);
3833                         } else {
3834                                 DP_NOTICE(p_dev, true,
3835                                           "What do we need to free when VF hwfn1 init fails\n");
3836                         }
3837                         return rc;
3838                 }
3839         }
3840
3841         return rc;
3842 }
3843
3844 void ecore_hw_remove(struct ecore_dev *p_dev)
3845 {
3846         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3847         int i;
3848
3849         if (IS_PF(p_dev))
3850                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3851                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3852
3853         for_each_hwfn(p_dev, i) {
3854                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3855
3856                 if (IS_VF(p_dev)) {
3857                         ecore_vf_pf_release(p_hwfn);
3858                         continue;
3859                 }
3860
3861                 ecore_init_free(p_hwfn);
3862                 ecore_hw_hwfn_free(p_hwfn);
3863                 ecore_mcp_free(p_hwfn);
3864
3865                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3866         }
3867
3868         ecore_iov_free_hw_info(p_dev);
3869 }
3870
3871 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3872                                       struct ecore_chain *p_chain)
3873 {
3874         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3875         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3876         struct ecore_chain_next *p_next;
3877         u32 size, i;
3878
3879         if (!p_virt)
3880                 return;
3881
3882         size = p_chain->elem_size * p_chain->usable_per_page;
3883
3884         for (i = 0; i < p_chain->page_cnt; i++) {
3885                 if (!p_virt)
3886                         break;
3887
3888                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3889                 p_virt_next = p_next->next_virt;
3890                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3891
3892                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3893                                        ECORE_CHAIN_PAGE_SIZE);
3894
3895                 p_virt = p_virt_next;
3896                 p_phys = p_phys_next;
3897         }
3898 }
3899
3900 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3901                                     struct ecore_chain *p_chain)
3902 {
3903         if (!p_chain->p_virt_addr)
3904                 return;
3905
3906         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3907                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3908 }
3909
3910 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3911                                  struct ecore_chain *p_chain)
3912 {
3913         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3914         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3915         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3916
3917         if (!pp_virt_addr_tbl)
3918                 return;
3919
3920         if (!p_pbl_virt)
3921                 goto out;
3922
3923         for (i = 0; i < page_cnt; i++) {
3924                 if (!pp_virt_addr_tbl[i])
3925                         break;
3926
3927                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3928                                        *(dma_addr_t *)p_pbl_virt,
3929                                        ECORE_CHAIN_PAGE_SIZE);
3930
3931                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3932         }
3933
3934         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3935
3936         if (!p_chain->b_external_pbl)
3937                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3938                                        p_chain->pbl_sp.p_phys_table, pbl_size);
3939 out:
3940         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3941 }
3942
3943 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3944 {
3945         switch (p_chain->mode) {
3946         case ECORE_CHAIN_MODE_NEXT_PTR:
3947                 ecore_chain_free_next_ptr(p_dev, p_chain);
3948                 break;
3949         case ECORE_CHAIN_MODE_SINGLE:
3950                 ecore_chain_free_single(p_dev, p_chain);
3951                 break;
3952         case ECORE_CHAIN_MODE_PBL:
3953                 ecore_chain_free_pbl(p_dev, p_chain);
3954                 break;
3955         }
3956 }
3957
3958 static enum _ecore_status_t
3959 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3960                                enum ecore_chain_cnt_type cnt_type,
3961                                osal_size_t elem_size, u32 page_cnt)
3962 {
3963         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3964
3965         /* The actual chain size can be larger than the maximal possible value
3966          * after rounding up the requested elements number to pages, and after
3967          * taking into acount the unusuable elements (next-ptr elements).
3968          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3969          * size/capacity fields are of a u32 type.
3970          */
3971         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3972              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3973             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3974              chain_size > ECORE_U32_MAX)) {
3975                 DP_NOTICE(p_dev, true,
3976                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3977                           (unsigned long)chain_size);
3978                 return ECORE_INVAL;
3979         }
3980
3981         return ECORE_SUCCESS;
3982 }
3983
3984 static enum _ecore_status_t
3985 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3986 {
3987         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3988         dma_addr_t p_phys = 0;
3989         u32 i;
3990
3991         for (i = 0; i < p_chain->page_cnt; i++) {
3992                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3993                                                  ECORE_CHAIN_PAGE_SIZE);
3994                 if (!p_virt) {
3995                         DP_NOTICE(p_dev, true,
3996                                   "Failed to allocate chain memory\n");
3997                         return ECORE_NOMEM;
3998                 }
3999
4000                 if (i == 0) {
4001                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4002                         ecore_chain_reset(p_chain);
4003                 } else {
4004                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4005                                                        p_virt, p_phys);
4006                 }
4007
4008                 p_virt_prev = p_virt;
4009         }
4010         /* Last page's next element should point to the beginning of the
4011          * chain.
4012          */
4013         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4014                                        p_chain->p_virt_addr,
4015                                        p_chain->p_phys_addr);
4016
4017         return ECORE_SUCCESS;
4018 }
4019
4020 static enum _ecore_status_t
4021 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4022 {
4023         dma_addr_t p_phys = 0;
4024         void *p_virt = OSAL_NULL;
4025
4026         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4027         if (!p_virt) {
4028                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4029                 return ECORE_NOMEM;
4030         }
4031
4032         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4033         ecore_chain_reset(p_chain);
4034
4035         return ECORE_SUCCESS;
4036 }
4037
4038 static enum _ecore_status_t
4039 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4040                       struct ecore_chain *p_chain,
4041                       struct ecore_chain_ext_pbl *ext_pbl)
4042 {
4043         void *p_virt = OSAL_NULL;
4044         u8 *p_pbl_virt = OSAL_NULL;
4045         void **pp_virt_addr_tbl = OSAL_NULL;
4046         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4047         u32 page_cnt = p_chain->page_cnt, size, i;
4048
4049         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4050         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4051         if (!pp_virt_addr_tbl) {
4052                 DP_NOTICE(p_dev, true,
4053                           "Failed to allocate memory for the chain virtual addresses table\n");
4054                 return ECORE_NOMEM;
4055         }
4056
4057         /* The allocation of the PBL table is done with its full size, since it
4058          * is expected to be successive.
4059          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4060          * failure, since pp_virt_addr_tbl was previously allocated, and it
4061          * should be saved to allow its freeing during the error flow.
4062          */
4063         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4064
4065         if (ext_pbl == OSAL_NULL) {
4066                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4067         } else {
4068                 p_pbl_virt = ext_pbl->p_pbl_virt;
4069                 p_pbl_phys = ext_pbl->p_pbl_phys;
4070                 p_chain->b_external_pbl = true;
4071         }
4072
4073         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4074                                  pp_virt_addr_tbl);
4075         if (!p_pbl_virt) {
4076                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4077                 return ECORE_NOMEM;
4078         }
4079
4080         for (i = 0; i < page_cnt; i++) {
4081                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4082                                                  ECORE_CHAIN_PAGE_SIZE);
4083                 if (!p_virt) {
4084                         DP_NOTICE(p_dev, true,
4085                                   "Failed to allocate chain memory\n");
4086                         return ECORE_NOMEM;
4087                 }
4088
4089                 if (i == 0) {
4090                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4091                         ecore_chain_reset(p_chain);
4092                 }
4093
4094                 /* Fill the PBL table with the physical address of the page */
4095                 *(dma_addr_t *)p_pbl_virt = p_phys;
4096                 /* Keep the virtual address of the page */
4097                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4098
4099                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4100         }
4101
4102         return ECORE_SUCCESS;
4103 }
4104
4105 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4106                                        enum ecore_chain_use_mode intended_use,
4107                                        enum ecore_chain_mode mode,
4108                                        enum ecore_chain_cnt_type cnt_type,
4109                                        u32 num_elems, osal_size_t elem_size,
4110                                        struct ecore_chain *p_chain,
4111                                        struct ecore_chain_ext_pbl *ext_pbl)
4112 {
4113         u32 page_cnt;
4114         enum _ecore_status_t rc = ECORE_SUCCESS;
4115
4116         if (mode == ECORE_CHAIN_MODE_SINGLE)
4117                 page_cnt = 1;
4118         else
4119                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4120
4121         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4122                                             page_cnt);
4123         if (rc) {
4124                 DP_NOTICE(p_dev, true,
4125                           "Cannot allocate a chain with the given arguments:\n"
4126                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4127                           intended_use, mode, cnt_type, num_elems, elem_size);
4128                 return rc;
4129         }
4130
4131         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4132                                 mode, cnt_type, p_dev->dp_ctx);
4133
4134         switch (mode) {
4135         case ECORE_CHAIN_MODE_NEXT_PTR:
4136                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4137                 break;
4138         case ECORE_CHAIN_MODE_SINGLE:
4139                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4140                 break;
4141         case ECORE_CHAIN_MODE_PBL:
4142                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4143                 break;
4144         }
4145         if (rc)
4146                 goto nomem;
4147
4148         return ECORE_SUCCESS;
4149
4150 nomem:
4151         ecore_chain_free(p_dev, p_chain);
4152         return rc;
4153 }
4154
4155 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4156                                        u16 src_id, u16 *dst_id)
4157 {
4158         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4159                 u16 min, max;
4160
4161                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4162                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4163                 DP_NOTICE(p_hwfn, true,
4164                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4165                           src_id, min, max);
4166
4167                 return ECORE_INVAL;
4168         }
4169
4170         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4171
4172         return ECORE_SUCCESS;
4173 }
4174
4175 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4176                                     u8 src_id, u8 *dst_id)
4177 {
4178         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4179                 u8 min, max;
4180
4181                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4182                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4183                 DP_NOTICE(p_hwfn, true,
4184                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4185                           src_id, min, max);
4186
4187                 return ECORE_INVAL;
4188         }
4189
4190         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4191
4192         return ECORE_SUCCESS;
4193 }
4194
4195 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4196                                       u8 src_id, u8 *dst_id)
4197 {
4198         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4199                 u8 min, max;
4200
4201                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4202                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4203                 DP_NOTICE(p_hwfn, true,
4204                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4205                           src_id, min, max);
4206
4207                 return ECORE_INVAL;
4208         }
4209
4210         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4211
4212         return ECORE_SUCCESS;
4213 }
4214
4215 static enum _ecore_status_t
4216 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4217                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4218                                u32 *p_entry_num)
4219 {
4220         u32 en;
4221         int i;
4222
4223         /* Find a free entry and utilize it */
4224         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4225                 en = ecore_rd(p_hwfn, p_ptt,
4226                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4227                               i * sizeof(u32));
4228                 if (en)
4229                         continue;
4230                 ecore_wr(p_hwfn, p_ptt,
4231                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4232                          2 * i * sizeof(u32), low);
4233                 ecore_wr(p_hwfn, p_ptt,
4234                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4235                          (2 * i + 1) * sizeof(u32), high);
4236                 ecore_wr(p_hwfn, p_ptt,
4237                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4238                          i * sizeof(u32), 0);
4239                 ecore_wr(p_hwfn, p_ptt,
4240                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4241                          i * sizeof(u32), 0);
4242                 ecore_wr(p_hwfn, p_ptt,
4243                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4244                          i * sizeof(u32), 1);
4245                 break;
4246         }
4247
4248         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4249                 return ECORE_NORESOURCES;
4250
4251         *p_entry_num = i;
4252
4253         return ECORE_SUCCESS;
4254 }
4255
4256 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4257                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4258 {
4259         u32 high, low, entry_num;
4260         enum _ecore_status_t rc;
4261
4262         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4263                 return ECORE_SUCCESS;
4264
4265         high = p_filter[1] | (p_filter[0] << 8);
4266         low = p_filter[5] | (p_filter[4] << 8) |
4267               (p_filter[3] << 16) | (p_filter[2] << 24);
4268
4269         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4270                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4271                                                     &entry_num);
4272         if (rc != ECORE_SUCCESS) {
4273                 DP_NOTICE(p_hwfn, false,
4274                           "Failed to find an empty LLH filter to utilize\n");
4275                 return rc;
4276         }
4277
4278         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4279                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4280                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4281                    p_filter[4], p_filter[5], entry_num);
4282
4283         return ECORE_SUCCESS;
4284 }
4285
4286 static enum _ecore_status_t
4287 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4288                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4289                                   u32 *p_entry_num)
4290 {
4291         int i;
4292
4293         /* Find the entry and clean it */
4294         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4295                 if (ecore_rd(p_hwfn, p_ptt,
4296                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4297                              2 * i * sizeof(u32)) != low)
4298                         continue;
4299                 if (ecore_rd(p_hwfn, p_ptt,
4300                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4301                              (2 * i + 1) * sizeof(u32)) != high)
4302                         continue;
4303
4304                 ecore_wr(p_hwfn, p_ptt,
4305                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4306                 ecore_wr(p_hwfn, p_ptt,
4307                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4308                          2 * i * sizeof(u32), 0);
4309                 ecore_wr(p_hwfn, p_ptt,
4310                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4311                          (2 * i + 1) * sizeof(u32), 0);
4312                 break;
4313         }
4314
4315         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4316                 return ECORE_INVAL;
4317
4318         *p_entry_num = i;
4319
4320         return ECORE_SUCCESS;
4321 }
4322
4323 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4324                              struct ecore_ptt *p_ptt, u8 *p_filter)
4325 {
4326         u32 high, low, entry_num;
4327         enum _ecore_status_t rc;
4328
4329         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4330                 return;
4331
4332         high = p_filter[1] | (p_filter[0] << 8);
4333         low = p_filter[5] | (p_filter[4] << 8) |
4334               (p_filter[3] << 16) | (p_filter[2] << 24);
4335
4336         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4337                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4338                                                        low, &entry_num);
4339         if (rc != ECORE_SUCCESS) {
4340                 DP_NOTICE(p_hwfn, false,
4341                           "Tried to remove a non-configured filter\n");
4342                 return;
4343         }
4344
4345
4346         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4347                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4348                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4349                    p_filter[4], p_filter[5], entry_num);
4350 }
4351
4352 static enum _ecore_status_t
4353 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4354                                     struct ecore_ptt *p_ptt,
4355                                     enum ecore_llh_port_filter_type_t type,
4356                                     u32 high, u32 low, u32 *p_entry_num)
4357 {
4358         u32 en;
4359         int i;
4360
4361         /* Find a free entry and utilize it */
4362         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4363                 en = ecore_rd(p_hwfn, p_ptt,
4364                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4365                               i * sizeof(u32));
4366                 if (en)
4367                         continue;
4368                 ecore_wr(p_hwfn, p_ptt,
4369                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4370                          2 * i * sizeof(u32), low);
4371                 ecore_wr(p_hwfn, p_ptt,
4372                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4373                          (2 * i + 1) * sizeof(u32), high);
4374                 ecore_wr(p_hwfn, p_ptt,
4375                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4376                          i * sizeof(u32), 1);
4377                 ecore_wr(p_hwfn, p_ptt,
4378                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4379                          i * sizeof(u32), 1 << type);
4380                 ecore_wr(p_hwfn, p_ptt,
4381                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4382                 break;
4383         }
4384
4385         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4386                 return ECORE_NORESOURCES;
4387
4388         *p_entry_num = i;
4389
4390         return ECORE_SUCCESS;
4391 }
4392
4393 enum _ecore_status_t
4394 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4395                               struct ecore_ptt *p_ptt,
4396                               u16 source_port_or_eth_type,
4397                               u16 dest_port,
4398                               enum ecore_llh_port_filter_type_t type)
4399 {
4400         u32 high, low, entry_num;
4401         enum _ecore_status_t rc;
4402
4403         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4404                 return ECORE_SUCCESS;
4405
4406         high = 0;
4407         low = 0;
4408
4409         switch (type) {
4410         case ECORE_LLH_FILTER_ETHERTYPE:
4411                 high = source_port_or_eth_type;
4412                 break;
4413         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4414         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4415                 low = source_port_or_eth_type << 16;
4416                 break;
4417         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4418         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4419                 low = dest_port;
4420                 break;
4421         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4422         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4423                 low = (source_port_or_eth_type << 16) | dest_port;
4424                 break;
4425         default:
4426                 DP_NOTICE(p_hwfn, true,
4427                           "Non valid LLH protocol filter type %d\n", type);
4428                 return ECORE_INVAL;
4429         }
4430
4431         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4432                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4433                                                          high, low, &entry_num);
4434         if (rc != ECORE_SUCCESS) {
4435                 DP_NOTICE(p_hwfn, false,
4436                           "Failed to find an empty LLH filter to utilize\n");
4437                 return rc;
4438         }
4439         switch (type) {
4440         case ECORE_LLH_FILTER_ETHERTYPE:
4441                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4442                            "ETH type %x is added at %d\n",
4443                            source_port_or_eth_type, entry_num);
4444                 break;
4445         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4446                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4447                            "TCP src port %x is added at %d\n",
4448                            source_port_or_eth_type, entry_num);
4449                 break;
4450         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4451                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4452                            "UDP src port %x is added at %d\n",
4453                            source_port_or_eth_type, entry_num);
4454                 break;
4455         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4456                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4457                            "TCP dst port %x is added at %d\n", dest_port,
4458                            entry_num);
4459                 break;
4460         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4461                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4462                            "UDP dst port %x is added at %d\n", dest_port,
4463                            entry_num);
4464                 break;
4465         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4466                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4467                            "TCP src/dst ports %x/%x are added at %d\n",
4468                            source_port_or_eth_type, dest_port, entry_num);
4469                 break;
4470         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4471                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4472                            "UDP src/dst ports %x/%x are added at %d\n",
4473                            source_port_or_eth_type, dest_port, entry_num);
4474                 break;
4475         }
4476
4477         return ECORE_SUCCESS;
4478 }
4479
4480 static enum _ecore_status_t
4481 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4482                                        struct ecore_ptt *p_ptt,
4483                                        enum ecore_llh_port_filter_type_t type,
4484                                        u32 high, u32 low, u32 *p_entry_num)
4485 {
4486         int i;
4487
4488         /* Find the entry and clean it */
4489         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4490                 if (!ecore_rd(p_hwfn, p_ptt,
4491                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4492                               i * sizeof(u32)))
4493                         continue;
4494                 if (!ecore_rd(p_hwfn, p_ptt,
4495                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4496                               i * sizeof(u32)))
4497                         continue;
4498                 if (!(ecore_rd(p_hwfn, p_ptt,
4499                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4500                                i * sizeof(u32)) & (1 << type)))
4501                         continue;
4502                 if (ecore_rd(p_hwfn, p_ptt,
4503                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4504                              2 * i * sizeof(u32)) != low)
4505                         continue;
4506                 if (ecore_rd(p_hwfn, p_ptt,
4507                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4508                              (2 * i + 1) * sizeof(u32)) != high)
4509                         continue;
4510
4511                 ecore_wr(p_hwfn, p_ptt,
4512                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4513                 ecore_wr(p_hwfn, p_ptt,
4514                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4515                          i * sizeof(u32), 0);
4516                 ecore_wr(p_hwfn, p_ptt,
4517                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4518                          i * sizeof(u32), 0);
4519                 ecore_wr(p_hwfn, p_ptt,
4520                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4521                          2 * i * sizeof(u32), 0);
4522                 ecore_wr(p_hwfn, p_ptt,
4523                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4524                          (2 * i + 1) * sizeof(u32), 0);
4525                 break;
4526         }
4527
4528         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4529                 return ECORE_INVAL;
4530
4531         *p_entry_num = i;
4532
4533         return ECORE_SUCCESS;
4534 }
4535
4536 void
4537 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4538                                  struct ecore_ptt *p_ptt,
4539                                  u16 source_port_or_eth_type,
4540                                  u16 dest_port,
4541                                  enum ecore_llh_port_filter_type_t type)
4542 {
4543         u32 high, low, entry_num;
4544         enum _ecore_status_t rc;
4545
4546         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4547                 return;
4548
4549         high = 0;
4550         low = 0;
4551
4552         switch (type) {
4553         case ECORE_LLH_FILTER_ETHERTYPE:
4554                 high = source_port_or_eth_type;
4555                 break;
4556         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4557         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4558                 low = source_port_or_eth_type << 16;
4559                 break;
4560         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4561         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4562                 low = dest_port;
4563                 break;
4564         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4565         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4566                 low = (source_port_or_eth_type << 16) | dest_port;
4567                 break;
4568         default:
4569                 DP_NOTICE(p_hwfn, true,
4570                           "Non valid LLH protocol filter type %d\n", type);
4571                 return;
4572         }
4573
4574         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4575                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4576                                                             high, low,
4577                                                             &entry_num);
4578         if (rc != ECORE_SUCCESS) {
4579                 DP_NOTICE(p_hwfn, false,
4580                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4581                           type, source_port_or_eth_type, dest_port);
4582                 return;
4583         }
4584
4585         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4586                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4587                    type, source_port_or_eth_type, dest_port, entry_num);
4588 }
4589
4590 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4591                                               struct ecore_ptt *p_ptt)
4592 {
4593         int i;
4594
4595         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4596                 return;
4597
4598         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4599                 ecore_wr(p_hwfn, p_ptt,
4600                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
4601                          i * sizeof(u32), 0);
4602                 ecore_wr(p_hwfn, p_ptt,
4603                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4604                          2 * i * sizeof(u32), 0);
4605                 ecore_wr(p_hwfn, p_ptt,
4606                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4607                          (2 * i + 1) * sizeof(u32), 0);
4608         }
4609 }
4610
4611 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4612                              struct ecore_ptt *p_ptt)
4613 {
4614         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4615                 return;
4616
4617         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4618                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
4619 }
4620
4621 enum _ecore_status_t
4622 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4623                                   struct ecore_ptt *p_ptt)
4624 {
4625         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4626                 ecore_wr(p_hwfn, p_ptt,
4627                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4628                          1 << p_hwfn->abs_pf_id / 2);
4629                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4630                 return ECORE_SUCCESS;
4631         }
4632
4633         DP_NOTICE(p_hwfn, false,
4634                   "This function can't be set as default\n");
4635         return ECORE_INVAL;
4636 }
4637
4638 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4639                                                struct ecore_ptt *p_ptt,
4640                                                u32 hw_addr, void *p_eth_qzone,
4641                                                osal_size_t eth_qzone_size,
4642                                                u8 timeset)
4643 {
4644         struct coalescing_timeset *p_coal_timeset;
4645
4646         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4647                 DP_NOTICE(p_hwfn, true,
4648                           "Coalescing configuration not enabled\n");
4649                 return ECORE_INVAL;
4650         }
4651
4652         p_coal_timeset = p_eth_qzone;
4653         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4654         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4655         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4656         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4657
4658         return ECORE_SUCCESS;
4659 }
4660
4661 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4662                                               u16 rx_coal, u16 tx_coal,
4663                                               void *p_handle)
4664 {
4665         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4666         enum _ecore_status_t rc = ECORE_SUCCESS;
4667         struct ecore_ptt *p_ptt;
4668
4669         /* TODO - Configuring a single queue's coalescing but
4670          * claiming all queues are abiding same configuration
4671          * for PF and VF both.
4672          */
4673
4674         if (IS_VF(p_hwfn->p_dev))
4675                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4676                                                 tx_coal, p_cid);
4677
4678         p_ptt = ecore_ptt_acquire(p_hwfn);
4679         if (!p_ptt)
4680                 return ECORE_AGAIN;
4681
4682         if (rx_coal) {
4683                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4684                 if (rc)
4685                         goto out;
4686                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
4687         }
4688
4689         if (tx_coal) {
4690                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4691                 if (rc)
4692                         goto out;
4693                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
4694         }
4695 out:
4696         ecore_ptt_release(p_hwfn, p_ptt);
4697
4698         return rc;
4699 }
4700
4701 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4702                                             struct ecore_ptt *p_ptt,
4703                                             u16 coalesce,
4704                                             struct ecore_queue_cid *p_cid)
4705 {
4706         struct ustorm_eth_queue_zone eth_qzone;
4707         u8 timeset, timer_res;
4708         u32 address;
4709         enum _ecore_status_t rc;
4710
4711         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4712         if (coalesce <= 0x7F) {
4713                 timer_res = 0;
4714         } else if (coalesce <= 0xFF) {
4715                 timer_res = 1;
4716         } else if (coalesce <= 0x1FF) {
4717                 timer_res = 2;
4718         } else {
4719                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4720                 return ECORE_INVAL;
4721         }
4722         timeset = (u8)(coalesce >> timer_res);
4723
4724         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4725                                      p_cid->sb_igu_id, false);
4726         if (rc != ECORE_SUCCESS)
4727                 goto out;
4728
4729         address = BAR0_MAP_REG_USDM_RAM +
4730                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4731
4732         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4733                                 sizeof(struct ustorm_eth_queue_zone), timeset);
4734         if (rc != ECORE_SUCCESS)
4735                 goto out;
4736
4737 out:
4738         return rc;
4739 }
4740
4741 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4742                                             struct ecore_ptt *p_ptt,
4743                                             u16 coalesce,
4744                                             struct ecore_queue_cid *p_cid)
4745 {
4746         struct xstorm_eth_queue_zone eth_qzone;
4747         u8 timeset, timer_res;
4748         u32 address;
4749         enum _ecore_status_t rc;
4750
4751         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4752         if (coalesce <= 0x7F) {
4753                 timer_res = 0;
4754         } else if (coalesce <= 0xFF) {
4755                 timer_res = 1;
4756         } else if (coalesce <= 0x1FF) {
4757                 timer_res = 2;
4758         } else {
4759                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4760                 return ECORE_INVAL;
4761         }
4762
4763         timeset = (u8)(coalesce >> timer_res);
4764
4765         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4766                                      p_cid->sb_igu_id, true);
4767         if (rc != ECORE_SUCCESS)
4768                 goto out;
4769
4770         address = BAR0_MAP_REG_XSDM_RAM +
4771                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4772
4773         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4774                                 sizeof(struct xstorm_eth_queue_zone), timeset);
4775 out:
4776         return rc;
4777 }
4778
4779 /* Calculate final WFQ values for all vports and configure it.
4780  * After this configuration each vport must have
4781  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4782  */
4783 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4784                                                struct ecore_ptt *p_ptt,
4785                                                u32 min_pf_rate)
4786 {
4787         struct init_qm_vport_params *vport_params;
4788         int i;
4789
4790         vport_params = p_hwfn->qm_info.qm_vport_params;
4791
4792         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4793                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4794
4795                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4796                     min_pf_rate;
4797                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4798                                      vport_params[i].first_tx_pq_id,
4799                                      vport_params[i].vport_wfq);
4800         }
4801 }
4802
4803 static void
4804 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4805 {
4806         int i;
4807
4808         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4809                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4810 }
4811
4812 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4813                                              struct ecore_ptt *p_ptt,
4814                                              u32 min_pf_rate)
4815 {
4816         struct init_qm_vport_params *vport_params;
4817         int i;
4818
4819         vport_params = p_hwfn->qm_info.qm_vport_params;
4820
4821         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4822                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4823                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4824                                      vport_params[i].first_tx_pq_id,
4825                                      vport_params[i].vport_wfq);
4826         }
4827 }
4828
4829 /* This function performs several validations for WFQ
4830  * configuration and required min rate for a given vport
4831  * 1. req_rate must be greater than one percent of min_pf_rate.
4832  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4833  *    rates to get less than one percent of min_pf_rate.
4834  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4835  */
4836 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4837                                                  u16 vport_id, u32 req_rate,
4838                                                  u32 min_pf_rate)
4839 {
4840         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4841         int non_requested_count = 0, req_count = 0, i, num_vports;
4842
4843         num_vports = p_hwfn->qm_info.num_vports;
4844
4845 /* Accounting for the vports which are configured for WFQ explicitly */
4846
4847         for (i = 0; i < num_vports; i++) {
4848                 u32 tmp_speed;
4849
4850                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4851                         req_count++;
4852                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4853                         total_req_min_rate += tmp_speed;
4854                 }
4855         }
4856
4857         /* Include current vport data as well */
4858         req_count++;
4859         total_req_min_rate += req_rate;
4860         non_requested_count = num_vports - req_count;
4861
4862         /* validate possible error cases */
4863         if (req_rate > min_pf_rate) {
4864                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4865                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4866                            vport_id, req_rate, min_pf_rate);
4867                 return ECORE_INVAL;
4868         }
4869
4870         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4871                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4872                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4873                            vport_id, req_rate, min_pf_rate);
4874                 return ECORE_INVAL;
4875         }
4876
4877         /* TBD - for number of vports greater than 100 */
4878         if (num_vports > ECORE_WFQ_UNIT) {
4879                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4880                            "Number of vports is greater than %d\n",
4881                            ECORE_WFQ_UNIT);
4882                 return ECORE_INVAL;
4883         }
4884
4885         if (total_req_min_rate > min_pf_rate) {
4886                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4887                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4888                            total_req_min_rate, min_pf_rate);
4889                 return ECORE_INVAL;
4890         }
4891
4892         /* Data left for non requested vports */
4893         total_left_rate = min_pf_rate - total_req_min_rate;
4894         left_rate_per_vp = total_left_rate / non_requested_count;
4895
4896         /* validate if non requested get < 1% of min bw */
4897         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4898                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4899                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4900                            left_rate_per_vp, min_pf_rate);
4901                 return ECORE_INVAL;
4902         }
4903
4904         /* now req_rate for given vport passes all scenarios.
4905          * assign final wfq rates to all vports.
4906          */
4907         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4908         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4909
4910         for (i = 0; i < num_vports; i++) {
4911                 if (p_hwfn->qm_info.wfq_data[i].configured)
4912                         continue;
4913
4914                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4915         }
4916
4917         return ECORE_SUCCESS;
4918 }
4919
4920 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4921                                        struct ecore_ptt *p_ptt,
4922                                        u16 vp_id, u32 rate)
4923 {
4924         struct ecore_mcp_link_state *p_link;
4925         int rc = ECORE_SUCCESS;
4926
4927         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4928
4929         if (!p_link->min_pf_rate) {
4930                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4931                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4932                 return rc;
4933         }
4934
4935         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4936
4937         if (rc == ECORE_SUCCESS)
4938                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4939                                                    p_link->min_pf_rate);
4940         else
4941                 DP_NOTICE(p_hwfn, false,
4942                           "Validation failed while configuring min rate\n");
4943
4944         return rc;
4945 }
4946
4947 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4948                                                    struct ecore_ptt *p_ptt,
4949                                                    u32 min_pf_rate)
4950 {
4951         bool use_wfq = false;
4952         int rc = ECORE_SUCCESS;
4953         u16 i;
4954
4955         /* Validate all pre configured vports for wfq */
4956         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4957                 u32 rate;
4958
4959                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4960                         continue;
4961
4962                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4963                 use_wfq = true;
4964
4965                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4966                 if (rc != ECORE_SUCCESS) {
4967                         DP_NOTICE(p_hwfn, false,
4968                                   "WFQ validation failed while configuring min rate\n");
4969                         break;
4970                 }
4971         }
4972
4973         if (rc == ECORE_SUCCESS && use_wfq)
4974                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4975         else
4976                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4977
4978         return rc;
4979 }
4980
4981 /* Main API for ecore clients to configure vport min rate.
4982  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4983  * rate - Speed in Mbps needs to be assigned to a given vport.
4984  */
4985 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4986 {
4987         int i, rc = ECORE_INVAL;
4988
4989         /* TBD - for multiple hardware functions - that is 100 gig */
4990         if (p_dev->num_hwfns > 1) {
4991                 DP_NOTICE(p_dev, false,
4992                           "WFQ configuration is not supported for this device\n");
4993                 return rc;
4994         }
4995
4996         for_each_hwfn(p_dev, i) {
4997                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4998                 struct ecore_ptt *p_ptt;
4999
5000                 p_ptt = ecore_ptt_acquire(p_hwfn);
5001                 if (!p_ptt)
5002                         return ECORE_TIMEOUT;
5003
5004                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5005
5006                 if (rc != ECORE_SUCCESS) {
5007                         ecore_ptt_release(p_hwfn, p_ptt);
5008                         return rc;
5009                 }
5010
5011                 ecore_ptt_release(p_hwfn, p_ptt);
5012         }
5013
5014         return rc;
5015 }
5016
5017 /* API to configure WFQ from mcp link change */
5018 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5019                                            struct ecore_ptt *p_ptt,
5020                                            u32 min_pf_rate)
5021 {
5022         int i;
5023
5024         /* TBD - for multiple hardware functions - that is 100 gig */
5025         if (p_dev->num_hwfns > 1) {
5026                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5027                            "WFQ configuration is not supported for this device\n");
5028                 return;
5029         }
5030
5031         for_each_hwfn(p_dev, i) {
5032                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5033
5034                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5035                                                         min_pf_rate);
5036         }
5037 }
5038
5039 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5040                                        struct ecore_ptt *p_ptt,
5041                                        struct ecore_mcp_link_state *p_link,
5042                                        u8 max_bw)
5043 {
5044         int rc = ECORE_SUCCESS;
5045
5046         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5047
5048         if (!p_link->line_speed && (max_bw != 100))
5049                 return rc;
5050
5051         p_link->speed = (p_link->line_speed * max_bw) / 100;
5052         p_hwfn->qm_info.pf_rl = p_link->speed;
5053
5054         /* Since the limiter also affects Tx-switched traffic, we don't want it
5055          * to limit such traffic in case there's no actual limit.
5056          * In that case, set limit to imaginary high boundary.
5057          */
5058         if (max_bw == 100)
5059                 p_hwfn->qm_info.pf_rl = 100000;
5060
5061         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5062                               p_hwfn->qm_info.pf_rl);
5063
5064         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5065                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5066                    p_link->speed);
5067
5068         return rc;
5069 }
5070
5071 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5072 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5073 {
5074         int i, rc = ECORE_INVAL;
5075
5076         if (max_bw < 1 || max_bw > 100) {
5077                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5078                 return rc;
5079         }
5080
5081         for_each_hwfn(p_dev, i) {
5082                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5083                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5084                 struct ecore_mcp_link_state *p_link;
5085                 struct ecore_ptt *p_ptt;
5086
5087                 p_link = &p_lead->mcp_info->link_output;
5088
5089                 p_ptt = ecore_ptt_acquire(p_hwfn);
5090                 if (!p_ptt)
5091                         return ECORE_TIMEOUT;
5092
5093                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5094                                                         p_link, max_bw);
5095
5096                 ecore_ptt_release(p_hwfn, p_ptt);
5097
5098                 if (rc != ECORE_SUCCESS)
5099                         break;
5100         }
5101
5102         return rc;
5103 }
5104
5105 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5106                                        struct ecore_ptt *p_ptt,
5107                                        struct ecore_mcp_link_state *p_link,
5108                                        u8 min_bw)
5109 {
5110         int rc = ECORE_SUCCESS;
5111
5112         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5113         p_hwfn->qm_info.pf_wfq = min_bw;
5114
5115         if (!p_link->line_speed)
5116                 return rc;
5117
5118         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5119
5120         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5121
5122         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5123                    "Configured MIN bandwidth to be %d Mb/sec\n",
5124                    p_link->min_pf_rate);
5125
5126         return rc;
5127 }
5128
5129 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5130 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5131 {
5132         int i, rc = ECORE_INVAL;
5133
5134         if (min_bw < 1 || min_bw > 100) {
5135                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5136                 return rc;
5137         }
5138
5139         for_each_hwfn(p_dev, i) {
5140                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5141                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5142                 struct ecore_mcp_link_state *p_link;
5143                 struct ecore_ptt *p_ptt;
5144
5145                 p_link = &p_lead->mcp_info->link_output;
5146
5147                 p_ptt = ecore_ptt_acquire(p_hwfn);
5148                 if (!p_ptt)
5149                         return ECORE_TIMEOUT;
5150
5151                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5152                                                         p_link, min_bw);
5153                 if (rc != ECORE_SUCCESS) {
5154                         ecore_ptt_release(p_hwfn, p_ptt);
5155                         return rc;
5156                 }
5157
5158                 if (p_link->min_pf_rate) {
5159                         u32 min_rate = p_link->min_pf_rate;
5160
5161                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5162                                                                      p_ptt,
5163                                                                      min_rate);
5164                 }
5165
5166                 ecore_ptt_release(p_hwfn, p_ptt);
5167         }
5168
5169         return rc;
5170 }
5171
5172 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5173 {
5174         struct ecore_mcp_link_state *p_link;
5175
5176         p_link = &p_hwfn->mcp_info->link_output;
5177
5178         if (p_link->min_pf_rate)
5179                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5180                                                  p_link->min_pf_rate);
5181
5182         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5183                     sizeof(*p_hwfn->qm_info.wfq_data) *
5184                     p_hwfn->qm_info.num_vports);
5185 }
5186
5187 int ecore_device_num_engines(struct ecore_dev *p_dev)
5188 {
5189         return ECORE_IS_BB(p_dev) ? 2 : 1;
5190 }
5191
5192 int ecore_device_num_ports(struct ecore_dev *p_dev)
5193 {
5194         /* in CMT always only one port */
5195         if (p_dev->num_hwfns > 1)
5196                 return 1;
5197
5198         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
5199 }
5200
5201 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5202                           __le16 *fw_mid,
5203                           __le16 *fw_lsb,
5204                           u8 *mac)
5205 {
5206         ((u8 *)fw_msb)[0] = mac[1];
5207         ((u8 *)fw_msb)[1] = mac[0];
5208         ((u8 *)fw_mid)[0] = mac[3];
5209         ((u8 *)fw_mid)[1] = mac[2];
5210         ((u8 *)fw_lsb)[0] = mac[5];
5211         ((u8 *)fw_lsb)[1] = mac[4];
5212 }