1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
9 #include "ecore_gtt_reg_addr.h"
11 #include "ecore_chain.h"
12 #include "ecore_status.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_init_ops.h"
16 #include "ecore_int.h"
17 #include "ecore_cxt.h"
18 #include "ecore_spq.h"
19 #include "ecore_init_fw_funcs.h"
20 #include "ecore_sp_commands.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
24 #include "ecore_mcp.h"
25 #include "ecore_hw_defs.h"
26 #include "mcp_public.h"
27 #include "ecore_iro.h"
29 #include "ecore_dcbx.h"
32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
33 * registers involved are not split and thus configuration is a race where
34 * some of the PFs configuration might be lost.
35 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
36 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
37 * there's more than a single compiled ecore component in system].
39 static osal_spinlock_t qm_lock;
40 static u32 qm_lock_ref_cnt;
42 /******************** Doorbell Recovery *******************/
43 /* The doorbell recovery mechanism consists of a list of entries which represent
44 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
45 * entity needs to register with the mechanism and provide the parameters
46 * describing it's doorbell, including a location where last used doorbell data
47 * can be found. The doorbell execute function will traverse the list and
48 * doorbell all of the registered entries.
50 struct ecore_db_recovery_entry {
51 osal_list_entry_t list_entry;
52 void OSAL_IOMEM *db_addr;
54 enum ecore_db_rec_width db_width;
55 enum ecore_db_rec_space db_space;
59 /* display a single doorbell recovery entry */
60 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
61 struct ecore_db_recovery_entry *db_entry,
64 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
65 action, db_entry, db_entry->db_addr, db_entry->db_data,
66 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
67 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
71 /* doorbell address sanity (address within doorbell bar range) */
72 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
75 /* make sure doorbell address is within the doorbell bar */
76 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
77 (u8 *)p_dev->doorbells + p_dev->db_size) {
79 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
80 db_addr, p_dev->doorbells,
81 (u8 *)p_dev->doorbells + p_dev->db_size);
85 /* make sure doorbell data pointer is not null */
87 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
94 /* find hwfn according to the doorbell address */
95 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
96 void OSAL_IOMEM *db_addr)
98 struct ecore_hwfn *p_hwfn;
100 /* In CMT doorbell bar is split down the middle between engine 0 and
103 if (ECORE_IS_CMT(p_dev))
104 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
105 &p_dev->hwfns[0] : &p_dev->hwfns[1];
107 p_hwfn = ECORE_LEADING_HWFN(p_dev);
112 /* add a new entry to the doorbell recovery mechanism */
113 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
114 void OSAL_IOMEM *db_addr,
116 enum ecore_db_rec_width db_width,
117 enum ecore_db_rec_space db_space)
119 struct ecore_db_recovery_entry *db_entry;
120 struct ecore_hwfn *p_hwfn;
122 /* shortcircuit VFs, for now */
124 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
125 return ECORE_SUCCESS;
128 /* sanitize doorbell address */
129 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
132 /* obtain hwfn from doorbell address */
133 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
136 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
138 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
143 db_entry->db_addr = db_addr;
144 db_entry->db_data = db_data;
145 db_entry->db_width = db_width;
146 db_entry->db_space = db_space;
147 db_entry->hwfn_idx = p_hwfn->my_id;
150 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
152 /* protect the list */
153 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
154 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
155 &p_hwfn->db_recovery_info.list);
156 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
158 return ECORE_SUCCESS;
161 /* remove an entry from the doorbell recovery mechanism */
162 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
163 void OSAL_IOMEM *db_addr,
166 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
167 enum _ecore_status_t rc = ECORE_INVAL;
168 struct ecore_hwfn *p_hwfn;
170 /* shortcircuit VFs, for now */
172 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
173 return ECORE_SUCCESS;
176 /* sanitize doorbell address */
177 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
180 /* obtain hwfn from doorbell address */
181 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
183 /* protect the list */
184 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
185 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
186 &p_hwfn->db_recovery_info.list,
188 struct ecore_db_recovery_entry) {
189 /* search according to db_data addr since db_addr is not unique
192 if (db_entry->db_data == db_data) {
193 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
195 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
196 &p_hwfn->db_recovery_info.list);
202 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
204 if (rc == ECORE_INVAL)
206 DP_NOTICE(p_hwfn, false,
207 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
210 OSAL_FREE(p_dev, db_entry);
215 /* initialize the doorbell recovery mechanism */
216 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
218 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
220 /* make sure db_size was set in p_dev */
221 if (!p_hwfn->p_dev->db_size) {
222 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
226 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
227 #ifdef CONFIG_ECORE_LOCK_ALLOC
228 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
231 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
232 p_hwfn->db_recovery_info.db_recovery_counter = 0;
234 return ECORE_SUCCESS;
237 /* destroy the doorbell recovery mechanism */
238 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
240 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
242 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
243 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
244 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
245 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
246 db_entry = OSAL_LIST_FIRST_ENTRY(
247 &p_hwfn->db_recovery_info.list,
248 struct ecore_db_recovery_entry,
250 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
251 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
252 &p_hwfn->db_recovery_info.list);
253 OSAL_FREE(p_hwfn->p_dev, db_entry);
256 #ifdef CONFIG_ECORE_LOCK_ALLOC
257 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
259 p_hwfn->db_recovery_info.db_recovery_counter = 0;
262 /* print the content of the doorbell recovery mechanism */
263 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
265 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
267 DP_NOTICE(p_hwfn, false,
268 "Dispalying doorbell recovery database. Counter was %d\n",
269 p_hwfn->db_recovery_info.db_recovery_counter);
271 /* protect the list */
272 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
273 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
274 &p_hwfn->db_recovery_info.list,
276 struct ecore_db_recovery_entry) {
277 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
280 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
283 /* ring the doorbell of a single doorbell recovery entry */
284 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
285 struct ecore_db_recovery_entry *db_entry,
286 enum ecore_db_rec_exec db_exec)
288 /* Print according to width */
289 if (db_entry->db_width == DB_REC_WIDTH_32B)
290 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
291 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
292 db_entry->db_addr, *(u32 *)db_entry->db_data);
294 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
295 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
297 *(unsigned long *)(db_entry->db_data));
300 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
304 /* Flush the write combined buffer. Since there are multiple doorbelling
305 * entities using the same address, if we don't flush, a transaction
308 OSAL_WMB(p_hwfn->p_dev);
310 /* Ring the doorbell */
311 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
312 if (db_entry->db_width == DB_REC_WIDTH_32B)
313 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
314 *(u32 *)(db_entry->db_data));
316 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
317 *(u64 *)(db_entry->db_data));
320 /* Flush the write combined buffer. Next doorbell may come from a
321 * different entity to the same address...
323 OSAL_WMB(p_hwfn->p_dev);
326 /* traverse the doorbell recovery entry list and ring all the doorbells */
327 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
328 enum ecore_db_rec_exec db_exec)
330 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
332 if (db_exec != DB_REC_ONCE) {
333 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
334 p_hwfn->db_recovery_info.db_recovery_counter);
336 /* track amount of times recovery was executed */
337 p_hwfn->db_recovery_info.db_recovery_counter++;
340 /* protect the list */
341 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
342 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
343 &p_hwfn->db_recovery_info.list,
345 struct ecore_db_recovery_entry) {
346 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
347 if (db_exec == DB_REC_ONCE)
351 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
353 /******************** Doorbell Recovery end ****************/
355 /********************************** NIG LLH ***********************************/
357 enum ecore_llh_filter_type {
358 ECORE_LLH_FILTER_TYPE_MAC,
359 ECORE_LLH_FILTER_TYPE_PROTOCOL,
362 struct ecore_llh_mac_filter {
366 struct ecore_llh_protocol_filter {
367 enum ecore_llh_prot_filter_type_t type;
368 u16 source_port_or_eth_type;
372 union ecore_llh_filter {
373 struct ecore_llh_mac_filter mac;
374 struct ecore_llh_protocol_filter protocol;
377 struct ecore_llh_filter_info {
380 enum ecore_llh_filter_type type;
381 union ecore_llh_filter filter;
384 struct ecore_llh_info {
385 /* Number of LLH filters banks */
388 #define MAX_NUM_PPFID 8
389 u8 ppfid_array[MAX_NUM_PPFID];
391 /* Array of filters arrays:
392 * "num_ppfid" elements of filters banks, where each is an array of
393 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
395 struct ecore_llh_filter_info **pp_filters;
398 static void ecore_llh_free(struct ecore_dev *p_dev)
400 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
403 if (p_llh_info != OSAL_NULL) {
404 if (p_llh_info->pp_filters != OSAL_NULL) {
405 for (i = 0; i < p_llh_info->num_ppfid; i++)
406 OSAL_FREE(p_dev, p_llh_info->pp_filters[i]);
409 OSAL_FREE(p_dev, p_llh_info->pp_filters);
412 OSAL_FREE(p_dev, p_llh_info);
413 p_dev->p_llh_info = OSAL_NULL;
416 static enum _ecore_status_t ecore_llh_alloc(struct ecore_dev *p_dev)
418 struct ecore_llh_info *p_llh_info;
422 p_llh_info = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_llh_info));
425 p_dev->p_llh_info = p_llh_info;
427 for (i = 0; i < MAX_NUM_PPFID; i++) {
428 if (!(p_dev->ppfid_bitmap & (0x1 << i)))
431 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
432 DP_VERBOSE(p_dev, ECORE_MSG_SP, "ppfid_array[%d] = %hhd\n",
433 p_llh_info->num_ppfid, i);
434 p_llh_info->num_ppfid++;
437 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
438 p_llh_info->pp_filters = OSAL_ZALLOC(p_dev, GFP_KERNEL, size);
439 if (!p_llh_info->pp_filters)
442 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
443 sizeof(**p_llh_info->pp_filters);
444 for (i = 0; i < p_llh_info->num_ppfid; i++) {
445 p_llh_info->pp_filters[i] = OSAL_ZALLOC(p_dev, GFP_KERNEL,
447 if (!p_llh_info->pp_filters[i])
451 return ECORE_SUCCESS;
454 static enum _ecore_status_t ecore_llh_shadow_sanity(struct ecore_dev *p_dev,
455 u8 ppfid, u8 filter_idx,
458 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
460 if (ppfid >= p_llh_info->num_ppfid) {
461 DP_NOTICE(p_dev, false,
462 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
463 action, ppfid, p_llh_info->num_ppfid);
467 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
468 DP_NOTICE(p_dev, false,
469 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
470 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
474 return ECORE_SUCCESS;
477 #define ECORE_LLH_INVALID_FILTER_IDX 0xff
479 static enum _ecore_status_t
480 ecore_llh_shadow_search_filter(struct ecore_dev *p_dev, u8 ppfid,
481 union ecore_llh_filter *p_filter,
484 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
485 struct ecore_llh_filter_info *p_filters;
486 enum _ecore_status_t rc;
489 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "search");
490 if (rc != ECORE_SUCCESS)
493 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
495 p_filters = p_llh_info->pp_filters[ppfid];
496 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
497 if (!OSAL_MEMCMP(p_filter, &p_filters[i].filter,
498 sizeof(*p_filter))) {
504 return ECORE_SUCCESS;
507 static enum _ecore_status_t
508 ecore_llh_shadow_get_free_idx(struct ecore_dev *p_dev, u8 ppfid,
511 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
512 struct ecore_llh_filter_info *p_filters;
513 enum _ecore_status_t rc;
516 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "get_free_idx");
517 if (rc != ECORE_SUCCESS)
520 *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
522 p_filters = p_llh_info->pp_filters[ppfid];
523 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
524 if (!p_filters[i].b_enabled) {
530 return ECORE_SUCCESS;
533 static enum _ecore_status_t
534 __ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, u8 filter_idx,
535 enum ecore_llh_filter_type type,
536 union ecore_llh_filter *p_filter, u32 *p_ref_cnt)
538 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
539 struct ecore_llh_filter_info *p_filters;
540 enum _ecore_status_t rc;
542 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "add");
543 if (rc != ECORE_SUCCESS)
546 p_filters = p_llh_info->pp_filters[ppfid];
547 if (!p_filters[filter_idx].ref_cnt) {
548 p_filters[filter_idx].b_enabled = true;
549 p_filters[filter_idx].type = type;
550 OSAL_MEMCPY(&p_filters[filter_idx].filter, p_filter,
551 sizeof(p_filters[filter_idx].filter));
554 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
556 return ECORE_SUCCESS;
559 static enum _ecore_status_t
560 ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid,
561 enum ecore_llh_filter_type type,
562 union ecore_llh_filter *p_filter,
563 u8 *p_filter_idx, u32 *p_ref_cnt)
565 enum _ecore_status_t rc;
567 /* Check if the same filter already exist */
568 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
570 if (rc != ECORE_SUCCESS)
573 /* Find a new entry in case of a new filter */
574 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
575 rc = ecore_llh_shadow_get_free_idx(p_dev, ppfid, p_filter_idx);
576 if (rc != ECORE_SUCCESS)
580 /* No free entry was found */
581 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
582 DP_NOTICE(p_dev, false,
583 "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
585 return ECORE_NORESOURCES;
588 return __ecore_llh_shadow_add_filter(p_dev, ppfid, *p_filter_idx, type,
589 p_filter, p_ref_cnt);
592 static enum _ecore_status_t
593 __ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
594 u8 filter_idx, u32 *p_ref_cnt)
596 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
597 struct ecore_llh_filter_info *p_filters;
598 enum _ecore_status_t rc;
600 rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "remove");
601 if (rc != ECORE_SUCCESS)
604 p_filters = p_llh_info->pp_filters[ppfid];
605 if (!p_filters[filter_idx].ref_cnt) {
606 DP_NOTICE(p_dev, false,
607 "LLH shadow: trying to remove a filter with ref_cnt=0\n");
611 *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
612 if (!p_filters[filter_idx].ref_cnt)
613 OSAL_MEM_ZERO(&p_filters[filter_idx],
614 sizeof(p_filters[filter_idx]));
616 return ECORE_SUCCESS;
619 static enum _ecore_status_t
620 ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
621 union ecore_llh_filter *p_filter,
622 u8 *p_filter_idx, u32 *p_ref_cnt)
624 enum _ecore_status_t rc;
626 rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
628 if (rc != ECORE_SUCCESS)
631 /* No matching filter was found */
632 if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
633 DP_NOTICE(p_dev, false,
634 "Failed to find a filter in the LLH shadow\n");
638 return __ecore_llh_shadow_remove_filter(p_dev, ppfid, *p_filter_idx,
642 static enum _ecore_status_t
643 ecore_llh_shadow_remove_all_filters(struct ecore_dev *p_dev, u8 ppfid)
645 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
646 struct ecore_llh_filter_info *p_filters;
647 enum _ecore_status_t rc;
649 rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "remove_all");
650 if (rc != ECORE_SUCCESS)
653 p_filters = p_llh_info->pp_filters[ppfid];
654 OSAL_MEM_ZERO(p_filters,
655 NIG_REG_LLH_FUNC_FILTER_EN_SIZE * sizeof(*p_filters));
657 return ECORE_SUCCESS;
660 static enum _ecore_status_t ecore_abs_ppfid(struct ecore_dev *p_dev,
661 u8 rel_ppfid, u8 *p_abs_ppfid)
663 struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
664 u8 ppfids = p_llh_info->num_ppfid - 1;
666 if (rel_ppfid >= p_llh_info->num_ppfid) {
667 DP_NOTICE(p_dev, false,
668 "rel_ppfid %d is not valid, available indices are 0..%hhd\n",
673 *p_abs_ppfid = p_llh_info->ppfid_array[rel_ppfid];
675 return ECORE_SUCCESS;
678 static enum _ecore_status_t
679 __ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
681 struct ecore_dev *p_dev = p_hwfn->p_dev;
684 enum _ecore_status_t rc;
686 rc = ecore_mcp_get_engine_config(p_hwfn, p_ptt);
687 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
688 DP_NOTICE(p_hwfn, false,
689 "Failed to get the engine affinity configuration\n");
693 /* RoCE PF is bound to a single engine */
694 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
695 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
696 rc = ecore_llh_set_roce_affinity(p_dev, eng);
697 if (rc != ECORE_SUCCESS) {
698 DP_NOTICE(p_dev, false,
699 "Failed to set the RoCE engine affinity\n");
703 DP_VERBOSE(p_dev, ECORE_MSG_SP,
704 "LLH: Set the engine affinity of RoCE packets as %d\n",
708 /* Storage PF is bound to a single engine while L2 PF uses both */
709 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
710 ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
711 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
712 else /* L2_PERSONALITY */
713 eng = ECORE_BOTH_ENG;
715 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
716 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
717 if (rc != ECORE_SUCCESS) {
718 DP_NOTICE(p_dev, false,
719 "Failed to set the engine affinity of ppfid %d\n",
725 DP_VERBOSE(p_dev, ECORE_MSG_SP,
726 "LLH: Set the engine affinity of non-RoCE packets as %d\n",
729 return ECORE_SUCCESS;
732 static enum _ecore_status_t
733 ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
734 bool avoid_eng_affin)
736 struct ecore_dev *p_dev = p_hwfn->p_dev;
737 enum _ecore_status_t rc;
739 /* Backwards compatible mode:
740 * - RoCE packets - Use engine 0.
741 * - Non-RoCE packets - Use connection based classification for L2 PFs,
742 * and engine 0 otherwise.
744 if (avoid_eng_affin) {
748 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
750 rc = ecore_llh_set_roce_affinity(p_dev, eng);
751 if (rc != ECORE_SUCCESS) {
752 DP_NOTICE(p_dev, false,
753 "Failed to set the RoCE engine affinity\n");
757 DP_VERBOSE(p_dev, ECORE_MSG_SP,
758 "LLH [backwards compatible mode]: Set the engine affinity of RoCE packets as %d\n",
762 eng = (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
763 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) ? ECORE_ENG0
765 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
766 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
767 if (rc != ECORE_SUCCESS) {
768 DP_NOTICE(p_dev, false,
769 "Failed to set the engine affinity of ppfid %d\n",
775 DP_VERBOSE(p_dev, ECORE_MSG_SP,
776 "LLH [backwards compatible mode]: Set the engine affinity of non-RoCE packets as %d\n",
779 return ECORE_SUCCESS;
782 return __ecore_llh_set_engine_affin(p_hwfn, p_ptt);
785 static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,
786 struct ecore_ptt *p_ptt,
787 bool avoid_eng_affin)
789 struct ecore_dev *p_dev = p_hwfn->p_dev;
791 enum _ecore_status_t rc;
793 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
796 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
797 if (rc != ECORE_SUCCESS)
800 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
801 ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
804 if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
805 !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
806 rc = ecore_llh_add_mac_filter(p_dev, 0,
807 p_hwfn->hw_info.hw_mac_addr);
808 if (rc != ECORE_SUCCESS)
809 DP_NOTICE(p_dev, false,
810 "Failed to add an LLH filter with the primary MAC\n");
813 if (ECORE_IS_CMT(p_dev)) {
814 rc = ecore_llh_set_engine_affin(p_hwfn, p_ptt, avoid_eng_affin);
815 if (rc != ECORE_SUCCESS)
819 return ECORE_SUCCESS;
822 u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev)
824 return p_dev->p_llh_info->num_ppfid;
827 enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev)
829 return p_dev->l2_affin_hint ? ECORE_ENG1 : ECORE_ENG0;
832 /* TBD - should be removed when these definitions are available in reg_addr.h */
833 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3
834 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0
835 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3
836 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2
838 enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,
839 u8 ppfid, enum ecore_eng eng)
841 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
842 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
843 u32 addr, val, eng_sel;
844 enum _ecore_status_t rc = ECORE_SUCCESS;
847 if (p_ptt == OSAL_NULL)
850 if (!ECORE_IS_CMT(p_dev))
853 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
854 if (rc != ECORE_SUCCESS)
868 DP_NOTICE(p_dev, false,
869 "Invalid affinity value for ppfid [%d]\n", eng);
874 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
875 val = ecore_rd(p_hwfn, p_ptt, addr);
876 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
877 ecore_wr(p_hwfn, p_ptt, addr, val);
879 /* The iWARP affinity is set as the affinity of ppfid 0 */
880 if (!ppfid && ECORE_IS_IWARP_PERSONALITY(p_hwfn))
881 p_dev->iwarp_affin = (eng == ECORE_ENG1) ? 1 : 0;
883 ecore_ptt_release(p_hwfn, p_ptt);
888 enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,
891 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
892 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
893 u32 addr, val, eng_sel;
894 enum _ecore_status_t rc = ECORE_SUCCESS;
897 if (p_ptt == OSAL_NULL)
900 if (!ECORE_IS_CMT(p_dev))
912 ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
913 0xf /* QP bit 15 */);
916 DP_NOTICE(p_dev, false,
917 "Invalid affinity value for RoCE [%d]\n", eng);
922 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
923 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
924 if (rc != ECORE_SUCCESS)
927 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
928 val = ecore_rd(p_hwfn, p_ptt, addr);
929 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
930 ecore_wr(p_hwfn, p_ptt, addr, val);
933 ecore_ptt_release(p_hwfn, p_ptt);
938 struct ecore_llh_filter_e4_details {
946 static enum _ecore_status_t
947 ecore_llh_access_filter_e4(struct ecore_hwfn *p_hwfn,
948 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,
949 struct ecore_llh_filter_e4_details *p_details,
952 u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
953 struct ecore_dmae_params params;
954 enum _ecore_status_t rc;
957 /* The NIG/LLH registers that are accessed in this function have only 16
958 * rows which are exposed to a PF. I.e. only the 16 filters of its
960 * Accessing filters of other ppfids requires pretending to other PFs,
961 * and thus the usage of the ecore_ppfid_rd/wr() functions.
964 /* Filter enable - should be done first when removing a filter */
965 if (b_write_access && !p_details->enable) {
966 addr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4;
967 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
972 addr = NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 2 * filter_idx * 0x4;
973 OSAL_MEMSET(¶ms, 0, sizeof(params));
975 if (b_write_access) {
976 params.flags = ECORE_DMAE_FLAG_PF_DST;
977 params.dst_pfid = pfid;
978 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
979 (u64)(osal_uintptr_t)&p_details->value,
980 addr, 2 /* size_in_dwords */, ¶ms);
982 params.flags = ECORE_DMAE_FLAG_PF_SRC |
983 ECORE_DMAE_FLAG_COMPLETION_DST;
984 params.src_pfid = pfid;
985 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr,
986 (u64)(osal_uintptr_t)&p_details->value,
987 2 /* size_in_dwords */, ¶ms);
990 if (rc != ECORE_SUCCESS)
994 addr = NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + filter_idx * 0x4;
996 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, p_details->mode);
998 p_details->mode = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1001 /* Filter protocol type */
1002 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + filter_idx * 0x4;
1004 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1005 p_details->protocol_type);
1007 p_details->protocol_type = ecore_ppfid_rd(p_hwfn, p_ptt,
1010 /* Filter header select */
1011 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 + filter_idx * 0x4;
1013 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1014 p_details->hdr_sel);
1016 p_details->hdr_sel = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1019 /* Filter enable - should be done last when adding a filter */
1020 if (!b_write_access || p_details->enable) {
1021 addr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4;
1023 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1026 p_details->enable = ecore_ppfid_rd(p_hwfn, p_ptt,
1030 return ECORE_SUCCESS;
1033 static enum _ecore_status_t
1034 ecore_llh_add_filter_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1035 u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type,
1038 struct ecore_llh_filter_e4_details filter_details;
1040 filter_details.enable = 1;
1041 filter_details.value = ((u64)high << 32) | low;
1042 filter_details.hdr_sel =
1043 OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
1044 1 : /* inner/encapsulated header */
1045 0; /* outer/tunnel header */
1046 filter_details.protocol_type = filter_prot_type;
1047 filter_details.mode = filter_prot_type ?
1048 1 : /* protocol-based classification */
1049 0; /* MAC-address based classification */
1051 return ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1053 true /* write access */);
1056 static enum _ecore_status_t
1057 ecore_llh_remove_filter_e4(struct ecore_hwfn *p_hwfn,
1058 struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
1060 struct ecore_llh_filter_e4_details filter_details;
1062 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1064 return ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1066 true /* write access */);
1069 static enum _ecore_status_t
1070 ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1071 u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type, u32 high,
1074 return ecore_llh_add_filter_e4(p_hwfn, p_ptt, abs_ppfid,
1075 filter_idx, filter_prot_type,
1079 static enum _ecore_status_t
1080 ecore_llh_remove_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1081 u8 abs_ppfid, u8 filter_idx)
1083 return ecore_llh_remove_filter_e4(p_hwfn, p_ptt, abs_ppfid,
1087 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1088 u8 mac_addr[ETH_ALEN])
1090 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1091 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1092 union ecore_llh_filter filter;
1093 u8 filter_idx, abs_ppfid;
1094 u32 high, low, ref_cnt;
1095 enum _ecore_status_t rc = ECORE_SUCCESS;
1097 if (p_ptt == OSAL_NULL)
1100 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1103 OSAL_MEM_ZERO(&filter, sizeof(filter));
1104 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1105 rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1106 ECORE_LLH_FILTER_TYPE_MAC,
1107 &filter, &filter_idx, &ref_cnt);
1108 if (rc != ECORE_SUCCESS)
1111 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1112 if (rc != ECORE_SUCCESS)
1115 /* Configure the LLH only in case of a new the filter */
1117 high = mac_addr[1] | (mac_addr[0] << 8);
1118 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1119 (mac_addr[2] << 24);
1120 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1122 if (rc != ECORE_SUCCESS)
1126 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1127 "LLH: Added MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1128 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1129 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1135 DP_NOTICE(p_dev, false,
1136 "LLH: Failed to add MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd\n",
1137 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1138 mac_addr[4], mac_addr[5], ppfid);
1140 ecore_ptt_release(p_hwfn, p_ptt);
1145 static enum _ecore_status_t
1146 ecore_llh_protocol_filter_stringify(struct ecore_dev *p_dev,
1147 enum ecore_llh_prot_filter_type_t type,
1148 u16 source_port_or_eth_type, u16 dest_port,
1149 char *str, osal_size_t str_len)
1152 case ECORE_LLH_FILTER_ETHERTYPE:
1153 OSAL_SNPRINTF(str, str_len, "Ethertype 0x%04x",
1154 source_port_or_eth_type);
1156 case ECORE_LLH_FILTER_TCP_SRC_PORT:
1157 OSAL_SNPRINTF(str, str_len, "TCP src port 0x%04x",
1158 source_port_or_eth_type);
1160 case ECORE_LLH_FILTER_UDP_SRC_PORT:
1161 OSAL_SNPRINTF(str, str_len, "UDP src port 0x%04x",
1162 source_port_or_eth_type);
1164 case ECORE_LLH_FILTER_TCP_DEST_PORT:
1165 OSAL_SNPRINTF(str, str_len, "TCP dst port 0x%04x", dest_port);
1167 case ECORE_LLH_FILTER_UDP_DEST_PORT:
1168 OSAL_SNPRINTF(str, str_len, "UDP dst port 0x%04x", dest_port);
1170 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1171 OSAL_SNPRINTF(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1172 source_port_or_eth_type, dest_port);
1174 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1175 OSAL_SNPRINTF(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1176 source_port_or_eth_type, dest_port);
1179 DP_NOTICE(p_dev, true,
1180 "Non valid LLH protocol filter type %d\n", type);
1184 return ECORE_SUCCESS;
1187 static enum _ecore_status_t
1188 ecore_llh_protocol_filter_to_hilo(struct ecore_dev *p_dev,
1189 enum ecore_llh_prot_filter_type_t type,
1190 u16 source_port_or_eth_type, u16 dest_port,
1191 u32 *p_high, u32 *p_low)
1197 case ECORE_LLH_FILTER_ETHERTYPE:
1198 *p_high = source_port_or_eth_type;
1200 case ECORE_LLH_FILTER_TCP_SRC_PORT:
1201 case ECORE_LLH_FILTER_UDP_SRC_PORT:
1202 *p_low = source_port_or_eth_type << 16;
1204 case ECORE_LLH_FILTER_TCP_DEST_PORT:
1205 case ECORE_LLH_FILTER_UDP_DEST_PORT:
1208 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1209 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1210 *p_low = (source_port_or_eth_type << 16) | dest_port;
1213 DP_NOTICE(p_dev, true,
1214 "Non valid LLH protocol filter type %d\n", type);
1218 return ECORE_SUCCESS;
1221 enum _ecore_status_t
1222 ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1223 enum ecore_llh_prot_filter_type_t type,
1224 u16 source_port_or_eth_type, u16 dest_port)
1226 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1227 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1228 u8 filter_idx, abs_ppfid, type_bitmap;
1230 union ecore_llh_filter filter;
1231 u32 high, low, ref_cnt;
1232 enum _ecore_status_t rc = ECORE_SUCCESS;
1234 if (p_ptt == OSAL_NULL)
1237 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1240 rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1241 source_port_or_eth_type,
1242 dest_port, str, sizeof(str));
1243 if (rc != ECORE_SUCCESS)
1246 OSAL_MEM_ZERO(&filter, sizeof(filter));
1247 filter.protocol.type = type;
1248 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1249 filter.protocol.dest_port = dest_port;
1250 rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1251 ECORE_LLH_FILTER_TYPE_PROTOCOL,
1252 &filter, &filter_idx, &ref_cnt);
1253 if (rc != ECORE_SUCCESS)
1256 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1257 if (rc != ECORE_SUCCESS)
1260 /* Configure the LLH only in case of a new the filter */
1262 rc = ecore_llh_protocol_filter_to_hilo(p_dev, type,
1263 source_port_or_eth_type,
1264 dest_port, &high, &low);
1265 if (rc != ECORE_SUCCESS)
1268 type_bitmap = 0x1 << type;
1269 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1270 type_bitmap, high, low);
1271 if (rc != ECORE_SUCCESS)
1275 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1276 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1277 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1282 DP_NOTICE(p_hwfn, false,
1283 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1286 ecore_ptt_release(p_hwfn, p_ptt);
1291 void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1292 u8 mac_addr[ETH_ALEN])
1294 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1295 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1296 union ecore_llh_filter filter;
1297 u8 filter_idx, abs_ppfid;
1298 enum _ecore_status_t rc = ECORE_SUCCESS;
1301 if (p_ptt == OSAL_NULL)
1304 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1307 OSAL_MEM_ZERO(&filter, sizeof(filter));
1308 OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1309 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1311 if (rc != ECORE_SUCCESS)
1314 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1315 if (rc != ECORE_SUCCESS)
1318 /* Remove from the LLH in case the filter is not in use */
1320 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1322 if (rc != ECORE_SUCCESS)
1326 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1327 "LLH: Removed MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1328 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1329 mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1335 DP_NOTICE(p_dev, false,
1336 "LLH: Failed to remove MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd\n",
1337 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1338 mac_addr[4], mac_addr[5], ppfid);
1340 ecore_ptt_release(p_hwfn, p_ptt);
1343 void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1344 enum ecore_llh_prot_filter_type_t type,
1345 u16 source_port_or_eth_type,
1348 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1349 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1350 u8 filter_idx, abs_ppfid;
1352 union ecore_llh_filter filter;
1353 enum _ecore_status_t rc = ECORE_SUCCESS;
1356 if (p_ptt == OSAL_NULL)
1359 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1362 rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1363 source_port_or_eth_type,
1364 dest_port, str, sizeof(str));
1365 if (rc != ECORE_SUCCESS)
1368 OSAL_MEM_ZERO(&filter, sizeof(filter));
1369 filter.protocol.type = type;
1370 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1371 filter.protocol.dest_port = dest_port;
1372 rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1374 if (rc != ECORE_SUCCESS)
1377 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1378 if (rc != ECORE_SUCCESS)
1381 /* Remove from the LLH in case the filter is not in use */
1383 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1385 if (rc != ECORE_SUCCESS)
1389 DP_VERBOSE(p_dev, ECORE_MSG_SP,
1390 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1391 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1396 DP_NOTICE(p_dev, false,
1397 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1400 ecore_ptt_release(p_hwfn, p_ptt);
1403 void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)
1405 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1406 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1407 u8 filter_idx, abs_ppfid;
1408 enum _ecore_status_t rc = ECORE_SUCCESS;
1410 if (p_ptt == OSAL_NULL)
1413 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1414 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1417 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1418 if (rc != ECORE_SUCCESS)
1421 rc = ecore_llh_shadow_remove_all_filters(p_dev, ppfid);
1422 if (rc != ECORE_SUCCESS)
1425 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1427 rc = ecore_llh_remove_filter_e4(p_hwfn, p_ptt,
1428 abs_ppfid, filter_idx);
1429 if (rc != ECORE_SUCCESS)
1433 ecore_ptt_release(p_hwfn, p_ptt);
1436 void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)
1440 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1441 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1444 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
1445 ecore_llh_clear_ppfid_filters(p_dev, ppfid);
1448 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1449 struct ecore_ptt *p_ptt, u32 addr,
1452 struct ecore_dev *p_dev = p_hwfn->p_dev;
1453 u8 ppfid, abs_ppfid;
1454 enum _ecore_status_t rc;
1456 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1457 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1458 if (rc != ECORE_SUCCESS)
1461 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, val);
1464 return ECORE_SUCCESS;
1467 static enum _ecore_status_t
1468 ecore_llh_dump_ppfid_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1471 struct ecore_llh_filter_e4_details filter_details;
1472 u8 abs_ppfid, filter_idx;
1474 enum _ecore_status_t rc;
1476 rc = ecore_abs_ppfid(p_hwfn->p_dev, ppfid, &abs_ppfid);
1477 if (rc != ECORE_SUCCESS)
1480 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
1481 DP_NOTICE(p_hwfn, false,
1482 "[rel_pf_id %hhd, ppfid={rel %hhd, abs %hhd}, engine_sel 0x%x]\n",
1483 p_hwfn->rel_pf_id, ppfid, abs_ppfid,
1484 ecore_rd(p_hwfn, p_ptt, addr));
1486 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1488 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1489 rc = ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid,
1490 filter_idx, &filter_details,
1491 false /* read access */);
1492 if (rc != ECORE_SUCCESS)
1495 DP_NOTICE(p_hwfn, false,
1496 "filter %2hhd: enable %d, value 0x%016lx, mode %d, protocol_type 0x%x, hdr_sel 0x%x\n",
1497 filter_idx, filter_details.enable,
1498 (unsigned long)filter_details.value,
1499 filter_details.mode,
1500 filter_details.protocol_type, filter_details.hdr_sel);
1503 return ECORE_SUCCESS;
1506 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid)
1508 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1509 struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1510 enum _ecore_status_t rc;
1512 if (p_ptt == OSAL_NULL)
1515 rc = ecore_llh_dump_ppfid_e4(p_hwfn, p_ptt, ppfid);
1517 ecore_ptt_release(p_hwfn, p_ptt);
1522 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev)
1525 enum _ecore_status_t rc;
1527 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1528 rc = ecore_llh_dump_ppfid(p_dev, ppfid);
1529 if (rc != ECORE_SUCCESS)
1533 return ECORE_SUCCESS;
1536 /******************************* NIG LLH - End ********************************/
1539 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
1540 * load the driver. The number was
1545 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
1547 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
1548 struct ecore_ptt *p_ptt,
1551 u32 bar_reg = (bar_id == BAR_ID_0 ?
1552 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1555 if (IS_VF(p_hwfn->p_dev))
1556 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
1558 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
1560 return 1 << (val + 15);
1562 /* The above registers were updated in the past only in CMT mode. Since
1563 * they were found to be useful MFW started updating them from 8.7.7.0.
1564 * In older MFW versions they are set to 0 which means disabled.
1566 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
1568 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1569 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1572 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1579 void ecore_init_dp(struct ecore_dev *p_dev,
1580 u32 dp_module, u8 dp_level, void *dp_ctx)
1584 p_dev->dp_level = dp_level;
1585 p_dev->dp_module = dp_module;
1586 p_dev->dp_ctx = dp_ctx;
1587 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1588 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1590 p_hwfn->dp_level = dp_level;
1591 p_hwfn->dp_module = dp_module;
1592 p_hwfn->dp_ctx = dp_ctx;
1596 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
1600 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1601 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1603 p_hwfn->p_dev = p_dev;
1605 p_hwfn->b_active = false;
1607 #ifdef CONFIG_ECORE_LOCK_ALLOC
1608 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
1611 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
1614 /* hwfn 0 is always active */
1615 p_dev->hwfns[0].b_active = true;
1617 /* set the default cache alignment to 128 (may be overridden later) */
1618 p_dev->cache_shift = 7;
1619 return ECORE_SUCCESS;
1620 #ifdef CONFIG_ECORE_LOCK_ALLOC
1623 struct ecore_hwfn *p_hwfn = OSAL_NULL;
1625 p_hwfn = &p_dev->hwfns[i];
1626 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
1632 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
1634 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1636 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
1637 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
1638 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
1639 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
1642 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
1644 OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
1645 p_hwfn->dbg_user_info = OSAL_NULL;
1648 void ecore_resc_free(struct ecore_dev *p_dev)
1653 for_each_hwfn(p_dev, i)
1654 ecore_l2_free(&p_dev->hwfns[i]);
1658 OSAL_FREE(p_dev, p_dev->fw_data);
1660 OSAL_FREE(p_dev, p_dev->reset_stats);
1662 ecore_llh_free(p_dev);
1664 for_each_hwfn(p_dev, i) {
1665 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1667 ecore_cxt_mngr_free(p_hwfn);
1668 ecore_qm_info_free(p_hwfn);
1669 ecore_spq_free(p_hwfn);
1670 ecore_eq_free(p_hwfn);
1671 ecore_consq_free(p_hwfn);
1672 ecore_int_free(p_hwfn);
1673 ecore_iov_free(p_hwfn);
1674 ecore_l2_free(p_hwfn);
1675 ecore_dmae_info_free(p_hwfn);
1676 ecore_dcbx_info_free(p_hwfn);
1677 ecore_dbg_user_data_free(p_hwfn);
1678 /* @@@TBD Flush work-queue ? */
1680 /* destroy doorbell recovery mechanism */
1681 ecore_db_recovery_teardown(p_hwfn);
1685 /******************** QM initialization *******************/
1687 /* bitmaps for indicating active traffic classes.
1688 * Special case for Arrowhead 4 port
1690 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
1691 #define ACTIVE_TCS_BMAP 0x9f
1692 /* 0..3 actually used, OOO and high priority stuff all use 3 */
1693 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1695 /* determines the physical queue flags for a given PF. */
1696 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
1701 flags = PQ_FLAGS_LB;
1704 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
1705 flags |= PQ_FLAGS_VFS;
1706 if (IS_ECORE_PACING(p_hwfn))
1707 flags |= PQ_FLAGS_RLS;
1709 /* protocol flags */
1710 switch (p_hwfn->hw_info.personality) {
1712 if (!IS_ECORE_PACING(p_hwfn))
1713 flags |= PQ_FLAGS_MCOS;
1715 case ECORE_PCI_FCOE:
1716 flags |= PQ_FLAGS_OFLD;
1718 case ECORE_PCI_ISCSI:
1719 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1721 case ECORE_PCI_ETH_ROCE:
1722 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1723 if (!IS_ECORE_PACING(p_hwfn))
1724 flags |= PQ_FLAGS_MCOS;
1726 case ECORE_PCI_ETH_IWARP:
1727 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1728 if (!IS_ECORE_PACING(p_hwfn))
1729 flags |= PQ_FLAGS_MCOS;
1732 DP_ERR(p_hwfn, "unknown personality %d\n",
1733 p_hwfn->hw_info.personality);
1739 /* Getters for resource amounts necessary for qm initialization */
1740 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
1742 return p_hwfn->hw_info.num_hw_tc;
1745 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
1747 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
1748 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
1751 #define NUM_DEFAULT_RLS 1
1753 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
1755 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
1757 /* num RLs can't exceed resource amount of rls or vports or the
1760 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
1761 RESC_NUM(p_hwfn, ECORE_VPORT));
1763 /* make sure after we reserve the default and VF rls we'll have
1766 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
1767 DP_NOTICE(p_hwfn, false,
1768 "no rate limiters left for PF rate limiting"
1769 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
1773 /* subtract rls necessary for VFs and one default one for the PF */
1774 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1779 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
1781 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1783 /* all pqs share the same vport (hence the 1 below), except for vfs
1786 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1787 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1788 (!!(PQ_FLAGS_VFS & pq_flags)) *
1789 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
1792 /* calc amount of PQs according to the requested flags */
1793 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
1795 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1797 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1798 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1799 (!!(PQ_FLAGS_MCOS & pq_flags)) *
1800 ecore_init_qm_get_num_tcs(p_hwfn) +
1801 (!!(PQ_FLAGS_LB & pq_flags)) +
1802 (!!(PQ_FLAGS_OOO & pq_flags)) +
1803 (!!(PQ_FLAGS_ACK & pq_flags)) +
1804 (!!(PQ_FLAGS_OFLD & pq_flags)) +
1805 (!!(PQ_FLAGS_VFS & pq_flags)) *
1806 ecore_init_qm_get_num_vfs(p_hwfn);
1809 /* initialize the top level QM params */
1810 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
1812 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1815 /* pq and vport bases for this PF */
1816 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
1817 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
1819 /* rate limiting and weighted fair queueing are always enabled */
1820 qm_info->vport_rl_en = 1;
1821 qm_info->vport_wfq_en = 1;
1823 /* TC config is different for AH 4 port */
1824 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1826 /* in AH 4 port we have fewer TCs per port */
1827 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1830 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
1833 if (!qm_info->ooo_tc)
1834 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1838 /* initialize qm vport params */
1839 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
1841 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1844 /* all vports participate in weighted fair queueing */
1845 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
1846 qm_info->qm_vport_params[i].vport_wfq = 1;
1849 /* initialize qm port params */
1850 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
1852 /* Initialize qm port parameters */
1853 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
1855 /* indicate how ooo and high pri traffic is dealt with */
1856 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1857 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
1859 for (i = 0; i < num_ports; i++) {
1860 struct init_qm_port_params *p_qm_port =
1861 &p_hwfn->qm_info.qm_port_params[i];
1863 p_qm_port->active = 1;
1864 p_qm_port->active_phys_tcs = active_phys_tcs;
1865 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
1866 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
1870 /* Reset the params which must be reset for qm init. QM init may be called as
1871 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1872 * params may be affected by the init but would simply recalculate to the same
1873 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1874 * affected as these amounts stay the same.
1876 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
1878 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1880 qm_info->num_pqs = 0;
1881 qm_info->num_vports = 0;
1882 qm_info->num_pf_rls = 0;
1883 qm_info->num_vf_pqs = 0;
1884 qm_info->first_vf_pq = 0;
1885 qm_info->first_mcos_pq = 0;
1886 qm_info->first_rl_pq = 0;
1889 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
1891 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1893 qm_info->num_vports++;
1895 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1897 "vport overflow! qm_info->num_vports %d,"
1898 " qm_init_get_num_vports() %d\n",
1899 qm_info->num_vports,
1900 ecore_init_qm_get_num_vports(p_hwfn));
1903 /* initialize a single pq and manage qm_info resources accounting.
1904 * The pq_init_flags param determines whether the PQ is rate limited
1906 * and whether a new vport is allocated to the pq or not (i.e. vport will be
1910 /* flags for pq init */
1911 #define PQ_INIT_SHARE_VPORT (1 << 0)
1912 #define PQ_INIT_PF_RL (1 << 1)
1913 #define PQ_INIT_VF_RL (1 << 2)
1915 /* defines for pq init */
1916 #define PQ_INIT_DEFAULT_WRR_GROUP 1
1917 #define PQ_INIT_DEFAULT_TC 0
1918 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
1920 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
1921 struct ecore_qm_info *qm_info,
1922 u8 tc, u32 pq_init_flags)
1924 u16 pq_idx = qm_info->num_pqs, max_pq =
1925 ecore_init_qm_get_num_pqs(p_hwfn);
1927 if (pq_idx > max_pq)
1929 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1931 /* init pq params */
1932 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1933 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1934 qm_info->num_vports;
1935 qm_info->qm_pq_params[pq_idx].tc_id = tc;
1936 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1937 qm_info->qm_pq_params[pq_idx].rl_valid =
1938 (pq_init_flags & PQ_INIT_PF_RL ||
1939 pq_init_flags & PQ_INIT_VF_RL);
1941 /* qm params accounting */
1943 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1944 qm_info->num_vports++;
1946 if (pq_init_flags & PQ_INIT_PF_RL)
1947 qm_info->num_pf_rls++;
1949 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1951 "vport overflow! qm_info->num_vports %d,"
1952 " qm_init_get_num_vports() %d\n",
1953 qm_info->num_vports,
1954 ecore_init_qm_get_num_vports(p_hwfn));
1956 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
1957 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
1958 " qm_init_get_num_pf_rls() %d\n",
1959 qm_info->num_pf_rls,
1960 ecore_init_qm_get_num_pf_rls(p_hwfn));
1963 /* get pq index according to PQ_FLAGS */
1964 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
1967 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1969 /* Can't have multiple flags set here */
1970 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
1971 sizeof(pq_flags)) > 1)
1976 return &qm_info->first_rl_pq;
1978 return &qm_info->first_mcos_pq;
1980 return &qm_info->pure_lb_pq;
1982 return &qm_info->ooo_pq;
1984 return &qm_info->pure_ack_pq;
1986 return &qm_info->offload_pq;
1988 return &qm_info->first_vf_pq;
1994 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
1998 /* save pq index in qm info */
1999 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
2000 u32 pq_flags, u16 pq_val)
2002 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
2004 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
2007 /* get tx pq index, with the PQ TX base already set (ready for context init) */
2008 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
2010 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
2012 return *base_pq_idx + CM_TX_PQ_BASE;
2015 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
2017 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
2020 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
2022 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
2025 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
2027 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
2030 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
2032 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
2035 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2037 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
2039 /* for rate limiters, it is okay to use the modulo behavior - no
2042 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl);
2045 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2047 u16 start_pq, pq, qm_pq_idx;
2049 pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
2050 start_pq = p_hwfn->qm_info.start_pq;
2051 qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
2053 if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
2055 "qm_pq_idx %d must be smaller than %d\n",
2056 qm_pq_idx, p_hwfn->qm_info.num_pqs);
2059 return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
2062 /* Functions for creating specific types of pqs */
2063 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
2065 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2067 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
2070 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
2071 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
2074 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
2076 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2078 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
2081 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
2082 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
2085 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
2087 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2089 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
2092 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
2093 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2096 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
2098 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2100 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
2103 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
2104 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2107 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
2109 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2112 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
2115 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
2116 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
2117 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
2120 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
2122 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2123 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
2125 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
2128 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
2130 qm_info->num_vf_pqs = num_vfs;
2131 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
2132 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
2136 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
2138 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
2139 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2141 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
2144 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
2145 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
2146 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
2150 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
2152 /* rate limited pqs, must come first (FW assumption) */
2153 ecore_init_qm_rl_pqs(p_hwfn);
2155 /* pqs for multi cos */
2156 ecore_init_qm_mcos_pqs(p_hwfn);
2158 /* pure loopback pq */
2159 ecore_init_qm_lb_pq(p_hwfn);
2161 /* out of order pq */
2162 ecore_init_qm_ooo_pq(p_hwfn);
2165 ecore_init_qm_pure_ack_pq(p_hwfn);
2167 /* pq for offloaded protocol */
2168 ecore_init_qm_offload_pq(p_hwfn);
2170 /* done sharing vports */
2171 ecore_init_qm_advance_vport(p_hwfn);
2174 ecore_init_qm_vf_pqs(p_hwfn);
2177 /* compare values of getters against resources amounts */
2178 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
2180 if (ecore_init_qm_get_num_vports(p_hwfn) >
2181 RESC_NUM(p_hwfn, ECORE_VPORT)) {
2182 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
2186 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
2187 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
2191 return ECORE_SUCCESS;
2195 * Function for verbose printing of the qm initialization results
2197 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
2199 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2200 struct init_qm_vport_params *vport;
2201 struct init_qm_port_params *port;
2202 struct init_qm_pq_params *pq;
2205 /* top level params */
2206 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2207 "qm init top level params: start_pq %d, start_vport %d,"
2208 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
2209 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
2210 qm_info->offload_pq, qm_info->pure_ack_pq);
2211 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2212 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
2213 " num_vports %d, max_phys_tcs_per_port %d\n",
2214 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
2215 qm_info->num_vf_pqs, qm_info->num_vports,
2216 qm_info->max_phys_tcs_per_port);
2217 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2218 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
2219 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2220 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
2221 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
2222 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
2225 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
2226 port = &qm_info->qm_port_params[i];
2227 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2228 "port idx %d, active %d, active_phys_tcs %d,"
2229 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
2231 i, port->active, port->active_phys_tcs,
2232 port->num_pbf_cmd_lines, port->num_btb_blocks,
2237 for (i = 0; i < qm_info->num_vports; i++) {
2238 vport = &qm_info->qm_vport_params[i];
2239 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2240 "vport idx %d, vport_rl %d, wfq %d,"
2241 " first_tx_pq_id [ ",
2242 qm_info->start_vport + i, vport->vport_rl,
2244 for (tc = 0; tc < NUM_OF_TCS; tc++)
2245 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
2246 vport->first_tx_pq_id[tc]);
2247 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
2251 for (i = 0; i < qm_info->num_pqs; i++) {
2252 pq = &qm_info->qm_pq_params[i];
2253 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2254 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
2255 qm_info->start_pq + i, pq->port_id, pq->vport_id,
2256 pq->tc_id, pq->wrr_group, pq->rl_valid);
2260 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
2262 /* reset params required for init run */
2263 ecore_init_qm_reset_params(p_hwfn);
2265 /* init QM top level params */
2266 ecore_init_qm_params(p_hwfn);
2268 /* init QM port params */
2269 ecore_init_qm_port_params(p_hwfn);
2271 /* init QM vport params */
2272 ecore_init_qm_vport_params(p_hwfn);
2274 /* init QM physical queue params */
2275 ecore_init_qm_pq_params(p_hwfn);
2277 /* display all that init */
2278 ecore_dp_init_qm_params(p_hwfn);
2281 /* This function reconfigures the QM pf on the fly.
2282 * For this purpose we:
2283 * 1. reconfigure the QM database
2284 * 2. set new values to runtime array
2285 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2286 * 4. activate init tool in QM_PF stage
2287 * 5. send an sdm_qm_cmd through rbc interface to release the QM
2289 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
2290 struct ecore_ptt *p_ptt)
2292 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2294 enum _ecore_status_t rc = ECORE_SUCCESS;
2296 /* multiple flows can issue qm reconf. Need to lock */
2297 OSAL_SPIN_LOCK(&qm_lock);
2299 /* initialize ecore's qm data structure */
2300 ecore_init_qm_info(p_hwfn);
2302 /* stop PF's qm queues */
2303 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2304 qm_info->start_pq, qm_info->num_pqs);
2310 /* clear the QM_PF runtime phase leftovers from previous init */
2311 ecore_init_clear_rt_data(p_hwfn);
2313 /* prepare QM portion of runtime array */
2314 ecore_qm_init_pf(p_hwfn, p_ptt, false);
2316 /* activate init tool on runtime array */
2317 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2318 p_hwfn->hw_info.hw_mode);
2320 /* start PF's qm queues */
2321 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2322 qm_info->start_pq, qm_info->num_pqs);
2327 OSAL_SPIN_UNLOCK(&qm_lock);
2332 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
2334 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2335 enum _ecore_status_t rc;
2337 rc = ecore_init_qm_sanity(p_hwfn);
2338 if (rc != ECORE_SUCCESS)
2341 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2342 sizeof(struct init_qm_pq_params) *
2343 ecore_init_qm_get_num_pqs(p_hwfn));
2344 if (!qm_info->qm_pq_params)
2347 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2348 sizeof(struct init_qm_vport_params) *
2349 ecore_init_qm_get_num_vports(p_hwfn));
2350 if (!qm_info->qm_vport_params)
2353 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2354 sizeof(struct init_qm_port_params) *
2355 p_hwfn->p_dev->num_ports_in_engine);
2356 if (!qm_info->qm_port_params)
2359 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2360 sizeof(struct ecore_wfq_data) *
2361 ecore_init_qm_get_num_vports(p_hwfn));
2362 if (!qm_info->wfq_data)
2365 return ECORE_SUCCESS;
2368 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
2369 ecore_qm_info_free(p_hwfn);
2372 /******************** End QM initialization ***************/
2374 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
2376 enum _ecore_status_t rc = ECORE_SUCCESS;
2380 for_each_hwfn(p_dev, i) {
2381 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
2382 if (rc != ECORE_SUCCESS)
2388 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2389 sizeof(*p_dev->fw_data));
2390 if (!p_dev->fw_data)
2393 for_each_hwfn(p_dev, i) {
2394 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2395 u32 n_eqes, num_cons;
2397 /* initialize the doorbell recovery mechanism */
2398 rc = ecore_db_recovery_setup(p_hwfn);
2402 /* First allocate the context manager structure */
2403 rc = ecore_cxt_mngr_alloc(p_hwfn);
2407 /* Set the HW cid/tid numbers (in the context manager)
2408 * Must be done prior to any further computations.
2410 rc = ecore_cxt_set_pf_params(p_hwfn);
2414 rc = ecore_alloc_qm_data(p_hwfn);
2419 ecore_init_qm_info(p_hwfn);
2421 /* Compute the ILT client partition */
2422 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
2426 /* CID map / ILT shadow table / T2
2427 * The talbes sizes are determined by the computations above
2429 rc = ecore_cxt_tables_alloc(p_hwfn);
2433 /* SPQ, must follow ILT because initializes SPQ context */
2434 rc = ecore_spq_alloc(p_hwfn);
2438 /* SP status block allocation */
2439 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
2442 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2446 rc = ecore_iov_alloc(p_hwfn);
2451 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
2452 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
2453 /* Calculate the EQ size
2454 * ---------------------
2455 * Each ICID may generate up to one event at a time i.e.
2456 * the event must be handled/cleared before a new one
2457 * can be generated. We calculate the sum of events per
2458 * protocol and create an EQ deep enough to handle the
2460 * - Core - according to SPQ.
2461 * - RoCE - per QP there are a couple of ICIDs, one
2462 * responder and one requester, each can
2463 * generate an EQE => n_eqes_qp = 2 * n_qp.
2464 * Each CQ can generate an EQE. There are 2 CQs
2465 * per QP => n_eqes_cq = 2 * n_qp.
2466 * Hence the RoCE total is 4 * n_qp or
2468 * - ENet - There can be up to two events per VF. One
2469 * for VF-PF channel and another for VF FLR
2470 * initial cleanup. The number of VFs is
2471 * bounded by MAX_NUM_VFS_BB, and is much
2472 * smaller than RoCE's so we avoid exact
2475 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
2477 ecore_cxt_get_proto_cid_count(
2483 num_cons = ecore_cxt_get_proto_cid_count(
2488 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
2489 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
2491 ecore_cxt_get_proto_cid_count(p_hwfn,
2494 n_eqes += 2 * num_cons;
2497 if (n_eqes > 0xFFFF) {
2498 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
2499 "The maximum of a u16 chain is 0x%x\n",
2504 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
2508 rc = ecore_consq_alloc(p_hwfn);
2512 rc = ecore_l2_alloc(p_hwfn);
2513 if (rc != ECORE_SUCCESS)
2516 /* DMA info initialization */
2517 rc = ecore_dmae_info_alloc(p_hwfn);
2519 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
2523 /* DCBX initialization */
2524 rc = ecore_dcbx_info_alloc(p_hwfn);
2526 DP_NOTICE(p_hwfn, false,
2527 "Failed to allocate memory for dcbx structure\n");
2531 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
2533 DP_NOTICE(p_hwfn, false,
2534 "Failed to allocate dbg user info structure\n");
2539 rc = ecore_llh_alloc(p_dev);
2540 if (rc != ECORE_SUCCESS) {
2541 DP_NOTICE(p_dev, true,
2542 "Failed to allocate memory for the llh_info structure\n");
2546 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2547 sizeof(*p_dev->reset_stats));
2548 if (!p_dev->reset_stats) {
2549 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
2553 return ECORE_SUCCESS;
2558 ecore_resc_free(p_dev);
2562 void ecore_resc_setup(struct ecore_dev *p_dev)
2567 for_each_hwfn(p_dev, i)
2568 ecore_l2_setup(&p_dev->hwfns[i]);
2572 for_each_hwfn(p_dev, i) {
2573 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2575 ecore_cxt_mngr_setup(p_hwfn);
2576 ecore_spq_setup(p_hwfn);
2577 ecore_eq_setup(p_hwfn);
2578 ecore_consq_setup(p_hwfn);
2580 /* Read shadow of current MFW mailbox */
2581 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2582 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2583 p_hwfn->mcp_info->mfw_mb_cur,
2584 p_hwfn->mcp_info->mfw_mb_length);
2586 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2588 ecore_l2_setup(p_hwfn);
2589 ecore_iov_setup(p_hwfn);
2593 #define FINAL_CLEANUP_POLL_CNT (100)
2594 #define FINAL_CLEANUP_POLL_TIME (10)
2595 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
2596 struct ecore_ptt *p_ptt,
2599 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2600 enum _ecore_status_t rc = ECORE_TIMEOUT;
2603 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
2604 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2605 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
2606 return ECORE_SUCCESS;
2610 addr = GTT_BAR0_MAP_REG_USDM_RAM +
2611 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2616 command |= X_FINAL_CLEANUP_AGG_INT <<
2617 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2618 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2619 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2620 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2622 /* Make sure notification is not set before initiating final cleanup */
2624 if (REG_RD(p_hwfn, addr)) {
2625 DP_NOTICE(p_hwfn, false,
2626 "Unexpected; Found final cleanup notification");
2627 DP_NOTICE(p_hwfn, false,
2628 " before initiating final cleanup\n");
2629 REG_WR(p_hwfn, addr, 0);
2632 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2633 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2636 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2638 /* Poll until completion */
2639 while (!REG_RD(p_hwfn, addr) && count--)
2640 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
2642 if (REG_RD(p_hwfn, addr))
2645 DP_NOTICE(p_hwfn, true,
2646 "Failed to receive FW final cleanup notification\n");
2648 /* Cleanup afterwards */
2649 REG_WR(p_hwfn, addr, 0);
2654 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
2658 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
2659 hw_mode |= 1 << MODE_BB;
2660 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
2661 hw_mode |= 1 << MODE_K2;
2663 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
2664 p_hwfn->p_dev->type);
2668 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
2669 switch (p_hwfn->p_dev->num_ports_in_engine) {
2671 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2674 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2677 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2680 DP_NOTICE(p_hwfn, true,
2681 "num_ports_in_engine = %d not supported\n",
2682 p_hwfn->p_dev->num_ports_in_engine);
2686 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
2687 hw_mode |= 1 << MODE_MF_SD;
2689 hw_mode |= 1 << MODE_MF_SI;
2692 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2693 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2694 hw_mode |= 1 << MODE_FPGA;
2696 if (p_hwfn->p_dev->b_is_emul_full)
2697 hw_mode |= 1 << MODE_EMUL_FULL;
2699 hw_mode |= 1 << MODE_EMUL_REDUCED;
2703 hw_mode |= 1 << MODE_ASIC;
2705 if (ECORE_IS_CMT(p_hwfn->p_dev))
2706 hw_mode |= 1 << MODE_100G;
2708 p_hwfn->hw_info.hw_mode = hw_mode;
2710 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
2711 "Configuring function for hw_mode: 0x%08x\n",
2712 p_hwfn->hw_info.hw_mode);
2714 return ECORE_SUCCESS;
2718 /* MFW-replacement initializations for non-ASIC */
2719 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
2720 struct ecore_ptt *p_ptt)
2722 struct ecore_dev *p_dev = p_hwfn->p_dev;
2726 if (CHIP_REV_IS_EMUL(p_dev)) {
2727 if (ECORE_IS_AH(p_dev))
2731 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
2733 if (CHIP_REV_IS_EMUL(p_dev) &&
2734 (ECORE_IS_AH(p_dev)))
2735 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
2738 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
2739 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
2740 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
2741 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
2743 if (CHIP_REV_IS_EMUL(p_dev)) {
2744 if (ECORE_IS_AH(p_dev)) {
2745 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
2746 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
2747 (p_dev->num_ports_in_engine >> 1));
2749 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
2750 p_dev->num_ports_in_engine == 4 ? 0 : 3);
2755 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
2756 for (i = 0; i < 100; i++) {
2758 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
2762 DP_NOTICE(p_hwfn, true,
2763 "RBC done failed to complete in PSWRQ2\n");
2765 return ECORE_SUCCESS;
2769 /* Init run time data for all PFs and their VFs on an engine.
2770 * TBD - for VFs - Once we have parent PF info for each VF in
2771 * shmem available as CAU requires knowledge of parent PF for each VF.
2773 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
2775 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2778 for_each_hwfn(p_dev, i) {
2779 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2780 struct ecore_igu_info *p_igu_info;
2781 struct ecore_igu_block *p_block;
2782 struct cau_sb_entry sb_entry;
2784 p_igu_info = p_hwfn->hw_info.p_igu_info;
2787 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
2789 p_block = &p_igu_info->entry[igu_sb_id];
2791 if (!p_block->is_pf)
2794 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
2795 p_block->function_id, 0, 0);
2796 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2802 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
2803 struct ecore_ptt *p_ptt)
2805 u32 val, wr_mbs, cache_line_size;
2807 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2820 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2825 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
2826 switch (cache_line_size) {
2841 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2845 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
2847 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2848 OSAL_CACHE_LINE_SIZE, wr_mbs);
2850 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2852 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2853 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2857 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
2858 struct ecore_ptt *p_ptt,
2861 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2862 struct ecore_dev *p_dev = p_hwfn->p_dev;
2863 u8 vf_id, max_num_vfs;
2866 enum _ecore_status_t rc = ECORE_SUCCESS;
2868 ecore_init_cau_rt_data(p_dev);
2870 /* Program GTT windows */
2871 ecore_gtt_init(p_hwfn, p_ptt);
2874 if (CHIP_REV_IS_EMUL(p_dev)) {
2875 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
2876 if (rc != ECORE_SUCCESS)
2881 if (p_hwfn->mcp_info) {
2882 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2883 qm_info->pf_rl_en = 1;
2884 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2885 qm_info->pf_wfq_en = 1;
2888 ecore_qm_common_rt_init(p_hwfn,
2889 p_dev->num_ports_in_engine,
2890 qm_info->max_phys_tcs_per_port,
2891 qm_info->pf_rl_en, qm_info->pf_wfq_en,
2892 qm_info->vport_rl_en, qm_info->vport_wfq_en,
2893 qm_info->qm_port_params);
2895 ecore_cxt_hw_init_common(p_hwfn);
2897 ecore_init_cache_line_size(p_hwfn, p_ptt);
2899 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
2901 if (rc != ECORE_SUCCESS)
2904 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
2905 * need to decide with which value, maybe runtime
2907 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2908 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2910 if (ECORE_IS_BB(p_dev)) {
2911 /* Workaround clears ROCE search for all functions to prevent
2912 * involving non initialized function in processing ROCE packet.
2914 num_pfs = NUM_OF_ENG_PFS(p_dev);
2915 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2916 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
2917 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2918 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2920 /* pretend to original PF */
2921 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2924 /* Workaround for avoiding CCFC execution error when getting packets
2925 * with CRC errors, and allowing instead the invoking of the FW error
2927 * This is not done inside the init tool since it currently can't
2928 * perform a pretending to VFs.
2930 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
2931 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2932 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
2933 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
2934 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2935 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2936 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2937 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2939 /* pretend to original PF */
2940 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2946 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
2947 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
2949 #define PMEG_IF_BYTE_COUNT 8
2951 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
2952 struct ecore_ptt *p_ptt,
2953 u32 addr, u64 data, u8 reg_type, u8 port)
2955 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2956 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
2957 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
2958 (8 << PMEG_IF_BYTE_COUNT),
2959 (reg_type << 25) | (addr << 8) | port,
2960 (u32)((data >> 32) & 0xffffffff),
2961 (u32)(data & 0xffffffff));
2963 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
2964 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
2965 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
2966 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
2967 (reg_type << 25) | (addr << 8) | port);
2968 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
2969 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
2970 (data >> 32) & 0xffffffff);
2973 #define XLPORT_MODE_REG (0x20a)
2974 #define XLPORT_MAC_CONTROL (0x210)
2975 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
2976 #define XLPORT_ENABLE_REG (0x20b)
2978 #define XLMAC_CTRL (0x600)
2979 #define XLMAC_MODE (0x601)
2980 #define XLMAC_RX_MAX_SIZE (0x608)
2981 #define XLMAC_TX_CTRL (0x604)
2982 #define XLMAC_PAUSE_CTRL (0x60d)
2983 #define XLMAC_PFC_CTRL (0x60e)
2985 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
2986 struct ecore_ptt *p_ptt)
2988 u8 loopback = 0, port = p_hwfn->port_id * 2;
2990 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
2992 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
2993 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
2995 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
2996 /* XLMAC: SOFT RESET */
2997 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
2998 /* XLMAC: Port Speed >= 10Gbps */
2999 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
3000 /* XLMAC: Max Size */
3001 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
3002 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
3003 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
3005 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
3006 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
3007 0x30ffffc000ULL, 0, port);
3008 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
3009 port); /* XLMAC: TX_EN, RX_EN */
3010 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
3011 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
3012 0x1003 | (loopback << 2), 0, port);
3013 /* Enabled Parallel PFC interface */
3014 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
3016 /* XLPORT port enable */
3017 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
3020 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
3021 struct ecore_ptt *p_ptt)
3023 u8 port = p_hwfn->port_id;
3024 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
3026 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
3028 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
3029 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
3031 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
3032 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
3034 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
3035 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
3037 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
3038 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
3040 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
3041 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
3043 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
3044 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
3046 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
3048 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
3050 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
3052 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
3056 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
3057 struct ecore_ptt *p_ptt)
3059 if (ECORE_IS_AH(p_hwfn->p_dev))
3060 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
3062 ecore_emul_link_init_bb(p_hwfn, p_ptt);
3065 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
3066 struct ecore_ptt *p_ptt, u8 port)
3068 int port_offset = port ? 0x800 : 0;
3069 u32 xmac_rxctrl = 0;
3072 /* FIXME: move to common start */
3073 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3074 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
3076 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3077 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
3079 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
3081 /* Set the number of ports on the Warp Core to 10G */
3082 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
3084 /* Soft reset of XMAC */
3085 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3086 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3088 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3089 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3091 /* FIXME: move to common end */
3092 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3093 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
3095 /* Set Max packet size: initialize XMAC block register for port 0 */
3096 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
3098 /* CRC append for Tx packets: init XMAC block register for port 1 */
3099 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
3101 /* Enable TX and RX: initialize XMAC block register for port 1 */
3102 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
3103 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
3104 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
3105 XMAC_REG_RX_CTRL_BB + port_offset);
3106 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
3107 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
3111 static enum _ecore_status_t
3112 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
3113 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
3115 u32 dpi_bit_shift, dpi_count, dpi_page_size;
3119 /* Calculate DPI size
3120 * ------------------
3121 * The PWM region contains Doorbell Pages. The first is reserverd for
3122 * the kernel for, e.g, L2. The others are free to be used by non-
3123 * trusted applications, typically from user space. Each page, called a
3124 * doorbell page is sectioned into windows that allow doorbells to be
3125 * issued in parallel by the kernel/application. The size of such a
3126 * window (a.k.a. WID) is 1kB.
3128 * 1kB WID x N WIDS = DPI page size
3129 * DPI page size x N DPIs = PWM region size
3131 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
3132 * in order to ensure that two applications won't share the same page.
3133 * It also must contain at least one WID per CPU to allow parallelism.
3134 * It also must be a power of 2, since it is stored as a bit shift.
3136 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
3137 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
3138 * containing 4 WIDs.
3140 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
3141 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
3142 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
3143 ~(OSAL_PAGE_SIZE - 1);
3144 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
3145 dpi_count = pwm_region_size / dpi_page_size;
3147 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
3148 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
3151 p_hwfn->dpi_size = dpi_page_size;
3152 p_hwfn->dpi_count = dpi_count;
3154 /* Update registers */
3155 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
3157 if (dpi_count < min_dpis)
3158 return ECORE_NORESOURCES;
3160 return ECORE_SUCCESS;
3163 enum ECORE_ROCE_EDPM_MODE {
3164 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
3165 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
3166 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
3169 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn)
3171 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
3177 static enum _ecore_status_t
3178 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
3179 struct ecore_ptt *p_ptt)
3181 u32 pwm_regsize, norm_regsize;
3182 u32 non_pwm_conn, min_addr_reg1;
3183 u32 db_bar_size, n_cpus;
3186 enum _ecore_status_t rc = ECORE_SUCCESS;
3189 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
3190 if (ECORE_IS_CMT(p_hwfn->p_dev))
3193 /* Calculate doorbell regions
3194 * -----------------------------------
3195 * The doorbell BAR is made of two regions. The first is called normal
3196 * region and the second is called PWM region. In the normal region
3197 * each ICID has its own set of addresses so that writing to that
3198 * specific address identifies the ICID. In the Process Window Mode
3199 * region the ICID is given in the data written to the doorbell. The
3200 * above per PF register denotes the offset in the doorbell BAR in which
3201 * the PWM region begins.
3202 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
3203 * non-PWM connection. The calculation below computes the total non-PWM
3204 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
3205 * in units of 4,096 bytes.
3207 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
3208 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
3210 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
3211 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
3213 min_addr_reg1 = norm_regsize / 4096;
3214 pwm_regsize = db_bar_size - norm_regsize;
3216 /* Check that the normal and PWM sizes are valid */
3217 if (db_bar_size < norm_regsize) {
3218 DP_ERR(p_hwfn->p_dev,
3219 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
3220 db_bar_size, norm_regsize);
3221 return ECORE_NORESOURCES;
3223 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
3224 DP_ERR(p_hwfn->p_dev,
3225 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
3226 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
3228 return ECORE_NORESOURCES;
3231 /* Calculate number of DPIs */
3232 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
3233 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
3234 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
3235 /* Either EDPM is mandatory, or we are attempting to allocate a
3238 n_cpus = OSAL_NUM_CPUS();
3239 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3242 cond = ((rc != ECORE_SUCCESS) &&
3243 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
3244 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
3245 if (cond || p_hwfn->dcbx_no_edpm) {
3246 /* Either EDPM is disabled from user configuration, or it is
3247 * disabled via DCBx, or it is not mandatory and we failed to
3248 * allocated a WID per CPU.
3251 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3253 /* If we entered this flow due to DCBX then the DPM register is
3254 * already configured.
3259 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
3260 norm_regsize, pwm_regsize);
3262 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
3263 p_hwfn->dpi_size, p_hwfn->dpi_count,
3264 (!ecore_edpm_enabled(p_hwfn)) ?
3265 "disabled" : "enabled");
3267 /* Check return codes from above calls */
3268 if (rc != ECORE_SUCCESS) {
3270 "Failed to allocate enough DPIs\n");
3271 return ECORE_NORESOURCES;
3275 p_hwfn->dpi_start_offset = norm_regsize;
3277 /* Update registers */
3278 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
3279 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
3280 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
3281 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
3283 return ECORE_SUCCESS;
3286 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
3287 struct ecore_ptt *p_ptt,
3290 enum _ecore_status_t rc = ECORE_SUCCESS;
3292 /* In CMT the gate should be cleared by the 2nd hwfn */
3293 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
3294 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
3296 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
3298 if (rc != ECORE_SUCCESS)
3301 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
3304 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
3305 return ECORE_SUCCESS;
3307 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
3308 if (ECORE_IS_AH(p_hwfn->p_dev))
3309 return ECORE_SUCCESS;
3310 else if (ECORE_IS_BB(p_hwfn->p_dev))
3311 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
3312 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3313 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
3314 /* Activate OPTE in CMT */
3317 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
3319 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
3320 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
3321 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
3322 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
3323 ecore_wr(p_hwfn, p_ptt,
3324 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
3325 ecore_wr(p_hwfn, p_ptt,
3326 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
3327 ecore_wr(p_hwfn, p_ptt,
3328 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
3332 ecore_emul_link_init(p_hwfn, p_ptt);
3334 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
3341 static enum _ecore_status_t
3342 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3343 int hw_mode, struct ecore_hw_init_params *p_params)
3345 u8 rel_pf_id = p_hwfn->rel_pf_id;
3347 enum _ecore_status_t rc = ECORE_SUCCESS;
3351 if (p_hwfn->mcp_info) {
3352 struct ecore_mcp_function_info *p_info;
3354 p_info = &p_hwfn->mcp_info->func_info;
3355 if (p_info->bandwidth_min)
3356 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
3358 /* Update rate limit once we'll actually have a link */
3359 p_hwfn->qm_info.pf_rl = 100000;
3361 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
3363 ecore_int_igu_init_rt(p_hwfn);
3365 /* Set VLAN in NIG if needed */
3366 if (hw_mode & (1 << MODE_MF_SD)) {
3367 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
3368 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
3369 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
3370 p_hwfn->hw_info.ovlan);
3372 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3373 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
3374 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
3378 /* Enable classification by MAC if needed */
3379 if (hw_mode & (1 << MODE_MF_SI)) {
3380 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3381 "Configuring TAGMAC_CLS_TYPE\n");
3382 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
3386 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
3387 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
3388 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
3389 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
3390 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
3391 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
3393 /* perform debug configuration when chip is out of reset */
3394 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
3396 /* Sanity check before the PF init sequence that uses DMAE */
3397 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
3401 /* PF Init sequence */
3402 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
3406 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
3407 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
3411 /* Pure runtime initializations - directly to the HW */
3412 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
3414 /* PCI relaxed ordering causes a decrease in the performance on some
3415 * systems. Till a root cause is found, disable this attribute in the
3419 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
3421 * DP_NOTICE(p_hwfn, true,
3422 * "Failed to find the PCIe Cap\n");
3425 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
3426 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
3427 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
3430 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
3431 if (rc != ECORE_SUCCESS)
3434 /* Use the leading hwfn since in CMT only NIG #0 is operational */
3435 if (IS_LEAD_HWFN(p_hwfn)) {
3436 rc = ecore_llh_hw_init_pf(p_hwfn, p_ptt,
3437 p_params->avoid_eng_affin);
3442 if (p_params->b_hw_start) {
3443 /* enable interrupts */
3444 rc = ecore_int_igu_enable(p_hwfn, p_ptt, p_params->int_mode);
3445 if (rc != ECORE_SUCCESS)
3448 /* send function start command */
3449 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_params->p_tunn,
3450 p_params->allow_npar_tx_switch);
3452 DP_NOTICE(p_hwfn, true,
3453 "Function start ramrod failed\n");
3457 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3458 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3459 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3461 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
3462 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
3464 ecore_wr(p_hwfn, p_ptt,
3465 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
3468 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3469 "PRS_REG_SEARCH registers after start PFn\n");
3470 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
3471 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3472 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
3473 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
3474 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3475 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
3476 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
3477 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3478 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
3479 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
3480 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3481 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
3482 prs_reg = ecore_rd(p_hwfn, p_ptt,
3483 PRS_REG_SEARCH_TCP_FIRST_FRAG);
3484 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3485 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
3487 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3488 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3489 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3491 return ECORE_SUCCESS;
3494 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
3495 struct ecore_ptt *p_ptt,
3498 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
3500 /* Configure the PF's internal FID_enable for master transactions */
3501 ecore_wr(p_hwfn, p_ptt,
3502 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
3504 /* Wait until value is set - try for 1 second every 50us */
3505 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
3506 val = ecore_rd(p_hwfn, p_ptt,
3507 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
3514 if (val != set_val) {
3515 DP_NOTICE(p_hwfn, true,
3516 "PFID_ENABLE_MASTER wasn't changed after a second\n");
3517 return ECORE_UNKNOWN_ERROR;
3520 return ECORE_SUCCESS;
3523 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
3524 struct ecore_ptt *p_main_ptt)
3526 /* Read shadow of current MFW mailbox */
3527 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
3528 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
3529 p_hwfn->mcp_info->mfw_mb_cur,
3530 p_hwfn->mcp_info->mfw_mb_length);
3533 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
3534 struct ecore_ptt *p_ptt)
3536 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3537 1 << p_hwfn->abs_pf_id);
3540 static enum _ecore_status_t
3541 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
3542 struct ecore_load_req_params *p_load_req,
3543 struct ecore_drv_load_params *p_drv_load)
3545 /* Make sure that if ecore-client didn't provide inputs, all the
3546 * expected defaults are indeed zero.
3548 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
3549 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
3550 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
3552 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
3554 if (p_drv_load == OSAL_NULL)
3557 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
3558 ECORE_DRV_ROLE_KDUMP :
3560 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
3561 p_load_req->override_force_load = p_drv_load->override_force_load;
3563 /* Old MFW versions don't support timeout values other than default and
3564 * none, so these values are replaced according to the fall-back action.
3567 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
3568 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
3569 (p_hwfn->mcp_info->capabilities &
3570 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
3571 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
3575 switch (p_drv_load->mfw_timeout_fallback) {
3576 case ECORE_TO_FALLBACK_TO_NONE:
3577 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
3579 case ECORE_TO_FALLBACK_TO_DEFAULT:
3580 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
3582 case ECORE_TO_FALLBACK_FAIL_LOAD:
3583 DP_NOTICE(p_hwfn, false,
3584 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
3585 p_drv_load->mfw_timeout_val,
3586 ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
3587 ECORE_LOAD_REQ_LOCK_TO_NONE);
3588 return ECORE_ABORTED;
3592 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
3593 p_drv_load->mfw_timeout_val,
3594 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
3596 p_load_req->timeout_val);
3598 return ECORE_SUCCESS;
3601 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
3602 struct ecore_hw_init_params *p_params)
3604 if (p_params->p_tunn) {
3605 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
3606 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
3609 p_hwfn->b_int_enabled = 1;
3611 return ECORE_SUCCESS;
3614 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
3615 struct ecore_hw_init_params *p_params)
3617 struct ecore_load_req_params load_req_params;
3618 u32 load_code, resp, param, drv_mb_param;
3619 bool b_default_mtu = true;
3620 struct ecore_hwfn *p_hwfn;
3621 enum _ecore_status_t rc = ECORE_SUCCESS;
3625 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
3626 DP_NOTICE(p_dev, false,
3627 "MSI mode is not supported for CMT devices\n");
3632 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
3633 if (rc != ECORE_SUCCESS)
3637 for_each_hwfn(p_dev, i) {
3638 p_hwfn = &p_dev->hwfns[i];
3640 /* If management didn't provide a default, set one of our own */
3641 if (!p_hwfn->hw_info.mtu) {
3642 p_hwfn->hw_info.mtu = 1500;
3643 b_default_mtu = false;
3647 ecore_vf_start(p_hwfn, p_params);
3651 rc = ecore_calc_hw_mode(p_hwfn);
3652 if (rc != ECORE_SUCCESS)
3655 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3657 OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
3658 &p_dev->mf_bits))) {
3659 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3661 ether_type = ETHER_TYPE_VLAN;
3663 ether_type = ETHER_TYPE_QINQ;
3664 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3666 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3668 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3670 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3674 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
3676 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
3677 p_params->p_drv_load_params);
3678 if (rc != ECORE_SUCCESS)
3681 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3683 if (rc != ECORE_SUCCESS) {
3684 DP_NOTICE(p_hwfn, false,
3685 "Failed sending a LOAD_REQ command\n");
3689 load_code = load_req_params.load_code;
3690 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3691 "Load request was sent. Load code: 0x%x\n",
3694 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3697 * When coming back from hiberbate state, the registers from
3698 * which shadow is read initially are not initialized. It turns
3699 * out that these registers get initialized during the call to
3700 * ecore_mcp_load_req request. So we need to reread them here
3701 * to get the proper shadow register value.
3702 * Note: This is a workaround for the missing MFW
3703 * initialization. It may be removed once the implementation
3706 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3708 /* Only relevant for recovery:
3709 * Clear the indication after the LOAD_REQ command is responded
3712 p_dev->recov_in_prog = false;
3714 p_hwfn->first_on_engine = (load_code ==
3715 FW_MSG_CODE_DRV_LOAD_ENGINE);
3717 if (!qm_lock_ref_cnt) {
3718 #ifdef CONFIG_ECORE_LOCK_ALLOC
3719 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
3721 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
3725 OSAL_SPIN_LOCK_INIT(&qm_lock);
3729 /* Clean up chip from previous driver if such remains exist.
3730 * This is not needed when the PF is the first one on the
3731 * engine, since afterwards we are going to init the FW.
3733 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3734 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3735 p_hwfn->rel_pf_id, false);
3736 if (rc != ECORE_SUCCESS) {
3737 ecore_hw_err_notify(p_hwfn,
3738 ECORE_HW_ERR_RAMROD_FAIL);
3743 /* Log and clear previous pglue_b errors if such exist */
3744 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
3746 /* Enable the PF's internal FID_enable in the PXP */
3747 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3749 if (rc != ECORE_SUCCESS)
3752 /* Clear the pglue_b was_error indication.
3753 * In E4 it must be done after the BME and the internal
3754 * FID_enable for the PF are set, since VDMs may cause the
3755 * indication to be set again.
3757 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3759 switch (load_code) {
3760 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3761 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3762 p_hwfn->hw_info.hw_mode);
3763 if (rc != ECORE_SUCCESS)
3766 case FW_MSG_CODE_DRV_LOAD_PORT:
3767 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3768 p_hwfn->hw_info.hw_mode);
3769 if (rc != ECORE_SUCCESS)
3772 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3773 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3774 p_hwfn->hw_info.hw_mode,
3778 DP_NOTICE(p_hwfn, false,
3779 "Unexpected load code [0x%08x]", load_code);
3784 if (rc != ECORE_SUCCESS) {
3785 DP_NOTICE(p_hwfn, false,
3786 "init phase failed for loadcode 0x%x (rc %d)\n",
3791 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3792 if (rc != ECORE_SUCCESS) {
3793 DP_NOTICE(p_hwfn, false,
3794 "Sending load done failed, rc = %d\n", rc);
3795 if (rc == ECORE_NOMEM) {
3796 DP_NOTICE(p_hwfn, false,
3797 "Sending load done was failed due to memory allocation failure\n");
3803 /* send DCBX attention request command */
3804 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
3805 "sending phony dcbx set command to trigger DCBx attention handling\n");
3806 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3807 DRV_MSG_CODE_SET_DCBX,
3808 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
3810 if (rc != ECORE_SUCCESS) {
3811 DP_NOTICE(p_hwfn, false,
3812 "Failed to send DCBX attention request\n");
3816 p_hwfn->hw_init_done = true;
3820 /* Get pre-negotiated values for stag, bandwidth etc. */
3821 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3822 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3823 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3824 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3825 DRV_MSG_CODE_GET_OEM_UPDATES,
3826 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3828 if (rc != ECORE_SUCCESS)
3829 DP_NOTICE(p_hwfn, false,
3830 "Failed to send GET_OEM_UPDATES attention request\n");
3834 /* Get pre-negotiated values for stag, bandwidth etc. */
3835 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3836 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3837 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3838 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3839 DRV_MSG_CODE_GET_OEM_UPDATES,
3840 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3842 if (rc != ECORE_SUCCESS)
3843 DP_NOTICE(p_hwfn, false,
3844 "Failed to send GET_OEM_UPDATES attention request\n");
3848 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3849 drv_mb_param = STORM_FW_VERSION;
3850 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3851 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3852 drv_mb_param, &resp, ¶m);
3853 if (rc != ECORE_SUCCESS)
3854 DP_INFO(p_hwfn, "Failed to update firmware version\n");
3856 if (!b_default_mtu) {
3857 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3858 p_hwfn->hw_info.mtu);
3859 if (rc != ECORE_SUCCESS)
3860 DP_INFO(p_hwfn, "Failed to update default mtu\n");
3863 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
3865 ECORE_OV_DRIVER_STATE_DISABLED);
3866 if (rc != ECORE_SUCCESS)
3867 DP_INFO(p_hwfn, "Failed to update driver state\n");
3869 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3870 ECORE_OV_ESWITCH_NONE);
3871 if (rc != ECORE_SUCCESS)
3872 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3879 #ifdef CONFIG_ECORE_LOCK_ALLOC
3880 if (!qm_lock_ref_cnt)
3881 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
3884 /* The MFW load lock should be released regardless of success or failure
3885 * of initialization.
3886 * TODO: replace this with an attempt to send cancel_load.
3888 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3892 #define ECORE_HW_STOP_RETRY_LIMIT (10)
3893 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
3894 struct ecore_hwfn *p_hwfn,
3895 struct ecore_ptt *p_ptt)
3900 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3901 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3902 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
3904 if ((!ecore_rd(p_hwfn, p_ptt,
3905 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3906 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3909 /* Dependent on number of connection/tasks, possibly
3910 * 1ms sleep is required between polls
3915 if (i < ECORE_HW_STOP_RETRY_LIMIT)
3918 DP_NOTICE(p_hwfn, false,
3919 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3920 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3921 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3924 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
3928 for_each_hwfn(p_dev, j) {
3929 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3930 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3932 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
3936 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
3937 struct ecore_ptt *p_ptt,
3938 u32 addr, u32 expected_val)
3940 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
3942 if (val != expected_val) {
3943 DP_NOTICE(p_hwfn, true,
3944 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
3945 addr, val, expected_val);
3946 return ECORE_UNKNOWN_ERROR;
3949 return ECORE_SUCCESS;
3952 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
3954 struct ecore_hwfn *p_hwfn;
3955 struct ecore_ptt *p_ptt;
3956 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
3959 for_each_hwfn(p_dev, j) {
3960 p_hwfn = &p_dev->hwfns[j];
3961 p_ptt = p_hwfn->p_main_ptt;
3963 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
3966 ecore_vf_pf_int_cleanup(p_hwfn);
3967 rc = ecore_vf_pf_reset(p_hwfn);
3968 if (rc != ECORE_SUCCESS) {
3969 DP_NOTICE(p_hwfn, true,
3970 "ecore_vf_pf_reset failed. rc = %d.\n",
3972 rc2 = ECORE_UNKNOWN_ERROR;
3977 /* mark the hw as uninitialized... */
3978 p_hwfn->hw_init_done = false;
3980 /* Send unload command to MCP */
3981 if (!p_dev->recov_in_prog) {
3982 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
3983 if (rc != ECORE_SUCCESS) {
3984 DP_NOTICE(p_hwfn, false,
3985 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
3987 rc2 = ECORE_UNKNOWN_ERROR;
3991 OSAL_DPC_SYNC(p_hwfn);
3993 /* After this point no MFW attentions are expected, e.g. prevent
3994 * race between pf stop and dcbx pf update.
3997 rc = ecore_sp_pf_stop(p_hwfn);
3998 if (rc != ECORE_SUCCESS) {
3999 DP_NOTICE(p_hwfn, false,
4000 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
4002 rc2 = ECORE_UNKNOWN_ERROR;
4005 OSAL_DPC_SYNC(p_hwfn);
4007 /* After this point we don't expect the FW to send us async
4011 /* perform debug action after PF stop was sent */
4012 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
4014 /* close NIG to BRB gate */
4015 ecore_wr(p_hwfn, p_ptt,
4016 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4019 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4020 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4021 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4022 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4023 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4025 /* @@@TBD - clean transmission queues (5.b) */
4026 /* @@@TBD - clean BTB (5.c) */
4028 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
4030 /* @@@TBD - verify DMAE requests are done (8) */
4032 /* Disable Attention Generation */
4033 ecore_int_igu_disable_int(p_hwfn, p_ptt);
4034 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
4035 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
4036 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
4037 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
4038 if (rc != ECORE_SUCCESS) {
4039 DP_NOTICE(p_hwfn, true,
4040 "Failed to return IGU CAM to default\n");
4041 rc2 = ECORE_UNKNOWN_ERROR;
4044 /* Need to wait 1ms to guarantee SBs are cleared */
4047 if (IS_LEAD_HWFN(p_hwfn) &&
4048 OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
4049 !ECORE_IS_FCOE_PERSONALITY(p_hwfn))
4050 ecore_llh_remove_mac_filter(p_dev, 0,
4051 p_hwfn->hw_info.hw_mac_addr);
4053 if (!p_dev->recov_in_prog) {
4054 ecore_verify_reg_val(p_hwfn, p_ptt,
4055 QM_REG_USG_CNT_PF_TX, 0);
4056 ecore_verify_reg_val(p_hwfn, p_ptt,
4057 QM_REG_USG_CNT_PF_OTHER, 0);
4058 /* @@@TBD - assert on incorrect xCFC values (10.b) */
4061 /* Disable PF in HW blocks */
4062 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
4063 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
4066 #ifdef CONFIG_ECORE_LOCK_ALLOC
4067 if (!qm_lock_ref_cnt)
4068 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
4071 if (!p_dev->recov_in_prog) {
4072 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4073 if (rc == ECORE_NOMEM) {
4074 DP_NOTICE(p_hwfn, false,
4075 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
4076 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4078 if (rc != ECORE_SUCCESS) {
4079 DP_NOTICE(p_hwfn, false,
4080 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
4082 rc2 = ECORE_UNKNOWN_ERROR;
4087 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
4088 p_hwfn = ECORE_LEADING_HWFN(p_dev);
4089 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
4091 /* Clear the PF's internal FID_enable in the PXP.
4092 * In CMT this should only be done for first hw-function, and
4093 * only after all transactions have stopped for all active
4096 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
4098 if (rc != ECORE_SUCCESS) {
4099 DP_NOTICE(p_hwfn, true,
4100 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
4102 rc2 = ECORE_UNKNOWN_ERROR;
4109 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
4113 for_each_hwfn(p_dev, j) {
4114 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4115 struct ecore_ptt *p_ptt;
4118 ecore_vf_pf_int_cleanup(p_hwfn);
4121 p_ptt = ecore_ptt_acquire(p_hwfn);
4125 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4126 "Shutting down the fastpath\n");
4128 ecore_wr(p_hwfn, p_ptt,
4129 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4131 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4132 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4133 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4134 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4135 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4137 /* @@@TBD - clean transmission queues (5.b) */
4138 /* @@@TBD - clean BTB (5.c) */
4140 /* @@@TBD - verify DMAE requests are done (8) */
4142 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
4143 /* Need to wait 1ms to guarantee SBs are cleared */
4145 ecore_ptt_release(p_hwfn, p_ptt);
4148 return ECORE_SUCCESS;
4151 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
4153 struct ecore_ptt *p_ptt;
4155 if (IS_VF(p_hwfn->p_dev))
4156 return ECORE_SUCCESS;
4158 p_ptt = ecore_ptt_acquire(p_hwfn);
4162 /* If roce info is allocated it means roce is initialized and should
4163 * be enabled in searcher.
4165 if (p_hwfn->p_rdma_info) {
4166 if (p_hwfn->b_rdma_enabled_in_prs)
4167 ecore_wr(p_hwfn, p_ptt,
4168 p_hwfn->rdma_prs_search_reg, 0x1);
4169 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
4172 /* Re-open incoming traffic */
4173 ecore_wr(p_hwfn, p_ptt,
4174 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
4175 ecore_ptt_release(p_hwfn, p_ptt);
4177 return ECORE_SUCCESS;
4180 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
4181 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
4183 ecore_ptt_pool_free(p_hwfn);
4184 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
4187 /* Setup bar access */
4188 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
4190 /* clear indirect access */
4191 if (ECORE_IS_AH(p_hwfn->p_dev)) {
4192 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4193 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
4194 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4195 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
4196 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4197 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
4198 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4199 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
4201 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4202 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
4203 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4204 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
4205 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4206 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
4207 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4208 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
4211 /* Clean previous pglue_b errors if such exist */
4212 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
4214 /* enable internal target-read */
4215 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4216 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
4219 static void get_function_id(struct ecore_hwfn *p_hwfn)
4222 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
4223 PXP_PF_ME_OPAQUE_ADDR);
4225 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
4227 /* Bits 16-19 from the ME registers are the pf_num */
4228 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
4229 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4230 PXP_CONCRETE_FID_PFID);
4231 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4232 PXP_CONCRETE_FID_PORT);
4234 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4235 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
4236 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
4239 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
4241 u32 *feat_num = p_hwfn->hw_info.feat_num;
4242 struct ecore_sb_cnt_info sb_cnt;
4245 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
4246 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
4248 /* L2 Queues require each: 1 status block. 1 L2 queue */
4249 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
4250 /* Start by allocating VF queues, then PF's */
4251 feat_num[ECORE_VF_L2_QUE] =
4253 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
4255 feat_num[ECORE_PF_L2_QUE] =
4257 sb_cnt.cnt - non_l2_sbs,
4258 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
4259 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
4262 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
4263 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) {
4264 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ?
4265 &feat_num[ECORE_FCOE_CQ] :
4266 &feat_num[ECORE_ISCSI_CQ];
4267 u32 limit = sb_cnt.cnt;
4269 /* The number of queues should not exceed the number of FP SBs.
4270 * In storage target, the queues are divided into pairs of a CQ
4271 * and a CmdQ, and each pair uses a single SB. The limit in
4272 * this case should allow a max ratio of 2:1 instead of 1:1.
4274 if (p_hwfn->p_dev->b_is_target)
4276 *p_storage_feat = OSAL_MIN_T(u32, limit,
4277 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
4280 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init
4281 * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2".
4283 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat,
4284 (NUM_OF_GLOBAL_QUEUES / 2));
4287 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4288 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
4289 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
4290 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
4291 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
4292 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
4293 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
4297 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
4300 case ECORE_L2_QUEUE:
4314 case ECORE_RDMA_CNQ_RAM:
4315 return "RDMA_CNQ_RAM";
4318 case ECORE_LL2_QUEUE:
4320 case ECORE_CMDQS_CQS:
4322 case ECORE_RDMA_STATS_QUEUE:
4323 return "RDMA_STATS_QUEUE";
4329 return "UNKNOWN_RESOURCE";
4333 static enum _ecore_status_t
4334 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4335 struct ecore_ptt *p_ptt,
4336 enum ecore_resources res_id,
4340 enum _ecore_status_t rc;
4342 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
4343 resc_max_val, p_mcp_resp);
4344 if (rc != ECORE_SUCCESS) {
4345 DP_NOTICE(p_hwfn, false,
4346 "MFW response failure for a max value setting of resource %d [%s]\n",
4347 res_id, ecore_hw_get_resc_name(res_id));
4351 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
4353 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
4354 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
4356 return ECORE_SUCCESS;
4359 static enum _ecore_status_t
4360 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4361 struct ecore_ptt *p_ptt)
4363 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
4364 u32 resc_max_val, mcp_resp;
4366 enum _ecore_status_t rc;
4368 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4371 case ECORE_LL2_QUEUE:
4372 case ECORE_RDMA_CNQ_RAM:
4373 case ECORE_RDMA_STATS_QUEUE:
4381 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
4382 resc_max_val, &mcp_resp);
4383 if (rc != ECORE_SUCCESS)
4386 /* There's no point to continue to the next resource if the
4387 * command is not supported by the MFW.
4388 * We do continue if the command is supported but the resource
4389 * is unknown to the MFW. Such a resource will be later
4390 * configured with the default allocation values.
4392 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
4393 return ECORE_NOTIMPL;
4396 return ECORE_SUCCESS;
4400 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
4401 enum ecore_resources res_id,
4402 u32 *p_resc_num, u32 *p_resc_start)
4404 u8 num_funcs = p_hwfn->num_funcs_on_engine;
4405 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
4408 case ECORE_L2_QUEUE:
4409 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
4410 MAX_NUM_L2_QUEUES_BB) / num_funcs;
4413 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
4414 MAX_NUM_VPORTS_BB) / num_funcs;
4417 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
4418 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
4421 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
4422 MAX_QM_TX_QUEUES_BB) / num_funcs;
4425 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
4429 /* Each VFC resource can accommodate both a MAC and a VLAN */
4430 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
4433 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
4434 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
4436 case ECORE_LL2_QUEUE:
4437 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
4439 case ECORE_RDMA_CNQ_RAM:
4440 case ECORE_CMDQS_CQS:
4441 /* CNQ/CMDQS are the same resource */
4443 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
4445 case ECORE_RDMA_STATS_QUEUE:
4447 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
4448 MAX_NUM_VPORTS_BB) / num_funcs;
4465 /* Since we want its value to reflect whether MFW supports
4466 * the new scheme, have a default of 0.
4471 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
4475 return ECORE_SUCCESS;
4478 static enum _ecore_status_t
4479 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
4480 bool drv_resc_alloc)
4482 u32 dflt_resc_num = 0, dflt_resc_start = 0;
4483 u32 mcp_resp, *p_resc_num, *p_resc_start;
4484 enum _ecore_status_t rc;
4486 p_resc_num = &RESC_NUM(p_hwfn, res_id);
4487 p_resc_start = &RESC_START(p_hwfn, res_id);
4489 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
4491 if (rc != ECORE_SUCCESS) {
4493 "Failed to get default amount for resource %d [%s]\n",
4494 res_id, ecore_hw_get_resc_name(res_id));
4499 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
4500 *p_resc_num = dflt_resc_num;
4501 *p_resc_start = dflt_resc_start;
4506 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
4507 &mcp_resp, p_resc_num, p_resc_start);
4508 if (rc != ECORE_SUCCESS) {
4509 DP_NOTICE(p_hwfn, true,
4510 "MFW response failure for an allocation request for"
4511 " resource %d [%s]\n",
4512 res_id, ecore_hw_get_resc_name(res_id));
4516 /* Default driver values are applied in the following cases:
4517 * - The resource allocation MB command is not supported by the MFW
4518 * - There is an internal error in the MFW while processing the request
4519 * - The resource ID is unknown to the MFW
4521 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
4523 "Failed to receive allocation info for resource %d [%s]."
4524 " mcp_resp = 0x%x. Applying default values"
4526 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
4527 dflt_resc_num, dflt_resc_start);
4529 *p_resc_num = dflt_resc_num;
4530 *p_resc_start = dflt_resc_start;
4534 if ((*p_resc_num != dflt_resc_num ||
4535 *p_resc_start != dflt_resc_start) &&
4536 res_id != ECORE_SB) {
4538 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
4539 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
4540 *p_resc_start, dflt_resc_num, dflt_resc_start,
4541 drv_resc_alloc ? " - Applying default values" : "");
4542 if (drv_resc_alloc) {
4543 *p_resc_num = dflt_resc_num;
4544 *p_resc_start = dflt_resc_start;
4548 return ECORE_SUCCESS;
4551 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
4552 bool drv_resc_alloc)
4554 enum _ecore_status_t rc;
4557 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4558 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
4559 if (rc != ECORE_SUCCESS)
4563 return ECORE_SUCCESS;
4566 #define ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS 0xaa
4567 #define ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS 0x55
4568 #define ECORE_NONUSED_PPFID_MASK_AH_4P 0xf0
4570 static enum _ecore_status_t ecore_hw_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,
4571 struct ecore_ptt *p_ptt)
4573 u8 native_ppfid_idx = ECORE_PPFID_BY_PFID(p_hwfn), new_bitmap;
4574 struct ecore_dev *p_dev = p_hwfn->p_dev;
4575 enum _ecore_status_t rc;
4577 rc = ecore_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
4578 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL)
4580 else if (rc == ECORE_NOTIMPL)
4581 p_dev->ppfid_bitmap = 0x1 << native_ppfid_idx;
4583 /* 4-ports mode has limitations that should be enforced:
4584 * - BB: the MFW can access only PPFIDs which their corresponding PFIDs
4585 * belong to this certain port.
4586 * - AH/E5: only 4 PPFIDs per port are available.
4588 if (ecore_device_num_ports(p_dev) == 4) {
4591 if (ECORE_IS_BB(p_dev))
4592 mask = MFW_PORT(p_hwfn) > 1 ?
4593 ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS :
4594 ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS;
4596 mask = ECORE_NONUSED_PPFID_MASK_AH_4P;
4598 if (p_dev->ppfid_bitmap & mask) {
4599 new_bitmap = p_dev->ppfid_bitmap & ~mask;
4601 "Fix the PPFID bitmap for 4-ports mode: 0x%hhx -> 0x%hhx\n",
4602 p_dev->ppfid_bitmap, new_bitmap);
4603 p_dev->ppfid_bitmap = new_bitmap;
4607 /* The native PPFID is expected to be part of the allocated bitmap */
4608 if (!(p_dev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
4609 new_bitmap = 0x1 << native_ppfid_idx;
4611 "Fix the PPFID bitmap to inculde the native PPFID: %hhd -> 0x%hhx\n",
4612 p_dev->ppfid_bitmap, new_bitmap);
4613 p_dev->ppfid_bitmap = new_bitmap;
4616 return ECORE_SUCCESS;
4619 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
4620 struct ecore_ptt *p_ptt,
4621 bool drv_resc_alloc)
4623 struct ecore_resc_unlock_params resc_unlock_params;
4624 struct ecore_resc_lock_params resc_lock_params;
4625 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
4627 enum _ecore_status_t rc;
4629 u32 *resc_start = p_hwfn->hw_info.resc_start;
4630 u32 *resc_num = p_hwfn->hw_info.resc_num;
4631 /* For AH, an equal share of the ILT lines between the maximal number of
4632 * PFs is not enough for RoCE. This would be solved by the future
4633 * resource allocation scheme, but isn't currently present for
4634 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
4635 * to work - the BB number of ILT lines divided by its max PFs number.
4637 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
4640 /* Setting the max values of the soft resources and the following
4641 * resources allocation queries should be atomic. Since several PFs can
4642 * run in parallel - a resource lock is needed.
4643 * If either the resource lock or resource set value commands are not
4644 * supported - skip the max values setting, release the lock if
4645 * needed, and proceed to the queries. Other failures, including a
4646 * failure to acquire the lock, will cause this function to fail.
4647 * Old drivers that don't acquire the lock can run in parallel, and
4648 * their allocation values won't be affected by the updated max values.
4650 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
4651 ECORE_RESC_LOCK_RESC_ALLOC, false);
4653 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
4654 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4656 } else if (rc == ECORE_NOTIMPL) {
4658 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
4659 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
4660 DP_NOTICE(p_hwfn, false,
4661 "Failed to acquire the resource lock for the resource allocation commands\n");
4663 goto unlock_and_exit;
4665 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
4666 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4667 DP_NOTICE(p_hwfn, false,
4668 "Failed to set the max values of the soft resources\n");
4669 goto unlock_and_exit;
4670 } else if (rc == ECORE_NOTIMPL) {
4672 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
4673 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4674 &resc_unlock_params);
4675 if (rc != ECORE_SUCCESS)
4677 "Failed to release the resource lock for the resource allocation commands\n");
4681 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
4682 if (rc != ECORE_SUCCESS)
4683 goto unlock_and_exit;
4685 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
4686 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4687 &resc_unlock_params);
4688 if (rc != ECORE_SUCCESS)
4690 "Failed to release the resource lock for the resource allocation commands\n");
4694 if (IS_LEAD_HWFN(p_hwfn)) {
4695 rc = ecore_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
4696 if (rc != ECORE_SUCCESS)
4701 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
4702 /* Reduced build contains less PQs */
4703 if (!(p_hwfn->p_dev->b_is_emul_full)) {
4704 resc_num[ECORE_PQ] = 32;
4705 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
4706 p_hwfn->enabled_func_idx;
4709 /* For AH emulation, since we have a possible maximal number of
4710 * 16 enabled PFs, in case there are not enough ILT lines -
4711 * allocate only first PF as RoCE and have all the other ETH
4712 * only with less ILT lines.
4714 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
4715 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
4716 resc_num[ECORE_ILT],
4717 roce_min_ilt_lines);
4720 /* Correct the common ILT calculation if PF0 has more */
4721 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
4722 p_hwfn->p_dev->b_is_emul_full &&
4723 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
4724 resc_start[ECORE_ILT] += roce_min_ilt_lines -
4725 resc_num[ECORE_ILT];
4728 /* Sanity for ILT */
4729 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
4730 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
4731 DP_NOTICE(p_hwfn, true,
4732 "Can't assign ILT pages [%08x,...,%08x]\n",
4733 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
4739 /* This will also learn the number of SBs from MFW */
4740 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
4743 ecore_hw_set_feat(p_hwfn);
4745 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4746 "The numbers for each resource are:\n");
4747 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
4748 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
4749 ecore_hw_get_resc_name(res_id),
4750 RESC_NUM(p_hwfn, res_id),
4751 RESC_START(p_hwfn, res_id));
4753 return ECORE_SUCCESS;
4756 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
4757 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4758 &resc_unlock_params);
4762 static enum _ecore_status_t
4763 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
4764 struct ecore_ptt *p_ptt,
4765 struct ecore_hw_prepare_params *p_params)
4767 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
4768 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
4769 struct ecore_mcp_link_capabilities *p_caps;
4770 struct ecore_mcp_link_params *link;
4771 enum _ecore_status_t rc;
4773 /* Read global nvm_cfg address */
4774 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
4776 /* Verify MCP has initialized it */
4777 if (!nvm_cfg_addr) {
4778 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
4779 if (p_params->b_relaxed_probe)
4780 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
4784 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
4786 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4788 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4789 OFFSETOF(struct nvm_cfg1, glob) +
4790 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
4792 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
4794 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4795 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4796 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4797 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
4799 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4800 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
4802 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4803 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
4805 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4806 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
4808 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4809 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
4811 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4812 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
4814 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4815 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
4817 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4818 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
4820 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4821 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
4823 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4824 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
4826 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4827 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
4830 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
4835 /* Read DCBX configuration */
4836 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4837 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4838 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
4840 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
4841 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
4842 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
4843 switch (dcbx_mode) {
4844 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
4845 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
4847 case NVM_CFG1_PORT_DCBX_MODE_CEE:
4848 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
4850 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
4851 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
4854 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
4857 /* Read default link configuration */
4858 link = &p_hwfn->mcp_info->link_input;
4859 p_caps = &p_hwfn->mcp_info->link_capabilities;
4860 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4861 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4862 link_temp = ecore_rd(p_hwfn, p_ptt,
4864 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
4865 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4866 link->speed.advertised_speeds = link_temp;
4867 p_caps->speed_capabilities = link->speed.advertised_speeds;
4869 link_temp = ecore_rd(p_hwfn, p_ptt,
4871 OFFSETOF(struct nvm_cfg1_port, link_settings));
4872 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4873 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4874 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4875 link->speed.autoneg = true;
4877 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4878 link->speed.forced_speed = 1000;
4880 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4881 link->speed.forced_speed = 10000;
4883 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4884 link->speed.forced_speed = 25000;
4886 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4887 link->speed.forced_speed = 40000;
4889 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
4890 link->speed.forced_speed = 50000;
4892 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
4893 link->speed.forced_speed = 100000;
4896 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
4899 p_caps->default_speed = link->speed.forced_speed;
4900 p_caps->default_speed_autoneg = link->speed.autoneg;
4902 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
4903 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
4904 link->pause.autoneg = !!(link_temp &
4905 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
4906 link->pause.forced_rx = !!(link_temp &
4907 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
4908 link->pause.forced_tx = !!(link_temp &
4909 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
4910 link->loopback_mode = 0;
4912 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
4913 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
4914 OFFSETOF(struct nvm_cfg1_port, ext_phy));
4915 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
4916 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
4917 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
4918 link->eee.enable = true;
4919 switch (link_temp) {
4920 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
4921 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
4922 link->eee.enable = false;
4924 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
4925 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
4927 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
4928 p_caps->eee_lpi_timer =
4929 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
4931 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
4932 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
4936 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
4937 link->eee.tx_lpi_enable = link->eee.enable;
4938 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
4940 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
4943 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4944 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
4945 link->speed.forced_speed, link->speed.advertised_speeds,
4946 link->speed.autoneg, link->pause.autoneg,
4947 p_caps->default_eee, p_caps->eee_lpi_timer);
4949 /* Read Multi-function information from shmem */
4950 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4951 OFFSETOF(struct nvm_cfg1, glob) +
4952 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
4954 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
4956 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
4957 NVM_CFG1_GLOB_MF_MODE_OFFSET;
4960 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
4961 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
4963 case NVM_CFG1_GLOB_MF_MODE_UFP:
4964 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
4965 1 << ECORE_MF_UFP_SPECIFIC |
4966 1 << ECORE_MF_8021Q_TAGGING;
4968 case NVM_CFG1_GLOB_MF_MODE_BD:
4969 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
4970 1 << ECORE_MF_LLH_PROTO_CLSS |
4971 1 << ECORE_MF_8021AD_TAGGING |
4972 1 << ECORE_MF_FIP_SPECIAL;
4974 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
4975 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
4976 1 << ECORE_MF_LLH_PROTO_CLSS |
4977 1 << ECORE_MF_LL2_NON_UNICAST |
4978 1 << ECORE_MF_INTER_PF_SWITCH |
4979 1 << ECORE_MF_DISABLE_ARFS;
4981 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
4982 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
4983 1 << ECORE_MF_LLH_PROTO_CLSS |
4984 1 << ECORE_MF_LL2_NON_UNICAST;
4985 if (ECORE_IS_BB(p_hwfn->p_dev))
4986 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
4989 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4990 p_hwfn->p_dev->mf_bits);
4992 if (ECORE_IS_CMT(p_hwfn->p_dev))
4993 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
4995 /* It's funny since we have another switch, but it's easier
4996 * to throw this away in linux this way. Long term, it might be
4997 * better to have have getters for needed ECORE_MF_* fields,
4998 * convert client code and eliminate this.
5001 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5002 case NVM_CFG1_GLOB_MF_MODE_BD:
5003 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
5005 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5006 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
5008 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5009 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
5011 case NVM_CFG1_GLOB_MF_MODE_UFP:
5012 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
5016 /* Read Multi-function information from shmem */
5017 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5018 OFFSETOF(struct nvm_cfg1, glob) +
5019 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
5021 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
5022 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
5023 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
5024 &p_hwfn->hw_info.device_capabilities);
5025 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
5026 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
5027 &p_hwfn->hw_info.device_capabilities);
5028 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
5029 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
5030 &p_hwfn->hw_info.device_capabilities);
5031 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
5032 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
5033 &p_hwfn->hw_info.device_capabilities);
5034 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
5035 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
5036 &p_hwfn->hw_info.device_capabilities);
5038 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
5039 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5041 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5047 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
5048 struct ecore_ptt *p_ptt)
5050 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
5051 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
5052 struct ecore_dev *p_dev = p_hwfn->p_dev;
5054 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
5056 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
5057 * in the other bits are selected.
5058 * Bits 1-15 are for functions 1-15, respectively, and their value is
5059 * '0' only for enabled functions (function 0 always exists and
5061 * In case of CMT in BB, only the "even" functions are enabled, and thus
5062 * the number of functions for both hwfns is learnt from the same bits.
5064 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
5065 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
5066 MISCS_REG_FUNCTION_HIDE_BB_K2);
5068 reg_function_hide = 0;
5071 if (reg_function_hide & 0x1) {
5072 if (ECORE_IS_BB(p_dev)) {
5073 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
5085 /* Get the number of the enabled functions on the engine */
5086 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
5093 /* Get the PF index within the enabled functions */
5094 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
5095 tmp = reg_function_hide & eng_mask & low_pfs_mask;
5103 p_hwfn->num_funcs_on_engine = num_funcs;
5104 p_hwfn->enabled_func_idx = enabled_func_idx;
5107 if (CHIP_REV_IS_FPGA(p_dev)) {
5108 DP_NOTICE(p_hwfn, false,
5109 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
5110 p_hwfn->num_funcs_on_engine = 4;
5114 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
5115 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
5116 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
5117 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
5120 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
5121 struct ecore_ptt *p_ptt)
5123 struct ecore_dev *p_dev = p_hwfn->p_dev;
5127 /* Read the port mode */
5128 if (CHIP_REV_IS_FPGA(p_dev))
5130 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
5131 /* In CMT on emulation, assume 1 port */
5135 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
5137 if (port_mode < 3) {
5138 p_dev->num_ports_in_engine = 1;
5139 } else if (port_mode <= 5) {
5140 p_dev->num_ports_in_engine = 2;
5142 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
5143 p_dev->num_ports_in_engine);
5145 /* Default num_ports_in_engine to something */
5146 p_dev->num_ports_in_engine = 1;
5150 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
5151 struct ecore_ptt *p_ptt)
5153 struct ecore_dev *p_dev = p_hwfn->p_dev;
5157 p_dev->num_ports_in_engine = 0;
5160 if (CHIP_REV_IS_EMUL(p_dev)) {
5161 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5162 switch ((port & 0xf000) >> 12) {
5164 p_dev->num_ports_in_engine = 1;
5167 p_dev->num_ports_in_engine = 2;
5170 p_dev->num_ports_in_engine = 4;
5173 DP_NOTICE(p_hwfn, false,
5174 "Unknown port mode in ECO_RESERVED %08x\n",
5179 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
5180 port = ecore_rd(p_hwfn, p_ptt,
5181 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
5184 p_dev->num_ports_in_engine++;
5187 if (!p_dev->num_ports_in_engine) {
5188 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
5190 /* Default num_ports_in_engine to something */
5191 p_dev->num_ports_in_engine = 1;
5195 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
5196 struct ecore_ptt *p_ptt)
5198 struct ecore_dev *p_dev = p_hwfn->p_dev;
5200 /* Determine the number of ports per engine */
5201 if (ECORE_IS_BB(p_dev))
5202 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
5204 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
5206 /* Get the total number of ports of the device */
5207 if (ECORE_IS_CMT(p_dev)) {
5208 /* In CMT there is always only one port */
5209 p_dev->num_ports = 1;
5211 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
5212 p_dev->num_ports = p_dev->num_ports_in_engine *
5213 ecore_device_num_engines(p_dev);
5216 u32 addr, global_offsize, global_addr;
5218 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
5220 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
5221 global_addr = SECTION_ADDR(global_offsize, 0);
5222 addr = global_addr + OFFSETOF(struct public_global, max_ports);
5223 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
5227 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
5228 struct ecore_ptt *p_ptt)
5230 struct ecore_mcp_link_capabilities *p_caps;
5233 p_caps = &p_hwfn->mcp_info->link_capabilities;
5234 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
5237 p_caps->eee_speed_caps = 0;
5238 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
5239 OFFSETOF(struct public_port, eee_status));
5240 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
5241 EEE_SUPPORTED_SPEED_OFFSET;
5242 if (eee_status & EEE_1G_SUPPORTED)
5243 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
5244 if (eee_status & EEE_10G_ADV)
5245 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
5248 static enum _ecore_status_t
5249 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
5250 enum ecore_pci_personality personality,
5251 struct ecore_hw_prepare_params *p_params)
5253 bool drv_resc_alloc = p_params->drv_resc_alloc;
5254 enum _ecore_status_t rc;
5256 if (IS_ECORE_PACING(p_hwfn)) {
5257 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
5258 "Skipping IOV as packet pacing is requested\n");
5261 /* Since all information is common, only first hwfns should do this */
5262 if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
5263 rc = ecore_iov_hw_info(p_hwfn);
5264 if (rc != ECORE_SUCCESS) {
5265 if (p_params->b_relaxed_probe)
5266 p_params->p_relaxed_res =
5267 ECORE_HW_PREPARE_BAD_IOV;
5273 if (IS_LEAD_HWFN(p_hwfn))
5274 ecore_hw_info_port_num(p_hwfn, p_ptt);
5276 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
5279 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
5281 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
5282 if (rc != ECORE_SUCCESS)
5288 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
5289 if (rc != ECORE_SUCCESS) {
5290 if (p_params->b_relaxed_probe)
5291 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
5297 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
5299 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
5300 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
5303 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
5305 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
5306 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
5310 if (ecore_mcp_is_init(p_hwfn)) {
5311 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
5312 p_hwfn->hw_info.ovlan =
5313 p_hwfn->mcp_info->func_info.ovlan;
5315 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
5317 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
5319 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
5322 if (personality != ECORE_PCI_DEFAULT) {
5323 p_hwfn->hw_info.personality = personality;
5324 } else if (ecore_mcp_is_init(p_hwfn)) {
5325 enum ecore_pci_personality protocol;
5327 protocol = p_hwfn->mcp_info->func_info.protocol;
5328 p_hwfn->hw_info.personality = protocol;
5332 /* To overcome ILT lack for emulation, until at least until we'll have
5333 * a definite answer from system about it, allow only PF0 to be RoCE.
5335 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
5336 if (!p_hwfn->rel_pf_id)
5337 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
5339 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
5343 /* although in BB some constellations may support more than 4 tcs,
5344 * that can result in performance penalty in some cases. 4
5345 * represents a good tradeoff between performance and flexibility.
5347 if (IS_ECORE_PACING(p_hwfn))
5348 p_hwfn->hw_info.num_hw_tc = 1;
5350 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
5352 /* start out with a single active tc. This can be increased either
5353 * by dcbx negotiation or by upper layer driver
5355 p_hwfn->hw_info.num_active_tc = 1;
5357 ecore_get_num_funcs(p_hwfn, p_ptt);
5359 if (ecore_mcp_is_init(p_hwfn))
5360 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
5362 /* In case of forcing the driver's default resource allocation, calling
5363 * ecore_hw_get_resc() should come after initializing the personality
5364 * and after getting the number of functions, since the calculation of
5365 * the resources/features depends on them.
5366 * This order is not harmful if not forcing.
5368 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
5369 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5371 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5377 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
5378 struct ecore_ptt *p_ptt)
5380 struct ecore_dev *p_dev = p_hwfn->p_dev;
5384 /* Read Vendor Id / Device Id */
5385 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
5387 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
5390 /* Determine type */
5391 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
5392 switch (device_id_mask) {
5393 case ECORE_DEV_ID_MASK_BB:
5394 p_dev->type = ECORE_DEV_TYPE_BB;
5396 case ECORE_DEV_ID_MASK_AH:
5397 p_dev->type = ECORE_DEV_TYPE_AH;
5400 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
5402 return ECORE_ABORTED;
5405 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
5406 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
5407 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
5408 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
5410 /* Learn number of HW-functions */
5411 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
5413 if (tmp & (1 << p_hwfn->rel_pf_id)) {
5414 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
5415 p_dev->num_hwfns = 2;
5417 p_dev->num_hwfns = 1;
5421 if (CHIP_REV_IS_EMUL(p_dev)) {
5422 /* For some reason we have problems with this register
5423 * in B0 emulation; Simply assume no CMT
5425 DP_NOTICE(p_dev->hwfns, false,
5426 "device on emul - assume no CMT\n");
5427 p_dev->num_hwfns = 1;
5431 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
5432 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
5433 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
5434 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
5436 DP_INFO(p_dev->hwfns,
5437 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
5438 ECORE_IS_BB(p_dev) ? "BB" : "AH",
5439 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
5440 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
5443 if (ECORE_IS_BB_A0(p_dev)) {
5444 DP_NOTICE(p_dev->hwfns, false,
5445 "The chip type/rev (BB A0) is not supported!\n");
5446 return ECORE_ABORTED;
5449 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
5450 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
5452 if (CHIP_REV_IS_EMUL(p_dev)) {
5453 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5454 if (tmp & (1 << 29)) {
5455 DP_NOTICE(p_hwfn, false,
5456 "Emulation: Running on a FULL build\n");
5457 p_dev->b_is_emul_full = true;
5459 DP_NOTICE(p_hwfn, false,
5460 "Emulation: Running on a REDUCED build\n");
5465 return ECORE_SUCCESS;
5468 #ifndef LINUX_REMOVE
5469 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
5476 for_each_hwfn(p_dev, j) {
5477 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
5479 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
5480 "Mark hw/fw uninitialized\n");
5482 p_hwfn->hw_init_done = false;
5484 ecore_ptt_invalidate(p_hwfn);
5489 static enum _ecore_status_t
5490 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
5491 void OSAL_IOMEM *p_doorbells, u64 db_phys_addr,
5492 struct ecore_hw_prepare_params *p_params)
5494 struct ecore_mdump_retain_data mdump_retain;
5495 struct ecore_dev *p_dev = p_hwfn->p_dev;
5496 struct ecore_mdump_info mdump_info;
5497 enum _ecore_status_t rc = ECORE_SUCCESS;
5499 /* Split PCI bars evenly between hwfns */
5500 p_hwfn->regview = p_regview;
5501 p_hwfn->doorbells = p_doorbells;
5502 p_hwfn->db_phys_addr = db_phys_addr;
5505 return ecore_vf_hw_prepare(p_hwfn);
5507 /* Validate that chip access is feasible */
5508 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
5510 "Reading the ME register returns all Fs; Preventing further chip access\n");
5511 if (p_params->b_relaxed_probe)
5512 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
5516 get_function_id(p_hwfn);
5518 /* Allocate PTT pool */
5519 rc = ecore_ptt_pool_alloc(p_hwfn);
5521 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
5522 if (p_params->b_relaxed_probe)
5523 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5527 /* Allocate the main PTT */
5528 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
5530 /* First hwfn learns basic information, e.g., number of hwfns */
5531 if (!p_hwfn->my_id) {
5532 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
5533 if (rc != ECORE_SUCCESS) {
5534 if (p_params->b_relaxed_probe)
5535 p_params->p_relaxed_res =
5536 ECORE_HW_PREPARE_FAILED_DEV;
5541 ecore_hw_hwfn_prepare(p_hwfn);
5543 /* Initialize MCP structure */
5544 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
5546 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
5547 if (p_params->b_relaxed_probe)
5548 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5552 /* Read the device configuration information from the HW and SHMEM */
5553 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
5554 p_params->personality, p_params);
5556 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
5560 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
5561 * called, since among others it sets the ports number in an engine.
5563 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
5564 !p_dev->recov_in_prog) {
5565 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
5566 if (rc != ECORE_SUCCESS)
5567 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
5569 /* Workaround for MFW issue where PF FLR does not cleanup
5572 if (!(p_hwfn->mcp_info->capabilities &
5573 FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
5574 ecore_pf_flr_igu_cleanup(p_hwfn);
5577 /* Check if mdump logs/data are present and update the epoch value */
5578 if (IS_LEAD_HWFN(p_hwfn)) {
5580 if (!CHIP_REV_IS_EMUL(p_dev)) {
5582 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
5584 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
5585 DP_NOTICE(p_hwfn, false,
5586 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
5588 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
5590 if (rc == ECORE_SUCCESS && mdump_retain.valid)
5591 DP_NOTICE(p_hwfn, false,
5592 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
5593 mdump_retain.epoch, mdump_retain.pf,
5594 mdump_retain.status);
5596 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
5603 /* Allocate the init RT array and initialize the init-ops engine */
5604 rc = ecore_init_alloc(p_hwfn);
5606 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
5607 if (p_params->b_relaxed_probe)
5608 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5612 if (CHIP_REV_IS_FPGA(p_dev)) {
5613 DP_NOTICE(p_hwfn, false,
5614 "FPGA: workaround; Prevent DMAE parities\n");
5615 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
5618 DP_NOTICE(p_hwfn, false,
5619 "FPGA: workaround: Set VF bar0 size\n");
5620 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
5621 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
5627 if (IS_LEAD_HWFN(p_hwfn))
5628 ecore_iov_free_hw_info(p_dev);
5629 ecore_mcp_free(p_hwfn);
5631 ecore_hw_hwfn_free(p_hwfn);
5636 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
5637 struct ecore_hw_prepare_params *p_params)
5639 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5640 enum _ecore_status_t rc;
5642 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
5643 p_dev->allow_mdump = p_params->allow_mdump;
5644 p_hwfn->b_en_pacing = p_params->b_en_pacing;
5645 p_dev->b_is_target = p_params->b_is_target;
5647 if (p_params->b_relaxed_probe)
5648 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
5650 /* Store the precompiled init data ptrs */
5652 ecore_init_iro_array(p_dev);
5654 /* Initialize the first hwfn - will learn number of hwfns */
5655 rc = ecore_hw_prepare_single(p_hwfn, p_dev->regview,
5656 p_dev->doorbells, p_dev->db_phys_addr,
5658 if (rc != ECORE_SUCCESS)
5661 p_params->personality = p_hwfn->hw_info.personality;
5663 /* initilalize 2nd hwfn if necessary */
5664 if (ECORE_IS_CMT(p_dev)) {
5665 void OSAL_IOMEM *p_regview, *p_doorbell;
5666 u8 OSAL_IOMEM *addr;
5670 /* adjust bar offset for second engine */
5671 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5673 addr = (u8 OSAL_IOMEM *)p_dev->regview + offset;
5674 p_regview = (void OSAL_IOMEM *)addr;
5676 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5678 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + offset;
5679 p_doorbell = (void OSAL_IOMEM *)addr;
5680 db_phys_addr = p_dev->db_phys_addr + offset;
5682 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
5683 /* prepare second hw function */
5684 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
5685 p_doorbell, db_phys_addr,
5688 /* in case of error, need to free the previously
5689 * initiliazed hwfn 0.
5691 if (rc != ECORE_SUCCESS) {
5692 if (p_params->b_relaxed_probe)
5693 p_params->p_relaxed_res =
5694 ECORE_HW_PREPARE_FAILED_ENG2;
5697 ecore_init_free(p_hwfn);
5698 ecore_mcp_free(p_hwfn);
5699 ecore_hw_hwfn_free(p_hwfn);
5701 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
5710 void ecore_hw_remove(struct ecore_dev *p_dev)
5712 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5716 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
5717 ECORE_OV_DRIVER_STATE_NOT_LOADED);
5719 for_each_hwfn(p_dev, i) {
5720 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5723 ecore_vf_pf_release(p_hwfn);
5727 ecore_init_free(p_hwfn);
5728 ecore_hw_hwfn_free(p_hwfn);
5729 ecore_mcp_free(p_hwfn);
5731 #ifdef CONFIG_ECORE_LOCK_ALLOC
5732 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
5736 ecore_iov_free_hw_info(p_dev);
5739 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
5740 struct ecore_chain *p_chain)
5742 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
5743 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
5744 struct ecore_chain_next *p_next;
5750 size = p_chain->elem_size * p_chain->usable_per_page;
5752 for (i = 0; i < p_chain->page_cnt; i++) {
5756 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
5757 p_virt_next = p_next->next_virt;
5758 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
5760 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
5761 ECORE_CHAIN_PAGE_SIZE);
5763 p_virt = p_virt_next;
5764 p_phys = p_phys_next;
5768 static void ecore_chain_free_single(struct ecore_dev *p_dev,
5769 struct ecore_chain *p_chain)
5771 if (!p_chain->p_virt_addr)
5774 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
5775 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
5778 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
5779 struct ecore_chain *p_chain)
5781 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
5782 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
5783 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
5785 if (!pp_virt_addr_tbl)
5791 for (i = 0; i < page_cnt; i++) {
5792 if (!pp_virt_addr_tbl[i])
5795 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
5796 *(dma_addr_t *)p_pbl_virt,
5797 ECORE_CHAIN_PAGE_SIZE);
5799 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
5802 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
5804 if (!p_chain->b_external_pbl)
5805 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
5806 p_chain->pbl_sp.p_phys_table, pbl_size);
5808 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
5811 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5813 switch (p_chain->mode) {
5814 case ECORE_CHAIN_MODE_NEXT_PTR:
5815 ecore_chain_free_next_ptr(p_dev, p_chain);
5817 case ECORE_CHAIN_MODE_SINGLE:
5818 ecore_chain_free_single(p_dev, p_chain);
5820 case ECORE_CHAIN_MODE_PBL:
5821 ecore_chain_free_pbl(p_dev, p_chain);
5826 static enum _ecore_status_t
5827 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
5828 enum ecore_chain_cnt_type cnt_type,
5829 osal_size_t elem_size, u32 page_cnt)
5831 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
5833 /* The actual chain size can be larger than the maximal possible value
5834 * after rounding up the requested elements number to pages, and after
5835 * taking into acount the unusuable elements (next-ptr elements).
5836 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
5837 * size/capacity fields are of a u32 type.
5839 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
5840 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
5841 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
5842 chain_size > ECORE_U32_MAX)) {
5843 DP_NOTICE(p_dev, true,
5844 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
5845 (unsigned long)chain_size);
5849 return ECORE_SUCCESS;
5852 static enum _ecore_status_t
5853 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5855 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
5856 dma_addr_t p_phys = 0;
5859 for (i = 0; i < p_chain->page_cnt; i++) {
5860 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
5861 ECORE_CHAIN_PAGE_SIZE);
5863 DP_NOTICE(p_dev, false,
5864 "Failed to allocate chain memory\n");
5869 ecore_chain_init_mem(p_chain, p_virt, p_phys);
5870 ecore_chain_reset(p_chain);
5872 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
5876 p_virt_prev = p_virt;
5878 /* Last page's next element should point to the beginning of the
5881 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
5882 p_chain->p_virt_addr,
5883 p_chain->p_phys_addr);
5885 return ECORE_SUCCESS;
5888 static enum _ecore_status_t
5889 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5891 dma_addr_t p_phys = 0;
5892 void *p_virt = OSAL_NULL;
5894 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
5896 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
5900 ecore_chain_init_mem(p_chain, p_virt, p_phys);
5901 ecore_chain_reset(p_chain);
5903 return ECORE_SUCCESS;
5906 static enum _ecore_status_t
5907 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
5908 struct ecore_chain *p_chain,
5909 struct ecore_chain_ext_pbl *ext_pbl)
5911 u32 page_cnt = p_chain->page_cnt, size, i;
5912 dma_addr_t p_phys = 0, p_pbl_phys = 0;
5913 void **pp_virt_addr_tbl = OSAL_NULL;
5914 u8 *p_pbl_virt = OSAL_NULL;
5915 void *p_virt = OSAL_NULL;
5917 size = page_cnt * sizeof(*pp_virt_addr_tbl);
5918 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
5919 if (!pp_virt_addr_tbl) {
5920 DP_NOTICE(p_dev, false,
5921 "Failed to allocate memory for the chain virtual addresses table\n");
5925 /* The allocation of the PBL table is done with its full size, since it
5926 * is expected to be successive.
5927 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
5928 * failure, since pp_virt_addr_tbl was previously allocated, and it
5929 * should be saved to allow its freeing during the error flow.
5931 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
5933 if (ext_pbl == OSAL_NULL) {
5934 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
5936 p_pbl_virt = ext_pbl->p_pbl_virt;
5937 p_pbl_phys = ext_pbl->p_pbl_phys;
5938 p_chain->b_external_pbl = true;
5941 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
5944 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
5948 for (i = 0; i < page_cnt; i++) {
5949 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
5950 ECORE_CHAIN_PAGE_SIZE);
5952 DP_NOTICE(p_dev, false,
5953 "Failed to allocate chain memory\n");
5958 ecore_chain_init_mem(p_chain, p_virt, p_phys);
5959 ecore_chain_reset(p_chain);
5962 /* Fill the PBL table with the physical address of the page */
5963 *(dma_addr_t *)p_pbl_virt = p_phys;
5964 /* Keep the virtual address of the page */
5965 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
5967 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
5970 return ECORE_SUCCESS;
5973 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
5974 enum ecore_chain_use_mode intended_use,
5975 enum ecore_chain_mode mode,
5976 enum ecore_chain_cnt_type cnt_type,
5977 u32 num_elems, osal_size_t elem_size,
5978 struct ecore_chain *p_chain,
5979 struct ecore_chain_ext_pbl *ext_pbl)
5982 enum _ecore_status_t rc = ECORE_SUCCESS;
5984 if (mode == ECORE_CHAIN_MODE_SINGLE)
5987 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
5989 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
5992 DP_NOTICE(p_dev, false,
5993 "Cannot allocate a chain with the given arguments:\n"
5994 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
5995 intended_use, mode, cnt_type, num_elems, elem_size);
5999 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
6000 mode, cnt_type, p_dev->dp_ctx);
6003 case ECORE_CHAIN_MODE_NEXT_PTR:
6004 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
6006 case ECORE_CHAIN_MODE_SINGLE:
6007 rc = ecore_chain_alloc_single(p_dev, p_chain);
6009 case ECORE_CHAIN_MODE_PBL:
6010 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
6016 return ECORE_SUCCESS;
6019 ecore_chain_free(p_dev, p_chain);
6023 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
6024 u16 src_id, u16 *dst_id)
6026 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
6029 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
6030 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
6031 DP_NOTICE(p_hwfn, true,
6032 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
6038 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
6040 return ECORE_SUCCESS;
6043 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
6044 u8 src_id, u8 *dst_id)
6046 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
6049 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
6050 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
6051 DP_NOTICE(p_hwfn, true,
6052 "vport id [%d] is not valid, available indices [%d - %d]\n",
6058 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
6060 return ECORE_SUCCESS;
6063 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
6064 u8 src_id, u8 *dst_id)
6066 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
6069 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
6070 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
6071 DP_NOTICE(p_hwfn, true,
6072 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
6078 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
6080 return ECORE_SUCCESS;
6083 enum _ecore_status_t
6084 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
6085 struct ecore_ptt *p_ptt)
6087 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
6088 ecore_wr(p_hwfn, p_ptt,
6089 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
6090 1 << p_hwfn->abs_pf_id / 2);
6091 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
6092 return ECORE_SUCCESS;
6095 DP_NOTICE(p_hwfn, false,
6096 "This function can't be set as default\n");
6100 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
6101 struct ecore_ptt *p_ptt,
6102 u32 hw_addr, void *p_eth_qzone,
6103 osal_size_t eth_qzone_size,
6106 struct coalescing_timeset *p_coal_timeset;
6108 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
6109 DP_NOTICE(p_hwfn, true,
6110 "Coalescing configuration not enabled\n");
6114 p_coal_timeset = p_eth_qzone;
6115 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
6116 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
6117 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
6118 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
6120 return ECORE_SUCCESS;
6123 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
6124 u16 rx_coal, u16 tx_coal,
6127 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
6128 enum _ecore_status_t rc = ECORE_SUCCESS;
6129 struct ecore_ptt *p_ptt;
6131 /* TODO - Configuring a single queue's coalescing but
6132 * claiming all queues are abiding same configuration
6133 * for PF and VF both.
6136 if (IS_VF(p_hwfn->p_dev))
6137 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
6140 p_ptt = ecore_ptt_acquire(p_hwfn);
6145 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
6148 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
6152 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
6155 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
6158 ecore_ptt_release(p_hwfn, p_ptt);
6163 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
6164 struct ecore_ptt *p_ptt,
6166 struct ecore_queue_cid *p_cid)
6168 struct ustorm_eth_queue_zone eth_qzone;
6169 u8 timeset, timer_res;
6171 enum _ecore_status_t rc;
6173 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6174 if (coalesce <= 0x7F) {
6176 } else if (coalesce <= 0xFF) {
6178 } else if (coalesce <= 0x1FF) {
6181 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6184 timeset = (u8)(coalesce >> timer_res);
6186 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6187 p_cid->sb_igu_id, false);
6188 if (rc != ECORE_SUCCESS)
6191 address = BAR0_MAP_REG_USDM_RAM +
6192 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6194 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
6195 sizeof(struct ustorm_eth_queue_zone), timeset);
6196 if (rc != ECORE_SUCCESS)
6203 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
6204 struct ecore_ptt *p_ptt,
6206 struct ecore_queue_cid *p_cid)
6208 struct xstorm_eth_queue_zone eth_qzone;
6209 u8 timeset, timer_res;
6211 enum _ecore_status_t rc;
6213 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6214 if (coalesce <= 0x7F) {
6216 } else if (coalesce <= 0xFF) {
6218 } else if (coalesce <= 0x1FF) {
6221 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6225 timeset = (u8)(coalesce >> timer_res);
6227 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6228 p_cid->sb_igu_id, true);
6229 if (rc != ECORE_SUCCESS)
6232 address = BAR0_MAP_REG_XSDM_RAM +
6233 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6235 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
6236 sizeof(struct xstorm_eth_queue_zone), timeset);
6241 /* Calculate final WFQ values for all vports and configure it.
6242 * After this configuration each vport must have
6243 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
6245 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6246 struct ecore_ptt *p_ptt,
6249 struct init_qm_vport_params *vport_params;
6252 vport_params = p_hwfn->qm_info.qm_vport_params;
6254 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6255 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6257 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
6259 ecore_init_vport_wfq(p_hwfn, p_ptt,
6260 vport_params[i].first_tx_pq_id,
6261 vport_params[i].vport_wfq);
6265 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
6269 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
6270 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
6273 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6274 struct ecore_ptt *p_ptt)
6276 struct init_qm_vport_params *vport_params;
6279 vport_params = p_hwfn->qm_info.qm_vport_params;
6281 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6282 ecore_init_wfq_default_param(p_hwfn);
6283 ecore_init_vport_wfq(p_hwfn, p_ptt,
6284 vport_params[i].first_tx_pq_id,
6285 vport_params[i].vport_wfq);
6289 /* This function performs several validations for WFQ
6290 * configuration and required min rate for a given vport
6291 * 1. req_rate must be greater than one percent of min_pf_rate.
6292 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
6293 * rates to get less than one percent of min_pf_rate.
6294 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
6296 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
6297 u16 vport_id, u32 req_rate,
6300 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
6301 int non_requested_count = 0, req_count = 0, i, num_vports;
6303 num_vports = p_hwfn->qm_info.num_vports;
6305 /* Accounting for the vports which are configured for WFQ explicitly */
6307 for (i = 0; i < num_vports; i++) {
6310 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
6312 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6313 total_req_min_rate += tmp_speed;
6317 /* Include current vport data as well */
6319 total_req_min_rate += req_rate;
6320 non_requested_count = num_vports - req_count;
6322 /* validate possible error cases */
6323 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
6324 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6325 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6326 vport_id, req_rate, min_pf_rate);
6330 /* TBD - for number of vports greater than 100 */
6331 if (num_vports > ECORE_WFQ_UNIT) {
6332 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6333 "Number of vports is greater than %d\n",
6338 if (total_req_min_rate > min_pf_rate) {
6339 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6340 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
6341 total_req_min_rate, min_pf_rate);
6345 /* Data left for non requested vports */
6346 total_left_rate = min_pf_rate - total_req_min_rate;
6347 left_rate_per_vp = total_left_rate / non_requested_count;
6349 /* validate if non requested get < 1% of min bw */
6350 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
6351 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6352 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6353 left_rate_per_vp, min_pf_rate);
6357 /* now req_rate for given vport passes all scenarios.
6358 * assign final wfq rates to all vports.
6360 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
6361 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
6363 for (i = 0; i < num_vports; i++) {
6364 if (p_hwfn->qm_info.wfq_data[i].configured)
6367 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
6370 return ECORE_SUCCESS;
6373 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
6374 struct ecore_ptt *p_ptt,
6375 u16 vp_id, u32 rate)
6377 struct ecore_mcp_link_state *p_link;
6378 int rc = ECORE_SUCCESS;
6380 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
6382 if (!p_link->min_pf_rate) {
6383 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
6384 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
6388 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
6390 if (rc == ECORE_SUCCESS)
6391 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
6392 p_link->min_pf_rate);
6394 DP_NOTICE(p_hwfn, false,
6395 "Validation failed while configuring min rate\n");
6400 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
6401 struct ecore_ptt *p_ptt,
6404 bool use_wfq = false;
6405 int rc = ECORE_SUCCESS;
6408 /* Validate all pre configured vports for wfq */
6409 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6412 if (!p_hwfn->qm_info.wfq_data[i].configured)
6415 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
6418 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
6419 if (rc != ECORE_SUCCESS) {
6420 DP_NOTICE(p_hwfn, false,
6421 "WFQ validation failed while configuring min rate\n");
6426 if (rc == ECORE_SUCCESS && use_wfq)
6427 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
6429 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6434 /* Main API for ecore clients to configure vport min rate.
6435 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
6436 * rate - Speed in Mbps needs to be assigned to a given vport.
6438 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
6440 int i, rc = ECORE_INVAL;
6442 /* TBD - for multiple hardware functions - that is 100 gig */
6443 if (ECORE_IS_CMT(p_dev)) {
6444 DP_NOTICE(p_dev, false,
6445 "WFQ configuration is not supported for this device\n");
6449 for_each_hwfn(p_dev, i) {
6450 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6451 struct ecore_ptt *p_ptt;
6453 p_ptt = ecore_ptt_acquire(p_hwfn);
6455 return ECORE_TIMEOUT;
6457 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
6459 if (rc != ECORE_SUCCESS) {
6460 ecore_ptt_release(p_hwfn, p_ptt);
6464 ecore_ptt_release(p_hwfn, p_ptt);
6470 /* API to configure WFQ from mcp link change */
6471 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
6472 struct ecore_ptt *p_ptt,
6477 /* TBD - for multiple hardware functions - that is 100 gig */
6478 if (ECORE_IS_CMT(p_dev)) {
6479 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
6480 "WFQ configuration is not supported for this device\n");
6484 for_each_hwfn(p_dev, i) {
6485 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6487 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
6492 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
6493 struct ecore_ptt *p_ptt,
6494 struct ecore_mcp_link_state *p_link,
6497 int rc = ECORE_SUCCESS;
6499 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
6501 if (!p_link->line_speed && (max_bw != 100))
6504 p_link->speed = (p_link->line_speed * max_bw) / 100;
6505 p_hwfn->qm_info.pf_rl = p_link->speed;
6507 /* Since the limiter also affects Tx-switched traffic, we don't want it
6508 * to limit such traffic in case there's no actual limit.
6509 * In that case, set limit to imaginary high boundary.
6512 p_hwfn->qm_info.pf_rl = 100000;
6514 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
6515 p_hwfn->qm_info.pf_rl);
6517 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6518 "Configured MAX bandwidth to be %08x Mb/sec\n",
6524 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
6525 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
6527 int i, rc = ECORE_INVAL;
6529 if (max_bw < 1 || max_bw > 100) {
6530 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
6534 for_each_hwfn(p_dev, i) {
6535 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6536 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6537 struct ecore_mcp_link_state *p_link;
6538 struct ecore_ptt *p_ptt;
6540 p_link = &p_lead->mcp_info->link_output;
6542 p_ptt = ecore_ptt_acquire(p_hwfn);
6544 return ECORE_TIMEOUT;
6546 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
6549 ecore_ptt_release(p_hwfn, p_ptt);
6551 if (rc != ECORE_SUCCESS)
6558 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
6559 struct ecore_ptt *p_ptt,
6560 struct ecore_mcp_link_state *p_link,
6563 int rc = ECORE_SUCCESS;
6565 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
6566 p_hwfn->qm_info.pf_wfq = min_bw;
6568 if (!p_link->line_speed)
6571 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
6573 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
6575 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6576 "Configured MIN bandwidth to be %d Mb/sec\n",
6577 p_link->min_pf_rate);
6582 /* Main API to configure PF min bandwidth where bw range is [1-100] */
6583 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
6585 int i, rc = ECORE_INVAL;
6587 if (min_bw < 1 || min_bw > 100) {
6588 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
6592 for_each_hwfn(p_dev, i) {
6593 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6594 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6595 struct ecore_mcp_link_state *p_link;
6596 struct ecore_ptt *p_ptt;
6598 p_link = &p_lead->mcp_info->link_output;
6600 p_ptt = ecore_ptt_acquire(p_hwfn);
6602 return ECORE_TIMEOUT;
6604 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
6606 if (rc != ECORE_SUCCESS) {
6607 ecore_ptt_release(p_hwfn, p_ptt);
6611 if (p_link->min_pf_rate) {
6612 u32 min_rate = p_link->min_pf_rate;
6614 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
6619 ecore_ptt_release(p_hwfn, p_ptt);
6625 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
6627 struct ecore_mcp_link_state *p_link;
6629 p_link = &p_hwfn->mcp_info->link_output;
6631 if (p_link->min_pf_rate)
6632 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6634 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
6635 sizeof(*p_hwfn->qm_info.wfq_data) *
6636 p_hwfn->qm_info.num_vports);
6639 int ecore_device_num_engines(struct ecore_dev *p_dev)
6641 return ECORE_IS_BB(p_dev) ? 2 : 1;
6644 int ecore_device_num_ports(struct ecore_dev *p_dev)
6646 return p_dev->num_ports;
6649 void ecore_set_fw_mac_addr(__le16 *fw_msb,
6654 ((u8 *)fw_msb)[0] = mac[1];
6655 ((u8 *)fw_msb)[1] = mac[0];
6656 ((u8 *)fw_mid)[0] = mac[3];
6657 ((u8 *)fw_mid)[1] = mac[2];
6658 ((u8 *)fw_lsb)[0] = mac[5];
6659 ((u8 *)fw_lsb)[1] = mac[4];
6662 bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
6664 return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);