drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73
  74         /* The above registers were updated in the past only in CMT mode. Since
  75          * they were found to be useful MFW started updating them from 8.7.7.0.
  76          * In older MFW versions they are set to 0 which means disabled.
  77          */
  78         if (!val) {
  79                 if (p_hwfn->p_dev->num_hwfns > 1) {
  80                         DP_NOTICE(p_hwfn, false,
  81                                   "BAR size not configured. Assuming BAR size");
  82                         DP_NOTICE(p_hwfn, false,
  83                                   "of 256kB for GRC and 512kB for DB\n");
  84                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85                 } else {
  86                         DP_NOTICE(p_hwfn, false,
  87                                   "BAR size not configured. Assuming BAR size");
  88                         DP_NOTICE(p_hwfn, false,
  89                                   "of 512kB for GRC and 512kB for DB\n");
  90                         return 512 * 1024;
  91                 }
  92         }
  93
  94         return 1 << (val + 15);
  95 }
  96
  97 void ecore_init_dp(struct ecore_dev *p_dev,
  98                    u32 dp_module, u8 dp_level, void *dp_ctx)
  99 {
 100         u32 i;
 101
 102         p_dev->dp_level = dp_level;
 103         p_dev->dp_module = dp_module;
 104         p_dev->dp_ctx = dp_ctx;
 105         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 106                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 107
 108                 p_hwfn->dp_level = dp_level;
 109                 p_hwfn->dp_module = dp_module;
 110                 p_hwfn->dp_ctx = dp_ctx;
 111         }
 112 }
 113
 114 void ecore_init_struct(struct ecore_dev *p_dev)
 115 {
 116         u8 i;
 117
 118         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 119                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 120
 121                 p_hwfn->p_dev = p_dev;
 122                 p_hwfn->my_id = i;
 123                 p_hwfn->b_active = false;
 124
 125                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 126                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 127         }
 128
 129         /* hwfn 0 is always active */
 130         p_dev->hwfns[0].b_active = true;
 131
 132         /* set the default cache alignment to 128 (may be overridden later) */
 133         p_dev->cache_shift = 7;
 134 }
 135
 136 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 137 {
 138         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 139
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 141         qm_info->qm_pq_params = OSAL_NULL;
 142         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 143         qm_info->qm_vport_params = OSAL_NULL;
 144         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 145         qm_info->qm_port_params = OSAL_NULL;
 146         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 147         qm_info->wfq_data = OSAL_NULL;
 148 }
 149
 150 void ecore_resc_free(struct ecore_dev *p_dev)
 151 {
 152         int i;
 153
 154         if (IS_VF(p_dev))
 155                 return;
 156
 157         OSAL_FREE(p_dev, p_dev->fw_data);
 158         p_dev->fw_data = OSAL_NULL;
 159
 160         OSAL_FREE(p_dev, p_dev->reset_stats);
 161
 162         for_each_hwfn(p_dev, i) {
 163                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 164
 165                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 166                 p_hwfn->p_tx_cids = OSAL_NULL;
 167                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 168                 p_hwfn->p_rx_cids = OSAL_NULL;
 169         }
 170
 171         for_each_hwfn(p_dev, i) {
 172                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 173
 174                 ecore_cxt_mngr_free(p_hwfn);
 175                 ecore_qm_info_free(p_hwfn);
 176                 ecore_spq_free(p_hwfn);
 177                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 178                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 179                 ecore_int_free(p_hwfn);
 180 #ifdef CONFIG_ECORE_LL2
 181                 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 182 #endif
 183                 ecore_iov_free(p_hwfn);
 184                 ecore_dmae_info_free(p_hwfn);
 185                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 186                 /* @@@TBD Flush work-queue ? */
 187         }
 188 }
 189
 190 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 191                                                bool b_sleepable)
 192 {
 193         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
 194         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 195         struct init_qm_port_params *p_qm_port;
 196         bool init_rdma_offload_pq = false;
 197         bool init_pure_ack_pq = false;
 198         bool init_ooo_pq = false;
 199         u16 num_pqs, protocol_pqs;
 200         u16 num_pf_rls = 0;
 201         u16 num_vfs = 0;
 202         u32 pf_rl;
 203         u8 pf_wfq;
 204
 205         /* @TMP - saving the existing min/max bw config before resetting the
 206          * qm_info to restore them.
 207          */
 208         pf_rl = qm_info->pf_rl;
 209         pf_wfq = qm_info->pf_wfq;
 210
 211 #ifdef CONFIG_ECORE_SRIOV
 212         if (p_hwfn->p_dev->p_iov_info)
 213                 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
 214 #endif
 215         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 216
 217 #ifndef ASIC_ONLY
 218         /* @TMP - Don't allocate QM queues for VFs on emulation */
 219         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 220                 DP_NOTICE(p_hwfn, false,
 221                           "Emulation - skip configuring QM queues for VFs\n");
 222                 num_vfs = 0;
 223         }
 224 #endif
 225
 226         /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
 227          * active, we want physical queues allocated for all of them, since we
 228          * don't have a good recycle flow. Non ethernet PFs require only a
 229          * single physical queue.
 230          */
 231         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 232             p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 233             p_hwfn->hw_info.personality == ECORE_PCI_ETH)
 234                 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
 235         else
 236                 protocol_pqs = 1;
 237
 238         num_pqs = protocol_pqs + num_vfs + 1;   /* The '1' is for pure-LB */
 239         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 240
 241         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 242                 num_pqs++;      /* for RoCE queue */
 243                 init_rdma_offload_pq = true;
 244                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
 245                         /* Due to FW assumption that rl==vport, we limit the
 246                          * number of rate limiters by the minimum between its
 247                          * allocated number and the allocated number of vports.
 248                          * Another limitation is the number of supported qps
 249                          * with rate limiters in FW.
 250                          */
 251                         num_pf_rls =
 252                             (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 253                                              RESC_NUM(p_hwfn, ECORE_VPORT));
 254
 255                         /* we subtract num_vfs because each one requires a rate
 256                          * limiter, and one default rate limiter.
 257                          */
 258                         if (num_pf_rls < num_vfs + 1) {
 259                                 DP_ERR(p_hwfn, "No RL for DCQCN");
 260                                 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
 261                                        num_pf_rls, num_vfs);
 262                                 return ECORE_INVAL;
 263                         }
 264                         num_pf_rls -= num_vfs + 1;
 265                 }
 266
 267                 num_pqs += num_pf_rls;
 268                 qm_info->num_pf_rls = (u8)num_pf_rls;
 269         }
 270
 271         if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
 272                 num_pqs += 3;   /* for iwarp queue / pure-ack / ooo */
 273                 init_rdma_offload_pq = true;
 274                 init_pure_ack_pq = true;
 275                 init_ooo_pq = true;
 276         }
 277
 278         if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 279                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 280                 init_pure_ack_pq = true;
 281                 init_ooo_pq = true;
 282         }
 283
 284         /* Sanity checking that setup requires legal number of resources */
 285         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 286                 DP_ERR(p_hwfn,
 287                        "Need too many Physical queues - 0x%04x avail %04x",
 288                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 289                 return ECORE_INVAL;
 290         }
 291
 292         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 293          * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
 294          */
 295         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 296                                             b_sleepable ? GFP_KERNEL :
 297                                             GFP_ATOMIC,
 298                                             sizeof(struct init_qm_pq_params) *
 299                                             num_pqs);
 300         if (!qm_info->qm_pq_params)
 301                 goto alloc_err;
 302
 303         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 304                                                b_sleepable ? GFP_KERNEL :
 305                                                GFP_ATOMIC,
 306                                                sizeof(struct
 307                                                       init_qm_vport_params) *
 308                                                num_vports);
 309         if (!qm_info->qm_vport_params)
 310                 goto alloc_err;
 311
 312         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 313                                               b_sleepable ? GFP_KERNEL :
 314                                               GFP_ATOMIC,
 315                                               sizeof(struct init_qm_port_params)
 316                                               * MAX_NUM_PORTS);
 317         if (!qm_info->qm_port_params)
 318                 goto alloc_err;
 319
 320         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 321                                         b_sleepable ? GFP_KERNEL :
 322                                         GFP_ATOMIC,
 323                                         sizeof(struct ecore_wfq_data) *
 324                                         num_vports);
 325
 326         if (!qm_info->wfq_data)
 327                 goto alloc_err;
 328
 329         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 330
 331         /* First init rate limited queues ( Due to RoCE assumption of
 332          * qpid=rlid )
 333          */
 334         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 335                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 336                 qm_info->qm_pq_params[curr_queue].tc_id =
 337                     p_hwfn->hw_info.offload_tc;
 338                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 339                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 340         };
 341
 342         /* Protocol PQs */
 343         for (i = 0; i < protocol_pqs; i++) {
 344                 struct init_qm_pq_params *params =
 345                     &qm_info->qm_pq_params[curr_queue++];
 346
 347                 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 348                     p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 349                     p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
 350                         params->vport_id = vport_id;
 351                         params->tc_id = i;
 352                         /* Note: this assumes that if we had a configuration
 353                          * with N tcs and subsequently another configuration
 354                          * With Fewer TCs, the in flight traffic (in QM queues,
 355                          * in FW, from driver to FW) will still trickle out and
 356                          * not get "stuck" in the QM. This is determined by the
 357                          * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
 358                          * supposed to be cleared in this map, allowing traffic
 359                          * to flush out. If this is not the case, we would need
 360                          * to set the TC of unused queues to 0, and reconfigure
 361                          * QM every time num of TCs changes. Unused queues in
 362                          * this context would mean those intended for TCs where
 363                          * tc_id > hw_info.num_active_tcs.
 364                          */
 365                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 366                 } else {
 367                         params->vport_id = vport_id;
 368                         params->tc_id = p_hwfn->hw_info.offload_tc;
 369                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 370                 }
 371         }
 372
 373         /* Then init pure-LB PQ */
 374         qm_info->pure_lb_pq = curr_queue;
 375         qm_info->qm_pq_params[curr_queue].vport_id =
 376             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 377         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 378         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 379         curr_queue++;
 380
 381         qm_info->offload_pq = 0;        /* Already initialized for iSCSI/FCoE */
 382         if (init_rdma_offload_pq) {
 383                 qm_info->offload_pq = curr_queue;
 384                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 385                 qm_info->qm_pq_params[curr_queue].tc_id =
 386                     p_hwfn->hw_info.offload_tc;
 387                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 388                 curr_queue++;
 389         }
 390
 391         if (init_pure_ack_pq) {
 392                 qm_info->pure_ack_pq = curr_queue;
 393                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 394                 qm_info->qm_pq_params[curr_queue].tc_id =
 395                     p_hwfn->hw_info.offload_tc;
 396                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 397                 curr_queue++;
 398         }
 399
 400         if (init_ooo_pq) {
 401                 qm_info->ooo_pq = curr_queue;
 402                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 403                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 404                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 405                 curr_queue++;
 406         }
 407
 408         /* Then init per-VF PQs */
 409         vf_offset = curr_queue;
 410         for (i = 0; i < num_vfs; i++) {
 411                 /* First vport is used by the PF */
 412                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 413                 /* @@@TBD VF Multi-cos */
 414                 qm_info->qm_pq_params[curr_queue].tc_id = 0;
 415                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 416                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 417                 curr_queue++;
 418         };
 419
 420         qm_info->vf_queues_offset = vf_offset;
 421         qm_info->num_pqs = num_pqs;
 422         qm_info->num_vports = num_vports;
 423
 424         /* Initialize qm port parameters */
 425         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 426         for (i = 0; i < num_ports; i++) {
 427                 p_qm_port = &qm_info->qm_port_params[i];
 428                 p_qm_port->active = 1;
 429                 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
 430                  * be in place
 431                  */
 432                 if (num_ports == 4)
 433                         p_qm_port->active_phys_tcs = 0xf;
 434                 else
 435                         p_qm_port->active_phys_tcs = 0x9f;
 436                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 437                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 438         }
 439
 440         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 441                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 442         else
 443                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 444
 445         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 446
 447         qm_info->num_vf_pqs = num_vfs;
 448         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 449
 450         for (i = 0; i < qm_info->num_vports; i++)
 451                 qm_info->qm_vport_params[i].vport_wfq = 1;
 452
 453         qm_info->vport_rl_en = 1;
 454         qm_info->vport_wfq_en = 1;
 455         qm_info->pf_rl = pf_rl;
 456         qm_info->pf_wfq = pf_wfq;
 457
 458         return ECORE_SUCCESS;
 459
 460  alloc_err:
 461         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 462         ecore_qm_info_free(p_hwfn);
 463         return ECORE_NOMEM;
 464 }
 465
 466 /* This function reconfigures the QM pf on the fly.
 467  * For this purpose we:
 468  * 1. reconfigure the QM database
 469  * 2. set new values to runtime arrat
 470  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 471  * 4. activate init tool in QM_PF stage
 472  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 473  */
 474 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 475                                      struct ecore_ptt *p_ptt)
 476 {
 477         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 478         bool b_rc;
 479         enum _ecore_status_t rc;
 480
 481         /* qm_info is allocated in ecore_init_qm_info() which is already called
 482          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 483          * The allocated size may change each init, so we free it before next
 484          * allocation.
 485          */
 486         ecore_qm_info_free(p_hwfn);
 487
 488         /* initialize ecore's qm data structure */
 489         rc = ecore_init_qm_info(p_hwfn, false);
 490         if (rc != ECORE_SUCCESS)
 491                 return rc;
 492
 493         /* stop PF's qm queues */
 494         OSAL_SPIN_LOCK(&qm_lock);
 495         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 496                                       qm_info->start_pq, qm_info->num_pqs);
 497         OSAL_SPIN_UNLOCK(&qm_lock);
 498         if (!b_rc)
 499                 return ECORE_INVAL;
 500
 501         /* clear the QM_PF runtime phase leftovers from previous init */
 502         ecore_init_clear_rt_data(p_hwfn);
 503
 504         /* prepare QM portion of runtime array */
 505         ecore_qm_init_pf(p_hwfn);
 506
 507         /* activate init tool on runtime array */
 508         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 509                             p_hwfn->hw_info.hw_mode);
 510         if (rc != ECORE_SUCCESS)
 511                 return rc;
 512
 513         /* start PF's qm queues */
 514         OSAL_SPIN_LOCK(&qm_lock);
 515         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 516                                       qm_info->start_pq, qm_info->num_pqs);
 517         OSAL_SPIN_UNLOCK(&qm_lock);
 518         if (!b_rc)
 519                 return ECORE_INVAL;
 520
 521         return ECORE_SUCCESS;
 522 }
 523
 524 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 525 {
 526         struct ecore_consq *p_consq;
 527         struct ecore_eq *p_eq;
 528 #ifdef  CONFIG_ECORE_LL2
 529         struct ecore_ll2_info *p_ll2_info;
 530 #endif
 531         enum _ecore_status_t rc = ECORE_SUCCESS;
 532         int i;
 533
 534         if (IS_VF(p_dev))
 535                 return rc;
 536
 537         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 538                                      sizeof(*p_dev->fw_data));
 539         if (!p_dev->fw_data)
 540                 return ECORE_NOMEM;
 541
 542         /* Allocate Memory for the Queue->CID mapping */
 543         for_each_hwfn(p_dev, i) {
 544                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 545                 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 546                 int tx_size, rx_size;
 547
 548                 /* @@@TMP - resc management, change to actual required size */
 549                 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
 550                         num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
 551                 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
 552                 rx_size = sizeof(struct ecore_hw_cid_data) *
 553                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 554
 555                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 556                                                 tx_size);
 557                 if (!p_hwfn->p_tx_cids) {
 558                         DP_NOTICE(p_hwfn, true,
 559                                   "Failed to allocate memory for Tx Cids\n");
 560                         goto alloc_no_mem;
 561                 }
 562
 563                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 564                                                 rx_size);
 565                 if (!p_hwfn->p_rx_cids) {
 566                         DP_NOTICE(p_hwfn, true,
 567                                   "Failed to allocate memory for Rx Cids\n");
 568                         goto alloc_no_mem;
 569                 }
 570         }
 571
 572         for_each_hwfn(p_dev, i) {
 573                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 574                 u32 n_eqes, num_cons;
 575
 576                 /* First allocate the context manager structure */
 577                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 578                 if (rc)
 579                         goto alloc_err;
 580
 581                 /* Set the HW cid/tid numbers (in the contest manager)
 582                  * Must be done prior to any further computations.
 583                  */
 584                 rc = ecore_cxt_set_pf_params(p_hwfn);
 585                 if (rc)
 586                         goto alloc_err;
 587
 588                 /* Prepare and process QM requirements */
 589                 rc = ecore_init_qm_info(p_hwfn, true);
 590                 if (rc)
 591                         goto alloc_err;
 592
 593                 /* Compute the ILT client partition */
 594                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 595                 if (rc)
 596                         goto alloc_err;
 597
 598                 /* CID map / ILT shadow table / T2
 599                  * The talbes sizes are determined by the computations above
 600                  */
 601                 rc = ecore_cxt_tables_alloc(p_hwfn);
 602                 if (rc)
 603                         goto alloc_err;
 604
 605                 /* SPQ, must follow ILT because initializes SPQ context */
 606                 rc = ecore_spq_alloc(p_hwfn);
 607                 if (rc)
 608                         goto alloc_err;
 609
 610                 /* SP status block allocation */
 611                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 612                                                            RESERVED_PTT_DPC);
 613
 614                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 615                 if (rc)
 616                         goto alloc_err;
 617
 618                 rc = ecore_iov_alloc(p_hwfn);
 619                 if (rc)
 620                         goto alloc_err;
 621
 622                 /* EQ */
 623                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 624                 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
 625                     (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
 626                         /* Calculate the EQ size
 627                          * ---------------------
 628                          * Each ICID may generate up to one event at a time i.e.
 629                          * the event must be handled/cleared before a new one
 630                          * can be generated. We calculate the sum of events per
 631                          * protocol and create an EQ deep enough to handle the
 632                          * worst case:
 633                          * - Core - according to SPQ.
 634                          * - RoCE - per QP there are a couple of ICIDs, one
 635                          *          responder and one requester, each can
 636                          *          generate an EQE => n_eqes_qp = 2 * n_qp.
 637                          *          Each CQ can generate an EQE. There are 2 CQs
 638                          *          per QP => n_eqes_cq = 2 * n_qp.
 639                          *          Hence the RoCE total is 4 * n_qp or
 640                          *          2 * num_cons.
 641                          * - ENet - There can be up to two events per VF. One
 642                          *          for VF-PF channel and another for VF FLR
 643                          *          initial cleanup. The number of VFs is
 644                          *          bounded by MAX_NUM_VFS_BB, and is much
 645                          *          smaller than RoCE's so we avoid exact
 646                          *          calculation.
 647                          */
 648                         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 649                                 num_cons =
 650                                     ecore_cxt_get_proto_cid_count(
 651                                                 p_hwfn,
 652                                                 PROTOCOLID_ROCE,
 653                                                 0);
 654                                 num_cons *= 2;
 655                         } else {
 656                                 num_cons = ecore_cxt_get_proto_cid_count(
 657                                                 p_hwfn,
 658                                                 PROTOCOLID_IWARP,
 659                                                 0);
 660                         }
 661                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 662                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 663                         num_cons =
 664                             ecore_cxt_get_proto_cid_count(p_hwfn,
 665                                                           PROTOCOLID_ISCSI, 0);
 666                         n_eqes += 2 * num_cons;
 667                 }
 668
 669                 if (n_eqes > 0xFFFF) {
 670                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 671                                        "The maximum of a u16 chain is 0x%x\n",
 672                                n_eqes, 0xFFFF);
 673                         rc = ECORE_INVAL;
 674                         goto alloc_err;
 675                 }
 676
 677                 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 678                 if (!p_eq)
 679                         goto alloc_no_mem;
 680                 p_hwfn->p_eq = p_eq;
 681
 682                 p_consq = ecore_consq_alloc(p_hwfn);
 683                 if (!p_consq)
 684                         goto alloc_no_mem;
 685                 p_hwfn->p_consq = p_consq;
 686
 687 #ifdef CONFIG_ECORE_LL2
 688                 if (p_hwfn->using_ll2) {
 689                         p_ll2_info = ecore_ll2_alloc(p_hwfn);
 690                         if (!p_ll2_info)
 691                                 goto alloc_no_mem;
 692                         p_hwfn->p_ll2_info = p_ll2_info;
 693                 }
 694 #endif
 695
 696                 /* DMA info initialization */
 697                 rc = ecore_dmae_info_alloc(p_hwfn);
 698                 if (rc) {
 699                         DP_NOTICE(p_hwfn, true,
 700                                   "Failed to allocate memory for dmae_info structure\n");
 701                         goto alloc_err;
 702                 }
 703
 704                 /* DCBX initialization */
 705                 rc = ecore_dcbx_info_alloc(p_hwfn);
 706                 if (rc) {
 707                         DP_NOTICE(p_hwfn, true,
 708                                   "Failed to allocate memory for dcbx structure\n");
 709                         goto alloc_err;
 710                 }
 711         }
 712
 713         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 714                                          sizeof(struct ecore_eth_stats));
 715         if (!p_dev->reset_stats) {
 716                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 717                 goto alloc_no_mem;
 718         }
 719
 720         return ECORE_SUCCESS;
 721
 722  alloc_no_mem:
 723         rc = ECORE_NOMEM;
 724  alloc_err:
 725         ecore_resc_free(p_dev);
 726         return rc;
 727 }
 728
 729 void ecore_resc_setup(struct ecore_dev *p_dev)
 730 {
 731         int i;
 732
 733         if (IS_VF(p_dev))
 734                 return;
 735
 736         for_each_hwfn(p_dev, i) {
 737                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 738
 739                 ecore_cxt_mngr_setup(p_hwfn);
 740                 ecore_spq_setup(p_hwfn);
 741                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 742                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 743
 744                 /* Read shadow of current MFW mailbox */
 745                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 746                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 747                             p_hwfn->mcp_info->mfw_mb_cur,
 748                             p_hwfn->mcp_info->mfw_mb_length);
 749
 750                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 751
 752                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 753 #ifdef CONFIG_ECORE_LL2
 754                 if (p_hwfn->using_ll2)
 755                         ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
 756 #endif
 757         }
 758 }
 759
 760 #define FINAL_CLEANUP_POLL_CNT  (100)
 761 #define FINAL_CLEANUP_POLL_TIME (10)
 762 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 763                                          struct ecore_ptt *p_ptt,
 764                                          u16 id, bool is_vf)
 765 {
 766         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 767         enum _ecore_status_t rc = ECORE_TIMEOUT;
 768
 769 #ifndef ASIC_ONLY
 770         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 771             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 772                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 773                 return ECORE_SUCCESS;
 774         }
 775 #endif
 776
 777         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 778             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 779
 780         if (is_vf)
 781                 id += 0x10;
 782
 783         command |= X_FINAL_CLEANUP_AGG_INT <<
 784             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 785         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 786         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 787         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 788
 789 /* Make sure notification is not set before initiating final cleanup */
 790
 791         if (REG_RD(p_hwfn, addr)) {
 792                 DP_NOTICE(p_hwfn, false,
 793                           "Unexpected; Found final cleanup notification");
 794                 DP_NOTICE(p_hwfn, false,
 795                           " before initiating final cleanup\n");
 796                 REG_WR(p_hwfn, addr, 0);
 797         }
 798
 799         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 800                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 801                    id, OSAL_CPU_TO_LE32(command));
 802
 803         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
 804                  OSAL_CPU_TO_LE32(command));
 805
 806         /* Poll until completion */
 807         while (!REG_RD(p_hwfn, addr) && count--)
 808                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 809
 810         if (REG_RD(p_hwfn, addr))
 811                 rc = ECORE_SUCCESS;
 812         else
 813                 DP_NOTICE(p_hwfn, true,
 814                           "Failed to receive FW final cleanup notification\n");
 815
 816         /* Cleanup afterwards */
 817         REG_WR(p_hwfn, addr, 0);
 818
 819         return rc;
 820 }
 821
 822 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 823 {
 824         int hw_mode = 0;
 825
 826         if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
 827                 hw_mode |= 1 << MODE_BB_A0;
 828         } else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
 829                 hw_mode |= 1 << MODE_BB_B0;
 830         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
 831                 hw_mode |= 1 << MODE_K2;
 832         } else {
 833                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
 834                           p_hwfn->p_dev->type);
 835                 return ECORE_INVAL;
 836         }
 837
 838         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 839         switch (p_hwfn->p_dev->num_ports_in_engines) {
 840         case 1:
 841                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 842                 break;
 843         case 2:
 844                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 845                 break;
 846         case 4:
 847                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 848                 break;
 849         default:
 850                 DP_NOTICE(p_hwfn, true,
 851                           "num_ports_in_engine = %d not supported\n",
 852                           p_hwfn->p_dev->num_ports_in_engines);
 853                 return ECORE_INVAL;
 854         }
 855
 856         switch (p_hwfn->p_dev->mf_mode) {
 857         case ECORE_MF_DEFAULT:
 858         case ECORE_MF_NPAR:
 859                 hw_mode |= 1 << MODE_MF_SI;
 860                 break;
 861         case ECORE_MF_OVLAN:
 862                 hw_mode |= 1 << MODE_MF_SD;
 863                 break;
 864         default:
 865                 DP_NOTICE(p_hwfn, true,
 866                           "Unsupported MF mode, init as DEFAULT\n");
 867                 hw_mode |= 1 << MODE_MF_SI;
 868         }
 869
 870 #ifndef ASIC_ONLY
 871         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 872                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 873                         hw_mode |= 1 << MODE_FPGA;
 874                 } else {
 875                         if (p_hwfn->p_dev->b_is_emul_full)
 876                                 hw_mode |= 1 << MODE_EMUL_FULL;
 877                         else
 878                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 879                 }
 880         } else
 881 #endif
 882                 hw_mode |= 1 << MODE_ASIC;
 883
 884 #ifndef REAL_ASIC_ONLY
 885         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))
 886                 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND;
 887 #endif
 888
 889         if (p_hwfn->p_dev->num_hwfns > 1)
 890                 hw_mode |= 1 << MODE_100G;
 891
 892         p_hwfn->hw_info.hw_mode = hw_mode;
 893
 894         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 895                    "Configuring function for hw_mode: 0x%08x\n",
 896                    p_hwfn->hw_info.hw_mode);
 897
 898         return ECORE_SUCCESS;
 899 }
 900
 901 #ifndef ASIC_ONLY
 902 /* MFW-replacement initializations for non-ASIC */
 903 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 904                                                struct ecore_ptt *p_ptt)
 905 {
 906         u32 pl_hv = 1;
 907         int i;
 908
 909         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 910                 pl_hv |= 0x600;
 911
 912         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 913
 914         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 915                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
 916
 917         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 918         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 919         if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
 920                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
 921
 922         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
 923                 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 924                 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 925                          (p_hwfn->p_dev->num_ports_in_engines >> 1));
 926
 927                 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 928                          p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
 929         }
 930
 931         /* Poll on RBC */
 932         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 933         for (i = 0; i < 100; i++) {
 934                 OSAL_UDELAY(50);
 935                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 936                         break;
 937         }
 938         if (i == 100)
 939                 DP_NOTICE(p_hwfn, true,
 940                           "RBC done failed to complete in PSWRQ2\n");
 941
 942         return ECORE_SUCCESS;
 943 }
 944 #endif
 945
 946 /* Init run time data for all PFs and their VFs on an engine.
 947  * TBD - for VFs - Once we have parent PF info for each VF in
 948  * shmem available as CAU requires knowledge of parent PF for each VF.
 949  */
 950 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 951 {
 952         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 953         int i, sb_id;
 954
 955         for_each_hwfn(p_dev, i) {
 956                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 957                 struct ecore_igu_info *p_igu_info;
 958                 struct ecore_igu_block *p_block;
 959                 struct cau_sb_entry sb_entry;
 960
 961                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 962
 963                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 964                      sb_id++) {
 965                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 966
 967                         if (!p_block->is_pf)
 968                                 continue;
 969
 970                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 971                                                 p_block->function_id, 0, 0);
 972                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 973                 }
 974         }
 975 }
 976
 977 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 978                                                  struct ecore_ptt *p_ptt,
 979                                                  int hw_mode)
 980 {
 981         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 982         struct ecore_dev *p_dev = p_hwfn->p_dev;
 983         u8 vf_id, max_num_vfs;
 984         u16 num_pfs, pf_id;
 985         u32 concrete_fid;
 986         enum _ecore_status_t rc = ECORE_SUCCESS;
 987
 988         ecore_init_cau_rt_data(p_dev);
 989
 990         /* Program GTT windows */
 991         ecore_gtt_init(p_hwfn);
 992
 993 #ifndef ASIC_ONLY
 994         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 995                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 996                 if (rc != ECORE_SUCCESS)
 997                         return rc;
 998         }
 999 #endif
1000
1001         if (p_hwfn->mcp_info) {
1002                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1003                         qm_info->pf_rl_en = 1;
1004                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1005                         qm_info->pf_wfq_en = 1;
1006         }
1007
1008         ecore_qm_common_rt_init(p_hwfn,
1009                                 p_hwfn->p_dev->num_ports_in_engines,
1010                                 qm_info->max_phys_tcs_per_port,
1011                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1012                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1013                                 qm_info->qm_port_params);
1014
1015         ecore_cxt_hw_init_common(p_hwfn);
1016
1017         /* Close gate from NIG to BRB/Storm; By default they are open, but
1018          * we close them to prevent NIG from passing data to reset blocks.
1019          * Should have been done in the ENGINE phase, but init-tool lacks
1020          * proper port-pretend capabilities.
1021          */
1022         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1023         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1024         ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1025         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1026         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1027         ecore_port_unpretend(p_hwfn, p_ptt);
1028
1029         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1030         if (rc != ECORE_SUCCESS)
1031                 return rc;
1032
1033         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1034          * need to decide with which value, maybe runtime
1035          */
1036         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1037         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1038
1039         if (ECORE_IS_BB(p_hwfn->p_dev)) {
1040                 /* Workaround clears ROCE search for all functions to prevent
1041                  * involving non initialized function in processing ROCE packet.
1042                  */
1043                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1044                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1045                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1046                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1047                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1048                 }
1049                 /* pretend to original PF */
1050                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1051         }
1052
1053         /* Workaround for avoiding CCFC execution error when getting packets
1054          * with CRC errors, and allowing instead the invoking of the FW error
1055          * handler.
1056          * This is not done inside the init tool since it currently can't
1057          * perform a pretending to VFs.
1058          */
1059         max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2
1060             : MAX_NUM_VFS_BB;
1061         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1062                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1063                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1064                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1065                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1066                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1067                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1068         }
1069         /* pretend to original PF */
1070         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1071
1072         return rc;
1073 }
1074
1075 #ifndef ASIC_ONLY
1076 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1077 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1078
1079 #define PMEG_IF_BYTE_COUNT      8
1080
1081 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1082                              struct ecore_ptt *p_ptt,
1083                              u32 addr, u64 data, u8 reg_type, u8 port)
1084 {
1085         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1086                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1087                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
1088                    (8 << PMEG_IF_BYTE_COUNT),
1089                    (reg_type << 25) | (addr << 8) | port,
1090                    (u32)((data >> 32) & 0xffffffff),
1091                    (u32)(data & 0xffffffff));
1092
1093         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
1094                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
1095                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1096         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
1097                  (reg_type << 25) | (addr << 8) | port);
1098         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1099                  data & 0xffffffff);
1100         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1101                  (data >> 32) & 0xffffffff);
1102 }
1103
1104 #define XLPORT_MODE_REG (0x20a)
1105 #define XLPORT_MAC_CONTROL (0x210)
1106 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1107 #define XLPORT_ENABLE_REG (0x20b)
1108
1109 #define XLMAC_CTRL (0x600)
1110 #define XLMAC_MODE (0x601)
1111 #define XLMAC_RX_MAX_SIZE (0x608)
1112 #define XLMAC_TX_CTRL (0x604)
1113 #define XLMAC_PAUSE_CTRL (0x60d)
1114 #define XLMAC_PFC_CTRL (0x60e)
1115
1116 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
1117                                     struct ecore_ptt *p_ptt)
1118 {
1119         u8 port = p_hwfn->port_id;
1120         u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
1121
1122         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
1123                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
1124                  (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
1125                  | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
1126
1127         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
1128                  1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
1129
1130         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
1131                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
1132
1133         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
1134                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
1135
1136         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
1137                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
1138
1139         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
1140                  (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
1141                  (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
1142
1143         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
1144 }
1145
1146 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1147                                  struct ecore_ptt *p_ptt)
1148 {
1149         u8 loopback = 0, port = p_hwfn->port_id * 2;
1150
1151         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1152
1153         if (ECORE_IS_AH(p_hwfn->p_dev)) {
1154                 ecore_emul_link_init_ah(p_hwfn, p_ptt);
1155                 return;
1156         }
1157
1158         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1159         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1160                          port);
1161         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1162         /* XLMAC: SOFT RESET */
1163         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1164         /* XLMAC: Port Speed >= 10Gbps */
1165         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1166         /* XLMAC: Max Size */
1167         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1168         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1169                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1170                          0, port);
1171         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1172         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1173                          0x30ffffc000ULL, 0, port);
1174         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1175                          port); /* XLMAC: TX_EN, RX_EN */
1176         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1177         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1178                          0x1003 | (loopback << 2), 0, port);
1179         /* Enabled Parallel PFC interface */
1180         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1181
1182         /* XLPORT port enable */
1183         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1184 }
1185
1186 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
1187                             struct ecore_ptt *p_ptt, u8 port)
1188 {
1189         int port_offset = port ? 0x800 : 0;
1190         u32 xmac_rxctrl = 0;
1191
1192         /* Reset of XMAC */
1193         /* FIXME: move to common start */
1194         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1195                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1196         OSAL_MSLEEP(1);
1197         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1198                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1199
1200         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1201
1202         /* Set the number of ports on the Warp Core to 10G */
1203         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1204
1205         /* Soft reset of XMAC */
1206         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1207                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1208         OSAL_MSLEEP(1);
1209         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1210                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1211
1212         /* FIXME: move to common end */
1213         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1214                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
1215
1216         /* Set Max packet size: initialize XMAC block register for port 0 */
1217         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
1218
1219         /* CRC append for Tx packets: init XMAC block register for port 1 */
1220         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
1221
1222         /* Enable TX and RX: initialize XMAC block register for port 1 */
1223         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
1224                  XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
1225         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
1226         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
1227         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1228 }
1229 #endif
1230
1231 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1232                                                struct ecore_ptt *p_ptt,
1233                                                int hw_mode)
1234 {
1235         enum _ecore_status_t rc = ECORE_SUCCESS;
1236
1237         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1238                             hw_mode);
1239         if (rc != ECORE_SUCCESS)
1240                 return rc;
1241 #ifndef ASIC_ONLY
1242         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1243                 return ECORE_SUCCESS;
1244
1245         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1246                 if (ECORE_IS_AH(p_hwfn->p_dev))
1247                         return ECORE_SUCCESS;
1248                 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1249         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1250                 if (p_hwfn->p_dev->num_hwfns > 1) {
1251                         /* Activate OPTE in CMT */
1252                         u32 val;
1253
1254                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1255                         val |= 0x10;
1256                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1257                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1258                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1259                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1260                         ecore_wr(p_hwfn, p_ptt,
1261                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1262                         ecore_wr(p_hwfn, p_ptt,
1263                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1264                         ecore_wr(p_hwfn, p_ptt,
1265                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1266                                  0x55555555);
1267                 }
1268
1269                 ecore_emul_link_init(p_hwfn, p_ptt);
1270         } else {
1271                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1272         }
1273 #endif
1274
1275         return rc;
1276 }
1277
1278 static enum _ecore_status_t
1279 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1280                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1281 {
1282         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1283         u32 dpi_bit_shift, dpi_count;
1284         u32 min_dpis;
1285
1286         /* Calculate DPI size
1287          * ------------------
1288          * The PWM region contains Doorbell Pages. The first is reserverd for
1289          * the kernel for, e.g, L2. The others are free to be used by non-
1290          * trusted applications, typically from user space. Each page, called a
1291          * doorbell page is sectioned into windows that allow doorbells to be
1292          * issued in parallel by the kernel/application. The size of such a
1293          * window (a.k.a. WID) is 1kB.
1294          * Summary:
1295          *    1kB WID x N WIDS = DPI page size
1296          *    DPI page size x N DPIs = PWM region size
1297          * Notes:
1298          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1299          * in order to ensure that two applications won't share the same page.
1300          * It also must contain at least one WID per CPU to allow parallelism.
1301          * It also must be a power of 2, since it is stored as a bit shift.
1302          *
1303          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1304          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1305          * containing 4 WIDs.
1306          */
1307         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1308         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1309         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1310         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1311         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1312
1313         dpi_count = pwm_region_size / dpi_page_size;
1314
1315         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1316         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1317
1318         /* Update hwfn */
1319         p_hwfn->dpi_size = dpi_page_size;
1320         p_hwfn->dpi_count = dpi_count;
1321
1322         /* Update registers */
1323         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1324
1325         if (dpi_count < min_dpis)
1326                 return ECORE_NORESOURCES;
1327
1328         return ECORE_SUCCESS;
1329 }
1330
1331 enum ECORE_ROCE_EDPM_MODE {
1332         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1333         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1334         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1335 };
1336
1337 static enum _ecore_status_t
1338 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1339                               struct ecore_ptt *p_ptt)
1340 {
1341         u32 pwm_regsize, norm_regsize;
1342         u32 non_pwm_conn, min_addr_reg1;
1343         u32 db_bar_size, n_cpus;
1344         u32 roce_edpm_mode;
1345         u32 pf_dems_shift;
1346         int rc = ECORE_SUCCESS;
1347         u8 cond;
1348
1349         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1350         if (p_hwfn->p_dev->num_hwfns > 1)
1351                 db_bar_size /= 2;
1352
1353         /* Calculate doorbell regions
1354          * -----------------------------------
1355          * The doorbell BAR is made of two regions. The first is called normal
1356          * region and the second is called PWM region. In the normal region
1357          * each ICID has its own set of addresses so that writing to that
1358          * specific address identifies the ICID. In the Process Window Mode
1359          * region the ICID is given in the data written to the doorbell. The
1360          * above per PF register denotes the offset in the doorbell BAR in which
1361          * the PWM region begins.
1362          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1363          * non-PWM connection. The calculation below computes the total non-PWM
1364          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1365          * in units of 4,096 bytes.
1366          */
1367         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1368             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1369                                           OSAL_NULL) +
1370             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1371         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1372         min_addr_reg1 = norm_regsize / 4096;
1373         pwm_regsize = db_bar_size - norm_regsize;
1374
1375         /* Check that the normal and PWM sizes are valid */
1376         if (db_bar_size < norm_regsize) {
1377                 DP_ERR(p_hwfn->p_dev,
1378                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1379                        db_bar_size, norm_regsize);
1380                 return ECORE_NORESOURCES;
1381         }
1382         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1383                 DP_ERR(p_hwfn->p_dev,
1384                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1385                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1386                        norm_regsize);
1387                 return ECORE_NORESOURCES;
1388         }
1389
1390         /* Calculate number of DPIs */
1391         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1392         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1393             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1394                 /* Either EDPM is mandatory, or we are attempting to allocate a
1395                  * WID per CPU.
1396                  */
1397                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1398                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1399         }
1400
1401         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1402             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1403         if (cond || p_hwfn->dcbx_no_edpm) {
1404                 /* Either EDPM is disabled from user configuration, or it is
1405                  * disabled via DCBx, or it is not mandatory and we failed to
1406                  * allocated a WID per CPU.
1407                  */
1408                 n_cpus = 1;
1409                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1410
1411                 /* If we entered this flow due to DCBX then the DPM register is
1412                  * already configured.
1413                  */
1414         }
1415
1416         DP_INFO(p_hwfn,
1417                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1418                 norm_regsize, pwm_regsize);
1419         DP_INFO(p_hwfn,
1420                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1421                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1422                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1423                 "disabled" : "enabled");
1424
1425         /* Check return codes from above calls */
1426         if (rc) {
1427                 DP_ERR(p_hwfn,
1428                        "Failed to allocate enough DPIs\n");
1429                 return ECORE_NORESOURCES;
1430         }
1431
1432         /* Update hwfn */
1433         p_hwfn->dpi_start_offset = norm_regsize;
1434
1435         /* Update registers */
1436         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1437         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1438         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1439         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1440
1441         return ECORE_SUCCESS;
1442 }
1443
1444 static enum _ecore_status_t
1445 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1446                  struct ecore_ptt *p_ptt,
1447                  struct ecore_tunn_start_params *p_tunn,
1448                  int hw_mode,
1449                  bool b_hw_start,
1450                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1451 {
1452         u8 rel_pf_id = p_hwfn->rel_pf_id;
1453         u32 prs_reg;
1454         enum _ecore_status_t rc = ECORE_SUCCESS;
1455         u16 ctrl;
1456         int pos;
1457
1458         if (p_hwfn->mcp_info) {
1459                 struct ecore_mcp_function_info *p_info;
1460
1461                 p_info = &p_hwfn->mcp_info->func_info;
1462                 if (p_info->bandwidth_min)
1463                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1464
1465                 /* Update rate limit once we'll actually have a link */
1466                 p_hwfn->qm_info.pf_rl = 100000;
1467         }
1468         ecore_cxt_hw_init_pf(p_hwfn);
1469
1470         ecore_int_igu_init_rt(p_hwfn);
1471
1472         /* Set VLAN in NIG if needed */
1473         if (hw_mode & (1 << MODE_MF_SD)) {
1474                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1475                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1476                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1477                              p_hwfn->hw_info.ovlan);
1478         }
1479
1480         /* Enable classification by MAC if needed */
1481         if (hw_mode & (1 << MODE_MF_SI)) {
1482                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1483                            "Configuring TAGMAC_CLS_TYPE\n");
1484                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1485                              1);
1486         }
1487
1488         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1489         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1490                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1491         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1492                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1493         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1494
1495         /* perform debug configuration when chip is out of reset */
1496         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1497
1498         /* Cleanup chip from previous driver if such remains exist */
1499         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1500         if (rc != ECORE_SUCCESS) {
1501                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1502                 return rc;
1503         }
1504
1505         /* PF Init sequence */
1506         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1507         if (rc)
1508                 return rc;
1509
1510         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1511         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1512         if (rc)
1513                 return rc;
1514
1515         /* Pure runtime initializations - directly to the HW  */
1516         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1517
1518         /* PCI relaxed ordering causes a decrease in the performance on some
1519          * systems. Till a root cause is found, disable this attribute in the
1520          * PCI config space.
1521          */
1522         /* Not in use @DPDK
1523         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1524         * if (!pos) {
1525         *       DP_NOTICE(p_hwfn, true,
1526         *                 "Failed to find the PCIe Cap\n");
1527         *       return ECORE_IO;
1528         * }
1529         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1530         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1531         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1532         */
1533
1534         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1535         if (rc)
1536                 return rc;
1537         if (b_hw_start) {
1538                 /* enable interrupts */
1539                 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1540
1541                 /* send function start command */
1542                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1543                                        allow_npar_tx_switch);
1544                 if (rc) {
1545                         DP_NOTICE(p_hwfn, true,
1546                                   "Function start ramrod failed\n");
1547                 } else {
1548                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1549                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1550                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1551
1552                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1553                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1554                                          (1 << 2));
1555                                 ecore_wr(p_hwfn, p_ptt,
1556                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1557                                     0x100);
1558                         }
1559                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1560                                    "PRS_REG_SEARCH registers after start PFn\n");
1561                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1562                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1563                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1564                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1565                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1566                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1567                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1568                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1569                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1570                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1571                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1572                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1573                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1574                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1575                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1576                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1577                                    prs_reg);
1578                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1579                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1580                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1581                 }
1582         }
1583         return rc;
1584 }
1585
1586 static enum _ecore_status_t
1587 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1588                       struct ecore_ptt *p_ptt, u8 enable)
1589 {
1590         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1591
1592         /* Change PF in PXP */
1593         ecore_wr(p_hwfn, p_ptt,
1594                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1595
1596         /* wait until value is set - try for 1 second every 50us */
1597         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1598                 val = ecore_rd(p_hwfn, p_ptt,
1599                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1600                 if (val == set_val)
1601                         break;
1602
1603                 OSAL_UDELAY(50);
1604         }
1605
1606         if (val != set_val) {
1607                 DP_NOTICE(p_hwfn, true,
1608                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1609                 return ECORE_UNKNOWN_ERROR;
1610         }
1611
1612         return ECORE_SUCCESS;
1613 }
1614
1615 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1616                                   struct ecore_ptt *p_main_ptt)
1617 {
1618         /* Read shadow of current MFW mailbox */
1619         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1620         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1621                     p_hwfn->mcp_info->mfw_mb_cur,
1622                     p_hwfn->mcp_info->mfw_mb_length);
1623 }
1624
1625 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1626                                    struct ecore_hw_init_params *p_params)
1627 {
1628         enum _ecore_status_t rc, mfw_rc;
1629         u32 load_code, param;
1630         int i, j;
1631
1632         if (p_params->int_mode == ECORE_INT_MODE_MSI && p_dev->num_hwfns > 1) {
1633                 DP_NOTICE(p_dev, false,
1634                           "MSI mode is not supported for CMT devices\n");
1635                 return ECORE_INVAL;
1636         }
1637
1638         if (IS_PF(p_dev)) {
1639                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1640                 if (rc != ECORE_SUCCESS)
1641                         return rc;
1642         }
1643
1644         for_each_hwfn(p_dev, i) {
1645                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1646
1647                 if (IS_VF(p_dev)) {
1648                         p_hwfn->b_int_enabled = 1;
1649                         continue;
1650                 }
1651
1652                 /* Enable DMAE in PXP */
1653                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1654                 if (rc != ECORE_SUCCESS)
1655                         return rc;
1656
1657                 rc = ecore_calc_hw_mode(p_hwfn);
1658                 if (rc != ECORE_SUCCESS)
1659                         return rc;
1660
1661                 /* @@@TBD need to add here:
1662                  * Check for fan failure
1663                  * Prev_unload
1664                  */
1665                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1666                 if (rc) {
1667                         DP_NOTICE(p_hwfn, true,
1668                                   "Failed sending LOAD_REQ command\n");
1669                         return rc;
1670                 }
1671
1672                 /* CQ75580:
1673                  * When coming back from hiberbate state, the registers from
1674                  * which shadow is read initially are not initialized. It turns
1675                  * out that these registers get initialized during the call to
1676                  * ecore_mcp_load_req request. So we need to reread them here
1677                  * to get the proper shadow register value.
1678                  * Note: This is a workaround for the missinginig MFW
1679                  * initialization. It may be removed once the implementation
1680                  * is done.
1681                  */
1682                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1683
1684                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1685                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1686                            rc, load_code);
1687
1688                 /* Only relevant for recovery:
1689                  * Clear the indication after the LOAD_REQ command is responded
1690                  * by the MFW.
1691                  */
1692                 p_dev->recov_in_prog = false;
1693
1694                 p_hwfn->first_on_engine = (load_code ==
1695                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1696
1697                 if (!qm_lock_init) {
1698                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1699                         qm_lock_init = true;
1700                 }
1701
1702                 switch (load_code) {
1703                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1704                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1705                                                   p_hwfn->hw_info.hw_mode);
1706                         if (rc)
1707                                 break;
1708                         /* Fall into */
1709                 case FW_MSG_CODE_DRV_LOAD_PORT:
1710                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1711                                                 p_hwfn->hw_info.hw_mode);
1712                         if (rc)
1713                                 break;
1714
1715 #ifndef REAL_ASIC_ONLY
1716                         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
1717                                 struct init_nig_pri_tc_map_req tc_map;
1718
1719                                 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map));
1720
1721                                 /* remove this once flow control is
1722                                  * implemented
1723                                  */
1724                                 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) {
1725                                         tc_map.pri[j].tc_id = 0;
1726                                         tc_map.pri[j].valid = 1;
1727                                 }
1728                                 ecore_init_nig_pri_tc_map(p_hwfn,
1729                                                           p_hwfn->p_main_ptt,
1730                                                           &tc_map);
1731                         }
1732 #endif
1733                         /* Fall into */
1734                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1735                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1736                                               p_params->p_tunn,
1737                                               p_hwfn->hw_info.hw_mode,
1738                                               p_params->b_hw_start,
1739                                               p_params->int_mode,
1740                                               p_params->allow_npar_tx_switch);
1741                         break;
1742                 default:
1743                         rc = ECORE_NOTIMPL;
1744                         break;
1745                 }
1746
1747                 if (rc != ECORE_SUCCESS)
1748                         DP_NOTICE(p_hwfn, true,
1749                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1750                                   load_code, rc);
1751
1752                 /* ACK mfw regardless of success or failure of initialization */
1753                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1754                                        DRV_MSG_CODE_LOAD_DONE,
1755                                        0, &load_code, &param);
1756                 if (rc != ECORE_SUCCESS)
1757                         return rc;
1758                 if (mfw_rc != ECORE_SUCCESS) {
1759                         DP_NOTICE(p_hwfn, true,
1760                                   "Failed sending LOAD_DONE command\n");
1761                         return mfw_rc;
1762                 }
1763
1764                 ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt);
1765                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
1766                                            p_params->epoch);
1767
1768                 /* send DCBX attention request command */
1769                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1770                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1771                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1772                                        DRV_MSG_CODE_SET_DCBX,
1773                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1774                                        &load_code, &param);
1775                 if (mfw_rc != ECORE_SUCCESS) {
1776                         DP_NOTICE(p_hwfn, true,
1777                                   "Failed to send DCBX attention request\n");
1778                         return mfw_rc;
1779                 }
1780
1781                 p_hwfn->hw_init_done = true;
1782         }
1783
1784         return ECORE_SUCCESS;
1785 }
1786
1787 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1788 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1789                                  struct ecore_hwfn *p_hwfn,
1790                                  struct ecore_ptt *p_ptt)
1791 {
1792         int i;
1793
1794         /* close timers */
1795         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1796         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1797         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1798                                                                         i++) {
1799                 if ((!ecore_rd(p_hwfn, p_ptt,
1800                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1801                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1802                         break;
1803
1804                 /* Dependent on number of connection/tasks, possibly
1805                  * 1ms sleep is required between polls
1806                  */
1807                 OSAL_MSLEEP(1);
1808         }
1809         if (i == ECORE_HW_STOP_RETRY_LIMIT)
1810                 DP_NOTICE(p_hwfn, true,
1811                           "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1812                           (u8)ecore_rd(p_hwfn, p_ptt,
1813                                         TM_REG_PF_SCAN_ACTIVE_CONN),
1814                           (u8)ecore_rd(p_hwfn, p_ptt,
1815                                         TM_REG_PF_SCAN_ACTIVE_TASK));
1816 }
1817
1818 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1819 {
1820         int j;
1821
1822         for_each_hwfn(p_dev, j) {
1823                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1824                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1825
1826                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1827         }
1828 }
1829
1830 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1831 {
1832         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1833         int j;
1834
1835         for_each_hwfn(p_dev, j) {
1836                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1837                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1838
1839                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1840
1841                 if (IS_VF(p_dev)) {
1842                         ecore_vf_pf_int_cleanup(p_hwfn);
1843                         continue;
1844                 }
1845
1846                 /* mark the hw as uninitialized... */
1847                 p_hwfn->hw_init_done = false;
1848
1849                 rc = ecore_sp_pf_stop(p_hwfn);
1850                 if (rc)
1851                         DP_NOTICE(p_hwfn, true,
1852                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1853
1854                 /* perform debug action after PF stop was sent */
1855                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1856
1857                 /* close NIG to BRB gate */
1858                 ecore_wr(p_hwfn, p_ptt,
1859                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1860
1861                 /* close parser */
1862                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1863                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1864                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1865                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1866                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1867
1868                 /* @@@TBD - clean transmission queues (5.b) */
1869                 /* @@@TBD - clean BTB (5.c) */
1870
1871                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1872
1873                 /* @@@TBD - verify DMAE requests are done (8) */
1874
1875                 /* Disable Attention Generation */
1876                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1877                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1878                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1879                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1880                 /* Need to wait 1ms to guarantee SBs are cleared */
1881                 OSAL_MSLEEP(1);
1882         }
1883
1884         if (IS_PF(p_dev)) {
1885                 /* Disable DMAE in PXP - in CMT, this should only be done for
1886                  * first hw-function, and only after all transactions have
1887                  * stopped for all active hw-functions.
1888                  */
1889                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1890                                              p_dev->hwfns[0].p_main_ptt, false);
1891                 if (t_rc != ECORE_SUCCESS)
1892                         rc = t_rc;
1893         }
1894
1895         return rc;
1896 }
1897
1898 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1899 {
1900         int j;
1901
1902         for_each_hwfn(p_dev, j) {
1903                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1904                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1905
1906                 if (IS_VF(p_dev)) {
1907                         ecore_vf_pf_int_cleanup(p_hwfn);
1908                         continue;
1909                 }
1910
1911                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1912                            "Shutting down the fastpath\n");
1913
1914                 ecore_wr(p_hwfn, p_ptt,
1915                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1916
1917                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1918                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1919                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1920                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1921                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1922
1923                 /* @@@TBD - clean transmission queues (5.b) */
1924                 /* @@@TBD - clean BTB (5.c) */
1925
1926                 /* @@@TBD - verify DMAE requests are done (8) */
1927
1928                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1929                 /* Need to wait 1ms to guarantee SBs are cleared */
1930                 OSAL_MSLEEP(1);
1931         }
1932 }
1933
1934 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1935 {
1936         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1937
1938         if (IS_VF(p_hwfn->p_dev))
1939                 return;
1940
1941         /* If roce info is allocated it means roce is initialized and should
1942          * be enabled in searcher.
1943          */
1944         if (p_hwfn->p_rdma_info) {
1945                 if (p_hwfn->b_rdma_enabled_in_prs)
1946                         ecore_wr(p_hwfn, p_ptt,
1947                                  p_hwfn->rdma_prs_search_reg, 0x1);
1948                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1949         }
1950
1951         /* Re-open incoming traffic */
1952         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1953                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1954 }
1955
1956 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1957                                              struct ecore_ptt *p_ptt, u32 reg,
1958                                              bool expected)
1959 {
1960         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1961
1962         if (assert_val != expected) {
1963                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1964                           reg, expected);
1965                 return ECORE_UNKNOWN_ERROR;
1966         }
1967
1968         return 0;
1969 }
1970
1971 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1972 {
1973         enum _ecore_status_t rc = ECORE_SUCCESS;
1974         u32 unload_resp, unload_param;
1975         int i;
1976
1977         for_each_hwfn(p_dev, i) {
1978                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1979
1980                 if (IS_VF(p_dev)) {
1981                         rc = ecore_vf_pf_reset(p_hwfn);
1982                         if (rc)
1983                                 return rc;
1984                         continue;
1985                 }
1986
1987                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1988
1989                 /* Check for incorrect states */
1990                 if (!p_dev->recov_in_prog) {
1991                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1992                                          QM_REG_USG_CNT_PF_TX, 0);
1993                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1994                                          QM_REG_USG_CNT_PF_OTHER, 0);
1995                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1996                 }
1997
1998                 /* Disable PF in HW blocks */
1999                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2000                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2001
2002                 if (p_dev->recov_in_prog) {
2003                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2004                                    "Recovery is in progress -> skip sending unload_req/done\n");
2005                         break;
2006                 }
2007
2008                 /* Send unload command to MCP */
2009                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2010                                    DRV_MSG_CODE_UNLOAD_REQ,
2011                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
2012                                    &unload_resp, &unload_param);
2013                 if (rc != ECORE_SUCCESS) {
2014                         DP_NOTICE(p_hwfn, true,
2015                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
2016                         /* @@TBD - what to do? for now, assume ENG. */
2017                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2018                 }
2019
2020                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2021                                    DRV_MSG_CODE_UNLOAD_DONE,
2022                                    0, &unload_resp, &unload_param);
2023                 if (rc != ECORE_SUCCESS) {
2024                         DP_NOTICE(p_hwfn,
2025                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2026                         /* @@@TBD - Should it really ASSERT here ? */
2027                         return rc;
2028                 }
2029         }
2030
2031         return rc;
2032 }
2033
2034 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2035 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2036 {
2037         ecore_ptt_pool_free(p_hwfn);
2038         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2039 }
2040
2041 /* Setup bar access */
2042 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2043 {
2044         /* clear indirect access */
2045         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2046                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2047                          PGLUE_B_REG_PGL_ADDR_E8_F0, 0);
2048                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2049                          PGLUE_B_REG_PGL_ADDR_EC_F0, 0);
2050                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2051                          PGLUE_B_REG_PGL_ADDR_F0_F0, 0);
2052                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2053                          PGLUE_B_REG_PGL_ADDR_F4_F0, 0);
2054         } else {
2055                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2056                          PGLUE_B_REG_PGL_ADDR_88_F0, 0);
2057                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2058                          PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
2059                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2060                          PGLUE_B_REG_PGL_ADDR_90_F0, 0);
2061                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2062                          PGLUE_B_REG_PGL_ADDR_94_F0, 0);
2063         }
2064
2065         /* Clean Previous errors if such exist */
2066         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2067                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2068
2069         /* enable internal target-read */
2070         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2071                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2072 }
2073
2074 static void get_function_id(struct ecore_hwfn *p_hwfn)
2075 {
2076         /* ME Register */
2077         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2078                                                   PXP_PF_ME_OPAQUE_ADDR);
2079
2080         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2081
2082         /* Bits 16-19 from the ME registers are the pf_num */
2083         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2084         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2085                                       PXP_CONCRETE_FID_PFID);
2086         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2087                                     PXP_CONCRETE_FID_PORT);
2088
2089         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2090                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2091                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2092 }
2093
2094 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2095 {
2096         u32 *feat_num = p_hwfn->hw_info.feat_num;
2097         int num_features = 1;
2098
2099         /* L2 Queues require each: 1 status block. 1 L2 queue */
2100         feat_num[ECORE_PF_L2_QUE] =
2101             OSAL_MIN_T(u32,
2102                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2103                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2104
2105         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2106                    "#PF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2107                    feat_num[ECORE_PF_L2_QUE],
2108                    feat_num[ECORE_RDMA_CNQ],
2109                    RESC_NUM(p_hwfn, ECORE_SB), num_features);
2110 }
2111
2112 static enum resource_id_enum
2113 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2114 {
2115         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2116
2117         switch (res_id) {
2118         case ECORE_SB:
2119                 mfw_res_id = RESOURCE_NUM_SB_E;
2120                 break;
2121         case ECORE_L2_QUEUE:
2122                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2123                 break;
2124         case ECORE_VPORT:
2125                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2126                 break;
2127         case ECORE_RSS_ENG:
2128                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2129                 break;
2130         case ECORE_PQ:
2131                 mfw_res_id = RESOURCE_NUM_PQ_E;
2132                 break;
2133         case ECORE_RL:
2134                 mfw_res_id = RESOURCE_NUM_RL_E;
2135                 break;
2136         case ECORE_MAC:
2137         case ECORE_VLAN:
2138                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2139                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2140                 break;
2141         case ECORE_ILT:
2142                 mfw_res_id = RESOURCE_ILT_E;
2143                 break;
2144         case ECORE_LL2_QUEUE:
2145                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2146                 break;
2147         case ECORE_RDMA_CNQ_RAM:
2148         case ECORE_CMDQS_CQS:
2149                 /* CNQ/CMDQS are the same resource */
2150                 mfw_res_id = RESOURCE_CQS_E;
2151                 break;
2152         case ECORE_RDMA_STATS_QUEUE:
2153                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2154                 break;
2155         default:
2156                 break;
2157         }
2158
2159         return mfw_res_id;
2160 }
2161
2162 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2163                                       enum ecore_resources res_id)
2164 {
2165         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2166         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2167         struct ecore_sb_cnt_info sb_cnt_info;
2168         u32 dflt_resc_num = 0;
2169
2170         switch (res_id) {
2171         case ECORE_SB:
2172                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2173                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2174                 dflt_resc_num = sb_cnt_info.sb_cnt;
2175                 break;
2176         case ECORE_L2_QUEUE:
2177                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2178                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2179                 break;
2180         case ECORE_VPORT:
2181                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2182                                  MAX_NUM_VPORTS_BB) / num_funcs;
2183                 break;
2184         case ECORE_RSS_ENG:
2185                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2186                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2187                 break;
2188         case ECORE_PQ:
2189                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2190                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2191                 break;
2192         case ECORE_RL:
2193                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2194                 break;
2195         case ECORE_MAC:
2196         case ECORE_VLAN:
2197                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2198                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2199                 break;
2200         case ECORE_ILT:
2201                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2202                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2203                 break;
2204         case ECORE_LL2_QUEUE:
2205                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2206                 break;
2207         case ECORE_RDMA_CNQ_RAM:
2208         case ECORE_CMDQS_CQS:
2209                 /* CNQ/CMDQS are the same resource */
2210                 /* @DPDK */
2211                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2212                 break;
2213         case ECORE_RDMA_STATS_QUEUE:
2214                 /* @DPDK */
2215                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2216                                  MAX_NUM_VPORTS_BB) / num_funcs;
2217                 break;
2218         default:
2219                 break;
2220         }
2221
2222         return dflt_resc_num;
2223 }
2224
2225 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2226 {
2227         switch (res_id) {
2228         case ECORE_SB:
2229                 return "SB";
2230         case ECORE_L2_QUEUE:
2231                 return "L2_QUEUE";
2232         case ECORE_VPORT:
2233                 return "VPORT";
2234         case ECORE_RSS_ENG:
2235                 return "RSS_ENG";
2236         case ECORE_PQ:
2237                 return "PQ";
2238         case ECORE_RL:
2239                 return "RL";
2240         case ECORE_MAC:
2241                 return "MAC";
2242         case ECORE_VLAN:
2243                 return "VLAN";
2244         case ECORE_RDMA_CNQ_RAM:
2245                 return "RDMA_CNQ_RAM";
2246         case ECORE_ILT:
2247                 return "ILT";
2248         case ECORE_LL2_QUEUE:
2249                 return "LL2_QUEUE";
2250         case ECORE_CMDQS_CQS:
2251                 return "CMDQS_CQS";
2252         case ECORE_RDMA_STATS_QUEUE:
2253                 return "RDMA_STATS_QUEUE";
2254         default:
2255                 return "UNKNOWN_RESOURCE";
2256         }
2257 }
2258
2259 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2260                                                    enum ecore_resources res_id,
2261                                                    bool drv_resc_alloc)
2262 {
2263         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2264         u32 *p_resc_num, *p_resc_start;
2265         struct resource_info resc_info;
2266         enum _ecore_status_t rc;
2267
2268         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2269         p_resc_start = &RESC_START(p_hwfn, res_id);
2270
2271         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2272         if (!dflt_resc_num) {
2273                 DP_ERR(p_hwfn,
2274                        "Failed to get default amount for resource %d [%s]\n",
2275                         res_id, ecore_hw_get_resc_name(res_id));
2276                 return ECORE_INVAL;
2277         }
2278         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2279
2280 #ifndef ASIC_ONLY
2281         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2282                 *p_resc_num = dflt_resc_num;
2283                 *p_resc_start = dflt_resc_start;
2284                 goto out;
2285         }
2286 #endif
2287
2288         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2289         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2290         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2291                 DP_ERR(p_hwfn,
2292                        "Failed to match resource %d with MFW resources\n",
2293                        res_id);
2294                 return ECORE_INVAL;
2295         }
2296
2297         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2298                                      &mcp_resp, &mcp_param);
2299         if (rc != ECORE_SUCCESS) {
2300                 DP_NOTICE(p_hwfn, true,
2301                           "MFW response failure for an allocation request for"
2302                           " resource %d [%s]\n",
2303                           res_id, ecore_hw_get_resc_name(res_id));
2304                 return rc;
2305         }
2306
2307         /* Default driver values are applied in the following cases:
2308          * - The resource allocation MB command is not supported by the MFW
2309          * - There is an internal error in the MFW while processing the request
2310          * - The resource ID is unknown to the MFW
2311          */
2312         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2313             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2314                 /* @DPDK */
2315                 DP_INFO(p_hwfn,
2316                         "Resource %d [%s]: No allocation info was received"
2317                         " [mcp_resp 0x%x]. Applying default values"
2318                         " [num %d, start %d].\n",
2319                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2320                         dflt_resc_num, dflt_resc_start);
2321
2322                 *p_resc_num = dflt_resc_num;
2323                 *p_resc_start = dflt_resc_start;
2324                 goto out;
2325         }
2326
2327         /* TBD - remove this when revising the handling of the SB resource */
2328         if (res_id == ECORE_SB) {
2329                 /* Excluding the slowpath SB */
2330                 resc_info.size -= 1;
2331                 resc_info.offset -= p_hwfn->enabled_func_idx;
2332         }
2333
2334         *p_resc_num = resc_info.size;
2335         *p_resc_start = resc_info.offset;
2336
2337         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2338                 DP_NOTICE(p_hwfn, false,
2339                           "Resource %d [%s]: MFW allocation [num %d, start %d]"
2340                           " differs from default values [num %d, start %d]%s\n",
2341                           res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2342                           *p_resc_start, dflt_resc_num, dflt_resc_start,
2343                           drv_resc_alloc ? " - Applying default values" : "");
2344                 if (drv_resc_alloc) {
2345                         *p_resc_num = dflt_resc_num;
2346                         *p_resc_start = dflt_resc_start;
2347                 }
2348         }
2349  out:
2350         return ECORE_SUCCESS;
2351 }
2352
2353 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2354                                               bool drv_resc_alloc)
2355 {
2356         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2357         enum _ecore_status_t rc;
2358         u8 res_id;
2359 #ifndef ASIC_ONLY
2360         u32 *resc_start = p_hwfn->hw_info.resc_start;
2361         u32 *resc_num = p_hwfn->hw_info.resc_num;
2362         /* For AH, an equal share of the ILT lines between the maximal number of
2363          * PFs is not enough for RoCE. This would be solved by the future
2364          * resource allocation scheme, but isn't currently present for
2365          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2366          * to work - the BB number of ILT lines divided by its max PFs number.
2367          */
2368         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2369 #endif
2370
2371         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2372                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2373                 if (rc != ECORE_SUCCESS)
2374                         return rc;
2375         }
2376
2377 #ifndef ASIC_ONLY
2378         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2379                 /* Reduced build contains less PQs */
2380                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2381                         resc_num[ECORE_PQ] = 32;
2382                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2383                             p_hwfn->enabled_func_idx;
2384                 }
2385
2386                 /* For AH emulation, since we have a possible maximal number of
2387                  * 16 enabled PFs, in case there are not enough ILT lines -
2388                  * allocate only first PF as RoCE and have all the other ETH
2389                  * only with less ILT lines.
2390                  */
2391                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2392                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2393                                                          resc_num[ECORE_ILT],
2394                                                          roce_min_ilt_lines);
2395         }
2396
2397         /* Correct the common ILT calculation if PF0 has more */
2398         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2399             p_hwfn->p_dev->b_is_emul_full &&
2400             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2401                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2402                     resc_num[ECORE_ILT];
2403 #endif
2404
2405         /* Sanity for ILT */
2406         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2407             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2408                 DP_NOTICE(p_hwfn, true,
2409                           "Can't assign ILT pages [%08x,...,%08x]\n",
2410                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2411                                                                   ECORE_ILT) -
2412                           1);
2413                 return ECORE_INVAL;
2414         }
2415
2416         ecore_hw_set_feat(p_hwfn);
2417
2418         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2419                    "The numbers for each resource are:\n");
2420         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2421                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2422                            ecore_hw_get_resc_name(res_id),
2423                            RESC_NUM(p_hwfn, res_id),
2424                            RESC_START(p_hwfn, res_id));
2425
2426         return ECORE_SUCCESS;
2427 }
2428
2429 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2430                                                   struct ecore_ptt *p_ptt)
2431 {
2432         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2433         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2434         struct ecore_mcp_link_params *link;
2435
2436         /* Read global nvm_cfg address */
2437         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2438
2439         /* Verify MCP has initialized it */
2440         if (!nvm_cfg_addr) {
2441                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2442                 return ECORE_INVAL;
2443         }
2444
2445 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2446
2447         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2448
2449         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2450             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2451                                                        core_cfg);
2452
2453         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2454
2455         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2456                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2457         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2458                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2459                 break;
2460         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2461                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2462                 break;
2463         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2464                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2465                 break;
2466         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2467                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2468                 break;
2469         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2470                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2471                 break;
2472         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2473                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2474                 break;
2475         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2476                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2477                 break;
2478         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2479                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2480                 break;
2481         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2482                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2483                 break;
2484         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2485                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2486                 break;
2487         default:
2488                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2489                           core_cfg);
2490                 break;
2491         }
2492
2493         /* Read default link configuration */
2494         link = &p_hwfn->mcp_info->link_input;
2495         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2496             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2497         link_temp = ecore_rd(p_hwfn, p_ptt,
2498                              port_cfg_addr +
2499                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2500         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2501         link->speed.advertised_speeds = link_temp;
2502
2503         link_temp = link->speed.advertised_speeds;
2504         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2505
2506         link_temp = ecore_rd(p_hwfn, p_ptt,
2507                              port_cfg_addr +
2508                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2509         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2510                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2511         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2512                 link->speed.autoneg = true;
2513                 break;
2514         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2515                 link->speed.forced_speed = 1000;
2516                 break;
2517         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2518                 link->speed.forced_speed = 10000;
2519                 break;
2520         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2521                 link->speed.forced_speed = 25000;
2522                 break;
2523         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2524                 link->speed.forced_speed = 40000;
2525                 break;
2526         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2527                 link->speed.forced_speed = 50000;
2528                 break;
2529         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2530                 link->speed.forced_speed = 100000;
2531                 break;
2532         default:
2533                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2534         }
2535
2536         p_hwfn->mcp_info->link_capabilities.default_speed =
2537             link->speed.forced_speed;
2538         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2539             link->speed.autoneg;
2540
2541         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2542         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2543         link->pause.autoneg = !!(link_temp &
2544                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2545         link->pause.forced_rx = !!(link_temp &
2546                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2547         link->pause.forced_tx = !!(link_temp &
2548                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2549         link->loopback_mode = 0;
2550
2551         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2552                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2553                    link->speed.forced_speed, link->speed.advertised_speeds,
2554                    link->speed.autoneg, link->pause.autoneg);
2555
2556         /* Read Multi-function information from shmem */
2557         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2558             OFFSETOF(struct nvm_cfg1, glob) +
2559             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2560
2561         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2562
2563         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2564             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2565
2566         switch (mf_mode) {
2567         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2568                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2569                 break;
2570         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2571                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2572                 break;
2573         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2574                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2575                 break;
2576         }
2577         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2578                 p_hwfn->p_dev->mf_mode);
2579
2580         /* Read Multi-function information from shmem */
2581         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2582             OFFSETOF(struct nvm_cfg1, glob) +
2583             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2584
2585         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2586         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2587                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2588                              &p_hwfn->hw_info.device_capabilities);
2589         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2590                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2591                              &p_hwfn->hw_info.device_capabilities);
2592         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2593                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2594                              &p_hwfn->hw_info.device_capabilities);
2595         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2596                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2597                              &p_hwfn->hw_info.device_capabilities);
2598         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2599                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2600                              &p_hwfn->hw_info.device_capabilities);
2601
2602         return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2603 }
2604
2605 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2606                                 struct ecore_ptt *p_ptt)
2607 {
2608         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2609         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2610         struct ecore_dev *p_dev = p_hwfn->p_dev;
2611
2612         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2613
2614         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2615          * in the other bits are selected.
2616          * Bits 1-15 are for functions 1-15, respectively, and their value is
2617          * '0' only for enabled functions (function 0 always exists and
2618          * enabled).
2619          * In case of CMT in BB, only the "even" functions are enabled, and thus
2620          * the number of functions for both hwfns is learnt from the same bits.
2621          */
2622         reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2623
2624         if (reg_function_hide & 0x1) {
2625                 if (ECORE_IS_BB(p_dev)) {
2626                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2627                                 num_funcs = 0;
2628                                 eng_mask = 0xaaaa;
2629                         } else {
2630                                 num_funcs = 1;
2631                                 eng_mask = 0x5554;
2632                         }
2633                 } else {
2634                         num_funcs = 1;
2635                         eng_mask = 0xfffe;
2636                 }
2637
2638                 /* Get the number of the enabled functions on the engine */
2639                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2640                 while (tmp) {
2641                         if (tmp & 0x1)
2642                                 num_funcs++;
2643                         tmp >>= 0x1;
2644                 }
2645
2646                 /* Get the PF index within the enabled functions */
2647                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2648                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2649                 while (tmp) {
2650                         if (tmp & 0x1)
2651                                 enabled_func_idx--;
2652                         tmp >>= 0x1;
2653                 }
2654         }
2655
2656         p_hwfn->num_funcs_on_engine = num_funcs;
2657         p_hwfn->enabled_func_idx = enabled_func_idx;
2658
2659 #ifndef ASIC_ONLY
2660         if (CHIP_REV_IS_FPGA(p_dev)) {
2661                 DP_NOTICE(p_hwfn, false,
2662                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2663                 p_hwfn->num_funcs_on_engine = 4;
2664         }
2665 #endif
2666
2667         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2668                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2669                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2670                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2671 }
2672
2673 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2674                                       struct ecore_ptt *p_ptt)
2675 {
2676         u32 port_mode;
2677
2678 #ifndef ASIC_ONLY
2679         /* Read the port mode */
2680         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2681                 port_mode = 4;
2682         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2683                  (p_hwfn->p_dev->num_hwfns > 1))
2684                 /* In CMT on emulation, assume 1 port */
2685                 port_mode = 1;
2686         else
2687 #endif
2688                 port_mode = ecore_rd(p_hwfn, p_ptt,
2689                                      CNIG_REG_NW_PORT_MODE_BB_B0);
2690
2691         if (port_mode < 3) {
2692                 p_hwfn->p_dev->num_ports_in_engines = 1;
2693         } else if (port_mode <= 5) {
2694                 p_hwfn->p_dev->num_ports_in_engines = 2;
2695         } else {
2696                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2697                           p_hwfn->p_dev->num_ports_in_engines);
2698
2699                 /* Default num_ports_in_engines to something */
2700                 p_hwfn->p_dev->num_ports_in_engines = 1;
2701         }
2702 }
2703
2704 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2705                                       struct ecore_ptt *p_ptt)
2706 {
2707         u32 port;
2708         int i;
2709
2710         p_hwfn->p_dev->num_ports_in_engines = 0;
2711
2712 #ifndef ASIC_ONLY
2713         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2714                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2715                 switch ((port & 0xf000) >> 12) {
2716                 case 1:
2717                         p_hwfn->p_dev->num_ports_in_engines = 1;
2718                         break;
2719                 case 3:
2720                         p_hwfn->p_dev->num_ports_in_engines = 2;
2721                         break;
2722                 case 0xf:
2723                         p_hwfn->p_dev->num_ports_in_engines = 4;
2724                         break;
2725                 default:
2726                         DP_NOTICE(p_hwfn, false,
2727                                   "Unknown port mode in ECO_RESERVED %08x\n",
2728                                   port);
2729                 }
2730         } else
2731 #endif
2732                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2733                         port = ecore_rd(p_hwfn, p_ptt,
2734                                         CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2735                         if (port & 1)
2736                                 p_hwfn->p_dev->num_ports_in_engines++;
2737                 }
2738 }
2739
2740 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2741                                    struct ecore_ptt *p_ptt)
2742 {
2743         if (ECORE_IS_BB(p_hwfn->p_dev))
2744                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2745         else
2746                 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2747 }
2748
2749 static enum _ecore_status_t
2750 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2751                   enum ecore_pci_personality personality, bool drv_resc_alloc)
2752 {
2753         enum _ecore_status_t rc;
2754
2755         /* Since all information is common, only first hwfns should do this */
2756         if (IS_LEAD_HWFN(p_hwfn)) {
2757                 rc = ecore_iov_hw_info(p_hwfn);
2758                 if (rc)
2759                         return rc;
2760         }
2761
2762         /* TODO In get_hw_info, amoungst others:
2763          * Get MCP FW revision and determine according to it the supported
2764          * featrues (e.g. DCB)
2765          * Get boot mode
2766          * ecore_get_pcie_width_speed, WOL capability.
2767          * Number of global CQ-s (for storage
2768          */
2769         ecore_hw_info_port_num(p_hwfn, p_ptt);
2770
2771 #ifndef ASIC_ONLY
2772         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2773 #endif
2774                 ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2775
2776         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2777         if (rc)
2778                 return rc;
2779
2780 #ifndef ASIC_ONLY
2781         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2782 #endif
2783                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2784                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2785 #ifndef ASIC_ONLY
2786         } else {
2787                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2788
2789                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2790                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2791         }
2792 #endif
2793
2794         if (ecore_mcp_is_init(p_hwfn)) {
2795                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2796                         p_hwfn->hw_info.ovlan =
2797                             p_hwfn->mcp_info->func_info.ovlan;
2798
2799                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2800         }
2801
2802         if (personality != ECORE_PCI_DEFAULT)
2803                 p_hwfn->hw_info.personality = personality;
2804         else if (ecore_mcp_is_init(p_hwfn))
2805                 p_hwfn->hw_info.personality =
2806                     p_hwfn->mcp_info->func_info.protocol;
2807
2808 #ifndef ASIC_ONLY
2809         /* To overcome ILT lack for emulation, until at least until we'll have
2810          * a definite answer from system about it, allow only PF0 to be RoCE.
2811          */
2812         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2813                 if (!p_hwfn->rel_pf_id)
2814                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2815                 else
2816                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2817         }
2818 #endif
2819
2820         /* although in BB some constellations may support more than 4 tcs,
2821          * that can result in performance penalty in some cases. 4
2822          * represents a good tradeoff between performance and flexibility.
2823          */
2824         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2825
2826         /* start out with a single active tc. This can be increased either
2827          * by dcbx negotiation or by upper layer driver
2828          */
2829         p_hwfn->hw_info.num_active_tc = 1;
2830
2831         ecore_get_num_funcs(p_hwfn, p_ptt);
2832
2833         /* In case of forcing the driver's default resource allocation, calling
2834          * ecore_hw_get_resc() should come after initializing the personality
2835          * and after getting the number of functions, since the calculation of
2836          * the resources/features depends on them.
2837          * This order is not harmful if not forcing.
2838          */
2839         return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2840 }
2841
2842 #define ECORE_DEV_ID_MASK       0xff00
2843 #define ECORE_DEV_ID_MASK_BB    0x1600
2844 #define ECORE_DEV_ID_MASK_AH    0x8000
2845
2846 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2847 {
2848         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2849         u32 tmp;
2850
2851         /* Read Vendor Id / Device Id */
2852         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2853                                   &p_dev->vendor_id);
2854         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2855                                   &p_dev->device_id);
2856
2857         /* Determine type */
2858         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2859                 p_dev->type = ECORE_DEV_TYPE_AH;
2860         else
2861                 p_dev->type = ECORE_DEV_TYPE_BB;
2862
2863         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2864                                          MISCS_REG_CHIP_NUM);
2865         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2866                                          MISCS_REG_CHIP_REV);
2867
2868         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2869
2870         /* Learn number of HW-functions */
2871         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2872                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2873
2874         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2875                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2876                 p_dev->num_hwfns = 2;
2877         } else {
2878                 p_dev->num_hwfns = 1;
2879         }
2880
2881 #ifndef ASIC_ONLY
2882         if (CHIP_REV_IS_EMUL(p_dev)) {
2883                 /* For some reason we have problems with this register
2884                  * in B0 emulation; Simply assume no CMT
2885                  */
2886                 DP_NOTICE(p_dev->hwfns, false,
2887                           "device on emul - assume no CMT\n");
2888                 p_dev->num_hwfns = 1;
2889         }
2890 #endif
2891
2892         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2893                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2894         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2895         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2896                                            MISCS_REG_CHIP_METAL);
2897         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2898         DP_INFO(p_dev->hwfns,
2899                 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2900                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2901                 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2902                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2903                 p_dev->chip_metal);
2904
2905         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2906                 DP_NOTICE(p_dev->hwfns, false,
2907                           "The chip type/rev (BB A0) is not supported!\n");
2908                 return ECORE_ABORTED;
2909         }
2910 #ifndef ASIC_ONLY
2911         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2912                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2913                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2914
2915         if (CHIP_REV_IS_EMUL(p_dev)) {
2916                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2917                                MISCS_REG_ECO_RESERVED);
2918                 if (tmp & (1 << 29)) {
2919                         DP_NOTICE(p_hwfn, false,
2920                                   "Emulation: Running on a FULL build\n");
2921                         p_dev->b_is_emul_full = true;
2922                 } else {
2923                         DP_NOTICE(p_hwfn, false,
2924                                   "Emulation: Running on a REDUCED build\n");
2925                 }
2926         }
2927 #endif
2928
2929         return ECORE_SUCCESS;
2930 }
2931
2932 #ifndef LINUX_REMOVE
2933 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2934 {
2935         int j;
2936
2937         if (IS_VF(p_dev))
2938                 return;
2939
2940         for_each_hwfn(p_dev, j) {
2941                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2942
2943                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2944                            "Mark hw/fw uninitialized\n");
2945
2946                 p_hwfn->hw_init_done = false;
2947                 p_hwfn->first_on_engine = false;
2948
2949                 ecore_ptt_invalidate(p_hwfn);
2950         }
2951 }
2952 #endif
2953
2954 static enum _ecore_status_t
2955 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
2956                         void OSAL_IOMEM *p_doorbells,
2957                         struct ecore_hw_prepare_params *p_params)
2958 {
2959         struct ecore_dev *p_dev = p_hwfn->p_dev;
2960         enum _ecore_status_t rc = ECORE_SUCCESS;
2961
2962         /* Split PCI bars evenly between hwfns */
2963         p_hwfn->regview = p_regview;
2964         p_hwfn->doorbells = p_doorbells;
2965
2966         if (IS_VF(p_dev))
2967                 return ecore_vf_hw_prepare(p_hwfn);
2968
2969         /* Validate that chip access is feasible */
2970         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2971                 DP_ERR(p_hwfn,
2972                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2973                 return ECORE_INVAL;
2974         }
2975
2976         get_function_id(p_hwfn);
2977
2978         /* Allocate PTT pool */
2979         rc = ecore_ptt_pool_alloc(p_hwfn);
2980         if (rc) {
2981                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2982                 goto err0;
2983         }
2984
2985         /* Allocate the main PTT */
2986         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2987
2988         /* First hwfn learns basic information, e.g., number of hwfns */
2989         if (!p_hwfn->my_id) {
2990                 rc = ecore_get_dev_info(p_dev);
2991                 if (rc != ECORE_SUCCESS)
2992                         goto err1;
2993         }
2994
2995         ecore_hw_hwfn_prepare(p_hwfn);
2996
2997         /* Initialize MCP structure */
2998         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2999         if (rc) {
3000                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3001                 goto err1;
3002         }
3003
3004         /* Read the device configuration information from the HW and SHMEM */
3005         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3006                                p_params->personality, p_params->drv_resc_alloc);
3007         if (rc) {
3008                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3009                 goto err2;
3010         }
3011
3012         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3013          * called, since among others it sets the ports number in an engine.
3014          */
3015         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3016             !p_dev->recov_in_prog) {
3017                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3018                 if (rc != ECORE_SUCCESS)
3019                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3020         }
3021
3022         /* Allocate the init RT array and initialize the init-ops engine */
3023         rc = ecore_init_alloc(p_hwfn);
3024         if (rc) {
3025                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3026                 goto err2;
3027         }
3028 #ifndef ASIC_ONLY
3029         if (CHIP_REV_IS_FPGA(p_dev)) {
3030                 DP_NOTICE(p_hwfn, false,
3031                           "FPGA: workaround; Prevent DMAE parities\n");
3032                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
3033
3034                 DP_NOTICE(p_hwfn, false,
3035                           "FPGA: workaround: Set VF bar0 size\n");
3036                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3037                          PGLUE_B_REG_VF_BAR0_SIZE, 4);
3038         }
3039 #endif
3040
3041         return rc;
3042  err2:
3043         if (IS_LEAD_HWFN(p_hwfn))
3044                 ecore_iov_free_hw_info(p_dev);
3045         ecore_mcp_free(p_hwfn);
3046  err1:
3047         ecore_hw_hwfn_free(p_hwfn);
3048  err0:
3049         return rc;
3050 }
3051
3052 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3053                                       struct ecore_hw_prepare_params *p_params)
3054 {
3055         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3056         enum _ecore_status_t rc;
3057
3058         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3059
3060         /* Store the precompiled init data ptrs */
3061         if (IS_PF(p_dev))
3062                 ecore_init_iro_array(p_dev);
3063
3064         /* Initialize the first hwfn - will learn number of hwfns */
3065         rc = ecore_hw_prepare_single(p_hwfn,
3066                                      p_dev->regview,
3067                                      p_dev->doorbells, p_params);
3068         if (rc != ECORE_SUCCESS)
3069                 return rc;
3070
3071         p_params->personality = p_hwfn->hw_info.personality;
3072
3073         /* initilalize 2nd hwfn if necessary */
3074         if (p_dev->num_hwfns > 1) {
3075                 void OSAL_IOMEM *p_regview, *p_doorbell;
3076                 u8 OSAL_IOMEM *addr;
3077
3078                 /* adjust bar offset for second engine */
3079                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3080                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3081                 p_regview = (void OSAL_IOMEM *)addr;
3082
3083                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3084                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3085                 p_doorbell = (void OSAL_IOMEM *)addr;
3086
3087                 /* prepare second hw function */
3088                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3089                                              p_doorbell, p_params);
3090
3091                 /* in case of error, need to free the previously
3092                  * initiliazed hwfn 0.
3093                  */
3094                 if (rc != ECORE_SUCCESS) {
3095                         if (IS_PF(p_dev)) {
3096                                 ecore_init_free(p_hwfn);
3097                                 ecore_mcp_free(p_hwfn);
3098                                 ecore_hw_hwfn_free(p_hwfn);
3099                         } else {
3100                                 DP_NOTICE(p_dev, true,
3101                                           "What do we need to free when VF hwfn1 init fails\n");
3102                         }
3103                         return rc;
3104                 }
3105         }
3106
3107         return ECORE_SUCCESS;
3108 }
3109
3110 void ecore_hw_remove(struct ecore_dev *p_dev)
3111 {
3112         int i;
3113
3114         for_each_hwfn(p_dev, i) {
3115                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3116
3117                 if (IS_VF(p_dev)) {
3118                         ecore_vf_pf_release(p_hwfn);
3119                         continue;
3120                 }
3121
3122                 ecore_init_free(p_hwfn);
3123                 ecore_hw_hwfn_free(p_hwfn);
3124                 ecore_mcp_free(p_hwfn);
3125
3126                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3127         }
3128
3129         ecore_iov_free_hw_info(p_dev);
3130 }
3131
3132 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3133                                       struct ecore_chain *p_chain)
3134 {
3135         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3136         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3137         struct ecore_chain_next *p_next;
3138         u32 size, i;
3139
3140         if (!p_virt)
3141                 return;
3142
3143         size = p_chain->elem_size * p_chain->usable_per_page;
3144
3145         for (i = 0; i < p_chain->page_cnt; i++) {
3146                 if (!p_virt)
3147                         break;
3148
3149                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3150                 p_virt_next = p_next->next_virt;
3151                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3152
3153                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3154                                        ECORE_CHAIN_PAGE_SIZE);
3155
3156                 p_virt = p_virt_next;
3157                 p_phys = p_phys_next;
3158         }
3159 }
3160
3161 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3162                                     struct ecore_chain *p_chain)
3163 {
3164         if (!p_chain->p_virt_addr)
3165                 return;
3166
3167         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3168                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3169 }
3170
3171 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3172                                  struct ecore_chain *p_chain)
3173 {
3174         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3175         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3176         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3177
3178         if (!pp_virt_addr_tbl)
3179                 return;
3180
3181         if (!p_chain->pbl.p_virt_table)
3182                 goto out;
3183
3184         for (i = 0; i < page_cnt; i++) {
3185                 if (!pp_virt_addr_tbl[i])
3186                         break;
3187
3188                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3189                                        *(dma_addr_t *)p_pbl_virt,
3190                                        ECORE_CHAIN_PAGE_SIZE);
3191
3192                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3193         }
3194
3195         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3196         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3197                                p_chain->pbl.p_phys_table, pbl_size);
3198  out:
3199         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3200 }
3201
3202 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3203 {
3204         switch (p_chain->mode) {
3205         case ECORE_CHAIN_MODE_NEXT_PTR:
3206                 ecore_chain_free_next_ptr(p_dev, p_chain);
3207                 break;
3208         case ECORE_CHAIN_MODE_SINGLE:
3209                 ecore_chain_free_single(p_dev, p_chain);
3210                 break;
3211         case ECORE_CHAIN_MODE_PBL:
3212                 ecore_chain_free_pbl(p_dev, p_chain);
3213                 break;
3214         }
3215 }
3216
3217 static enum _ecore_status_t
3218 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3219                                enum ecore_chain_cnt_type cnt_type,
3220                                osal_size_t elem_size, u32 page_cnt)
3221 {
3222         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3223
3224         /* The actual chain size can be larger than the maximal possible value
3225          * after rounding up the requested elements number to pages, and after
3226          * taking into acount the unusuable elements (next-ptr elements).
3227          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3228          * size/capacity fields are of a u32 type.
3229          */
3230         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3231              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3232             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3233              chain_size > ECORE_U32_MAX)) {
3234                 DP_NOTICE(p_dev, true,
3235                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3236                           (unsigned long)chain_size);
3237                 return ECORE_INVAL;
3238         }
3239
3240         return ECORE_SUCCESS;
3241 }
3242
3243 static enum _ecore_status_t
3244 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3245 {
3246         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3247         dma_addr_t p_phys = 0;
3248         u32 i;
3249
3250         for (i = 0; i < p_chain->page_cnt; i++) {
3251                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3252                                                  ECORE_CHAIN_PAGE_SIZE);
3253                 if (!p_virt) {
3254                         DP_NOTICE(p_dev, true,
3255                                   "Failed to allocate chain memory\n");
3256                         return ECORE_NOMEM;
3257                 }
3258
3259                 if (i == 0) {
3260                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3261                         ecore_chain_reset(p_chain);
3262                 } else {
3263                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3264                                                        p_virt, p_phys);
3265                 }
3266
3267                 p_virt_prev = p_virt;
3268         }
3269         /* Last page's next element should point to the beginning of the
3270          * chain.
3271          */
3272         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3273                                        p_chain->p_virt_addr,
3274                                        p_chain->p_phys_addr);
3275
3276         return ECORE_SUCCESS;
3277 }
3278
3279 static enum _ecore_status_t
3280 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3281 {
3282         void *p_virt = OSAL_NULL;
3283         dma_addr_t p_phys = 0;
3284
3285         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3286         if (!p_virt) {
3287                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3288                 return ECORE_NOMEM;
3289         }
3290
3291         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3292         ecore_chain_reset(p_chain);
3293
3294         return ECORE_SUCCESS;
3295 }
3296
3297 static enum _ecore_status_t ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3298                                                   struct ecore_chain *p_chain)
3299 {
3300         void *p_virt = OSAL_NULL;
3301         u8 *p_pbl_virt = OSAL_NULL;
3302         void **pp_virt_addr_tbl = OSAL_NULL;
3303         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3304         u32 page_cnt = p_chain->page_cnt, size, i;
3305
3306         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3307         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3308         if (!pp_virt_addr_tbl) {
3309                 DP_NOTICE(p_dev, true,
3310                           "Failed to allocate memory for the chain virtual addresses table\n");
3311                 return ECORE_NOMEM;
3312         }
3313         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3314
3315         /* The allocation of the PBL table is done with its full size, since it
3316          * is expected to be successive.
3317          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3318          * failure, since pp_virt_addr_tbl was previously allocated, and it
3319          * should be saved to allow its freeing during the error flow.
3320          */
3321         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3322         p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3323         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3324                                  pp_virt_addr_tbl);
3325         if (!p_pbl_virt) {
3326                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3327                 return ECORE_NOMEM;
3328         }
3329
3330         for (i = 0; i < page_cnt; i++) {
3331                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3332                                                  ECORE_CHAIN_PAGE_SIZE);
3333                 if (!p_virt) {
3334                         DP_NOTICE(p_dev, true,
3335                                   "Failed to allocate chain memory\n");
3336                         return ECORE_NOMEM;
3337                 }
3338
3339                 if (i == 0) {
3340                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3341                         ecore_chain_reset(p_chain);
3342                 }
3343
3344                 /* Fill the PBL table with the physical address of the page */
3345                 *(dma_addr_t *)p_pbl_virt = p_phys;
3346                 /* Keep the virtual address of the page */
3347                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3348
3349                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3350         }
3351
3352         return ECORE_SUCCESS;
3353 }
3354
3355 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3356                                        enum ecore_chain_use_mode intended_use,
3357                                        enum ecore_chain_mode mode,
3358                                        enum ecore_chain_cnt_type cnt_type,
3359                                        u32 num_elems, osal_size_t elem_size,
3360                                        struct ecore_chain *p_chain)
3361 {
3362         u32 page_cnt;
3363         enum _ecore_status_t rc = ECORE_SUCCESS;
3364
3365         if (mode == ECORE_CHAIN_MODE_SINGLE)
3366                 page_cnt = 1;
3367         else
3368                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3369
3370         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3371                                             page_cnt);
3372         if (rc) {
3373                 DP_NOTICE(p_dev, true,
3374                           "Cannot allocate a chain with the given arguments:\n"
3375                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3376                           intended_use, mode, cnt_type, num_elems, elem_size);
3377                 return rc;
3378         }
3379
3380         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3381                                 mode, cnt_type, p_dev->dp_ctx);
3382
3383         switch (mode) {
3384         case ECORE_CHAIN_MODE_NEXT_PTR:
3385                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3386                 break;
3387         case ECORE_CHAIN_MODE_SINGLE:
3388                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3389                 break;
3390         case ECORE_CHAIN_MODE_PBL:
3391                 rc = ecore_chain_alloc_pbl(p_dev, p_chain);
3392                 break;
3393         }
3394         if (rc)
3395                 goto nomem;
3396
3397         return ECORE_SUCCESS;
3398
3399  nomem:
3400         ecore_chain_free(p_dev, p_chain);
3401         return rc;
3402 }
3403
3404 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3405                                        u16 src_id, u16 *dst_id)
3406 {
3407         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3408                 u16 min, max;
3409
3410                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3411                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3412                 DP_NOTICE(p_hwfn, true,
3413                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3414                           src_id, min, max);
3415
3416                 return ECORE_INVAL;
3417         }
3418
3419         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3420
3421         return ECORE_SUCCESS;
3422 }
3423
3424 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3425                                     u8 src_id, u8 *dst_id)
3426 {
3427         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3428                 u8 min, max;
3429
3430                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3431                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3432                 DP_NOTICE(p_hwfn, true,
3433                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3434                           src_id, min, max);
3435
3436                 return ECORE_INVAL;
3437         }
3438
3439         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3440
3441         return ECORE_SUCCESS;
3442 }
3443
3444 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3445                                       u8 src_id, u8 *dst_id)
3446 {
3447         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3448                 u8 min, max;
3449
3450                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3451                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3452                 DP_NOTICE(p_hwfn, true,
3453                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3454                           src_id, min, max);
3455
3456                 return ECORE_INVAL;
3457         }
3458
3459         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3460
3461         return ECORE_SUCCESS;
3462 }
3463
3464 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3465                                               struct ecore_ptt *p_ptt,
3466                                               u8 *p_filter)
3467 {
3468         u32 high, low, en;
3469         int i;
3470
3471         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3472                 return ECORE_SUCCESS;
3473
3474         high = p_filter[1] | (p_filter[0] << 8);
3475         low = p_filter[5] | (p_filter[4] << 8) |
3476             (p_filter[3] << 16) | (p_filter[2] << 24);
3477
3478         /* Find a free entry and utilize it */
3479         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3480                 en = ecore_rd(p_hwfn, p_ptt,
3481                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3482                 if (en)
3483                         continue;
3484                 ecore_wr(p_hwfn, p_ptt,
3485                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3486                          2 * i * sizeof(u32), low);
3487                 ecore_wr(p_hwfn, p_ptt,
3488                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3489                          (2 * i + 1) * sizeof(u32), high);
3490                 ecore_wr(p_hwfn, p_ptt,
3491                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3492                 ecore_wr(p_hwfn, p_ptt,
3493                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3494                          i * sizeof(u32), 0);
3495                 ecore_wr(p_hwfn, p_ptt,
3496                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3497                 break;
3498         }
3499         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3500                 DP_NOTICE(p_hwfn, false,
3501                           "Failed to find an empty LLH filter to utilize\n");
3502                 return ECORE_INVAL;
3503         }
3504
3505         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3506                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3507                    p_filter[0], p_filter[1], p_filter[2],
3508                    p_filter[3], p_filter[4], p_filter[5], i);
3509
3510         return ECORE_SUCCESS;
3511 }
3512
3513 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3514                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3515 {
3516         u32 high, low;
3517         int i;
3518
3519         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3520                 return;
3521
3522         high = p_filter[1] | (p_filter[0] << 8);
3523         low = p_filter[5] | (p_filter[4] << 8) |
3524             (p_filter[3] << 16) | (p_filter[2] << 24);
3525
3526         /* Find the entry and clean it */
3527         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3528                 if (ecore_rd(p_hwfn, p_ptt,
3529                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3530                              2 * i * sizeof(u32)) != low)
3531                         continue;
3532                 if (ecore_rd(p_hwfn, p_ptt,
3533                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3534                              (2 * i + 1) * sizeof(u32)) != high)
3535                         continue;
3536
3537                 ecore_wr(p_hwfn, p_ptt,
3538                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3539                 ecore_wr(p_hwfn, p_ptt,
3540                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3541                          2 * i * sizeof(u32), 0);
3542                 ecore_wr(p_hwfn, p_ptt,
3543                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3544                          (2 * i + 1) * sizeof(u32), 0);
3545                 break;
3546         }
3547         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3548                 DP_NOTICE(p_hwfn, false,
3549                           "Tried to remove a non-configured filter\n");
3550 }
3551
3552 enum _ecore_status_t
3553 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3554                               struct ecore_ptt *p_ptt,
3555                               u16 source_port_or_eth_type,
3556                               u16 dest_port,
3557                               enum ecore_llh_port_filter_type_t type)
3558 {
3559         u32 high, low, en;
3560         int i;
3561
3562         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3563                 return ECORE_SUCCESS;
3564
3565         high = 0;
3566         low = 0;
3567         switch (type) {
3568         case ECORE_LLH_FILTER_ETHERTYPE:
3569                 high = source_port_or_eth_type;
3570                 break;
3571         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3572         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3573                 low = source_port_or_eth_type << 16;
3574                 break;
3575         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3576         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3577                 low = dest_port;
3578                 break;
3579         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3580         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3581                 low = (source_port_or_eth_type << 16) | dest_port;
3582                 break;
3583         default:
3584                 DP_NOTICE(p_hwfn, true,
3585                           "Non valid LLH protocol filter type %d\n", type);
3586                 return ECORE_INVAL;
3587         }
3588         /* Find a free entry and utilize it */
3589         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3590                 en = ecore_rd(p_hwfn, p_ptt,
3591                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3592                 if (en)
3593                         continue;
3594                 ecore_wr(p_hwfn, p_ptt,
3595                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3596                          2 * i * sizeof(u32), low);
3597                 ecore_wr(p_hwfn, p_ptt,
3598                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3599                          (2 * i + 1) * sizeof(u32), high);
3600                 ecore_wr(p_hwfn, p_ptt,
3601                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3602                 ecore_wr(p_hwfn, p_ptt,
3603                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3604                          i * sizeof(u32), 1 << type);
3605                 ecore_wr(p_hwfn, p_ptt,
3606                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3607                 break;
3608         }
3609         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3610                 DP_NOTICE(p_hwfn, false,
3611                           "Failed to find an empty LLH filter to utilize\n");
3612                 return ECORE_NORESOURCES;
3613         }
3614         switch (type) {
3615         case ECORE_LLH_FILTER_ETHERTYPE:
3616                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3617                            "ETH type %x is added at %d\n",
3618                            source_port_or_eth_type, i);
3619                 break;
3620         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3621                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3622                            "TCP src port %x is added at %d\n",
3623                            source_port_or_eth_type, i);
3624                 break;
3625         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3626                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3627                            "UDP src port %x is added at %d\n",
3628                            source_port_or_eth_type, i);
3629                 break;
3630         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3631                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3632                            "TCP dst port %x is added at %d\n", dest_port, i);
3633                 break;
3634         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3635                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3636                            "UDP dst port %x is added at %d\n", dest_port, i);
3637                 break;
3638         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3639                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3640                            "TCP src/dst ports %x/%x are added at %d\n",
3641                            source_port_or_eth_type, dest_port, i);
3642                 break;
3643         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3644                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3645                            "UDP src/dst ports %x/%x are added at %d\n",
3646                            source_port_or_eth_type, dest_port, i);
3647                 break;
3648         }
3649         return ECORE_SUCCESS;
3650 }
3651
3652 void
3653 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3654                                  struct ecore_ptt *p_ptt,
3655                                  u16 source_port_or_eth_type,
3656                                  u16 dest_port,
3657                                  enum ecore_llh_port_filter_type_t type)
3658 {
3659         u32 high, low;
3660         int i;
3661
3662         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3663                 return;
3664
3665         high = 0;
3666         low = 0;
3667         switch (type) {
3668         case ECORE_LLH_FILTER_ETHERTYPE:
3669                 high = source_port_or_eth_type;
3670                 break;
3671         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3672         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3673                 low = source_port_or_eth_type << 16;
3674                 break;
3675         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3676         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3677                 low = dest_port;
3678                 break;
3679         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3680         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3681                 low = (source_port_or_eth_type << 16) | dest_port;
3682                 break;
3683         default:
3684                 DP_NOTICE(p_hwfn, true,
3685                           "Non valid LLH protocol filter type %d\n", type);
3686                 return;
3687         }
3688
3689         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3690                 if (!ecore_rd(p_hwfn, p_ptt,
3691                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3692                         continue;
3693                 if (!ecore_rd(p_hwfn, p_ptt,
3694                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3695                         continue;
3696                 if (!(ecore_rd(p_hwfn, p_ptt,
3697                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3698                                i * sizeof(u32)) & (1 << type)))
3699                         continue;
3700                 if (ecore_rd(p_hwfn, p_ptt,
3701                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3702                              2 * i * sizeof(u32)) != low)
3703                         continue;
3704                 if (ecore_rd(p_hwfn, p_ptt,
3705                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3706                              (2 * i + 1) * sizeof(u32)) != high)
3707                         continue;
3708
3709                 ecore_wr(p_hwfn, p_ptt,
3710                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3711                 ecore_wr(p_hwfn, p_ptt,
3712                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3713                 ecore_wr(p_hwfn, p_ptt,
3714                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3715                          i * sizeof(u32), 0);
3716                 ecore_wr(p_hwfn, p_ptt,
3717                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3718                          2 * i * sizeof(u32), 0);
3719                 ecore_wr(p_hwfn, p_ptt,
3720                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3721                          (2 * i + 1) * sizeof(u32), 0);
3722                 break;
3723         }
3724
3725         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3726                 DP_NOTICE(p_hwfn, false,
3727                           "Tried to remove a non-configured filter\n");
3728 }
3729
3730 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3731                                  struct ecore_ptt *p_ptt)
3732 {
3733         int i;
3734
3735         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3736                 return;
3737
3738         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3739                 ecore_wr(p_hwfn, p_ptt,
3740                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3741                 ecore_wr(p_hwfn, p_ptt,
3742                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3743                          2 * i * sizeof(u32), 0);
3744                 ecore_wr(p_hwfn, p_ptt,
3745                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3746                          (2 * i + 1) * sizeof(u32), 0);
3747         }
3748 }
3749
3750 enum _ecore_status_t
3751 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3752                                   struct ecore_ptt *p_ptt)
3753 {
3754         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3755                 ecore_wr(p_hwfn, p_ptt,
3756                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3757                          1 << p_hwfn->abs_pf_id / 2);
3758                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3759                 return ECORE_SUCCESS;
3760         }
3761
3762         DP_NOTICE(p_hwfn, false,
3763                   "This function can't be set as default\n");
3764         return ECORE_INVAL;
3765 }
3766
3767 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3768                                                struct ecore_ptt *p_ptt,
3769                                                u32 hw_addr, void *p_eth_qzone,
3770                                                osal_size_t eth_qzone_size,
3771                                                u8 timeset)
3772 {
3773         struct coalescing_timeset *p_coal_timeset;
3774
3775         if (IS_VF(p_hwfn->p_dev)) {
3776                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3777                 return ECORE_INVAL;
3778         }
3779
3780         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3781                 DP_NOTICE(p_hwfn, true,
3782                           "Coalescing configuration not enabled\n");
3783                 return ECORE_INVAL;
3784         }
3785
3786         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3787         p_coal_timeset = p_eth_qzone;
3788         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3789         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3790         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3791
3792         return ECORE_SUCCESS;
3793 }
3794
3795 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3796                                             struct ecore_ptt *p_ptt,
3797                                             u16 coalesce, u8 qid, u16 sb_id)
3798 {
3799         struct ustorm_eth_queue_zone eth_qzone;
3800         u16 fw_qid = 0;
3801         u32 address;
3802         enum _ecore_status_t rc;
3803         u8 timeset, timer_res;
3804
3805         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3806         if (coalesce <= 0x7F) {
3807                 timer_res = 0;
3808         } else if (coalesce <= 0xFF) {
3809                 timer_res = 1;
3810         } else if (coalesce <= 0x1FF) {
3811                 timer_res = 2;
3812         } else {
3813                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3814                 return ECORE_INVAL;
3815         }
3816         timeset = (u8)(coalesce >> timer_res);
3817
3818         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3819         if (rc != ECORE_SUCCESS)
3820                 return rc;
3821
3822         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3823         if (rc != ECORE_SUCCESS)
3824                 goto out;
3825
3826         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3827
3828         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3829                                 sizeof(struct ustorm_eth_queue_zone), timeset);
3830         if (rc != ECORE_SUCCESS)
3831                 goto out;
3832
3833         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3834  out:
3835         return rc;
3836 }
3837
3838 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3839                                             struct ecore_ptt *p_ptt,
3840                                             u16 coalesce, u8 qid, u16 sb_id)
3841 {
3842         struct xstorm_eth_queue_zone eth_qzone;
3843         u16 fw_qid = 0;
3844         u32 address;
3845         enum _ecore_status_t rc;
3846         u8 timeset, timer_res;
3847
3848         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3849         if (coalesce <= 0x7F) {
3850                 timer_res = 0;
3851         } else if (coalesce <= 0xFF) {
3852                 timer_res = 1;
3853         } else if (coalesce <= 0x1FF) {
3854                 timer_res = 2;
3855         } else {
3856                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3857                 return ECORE_INVAL;
3858         }
3859
3860         timeset = (u8)(coalesce >> timer_res);
3861
3862         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3863         if (rc != ECORE_SUCCESS)
3864                 return rc;
3865
3866         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3867         if (rc != ECORE_SUCCESS)
3868                 goto out;
3869
3870         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3871
3872         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3873                                 sizeof(struct xstorm_eth_queue_zone), timeset);
3874         if (rc != ECORE_SUCCESS)
3875                 goto out;
3876
3877         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3878  out:
3879         return rc;
3880 }
3881
3882 /* Calculate final WFQ values for all vports and configure it.
3883  * After this configuration each vport must have
3884  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3885  */
3886 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3887                                                struct ecore_ptt *p_ptt,
3888                                                u32 min_pf_rate)
3889 {
3890         struct init_qm_vport_params *vport_params;
3891         int i;
3892
3893         vport_params = p_hwfn->qm_info.qm_vport_params;
3894
3895         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3896                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3897
3898                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3899                     min_pf_rate;
3900                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3901                                      vport_params[i].first_tx_pq_id,
3902                                      vport_params[i].vport_wfq);
3903         }
3904 }
3905
3906 static void
3907 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3908 {
3909         int i;
3910
3911         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3912                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3913 }
3914
3915 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3916                                              struct ecore_ptt *p_ptt,
3917                                              u32 min_pf_rate)
3918 {
3919         struct init_qm_vport_params *vport_params;
3920         int i;
3921
3922         vport_params = p_hwfn->qm_info.qm_vport_params;
3923
3924         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3925                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3926                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3927                                      vport_params[i].first_tx_pq_id,
3928                                      vport_params[i].vport_wfq);
3929         }
3930 }
3931
3932 /* This function performs several validations for WFQ
3933  * configuration and required min rate for a given vport
3934  * 1. req_rate must be greater than one percent of min_pf_rate.
3935  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3936  *    rates to get less than one percent of min_pf_rate.
3937  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3938  */
3939 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3940                                                  u16 vport_id, u32 req_rate,
3941                                                  u32 min_pf_rate)
3942 {
3943         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3944         int non_requested_count = 0, req_count = 0, i, num_vports;
3945
3946         num_vports = p_hwfn->qm_info.num_vports;
3947
3948 /* Accounting for the vports which are configured for WFQ explicitly */
3949
3950         for (i = 0; i < num_vports; i++) {
3951                 u32 tmp_speed;
3952
3953                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3954                         req_count++;
3955                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3956                         total_req_min_rate += tmp_speed;
3957                 }
3958         }
3959
3960         /* Include current vport data as well */
3961         req_count++;
3962         total_req_min_rate += req_rate;
3963         non_requested_count = num_vports - req_count;
3964
3965         /* validate possible error cases */
3966         if (req_rate > min_pf_rate) {
3967                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3968                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3969                            vport_id, req_rate, min_pf_rate);
3970                 return ECORE_INVAL;
3971         }
3972
3973         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
3974                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3975                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3976                            vport_id, req_rate, min_pf_rate);
3977                 return ECORE_INVAL;
3978         }
3979
3980         /* TBD - for number of vports greater than 100 */
3981         if (num_vports > ECORE_WFQ_UNIT) {
3982                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3983                            "Number of vports is greater than %d\n",
3984                            ECORE_WFQ_UNIT);
3985                 return ECORE_INVAL;
3986         }
3987
3988         if (total_req_min_rate > min_pf_rate) {
3989                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3990                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3991                            total_req_min_rate, min_pf_rate);
3992                 return ECORE_INVAL;
3993         }
3994
3995         /* Data left for non requested vports */
3996         total_left_rate = min_pf_rate - total_req_min_rate;
3997         left_rate_per_vp = total_left_rate / non_requested_count;
3998
3999         /* validate if non requested get < 1% of min bw */
4000         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4001                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4002                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4003                            left_rate_per_vp, min_pf_rate);
4004                 return ECORE_INVAL;
4005         }
4006
4007         /* now req_rate for given vport passes all scenarios.
4008          * assign final wfq rates to all vports.
4009          */
4010         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4011         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4012
4013         for (i = 0; i < num_vports; i++) {
4014                 if (p_hwfn->qm_info.wfq_data[i].configured)
4015                         continue;
4016
4017                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4018         }
4019
4020         return ECORE_SUCCESS;
4021 }
4022
4023 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4024                                        struct ecore_ptt *p_ptt,
4025                                        u16 vp_id, u32 rate)
4026 {
4027         struct ecore_mcp_link_state *p_link;
4028         int rc = ECORE_SUCCESS;
4029
4030         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4031
4032         if (!p_link->min_pf_rate) {
4033                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4034                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4035                 return rc;
4036         }
4037
4038         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4039
4040         if (rc == ECORE_SUCCESS)
4041                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4042                                                    p_link->min_pf_rate);
4043         else
4044                 DP_NOTICE(p_hwfn, false,
4045                           "Validation failed while configuring min rate\n");
4046
4047         return rc;
4048 }
4049
4050 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4051                                                    struct ecore_ptt *p_ptt,
4052                                                    u32 min_pf_rate)
4053 {
4054         bool use_wfq = false;
4055         int rc = ECORE_SUCCESS;
4056         u16 i;
4057
4058         /* Validate all pre configured vports for wfq */
4059         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4060                 u32 rate;
4061
4062                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4063                         continue;
4064
4065                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4066                 use_wfq = true;
4067
4068                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4069                 if (rc != ECORE_SUCCESS) {
4070                         DP_NOTICE(p_hwfn, false,
4071                                   "WFQ validation failed while configuring min rate\n");
4072                         break;
4073                 }
4074         }
4075
4076         if (rc == ECORE_SUCCESS && use_wfq)
4077                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4078         else
4079                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4080
4081         return rc;
4082 }
4083
4084 /* Main API for ecore clients to configure vport min rate.
4085  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4086  * rate - Speed in Mbps needs to be assigned to a given vport.
4087  */
4088 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4089 {
4090         int i, rc = ECORE_INVAL;
4091
4092         /* TBD - for multiple hardware functions - that is 100 gig */
4093         if (p_dev->num_hwfns > 1) {
4094                 DP_NOTICE(p_dev, false,
4095                           "WFQ configuration is not supported for this device\n");
4096                 return rc;
4097         }
4098
4099         for_each_hwfn(p_dev, i) {
4100                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4101                 struct ecore_ptt *p_ptt;
4102
4103                 p_ptt = ecore_ptt_acquire(p_hwfn);
4104                 if (!p_ptt)
4105                         return ECORE_TIMEOUT;
4106
4107                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4108
4109                 if (rc != ECORE_SUCCESS) {
4110                         ecore_ptt_release(p_hwfn, p_ptt);
4111                         return rc;
4112                 }
4113
4114                 ecore_ptt_release(p_hwfn, p_ptt);
4115         }
4116
4117         return rc;
4118 }
4119
4120 /* API to configure WFQ from mcp link change */
4121 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4122                                            u32 min_pf_rate)
4123 {
4124         int i;
4125
4126         /* TBD - for multiple hardware functions - that is 100 gig */
4127         if (p_dev->num_hwfns > 1) {
4128                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4129                            "WFQ configuration is not supported for this device\n");
4130                 return;
4131         }
4132
4133         for_each_hwfn(p_dev, i) {
4134                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4135
4136                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4137                                                         p_hwfn->p_dpc_ptt,
4138                                                         min_pf_rate);
4139         }
4140 }
4141
4142 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4143                                        struct ecore_ptt *p_ptt,
4144                                        struct ecore_mcp_link_state *p_link,
4145                                        u8 max_bw)
4146 {
4147         int rc = ECORE_SUCCESS;
4148
4149         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4150
4151         if (!p_link->line_speed && (max_bw != 100))
4152                 return rc;
4153
4154         p_link->speed = (p_link->line_speed * max_bw) / 100;
4155         p_hwfn->qm_info.pf_rl = p_link->speed;
4156
4157         /* Since the limiter also affects Tx-switched traffic, we don't want it
4158          * to limit such traffic in case there's no actual limit.
4159          * In that case, set limit to imaginary high boundary.
4160          */
4161         if (max_bw == 100)
4162                 p_hwfn->qm_info.pf_rl = 100000;
4163
4164         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4165                               p_hwfn->qm_info.pf_rl);
4166
4167         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4168                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4169                    p_link->speed);
4170
4171         return rc;
4172 }
4173
4174 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4175 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4176 {
4177         int i, rc = ECORE_INVAL;
4178
4179         if (max_bw < 1 || max_bw > 100) {
4180                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4181                 return rc;
4182         }
4183
4184         for_each_hwfn(p_dev, i) {
4185                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4186                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4187                 struct ecore_mcp_link_state *p_link;
4188                 struct ecore_ptt *p_ptt;
4189
4190                 p_link = &p_lead->mcp_info->link_output;
4191
4192                 p_ptt = ecore_ptt_acquire(p_hwfn);
4193                 if (!p_ptt)
4194                         return ECORE_TIMEOUT;
4195
4196                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4197                                                         p_link, max_bw);
4198
4199                 ecore_ptt_release(p_hwfn, p_ptt);
4200
4201                 if (rc != ECORE_SUCCESS)
4202                         break;
4203         }
4204
4205         return rc;
4206 }
4207
4208 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4209                                        struct ecore_ptt *p_ptt,
4210                                        struct ecore_mcp_link_state *p_link,
4211                                        u8 min_bw)
4212 {
4213         int rc = ECORE_SUCCESS;
4214
4215         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4216         p_hwfn->qm_info.pf_wfq = min_bw;
4217
4218         if (!p_link->line_speed)
4219                 return rc;
4220
4221         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4222
4223         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4224
4225         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4226                    "Configured MIN bandwidth to be %d Mb/sec\n",
4227                    p_link->min_pf_rate);
4228
4229         return rc;
4230 }
4231
4232 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4233 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4234 {
4235         int i, rc = ECORE_INVAL;
4236
4237         if (min_bw < 1 || min_bw > 100) {
4238                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4239                 return rc;
4240         }
4241
4242         for_each_hwfn(p_dev, i) {
4243                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4244                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4245                 struct ecore_mcp_link_state *p_link;
4246                 struct ecore_ptt *p_ptt;
4247
4248                 p_link = &p_lead->mcp_info->link_output;
4249
4250                 p_ptt = ecore_ptt_acquire(p_hwfn);
4251                 if (!p_ptt)
4252                         return ECORE_TIMEOUT;
4253
4254                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4255                                                         p_link, min_bw);
4256                 if (rc != ECORE_SUCCESS) {
4257                         ecore_ptt_release(p_hwfn, p_ptt);
4258                         return rc;
4259                 }
4260
4261                 if (p_link->min_pf_rate) {
4262                         u32 min_rate = p_link->min_pf_rate;
4263
4264                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4265                                                                      p_ptt,
4266                                                                      min_rate);
4267                 }
4268
4269                 ecore_ptt_release(p_hwfn, p_ptt);
4270         }
4271
4272         return rc;
4273 }
4274
4275 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4276 {
4277         struct ecore_mcp_link_state *p_link;
4278
4279         p_link = &p_hwfn->mcp_info->link_output;
4280
4281         if (p_link->min_pf_rate)
4282                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4283                                                  p_link->min_pf_rate);
4284
4285         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4286                     sizeof(*p_hwfn->qm_info.wfq_data) *
4287                     p_hwfn->qm_info.num_vports);
4288 }
4289
4290 int ecore_device_num_engines(struct ecore_dev *p_dev)
4291 {
4292         return ECORE_IS_BB(p_dev) ? 2 : 1;
4293 }
4294
4295 int ecore_device_num_ports(struct ecore_dev *p_dev)
4296 {
4297         /* in CMT always only one port */
4298         if (p_dev->num_hwfns > 1)
4299                 return 1;
4300
4301         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4302 }
4303
4304 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4305                           __le16 *fw_mid,
4306                           __le16 *fw_lsb,
4307                           u8 *mac)
4308 {
4309         ((u8 *)fw_msb)[0] = mac[1];
4310         ((u8 *)fw_msb)[1] = mac[0];
4311         ((u8 *)fw_mid)[0] = mac[3];
4312         ((u8 *)fw_mid)[1] = mac[2];
4313         ((u8 *)fw_lsb)[0] = mac[5];
4314         ((u8 *)fw_lsb)[1] = mac[4];
4315 }