drivers/net/qede/base/ecore_dev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "bcm_osal.h"
   8 #include "reg_addr.h"
   9 #include "ecore_gtt_reg_addr.h"
  10 #include "ecore.h"
  11 #include "ecore_chain.h"
  12 #include "ecore_status.h"
  13 #include "ecore_hw.h"
  14 #include "ecore_rt_defs.h"
  15 #include "ecore_init_ops.h"
  16 #include "ecore_int.h"
  17 #include "ecore_cxt.h"
  18 #include "ecore_spq.h"
  19 #include "ecore_init_fw_funcs.h"
  20 #include "ecore_sp_commands.h"
  21 #include "ecore_dev_api.h"
  22 #include "ecore_sriov.h"
  23 #include "ecore_vf.h"
  24 #include "ecore_mcp.h"
  25 #include "ecore_hw_defs.h"
  26 #include "mcp_public.h"
  27 #include "ecore_iro.h"
  28 #include "nvm_cfg.h"
  29 #include "ecore_dcbx.h"
  30 #include "ecore_l2.h"
  31
  32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  33  * registers involved are not split and thus configuration is a race where
  34  * some of the PFs configuration might be lost.
  35  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  36  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  37  * there's more than a single compiled ecore component in system].
  38  */
  39 static osal_spinlock_t qm_lock;
  40 static u32 qm_lock_ref_cnt;
  41
  42 #ifndef ASIC_ONLY
  43 static bool b_ptt_gtt_init;
  44 #endif
  45
  46 /******************** Doorbell Recovery *******************/
  47 /* The doorbell recovery mechanism consists of a list of entries which represent
  48  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  49  * entity needs to register with the mechanism and provide the parameters
  50  * describing it's doorbell, including a location where last used doorbell data
  51  * can be found. The doorbell execute function will traverse the list and
  52  * doorbell all of the registered entries.
  53  */
  54 struct ecore_db_recovery_entry {
  55         osal_list_entry_t       list_entry;
  56         void OSAL_IOMEM         *db_addr;
  57         void                    *db_data;
  58         enum ecore_db_rec_width db_width;
  59         enum ecore_db_rec_space db_space;
  60         u8                      hwfn_idx;
  61 };
  62
  63 /* display a single doorbell recovery entry */
  64 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  65                                 struct ecore_db_recovery_entry *db_entry,
  66                                 const char *action)
  67 {
  68         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  69                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  70                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  71                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  72                    db_entry->hwfn_idx);
  73 }
  74
  75 /* doorbell address sanity (address within doorbell bar range) */
  76 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  77                          void *db_data)
  78 {
  79         /* make sure doorbell address  is within the doorbell bar */
  80         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  81                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  82                 OSAL_WARN(true,
  83                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  84                           db_addr, p_dev->doorbells,
  85                           (u8 *)p_dev->doorbells + p_dev->db_size);
  86                 return false;
  87         }
  88
  89         /* make sure doorbell data pointer is not null */
  90         if (!db_data) {
  91                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  92                 return false;
  93         }
  94
  95         return true;
  96 }
  97
  98 /* find hwfn according to the doorbell address */
  99 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
 100                                           void OSAL_IOMEM *db_addr)
 101 {
 102         struct ecore_hwfn *p_hwfn;
 103
 104         /* In CMT doorbell bar is split down the middle between engine 0 and
 105          * enigne 1
 106          */
 107         if (ECORE_IS_CMT(p_dev))
 108                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 109                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 110         else
 111                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 112
 113         return p_hwfn;
 114 }
 115
 116 /* add a new entry to the doorbell recovery mechanism */
 117 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 118                                            void OSAL_IOMEM *db_addr,
 119                                            void *db_data,
 120                                            enum ecore_db_rec_width db_width,
 121                                            enum ecore_db_rec_space db_space)
 122 {
 123         struct ecore_db_recovery_entry *db_entry;
 124         struct ecore_hwfn *p_hwfn;
 125
 126         /* shortcircuit VFs, for now */
 127         if (IS_VF(p_dev)) {
 128                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 129                 return ECORE_SUCCESS;
 130         }
 131
 132         /* sanitize doorbell address */
 133         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 134                 return ECORE_INVAL;
 135
 136         /* obtain hwfn from doorbell address */
 137         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 138
 139         /* create entry */
 140         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 141         if (!db_entry) {
 142                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 143                 return ECORE_NOMEM;
 144         }
 145
 146         /* populate entry */
 147         db_entry->db_addr = db_addr;
 148         db_entry->db_data = db_data;
 149         db_entry->db_width = db_width;
 150         db_entry->db_space = db_space;
 151         db_entry->hwfn_idx = p_hwfn->my_id;
 152
 153         /* display */
 154         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 155
 156         /* protect the list */
 157         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 158         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 159                             &p_hwfn->db_recovery_info.list);
 160         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 161
 162         return ECORE_SUCCESS;
 163 }
 164
 165 /* remove an entry from the doorbell recovery mechanism */
 166 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 167                                            void OSAL_IOMEM *db_addr,
 168                                            void *db_data)
 169 {
 170         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 171         enum _ecore_status_t rc = ECORE_INVAL;
 172         struct ecore_hwfn *p_hwfn;
 173
 174         /* shortcircuit VFs, for now */
 175         if (IS_VF(p_dev)) {
 176                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 177                 return ECORE_SUCCESS;
 178         }
 179
 180         /* sanitize doorbell address */
 181         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 182                 return ECORE_INVAL;
 183
 184         /* obtain hwfn from doorbell address */
 185         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 186
 187         /* protect the list */
 188         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 189         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 190                                  &p_hwfn->db_recovery_info.list,
 191                                  list_entry,
 192                                  struct ecore_db_recovery_entry) {
 193                 /* search according to db_data addr since db_addr is not unique
 194                  * (roce)
 195                  */
 196                 if (db_entry->db_data == db_data) {
 197                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 198                                                    "Deleting");
 199                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 200                                                &p_hwfn->db_recovery_info.list);
 201                         rc = ECORE_SUCCESS;
 202                         break;
 203                 }
 204         }
 205
 206         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 207
 208         if (rc == ECORE_INVAL)
 209                 /*OSAL_WARN(true,*/
 210                 DP_NOTICE(p_hwfn, false,
 211                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 212                           db_data, db_addr);
 213         else
 214                 OSAL_FREE(p_dev, db_entry);
 215
 216         return rc;
 217 }
 218
 219 /* initialize the doorbell recovery mechanism */
 220 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 221 {
 222         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 223
 224         /* make sure db_size was set in p_dev */
 225         if (!p_hwfn->p_dev->db_size) {
 226                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 227                 return ECORE_INVAL;
 228         }
 229
 230         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 231 #ifdef CONFIG_ECORE_LOCK_ALLOC
 232         if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
 233                 return ECORE_NOMEM;
 234 #endif
 235         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 236         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 237
 238         return ECORE_SUCCESS;
 239 }
 240
 241 /* destroy the doorbell recovery mechanism */
 242 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 243 {
 244         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 245
 246         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 247         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 248                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 249                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 250                         db_entry = OSAL_LIST_FIRST_ENTRY(
 251                                                 &p_hwfn->db_recovery_info.list,
 252                                                 struct ecore_db_recovery_entry,
 253                                                 list_entry);
 254                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 255                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 256                                                &p_hwfn->db_recovery_info.list);
 257                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 258                 }
 259         }
 260 #ifdef CONFIG_ECORE_LOCK_ALLOC
 261         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 262 #endif
 263         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 264 }
 265
 266 /* print the content of the doorbell recovery mechanism */
 267 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 268 {
 269         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 270
 271         DP_NOTICE(p_hwfn, false,
 272                   "Dispalying doorbell recovery database. Counter was %d\n",
 273                   p_hwfn->db_recovery_info.db_recovery_counter);
 274
 275         /* protect the list */
 276         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 277         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 278                                  &p_hwfn->db_recovery_info.list,
 279                                  list_entry,
 280                                  struct ecore_db_recovery_entry) {
 281                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 282         }
 283
 284         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 285 }
 286
 287 /* ring the doorbell of a single doorbell recovery entry */
 288 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 289                             struct ecore_db_recovery_entry *db_entry,
 290                             enum ecore_db_rec_exec db_exec)
 291 {
 292         /* Print according to width */
 293         if (db_entry->db_width == DB_REC_WIDTH_32B)
 294                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 295                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 296                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 297         else
 298                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 299                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 300                            db_entry->db_addr,
 301                            *(unsigned long *)(db_entry->db_data));
 302
 303         /* Sanity */
 304         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 305                                  db_entry->db_data))
 306                 return;
 307
 308         /* Flush the write combined buffer. Since there are multiple doorbelling
 309          * entities using the same address, if we don't flush, a transaction
 310          * could be lost.
 311          */
 312         OSAL_WMB(p_hwfn->p_dev);
 313
 314         /* Ring the doorbell */
 315         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 316                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 317                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 318                                       *(u32 *)(db_entry->db_data));
 319                 else
 320                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 321                                         *(u64 *)(db_entry->db_data));
 322         }
 323
 324         /* Flush the write combined buffer. Next doorbell may come from a
 325          * different entity to the same address...
 326          */
 327         OSAL_WMB(p_hwfn->p_dev);
 328 }
 329
 330 /* traverse the doorbell recovery entry list and ring all the doorbells */
 331 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 332                                enum ecore_db_rec_exec db_exec)
 333 {
 334         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 335
 336         if (db_exec != DB_REC_ONCE) {
 337                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 338                           p_hwfn->db_recovery_info.db_recovery_counter);
 339
 340                 /* track amount of times recovery was executed */
 341                 p_hwfn->db_recovery_info.db_recovery_counter++;
 342         }
 343
 344         /* protect the list */
 345         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 346         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 347                                  &p_hwfn->db_recovery_info.list,
 348                                  list_entry,
 349                                  struct ecore_db_recovery_entry) {
 350                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 351                 if (db_exec == DB_REC_ONCE)
 352                         break;
 353         }
 354
 355         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 356 }
 357 /******************** Doorbell Recovery end ****************/
 358
 359 /********************************** NIG LLH ***********************************/
 360
 361 enum ecore_llh_filter_type {
 362         ECORE_LLH_FILTER_TYPE_MAC,
 363         ECORE_LLH_FILTER_TYPE_PROTOCOL,
 364 };
 365
 366 struct ecore_llh_mac_filter {
 367         u8 addr[ETH_ALEN];
 368 };
 369
 370 struct ecore_llh_protocol_filter {
 371         enum ecore_llh_prot_filter_type_t type;
 372         u16 source_port_or_eth_type;
 373         u16 dest_port;
 374 };
 375
 376 union ecore_llh_filter {
 377         struct ecore_llh_mac_filter mac;
 378         struct ecore_llh_protocol_filter protocol;
 379 };
 380
 381 struct ecore_llh_filter_info {
 382         bool b_enabled;
 383         u32 ref_cnt;
 384         enum ecore_llh_filter_type type;
 385         union ecore_llh_filter filter;
 386 };
 387
 388 struct ecore_llh_info {
 389         /* Number of LLH filters banks */
 390         u8 num_ppfid;
 391
 392 #define MAX_NUM_PPFID   8
 393         u8 ppfid_array[MAX_NUM_PPFID];
 394
 395         /* Array of filters arrays:
 396          * "num_ppfid" elements of filters banks, where each is an array of
 397          * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
 398          */
 399         struct ecore_llh_filter_info **pp_filters;
 400 };
 401
 402 static void ecore_llh_free(struct ecore_dev *p_dev)
 403 {
 404         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 405         u32 i;
 406
 407         if (p_llh_info != OSAL_NULL) {
 408                 if (p_llh_info->pp_filters != OSAL_NULL) {
 409                         for (i = 0; i < p_llh_info->num_ppfid; i++)
 410                                 OSAL_FREE(p_dev, p_llh_info->pp_filters[i]);
 411                 }
 412
 413                 OSAL_FREE(p_dev, p_llh_info->pp_filters);
 414         }
 415
 416         OSAL_FREE(p_dev, p_llh_info);
 417         p_dev->p_llh_info = OSAL_NULL;
 418 }
 419
 420 static enum _ecore_status_t ecore_llh_alloc(struct ecore_dev *p_dev)
 421 {
 422         struct ecore_llh_info *p_llh_info;
 423         u32 size;
 424         u8 i;
 425
 426         p_llh_info = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_llh_info));
 427         if (!p_llh_info)
 428                 return ECORE_NOMEM;
 429         p_dev->p_llh_info = p_llh_info;
 430
 431         for (i = 0; i < MAX_NUM_PPFID; i++) {
 432                 if (!(p_dev->ppfid_bitmap & (0x1 << i)))
 433                         continue;
 434
 435                 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
 436                 DP_VERBOSE(p_dev, ECORE_MSG_SP, "ppfid_array[%d] = %hhd\n",
 437                            p_llh_info->num_ppfid, i);
 438                 p_llh_info->num_ppfid++;
 439         }
 440
 441         size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
 442         p_llh_info->pp_filters = OSAL_ZALLOC(p_dev, GFP_KERNEL, size);
 443         if (!p_llh_info->pp_filters)
 444                 return ECORE_NOMEM;
 445
 446         size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
 447                sizeof(**p_llh_info->pp_filters);
 448         for (i = 0; i < p_llh_info->num_ppfid; i++) {
 449                 p_llh_info->pp_filters[i] = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 450                                                         size);
 451                 if (!p_llh_info->pp_filters[i])
 452                         return ECORE_NOMEM;
 453         }
 454
 455         return ECORE_SUCCESS;
 456 }
 457
 458 static enum _ecore_status_t ecore_llh_shadow_sanity(struct ecore_dev *p_dev,
 459                                                     u8 ppfid, u8 filter_idx,
 460                                                     const char *action)
 461 {
 462         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 463
 464         if (ppfid >= p_llh_info->num_ppfid) {
 465                 DP_NOTICE(p_dev, false,
 466                           "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
 467                           action, ppfid, p_llh_info->num_ppfid);
 468                 return ECORE_INVAL;
 469         }
 470
 471         if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
 472                 DP_NOTICE(p_dev, false,
 473                           "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
 474                           action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
 475                 return ECORE_INVAL;
 476         }
 477
 478         return ECORE_SUCCESS;
 479 }
 480
 481 #define ECORE_LLH_INVALID_FILTER_IDX    0xff
 482
 483 static enum _ecore_status_t
 484 ecore_llh_shadow_search_filter(struct ecore_dev *p_dev, u8 ppfid,
 485                                union ecore_llh_filter *p_filter,
 486                                u8 *p_filter_idx)
 487 {
 488         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 489         struct ecore_llh_filter_info *p_filters;
 490         enum _ecore_status_t rc;
 491         u8 i;
 492
 493         rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "search");
 494         if (rc != ECORE_SUCCESS)
 495                 return rc;
 496
 497         *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
 498
 499         p_filters = p_llh_info->pp_filters[ppfid];
 500         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 501                 if (!OSAL_MEMCMP(p_filter, &p_filters[i].filter,
 502                                  sizeof(*p_filter))) {
 503                         *p_filter_idx = i;
 504                         break;
 505                 }
 506         }
 507
 508         return ECORE_SUCCESS;
 509 }
 510
 511 static enum _ecore_status_t
 512 ecore_llh_shadow_get_free_idx(struct ecore_dev *p_dev, u8 ppfid,
 513                               u8 *p_filter_idx)
 514 {
 515         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 516         struct ecore_llh_filter_info *p_filters;
 517         enum _ecore_status_t rc;
 518         u8 i;
 519
 520         rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "get_free_idx");
 521         if (rc != ECORE_SUCCESS)
 522                 return rc;
 523
 524         *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
 525
 526         p_filters = p_llh_info->pp_filters[ppfid];
 527         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 528                 if (!p_filters[i].b_enabled) {
 529                         *p_filter_idx = i;
 530                         break;
 531                 }
 532         }
 533
 534         return ECORE_SUCCESS;
 535 }
 536
 537 static enum _ecore_status_t
 538 __ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, u8 filter_idx,
 539                               enum ecore_llh_filter_type type,
 540                               union ecore_llh_filter *p_filter, u32 *p_ref_cnt)
 541 {
 542         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 543         struct ecore_llh_filter_info *p_filters;
 544         enum _ecore_status_t rc;
 545
 546         rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "add");
 547         if (rc != ECORE_SUCCESS)
 548                 return rc;
 549
 550         p_filters = p_llh_info->pp_filters[ppfid];
 551         if (!p_filters[filter_idx].ref_cnt) {
 552                 p_filters[filter_idx].b_enabled = true;
 553                 p_filters[filter_idx].type = type;
 554                 OSAL_MEMCPY(&p_filters[filter_idx].filter, p_filter,
 555                             sizeof(p_filters[filter_idx].filter));
 556         }
 557
 558         *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
 559
 560         return ECORE_SUCCESS;
 561 }
 562
 563 static enum _ecore_status_t
 564 ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid,
 565                             enum ecore_llh_filter_type type,
 566                             union ecore_llh_filter *p_filter,
 567                             u8 *p_filter_idx, u32 *p_ref_cnt)
 568 {
 569         enum _ecore_status_t rc;
 570
 571         /* Check if the same filter already exist */
 572         rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
 573                                             p_filter_idx);
 574         if (rc != ECORE_SUCCESS)
 575                 return rc;
 576
 577         /* Find a new entry in case of a new filter */
 578         if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
 579                 rc = ecore_llh_shadow_get_free_idx(p_dev, ppfid, p_filter_idx);
 580                 if (rc != ECORE_SUCCESS)
 581                         return rc;
 582         }
 583
 584         /* No free entry was found */
 585         if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
 586                 DP_NOTICE(p_dev, false,
 587                           "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
 588                           ppfid);
 589                 return ECORE_NORESOURCES;
 590         }
 591
 592         return __ecore_llh_shadow_add_filter(p_dev, ppfid, *p_filter_idx, type,
 593                                              p_filter, p_ref_cnt);
 594 }
 595
 596 static enum _ecore_status_t
 597 __ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
 598                                  u8 filter_idx, u32 *p_ref_cnt)
 599 {
 600         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 601         struct ecore_llh_filter_info *p_filters;
 602         enum _ecore_status_t rc;
 603
 604         rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "remove");
 605         if (rc != ECORE_SUCCESS)
 606                 return rc;
 607
 608         p_filters = p_llh_info->pp_filters[ppfid];
 609         if (!p_filters[filter_idx].ref_cnt) {
 610                 DP_NOTICE(p_dev, false,
 611                           "LLH shadow: trying to remove a filter with ref_cnt=0\n");
 612                 return ECORE_INVAL;
 613         }
 614
 615         *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
 616         if (!p_filters[filter_idx].ref_cnt)
 617                 OSAL_MEM_ZERO(&p_filters[filter_idx],
 618                               sizeof(p_filters[filter_idx]));
 619
 620         return ECORE_SUCCESS;
 621 }
 622
 623 static enum _ecore_status_t
 624 ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
 625                                union ecore_llh_filter *p_filter,
 626                                u8 *p_filter_idx, u32 *p_ref_cnt)
 627 {
 628         enum _ecore_status_t rc;
 629
 630         rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
 631                                             p_filter_idx);
 632         if (rc != ECORE_SUCCESS)
 633                 return rc;
 634
 635         /* No matching filter was found */
 636         if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
 637                 DP_NOTICE(p_dev, false,
 638                           "Failed to find a filter in the LLH shadow\n");
 639                 return ECORE_INVAL;
 640         }
 641
 642         return __ecore_llh_shadow_remove_filter(p_dev, ppfid, *p_filter_idx,
 643                                                 p_ref_cnt);
 644 }
 645
 646 static enum _ecore_status_t
 647 ecore_llh_shadow_remove_all_filters(struct ecore_dev *p_dev, u8 ppfid)
 648 {
 649         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 650         struct ecore_llh_filter_info *p_filters;
 651         enum _ecore_status_t rc;
 652
 653         rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "remove_all");
 654         if (rc != ECORE_SUCCESS)
 655                 return rc;
 656
 657         p_filters = p_llh_info->pp_filters[ppfid];
 658         OSAL_MEM_ZERO(p_filters,
 659                       NIG_REG_LLH_FUNC_FILTER_EN_SIZE * sizeof(*p_filters));
 660
 661         return ECORE_SUCCESS;
 662 }
 663
 664 static enum _ecore_status_t ecore_abs_ppfid(struct ecore_dev *p_dev,
 665                                             u8 rel_ppfid, u8 *p_abs_ppfid)
 666 {
 667         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 668         u8 ppfids = p_llh_info->num_ppfid - 1;
 669
 670         if (rel_ppfid >= p_llh_info->num_ppfid) {
 671                 DP_NOTICE(p_dev, false,
 672                           "rel_ppfid %d is not valid, available indices are 0..%hhd\n",
 673                           rel_ppfid, ppfids);
 674                 return ECORE_INVAL;
 675         }
 676
 677         *p_abs_ppfid = p_llh_info->ppfid_array[rel_ppfid];
 678
 679         return ECORE_SUCCESS;
 680 }
 681
 682 static enum _ecore_status_t
 683 __ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 684 {
 685         struct ecore_dev *p_dev = p_hwfn->p_dev;
 686         enum ecore_eng eng;
 687         u8 ppfid;
 688         enum _ecore_status_t rc;
 689
 690         rc = ecore_mcp_get_engine_config(p_hwfn, p_ptt);
 691         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
 692                 DP_NOTICE(p_hwfn, false,
 693                           "Failed to get the engine affinity configuration\n");
 694                 return rc;
 695         }
 696
 697         /* RoCE PF is bound to a single engine */
 698         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 699                 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
 700                 rc = ecore_llh_set_roce_affinity(p_dev, eng);
 701                 if (rc != ECORE_SUCCESS) {
 702                         DP_NOTICE(p_dev, false,
 703                                   "Failed to set the RoCE engine affinity\n");
 704                         return rc;
 705                 }
 706
 707                 DP_VERBOSE(p_dev, ECORE_MSG_SP,
 708                            "LLH: Set the engine affinity of RoCE packets as %d\n",
 709                            eng);
 710         }
 711
 712         /* Storage PF is bound to a single engine while L2 PF uses both */
 713         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
 714             ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
 715                 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
 716         else /* L2_PERSONALITY */
 717                 eng = ECORE_BOTH_ENG;
 718
 719         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
 720                 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
 721                 if (rc != ECORE_SUCCESS) {
 722                         DP_NOTICE(p_dev, false,
 723                                   "Failed to set the engine affinity of ppfid %d\n",
 724                                   ppfid);
 725                         return rc;
 726                 }
 727         }
 728
 729         DP_VERBOSE(p_dev, ECORE_MSG_SP,
 730                    "LLH: Set the engine affinity of non-RoCE packets as %d\n",
 731                    eng);
 732
 733         return ECORE_SUCCESS;
 734 }
 735
 736 static enum _ecore_status_t
 737 ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 738                            bool avoid_eng_affin)
 739 {
 740         struct ecore_dev *p_dev = p_hwfn->p_dev;
 741         enum _ecore_status_t rc;
 742
 743         /* Backwards compatible mode:
 744          * - RoCE packets     - Use engine 0.
 745          * - Non-RoCE packets - Use connection based classification for L2 PFs,
 746          *                      and engine 0 otherwise.
 747          */
 748         if (avoid_eng_affin) {
 749                 enum ecore_eng eng;
 750                 u8 ppfid;
 751
 752                 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 753                         eng = ECORE_ENG0;
 754                         rc = ecore_llh_set_roce_affinity(p_dev, eng);
 755                         if (rc != ECORE_SUCCESS) {
 756                                 DP_NOTICE(p_dev, false,
 757                                           "Failed to set the RoCE engine affinity\n");
 758                                 return rc;
 759                         }
 760
 761                         DP_VERBOSE(p_dev, ECORE_MSG_SP,
 762                                    "LLH [backwards compatible mode]: Set the engine affinity of RoCE packets as %d\n",
 763                                    eng);
 764                 }
 765
 766                 eng = (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
 767                        ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) ? ECORE_ENG0
 768                                                            : ECORE_BOTH_ENG;
 769                 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
 770                         rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
 771                         if (rc != ECORE_SUCCESS) {
 772                                 DP_NOTICE(p_dev, false,
 773                                           "Failed to set the engine affinity of ppfid %d\n",
 774                                           ppfid);
 775                                 return rc;
 776                         }
 777                 }
 778
 779                 DP_VERBOSE(p_dev, ECORE_MSG_SP,
 780                            "LLH [backwards compatible mode]: Set the engine affinity of non-RoCE packets as %d\n",
 781                            eng);
 782
 783                 return ECORE_SUCCESS;
 784         }
 785
 786         return __ecore_llh_set_engine_affin(p_hwfn, p_ptt);
 787 }
 788
 789 static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,
 790                                                  struct ecore_ptt *p_ptt,
 791                                                  bool avoid_eng_affin)
 792 {
 793         struct ecore_dev *p_dev = p_hwfn->p_dev;
 794         u8 ppfid, abs_ppfid;
 795         enum _ecore_status_t rc;
 796
 797         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
 798                 u32 addr;
 799
 800                 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
 801                 if (rc != ECORE_SUCCESS)
 802                         return rc;
 803
 804                 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
 805                 ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
 806         }
 807
 808         if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
 809             !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
 810                 rc = ecore_llh_add_mac_filter(p_dev, 0,
 811                                               p_hwfn->hw_info.hw_mac_addr);
 812                 if (rc != ECORE_SUCCESS)
 813                         DP_NOTICE(p_dev, false,
 814                                   "Failed to add an LLH filter with the primary MAC\n");
 815         }
 816
 817         if (ECORE_IS_CMT(p_dev)) {
 818                 rc = ecore_llh_set_engine_affin(p_hwfn, p_ptt, avoid_eng_affin);
 819                 if (rc != ECORE_SUCCESS)
 820                         return rc;
 821         }
 822
 823         return ECORE_SUCCESS;
 824 }
 825
 826 u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev)
 827 {
 828         return p_dev->p_llh_info->num_ppfid;
 829 }
 830
 831 enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev)
 832 {
 833         return p_dev->l2_affin_hint ? ECORE_ENG1 : ECORE_ENG0;
 834 }
 835
 836 /* TBD - should be removed when these definitions are available in reg_addr.h */
 837 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK             0x3
 838 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT            0
 839 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK         0x3
 840 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT        2
 841
 842 enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,
 843                                                   u8 ppfid, enum ecore_eng eng)
 844 {
 845         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
 846         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
 847         u32 addr, val, eng_sel;
 848         enum _ecore_status_t rc = ECORE_SUCCESS;
 849         u8 abs_ppfid;
 850
 851         if (p_ptt == OSAL_NULL)
 852                 return ECORE_AGAIN;
 853
 854         if (!ECORE_IS_CMT(p_dev))
 855                 goto out;
 856
 857         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
 858         if (rc != ECORE_SUCCESS)
 859                 goto out;
 860
 861         switch (eng) {
 862         case ECORE_ENG0:
 863                 eng_sel = 0;
 864                 break;
 865         case ECORE_ENG1:
 866                 eng_sel = 1;
 867                 break;
 868         case ECORE_BOTH_ENG:
 869                 eng_sel = 2;
 870                 break;
 871         default:
 872                 DP_NOTICE(p_dev, false,
 873                           "Invalid affinity value for ppfid [%d]\n", eng);
 874                 rc = ECORE_INVAL;
 875                 goto out;
 876         }
 877
 878         addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 879         val = ecore_rd(p_hwfn, p_ptt, addr);
 880         SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
 881         ecore_wr(p_hwfn, p_ptt, addr, val);
 882
 883         /* The iWARP affinity is set as the affinity of ppfid 0 */
 884         if (!ppfid && ECORE_IS_IWARP_PERSONALITY(p_hwfn))
 885                 p_dev->iwarp_affin = (eng == ECORE_ENG1) ? 1 : 0;
 886 out:
 887         ecore_ptt_release(p_hwfn, p_ptt);
 888
 889         return rc;
 890 }
 891
 892 enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,
 893                                                  enum ecore_eng eng)
 894 {
 895         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
 896         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
 897         u32 addr, val, eng_sel;
 898         enum _ecore_status_t rc = ECORE_SUCCESS;
 899         u8 ppfid, abs_ppfid;
 900
 901         if (p_ptt == OSAL_NULL)
 902                 return ECORE_AGAIN;
 903
 904         if (!ECORE_IS_CMT(p_dev))
 905                 goto out;
 906
 907         switch (eng) {
 908         case ECORE_ENG0:
 909                 eng_sel = 0;
 910                 break;
 911         case ECORE_ENG1:
 912                 eng_sel = 1;
 913                 break;
 914         case ECORE_BOTH_ENG:
 915                 eng_sel = 2;
 916                 ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
 917                          0xf /* QP bit 15 */);
 918                 break;
 919         default:
 920                 DP_NOTICE(p_dev, false,
 921                           "Invalid affinity value for RoCE [%d]\n", eng);
 922                 rc = ECORE_INVAL;
 923                 goto out;
 924         }
 925
 926         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
 927                 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
 928                 if (rc != ECORE_SUCCESS)
 929                         goto out;
 930
 931                 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 932                 val = ecore_rd(p_hwfn, p_ptt, addr);
 933                 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
 934                 ecore_wr(p_hwfn, p_ptt, addr, val);
 935         }
 936 out:
 937         ecore_ptt_release(p_hwfn, p_ptt);
 938
 939         return rc;
 940 }
 941
 942 struct ecore_llh_filter_details {
 943         u64 value;
 944         u32 mode;
 945         u32 protocol_type;
 946         u32 hdr_sel;
 947         u32 enable;
 948 };
 949
 950 static enum _ecore_status_t
 951 ecore_llh_access_filter(struct ecore_hwfn *p_hwfn,
 952                         struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,
 953                         struct ecore_llh_filter_details *p_details,
 954                         bool b_write_access)
 955 {
 956         u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
 957         struct dmae_params params;
 958         enum _ecore_status_t rc;
 959         u32 addr;
 960
 961         /* The NIG/LLH registers that are accessed in this function have only 16
 962          * rows which are exposed to a PF. I.e. only the 16 filters of its
 963          * default ppfid
 964          * Accessing filters of other ppfids requires pretending to other PFs,
 965          * and thus the usage of the ecore_ppfid_rd/wr() functions.
 966          */
 967
 968         /* Filter enable - should be done first when removing a filter */
 969         if (b_write_access && !p_details->enable) {
 970                 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
 971                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
 972                                p_details->enable);
 973         }
 974
 975         /* Filter value */
 976         addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
 977         OSAL_MEMSET(&params, 0, sizeof(params));
 978
 979         if (b_write_access) {
 980                 SET_FIELD(params.flags, DMAE_PARAMS_DST_PF_VALID, 0x1);
 981                 params.dst_pf_id = pfid;
 982                 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
 983                                          (u64)(osal_uintptr_t)&p_details->value,
 984                                          addr, 2 /* size_in_dwords */, &params);
 985         } else {
 986                 SET_FIELD(params.flags, DMAE_PARAMS_SRC_PF_VALID, 0x1);
 987                 SET_FIELD(params.flags, DMAE_PARAMS_COMPLETION_DST, 0x1);
 988                 params.src_pf_id = pfid;
 989                 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr,
 990                                          (u64)(osal_uintptr_t)&p_details->value,
 991                                          2 /* size_in_dwords */, &params);
 992         }
 993
 994         if (rc != ECORE_SUCCESS)
 995                 return rc;
 996
 997         /* Filter mode */
 998         addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
 999         if (b_write_access)
1000                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, p_details->mode);
1001         else
1002                 p_details->mode = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1003                                                  addr);
1004
1005         /* Filter protocol type */
1006         addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
1007         if (b_write_access)
1008                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1009                                p_details->protocol_type);
1010         else
1011                 p_details->protocol_type = ecore_ppfid_rd(p_hwfn, p_ptt,
1012                                                           abs_ppfid, addr);
1013
1014         /* Filter header select */
1015         addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
1016         if (b_write_access)
1017                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1018                                p_details->hdr_sel);
1019         else
1020                 p_details->hdr_sel = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1021                                                     addr);
1022
1023         /* Filter enable - should be done last when adding a filter */
1024         if (!b_write_access || p_details->enable) {
1025                 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
1026                 if (b_write_access)
1027                         ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1028                                        p_details->enable);
1029                 else
1030                         p_details->enable = ecore_ppfid_rd(p_hwfn, p_ptt,
1031                                                            abs_ppfid, addr);
1032         }
1033
1034         return ECORE_SUCCESS;
1035 }
1036
1037 static enum _ecore_status_t
1038 ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1039                         u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type,
1040                         u32 high, u32 low)
1041 {
1042         struct ecore_llh_filter_details filter_details;
1043
1044         filter_details.enable = 1;
1045         filter_details.value = ((u64)high << 32) | low;
1046         filter_details.hdr_sel =
1047                 OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
1048                 1 : /* inner/encapsulated header */
1049                 0;  /* outer/tunnel header */
1050         filter_details.protocol_type = filter_prot_type;
1051         filter_details.mode = filter_prot_type ?
1052                               1 : /* protocol-based classification */
1053                               0;  /* MAC-address based classification */
1054
1055         return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1056                                 &filter_details,
1057                                 true /* write access */);
1058 }
1059
1060 static enum _ecore_status_t
1061 ecore_llh_remove_filter(struct ecore_hwfn *p_hwfn,
1062                            struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
1063 {
1064         struct ecore_llh_filter_details filter_details;
1065
1066         OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1067
1068         return ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1069                                        &filter_details,
1070                                        true /* write access */);
1071 }
1072
1073 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1074                                               u8 mac_addr[ETH_ALEN])
1075 {
1076         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1077         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1078         union ecore_llh_filter filter;
1079         u8 filter_idx, abs_ppfid;
1080         u32 high, low, ref_cnt;
1081         enum _ecore_status_t rc = ECORE_SUCCESS;
1082
1083         if (p_ptt == OSAL_NULL)
1084                 return ECORE_AGAIN;
1085
1086         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1087                 goto out;
1088
1089         OSAL_MEM_ZERO(&filter, sizeof(filter));
1090         OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1091         rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1092                                          ECORE_LLH_FILTER_TYPE_MAC,
1093                                          &filter, &filter_idx, &ref_cnt);
1094         if (rc != ECORE_SUCCESS)
1095                 goto err;
1096
1097         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1098         if (rc != ECORE_SUCCESS)
1099                 goto err;
1100
1101         /* Configure the LLH only in case of a new the filter */
1102         if (ref_cnt == 1) {
1103                 high = mac_addr[1] | (mac_addr[0] << 8);
1104                 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1105                       (mac_addr[2] << 24);
1106                 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1107                                           0, high, low);
1108                 if (rc != ECORE_SUCCESS)
1109                         goto err;
1110         }
1111
1112         DP_VERBOSE(p_dev, ECORE_MSG_SP,
1113                    "LLH: Added MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1114                    mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1115                    mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1116                    ref_cnt);
1117
1118         goto out;
1119
1120 err:
1121         DP_NOTICE(p_dev, false,
1122                   "LLH: Failed to add MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd\n",
1123                   mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1124                   mac_addr[4], mac_addr[5], ppfid);
1125 out:
1126         ecore_ptt_release(p_hwfn, p_ptt);
1127
1128         return rc;
1129 }
1130
1131 static enum _ecore_status_t
1132 ecore_llh_protocol_filter_stringify(struct ecore_dev *p_dev,
1133                                     enum ecore_llh_prot_filter_type_t type,
1134                                     u16 source_port_or_eth_type, u16 dest_port,
1135                                     char *str, osal_size_t str_len)
1136 {
1137         switch (type) {
1138         case ECORE_LLH_FILTER_ETHERTYPE:
1139                 OSAL_SNPRINTF(str, str_len, "Ethertype 0x%04x",
1140                               source_port_or_eth_type);
1141                 break;
1142         case ECORE_LLH_FILTER_TCP_SRC_PORT:
1143                 OSAL_SNPRINTF(str, str_len, "TCP src port 0x%04x",
1144                               source_port_or_eth_type);
1145                 break;
1146         case ECORE_LLH_FILTER_UDP_SRC_PORT:
1147                 OSAL_SNPRINTF(str, str_len, "UDP src port 0x%04x",
1148                               source_port_or_eth_type);
1149                 break;
1150         case ECORE_LLH_FILTER_TCP_DEST_PORT:
1151                 OSAL_SNPRINTF(str, str_len, "TCP dst port 0x%04x", dest_port);
1152                 break;
1153         case ECORE_LLH_FILTER_UDP_DEST_PORT:
1154                 OSAL_SNPRINTF(str, str_len, "UDP dst port 0x%04x", dest_port);
1155                 break;
1156         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1157                 OSAL_SNPRINTF(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1158                               source_port_or_eth_type, dest_port);
1159                 break;
1160         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1161                 OSAL_SNPRINTF(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1162                               source_port_or_eth_type, dest_port);
1163                 break;
1164         default:
1165                 DP_NOTICE(p_dev, true,
1166                           "Non valid LLH protocol filter type %d\n", type);
1167                 return ECORE_INVAL;
1168         }
1169
1170         return ECORE_SUCCESS;
1171 }
1172
1173 static enum _ecore_status_t
1174 ecore_llh_protocol_filter_to_hilo(struct ecore_dev *p_dev,
1175                                   enum ecore_llh_prot_filter_type_t type,
1176                                   u16 source_port_or_eth_type, u16 dest_port,
1177                                   u32 *p_high, u32 *p_low)
1178 {
1179         *p_high = 0;
1180         *p_low = 0;
1181
1182         switch (type) {
1183         case ECORE_LLH_FILTER_ETHERTYPE:
1184                 *p_high = source_port_or_eth_type;
1185                 break;
1186         case ECORE_LLH_FILTER_TCP_SRC_PORT:
1187         case ECORE_LLH_FILTER_UDP_SRC_PORT:
1188                 *p_low = source_port_or_eth_type << 16;
1189                 break;
1190         case ECORE_LLH_FILTER_TCP_DEST_PORT:
1191         case ECORE_LLH_FILTER_UDP_DEST_PORT:
1192                 *p_low = dest_port;
1193                 break;
1194         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1195         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1196                 *p_low = (source_port_or_eth_type << 16) | dest_port;
1197                 break;
1198         default:
1199                 DP_NOTICE(p_dev, true,
1200                           "Non valid LLH protocol filter type %d\n", type);
1201                 return ECORE_INVAL;
1202         }
1203
1204         return ECORE_SUCCESS;
1205 }
1206
1207 enum _ecore_status_t
1208 ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1209                               enum ecore_llh_prot_filter_type_t type,
1210                               u16 source_port_or_eth_type, u16 dest_port)
1211 {
1212         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1213         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1214         u8 filter_idx, abs_ppfid, type_bitmap;
1215         char str[32];
1216         union ecore_llh_filter filter;
1217         u32 high, low, ref_cnt;
1218         enum _ecore_status_t rc = ECORE_SUCCESS;
1219
1220         if (p_ptt == OSAL_NULL)
1221                 return ECORE_AGAIN;
1222
1223         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1224                 goto out;
1225
1226         rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1227                                                  source_port_or_eth_type,
1228                                                  dest_port, str, sizeof(str));
1229         if (rc != ECORE_SUCCESS)
1230                 goto err;
1231
1232         OSAL_MEM_ZERO(&filter, sizeof(filter));
1233         filter.protocol.type = type;
1234         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1235         filter.protocol.dest_port = dest_port;
1236         rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1237                                          ECORE_LLH_FILTER_TYPE_PROTOCOL,
1238                                          &filter, &filter_idx, &ref_cnt);
1239         if (rc != ECORE_SUCCESS)
1240                 goto err;
1241
1242         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1243         if (rc != ECORE_SUCCESS)
1244                 goto err;
1245
1246         /* Configure the LLH only in case of a new the filter */
1247         if (ref_cnt == 1) {
1248                 rc = ecore_llh_protocol_filter_to_hilo(p_dev, type,
1249                                                        source_port_or_eth_type,
1250                                                        dest_port, &high, &low);
1251                 if (rc != ECORE_SUCCESS)
1252                         goto err;
1253
1254                 type_bitmap = 0x1 << type;
1255                 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1256                                           type_bitmap, high, low);
1257                 if (rc != ECORE_SUCCESS)
1258                         goto err;
1259         }
1260
1261         DP_VERBOSE(p_dev, ECORE_MSG_SP,
1262                    "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1263                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1264
1265         goto out;
1266
1267 err:
1268         DP_NOTICE(p_hwfn, false,
1269                   "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1270                   str, ppfid);
1271 out:
1272         ecore_ptt_release(p_hwfn, p_ptt);
1273
1274         return rc;
1275 }
1276
1277 void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1278                                  u8 mac_addr[ETH_ALEN])
1279 {
1280         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1281         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1282         union ecore_llh_filter filter;
1283         u8 filter_idx, abs_ppfid;
1284         enum _ecore_status_t rc = ECORE_SUCCESS;
1285         u32 ref_cnt;
1286
1287         if (p_ptt == OSAL_NULL)
1288                 return;
1289
1290         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1291                 goto out;
1292
1293         OSAL_MEM_ZERO(&filter, sizeof(filter));
1294         OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1295         rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1296                                             &ref_cnt);
1297         if (rc != ECORE_SUCCESS)
1298                 goto err;
1299
1300         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1301         if (rc != ECORE_SUCCESS)
1302                 goto err;
1303
1304         /* Remove from the LLH in case the filter is not in use */
1305         if (!ref_cnt) {
1306                 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1307                                              filter_idx);
1308                 if (rc != ECORE_SUCCESS)
1309                         goto err;
1310         }
1311
1312         DP_VERBOSE(p_dev, ECORE_MSG_SP,
1313                    "LLH: Removed MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1314                    mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1315                    mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1316                    ref_cnt);
1317
1318         goto out;
1319
1320 err:
1321         DP_NOTICE(p_dev, false,
1322                   "LLH: Failed to remove MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd\n",
1323                   mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1324                   mac_addr[4], mac_addr[5], ppfid);
1325 out:
1326         ecore_ptt_release(p_hwfn, p_ptt);
1327 }
1328
1329 void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1330                                       enum ecore_llh_prot_filter_type_t type,
1331                                       u16 source_port_or_eth_type,
1332                                       u16 dest_port)
1333 {
1334         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1335         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1336         u8 filter_idx, abs_ppfid;
1337         char str[32];
1338         union ecore_llh_filter filter;
1339         enum _ecore_status_t rc = ECORE_SUCCESS;
1340         u32 ref_cnt;
1341
1342         if (p_ptt == OSAL_NULL)
1343                 return;
1344
1345         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1346                 goto out;
1347
1348         rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1349                                                  source_port_or_eth_type,
1350                                                  dest_port, str, sizeof(str));
1351         if (rc != ECORE_SUCCESS)
1352                 goto err;
1353
1354         OSAL_MEM_ZERO(&filter, sizeof(filter));
1355         filter.protocol.type = type;
1356         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1357         filter.protocol.dest_port = dest_port;
1358         rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1359                                             &ref_cnt);
1360         if (rc != ECORE_SUCCESS)
1361                 goto err;
1362
1363         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1364         if (rc != ECORE_SUCCESS)
1365                 goto err;
1366
1367         /* Remove from the LLH in case the filter is not in use */
1368         if (!ref_cnt) {
1369                 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1370                                              filter_idx);
1371                 if (rc != ECORE_SUCCESS)
1372                         goto err;
1373         }
1374
1375         DP_VERBOSE(p_dev, ECORE_MSG_SP,
1376                    "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1377                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1378
1379         goto out;
1380
1381 err:
1382         DP_NOTICE(p_dev, false,
1383                   "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1384                   str, ppfid);
1385 out:
1386         ecore_ptt_release(p_hwfn, p_ptt);
1387 }
1388
1389 void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)
1390 {
1391         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1392         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1393         u8 filter_idx, abs_ppfid;
1394         enum _ecore_status_t rc = ECORE_SUCCESS;
1395
1396         if (p_ptt == OSAL_NULL)
1397                 return;
1398
1399         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1400             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1401                 goto out;
1402
1403         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1404         if (rc != ECORE_SUCCESS)
1405                 goto out;
1406
1407         rc = ecore_llh_shadow_remove_all_filters(p_dev, ppfid);
1408         if (rc != ECORE_SUCCESS)
1409                 goto out;
1410
1411         for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1412              filter_idx++) {
1413                 rc = ecore_llh_remove_filter(p_hwfn, p_ptt,
1414                                                 abs_ppfid, filter_idx);
1415                 if (rc != ECORE_SUCCESS)
1416                         goto out;
1417         }
1418 out:
1419         ecore_ptt_release(p_hwfn, p_ptt);
1420 }
1421
1422 void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)
1423 {
1424         u8 ppfid;
1425
1426         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1427             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1428                 return;
1429
1430         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
1431                 ecore_llh_clear_ppfid_filters(p_dev, ppfid);
1432 }
1433
1434 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1435                                          struct ecore_ptt *p_ptt, u32 addr,
1436                                          u32 val)
1437 {
1438         struct ecore_dev *p_dev = p_hwfn->p_dev;
1439         u8 ppfid, abs_ppfid;
1440         enum _ecore_status_t rc;
1441
1442         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1443                 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1444                 if (rc != ECORE_SUCCESS)
1445                         return rc;
1446
1447                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, val);
1448         }
1449
1450         return ECORE_SUCCESS;
1451 }
1452
1453 enum _ecore_status_t
1454 ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid)
1455 {
1456         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1457         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1458         struct ecore_llh_filter_details filter_details;
1459         u8 abs_ppfid, filter_idx;
1460         u32 addr;
1461         enum _ecore_status_t rc;
1462
1463         if (!p_ptt)
1464                 return ECORE_AGAIN;
1465
1466         rc = ecore_abs_ppfid(p_hwfn->p_dev, ppfid, &abs_ppfid);
1467         if (rc != ECORE_SUCCESS)
1468                 goto out;
1469
1470         addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
1471         DP_NOTICE(p_hwfn, false,
1472                   "[rel_pf_id %hhd, ppfid={rel %hhd, abs %hhd}, engine_sel 0x%x]\n",
1473                   p_hwfn->rel_pf_id, ppfid, abs_ppfid,
1474                   ecore_rd(p_hwfn, p_ptt, addr));
1475
1476         for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1477              filter_idx++) {
1478                 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1479                 rc =  ecore_llh_access_filter(p_hwfn, p_ptt, abs_ppfid,
1480                                               filter_idx, &filter_details,
1481                                               false /* read access */);
1482                 if (rc != ECORE_SUCCESS)
1483                         goto out;
1484
1485                 DP_NOTICE(p_hwfn, false,
1486                           "filter %2hhd: enable %d, value 0x%016lx, mode %d, protocol_type 0x%x, hdr_sel 0x%x\n",
1487                           filter_idx, filter_details.enable,
1488                           (unsigned long)filter_details.value,
1489                           filter_details.mode,
1490                           filter_details.protocol_type, filter_details.hdr_sel);
1491         }
1492
1493
1494 out:
1495         ecore_ptt_release(p_hwfn, p_ptt);
1496
1497         return rc;
1498 }
1499
1500 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev)
1501 {
1502         u8 ppfid;
1503         enum _ecore_status_t rc;
1504
1505         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1506                 rc = ecore_llh_dump_ppfid(p_dev, ppfid);
1507                 if (rc != ECORE_SUCCESS)
1508                         return rc;
1509         }
1510
1511         return ECORE_SUCCESS;
1512 }
1513
1514 /******************************* NIG LLH - End ********************************/
1515
1516 /* Configurable */
1517 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
1518                                          * load the driver. The number was
1519                                          * arbitrarily set.
1520                                          */
1521
1522 /* Derived */
1523 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
1524
1525 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
1526                              struct ecore_ptt *p_ptt,
1527                              enum BAR_ID bar_id)
1528 {
1529         u32 bar_reg = (bar_id == BAR_ID_0 ?
1530                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1531         u32 val;
1532
1533         if (IS_VF(p_hwfn->p_dev))
1534                 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
1535
1536         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
1537         if (val)
1538                 return 1 << (val + 15);
1539
1540         /* The above registers were updated in the past only in CMT mode. Since
1541          * they were found to be useful MFW started updating them from 8.7.7.0.
1542          * In older MFW versions they are set to 0 which means disabled.
1543          */
1544         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
1545                 DP_INFO(p_hwfn,
1546                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1547                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1548         } else {
1549                 DP_INFO(p_hwfn,
1550                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1551                 val = 512 * 1024;
1552         }
1553
1554         return val;
1555 }
1556
1557 void ecore_init_dp(struct ecore_dev *p_dev,
1558                    u32 dp_module, u8 dp_level, void *dp_ctx)
1559 {
1560         u32 i;
1561
1562         p_dev->dp_level = dp_level;
1563         p_dev->dp_module = dp_module;
1564         p_dev->dp_ctx = dp_ctx;
1565         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1566                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1567
1568                 p_hwfn->dp_level = dp_level;
1569                 p_hwfn->dp_module = dp_module;
1570                 p_hwfn->dp_ctx = dp_ctx;
1571         }
1572 }
1573
1574 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
1575 {
1576         u8 i;
1577
1578         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1579                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1580
1581                 p_hwfn->p_dev = p_dev;
1582                 p_hwfn->my_id = i;
1583                 p_hwfn->b_active = false;
1584
1585 #ifdef CONFIG_ECORE_LOCK_ALLOC
1586                 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
1587                         goto handle_err;
1588 #endif
1589                 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
1590         }
1591
1592         /* hwfn 0 is always active */
1593         p_dev->hwfns[0].b_active = true;
1594
1595         /* set the default cache alignment to 128 (may be overridden later) */
1596         p_dev->cache_shift = 7;
1597         return ECORE_SUCCESS;
1598 #ifdef CONFIG_ECORE_LOCK_ALLOC
1599 handle_err:
1600         while (--i) {
1601                 struct ecore_hwfn *p_hwfn = OSAL_NULL;
1602
1603                 p_hwfn = &p_dev->hwfns[i];
1604                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
1605         }
1606         return ECORE_NOMEM;
1607 #endif
1608 }
1609
1610 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
1611 {
1612         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1613
1614         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
1615         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
1616         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
1617         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
1618 }
1619
1620 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
1621 {
1622         OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
1623         p_hwfn->dbg_user_info = OSAL_NULL;
1624 }
1625
1626 void ecore_resc_free(struct ecore_dev *p_dev)
1627 {
1628         int i;
1629
1630         if (IS_VF(p_dev)) {
1631                 for_each_hwfn(p_dev, i)
1632                         ecore_l2_free(&p_dev->hwfns[i]);
1633                 return;
1634         }
1635
1636         OSAL_FREE(p_dev, p_dev->fw_data);
1637
1638         OSAL_FREE(p_dev, p_dev->reset_stats);
1639
1640         ecore_llh_free(p_dev);
1641
1642         for_each_hwfn(p_dev, i) {
1643                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1644
1645                 ecore_cxt_mngr_free(p_hwfn);
1646                 ecore_qm_info_free(p_hwfn);
1647                 ecore_spq_free(p_hwfn);
1648                 ecore_eq_free(p_hwfn);
1649                 ecore_consq_free(p_hwfn);
1650                 ecore_int_free(p_hwfn);
1651                 ecore_iov_free(p_hwfn);
1652                 ecore_l2_free(p_hwfn);
1653                 ecore_dmae_info_free(p_hwfn);
1654                 ecore_dcbx_info_free(p_hwfn);
1655                 ecore_dbg_user_data_free(p_hwfn);
1656                 ecore_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
1657                 /* @@@TBD Flush work-queue ? */
1658
1659                 /* destroy doorbell recovery mechanism */
1660                 ecore_db_recovery_teardown(p_hwfn);
1661         }
1662 }
1663
1664 /******************** QM initialization *******************/
1665
1666 /* bitmaps for indicating active traffic classes.
1667  * Special case for Arrowhead 4 port
1668  */
1669 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
1670 #define ACTIVE_TCS_BMAP 0x9f
1671 /* 0..3 actually used, OOO and high priority stuff all use 3 */
1672 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1673
1674 /* determines the physical queue flags for a given PF. */
1675 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
1676 {
1677         u32 flags;
1678
1679         /* common flags */
1680         flags = PQ_FLAGS_LB;
1681
1682         /* feature flags */
1683         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
1684                 flags |= PQ_FLAGS_VFS;
1685         if (IS_ECORE_PACING(p_hwfn))
1686                 flags |= PQ_FLAGS_RLS;
1687
1688         /* protocol flags */
1689         switch (p_hwfn->hw_info.personality) {
1690         case ECORE_PCI_ETH:
1691                 if (!IS_ECORE_PACING(p_hwfn))
1692                         flags |= PQ_FLAGS_MCOS;
1693                 break;
1694         case ECORE_PCI_FCOE:
1695                 flags |= PQ_FLAGS_OFLD;
1696                 break;
1697         case ECORE_PCI_ISCSI:
1698                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1699                 break;
1700         case ECORE_PCI_ETH_ROCE:
1701                 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1702                 if (!IS_ECORE_PACING(p_hwfn))
1703                         flags |= PQ_FLAGS_MCOS;
1704                 break;
1705         case ECORE_PCI_ETH_IWARP:
1706                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1707                 if (!IS_ECORE_PACING(p_hwfn))
1708                         flags |= PQ_FLAGS_MCOS;
1709                 break;
1710         default:
1711                 DP_ERR(p_hwfn, "unknown personality %d\n",
1712                        p_hwfn->hw_info.personality);
1713                 return 0;
1714         }
1715         return flags;
1716 }
1717
1718 /* Getters for resource amounts necessary for qm initialization */
1719 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
1720 {
1721         return p_hwfn->hw_info.num_hw_tc;
1722 }
1723
1724 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
1725 {
1726         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
1727                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
1728 }
1729
1730 #define NUM_DEFAULT_RLS 1
1731
1732 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
1733 {
1734         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
1735
1736         /* num RLs can't exceed resource amount of rls or vports or the
1737          * dcqcn qps
1738          */
1739         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
1740                                      RESC_NUM(p_hwfn, ECORE_VPORT));
1741
1742         /* make sure after we reserve the default and VF rls we'll have
1743          * something left
1744          */
1745         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
1746                 DP_NOTICE(p_hwfn, false,
1747                           "no rate limiters left for PF rate limiting"
1748                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
1749                 return 0;
1750         }
1751
1752         /* subtract rls necessary for VFs and one default one for the PF */
1753         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1754
1755         return num_pf_rls;
1756 }
1757
1758 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
1759 {
1760         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1761
1762         /* all pqs share the same vport (hence the 1 below), except for vfs
1763          * and pf_rl pqs
1764          */
1765         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1766                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1767                (!!(PQ_FLAGS_VFS & pq_flags)) *
1768                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
1769 }
1770
1771 /* calc amount of PQs according to the requested flags */
1772 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
1773 {
1774         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1775
1776         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1777                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1778                (!!(PQ_FLAGS_MCOS & pq_flags)) *
1779                 ecore_init_qm_get_num_tcs(p_hwfn) +
1780                (!!(PQ_FLAGS_LB & pq_flags)) +
1781                (!!(PQ_FLAGS_OOO & pq_flags)) +
1782                (!!(PQ_FLAGS_ACK & pq_flags)) +
1783                (!!(PQ_FLAGS_OFLD & pq_flags)) +
1784                (!!(PQ_FLAGS_VFS & pq_flags)) *
1785                 ecore_init_qm_get_num_vfs(p_hwfn);
1786 }
1787
1788 /* initialize the top level QM params */
1789 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
1790 {
1791         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1792         bool four_port;
1793
1794         /* pq and vport bases for this PF */
1795         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
1796         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
1797
1798         /* rate limiting and weighted fair queueing are always enabled */
1799         qm_info->vport_rl_en = 1;
1800         qm_info->vport_wfq_en = 1;
1801
1802         /* TC config is different for AH 4 port */
1803         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1804
1805         /* in AH 4 port we have fewer TCs per port */
1806         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1807                                                      NUM_OF_PHYS_TCS;
1808
1809         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
1810          * 4 otherwise
1811          */
1812         if (!qm_info->ooo_tc)
1813                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1814                                               DCBX_TCP_OOO_TC;
1815 }
1816
1817 /* initialize qm vport params */
1818 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
1819 {
1820         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1821         u8 i;
1822
1823         /* all vports participate in weighted fair queueing */
1824         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
1825                 qm_info->qm_vport_params[i].wfq = 1;
1826 }
1827
1828 /* initialize qm port params */
1829 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
1830 {
1831         /* Initialize qm port parameters */
1832         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
1833         struct ecore_dev *p_dev = p_hwfn->p_dev;
1834
1835         /* indicate how ooo and high pri traffic is dealt with */
1836         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1837                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
1838
1839         for (i = 0; i < num_ports; i++) {
1840                 struct init_qm_port_params *p_qm_port =
1841                         &p_hwfn->qm_info.qm_port_params[i];
1842                 u16 pbf_max_cmd_lines;
1843
1844                 p_qm_port->active = 1;
1845                 p_qm_port->active_phys_tcs = active_phys_tcs;
1846                 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(p_dev);
1847                 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
1848                 p_qm_port->num_btb_blocks =
1849                         NUM_OF_BTB_BLOCKS(p_dev) / num_ports;
1850         }
1851 }
1852
1853 /* Reset the params which must be reset for qm init. QM init may be called as
1854  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1855  * params may be affected by the init but would simply recalculate to the same
1856  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1857  * affected as these amounts stay the same.
1858  */
1859 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
1860 {
1861         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1862
1863         qm_info->num_pqs = 0;
1864         qm_info->num_vports = 0;
1865         qm_info->num_pf_rls = 0;
1866         qm_info->num_vf_pqs = 0;
1867         qm_info->first_vf_pq = 0;
1868         qm_info->first_mcos_pq = 0;
1869         qm_info->first_rl_pq = 0;
1870 }
1871
1872 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
1873 {
1874         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1875
1876         qm_info->num_vports++;
1877
1878         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1879                 DP_ERR(p_hwfn,
1880                        "vport overflow! qm_info->num_vports %d,"
1881                        " qm_init_get_num_vports() %d\n",
1882                        qm_info->num_vports,
1883                        ecore_init_qm_get_num_vports(p_hwfn));
1884 }
1885
1886 /* initialize a single pq and manage qm_info resources accounting.
1887  * The pq_init_flags param determines whether the PQ is rate limited
1888  * (for VF or PF)
1889  * and whether a new vport is allocated to the pq or not (i.e. vport will be
1890  * shared)
1891  */
1892
1893 /* flags for pq init */
1894 #define PQ_INIT_SHARE_VPORT     (1 << 0)
1895 #define PQ_INIT_PF_RL           (1 << 1)
1896 #define PQ_INIT_VF_RL           (1 << 2)
1897
1898 /* defines for pq init */
1899 #define PQ_INIT_DEFAULT_WRR_GROUP       1
1900 #define PQ_INIT_DEFAULT_TC              0
1901 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
1902
1903 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
1904                              struct ecore_qm_info *qm_info,
1905                              u8 tc, u32 pq_init_flags)
1906 {
1907         u16 pq_idx = qm_info->num_pqs, max_pq =
1908                                         ecore_init_qm_get_num_pqs(p_hwfn);
1909
1910         if (pq_idx > max_pq)
1911                 DP_ERR(p_hwfn,
1912                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1913
1914         /* init pq params */
1915         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1916         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1917                                                  qm_info->num_vports;
1918         qm_info->qm_pq_params[pq_idx].tc_id = tc;
1919         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1920         qm_info->qm_pq_params[pq_idx].rl_valid =
1921                 (pq_init_flags & PQ_INIT_PF_RL ||
1922                  pq_init_flags & PQ_INIT_VF_RL);
1923
1924         /* The "rl_id" is set as the "vport_id" */
1925         qm_info->qm_pq_params[pq_idx].rl_id =
1926                 qm_info->qm_pq_params[pq_idx].vport_id;
1927
1928         /* qm params accounting */
1929         qm_info->num_pqs++;
1930         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1931                 qm_info->num_vports++;
1932
1933         if (pq_init_flags & PQ_INIT_PF_RL)
1934                 qm_info->num_pf_rls++;
1935
1936         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1937                 DP_ERR(p_hwfn,
1938                        "vport overflow! qm_info->num_vports %d,"
1939                        " qm_init_get_num_vports() %d\n",
1940                        qm_info->num_vports,
1941                        ecore_init_qm_get_num_vports(p_hwfn));
1942
1943         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
1944                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
1945                        " qm_init_get_num_pf_rls() %d\n",
1946                        qm_info->num_pf_rls,
1947                        ecore_init_qm_get_num_pf_rls(p_hwfn));
1948 }
1949
1950 /* get pq index according to PQ_FLAGS */
1951 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
1952                                              u32 pq_flags)
1953 {
1954         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1955
1956         /* Can't have multiple flags set here */
1957         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
1958                                 sizeof(pq_flags)) > 1)
1959                 goto err;
1960
1961         switch (pq_flags) {
1962         case PQ_FLAGS_RLS:
1963                 return &qm_info->first_rl_pq;
1964         case PQ_FLAGS_MCOS:
1965                 return &qm_info->first_mcos_pq;
1966         case PQ_FLAGS_LB:
1967                 return &qm_info->pure_lb_pq;
1968         case PQ_FLAGS_OOO:
1969                 return &qm_info->ooo_pq;
1970         case PQ_FLAGS_ACK:
1971                 return &qm_info->pure_ack_pq;
1972         case PQ_FLAGS_OFLD:
1973                 return &qm_info->offload_pq;
1974         case PQ_FLAGS_VFS:
1975                 return &qm_info->first_vf_pq;
1976         default:
1977                 goto err;
1978         }
1979
1980 err:
1981         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
1982         return OSAL_NULL;
1983 }
1984
1985 /* save pq index in qm info */
1986 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
1987                                   u32 pq_flags, u16 pq_val)
1988 {
1989         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1990
1991         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1992 }
1993
1994 /* get tx pq index, with the PQ TX base already set (ready for context init) */
1995 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
1996 {
1997         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1998
1999         return *base_pq_idx + CM_TX_PQ_BASE;
2000 }
2001
2002 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
2003 {
2004         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
2005
2006         if (tc > max_tc)
2007                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
2008
2009         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
2010 }
2011
2012 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
2013 {
2014         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
2015
2016         if (vf > max_vf)
2017                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
2018
2019         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
2020 }
2021
2022 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2023 {
2024         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
2025
2026         /* for rate limiters, it is okay to use the modulo behavior - no
2027          * DP_ERR
2028          */
2029         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl);
2030 }
2031
2032 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2033 {
2034         u16 start_pq, pq, qm_pq_idx;
2035
2036         pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
2037         start_pq = p_hwfn->qm_info.start_pq;
2038         qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
2039
2040         if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
2041                 DP_ERR(p_hwfn,
2042                        "qm_pq_idx %d must be smaller than %d\n",
2043                         qm_pq_idx, p_hwfn->qm_info.num_pqs);
2044         }
2045
2046         return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
2047 }
2048
2049 /* Functions for creating specific types of pqs */
2050 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
2051 {
2052         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2053
2054         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
2055                 return;
2056
2057         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
2058         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
2059 }
2060
2061 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
2062 {
2063         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2064
2065         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
2066                 return;
2067
2068         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
2069         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
2070 }
2071
2072 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
2073 {
2074         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2075
2076         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
2077                 return;
2078
2079         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
2080         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2081 }
2082
2083 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
2084 {
2085         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2086
2087         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
2088                 return;
2089
2090         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
2091         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2092 }
2093
2094 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
2095 {
2096         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2097         u8 tc_idx;
2098
2099         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
2100                 return;
2101
2102         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
2103         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
2104                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
2105 }
2106
2107 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
2108 {
2109         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2110         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
2111
2112         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
2113                 return;
2114
2115         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
2116
2117         qm_info->num_vf_pqs = num_vfs;
2118         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
2119                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
2120                                  PQ_INIT_VF_RL);
2121 }
2122
2123 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
2124 {
2125         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
2126         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2127
2128         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
2129                 return;
2130
2131         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
2132         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
2133                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
2134                                  PQ_INIT_PF_RL);
2135 }
2136
2137 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
2138 {
2139         /* rate limited pqs, must come first (FW assumption) */
2140         ecore_init_qm_rl_pqs(p_hwfn);
2141
2142         /* pqs for multi cos */
2143         ecore_init_qm_mcos_pqs(p_hwfn);
2144
2145         /* pure loopback pq */
2146         ecore_init_qm_lb_pq(p_hwfn);
2147
2148         /* out of order pq */
2149         ecore_init_qm_ooo_pq(p_hwfn);
2150
2151         /* pure ack pq */
2152         ecore_init_qm_pure_ack_pq(p_hwfn);
2153
2154         /* pq for offloaded protocol */
2155         ecore_init_qm_offload_pq(p_hwfn);
2156
2157         /* done sharing vports */
2158         ecore_init_qm_advance_vport(p_hwfn);
2159
2160         /* pqs for vfs */
2161         ecore_init_qm_vf_pqs(p_hwfn);
2162 }
2163
2164 /* compare values of getters against resources amounts */
2165 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
2166 {
2167         if (ecore_init_qm_get_num_vports(p_hwfn) >
2168             RESC_NUM(p_hwfn, ECORE_VPORT)) {
2169                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
2170                 return ECORE_INVAL;
2171         }
2172
2173         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
2174                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
2175                 return ECORE_INVAL;
2176         }
2177
2178         return ECORE_SUCCESS;
2179 }
2180
2181 /*
2182  * Function for verbose printing of the qm initialization results
2183  */
2184 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
2185 {
2186         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2187         struct init_qm_vport_params *vport;
2188         struct init_qm_port_params *port;
2189         struct init_qm_pq_params *pq;
2190         int i, tc;
2191
2192         /* top level params */
2193         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2194                    "qm init top level params: start_pq %d, start_vport %d,"
2195                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
2196                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
2197                    qm_info->offload_pq, qm_info->pure_ack_pq);
2198         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2199                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
2200                    " num_vports %d, max_phys_tcs_per_port %d\n",
2201                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
2202                    qm_info->num_vf_pqs, qm_info->num_vports,
2203                    qm_info->max_phys_tcs_per_port);
2204         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2205                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
2206                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2207                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
2208                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
2209                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
2210
2211         /* port table */
2212         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
2213                 port = &qm_info->qm_port_params[i];
2214                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2215                            "port idx %d, active %d, active_phys_tcs %d,"
2216                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
2217                            " reserved %d\n",
2218                            i, port->active, port->active_phys_tcs,
2219                            port->num_pbf_cmd_lines, port->num_btb_blocks,
2220                            port->reserved);
2221         }
2222
2223         /* vport table */
2224         for (i = 0; i < qm_info->num_vports; i++) {
2225                 vport = &qm_info->qm_vport_params[i];
2226                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "vport idx %d, wfq %d, first_tx_pq_id [ ",
2227                            qm_info->start_vport + i, vport->wfq);
2228                 for (tc = 0; tc < NUM_OF_TCS; tc++)
2229                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
2230                                    vport->first_tx_pq_id[tc]);
2231                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
2232         }
2233
2234         /* pq table */
2235         for (i = 0; i < qm_info->num_pqs; i++) {
2236                 pq = &qm_info->qm_pq_params[i];
2237                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2238                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d, rl_id %d\n",
2239                            qm_info->start_pq + i, pq->port_id, pq->vport_id,
2240                            pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
2241         }
2242 }
2243
2244 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
2245 {
2246         /* reset params required for init run */
2247         ecore_init_qm_reset_params(p_hwfn);
2248
2249         /* init QM top level params */
2250         ecore_init_qm_params(p_hwfn);
2251
2252         /* init QM port params */
2253         ecore_init_qm_port_params(p_hwfn);
2254
2255         /* init QM vport params */
2256         ecore_init_qm_vport_params(p_hwfn);
2257
2258         /* init QM physical queue params */
2259         ecore_init_qm_pq_params(p_hwfn);
2260
2261         /* display all that init */
2262         ecore_dp_init_qm_params(p_hwfn);
2263 }
2264
2265 /* This function reconfigures the QM pf on the fly.
2266  * For this purpose we:
2267  * 1. reconfigure the QM database
2268  * 2. set new values to runtime array
2269  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2270  * 4. activate init tool in QM_PF stage
2271  * 5. send an sdm_qm_cmd through rbc interface to release the QM
2272  */
2273 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
2274                                      struct ecore_ptt *p_ptt)
2275 {
2276         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2277         bool b_rc;
2278         enum _ecore_status_t rc = ECORE_SUCCESS;
2279
2280         /* multiple flows can issue qm reconf. Need to lock */
2281         OSAL_SPIN_LOCK(&qm_lock);
2282
2283         /* initialize ecore's qm data structure */
2284         ecore_init_qm_info(p_hwfn);
2285
2286         /* stop PF's qm queues */
2287         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2288                                       qm_info->start_pq, qm_info->num_pqs);
2289         if (!b_rc) {
2290                 rc = ECORE_INVAL;
2291                 goto unlock;
2292         }
2293
2294         /* clear the QM_PF runtime phase leftovers from previous init */
2295         ecore_init_clear_rt_data(p_hwfn);
2296
2297         /* prepare QM portion of runtime array */
2298         ecore_qm_init_pf(p_hwfn, p_ptt, false);
2299
2300         /* activate init tool on runtime array */
2301         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2302                             p_hwfn->hw_info.hw_mode);
2303
2304         /* start PF's qm queues */
2305         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2306                                       qm_info->start_pq, qm_info->num_pqs);
2307         if (!b_rc)
2308                 rc = ECORE_INVAL;
2309
2310 unlock:
2311         OSAL_SPIN_UNLOCK(&qm_lock);
2312
2313         return rc;
2314 }
2315
2316 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
2317 {
2318         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2319         enum _ecore_status_t rc;
2320
2321         rc = ecore_init_qm_sanity(p_hwfn);
2322         if (rc != ECORE_SUCCESS)
2323                 goto alloc_err;
2324
2325         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2326                                             sizeof(struct init_qm_pq_params) *
2327                                             ecore_init_qm_get_num_pqs(p_hwfn));
2328         if (!qm_info->qm_pq_params)
2329                 goto alloc_err;
2330
2331         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2332                                        sizeof(struct init_qm_vport_params) *
2333                                        ecore_init_qm_get_num_vports(p_hwfn));
2334         if (!qm_info->qm_vport_params)
2335                 goto alloc_err;
2336
2337         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2338                                       sizeof(struct init_qm_port_params) *
2339                                       p_hwfn->p_dev->num_ports_in_engine);
2340         if (!qm_info->qm_port_params)
2341                 goto alloc_err;
2342
2343         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2344                                         sizeof(struct ecore_wfq_data) *
2345                                         ecore_init_qm_get_num_vports(p_hwfn));
2346         if (!qm_info->wfq_data)
2347                 goto alloc_err;
2348
2349         return ECORE_SUCCESS;
2350
2351 alloc_err:
2352         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
2353         ecore_qm_info_free(p_hwfn);
2354         return ECORE_NOMEM;
2355 }
2356 /******************** End QM initialization ***************/
2357
2358 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
2359 {
2360         enum _ecore_status_t rc = ECORE_SUCCESS;
2361         int i;
2362
2363         if (IS_VF(p_dev)) {
2364                 for_each_hwfn(p_dev, i) {
2365                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
2366                         if (rc != ECORE_SUCCESS)
2367                                 return rc;
2368                 }
2369                 return rc;
2370         }
2371
2372         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2373                                      sizeof(*p_dev->fw_data));
2374         if (!p_dev->fw_data)
2375                 return ECORE_NOMEM;
2376
2377         for_each_hwfn(p_dev, i) {
2378                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2379                 u32 n_eqes, num_cons;
2380
2381                 /* initialize the doorbell recovery mechanism */
2382                 rc = ecore_db_recovery_setup(p_hwfn);
2383                 if (rc)
2384                         goto alloc_err;
2385
2386                 /* First allocate the context manager structure */
2387                 rc = ecore_cxt_mngr_alloc(p_hwfn);
2388                 if (rc)
2389                         goto alloc_err;
2390
2391                 /* Set the HW cid/tid numbers (in the context manager)
2392                  * Must be done prior to any further computations.
2393                  */
2394                 rc = ecore_cxt_set_pf_params(p_hwfn);
2395                 if (rc)
2396                         goto alloc_err;
2397
2398                 rc = ecore_alloc_qm_data(p_hwfn);
2399                 if (rc)
2400                         goto alloc_err;
2401
2402                 /* init qm info */
2403                 ecore_init_qm_info(p_hwfn);
2404
2405                 /* Compute the ILT client partition */
2406                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
2407                 if (rc)
2408                         goto alloc_err;
2409
2410                 /* CID map / ILT shadow table / T2
2411                  * The talbes sizes are determined by the computations above
2412                  */
2413                 rc = ecore_cxt_tables_alloc(p_hwfn);
2414                 if (rc)
2415                         goto alloc_err;
2416
2417                 /* SPQ, must follow ILT because initializes SPQ context */
2418                 rc = ecore_spq_alloc(p_hwfn);
2419                 if (rc)
2420                         goto alloc_err;
2421
2422                 /* SP status block allocation */
2423                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
2424                                                            RESERVED_PTT_DPC);
2425
2426                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2427                 if (rc)
2428                         goto alloc_err;
2429
2430                 rc = ecore_iov_alloc(p_hwfn);
2431                 if (rc)
2432                         goto alloc_err;
2433
2434                 /* EQ */
2435                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
2436                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
2437                         /* Calculate the EQ size
2438                          * ---------------------
2439                          * Each ICID may generate up to one event at a time i.e.
2440                          * the event must be handled/cleared before a new one
2441                          * can be generated. We calculate the sum of events per
2442                          * protocol and create an EQ deep enough to handle the
2443                          * worst case:
2444                          * - Core - according to SPQ.
2445                          * - RoCE - per QP there are a couple of ICIDs, one
2446                          *        responder and one requester, each can
2447                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
2448                          *        Each CQ can generate an EQE. There are 2 CQs
2449                          *        per QP => n_eqes_cq = 2 * n_qp.
2450                          *        Hence the RoCE total is 4 * n_qp or
2451                          *        2 * num_cons.
2452                          * - ENet - There can be up to two events per VF. One
2453                          *        for VF-PF channel and another for VF FLR
2454                          *        initial cleanup. The number of VFs is
2455                          *        bounded by MAX_NUM_VFS_BB, and is much
2456                          *        smaller than RoCE's so we avoid exact
2457                          *        calculation.
2458                          */
2459                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
2460                                 num_cons =
2461                                     ecore_cxt_get_proto_cid_count(
2462                                                 p_hwfn,
2463                                                 PROTOCOLID_ROCE,
2464                                                 OSAL_NULL);
2465                                 num_cons *= 2;
2466                         } else {
2467                                 num_cons = ecore_cxt_get_proto_cid_count(
2468                                                 p_hwfn,
2469                                                 PROTOCOLID_IWARP,
2470                                                 OSAL_NULL);
2471                         }
2472                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
2473                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
2474                         num_cons =
2475                             ecore_cxt_get_proto_cid_count(p_hwfn,
2476                                                           PROTOCOLID_ISCSI,
2477                                                           OSAL_NULL);
2478                         n_eqes += 2 * num_cons;
2479                 }
2480
2481                 if (n_eqes > 0xFFFF) {
2482                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
2483                                        "The maximum of a u16 chain is 0x%x\n",
2484                                n_eqes, 0xFFFF);
2485                         goto alloc_no_mem;
2486                 }
2487
2488                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
2489                 if (rc)
2490                         goto alloc_err;
2491
2492                 rc = ecore_consq_alloc(p_hwfn);
2493                 if (rc)
2494                         goto alloc_err;
2495
2496                 rc = ecore_l2_alloc(p_hwfn);
2497                 if (rc != ECORE_SUCCESS)
2498                         goto alloc_err;
2499
2500                 /* DMA info initialization */
2501                 rc = ecore_dmae_info_alloc(p_hwfn);
2502                 if (rc) {
2503                         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
2504                         goto alloc_err;
2505                 }
2506
2507                 /* DCBX initialization */
2508                 rc = ecore_dcbx_info_alloc(p_hwfn);
2509                 if (rc) {
2510                         DP_NOTICE(p_hwfn, false,
2511                                   "Failed to allocate memory for dcbx structure\n");
2512                         goto alloc_err;
2513                 }
2514
2515                 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
2516                 if (rc) {
2517                         DP_NOTICE(p_hwfn, false,
2518                                   "Failed to allocate dbg user info structure\n");
2519                         goto alloc_err;
2520                 }
2521
2522                 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
2523                 if (rc) {
2524                         DP_NOTICE(p_hwfn, false,
2525                                   "Failed to allocate dbg user info structure\n");
2526                         goto alloc_err;
2527                 }
2528         } /* hwfn loop */
2529
2530         rc = ecore_llh_alloc(p_dev);
2531         if (rc != ECORE_SUCCESS) {
2532                 DP_NOTICE(p_dev, true,
2533                           "Failed to allocate memory for the llh_info structure\n");
2534                 goto alloc_err;
2535         }
2536
2537         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2538                                          sizeof(*p_dev->reset_stats));
2539         if (!p_dev->reset_stats) {
2540                 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
2541                 goto alloc_no_mem;
2542         }
2543
2544         return ECORE_SUCCESS;
2545
2546 alloc_no_mem:
2547         rc = ECORE_NOMEM;
2548 alloc_err:
2549         ecore_resc_free(p_dev);
2550         return rc;
2551 }
2552
2553 void ecore_resc_setup(struct ecore_dev *p_dev)
2554 {
2555         int i;
2556
2557         if (IS_VF(p_dev)) {
2558                 for_each_hwfn(p_dev, i)
2559                         ecore_l2_setup(&p_dev->hwfns[i]);
2560                 return;
2561         }
2562
2563         for_each_hwfn(p_dev, i) {
2564                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2565
2566                 ecore_cxt_mngr_setup(p_hwfn);
2567                 ecore_spq_setup(p_hwfn);
2568                 ecore_eq_setup(p_hwfn);
2569                 ecore_consq_setup(p_hwfn);
2570
2571                 /* Read shadow of current MFW mailbox */
2572                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2573                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2574                             p_hwfn->mcp_info->mfw_mb_cur,
2575                             p_hwfn->mcp_info->mfw_mb_length);
2576
2577                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2578
2579                 ecore_l2_setup(p_hwfn);
2580                 ecore_iov_setup(p_hwfn);
2581         }
2582 }
2583
2584 #define FINAL_CLEANUP_POLL_CNT  (100)
2585 #define FINAL_CLEANUP_POLL_TIME (10)
2586 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
2587                                          struct ecore_ptt *p_ptt,
2588                                          u16 id, bool is_vf)
2589 {
2590         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2591         enum _ecore_status_t rc = ECORE_TIMEOUT;
2592
2593 #ifndef ASIC_ONLY
2594         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
2595             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2596                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
2597                 return ECORE_SUCCESS;
2598         }
2599 #endif
2600
2601         addr = GTT_BAR0_MAP_REG_USDM_RAM +
2602             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2603
2604         if (is_vf)
2605                 id += 0x10;
2606
2607         command |= X_FINAL_CLEANUP_AGG_INT <<
2608             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2609         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2610         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2611         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2612
2613 /* Make sure notification is not set before initiating final cleanup */
2614
2615         if (REG_RD(p_hwfn, addr)) {
2616                 DP_NOTICE(p_hwfn, false,
2617                           "Unexpected; Found final cleanup notification");
2618                 DP_NOTICE(p_hwfn, false,
2619                           " before initiating final cleanup\n");
2620                 REG_WR(p_hwfn, addr, 0);
2621         }
2622
2623         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2624                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2625                    id, command);
2626
2627         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2628
2629         /* Poll until completion */
2630         while (!REG_RD(p_hwfn, addr) && count--)
2631                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
2632
2633         if (REG_RD(p_hwfn, addr))
2634                 rc = ECORE_SUCCESS;
2635         else
2636                 DP_NOTICE(p_hwfn, true,
2637                           "Failed to receive FW final cleanup notification\n");
2638
2639         /* Cleanup afterwards */
2640         REG_WR(p_hwfn, addr, 0);
2641
2642         return rc;
2643 }
2644
2645 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
2646 {
2647         int hw_mode = 0;
2648
2649         if (ECORE_IS_BB(p_hwfn->p_dev)) {
2650                 hw_mode |= 1 << MODE_BB;
2651         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
2652                 hw_mode |= 1 << MODE_K2;
2653         } else {
2654                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
2655                           p_hwfn->p_dev->type);
2656                 return ECORE_INVAL;
2657         }
2658
2659         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
2660         switch (p_hwfn->p_dev->num_ports_in_engine) {
2661         case 1:
2662                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2663                 break;
2664         case 2:
2665                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2666                 break;
2667         case 4:
2668                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2669                 break;
2670         default:
2671                 DP_NOTICE(p_hwfn, true,
2672                           "num_ports_in_engine = %d not supported\n",
2673                           p_hwfn->p_dev->num_ports_in_engine);
2674                 return ECORE_INVAL;
2675         }
2676
2677         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
2678                 hw_mode |= 1 << MODE_MF_SD;
2679         else
2680                 hw_mode |= 1 << MODE_MF_SI;
2681
2682 #ifndef ASIC_ONLY
2683         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2684                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2685                         hw_mode |= 1 << MODE_FPGA;
2686                 } else {
2687                         if (p_hwfn->p_dev->b_is_emul_full)
2688                                 hw_mode |= 1 << MODE_EMUL_FULL;
2689                         else
2690                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
2691                 }
2692         } else
2693 #endif
2694                 hw_mode |= 1 << MODE_ASIC;
2695
2696         if (ECORE_IS_CMT(p_hwfn->p_dev))
2697                 hw_mode |= 1 << MODE_100G;
2698
2699         p_hwfn->hw_info.hw_mode = hw_mode;
2700
2701         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
2702                    "Configuring function for hw_mode: 0x%08x\n",
2703                    p_hwfn->hw_info.hw_mode);
2704
2705         return ECORE_SUCCESS;
2706 }
2707
2708 #ifndef ASIC_ONLY
2709 /* MFW-replacement initializations for emulation */
2710 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_dev *p_dev,
2711                                                struct ecore_ptt *p_ptt)
2712 {
2713         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2714         u32 pl_hv, wr_mbs;
2715         int i, pos;
2716         u16 ctrl = 0;
2717
2718         if (!CHIP_REV_IS_EMUL(p_dev)) {
2719                 DP_NOTICE(p_dev, false,
2720                           "ecore_hw_init_chip() shouldn't be called in a non-emulation environment\n");
2721                 return ECORE_INVAL;
2722         }
2723
2724         pl_hv = ECORE_IS_BB(p_dev) ? 0x1 : 0x401;
2725         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
2726
2727         if (ECORE_IS_AH(p_dev))
2728                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2, 0x3ffffff);
2729
2730         /* Initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
2731         if (ECORE_IS_BB(p_dev))
2732                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
2733
2734         if (ECORE_IS_AH(p_dev)) {
2735                 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
2736                 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
2737                          p_dev->num_ports_in_engine >> 1);
2738
2739                 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
2740                          p_dev->num_ports_in_engine == 4 ? 0 : 3);
2741         }
2742
2743         /* Signal the PSWRQ block to start initializing internal memories */
2744         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
2745         for (i = 0; i < 100; i++) {
2746                 OSAL_UDELAY(50);
2747                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
2748                         break;
2749         }
2750         if (i == 100) {
2751                 DP_NOTICE(p_hwfn, true,
2752                           "RBC done failed to complete in PSWRQ2\n");
2753                 return ECORE_TIMEOUT;
2754         }
2755
2756         /* Indicate PSWRQ to initialize steering tag table with zeros */
2757         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RESET_STT, 1);
2758         for (i = 0; i < 100; i++) {
2759                 OSAL_UDELAY(50);
2760                 if (!ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_RESET_STT))
2761                         break;
2762         }
2763         if (i == 100) {
2764                 DP_NOTICE(p_hwfn, true,
2765                           "Steering tag table initialization failed to complete in PSWRQ2\n");
2766                 return ECORE_TIMEOUT;
2767         }
2768
2769         /* Clear a possible PSWRQ2 STT parity which might have been generated by
2770          * a previous MSI-X read.
2771          */
2772         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_PRTY_STS_WR_H_0, 0x8);
2773
2774         /* Configure PSWRQ2_REG_WR_MBS0 according to the MaxPayloadSize field in
2775          * the PCI configuration space. The value is common for all PFs, so it
2776          * is okay to do it according to the first loading PF.
2777          */
2778         pos = OSAL_PCI_FIND_CAPABILITY(p_dev, PCI_CAP_ID_EXP);
2779         if (!pos) {
2780                 DP_NOTICE(p_dev, true,
2781                           "Failed to find the PCI Express Capability structure in the PCI config space\n");
2782                 return ECORE_IO;
2783         }
2784
2785         OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2786         wr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
2787         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs);
2788
2789         /* Configure the PGLUE_B to discard mode */
2790         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_DISCARD_NBLOCK, 0x3f);
2791
2792         return ECORE_SUCCESS;
2793 }
2794 #endif
2795
2796 /* Init run time data for all PFs and their VFs on an engine.
2797  * TBD - for VFs - Once we have parent PF info for each VF in
2798  * shmem available as CAU requires knowledge of parent PF for each VF.
2799  */
2800 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
2801 {
2802         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2803         u32 igu_sb_id;
2804         int i;
2805
2806         for_each_hwfn(p_dev, i) {
2807                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2808                 struct ecore_igu_info *p_igu_info;
2809                 struct ecore_igu_block *p_block;
2810                 struct cau_sb_entry sb_entry;
2811
2812                 p_igu_info = p_hwfn->hw_info.p_igu_info;
2813
2814                 for (igu_sb_id = 0;
2815                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
2816                      igu_sb_id++) {
2817                         p_block = &p_igu_info->entry[igu_sb_id];
2818
2819                         if (!p_block->is_pf)
2820                                 continue;
2821
2822                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
2823                                                 p_block->function_id, 0, 0);
2824                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2825                                          sb_entry);
2826                 }
2827         }
2828 }
2829
2830 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
2831                                        struct ecore_ptt *p_ptt)
2832 {
2833         u32 val, wr_mbs, cache_line_size;
2834
2835         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2836         switch (val) {
2837         case 0:
2838                 wr_mbs = 128;
2839                 break;
2840         case 1:
2841                 wr_mbs = 256;
2842                 break;
2843         case 2:
2844                 wr_mbs = 512;
2845                 break;
2846         default:
2847                 DP_INFO(p_hwfn,
2848                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2849                         val);
2850                 return;
2851         }
2852
2853         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
2854         switch (cache_line_size) {
2855         case 32:
2856                 val = 0;
2857                 break;
2858         case 64:
2859                 val = 1;
2860                 break;
2861         case 128:
2862                 val = 2;
2863                 break;
2864         case 256:
2865                 val = 3;
2866                 break;
2867         default:
2868                 DP_INFO(p_hwfn,
2869                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2870                         cache_line_size);
2871         }
2872
2873         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
2874                 DP_INFO(p_hwfn,
2875                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2876                         OSAL_CACHE_LINE_SIZE, wr_mbs);
2877
2878         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2879         if (val > 0) {
2880                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2881                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2882         }
2883 }
2884
2885 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
2886                                                  struct ecore_ptt *p_ptt,
2887                                                  int hw_mode)
2888 {
2889         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2890         struct ecore_dev *p_dev = p_hwfn->p_dev;
2891         u8 vf_id, max_num_vfs;
2892         u16 num_pfs, pf_id;
2893         u32 concrete_fid;
2894         enum _ecore_status_t rc = ECORE_SUCCESS;
2895
2896         ecore_init_cau_rt_data(p_dev);
2897
2898         /* Program GTT windows */
2899         ecore_gtt_init(p_hwfn);
2900
2901 #ifndef ASIC_ONLY
2902         if (CHIP_REV_IS_EMUL(p_dev) && IS_LEAD_HWFN(p_hwfn)) {
2903                 rc = ecore_hw_init_chip(p_dev, p_ptt);
2904                 if (rc != ECORE_SUCCESS)
2905                         return rc;
2906         }
2907 #endif
2908
2909         if (p_hwfn->mcp_info) {
2910                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2911                         qm_info->pf_rl_en = 1;
2912                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2913                         qm_info->pf_wfq_en = 1;
2914         }
2915
2916         ecore_qm_common_rt_init(p_hwfn,
2917                                 p_dev->num_ports_in_engine,
2918                                 qm_info->max_phys_tcs_per_port,
2919                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
2920                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
2921                                 qm_info->qm_port_params,
2922                                 OSAL_NULL /* global RLs are not configured */);
2923
2924         ecore_cxt_hw_init_common(p_hwfn);
2925
2926         ecore_init_cache_line_size(p_hwfn, p_ptt);
2927
2928         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
2929                             hw_mode);
2930         if (rc != ECORE_SUCCESS)
2931                 return rc;
2932
2933         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
2934          * need to decide with which value, maybe runtime
2935          */
2936         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2937         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2938
2939         if (ECORE_IS_BB(p_dev)) {
2940                 /* Workaround clears ROCE search for all functions to prevent
2941                  * involving non initialized function in processing ROCE packet.
2942                  */
2943                 num_pfs = (u16)NUM_OF_ENG_PFS(p_dev);
2944                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2945                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
2946                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2947                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2948                 }
2949                 /* pretend to original PF */
2950                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2951         }
2952
2953         /* Workaround for avoiding CCFC execution error when getting packets
2954          * with CRC errors, and allowing instead the invoking of the FW error
2955          * handler.
2956          * This is not done inside the init tool since it currently can't
2957          * perform a pretending to VFs.
2958          */
2959         max_num_vfs = (u8)NUM_OF_VFS(p_dev);
2960         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2961                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
2962                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
2963                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2964                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2965                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2966                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2967         }
2968         /* pretend to original PF */
2969         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2970
2971         return rc;
2972 }
2973
2974 #ifndef ASIC_ONLY
2975 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
2976 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
2977
2978 #define PMEG_IF_BYTE_COUNT      8
2979
2980 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
2981                              struct ecore_ptt *p_ptt,
2982                              u32 addr, u64 data, u8 reg_type, u8 port)
2983 {
2984         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2985                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
2986                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
2987                    (8 << PMEG_IF_BYTE_COUNT),
2988                    (reg_type << 25) | (addr << 8) | port,
2989                    (u32)((data >> 32) & 0xffffffff),
2990                    (u32)(data & 0xffffffff));
2991
2992         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
2993                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
2994                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
2995         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
2996                  (reg_type << 25) | (addr << 8) | port);
2997         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
2998         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
2999                  (data >> 32) & 0xffffffff);
3000 }
3001
3002 #define XLPORT_MODE_REG (0x20a)
3003 #define XLPORT_MAC_CONTROL (0x210)
3004 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
3005 #define XLPORT_ENABLE_REG (0x20b)
3006
3007 #define XLMAC_CTRL (0x600)
3008 #define XLMAC_MODE (0x601)
3009 #define XLMAC_RX_MAX_SIZE (0x608)
3010 #define XLMAC_TX_CTRL (0x604)
3011 #define XLMAC_PAUSE_CTRL (0x60d)
3012 #define XLMAC_PFC_CTRL (0x60e)
3013
3014 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
3015                                     struct ecore_ptt *p_ptt)
3016 {
3017         u8 loopback = 0, port = p_hwfn->port_id * 2;
3018
3019         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
3020         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
3021                          port);
3022         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
3023         /* XLMAC: SOFT RESET */
3024         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
3025         /* XLMAC: Port Speed >= 10Gbps */
3026         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
3027         /* XLMAC: Max Size */
3028         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
3029         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
3030                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
3031                          0, port);
3032         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
3033         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
3034                          0x30ffffc000ULL, 0, port);
3035         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
3036                          port); /* XLMAC: TX_EN, RX_EN */
3037         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
3038         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
3039                          0x1003 | (loopback << 2), 0, port);
3040         /* Enabled Parallel PFC interface */
3041         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
3042
3043         /* XLPORT port enable */
3044         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
3045 }
3046
3047 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
3048                                        struct ecore_ptt *p_ptt)
3049 {
3050         u32 mac_base, mac_config_val = 0xa853;
3051         u8 port = p_hwfn->port_id;
3052
3053         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
3054                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT) |
3055                  (port <<
3056                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT) |
3057                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT));
3058
3059         mac_base = NWM_REG_MAC0_K2 + (port << 2) * NWM_REG_MAC0_SIZE;
3060
3061         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2,
3062                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT);
3063
3064         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2,
3065                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT);
3066
3067         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2,
3068                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT);
3069
3070         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2,
3071                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT);
3072
3073         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2,
3074                  (0xA <<
3075                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT) |
3076                  (8 <<
3077                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT));
3078
3079         /* Strip the CRC field from the frame */
3080         mac_config_val &= ~ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2;
3081         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2,
3082                  mac_config_val);
3083 }
3084
3085 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
3086                                  struct ecore_ptt *p_ptt)
3087 {
3088         u8 port = ECORE_IS_BB(p_hwfn->p_dev) ? p_hwfn->port_id * 2
3089                                              : p_hwfn->port_id;
3090
3091         DP_INFO(p_hwfn->p_dev, "Emulation: Configuring Link [port %02x]\n",
3092                 port);
3093
3094         if (ECORE_IS_BB(p_hwfn->p_dev))
3095                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
3096         else
3097                 ecore_emul_link_init_ah(p_hwfn, p_ptt);
3098
3099         return;
3100 }
3101
3102 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
3103                                struct ecore_ptt *p_ptt,  u8 port)
3104 {
3105         int port_offset = port ? 0x800 : 0;
3106         u32 xmac_rxctrl = 0;
3107
3108         /* Reset of XMAC */
3109         /* FIXME: move to common start */
3110         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3111                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
3112         OSAL_MSLEEP(1);
3113         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3114                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
3115
3116         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
3117
3118         /* Set the number of ports on the Warp Core to 10G */
3119         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
3120
3121         /* Soft reset of XMAC */
3122         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3123                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3124         OSAL_MSLEEP(1);
3125         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3126                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3127
3128         /* FIXME: move to common end */
3129         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3130                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
3131
3132         /* Set Max packet size: initialize XMAC block register for port 0 */
3133         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
3134
3135         /* CRC append for Tx packets: init XMAC block register for port 1 */
3136         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
3137
3138         /* Enable TX and RX: initialize XMAC block register for port 1 */
3139         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
3140                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
3141         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
3142                                XMAC_REG_RX_CTRL_BB + port_offset);
3143         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
3144         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
3145 }
3146 #endif
3147
3148 static u32 ecore_hw_norm_region_conn(struct ecore_hwfn *p_hwfn)
3149 {
3150         u32 norm_region_conn;
3151
3152         /* The order of CIDs allocation is according to the order of
3153          * 'enum protocol_type'. Therefore, the number of CIDs for the normal
3154          * region is calculated based on the CORE CIDs, in case of non-ETH
3155          * personality, and otherwise - based on the ETH CIDs.
3156          */
3157         norm_region_conn =
3158                 ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
3159                 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
3160                                               OSAL_NULL) +
3161                 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
3162                                               OSAL_NULL);
3163
3164         return norm_region_conn;
3165 }
3166
3167 static enum _ecore_status_t
3168 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
3169                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
3170 {
3171         u32 dpi_bit_shift, dpi_count, dpi_page_size;
3172         u32 min_dpis;
3173         u32 n_wids;
3174
3175         /* Calculate DPI size
3176          * ------------------
3177          * The PWM region contains Doorbell Pages. The first is reserverd for
3178          * the kernel for, e.g, L2. The others are free to be used by non-
3179          * trusted applications, typically from user space. Each page, called a
3180          * doorbell page is sectioned into windows that allow doorbells to be
3181          * issued in parallel by the kernel/application. The size of such a
3182          * window (a.k.a. WID) is 1kB.
3183          * Summary:
3184          *    1kB WID x N WIDS = DPI page size
3185          *    DPI page size x N DPIs = PWM region size
3186          * Notes:
3187          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
3188          * in order to ensure that two applications won't share the same page.
3189          * It also must contain at least one WID per CPU to allow parallelism.
3190          * It also must be a power of 2, since it is stored as a bit shift.
3191          *
3192          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
3193          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
3194          * containing 4 WIDs.
3195          */
3196         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
3197         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
3198         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
3199                         ~(OSAL_PAGE_SIZE - 1);
3200         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
3201         dpi_count = pwm_region_size / dpi_page_size;
3202
3203         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
3204         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
3205
3206         /* Update hwfn */
3207         p_hwfn->dpi_size = dpi_page_size;
3208         p_hwfn->dpi_count = dpi_count;
3209
3210         /* Update registers */
3211         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
3212
3213         if (dpi_count < min_dpis)
3214                 return ECORE_NORESOURCES;
3215
3216         return ECORE_SUCCESS;
3217 }
3218
3219 enum ECORE_ROCE_EDPM_MODE {
3220         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
3221         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
3222         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
3223 };
3224
3225 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn)
3226 {
3227         if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
3228                 return false;
3229
3230         return true;
3231 }
3232
3233 static enum _ecore_status_t
3234 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
3235                               struct ecore_ptt *p_ptt)
3236 {
3237         u32 norm_region_conn, min_addr_reg1;
3238         u32 pwm_regsize, norm_regsize;
3239         u32 db_bar_size, n_cpus;
3240         u32 roce_edpm_mode;
3241         u32 pf_dems_shift;
3242         enum _ecore_status_t rc = ECORE_SUCCESS;
3243         u8 cond;
3244
3245         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
3246         if (ECORE_IS_CMT(p_hwfn->p_dev))
3247                 db_bar_size /= 2;
3248
3249         /* Calculate doorbell regions
3250          * -----------------------------------
3251          * The doorbell BAR is made of two regions. The first is called normal
3252          * region and the second is called PWM region. In the normal region
3253          * each ICID has its own set of addresses so that writing to that
3254          * specific address identifies the ICID. In the Process Window Mode
3255          * region the ICID is given in the data written to the doorbell. The
3256          * above per PF register denotes the offset in the doorbell BAR in which
3257          * the PWM region begins.
3258          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
3259          * non-PWM connection. The calculation below computes the total non-PWM
3260          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
3261          * in units of 4,096 bytes.
3262          */
3263         norm_region_conn = ecore_hw_norm_region_conn(p_hwfn);
3264         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * norm_region_conn,
3265                                OSAL_PAGE_SIZE);
3266         min_addr_reg1 = norm_regsize / 4096;
3267         pwm_regsize = db_bar_size - norm_regsize;
3268
3269         /* Check that the normal and PWM sizes are valid */
3270         if (db_bar_size < norm_regsize) {
3271                 DP_ERR(p_hwfn->p_dev,
3272                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
3273                        db_bar_size, norm_regsize);
3274                 return ECORE_NORESOURCES;
3275         }
3276         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
3277                 DP_ERR(p_hwfn->p_dev,
3278                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
3279                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
3280                        norm_regsize);
3281                 return ECORE_NORESOURCES;
3282         }
3283
3284         /* Calculate number of DPIs */
3285         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
3286         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
3287             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
3288                 /* Either EDPM is mandatory, or we are attempting to allocate a
3289                  * WID per CPU.
3290                  */
3291                 n_cpus = OSAL_NUM_CPUS();
3292                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3293         }
3294
3295         cond = ((rc != ECORE_SUCCESS) &&
3296                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
3297                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
3298         if (cond || p_hwfn->dcbx_no_edpm) {
3299                 /* Either EDPM is disabled from user configuration, or it is
3300                  * disabled via DCBx, or it is not mandatory and we failed to
3301                  * allocated a WID per CPU.
3302                  */
3303                 n_cpus = 1;
3304                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3305
3306                 /* If we entered this flow due to DCBX then the DPM register is
3307                  * already configured.
3308                  */
3309         }
3310
3311         DP_INFO(p_hwfn,
3312                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
3313                 norm_regsize, pwm_regsize);
3314         DP_INFO(p_hwfn,
3315                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
3316                 p_hwfn->dpi_size, p_hwfn->dpi_count,
3317                 (!ecore_edpm_enabled(p_hwfn)) ?
3318                 "disabled" : "enabled");
3319
3320         /* Check return codes from above calls */
3321         if (rc != ECORE_SUCCESS) {
3322                 DP_ERR(p_hwfn,
3323                        "Failed to allocate enough DPIs\n");
3324                 return ECORE_NORESOURCES;
3325         }
3326
3327         /* Update hwfn */
3328         p_hwfn->dpi_start_offset = norm_regsize;
3329
3330         /* Update registers */
3331         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
3332         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
3333         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
3334         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
3335
3336         return ECORE_SUCCESS;
3337 }
3338
3339 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
3340                                                struct ecore_ptt *p_ptt,
3341                                                int hw_mode)
3342 {
3343         struct ecore_dev *p_dev = p_hwfn->p_dev;
3344         enum _ecore_status_t rc = ECORE_SUCCESS;
3345
3346         /* In CMT the gate should be cleared by the 2nd hwfn */
3347         if (!ECORE_IS_CMT(p_dev) || !IS_LEAD_HWFN(p_hwfn))
3348                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
3349
3350         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
3351                             hw_mode);
3352         if (rc != ECORE_SUCCESS)
3353                 return rc;
3354
3355         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
3356
3357 #ifndef ASIC_ONLY
3358         if (CHIP_REV_IS_FPGA(p_dev) && ECORE_IS_BB(p_dev))
3359                 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
3360
3361         if (CHIP_REV_IS_EMUL(p_dev)) {
3362                 if (ECORE_IS_CMT(p_dev)) {
3363                         /* Activate OPTE in CMT */
3364                         u32 val;
3365
3366                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
3367                         val |= 0x10;
3368                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
3369                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
3370                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
3371                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
3372                         ecore_wr(p_hwfn, p_ptt,
3373                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
3374                         ecore_wr(p_hwfn, p_ptt,
3375                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
3376                         ecore_wr(p_hwfn, p_ptt,
3377                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
3378                                  0x55555555);
3379                 }
3380
3381                 /* Set the TAGMAC default function on the port if needed.
3382                  * The ppfid should be set in the vector, except in BB which has
3383                  * a bug in the LLH where the ppfid is actually engine based.
3384                  */
3385                 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {
3386                         u8 pf_id = p_hwfn->rel_pf_id;
3387
3388                         if (!ECORE_IS_BB(p_dev))
3389                                 pf_id /= p_dev->num_ports_in_engine;
3390                         ecore_wr(p_hwfn, p_ptt,
3391                                  NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
3392                 }
3393
3394                 ecore_emul_link_init(p_hwfn, p_ptt);
3395         }
3396 #endif
3397
3398         return ECORE_SUCCESS;
3399 }
3400
3401 static enum _ecore_status_t
3402 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3403                  int hw_mode, struct ecore_hw_init_params *p_params)
3404 {
3405         u8 rel_pf_id = p_hwfn->rel_pf_id;
3406         u32 prs_reg;
3407         enum _ecore_status_t rc = ECORE_SUCCESS;
3408         u16 ctrl;
3409         int pos;
3410
3411         if (p_hwfn->mcp_info) {
3412                 struct ecore_mcp_function_info *p_info;
3413
3414                 p_info = &p_hwfn->mcp_info->func_info;
3415                 if (p_info->bandwidth_min)
3416                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
3417
3418                 /* Update rate limit once we'll actually have a link */
3419                 p_hwfn->qm_info.pf_rl = 100000;
3420         }
3421         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
3422
3423         ecore_int_igu_init_rt(p_hwfn);
3424
3425         /* Set VLAN in NIG if needed */
3426         if (hw_mode & (1 << MODE_MF_SD)) {
3427                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
3428                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
3429                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
3430                              p_hwfn->hw_info.ovlan);
3431
3432                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3433                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
3434                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
3435                              1);
3436         }
3437
3438         /* Enable classification by MAC if needed */
3439         if (hw_mode & (1 << MODE_MF_SI)) {
3440                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3441                            "Configuring TAGMAC_CLS_TYPE\n");
3442                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
3443                              1);
3444         }
3445
3446         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
3447         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
3448                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
3449         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
3450                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
3451         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
3452
3453         /* perform debug configuration when chip is out of reset */
3454         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
3455
3456         /* Sanity check before the PF init sequence that uses DMAE */
3457         rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
3458         if (rc)
3459                 return rc;
3460
3461         /* PF Init sequence */
3462         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
3463         if (rc)
3464                 return rc;
3465
3466         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
3467         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
3468         if (rc)
3469                 return rc;
3470
3471         ecore_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
3472
3473         /* Pure runtime initializations - directly to the HW  */
3474         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
3475
3476         /* PCI relaxed ordering causes a decrease in the performance on some
3477          * systems. Till a root cause is found, disable this attribute in the
3478          * PCI config space.
3479          */
3480         /* Not in use @DPDK
3481         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
3482         * if (!pos) {
3483         *       DP_NOTICE(p_hwfn, true,
3484         *                 "Failed to find the PCIe Cap\n");
3485         *       return ECORE_IO;
3486         * }
3487         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
3488         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
3489         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
3490         */
3491
3492         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
3493         if (rc != ECORE_SUCCESS)
3494                 return rc;
3495
3496         /* Use the leading hwfn since in CMT only NIG #0 is operational */
3497         if (IS_LEAD_HWFN(p_hwfn)) {
3498                 rc = ecore_llh_hw_init_pf(p_hwfn, p_ptt,
3499                                         p_params->avoid_eng_affin);
3500                 if (rc != ECORE_SUCCESS)
3501                         return rc;
3502         }
3503
3504         if (p_params->b_hw_start) {
3505                 /* enable interrupts */
3506                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, p_params->int_mode);
3507                 if (rc != ECORE_SUCCESS)
3508                         return rc;
3509
3510                 /* send function start command */
3511                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_params->p_tunn,
3512                                        p_params->allow_npar_tx_switch);
3513                 if (rc) {
3514                         DP_NOTICE(p_hwfn, true,
3515                                   "Function start ramrod failed\n");
3516                         return rc;
3517                 }
3518                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3519                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3520                                 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3521
3522                 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
3523                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
3524                                         (1 << 2));
3525                         ecore_wr(p_hwfn, p_ptt,
3526                                  PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
3527                                  0x100);
3528                 }
3529                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3530                                 "PRS_REG_SEARCH registers after start PFn\n");
3531                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
3532                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3533                                 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
3534                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
3535                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3536                                 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
3537                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
3538                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3539                                 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
3540                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
3541                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3542                                 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
3543                 prs_reg = ecore_rd(p_hwfn, p_ptt,
3544                                 PRS_REG_SEARCH_TCP_FIRST_FRAG);
3545                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3546                                 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
3547                                 prs_reg);
3548                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3549                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3550                                 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3551         }
3552         return ECORE_SUCCESS;
3553 }
3554
3555 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
3556                                                   struct ecore_ptt *p_ptt,
3557                                                   bool b_enable)
3558 {
3559         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
3560
3561         /* Configure the PF's internal FID_enable for master transactions */
3562         ecore_wr(p_hwfn, p_ptt,
3563                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
3564
3565         /* Wait until value is set - try for 1 second every 50us */
3566         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
3567                 val = ecore_rd(p_hwfn, p_ptt,
3568                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
3569                 if (val == set_val)
3570                         break;
3571
3572                 OSAL_UDELAY(50);
3573         }
3574
3575         if (val != set_val) {
3576                 DP_NOTICE(p_hwfn, true,
3577                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
3578                 return ECORE_UNKNOWN_ERROR;
3579         }
3580
3581         return ECORE_SUCCESS;
3582 }
3583
3584 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
3585                                   struct ecore_ptt *p_main_ptt)
3586 {
3587         /* Read shadow of current MFW mailbox */
3588         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
3589         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
3590                     p_hwfn->mcp_info->mfw_mb_cur,
3591                     p_hwfn->mcp_info->mfw_mb_length);
3592 }
3593
3594 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
3595                                    struct ecore_ptt *p_ptt)
3596 {
3597         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3598                  1 << p_hwfn->abs_pf_id);
3599 }
3600
3601 static enum _ecore_status_t
3602 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
3603                            struct ecore_load_req_params *p_load_req,
3604                            struct ecore_drv_load_params *p_drv_load)
3605 {
3606         /* Make sure that if ecore-client didn't provide inputs, all the
3607          * expected defaults are indeed zero.
3608          */
3609         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
3610         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
3611         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
3612
3613         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
3614
3615         if (p_drv_load == OSAL_NULL)
3616                 goto out;
3617
3618         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
3619                                ECORE_DRV_ROLE_KDUMP :
3620                                ECORE_DRV_ROLE_OS;
3621         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
3622         p_load_req->override_force_load = p_drv_load->override_force_load;
3623
3624         /* Old MFW versions don't support timeout values other than default and
3625          * none, so these values are replaced according to the fall-back action.
3626          */
3627
3628         if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
3629             p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
3630             (p_hwfn->mcp_info->capabilities &
3631              FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
3632                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
3633                 goto out;
3634         }
3635
3636         switch (p_drv_load->mfw_timeout_fallback) {
3637         case ECORE_TO_FALLBACK_TO_NONE:
3638                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
3639                 break;
3640         case ECORE_TO_FALLBACK_TO_DEFAULT:
3641                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
3642                 break;
3643         case ECORE_TO_FALLBACK_FAIL_LOAD:
3644                 DP_NOTICE(p_hwfn, false,
3645                           "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
3646                           p_drv_load->mfw_timeout_val,
3647                           ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
3648                           ECORE_LOAD_REQ_LOCK_TO_NONE);
3649                 return ECORE_ABORTED;
3650         }
3651
3652         DP_INFO(p_hwfn,
3653                 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
3654                 p_drv_load->mfw_timeout_val,
3655                 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
3656                 "default" : "none",
3657                 p_load_req->timeout_val);
3658 out:
3659         return ECORE_SUCCESS;
3660 }
3661
3662 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
3663                                     struct ecore_hw_init_params *p_params)
3664 {
3665         if (p_params->p_tunn) {
3666                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
3667                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
3668         }
3669
3670         p_hwfn->b_int_enabled = 1;
3671
3672         return ECORE_SUCCESS;
3673 }
3674
3675 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
3676                                    struct ecore_hw_init_params *p_params)
3677 {
3678         struct ecore_load_req_params load_req_params;
3679         u32 load_code, resp, param, drv_mb_param;
3680         bool b_default_mtu = true;
3681         struct ecore_hwfn *p_hwfn;
3682         const u32 *fw_overlays;
3683         u32 fw_overlays_len;
3684         enum _ecore_status_t rc = ECORE_SUCCESS;
3685         u16 ether_type;
3686         int i;
3687
3688         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
3689                 DP_NOTICE(p_dev, false,
3690                           "MSI mode is not supported for CMT devices\n");
3691                 return ECORE_INVAL;
3692         }
3693
3694         if (IS_PF(p_dev)) {
3695                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
3696                 if (rc != ECORE_SUCCESS)
3697                         return rc;
3698         }
3699
3700         for_each_hwfn(p_dev, i) {
3701                 p_hwfn = &p_dev->hwfns[i];
3702
3703                 /* If management didn't provide a default, set one of our own */
3704                 if (!p_hwfn->hw_info.mtu) {
3705                         p_hwfn->hw_info.mtu = 1500;
3706                         b_default_mtu = false;
3707                 }
3708
3709                 if (IS_VF(p_dev)) {
3710                         ecore_vf_start(p_hwfn, p_params);
3711                         continue;
3712                 }
3713
3714                 rc = ecore_calc_hw_mode(p_hwfn);
3715                 if (rc != ECORE_SUCCESS)
3716                         return rc;
3717
3718                 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3719                                                    &p_dev->mf_bits) ||
3720                                      OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
3721                                                    &p_dev->mf_bits))) {
3722                         if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3723                                           &p_dev->mf_bits))
3724                                 ether_type = ETHER_TYPE_VLAN;
3725                         else
3726                                 ether_type = ETHER_TYPE_QINQ;
3727                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3728                                      ether_type);
3729                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3730                                      ether_type);
3731                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3732                                      ether_type);
3733                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3734                                      ether_type);
3735                 }
3736
3737                 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
3738
3739                 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
3740                                                 p_params->p_drv_load_params);
3741                 if (rc != ECORE_SUCCESS)
3742                         return rc;
3743
3744                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3745                                         &load_req_params);
3746                 if (rc != ECORE_SUCCESS) {
3747                         DP_NOTICE(p_hwfn, false,
3748                                   "Failed sending a LOAD_REQ command\n");
3749                         return rc;
3750                 }
3751
3752                 load_code = load_req_params.load_code;
3753                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3754                            "Load request was sent. Load code: 0x%x\n",
3755                            load_code);
3756
3757                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3758
3759                 /* CQ75580:
3760                  * When coming back from hiberbate state, the registers from
3761                  * which shadow is read initially are not initialized. It turns
3762                  * out that these registers get initialized during the call to
3763                  * ecore_mcp_load_req request. So we need to reread them here
3764                  * to get the proper shadow register value.
3765                  * Note: This is a workaround for the missing MFW
3766                  * initialization. It may be removed once the implementation
3767                  * is done.
3768                  */
3769                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3770
3771                 /* Only relevant for recovery:
3772                  * Clear the indication after the LOAD_REQ command is responded
3773                  * by the MFW.
3774                  */
3775                 p_dev->recov_in_prog = false;
3776
3777                 p_hwfn->first_on_engine = (load_code ==
3778                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
3779
3780                 if (!qm_lock_ref_cnt) {
3781 #ifdef CONFIG_ECORE_LOCK_ALLOC
3782                         rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
3783                         if (rc) {
3784                                 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
3785                                 goto qm_lock_fail;
3786                         }
3787 #endif
3788                         OSAL_SPIN_LOCK_INIT(&qm_lock);
3789                 }
3790                 ++qm_lock_ref_cnt;
3791
3792                 /* Clean up chip from previous driver if such remains exist.
3793                  * This is not needed when the PF is the first one on the
3794                  * engine, since afterwards we are going to init the FW.
3795                  */
3796                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3797                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3798                                                  p_hwfn->rel_pf_id, false);
3799                         if (rc != ECORE_SUCCESS) {
3800                                 ecore_hw_err_notify(p_hwfn,
3801                                                     ECORE_HW_ERR_RAMROD_FAIL);
3802                                 goto load_err;
3803                         }
3804                 }
3805
3806                 /* Log and clear previous pglue_b errors if such exist */
3807                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
3808
3809                 /* Enable the PF's internal FID_enable in the PXP */
3810                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3811                                                   true);
3812                 if (rc != ECORE_SUCCESS)
3813                         goto load_err;
3814
3815                 /* Clear the pglue_b was_error indication.
3816                  * It must be done after the BME and the internal FID_enable for
3817                  * the PF are set, since VDMs may cause the indication to be set
3818                  * again.
3819                  */
3820                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3821
3822                 fw_overlays = p_dev->fw_data->fw_overlays;
3823                 fw_overlays_len = p_dev->fw_data->fw_overlays_len;
3824                 p_hwfn->fw_overlay_mem =
3825                         ecore_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
3826                                                    fw_overlays_len);
3827                 if (!p_hwfn->fw_overlay_mem) {
3828                         DP_NOTICE(p_hwfn, false,
3829                                   "Failed to allocate fw overlay memory\n");
3830                         goto load_err;
3831                 }
3832
3833                 switch (load_code) {
3834                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3835                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3836                                                   p_hwfn->hw_info.hw_mode);
3837                         if (rc != ECORE_SUCCESS)
3838                                 break;
3839                         /* Fall into */
3840                 case FW_MSG_CODE_DRV_LOAD_PORT:
3841                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3842                                                 p_hwfn->hw_info.hw_mode);
3843                         if (rc != ECORE_SUCCESS)
3844                                 break;
3845                         /* Fall into */
3846                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3847                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3848                                               p_hwfn->hw_info.hw_mode,
3849                                               p_params);
3850                         break;
3851                 default:
3852                         DP_NOTICE(p_hwfn, false,
3853                                   "Unexpected load code [0x%08x]", load_code);
3854                         rc = ECORE_NOTIMPL;
3855                         break;
3856                 }
3857
3858                 if (rc != ECORE_SUCCESS) {
3859                         DP_NOTICE(p_hwfn, false,
3860                                   "init phase failed for loadcode 0x%x (rc %d)\n",
3861                                   load_code, rc);
3862                         goto load_err;
3863                 }
3864
3865                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3866                 if (rc != ECORE_SUCCESS) {
3867                         DP_NOTICE(p_hwfn, false,
3868                                   "Sending load done failed, rc = %d\n", rc);
3869                         if (rc == ECORE_NOMEM) {
3870                                 DP_NOTICE(p_hwfn, false,
3871                                           "Sending load done was failed due to memory allocation failure\n");
3872                                 goto load_err;
3873                         }
3874                         return rc;
3875                 }
3876
3877                 /* send DCBX attention request command */
3878                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
3879                            "sending phony dcbx set command to trigger DCBx attention handling\n");
3880                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3881                                    DRV_MSG_CODE_SET_DCBX,
3882                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
3883                                    &param);
3884                 if (rc != ECORE_SUCCESS) {
3885                         DP_NOTICE(p_hwfn, false,
3886                                   "Failed to send DCBX attention request\n");
3887                         return rc;
3888                 }
3889
3890                 p_hwfn->hw_init_done = true;
3891         }
3892
3893         if (IS_PF(p_dev)) {
3894                 /* Get pre-negotiated values for stag, bandwidth etc. */
3895                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3896                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3897                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3898                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3899                                    DRV_MSG_CODE_GET_OEM_UPDATES,
3900                                    1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3901                                    &resp, &param);
3902                 if (rc != ECORE_SUCCESS)
3903                         DP_NOTICE(p_hwfn, false,
3904                                   "Failed to send GET_OEM_UPDATES attention request\n");
3905         }
3906
3907         if (IS_PF(p_dev)) {
3908                 /* Get pre-negotiated values for stag, bandwidth etc. */
3909                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3910                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3911                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3912                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3913                                    DRV_MSG_CODE_GET_OEM_UPDATES,
3914                                    1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3915                                    &resp, &param);
3916                 if (rc != ECORE_SUCCESS)
3917                         DP_NOTICE(p_hwfn, false,
3918                                   "Failed to send GET_OEM_UPDATES attention request\n");
3919         }
3920
3921         if (IS_PF(p_dev)) {
3922                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3923                 drv_mb_param = STORM_FW_VERSION;
3924                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3925                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3926                                    drv_mb_param, &resp, &param);
3927                 if (rc != ECORE_SUCCESS)
3928                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
3929
3930                 if (!b_default_mtu) {
3931                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3932                                                       p_hwfn->hw_info.mtu);
3933                         if (rc != ECORE_SUCCESS)
3934                                 DP_INFO(p_hwfn, "Failed to update default mtu\n");
3935                 }
3936
3937                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
3938                                                       p_hwfn->p_main_ptt,
3939                                                 ECORE_OV_DRIVER_STATE_DISABLED);
3940                 if (rc != ECORE_SUCCESS)
3941                         DP_INFO(p_hwfn, "Failed to update driver state\n");
3942
3943                 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3944                                                  ECORE_OV_ESWITCH_NONE);
3945                 if (rc != ECORE_SUCCESS)
3946                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3947         }
3948
3949         return rc;
3950
3951 load_err:
3952         --qm_lock_ref_cnt;
3953 #ifdef CONFIG_ECORE_LOCK_ALLOC
3954         if (!qm_lock_ref_cnt)
3955                 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
3956 qm_lock_fail:
3957 #endif
3958         /* The MFW load lock should be released regardless of success or failure
3959          * of initialization.
3960          * TODO: replace this with an attempt to send cancel_load.
3961          */
3962         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3963         return rc;
3964 }
3965
3966 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
3967 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
3968                                  struct ecore_hwfn *p_hwfn,
3969                                  struct ecore_ptt *p_ptt)
3970 {
3971         int i;
3972
3973         /* close timers */
3974         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3975         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3976         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
3977                                                                         i++) {
3978                 if ((!ecore_rd(p_hwfn, p_ptt,
3979                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3980                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3981                         break;
3982
3983                 /* Dependent on number of connection/tasks, possibly
3984                  * 1ms sleep is required between polls
3985                  */
3986                 OSAL_MSLEEP(1);
3987         }
3988
3989         if (i < ECORE_HW_STOP_RETRY_LIMIT)
3990                 return;
3991
3992         DP_NOTICE(p_hwfn, false,
3993                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3994                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3995                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3996 }
3997
3998 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
3999 {
4000         int j;
4001
4002         for_each_hwfn(p_dev, j) {
4003                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4004                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
4005
4006                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
4007         }
4008 }
4009
4010 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
4011                                                  struct ecore_ptt *p_ptt,
4012                                                  u32 addr, u32 expected_val)
4013 {
4014         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
4015
4016         if (val != expected_val) {
4017                 DP_NOTICE(p_hwfn, true,
4018                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
4019                           addr, val, expected_val);
4020                 return ECORE_UNKNOWN_ERROR;
4021         }
4022
4023         return ECORE_SUCCESS;
4024 }
4025
4026 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
4027 {
4028         struct ecore_hwfn *p_hwfn;
4029         struct ecore_ptt *p_ptt;
4030         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
4031         int j;
4032
4033         for_each_hwfn(p_dev, j) {
4034                 p_hwfn = &p_dev->hwfns[j];
4035                 p_ptt = p_hwfn->p_main_ptt;
4036
4037                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
4038
4039                 if (IS_VF(p_dev)) {
4040                         ecore_vf_pf_int_cleanup(p_hwfn);
4041                         rc = ecore_vf_pf_reset(p_hwfn);
4042                         if (rc != ECORE_SUCCESS) {
4043                                 DP_NOTICE(p_hwfn, true,
4044                                           "ecore_vf_pf_reset failed. rc = %d.\n",
4045                                           rc);
4046                                 rc2 = ECORE_UNKNOWN_ERROR;
4047                         }
4048                         continue;
4049                 }
4050
4051                 /* mark the hw as uninitialized... */
4052                 p_hwfn->hw_init_done = false;
4053
4054                 /* Send unload command to MCP */
4055                 if (!p_dev->recov_in_prog) {
4056                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
4057                         if (rc != ECORE_SUCCESS) {
4058                                 DP_NOTICE(p_hwfn, false,
4059                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
4060                                           rc);
4061                                 rc2 = ECORE_UNKNOWN_ERROR;
4062                         }
4063                 }
4064
4065                 OSAL_DPC_SYNC(p_hwfn);
4066
4067                 /* After this point no MFW attentions are expected, e.g. prevent
4068                  * race between pf stop and dcbx pf update.
4069                  */
4070
4071                 rc = ecore_sp_pf_stop(p_hwfn);
4072                 if (rc != ECORE_SUCCESS) {
4073                         DP_NOTICE(p_hwfn, false,
4074                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
4075                                   rc);
4076                         rc2 = ECORE_UNKNOWN_ERROR;
4077                 }
4078
4079                 OSAL_DPC_SYNC(p_hwfn);
4080
4081                 /* After this point we don't expect the FW to send us async
4082                  * events
4083                  */
4084
4085                 /* perform debug action after PF stop was sent */
4086                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
4087
4088                 /* close NIG to BRB gate */
4089                 ecore_wr(p_hwfn, p_ptt,
4090                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4091
4092                 /* close parser */
4093                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4094                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4095                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4096                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4097                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4098
4099                 /* @@@TBD - clean transmission queues (5.b) */
4100                 /* @@@TBD - clean BTB (5.c) */
4101
4102                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
4103
4104                 /* @@@TBD - verify DMAE requests are done (8) */
4105
4106                 /* Disable Attention Generation */
4107                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
4108                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
4109                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
4110                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
4111                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
4112                 if (rc != ECORE_SUCCESS) {
4113                         DP_NOTICE(p_hwfn, true,
4114                                   "Failed to return IGU CAM to default\n");
4115                         rc2 = ECORE_UNKNOWN_ERROR;
4116                 }
4117
4118                 /* Need to wait 1ms to guarantee SBs are cleared */
4119                 OSAL_MSLEEP(1);
4120
4121                 if (IS_LEAD_HWFN(p_hwfn) &&
4122                     OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
4123                     !ECORE_IS_FCOE_PERSONALITY(p_hwfn))
4124                         ecore_llh_remove_mac_filter(p_dev, 0,
4125                                                    p_hwfn->hw_info.hw_mac_addr);
4126
4127                 if (!p_dev->recov_in_prog) {
4128                         ecore_verify_reg_val(p_hwfn, p_ptt,
4129                                              QM_REG_USG_CNT_PF_TX, 0);
4130                         ecore_verify_reg_val(p_hwfn, p_ptt,
4131                                              QM_REG_USG_CNT_PF_OTHER, 0);
4132                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
4133                 }
4134
4135                 /* Disable PF in HW blocks */
4136                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
4137                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
4138
4139                 --qm_lock_ref_cnt;
4140 #ifdef CONFIG_ECORE_LOCK_ALLOC
4141                 if (!qm_lock_ref_cnt)
4142                         OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
4143 #endif
4144
4145                 if (!p_dev->recov_in_prog) {
4146                         rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4147                         if (rc == ECORE_NOMEM) {
4148                                 DP_NOTICE(p_hwfn, false,
4149                                          "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
4150                                 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4151                         }
4152                         if (rc != ECORE_SUCCESS) {
4153                                 DP_NOTICE(p_hwfn, false,
4154                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
4155                                           rc);
4156                                 rc2 = ECORE_UNKNOWN_ERROR;
4157                         }
4158                 }
4159         } /* hwfn loop */
4160
4161         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
4162                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
4163                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
4164
4165                  /* Clear the PF's internal FID_enable in the PXP.
4166                   * In CMT this should only be done for first hw-function, and
4167                   * only after all transactions have stopped for all active
4168                   * hw-functions.
4169                   */
4170                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
4171                                                   false);
4172                 if (rc != ECORE_SUCCESS) {
4173                         DP_NOTICE(p_hwfn, true,
4174                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
4175                                   rc);
4176                         rc2 = ECORE_UNKNOWN_ERROR;
4177                 }
4178         }
4179
4180         return rc2;
4181 }
4182
4183 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
4184 {
4185         int j;
4186
4187         for_each_hwfn(p_dev, j) {
4188                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4189                 struct ecore_ptt *p_ptt;
4190
4191                 if (IS_VF(p_dev)) {
4192                         ecore_vf_pf_int_cleanup(p_hwfn);
4193                         continue;
4194                 }
4195                 p_ptt = ecore_ptt_acquire(p_hwfn);
4196                 if (!p_ptt)
4197                         return ECORE_AGAIN;
4198
4199                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4200                            "Shutting down the fastpath\n");
4201
4202                 ecore_wr(p_hwfn, p_ptt,
4203                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4204
4205                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4206                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4207                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4208                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4209                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4210
4211                 /* @@@TBD - clean transmission queues (5.b) */
4212                 /* @@@TBD - clean BTB (5.c) */
4213
4214                 /* @@@TBD - verify DMAE requests are done (8) */
4215
4216                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
4217                 /* Need to wait 1ms to guarantee SBs are cleared */
4218                 OSAL_MSLEEP(1);
4219                 ecore_ptt_release(p_hwfn, p_ptt);
4220         }
4221
4222         return ECORE_SUCCESS;
4223 }
4224
4225 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
4226 {
4227         struct ecore_ptt *p_ptt;
4228
4229         if (IS_VF(p_hwfn->p_dev))
4230                 return ECORE_SUCCESS;
4231
4232         p_ptt = ecore_ptt_acquire(p_hwfn);
4233         if (!p_ptt)
4234                 return ECORE_AGAIN;
4235
4236         /* If roce info is allocated it means roce is initialized and should
4237          * be enabled in searcher.
4238          */
4239         if (p_hwfn->p_rdma_info) {
4240                 if (p_hwfn->b_rdma_enabled_in_prs)
4241                         ecore_wr(p_hwfn, p_ptt,
4242                                  p_hwfn->rdma_prs_search_reg, 0x1);
4243                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
4244         }
4245
4246         /* Re-open incoming traffic */
4247         ecore_wr(p_hwfn, p_ptt,
4248                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
4249         ecore_ptt_release(p_hwfn, p_ptt);
4250
4251         return ECORE_SUCCESS;
4252 }
4253
4254 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
4255 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
4256 {
4257         ecore_ptt_pool_free(p_hwfn);
4258         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
4259 }
4260
4261 /* Setup bar access */
4262 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
4263 {
4264         /* clear indirect access */
4265         if (ECORE_IS_AH(p_hwfn->p_dev)) {
4266                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4267                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
4268                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4269                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
4270                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4271                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
4272                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4273                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
4274         } else {
4275                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4276                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
4277                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4278                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
4279                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4280                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
4281                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4282                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
4283         }
4284
4285         /* Clean previous pglue_b errors if such exist */
4286         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
4287
4288         /* enable internal target-read */
4289         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4290                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
4291 }
4292
4293 static void get_function_id(struct ecore_hwfn *p_hwfn)
4294 {
4295         /* ME Register */
4296         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
4297                                                   PXP_PF_ME_OPAQUE_ADDR);
4298
4299         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
4300
4301         /* Bits 16-19 from the ME registers are the pf_num */
4302         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
4303         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4304                                       PXP_CONCRETE_FID_PFID);
4305         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4306                                     PXP_CONCRETE_FID_PORT);
4307
4308         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4309                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
4310                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
4311 }
4312
4313 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
4314 {
4315         u32 *feat_num = p_hwfn->hw_info.feat_num;
4316         struct ecore_sb_cnt_info sb_cnt;
4317         u32 non_l2_sbs = 0;
4318
4319         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
4320         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
4321
4322         /* L2 Queues require each: 1 status block. 1 L2 queue */
4323         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
4324                 /* Start by allocating VF queues, then PF's */
4325                 feat_num[ECORE_VF_L2_QUE] =
4326                         OSAL_MIN_T(u32,
4327                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
4328                                    sb_cnt.iov_cnt);
4329                 feat_num[ECORE_PF_L2_QUE] =
4330                         OSAL_MIN_T(u32,
4331                                    sb_cnt.cnt - non_l2_sbs,
4332                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
4333                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
4334         }
4335
4336         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
4337             ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) {
4338                 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ?
4339                                       &feat_num[ECORE_FCOE_CQ] :
4340                                       &feat_num[ECORE_ISCSI_CQ];
4341                 u32 limit = sb_cnt.cnt;
4342
4343                 /* The number of queues should not exceed the number of FP SBs.
4344                  * In storage target, the queues are divided into pairs of a CQ
4345                  * and a CmdQ, and each pair uses a single SB. The limit in
4346                  * this case should allow a max ratio of 2:1 instead of 1:1.
4347                  */
4348                 if (p_hwfn->p_dev->b_is_target)
4349                         limit *= 2;
4350                 *p_storage_feat = OSAL_MIN_T(u32, limit,
4351                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
4352
4353                 /* @DPDK */
4354                 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init
4355                  * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2".
4356                  */
4357                 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat,
4358                                              (NUM_OF_GLOBAL_QUEUES / 2));
4359         }
4360
4361         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4362                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
4363                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
4364                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
4365                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
4366                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
4367                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
4368                    (int)sb_cnt.cnt);
4369 }
4370
4371 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
4372 {
4373         switch (res_id) {
4374         case ECORE_L2_QUEUE:
4375                 return "L2_QUEUE";
4376         case ECORE_VPORT:
4377                 return "VPORT";
4378         case ECORE_RSS_ENG:
4379                 return "RSS_ENG";
4380         case ECORE_PQ:
4381                 return "PQ";
4382         case ECORE_RL:
4383                 return "RL";
4384         case ECORE_MAC:
4385                 return "MAC";
4386         case ECORE_VLAN:
4387                 return "VLAN";
4388         case ECORE_RDMA_CNQ_RAM:
4389                 return "RDMA_CNQ_RAM";
4390         case ECORE_ILT:
4391                 return "ILT";
4392         case ECORE_LL2_QUEUE:
4393                 return "LL2_QUEUE";
4394         case ECORE_CMDQS_CQS:
4395                 return "CMDQS_CQS";
4396         case ECORE_RDMA_STATS_QUEUE:
4397                 return "RDMA_STATS_QUEUE";
4398         case ECORE_BDQ:
4399                 return "BDQ";
4400         case ECORE_SB:
4401                 return "SB";
4402         default:
4403                 return "UNKNOWN_RESOURCE";
4404         }
4405 }
4406
4407 static enum _ecore_status_t
4408 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4409                               struct ecore_ptt *p_ptt,
4410                               enum ecore_resources res_id,
4411                               u32 resc_max_val,
4412                               u32 *p_mcp_resp)
4413 {
4414         enum _ecore_status_t rc;
4415
4416         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
4417                                         resc_max_val, p_mcp_resp);
4418         if (rc != ECORE_SUCCESS) {
4419                 DP_NOTICE(p_hwfn, false,
4420                           "MFW response failure for a max value setting of resource %d [%s]\n",
4421                           res_id, ecore_hw_get_resc_name(res_id));
4422                 return rc;
4423         }
4424
4425         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
4426                 DP_INFO(p_hwfn,
4427                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
4428                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
4429
4430         return ECORE_SUCCESS;
4431 }
4432
4433 #define RDMA_NUM_STATISTIC_COUNTERS_K2                  MAX_NUM_VPORTS_K2
4434 #define RDMA_NUM_STATISTIC_COUNTERS_BB                  MAX_NUM_VPORTS_BB
4435
4436 static u32 ecore_hsi_def_val[][MAX_CHIP_IDS] = {
4437         {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
4438         {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
4439         {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
4440         {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2, },
4441         {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
4442         {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
4443         {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
4444         {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
4445         {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
4446         {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
4447         {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
4448         {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
4449         {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
4450 };
4451
4452 u32 ecore_get_hsi_def_val(struct ecore_dev *p_dev, enum ecore_hsi_def_type type)
4453 {
4454         enum chip_ids chip_id = ECORE_IS_BB(p_dev) ? CHIP_BB : CHIP_K2;
4455
4456         if (type >= ECORE_NUM_HSI_DEFS) {
4457                 DP_ERR(p_dev, "Unexpected HSI definition type [%d]\n", type);
4458                 return 0;
4459         }
4460
4461         return ecore_hsi_def_val[type][chip_id];
4462 }
4463
4464 static enum _ecore_status_t
4465 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4466                             struct ecore_ptt *p_ptt)
4467 {
4468         u32 resc_max_val, mcp_resp;
4469         u8 res_id;
4470         enum _ecore_status_t rc;
4471
4472         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4473                 /* @DPDK */
4474                 switch (res_id) {
4475                 case ECORE_LL2_QUEUE:
4476                 case ECORE_RDMA_CNQ_RAM:
4477                 case ECORE_RDMA_STATS_QUEUE:
4478                 case ECORE_BDQ:
4479                         resc_max_val = 0;
4480                         break;
4481                 default:
4482                         continue;
4483                 }
4484
4485                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
4486                                                    resc_max_val, &mcp_resp);
4487                 if (rc != ECORE_SUCCESS)
4488                         return rc;
4489
4490                 /* There's no point to continue to the next resource if the
4491                  * command is not supported by the MFW.
4492                  * We do continue if the command is supported but the resource
4493                  * is unknown to the MFW. Such a resource will be later
4494                  * configured with the default allocation values.
4495                  */
4496                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
4497                         return ECORE_NOTIMPL;
4498         }
4499
4500         return ECORE_SUCCESS;
4501 }
4502
4503 static
4504 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
4505                                             enum ecore_resources res_id,
4506                                             u32 *p_resc_num, u32 *p_resc_start)
4507 {
4508         u8 num_funcs = p_hwfn->num_funcs_on_engine;
4509         struct ecore_dev *p_dev = p_hwfn->p_dev;
4510
4511         switch (res_id) {
4512         case ECORE_L2_QUEUE:
4513                 *p_resc_num = NUM_OF_L2_QUEUES(p_dev) / num_funcs;
4514                 break;
4515         case ECORE_VPORT:
4516                 *p_resc_num = NUM_OF_VPORTS(p_dev) / num_funcs;
4517                 break;
4518         case ECORE_RSS_ENG:
4519                 *p_resc_num = NUM_OF_RSS_ENGINES(p_dev) / num_funcs;
4520                 break;
4521         case ECORE_PQ:
4522                 *p_resc_num = NUM_OF_QM_TX_QUEUES(p_dev) / num_funcs;
4523                 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
4524                 break;
4525         case ECORE_RL:
4526                 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(p_dev) / num_funcs;
4527                 break;
4528         case ECORE_MAC:
4529         case ECORE_VLAN:
4530                 /* Each VFC resource can accommodate both a MAC and a VLAN */
4531                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
4532                 break;
4533         case ECORE_ILT:
4534                 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(p_dev) / num_funcs;
4535                 break;
4536         case ECORE_LL2_QUEUE:
4537                 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
4538                 break;
4539         case ECORE_RDMA_CNQ_RAM:
4540         case ECORE_CMDQS_CQS:
4541                 /* CNQ/CMDQS are the same resource */
4542                 /* @DPDK */
4543                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
4544                 break;
4545         case ECORE_RDMA_STATS_QUEUE:
4546                 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(p_dev) / num_funcs;
4547                 break;
4548         case ECORE_BDQ:
4549                 /* @DPDK */
4550                 *p_resc_num = 0;
4551                 break;
4552         default:
4553                 break;
4554         }
4555
4556
4557         switch (res_id) {
4558         case ECORE_BDQ:
4559                 if (!*p_resc_num)
4560                         *p_resc_start = 0;
4561                 break;
4562         case ECORE_SB:
4563                 /* Since we want its value to reflect whether MFW supports
4564                  * the new scheme, have a default of 0.
4565                  */
4566                 *p_resc_num = 0;
4567                 break;
4568         default:
4569                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
4570                 break;
4571         }
4572
4573         return ECORE_SUCCESS;
4574 }
4575
4576 static enum _ecore_status_t
4577 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
4578                          bool drv_resc_alloc)
4579 {
4580         u32 dflt_resc_num = 0, dflt_resc_start = 0;
4581         u32 mcp_resp, *p_resc_num, *p_resc_start;
4582         enum _ecore_status_t rc;
4583
4584         p_resc_num = &RESC_NUM(p_hwfn, res_id);
4585         p_resc_start = &RESC_START(p_hwfn, res_id);
4586
4587         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
4588                                     &dflt_resc_start);
4589         if (rc != ECORE_SUCCESS) {
4590                 DP_ERR(p_hwfn,
4591                        "Failed to get default amount for resource %d [%s]\n",
4592                         res_id, ecore_hw_get_resc_name(res_id));
4593                 return rc;
4594         }
4595
4596 #ifndef ASIC_ONLY
4597         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
4598                 *p_resc_num = dflt_resc_num;
4599                 *p_resc_start = dflt_resc_start;
4600                 goto out;
4601         }
4602 #endif
4603
4604         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
4605                                      &mcp_resp, p_resc_num, p_resc_start);
4606         if (rc != ECORE_SUCCESS) {
4607                 DP_NOTICE(p_hwfn, true,
4608                           "MFW response failure for an allocation request for"
4609                           " resource %d [%s]\n",
4610                           res_id, ecore_hw_get_resc_name(res_id));
4611                 return rc;
4612         }
4613
4614         /* Default driver values are applied in the following cases:
4615          * - The resource allocation MB command is not supported by the MFW
4616          * - There is an internal error in the MFW while processing the request
4617          * - The resource ID is unknown to the MFW
4618          */
4619         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
4620                 DP_INFO(p_hwfn,
4621                         "Failed to receive allocation info for resource %d [%s]."
4622                         " mcp_resp = 0x%x. Applying default values"
4623                         " [%d,%d].\n",
4624                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
4625                         dflt_resc_num, dflt_resc_start);
4626
4627                 *p_resc_num = dflt_resc_num;
4628                 *p_resc_start = dflt_resc_start;
4629                 goto out;
4630         }
4631
4632         if ((*p_resc_num != dflt_resc_num ||
4633              *p_resc_start != dflt_resc_start) &&
4634             res_id != ECORE_SB) {
4635                 DP_INFO(p_hwfn,
4636                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
4637                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
4638                         *p_resc_start, dflt_resc_num, dflt_resc_start,
4639                         drv_resc_alloc ? " - Applying default values" : "");
4640                 if (drv_resc_alloc) {
4641                         *p_resc_num = dflt_resc_num;
4642                         *p_resc_start = dflt_resc_start;
4643                 }
4644         }
4645 out:
4646         return ECORE_SUCCESS;
4647 }
4648
4649 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
4650                                                    bool drv_resc_alloc)
4651 {
4652         enum _ecore_status_t rc;
4653         u8 res_id;
4654
4655         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4656                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
4657                 if (rc != ECORE_SUCCESS)
4658                         return rc;
4659         }
4660
4661         return ECORE_SUCCESS;
4662 }
4663
4664 #define ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS 0xaa
4665 #define ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS 0x55
4666 #define ECORE_NONUSED_PPFID_MASK_AH_4P          0xf0
4667
4668 static enum _ecore_status_t ecore_hw_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,
4669                                                       struct ecore_ptt *p_ptt)
4670 {
4671         u8 native_ppfid_idx = ECORE_PPFID_BY_PFID(p_hwfn), new_bitmap;
4672         struct ecore_dev *p_dev = p_hwfn->p_dev;
4673         enum _ecore_status_t rc;
4674
4675         rc = ecore_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
4676         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL)
4677                 return rc;
4678         else if (rc == ECORE_NOTIMPL)
4679                 p_dev->ppfid_bitmap = 0x1 << native_ppfid_idx;
4680
4681         /* 4-ports mode has limitations that should be enforced:
4682          * - BB: the MFW can access only PPFIDs which their corresponding PFIDs
4683          *       belong to this certain port.
4684          * - AH: only 4 PPFIDs per port are available.
4685          */
4686         if (ecore_device_num_ports(p_dev) == 4) {
4687                 u8 mask;
4688
4689                 if (ECORE_IS_BB(p_dev))
4690                         mask = MFW_PORT(p_hwfn) > 1 ?
4691                                ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS :
4692                                ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS;
4693                 else
4694                         mask = ECORE_NONUSED_PPFID_MASK_AH_4P;
4695
4696                 if (p_dev->ppfid_bitmap & mask) {
4697                         new_bitmap = p_dev->ppfid_bitmap & ~mask;
4698                         DP_INFO(p_hwfn,
4699                                 "Fix the PPFID bitmap for 4-ports mode: 0x%hhx -> 0x%hhx\n",
4700                                 p_dev->ppfid_bitmap, new_bitmap);
4701                         p_dev->ppfid_bitmap = new_bitmap;
4702                 }
4703         }
4704
4705         /* The native PPFID is expected to be part of the allocated bitmap */
4706         if (!(p_dev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
4707                 new_bitmap = 0x1 << native_ppfid_idx;
4708                 DP_INFO(p_hwfn,
4709                         "Fix the PPFID bitmap to inculde the native PPFID: %hhd -> 0x%hhx\n",
4710                         p_dev->ppfid_bitmap, new_bitmap);
4711                 p_dev->ppfid_bitmap = new_bitmap;
4712         }
4713
4714         return ECORE_SUCCESS;
4715 }
4716
4717 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
4718                                               struct ecore_ptt *p_ptt,
4719                                               bool drv_resc_alloc)
4720 {
4721         struct ecore_resc_unlock_params resc_unlock_params;
4722         struct ecore_resc_lock_params resc_lock_params;
4723         struct ecore_dev *p_dev = p_hwfn->p_dev;
4724         u32 max_ilt_lines;
4725         u8 res_id;
4726         enum _ecore_status_t rc;
4727 #ifndef ASIC_ONLY
4728         u32 *resc_start = p_hwfn->hw_info.resc_start;
4729         u32 *resc_num = p_hwfn->hw_info.resc_num;
4730         /* For AH, an equal share of the ILT lines between the maximal number of
4731          * PFs is not enough for RoCE. This would be solved by the future
4732          * resource allocation scheme, but isn't currently present for
4733          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
4734          * to work - the BB number of ILT lines divided by its max PFs number.
4735          */
4736         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
4737 #endif
4738
4739         /* Setting the max values of the soft resources and the following
4740          * resources allocation queries should be atomic. Since several PFs can
4741          * run in parallel - a resource lock is needed.
4742          * If either the resource lock or resource set value commands are not
4743          * supported - skip the max values setting, release the lock if
4744          * needed, and proceed to the queries. Other failures, including a
4745          * failure to acquire the lock, will cause this function to fail.
4746          * Old drivers that don't acquire the lock can run in parallel, and
4747          * their allocation values won't be affected by the updated max values.
4748          */
4749         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
4750                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
4751
4752         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
4753         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4754                 return rc;
4755         } else if (rc == ECORE_NOTIMPL) {
4756                 DP_INFO(p_hwfn,
4757                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
4758         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
4759                 DP_NOTICE(p_hwfn, false,
4760                           "Failed to acquire the resource lock for the resource allocation commands\n");
4761                 rc = ECORE_BUSY;
4762                 goto unlock_and_exit;
4763         } else {
4764                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
4765                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4766                         DP_NOTICE(p_hwfn, false,
4767                                   "Failed to set the max values of the soft resources\n");
4768                         goto unlock_and_exit;
4769                 } else if (rc == ECORE_NOTIMPL) {
4770                         DP_INFO(p_hwfn,
4771                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
4772                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4773                                                    &resc_unlock_params);
4774                         if (rc != ECORE_SUCCESS)
4775                                 DP_INFO(p_hwfn,
4776                                         "Failed to release the resource lock for the resource allocation commands\n");
4777                 }
4778         }
4779
4780         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
4781         if (rc != ECORE_SUCCESS)
4782                 goto unlock_and_exit;
4783
4784         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
4785                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4786                                            &resc_unlock_params);
4787                 if (rc != ECORE_SUCCESS)
4788                         DP_INFO(p_hwfn,
4789                                 "Failed to release the resource lock for the resource allocation commands\n");
4790         }
4791
4792         /* PPFID bitmap */
4793         if (IS_LEAD_HWFN(p_hwfn)) {
4794                 rc = ecore_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
4795                 if (rc != ECORE_SUCCESS)
4796                         return rc;
4797         }
4798
4799 #ifndef ASIC_ONLY
4800         if (CHIP_REV_IS_EMUL(p_dev)) {
4801                 /* Reduced build contains less PQs */
4802                 if (!(p_dev->b_is_emul_full)) {
4803                         resc_num[ECORE_PQ] = 32;
4804                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
4805                             p_hwfn->enabled_func_idx;
4806                 }
4807
4808                 /* For AH emulation, since we have a possible maximal number of
4809                  * 16 enabled PFs, in case there are not enough ILT lines -
4810                  * allocate only first PF as RoCE and have all the other as
4811                  * ETH-only with less ILT lines.
4812                  * In case we increase the number of ILT lines for PF0, we need
4813                  * also to correct the start value for PF1-15.
4814                  */
4815                 if (ECORE_IS_AH(p_dev) && p_dev->b_is_emul_full) {
4816                         if (!p_hwfn->rel_pf_id) {
4817                                 resc_num[ECORE_ILT] =
4818                                         OSAL_MAX_T(u32, resc_num[ECORE_ILT],
4819                                                          roce_min_ilt_lines);
4820                         } else if (resc_num[ECORE_ILT] < roce_min_ilt_lines) {
4821                                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
4822                                                          resc_num[ECORE_ILT];
4823                         }
4824                 }
4825         }
4826 #endif
4827
4828         /* Sanity for ILT */
4829         max_ilt_lines = NUM_OF_PXP_ILT_RECORDS(p_dev);
4830         if (RESC_END(p_hwfn, ECORE_ILT) > max_ilt_lines) {
4831                 DP_NOTICE(p_hwfn, true,
4832                           "Can't assign ILT pages [%08x,...,%08x]\n",
4833                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
4834                                                                   ECORE_ILT) -
4835                           1);
4836                 return ECORE_INVAL;
4837         }
4838
4839         /* This will also learn the number of SBs from MFW */
4840         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
4841                 return ECORE_INVAL;
4842
4843         ecore_hw_set_feat(p_hwfn);
4844
4845         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4846                    "The numbers for each resource are:\n");
4847         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
4848                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
4849                            ecore_hw_get_resc_name(res_id),
4850                            RESC_NUM(p_hwfn, res_id),
4851                            RESC_START(p_hwfn, res_id));
4852
4853         return ECORE_SUCCESS;
4854
4855 unlock_and_exit:
4856         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
4857                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4858                                       &resc_unlock_params);
4859         return rc;
4860 }
4861
4862 #ifndef ASIC_ONLY
4863 static enum _ecore_status_t
4864 ecore_emul_hw_get_nvm_info(struct ecore_hwfn *p_hwfn)
4865 {
4866         if (IS_LEAD_HWFN(p_hwfn)) {
4867                 struct ecore_dev *p_dev = p_hwfn->p_dev;
4868
4869                 /* The MF mode on emulation is either default or NPAR 1.0 */
4870                 p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
4871                                  1 << ECORE_MF_LLH_PROTO_CLSS |
4872                                  1 << ECORE_MF_LL2_NON_UNICAST;
4873                 if (p_hwfn->num_funcs_on_port > 1)
4874                         p_dev->mf_bits |= 1 << ECORE_MF_INTER_PF_SWITCH |
4875                                           1 << ECORE_MF_DISABLE_ARFS;
4876                 else
4877                         p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
4878         }
4879
4880         return ECORE_SUCCESS;
4881 }
4882 #endif
4883
4884 static enum _ecore_status_t
4885 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
4886                       struct ecore_ptt *p_ptt,
4887                       struct ecore_hw_prepare_params *p_params)
4888 {
4889         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
4890         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
4891         struct ecore_mcp_link_capabilities *p_caps;
4892         struct ecore_mcp_link_params *link;
4893         enum _ecore_status_t rc;
4894
4895 #ifndef ASIC_ONLY
4896         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
4897                 return ecore_emul_hw_get_nvm_info(p_hwfn);
4898 #endif
4899
4900         /* Read global nvm_cfg address */
4901         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
4902
4903         /* Verify MCP has initialized it */
4904         if (!nvm_cfg_addr) {
4905                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
4906                 if (p_params->b_relaxed_probe)
4907                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
4908                 return ECORE_INVAL;
4909         }
4910
4911 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
4912
4913         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4914
4915         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4916                    OFFSETOF(struct nvm_cfg1, glob) +
4917                    OFFSETOF(struct nvm_cfg1_glob, core_cfg);
4918
4919         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
4920
4921         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4922                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4923         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4924                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
4925                 break;
4926         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4927                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
4928                 break;
4929         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4930                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
4931                 break;
4932         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4933                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
4934                 break;
4935         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4936                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
4937                 break;
4938         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4939                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
4940                 break;
4941         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4942                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
4943                 break;
4944         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4945                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
4946                 break;
4947         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4948                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
4949                 break;
4950         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4951                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
4952                 break;
4953         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4954                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
4955                 break;
4956         default:
4957                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
4958                           core_cfg);
4959                 break;
4960         }
4961
4962         /* Read DCBX configuration */
4963         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4964                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4965         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
4966                              port_cfg_addr +
4967                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
4968         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
4969                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
4970         switch (dcbx_mode) {
4971         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
4972                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
4973                 break;
4974         case NVM_CFG1_PORT_DCBX_MODE_CEE:
4975                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
4976                 break;
4977         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
4978                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
4979                 break;
4980         default:
4981                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
4982         }
4983
4984         /* Read default link configuration */
4985         link = &p_hwfn->mcp_info->link_input;
4986         p_caps = &p_hwfn->mcp_info->link_capabilities;
4987         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4988             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4989         link_temp = ecore_rd(p_hwfn, p_ptt,
4990                              port_cfg_addr +
4991                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
4992         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4993         link->speed.advertised_speeds = link_temp;
4994         p_caps->speed_capabilities = link->speed.advertised_speeds;
4995
4996         link_temp = ecore_rd(p_hwfn, p_ptt,
4997                                  port_cfg_addr +
4998                                  OFFSETOF(struct nvm_cfg1_port, link_settings));
4999         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
5000                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
5001         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
5002                 link->speed.autoneg = true;
5003                 break;
5004         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
5005                 link->speed.forced_speed = 1000;
5006                 break;
5007         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
5008                 link->speed.forced_speed = 10000;
5009                 break;
5010         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
5011                 link->speed.forced_speed = 25000;
5012                 break;
5013         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
5014                 link->speed.forced_speed = 40000;
5015                 break;
5016         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
5017                 link->speed.forced_speed = 50000;
5018                 break;
5019         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
5020                 link->speed.forced_speed = 100000;
5021                 break;
5022         default:
5023                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
5024         }
5025
5026         p_caps->default_speed = link->speed.forced_speed;
5027         p_caps->default_speed_autoneg = link->speed.autoneg;
5028
5029         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
5030         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
5031         link->pause.autoneg = !!(link_temp &
5032                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
5033         link->pause.forced_rx = !!(link_temp &
5034                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
5035         link->pause.forced_tx = !!(link_temp &
5036                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
5037         link->loopback_mode = 0;
5038
5039         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
5040                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
5041                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
5042                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
5043                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
5044                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
5045                 link->eee.enable = true;
5046                 switch (link_temp) {
5047                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
5048                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
5049                         link->eee.enable = false;
5050                         break;
5051                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
5052                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
5053                         break;
5054                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
5055                         p_caps->eee_lpi_timer =
5056                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
5057                         break;
5058                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
5059                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
5060                         break;
5061                 }
5062
5063                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
5064                 link->eee.tx_lpi_enable = link->eee.enable;
5065                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
5066         } else {
5067                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
5068         }
5069
5070         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5071                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
5072                    link->speed.forced_speed, link->speed.advertised_speeds,
5073                    link->speed.autoneg, link->pause.autoneg,
5074                    p_caps->default_eee, p_caps->eee_lpi_timer);
5075
5076         /* Read Multi-function information from shmem */
5077         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5078                    OFFSETOF(struct nvm_cfg1, glob) +
5079                    OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
5080
5081         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
5082
5083         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
5084             NVM_CFG1_GLOB_MF_MODE_OFFSET;
5085
5086         switch (mf_mode) {
5087         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5088                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
5089                 break;
5090         case NVM_CFG1_GLOB_MF_MODE_UFP:
5091                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
5092                                          1 << ECORE_MF_UFP_SPECIFIC |
5093                                          1 << ECORE_MF_8021Q_TAGGING;
5094                 break;
5095         case NVM_CFG1_GLOB_MF_MODE_BD:
5096                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
5097                                          1 << ECORE_MF_LLH_PROTO_CLSS |
5098                                          1 << ECORE_MF_8021AD_TAGGING |
5099                                          1 << ECORE_MF_FIP_SPECIAL;
5100                 break;
5101         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5102                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
5103                                          1 << ECORE_MF_LLH_PROTO_CLSS |
5104                                          1 << ECORE_MF_LL2_NON_UNICAST |
5105                                          1 << ECORE_MF_INTER_PF_SWITCH |
5106                                          1 << ECORE_MF_DISABLE_ARFS;
5107                 break;
5108         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5109                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
5110                                          1 << ECORE_MF_LLH_PROTO_CLSS |
5111                                          1 << ECORE_MF_LL2_NON_UNICAST;
5112                 if (ECORE_IS_BB(p_hwfn->p_dev))
5113                         p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
5114                 break;
5115         }
5116         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
5117                 p_hwfn->p_dev->mf_bits);
5118
5119         if (ECORE_IS_CMT(p_hwfn->p_dev))
5120                 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
5121
5122         /* It's funny since we have another switch, but it's easier
5123          * to throw this away in linux this way. Long term, it might be
5124          * better to have have getters for needed ECORE_MF_* fields,
5125          * convert client code and eliminate this.
5126          */
5127         switch (mf_mode) {
5128         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5129         case NVM_CFG1_GLOB_MF_MODE_BD:
5130                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
5131                 break;
5132         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5133                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
5134                 break;
5135         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5136                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
5137                 break;
5138         case NVM_CFG1_GLOB_MF_MODE_UFP:
5139                 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
5140                 break;
5141         }
5142
5143         /* Read Multi-function information from shmem */
5144         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5145                    OFFSETOF(struct nvm_cfg1, glob) +
5146                    OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
5147
5148         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
5149         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
5150                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
5151                                 &p_hwfn->hw_info.device_capabilities);
5152         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
5153                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
5154                                 &p_hwfn->hw_info.device_capabilities);
5155         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
5156                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
5157                                 &p_hwfn->hw_info.device_capabilities);
5158         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
5159                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
5160                                 &p_hwfn->hw_info.device_capabilities);
5161         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
5162                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
5163                                 &p_hwfn->hw_info.device_capabilities);
5164
5165         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
5166         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5167                 rc = ECORE_SUCCESS;
5168                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5169         }
5170
5171         return rc;
5172 }
5173
5174 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
5175                                 struct ecore_ptt *p_ptt)
5176 {
5177         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
5178         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
5179         struct ecore_dev *p_dev = p_hwfn->p_dev;
5180
5181         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
5182
5183         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
5184          * in the other bits are selected.
5185          * Bits 1-15 are for functions 1-15, respectively, and their value is
5186          * '0' only for enabled functions (function 0 always exists and
5187          * enabled).
5188          * In case of CMT in BB, only the "even" functions are enabled, and thus
5189          * the number of functions for both hwfns is learnt from the same bits.
5190          */
5191         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
5192                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
5193                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
5194         } else { /* E5 */
5195                 reg_function_hide = 0;
5196         }
5197
5198         if (reg_function_hide & 0x1) {
5199                 if (ECORE_IS_BB(p_dev)) {
5200                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
5201                                 num_funcs = 0;
5202                                 eng_mask = 0xaaaa;
5203                         } else {
5204                                 num_funcs = 1;
5205                                 eng_mask = 0x5554;
5206                         }
5207                 } else {
5208                         num_funcs = 1;
5209                         eng_mask = 0xfffe;
5210                 }
5211
5212                 /* Get the number of the enabled functions on the engine */
5213                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
5214                 while (tmp) {
5215                         if (tmp & 0x1)
5216                                 num_funcs++;
5217                         tmp >>= 0x1;
5218                 }
5219
5220                 /* Get the PF index within the enabled functions */
5221                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
5222                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
5223                 while (tmp) {
5224                         if (tmp & 0x1)
5225                                 enabled_func_idx--;
5226                         tmp >>= 0x1;
5227                 }
5228         }
5229
5230         p_hwfn->num_funcs_on_engine = num_funcs;
5231         p_hwfn->enabled_func_idx = enabled_func_idx;
5232
5233 #ifndef ASIC_ONLY
5234         if (CHIP_REV_IS_FPGA(p_dev)) {
5235                 DP_NOTICE(p_hwfn, false,
5236                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
5237                 p_hwfn->num_funcs_on_engine = 4;
5238         }
5239 #endif
5240
5241         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
5242                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
5243                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
5244                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
5245 }
5246
5247 #ifndef ASIC_ONLY
5248 static void ecore_emul_hw_info_port_num(struct ecore_hwfn *p_hwfn,
5249                                          struct ecore_ptt *p_ptt)
5250 {
5251         struct ecore_dev *p_dev = p_hwfn->p_dev;
5252         u32 eco_reserved;
5253
5254         /* MISCS_REG_ECO_RESERVED[15:12]: num of ports in an engine */
5255         eco_reserved = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5256         switch ((eco_reserved & 0xf000) >> 12) {
5257                 case 1:
5258                         p_dev->num_ports_in_engine = 1;
5259                         break;
5260                 case 3:
5261                         p_dev->num_ports_in_engine = 2;
5262                         break;
5263                 case 0xf:
5264                         p_dev->num_ports_in_engine = 4;
5265                         break;
5266                 default:
5267                         DP_NOTICE(p_hwfn, false,
5268                           "Emulation: Unknown port mode [ECO_RESERVED 0x%08x]\n",
5269                           eco_reserved);
5270                 p_dev->num_ports_in_engine = 1; /* Default to something */
5271                 break;
5272                 }
5273
5274         p_dev->num_ports = p_dev->num_ports_in_engine *
5275                            ecore_device_num_engines(p_dev);
5276 }
5277 #endif
5278
5279 /* Determine the number of ports of the device and per engine */
5280 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
5281                                    struct ecore_ptt *p_ptt)
5282 {
5283         u32 addr, global_offsize, global_addr, port_mode;
5284         struct ecore_dev *p_dev = p_hwfn->p_dev;
5285
5286 #ifndef ASIC_ONLY
5287         if (CHIP_REV_IS_TEDIBEAR(p_dev)) {
5288                 p_dev->num_ports_in_engine = 1;
5289                 p_dev->num_ports = 2;
5290                 return;
5291         }
5292
5293         if (CHIP_REV_IS_EMUL(p_dev)) {
5294                 ecore_emul_hw_info_port_num(p_hwfn, p_ptt);
5295                 return;
5296         }
5297 #endif
5298
5299                 /* In CMT there is always only one port */
5300         if (ECORE_IS_CMT(p_dev)) {
5301                 p_dev->num_ports_in_engine = 1;
5302                 p_dev->num_ports = 1;
5303                 return;
5304         }
5305
5306         /* Determine the number of ports per engine */
5307         port_mode = ecore_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
5308         switch (port_mode) {
5309         case 0x0:
5310                 p_dev->num_ports_in_engine = 1;
5311                 break;
5312         case 0x1:
5313                 p_dev->num_ports_in_engine = 2;
5314                 break;
5315         case 0x2:
5316                 p_dev->num_ports_in_engine = 4;
5317                 break;
5318         default:
5319                 DP_NOTICE(p_hwfn, false, "Unknown port mode 0x%08x\n",
5320                           port_mode);
5321                 p_dev->num_ports_in_engine = 1; /* Default to something */
5322                 break;
5323         }
5324
5325         /* Get the total number of ports of the device */
5326         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
5327                                     PUBLIC_GLOBAL);
5328         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
5329         global_addr = SECTION_ADDR(global_offsize, 0);
5330         addr = global_addr + OFFSETOF(struct public_global, max_ports);
5331         p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
5332 }
5333
5334 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
5335                                    struct ecore_ptt *p_ptt)
5336 {
5337         struct ecore_mcp_link_capabilities *p_caps;
5338         u32 eee_status;
5339
5340         p_caps = &p_hwfn->mcp_info->link_capabilities;
5341         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
5342                 return;
5343
5344         p_caps->eee_speed_caps = 0;
5345         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
5346                               OFFSETOF(struct public_port, eee_status));
5347         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
5348                         EEE_SUPPORTED_SPEED_OFFSET;
5349         if (eee_status & EEE_1G_SUPPORTED)
5350                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
5351         if (eee_status & EEE_10G_ADV)
5352                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
5353 }
5354
5355 static enum _ecore_status_t
5356 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
5357                   enum ecore_pci_personality personality,
5358                   struct ecore_hw_prepare_params *p_params)
5359 {
5360         bool drv_resc_alloc = p_params->drv_resc_alloc;
5361         enum _ecore_status_t rc;
5362
5363         if (IS_ECORE_PACING(p_hwfn)) {
5364                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
5365                            "Skipping IOV as packet pacing is requested\n");
5366         }
5367
5368         /* Since all information is common, only first hwfns should do this */
5369         if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
5370                 rc = ecore_iov_hw_info(p_hwfn);
5371                 if (rc != ECORE_SUCCESS) {
5372                         if (p_params->b_relaxed_probe)
5373                                 p_params->p_relaxed_res =
5374                                                 ECORE_HW_PREPARE_BAD_IOV;
5375                         else
5376                                 return rc;
5377                 }
5378         }
5379
5380         if (IS_LEAD_HWFN(p_hwfn))
5381                 ecore_hw_info_port_num(p_hwfn, p_ptt);
5382
5383         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
5384
5385         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
5386         if (rc != ECORE_SUCCESS)
5387                 return rc;
5388
5389         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
5390         if (rc != ECORE_SUCCESS) {
5391                 if (p_params->b_relaxed_probe)
5392                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
5393                 else
5394                         return rc;
5395         }
5396
5397 #ifndef ASIC_ONLY
5398         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
5399 #endif
5400                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
5401                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
5402 #ifndef ASIC_ONLY
5403         } else {
5404                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
5405
5406                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
5407                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
5408         }
5409 #endif
5410
5411         if (ecore_mcp_is_init(p_hwfn)) {
5412                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
5413                         p_hwfn->hw_info.ovlan =
5414                             p_hwfn->mcp_info->func_info.ovlan;
5415
5416                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
5417
5418                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
5419
5420                 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
5421         }
5422
5423         if (personality != ECORE_PCI_DEFAULT) {
5424                 p_hwfn->hw_info.personality = personality;
5425         } else if (ecore_mcp_is_init(p_hwfn)) {
5426                 enum ecore_pci_personality protocol;
5427
5428                 protocol = p_hwfn->mcp_info->func_info.protocol;
5429                 p_hwfn->hw_info.personality = protocol;
5430         }
5431 #ifndef ASIC_ONLY
5432         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
5433                 /* AH emulation:
5434                  * Allow only PF0 to be RoCE to overcome a lack of ILT lines.
5435          */
5436                 if (ECORE_IS_AH(p_hwfn->p_dev) && p_hwfn->rel_pf_id)
5437                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
5438                 else
5439                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
5440         }
5441 #endif
5442
5443         /* although in BB some constellations may support more than 4 tcs,
5444          * that can result in performance penalty in some cases. 4
5445          * represents a good tradeoff between performance and flexibility.
5446          */
5447         if (IS_ECORE_PACING(p_hwfn))
5448                 p_hwfn->hw_info.num_hw_tc = 1;
5449         else
5450                 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
5451
5452         /* start out with a single active tc. This can be increased either
5453          * by dcbx negotiation or by upper layer driver
5454          */
5455         p_hwfn->hw_info.num_active_tc = 1;
5456
5457         ecore_get_num_funcs(p_hwfn, p_ptt);
5458
5459         if (ecore_mcp_is_init(p_hwfn))
5460                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
5461
5462         /* In case of forcing the driver's default resource allocation, calling
5463          * ecore_hw_get_resc() should come after initializing the personality
5464          * and after getting the number of functions, since the calculation of
5465          * the resources/features depends on them.
5466          * This order is not harmful if not forcing.
5467          */
5468         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
5469         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5470                 rc = ECORE_SUCCESS;
5471                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5472         }
5473
5474         return rc;
5475 }
5476
5477 #define ECORE_MAX_DEVICE_NAME_LEN (8)
5478
5479 void ecore_get_dev_name(struct ecore_dev *p_dev, u8 *name, u8 max_chars)
5480 {
5481         u8 n;
5482
5483         n = OSAL_MIN_T(u8, max_chars, ECORE_MAX_DEVICE_NAME_LEN);
5484         OSAL_SNPRINTF((char *)name, n, "%s %c%d",
5485                       ECORE_IS_BB(p_dev) ? "BB" : "AH",
5486                       'A' + p_dev->chip_rev, (int)p_dev->chip_metal);
5487 }
5488
5489 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
5490                                                struct ecore_ptt *p_ptt)
5491 {
5492         struct ecore_dev *p_dev = p_hwfn->p_dev;
5493         u16 device_id_mask;
5494         u32 tmp;
5495
5496         /* Read Vendor Id / Device Id */
5497         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
5498                                   &p_dev->vendor_id);
5499         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
5500                                   &p_dev->device_id);
5501
5502         /* Determine type */
5503         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
5504         switch (device_id_mask) {
5505         case ECORE_DEV_ID_MASK_BB:
5506                 p_dev->type = ECORE_DEV_TYPE_BB;
5507                 break;
5508         case ECORE_DEV_ID_MASK_AH:
5509                 p_dev->type = ECORE_DEV_TYPE_AH;
5510                 break;
5511         default:
5512                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
5513                           p_dev->device_id);
5514                 return ECORE_ABORTED;
5515         }
5516
5517         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
5518         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
5519         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
5520         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
5521
5522         /* Learn number of HW-functions */
5523         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
5524
5525         if (tmp & (1 << p_hwfn->rel_pf_id)) {
5526                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
5527                 p_dev->num_hwfns = 2;
5528         } else {
5529                 p_dev->num_hwfns = 1;
5530         }
5531
5532 #ifndef ASIC_ONLY
5533         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_BB(p_dev)) {
5534                 /* For some reason we have problems with this register
5535                  * in BB B0 emulation; Simply assume no CMT
5536                  */
5537                 DP_NOTICE(p_dev->hwfns, false,
5538                           "device on emul - assume no CMT\n");
5539                 p_dev->num_hwfns = 1;
5540         }
5541 #endif
5542
5543         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
5544         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
5545         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
5546         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
5547
5548         DP_INFO(p_dev->hwfns,
5549                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
5550                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
5551                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
5552                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
5553                 p_dev->chip_metal);
5554
5555         if (ECORE_IS_BB_A0(p_dev)) {
5556                 DP_NOTICE(p_dev->hwfns, false,
5557                           "The chip type/rev (BB A0) is not supported!\n");
5558                 return ECORE_ABORTED;
5559         }
5560 #ifndef ASIC_ONLY
5561         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
5562                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
5563
5564         if (CHIP_REV_IS_EMUL(p_dev)) {
5565                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5566
5567                 /* MISCS_REG_ECO_RESERVED[29]: full/reduced emulation build */
5568                 p_dev->b_is_emul_full = !!(tmp & (1 << 29));
5569
5570                 /* MISCS_REG_ECO_RESERVED[28]: emulation build w/ or w/o MAC */
5571                 p_dev->b_is_emul_mac = !!(tmp & (1 << 28));
5572
5573                         DP_NOTICE(p_hwfn, false,
5574                           "Emulation: Running on a %s build %s MAC\n",
5575                           p_dev->b_is_emul_full ? "full" : "reduced",
5576                           p_dev->b_is_emul_mac ? "with" : "without");
5577         }
5578 #endif
5579
5580         return ECORE_SUCCESS;
5581 }
5582
5583 #ifndef LINUX_REMOVE
5584 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
5585 {
5586         int j;
5587
5588         if (IS_VF(p_dev))
5589                 return;
5590
5591         for_each_hwfn(p_dev, j) {
5592                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
5593
5594                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
5595                            "Mark hw/fw uninitialized\n");
5596
5597                 p_hwfn->hw_init_done = false;
5598
5599                 ecore_ptt_invalidate(p_hwfn);
5600         }
5601 }
5602 #endif
5603
5604 static enum _ecore_status_t
5605 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
5606                         void OSAL_IOMEM *p_doorbells, u64 db_phys_addr,
5607                         struct ecore_hw_prepare_params *p_params)
5608 {
5609         struct ecore_mdump_retain_data mdump_retain;
5610         struct ecore_dev *p_dev = p_hwfn->p_dev;
5611         struct ecore_mdump_info mdump_info;
5612         enum _ecore_status_t rc = ECORE_SUCCESS;
5613
5614         /* Split PCI bars evenly between hwfns */
5615         p_hwfn->regview = p_regview;
5616         p_hwfn->doorbells = p_doorbells;
5617         p_hwfn->db_phys_addr = db_phys_addr;
5618
5619         if (IS_VF(p_dev))
5620                 return ecore_vf_hw_prepare(p_hwfn);
5621
5622         /* Validate that chip access is feasible */
5623         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
5624                 DP_ERR(p_hwfn,
5625                        "Reading the ME register returns all Fs; Preventing further chip access\n");
5626                 if (p_params->b_relaxed_probe)
5627                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
5628                 return ECORE_INVAL;
5629         }
5630
5631         get_function_id(p_hwfn);
5632
5633         /* Allocate PTT pool */
5634         rc = ecore_ptt_pool_alloc(p_hwfn);
5635         if (rc) {
5636                 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
5637                 if (p_params->b_relaxed_probe)
5638                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5639                 goto err0;
5640         }
5641
5642         /* Allocate the main PTT */
5643         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
5644
5645         /* First hwfn learns basic information, e.g., number of hwfns */
5646         if (IS_LEAD_HWFN(p_hwfn)) {
5647                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
5648                 if (rc != ECORE_SUCCESS) {
5649                         if (p_params->b_relaxed_probe)
5650                                 p_params->p_relaxed_res =
5651                                         ECORE_HW_PREPARE_FAILED_DEV;
5652                         goto err1;
5653                 }
5654         }
5655
5656 #ifndef ASIC_ONLY
5657         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) && !b_ptt_gtt_init) {
5658                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
5659                 u32 val;
5660
5661                 /* Initialize PTT/GTT (done by MFW on ASIC) */
5662                 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_START_INIT_PTT_GTT, 1);
5663                 OSAL_MSLEEP(10);
5664                 ecore_ptt_invalidate(p_hwfn);
5665                 val = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_INIT_DONE_PTT_GTT);
5666                 if (val != 1) {
5667                         DP_ERR(p_hwfn,
5668                                "PTT and GTT init in PGLUE_B didn't complete\n");
5669                         goto err1;
5670                 }
5671
5672                 /* Clear a possible PGLUE_B parity from a previous GRC access */
5673                 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_PRTY_STS_WR_H_0, 0x380);
5674
5675                 b_ptt_gtt_init = true;
5676         }
5677 #endif
5678
5679         /* Store the precompiled init data ptrs */
5680         if (IS_LEAD_HWFN(p_hwfn))
5681                 ecore_init_iro_array(p_hwfn->p_dev);
5682
5683         ecore_hw_hwfn_prepare(p_hwfn);
5684
5685         /* Initialize MCP structure */
5686         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
5687         if (rc) {
5688                 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
5689                 if (p_params->b_relaxed_probe)
5690                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5691                 goto err1;
5692         }
5693
5694         /* Read the device configuration information from the HW and SHMEM */
5695         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
5696                                p_params->personality, p_params);
5697         if (rc) {
5698                 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
5699                 goto err2;
5700         }
5701
5702         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
5703          * called, since among others it sets the ports number in an engine.
5704          */
5705         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
5706             !p_dev->recov_in_prog) {
5707                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
5708                 if (rc != ECORE_SUCCESS)
5709                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
5710
5711                 /* Workaround for MFW issue where PF FLR does not cleanup
5712                  * IGU block
5713                  */
5714                 if (!(p_hwfn->mcp_info->capabilities &
5715                       FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
5716                         ecore_pf_flr_igu_cleanup(p_hwfn);
5717         }
5718
5719         /* Check if mdump logs/data are present and update the epoch value */
5720         if (IS_LEAD_HWFN(p_hwfn)) {
5721                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
5722                                               &mdump_info);
5723                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
5724                         DP_NOTICE(p_hwfn, false,
5725                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
5726
5727                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
5728                                                 &mdump_retain);
5729                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
5730                         DP_NOTICE(p_hwfn, false,
5731                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
5732                                   mdump_retain.epoch, mdump_retain.pf,
5733                                   mdump_retain.status);
5734
5735                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
5736                                            p_params->epoch);
5737         }
5738
5739         /* Allocate the init RT array and initialize the init-ops engine */
5740         rc = ecore_init_alloc(p_hwfn);
5741         if (rc) {
5742                 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
5743                 if (p_params->b_relaxed_probe)
5744                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5745                 goto err2;
5746         }
5747 #ifndef ASIC_ONLY
5748         if (CHIP_REV_IS_FPGA(p_dev)) {
5749                 if (ECORE_IS_AH(p_dev)) {
5750                         DP_NOTICE(p_hwfn, false,
5751                                   "FPGA: workaround; Prevent DMAE parities\n");
5752                         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
5753                                  PCIE_REG_PRTY_MASK_K2, 7);
5754                 }
5755
5756                 DP_NOTICE(p_hwfn, false,
5757                           "FPGA: workaround: Set VF bar0 size\n");
5758                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
5759                          PGLUE_B_REG_VF_BAR0_SIZE_K2, 4);
5760         }
5761 #endif
5762
5763         return rc;
5764 err2:
5765         if (IS_LEAD_HWFN(p_hwfn))
5766                 ecore_iov_free_hw_info(p_dev);
5767         ecore_mcp_free(p_hwfn);
5768 err1:
5769         ecore_hw_hwfn_free(p_hwfn);
5770 err0:
5771         return rc;
5772 }
5773
5774 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
5775                                       struct ecore_hw_prepare_params *p_params)
5776 {
5777         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5778         enum _ecore_status_t rc;
5779
5780         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
5781         p_dev->allow_mdump = p_params->allow_mdump;
5782         p_hwfn->b_en_pacing = p_params->b_en_pacing;
5783         p_dev->b_is_target = p_params->b_is_target;
5784
5785         if (p_params->b_relaxed_probe)
5786                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
5787
5788         /* Initialize the first hwfn - will learn number of hwfns */
5789         rc = ecore_hw_prepare_single(p_hwfn, p_dev->regview,
5790                                      p_dev->doorbells, p_dev->db_phys_addr,
5791                                      p_params);
5792         if (rc != ECORE_SUCCESS)
5793                 return rc;
5794
5795         p_params->personality = p_hwfn->hw_info.personality;
5796
5797         /* Initialize 2nd hwfn if necessary */
5798         if (ECORE_IS_CMT(p_dev)) {
5799                 void OSAL_IOMEM *p_regview, *p_doorbell;
5800                 u8 OSAL_IOMEM *addr;
5801                 u64 db_phys_addr;
5802                 u32 offset;
5803
5804                 /* adjust bar offset for second engine */
5805                 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5806                                            BAR_ID_0) / 2;
5807                 addr = (u8 OSAL_IOMEM *)p_dev->regview + offset;
5808                 p_regview = (void OSAL_IOMEM *)addr;
5809
5810                 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5811                                            BAR_ID_1) / 2;
5812                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + offset;
5813                 p_doorbell = (void OSAL_IOMEM *)addr;
5814                 db_phys_addr = p_dev->db_phys_addr + offset;
5815
5816                 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
5817                 /* prepare second hw function */
5818                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
5819                                              p_doorbell, db_phys_addr,
5820                                              p_params);
5821
5822                 /* in case of error, need to free the previously
5823                  * initiliazed hwfn 0.
5824                  */
5825                 if (rc != ECORE_SUCCESS) {
5826                         if (p_params->b_relaxed_probe)
5827                                 p_params->p_relaxed_res =
5828                                                 ECORE_HW_PREPARE_FAILED_ENG2;
5829
5830                         if (IS_PF(p_dev)) {
5831                                 ecore_init_free(p_hwfn);
5832                                 ecore_mcp_free(p_hwfn);
5833                                 ecore_hw_hwfn_free(p_hwfn);
5834                         } else {
5835                                 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
5836                         }
5837                         return rc;
5838                 }
5839         }
5840
5841         return rc;
5842 }
5843
5844 void ecore_hw_remove(struct ecore_dev *p_dev)
5845 {
5846         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5847         int i;
5848
5849         if (IS_PF(p_dev))
5850                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
5851                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
5852
5853         for_each_hwfn(p_dev, i) {
5854                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5855
5856                 if (IS_VF(p_dev)) {
5857                         ecore_vf_pf_release(p_hwfn);
5858                         continue;
5859                 }
5860
5861                 ecore_init_free(p_hwfn);
5862                 ecore_hw_hwfn_free(p_hwfn);
5863                 ecore_mcp_free(p_hwfn);
5864
5865 #ifdef CONFIG_ECORE_LOCK_ALLOC
5866                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
5867 #endif
5868         }
5869
5870         ecore_iov_free_hw_info(p_dev);
5871 }
5872
5873 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
5874                                       struct ecore_chain *p_chain)
5875 {
5876         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
5877         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
5878         struct ecore_chain_next *p_next;
5879         u32 size, i;
5880
5881         if (!p_virt)
5882                 return;
5883
5884         size = p_chain->elem_size * p_chain->usable_per_page;
5885
5886         for (i = 0; i < p_chain->page_cnt; i++) {
5887                 if (!p_virt)
5888                         break;
5889
5890                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
5891                 p_virt_next = p_next->next_virt;
5892                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
5893
5894                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
5895                                        ECORE_CHAIN_PAGE_SIZE);
5896
5897                 p_virt = p_virt_next;
5898                 p_phys = p_phys_next;
5899         }
5900 }
5901
5902 static void ecore_chain_free_single(struct ecore_dev *p_dev,
5903                                     struct ecore_chain *p_chain)
5904 {
5905         if (!p_chain->p_virt_addr)
5906                 return;
5907
5908         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
5909                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
5910 }
5911
5912 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
5913                                  struct ecore_chain *p_chain)
5914 {
5915         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
5916         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
5917         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
5918
5919         if (!pp_virt_addr_tbl)
5920                 return;
5921
5922         if (!p_pbl_virt)
5923                 goto out;
5924
5925         for (i = 0; i < page_cnt; i++) {
5926                 if (!pp_virt_addr_tbl[i])
5927                         break;
5928
5929                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
5930                                        *(dma_addr_t *)p_pbl_virt,
5931                                        ECORE_CHAIN_PAGE_SIZE);
5932
5933                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
5934         }
5935
5936         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
5937
5938         if (!p_chain->b_external_pbl)
5939                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
5940                                        p_chain->pbl_sp.p_phys_table, pbl_size);
5941 out:
5942         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
5943 }
5944
5945 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5946 {
5947         switch (p_chain->mode) {
5948         case ECORE_CHAIN_MODE_NEXT_PTR:
5949                 ecore_chain_free_next_ptr(p_dev, p_chain);
5950                 break;
5951         case ECORE_CHAIN_MODE_SINGLE:
5952                 ecore_chain_free_single(p_dev, p_chain);
5953                 break;
5954         case ECORE_CHAIN_MODE_PBL:
5955                 ecore_chain_free_pbl(p_dev, p_chain);
5956                 break;
5957         }
5958 }
5959
5960 static enum _ecore_status_t
5961 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
5962                                enum ecore_chain_cnt_type cnt_type,
5963                                osal_size_t elem_size, u32 page_cnt)
5964 {
5965         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
5966
5967         /* The actual chain size can be larger than the maximal possible value
5968          * after rounding up the requested elements number to pages, and after
5969          * taking into acount the unusuable elements (next-ptr elements).
5970          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
5971          * size/capacity fields are of a u32 type.
5972          */
5973         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
5974              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
5975             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
5976              chain_size > ECORE_U32_MAX)) {
5977                 DP_NOTICE(p_dev, true,
5978                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
5979                           (unsigned long)chain_size);
5980                 return ECORE_INVAL;
5981         }
5982
5983         return ECORE_SUCCESS;
5984 }
5985
5986 static enum _ecore_status_t
5987 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5988 {
5989         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
5990         dma_addr_t p_phys = 0;
5991         u32 i;
5992
5993         for (i = 0; i < p_chain->page_cnt; i++) {
5994                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
5995                                                  ECORE_CHAIN_PAGE_SIZE);
5996                 if (!p_virt) {
5997                         DP_NOTICE(p_dev, false,
5998                                   "Failed to allocate chain memory\n");
5999                         return ECORE_NOMEM;
6000                 }
6001
6002                 if (i == 0) {
6003                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
6004                         ecore_chain_reset(p_chain);
6005                 } else {
6006                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
6007                                                        p_virt, p_phys);
6008                 }
6009
6010                 p_virt_prev = p_virt;
6011         }
6012         /* Last page's next element should point to the beginning of the
6013          * chain.
6014          */
6015         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
6016                                        p_chain->p_virt_addr,
6017                                        p_chain->p_phys_addr);
6018
6019         return ECORE_SUCCESS;
6020 }
6021
6022 static enum _ecore_status_t
6023 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
6024 {
6025         dma_addr_t p_phys = 0;
6026         void *p_virt = OSAL_NULL;
6027
6028         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
6029         if (!p_virt) {
6030                 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
6031                 return ECORE_NOMEM;
6032         }
6033
6034         ecore_chain_init_mem(p_chain, p_virt, p_phys);
6035         ecore_chain_reset(p_chain);
6036
6037         return ECORE_SUCCESS;
6038 }
6039
6040 static enum _ecore_status_t
6041 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
6042                       struct ecore_chain *p_chain,
6043                       struct ecore_chain_ext_pbl *ext_pbl)
6044 {
6045         u32 page_cnt = p_chain->page_cnt, size, i;
6046         dma_addr_t p_phys = 0, p_pbl_phys = 0;
6047         void **pp_virt_addr_tbl = OSAL_NULL;
6048         u8 *p_pbl_virt = OSAL_NULL;
6049         void *p_virt = OSAL_NULL;
6050
6051         size = page_cnt * sizeof(*pp_virt_addr_tbl);
6052         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
6053         if (!pp_virt_addr_tbl) {
6054                 DP_NOTICE(p_dev, false,
6055                           "Failed to allocate memory for the chain virtual addresses table\n");
6056                 return ECORE_NOMEM;
6057         }
6058
6059         /* The allocation of the PBL table is done with its full size, since it
6060          * is expected to be successive.
6061          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
6062          * failure, since pp_virt_addr_tbl was previously allocated, and it
6063          * should be saved to allow its freeing during the error flow.
6064          */
6065         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
6066
6067         if (ext_pbl == OSAL_NULL) {
6068                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
6069         } else {
6070                 p_pbl_virt = ext_pbl->p_pbl_virt;
6071                 p_pbl_phys = ext_pbl->p_pbl_phys;
6072                 p_chain->b_external_pbl = true;
6073         }
6074
6075         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
6076                                  pp_virt_addr_tbl);
6077         if (!p_pbl_virt) {
6078                 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
6079                 return ECORE_NOMEM;
6080         }
6081
6082         for (i = 0; i < page_cnt; i++) {
6083                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
6084                                                  ECORE_CHAIN_PAGE_SIZE);
6085                 if (!p_virt) {
6086                         DP_NOTICE(p_dev, false,
6087                                   "Failed to allocate chain memory\n");
6088                         return ECORE_NOMEM;
6089                 }
6090
6091                 if (i == 0) {
6092                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
6093                         ecore_chain_reset(p_chain);
6094                 }
6095
6096                 /* Fill the PBL table with the physical address of the page */
6097                 *(dma_addr_t *)p_pbl_virt = p_phys;
6098                 /* Keep the virtual address of the page */
6099                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
6100
6101                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
6102         }
6103
6104         return ECORE_SUCCESS;
6105 }
6106
6107 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
6108                                        enum ecore_chain_use_mode intended_use,
6109                                        enum ecore_chain_mode mode,
6110                                        enum ecore_chain_cnt_type cnt_type,
6111                                        u32 num_elems, osal_size_t elem_size,
6112                                        struct ecore_chain *p_chain,
6113                                        struct ecore_chain_ext_pbl *ext_pbl)
6114 {
6115         u32 page_cnt;
6116         enum _ecore_status_t rc = ECORE_SUCCESS;
6117
6118         if (mode == ECORE_CHAIN_MODE_SINGLE)
6119                 page_cnt = 1;
6120         else
6121                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
6122
6123         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
6124                                             page_cnt);
6125         if (rc) {
6126                 DP_NOTICE(p_dev, false,
6127                           "Cannot allocate a chain with the given arguments:\n"
6128                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
6129                           intended_use, mode, cnt_type, num_elems, elem_size);
6130                 return rc;
6131         }
6132
6133         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
6134                                 mode, cnt_type, p_dev->dp_ctx);
6135
6136         switch (mode) {
6137         case ECORE_CHAIN_MODE_NEXT_PTR:
6138                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
6139                 break;
6140         case ECORE_CHAIN_MODE_SINGLE:
6141                 rc = ecore_chain_alloc_single(p_dev, p_chain);
6142                 break;
6143         case ECORE_CHAIN_MODE_PBL:
6144                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
6145                 break;
6146         }
6147         if (rc)
6148                 goto nomem;
6149
6150         return ECORE_SUCCESS;
6151
6152 nomem:
6153         ecore_chain_free(p_dev, p_chain);
6154         return rc;
6155 }
6156
6157 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
6158                                        u16 src_id, u16 *dst_id)
6159 {
6160         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
6161                 u16 min, max;
6162
6163                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
6164                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
6165                 DP_NOTICE(p_hwfn, true,
6166                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
6167                           src_id, min, max);
6168
6169                 return ECORE_INVAL;
6170         }
6171
6172         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
6173
6174         return ECORE_SUCCESS;
6175 }
6176
6177 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
6178                                     u8 src_id, u8 *dst_id)
6179 {
6180         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
6181                 u8 min, max;
6182
6183                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
6184                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
6185                 DP_NOTICE(p_hwfn, true,
6186                           "vport id [%d] is not valid, available indices [%d - %d]\n",
6187                           src_id, min, max);
6188
6189                 return ECORE_INVAL;
6190         }
6191
6192         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
6193
6194         return ECORE_SUCCESS;
6195 }
6196
6197 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
6198                                       u8 src_id, u8 *dst_id)
6199 {
6200         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
6201                 u8 min, max;
6202
6203                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
6204                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
6205                 DP_NOTICE(p_hwfn, true,
6206                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
6207                           src_id, min, max);
6208
6209                 return ECORE_INVAL;
6210         }
6211
6212         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
6213
6214         return ECORE_SUCCESS;
6215 }
6216
6217 enum _ecore_status_t
6218 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
6219                                   struct ecore_ptt *p_ptt)
6220 {
6221         if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
6222                 ecore_wr(p_hwfn, p_ptt,
6223                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
6224                          1 << p_hwfn->abs_pf_id / 2);
6225                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
6226                 return ECORE_SUCCESS;
6227         }
6228
6229         DP_NOTICE(p_hwfn, false,
6230                   "This function can't be set as default\n");
6231         return ECORE_INVAL;
6232 }
6233
6234 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
6235                                                struct ecore_ptt *p_ptt,
6236                                                u32 hw_addr, void *p_eth_qzone,
6237                                                osal_size_t eth_qzone_size,
6238                                                u8 timeset)
6239 {
6240         struct coalescing_timeset *p_coal_timeset;
6241
6242         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
6243                 DP_NOTICE(p_hwfn, true,
6244                           "Coalescing configuration not enabled\n");
6245                 return ECORE_INVAL;
6246         }
6247
6248         p_coal_timeset = p_eth_qzone;
6249         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
6250         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
6251         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
6252         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
6253
6254         return ECORE_SUCCESS;
6255 }
6256
6257 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
6258                                               u16 rx_coal, u16 tx_coal,
6259                                               void *p_handle)
6260 {
6261         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
6262         enum _ecore_status_t rc = ECORE_SUCCESS;
6263         struct ecore_ptt *p_ptt;
6264
6265         /* TODO - Configuring a single queue's coalescing but
6266          * claiming all queues are abiding same configuration
6267          * for PF and VF both.
6268          */
6269
6270         if (IS_VF(p_hwfn->p_dev))
6271                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
6272                                                 tx_coal, p_cid);
6273
6274         p_ptt = ecore_ptt_acquire(p_hwfn);
6275         if (!p_ptt)
6276                 return ECORE_AGAIN;
6277
6278         if (rx_coal) {
6279                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
6280                 if (rc)
6281                         goto out;
6282                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
6283         }
6284
6285         if (tx_coal) {
6286                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
6287                 if (rc)
6288                         goto out;
6289                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
6290         }
6291 out:
6292         ecore_ptt_release(p_hwfn, p_ptt);
6293
6294         return rc;
6295 }
6296
6297 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
6298                                             struct ecore_ptt *p_ptt,
6299                                             u16 coalesce,
6300                                             struct ecore_queue_cid *p_cid)
6301 {
6302         struct ustorm_eth_queue_zone eth_qzone;
6303         u8 timeset, timer_res;
6304         u32 address;
6305         enum _ecore_status_t rc;
6306
6307         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6308         if (coalesce <= 0x7F) {
6309                 timer_res = 0;
6310         } else if (coalesce <= 0xFF) {
6311                 timer_res = 1;
6312         } else if (coalesce <= 0x1FF) {
6313                 timer_res = 2;
6314         } else {
6315                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6316                 return ECORE_INVAL;
6317         }
6318         timeset = (u8)(coalesce >> timer_res);
6319
6320         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6321                                      p_cid->sb_igu_id, false);
6322         if (rc != ECORE_SUCCESS)
6323                 goto out;
6324
6325         address = BAR0_MAP_REG_USDM_RAM +
6326                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6327
6328         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
6329                                 sizeof(struct ustorm_eth_queue_zone), timeset);
6330         if (rc != ECORE_SUCCESS)
6331                 goto out;
6332
6333 out:
6334         return rc;
6335 }
6336
6337 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
6338                                             struct ecore_ptt *p_ptt,
6339                                             u16 coalesce,
6340                                             struct ecore_queue_cid *p_cid)
6341 {
6342         struct xstorm_eth_queue_zone eth_qzone;
6343         u8 timeset, timer_res;
6344         u32 address;
6345         enum _ecore_status_t rc;
6346
6347         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6348         if (coalesce <= 0x7F) {
6349                 timer_res = 0;
6350         } else if (coalesce <= 0xFF) {
6351                 timer_res = 1;
6352         } else if (coalesce <= 0x1FF) {
6353                 timer_res = 2;
6354         } else {
6355                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6356                 return ECORE_INVAL;
6357         }
6358
6359         timeset = (u8)(coalesce >> timer_res);
6360
6361         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6362                                      p_cid->sb_igu_id, true);
6363         if (rc != ECORE_SUCCESS)
6364                 goto out;
6365
6366         address = BAR0_MAP_REG_XSDM_RAM +
6367                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6368
6369         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
6370                                 sizeof(struct xstorm_eth_queue_zone), timeset);
6371 out:
6372         return rc;
6373 }
6374
6375 /* Calculate final WFQ values for all vports and configure it.
6376  * After this configuration each vport must have
6377  * approx min rate =  wfq * min_pf_rate / ECORE_WFQ_UNIT
6378  */
6379 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6380                                                struct ecore_ptt *p_ptt,
6381                                                u32 min_pf_rate)
6382 {
6383         struct init_qm_vport_params *vport_params;
6384         int i;
6385
6386         vport_params = p_hwfn->qm_info.qm_vport_params;
6387
6388         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6389                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6390
6391                 vport_params[i].wfq = (wfq_speed * ECORE_WFQ_UNIT) /
6392                     min_pf_rate;
6393                 ecore_init_vport_wfq(p_hwfn, p_ptt,
6394                                      vport_params[i].first_tx_pq_id,
6395                                      vport_params[i].wfq);
6396         }
6397 }
6398
6399 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
6400 {
6401         int i;
6402
6403         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
6404                 p_hwfn->qm_info.qm_vport_params[i].wfq = 1;
6405 }
6406
6407 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6408                                              struct ecore_ptt *p_ptt)
6409 {
6410         struct init_qm_vport_params *vport_params;
6411         int i;
6412
6413         vport_params = p_hwfn->qm_info.qm_vport_params;
6414
6415         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6416                 ecore_init_wfq_default_param(p_hwfn);
6417                 ecore_init_vport_wfq(p_hwfn, p_ptt,
6418                                      vport_params[i].first_tx_pq_id,
6419                                      vport_params[i].wfq);
6420         }
6421 }
6422
6423 /* This function performs several validations for WFQ
6424  * configuration and required min rate for a given vport
6425  * 1. req_rate must be greater than one percent of min_pf_rate.
6426  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
6427  *    rates to get less than one percent of min_pf_rate.
6428  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
6429  */
6430 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
6431                                                  u16 vport_id, u32 req_rate,
6432                                                  u32 min_pf_rate)
6433 {
6434         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
6435         int non_requested_count = 0, req_count = 0, i, num_vports;
6436
6437         num_vports = p_hwfn->qm_info.num_vports;
6438
6439 /* Accounting for the vports which are configured for WFQ explicitly */
6440
6441         for (i = 0; i < num_vports; i++) {
6442                 u32 tmp_speed;
6443
6444                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
6445                         req_count++;
6446                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6447                         total_req_min_rate += tmp_speed;
6448                 }
6449         }
6450
6451         /* Include current vport data as well */
6452         req_count++;
6453         total_req_min_rate += req_rate;
6454         non_requested_count = num_vports - req_count;
6455
6456         /* validate possible error cases */
6457         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
6458                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6459                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6460                            vport_id, req_rate, min_pf_rate);
6461                 return ECORE_INVAL;
6462         }
6463
6464         /* TBD - for number of vports greater than 100 */
6465         if (num_vports > ECORE_WFQ_UNIT) {
6466                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6467                            "Number of vports is greater than %d\n",
6468                            ECORE_WFQ_UNIT);
6469                 return ECORE_INVAL;
6470         }
6471
6472         if (total_req_min_rate > min_pf_rate) {
6473                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6474                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
6475                            total_req_min_rate, min_pf_rate);
6476                 return ECORE_INVAL;
6477         }
6478
6479         /* Data left for non requested vports */
6480         total_left_rate = min_pf_rate - total_req_min_rate;
6481         left_rate_per_vp = total_left_rate / non_requested_count;
6482
6483         /* validate if non requested get < 1% of min bw */
6484         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
6485                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6486                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6487                            left_rate_per_vp, min_pf_rate);
6488                 return ECORE_INVAL;
6489         }
6490
6491         /* now req_rate for given vport passes all scenarios.
6492          * assign final wfq rates to all vports.
6493          */
6494         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
6495         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
6496
6497         for (i = 0; i < num_vports; i++) {
6498                 if (p_hwfn->qm_info.wfq_data[i].configured)
6499                         continue;
6500
6501                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
6502         }
6503
6504         return ECORE_SUCCESS;
6505 }
6506
6507 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
6508                                        struct ecore_ptt *p_ptt,
6509                                        u16 vp_id, u32 rate)
6510 {
6511         struct ecore_mcp_link_state *p_link;
6512         int rc = ECORE_SUCCESS;
6513
6514         p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output;
6515
6516         if (!p_link->min_pf_rate) {
6517                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
6518                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
6519                 return rc;
6520         }
6521
6522         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
6523
6524         if (rc == ECORE_SUCCESS)
6525                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
6526                                                    p_link->min_pf_rate);
6527         else
6528                 DP_NOTICE(p_hwfn, false,
6529                           "Validation failed while configuring min rate\n");
6530
6531         return rc;
6532 }
6533
6534 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
6535                                                    struct ecore_ptt *p_ptt,
6536                                                    u32 min_pf_rate)
6537 {
6538         bool use_wfq = false;
6539         int rc = ECORE_SUCCESS;
6540         u16 i;
6541
6542         /* Validate all pre configured vports for wfq */
6543         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6544                 u32 rate;
6545
6546                 if (!p_hwfn->qm_info.wfq_data[i].configured)
6547                         continue;
6548
6549                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
6550                 use_wfq = true;
6551
6552                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
6553                 if (rc != ECORE_SUCCESS) {
6554                         DP_NOTICE(p_hwfn, false,
6555                                   "WFQ validation failed while configuring min rate\n");
6556                         break;
6557                 }
6558         }
6559
6560         if (rc == ECORE_SUCCESS && use_wfq)
6561                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
6562         else
6563                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6564
6565         return rc;
6566 }
6567
6568 /* Main API for ecore clients to configure vport min rate.
6569  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
6570  * rate - Speed in Mbps needs to be assigned to a given vport.
6571  */
6572 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
6573 {
6574         int i, rc = ECORE_INVAL;
6575
6576         /* TBD - for multiple hardware functions - that is 100 gig */
6577         if (ECORE_IS_CMT(p_dev)) {
6578                 DP_NOTICE(p_dev, false,
6579                           "WFQ configuration is not supported for this device\n");
6580                 return rc;
6581         }
6582
6583         for_each_hwfn(p_dev, i) {
6584                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6585                 struct ecore_ptt *p_ptt;
6586
6587                 p_ptt = ecore_ptt_acquire(p_hwfn);
6588                 if (!p_ptt)
6589                         return ECORE_TIMEOUT;
6590
6591                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
6592
6593                 if (rc != ECORE_SUCCESS) {
6594                         ecore_ptt_release(p_hwfn, p_ptt);
6595                         return rc;
6596                 }
6597
6598                 ecore_ptt_release(p_hwfn, p_ptt);
6599         }
6600
6601         return rc;
6602 }
6603
6604 /* API to configure WFQ from mcp link change */
6605 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
6606                                            struct ecore_ptt *p_ptt,
6607                                            u32 min_pf_rate)
6608 {
6609         int i;
6610
6611         /* TBD - for multiple hardware functions - that is 100 gig */
6612         if (ECORE_IS_CMT(p_dev)) {
6613                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
6614                            "WFQ configuration is not supported for this device\n");
6615                 return;
6616         }
6617
6618         for_each_hwfn(p_dev, i) {
6619                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6620
6621                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
6622                                                         min_pf_rate);
6623         }
6624 }
6625
6626 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
6627                                        struct ecore_ptt *p_ptt,
6628                                        struct ecore_mcp_link_state *p_link,
6629                                        u8 max_bw)
6630 {
6631         int rc = ECORE_SUCCESS;
6632
6633         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
6634
6635         if (!p_link->line_speed && (max_bw != 100))
6636                 return rc;
6637
6638         p_link->speed = (p_link->line_speed * max_bw) / 100;
6639         p_hwfn->qm_info.pf_rl = p_link->speed;
6640
6641         /* Since the limiter also affects Tx-switched traffic, we don't want it
6642          * to limit such traffic in case there's no actual limit.
6643          * In that case, set limit to imaginary high boundary.
6644          */
6645         if (max_bw == 100)
6646                 p_hwfn->qm_info.pf_rl = 100000;
6647
6648         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
6649                               p_hwfn->qm_info.pf_rl);
6650
6651         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6652                    "Configured MAX bandwidth to be %08x Mb/sec\n",
6653                    p_link->speed);
6654
6655         return rc;
6656 }
6657
6658 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
6659 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
6660 {
6661         int i, rc = ECORE_INVAL;
6662
6663         if (max_bw < 1 || max_bw > 100) {
6664                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
6665                 return rc;
6666         }
6667
6668         for_each_hwfn(p_dev, i) {
6669                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6670                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6671                 struct ecore_mcp_link_state *p_link;
6672                 struct ecore_ptt *p_ptt;
6673
6674                 p_link = &p_lead->mcp_info->link_output;
6675
6676                 p_ptt = ecore_ptt_acquire(p_hwfn);
6677                 if (!p_ptt)
6678                         return ECORE_TIMEOUT;
6679
6680                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
6681                                                         p_link, max_bw);
6682
6683                 ecore_ptt_release(p_hwfn, p_ptt);
6684
6685                 if (rc != ECORE_SUCCESS)
6686                         break;
6687         }
6688
6689         return rc;
6690 }
6691
6692 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
6693                                        struct ecore_ptt *p_ptt,
6694                                        struct ecore_mcp_link_state *p_link,
6695                                        u8 min_bw)
6696 {
6697         int rc = ECORE_SUCCESS;
6698
6699         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
6700         p_hwfn->qm_info.pf_wfq = min_bw;
6701
6702         if (!p_link->line_speed)
6703                 return rc;
6704
6705         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
6706
6707         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
6708
6709         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6710                    "Configured MIN bandwidth to be %d Mb/sec\n",
6711                    p_link->min_pf_rate);
6712
6713         return rc;
6714 }
6715
6716 /* Main API to configure PF min bandwidth where bw range is [1-100] */
6717 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
6718 {
6719         int i, rc = ECORE_INVAL;
6720
6721         if (min_bw < 1 || min_bw > 100) {
6722                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
6723                 return rc;
6724         }
6725
6726         for_each_hwfn(p_dev, i) {
6727                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6728                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6729                 struct ecore_mcp_link_state *p_link;
6730                 struct ecore_ptt *p_ptt;
6731
6732                 p_link = &p_lead->mcp_info->link_output;
6733
6734                 p_ptt = ecore_ptt_acquire(p_hwfn);
6735                 if (!p_ptt)
6736                         return ECORE_TIMEOUT;
6737
6738                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
6739                                                         p_link, min_bw);
6740                 if (rc != ECORE_SUCCESS) {
6741                         ecore_ptt_release(p_hwfn, p_ptt);
6742                         return rc;
6743                 }
6744
6745                 if (p_link->min_pf_rate) {
6746                         u32 min_rate = p_link->min_pf_rate;
6747
6748                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
6749                                                                      p_ptt,
6750                                                                      min_rate);
6751                 }
6752
6753                 ecore_ptt_release(p_hwfn, p_ptt);
6754         }
6755
6756         return rc;
6757 }
6758
6759 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
6760 {
6761         struct ecore_mcp_link_state *p_link;
6762
6763         p_link = &p_hwfn->mcp_info->link_output;
6764
6765         if (p_link->min_pf_rate)
6766                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6767
6768         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
6769                     sizeof(*p_hwfn->qm_info.wfq_data) *
6770                     p_hwfn->qm_info.num_vports);
6771 }
6772
6773 int ecore_device_num_engines(struct ecore_dev *p_dev)
6774 {
6775         return ECORE_IS_BB(p_dev) ? 2 : 1;
6776 }
6777
6778 int ecore_device_num_ports(struct ecore_dev *p_dev)
6779 {
6780         return p_dev->num_ports;
6781 }
6782
6783 void ecore_set_fw_mac_addr(__le16 *fw_msb,
6784                           __le16 *fw_mid,
6785                           __le16 *fw_lsb,
6786                           u8 *mac)
6787 {
6788         ((u8 *)fw_msb)[0] = mac[1];
6789         ((u8 *)fw_msb)[1] = mac[0];
6790         ((u8 *)fw_mid)[0] = mac[3];
6791         ((u8 *)fw_mid)[1] = mac[2];
6792         ((u8 *)fw_lsb)[0] = mac[5];
6793         ((u8 *)fw_lsb)[1] = mac[4];
6794 }
6795
6796 bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
6797 {
6798         return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
6799 }