drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_attn_values.h"
  33 #include "ecore_dcbx.h"
  34
  35 /* Configurable */
  36 #define ECORE_MIN_DPIS          (4)     /* The minimal number of DPIs required
  37                                          * load the driver. The number was
  38                                          * arbitrarily set.
  39                                          */
  40
  41 /* Derived */
  42 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  43
  44 enum BAR_ID {
  45         BAR_ID_0,               /* used for GRC */
  46         BAR_ID_1                /* Used for doorbells */
  47 };
  48
  49 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  50 {
  51         u32 bar_reg = (bar_id == BAR_ID_0 ?
  52                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  53         u32 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  54
  55         /* The above registers were updated in the past only in CMT mode. Since
  56          * they were found to be useful MFW started updating them from 8.7.7.0.
  57          * In older MFW versions they are set to 0 which means disabled.
  58          */
  59         if (!val) {
  60                 if (p_hwfn->p_dev->num_hwfns > 1) {
  61                         DP_NOTICE(p_hwfn, false,
  62                                   "BAR size not configured. Assuming BAR"
  63                                   " size of 256kB for GRC and 512kB for DB\n");
  64                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  65                 }
  66
  67                         DP_NOTICE(p_hwfn, false,
  68                           "BAR size not configured. Assuming BAR"
  69                           " size of 512kB for GRC and 512kB for DB\n");
  70                         return 512 * 1024;
  71                 }
  72
  73         return 1 << (val + 15);
  74 }
  75
  76 void ecore_init_dp(struct ecore_dev *p_dev,
  77                    u32 dp_module, u8 dp_level, void *dp_ctx)
  78 {
  79         u32 i;
  80
  81         p_dev->dp_level = dp_level;
  82         p_dev->dp_module = dp_module;
  83         p_dev->dp_ctx = dp_ctx;
  84         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  85                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
  86
  87                 p_hwfn->dp_level = dp_level;
  88                 p_hwfn->dp_module = dp_module;
  89                 p_hwfn->dp_ctx = dp_ctx;
  90         }
  91 }
  92
  93 void ecore_init_struct(struct ecore_dev *p_dev)
  94 {
  95         u8 i;
  96
  97         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  98                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
  99
 100                 p_hwfn->p_dev = p_dev;
 101                 p_hwfn->my_id = i;
 102                 p_hwfn->b_active = false;
 103
 104                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 105                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 106         }
 107
 108         /* hwfn 0 is always active */
 109         p_dev->hwfns[0].b_active = true;
 110
 111         /* set the default cache alignment to 128 (may be overridden later) */
 112         p_dev->cache_shift = 7;
 113 }
 114
 115 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 116 {
 117         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 118
 119         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 120         qm_info->qm_pq_params = OSAL_NULL;
 121         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 122         qm_info->qm_vport_params = OSAL_NULL;
 123         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 124         qm_info->qm_port_params = OSAL_NULL;
 125         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 126         qm_info->wfq_data = OSAL_NULL;
 127 }
 128
 129 void ecore_resc_free(struct ecore_dev *p_dev)
 130 {
 131         int i;
 132
 133         if (IS_VF(p_dev))
 134                 return;
 135
 136         OSAL_FREE(p_dev, p_dev->fw_data);
 137         p_dev->fw_data = OSAL_NULL;
 138
 139         OSAL_FREE(p_dev, p_dev->reset_stats);
 140
 141         for_each_hwfn(p_dev, i) {
 142                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 143
 144                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 145                 p_hwfn->p_tx_cids = OSAL_NULL;
 146                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 147                 p_hwfn->p_rx_cids = OSAL_NULL;
 148         }
 149
 150         for_each_hwfn(p_dev, i) {
 151                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 152
 153                 ecore_cxt_mngr_free(p_hwfn);
 154                 ecore_qm_info_free(p_hwfn);
 155                 ecore_spq_free(p_hwfn);
 156                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 157                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 158                 ecore_int_free(p_hwfn);
 159                 ecore_iov_free(p_hwfn);
 160                 ecore_dmae_info_free(p_hwfn);
 161                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 162                 /* @@@TBD Flush work-queue ? */
 163         }
 164 }
 165
 166 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 167                                                bool b_sleepable)
 168 {
 169         u8 num_vports, vf_offset = 0, i, vport_id, num_ports;
 170         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 171         struct init_qm_port_params *p_qm_port;
 172         u16 num_pqs, multi_cos_tcs = 1;
 173 #ifdef CONFIG_ECORE_SRIOV
 174         u16 num_vfs = p_hwfn->p_dev->sriov_info.total_vfs;
 175 #else
 176         u16 num_vfs = 0;
 177 #endif
 178
 179         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 180
 181 #ifndef ASIC_ONLY
 182         /* @TMP - Don't allocate QM queues for VFs on emulation */
 183         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 184                 DP_NOTICE(p_hwfn, false,
 185                           "Emulation - skip configuring QM queues for VFs\n");
 186                 num_vfs = 0;
 187         }
 188 #endif
 189
 190         num_pqs = multi_cos_tcs + num_vfs + 1;  /* The '1' is for pure-LB */
 191         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 192
 193         /* Sanity checking that setup requires legal number of resources */
 194         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 195                 DP_ERR(p_hwfn,
 196                        "Need too many Physical queues - 0x%04x when"
 197                         " only %04x are available\n",
 198                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 199                 return ECORE_INVAL;
 200         }
 201
 202         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 203          * then special queues, then per-VF PQ.
 204          */
 205         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 206                                             b_sleepable ? GFP_KERNEL :
 207                                             GFP_ATOMIC,
 208                                             sizeof(struct init_qm_pq_params) *
 209                                             num_pqs);
 210         if (!qm_info->qm_pq_params)
 211                 goto alloc_err;
 212
 213         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 214                                                b_sleepable ? GFP_KERNEL :
 215                                                GFP_ATOMIC,
 216                                                sizeof(struct
 217                                                       init_qm_vport_params) *
 218                                                num_vports);
 219         if (!qm_info->qm_vport_params)
 220                 goto alloc_err;
 221
 222         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 223                                               b_sleepable ? GFP_KERNEL :
 224                                               GFP_ATOMIC,
 225                                               sizeof(struct init_qm_port_params)
 226                                               * MAX_NUM_PORTS);
 227         if (!qm_info->qm_port_params)
 228                 goto alloc_err;
 229
 230         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 231                                         b_sleepable ? GFP_KERNEL :
 232                                         GFP_ATOMIC,
 233                                         sizeof(struct ecore_wfq_data) *
 234                                         num_vports);
 235
 236         if (!qm_info->wfq_data)
 237                 goto alloc_err;
 238
 239         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 240
 241         /* First init per-TC PQs */
 242         for (i = 0; i < multi_cos_tcs; i++) {
 243                 struct init_qm_pq_params *params = &qm_info->qm_pq_params[i];
 244
 245                 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
 246                         params->vport_id = vport_id;
 247                         params->tc_id = p_hwfn->hw_info.non_offload_tc;
 248                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 249                 } else {
 250                         params->vport_id = vport_id;
 251                         params->tc_id = p_hwfn->hw_info.offload_tc;
 252                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 253                 }
 254         }
 255
 256         /* Then init pure-LB PQ */
 257         qm_info->pure_lb_pq = i;
 258         qm_info->qm_pq_params[i].vport_id =
 259             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 260         qm_info->qm_pq_params[i].tc_id = PURE_LB_TC;
 261         qm_info->qm_pq_params[i].wrr_group = 1;
 262         i++;
 263
 264         /* Then init per-VF PQs */
 265         vf_offset = i;
 266         for (i = 0; i < num_vfs; i++) {
 267                 /* First vport is used by the PF */
 268                 qm_info->qm_pq_params[vf_offset + i].vport_id = vport_id +
 269                     i + 1;
 270                 qm_info->qm_pq_params[vf_offset + i].tc_id =
 271                     p_hwfn->hw_info.non_offload_tc;
 272                 qm_info->qm_pq_params[vf_offset + i].wrr_group = 1;
 273         };
 274
 275         qm_info->vf_queues_offset = vf_offset;
 276         qm_info->num_pqs = num_pqs;
 277         qm_info->num_vports = num_vports;
 278
 279         /* Initialize qm port parameters */
 280         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 281         for (i = 0; i < num_ports; i++) {
 282                 p_qm_port = &qm_info->qm_port_params[i];
 283                 p_qm_port->active = 1;
 284                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 285                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 286         }
 287
 288         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 289                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 290         else
 291                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 292
 293         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 294
 295         qm_info->num_vf_pqs = num_vfs;
 296         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 297
 298         for (i = 0; i < qm_info->num_vports; i++)
 299                 qm_info->qm_vport_params[i].vport_wfq = 1;
 300
 301         qm_info->pf_wfq = 0;
 302         qm_info->pf_rl = 0;
 303         qm_info->vport_rl_en = 1;
 304         qm_info->vport_wfq_en = 1;
 305
 306         return ECORE_SUCCESS;
 307
 308  alloc_err:
 309         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 310         ecore_qm_info_free(p_hwfn);
 311         return ECORE_NOMEM;
 312 }
 313
 314 /* This function reconfigures the QM pf on the fly.
 315  * For this purpose we:
 316  * 1. reconfigure the QM database
 317  * 2. set new values to runtime arrat
 318  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 319  * 4. activate init tool in QM_PF stage
 320  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 321  */
 322 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 323                                      struct ecore_ptt *p_ptt)
 324 {
 325         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 326         bool b_rc;
 327         enum _ecore_status_t rc;
 328
 329         /* qm_info is allocated in ecore_init_qm_info() which is already called
 330          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 331          * The allocated size may change each init, so we free it before next
 332          * allocation.
 333          */
 334         ecore_qm_info_free(p_hwfn);
 335
 336         /* initialize ecore's qm data structure */
 337         rc = ecore_init_qm_info(p_hwfn, false);
 338         if (rc != ECORE_SUCCESS)
 339                 return rc;
 340
 341         /* stop PF's qm queues */
 342         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 343                                       qm_info->start_pq, qm_info->num_pqs);
 344         if (!b_rc)
 345                 return ECORE_INVAL;
 346
 347         /* clear the QM_PF runtime phase leftovers from previous init */
 348         ecore_init_clear_rt_data(p_hwfn);
 349
 350         /* prepare QM portion of runtime array */
 351         ecore_qm_init_pf(p_hwfn);
 352
 353         /* activate init tool on runtime array */
 354         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 355                             p_hwfn->hw_info.hw_mode);
 356         if (rc != ECORE_SUCCESS)
 357                 return rc;
 358
 359         /* start PF's qm queues */
 360         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 361                                       qm_info->start_pq, qm_info->num_pqs);
 362         if (!rc)
 363                 return ECORE_INVAL;
 364
 365         return ECORE_SUCCESS;
 366 }
 367
 368 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 369 {
 370         enum _ecore_status_t rc = ECORE_SUCCESS;
 371         struct ecore_consq *p_consq;
 372         struct ecore_eq *p_eq;
 373         int i;
 374
 375         if (IS_VF(p_dev))
 376                 return rc;
 377
 378         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 379                                      sizeof(struct ecore_fw_data));
 380         if (!p_dev->fw_data)
 381                 return ECORE_NOMEM;
 382
 383         /* Allocate Memory for the Queue->CID mapping */
 384         for_each_hwfn(p_dev, i) {
 385                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 386
 387                 /* @@@TMP - resc management, change to actual required size */
 388                 int tx_size = sizeof(struct ecore_hw_cid_data) *
 389                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 390                 int rx_size = sizeof(struct ecore_hw_cid_data) *
 391                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 392
 393                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 394                                                 tx_size);
 395                 if (!p_hwfn->p_tx_cids) {
 396                         DP_NOTICE(p_hwfn, true,
 397                                   "Failed to allocate memory for Tx Cids\n");
 398                         goto alloc_no_mem;
 399                 }
 400
 401                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 402                                                 rx_size);
 403                 if (!p_hwfn->p_rx_cids) {
 404                         DP_NOTICE(p_hwfn, true,
 405                                   "Failed to allocate memory for Rx Cids\n");
 406                         goto alloc_no_mem;
 407                 }
 408         }
 409
 410         for_each_hwfn(p_dev, i) {
 411                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 412
 413                 /* First allocate the context manager structure */
 414                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 415                 if (rc)
 416                         goto alloc_err;
 417
 418                 /* Set the HW cid/tid numbers (in the contest manager)
 419                  * Must be done prior to any further computations.
 420                  */
 421                 rc = ecore_cxt_set_pf_params(p_hwfn);
 422                 if (rc)
 423                         goto alloc_err;
 424
 425                 /* Prepare and process QM requirements */
 426                 rc = ecore_init_qm_info(p_hwfn, true);
 427                 if (rc)
 428                         goto alloc_err;
 429
 430                 /* Compute the ILT client partition */
 431                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 432                 if (rc)
 433                         goto alloc_err;
 434
 435                 /* CID map / ILT shadow table / T2
 436                  * The talbes sizes are determined by the computations above
 437                  */
 438                 rc = ecore_cxt_tables_alloc(p_hwfn);
 439                 if (rc)
 440                         goto alloc_err;
 441
 442                 /* SPQ, must follow ILT because initializes SPQ context */
 443                 rc = ecore_spq_alloc(p_hwfn);
 444                 if (rc)
 445                         goto alloc_err;
 446
 447                 /* SP status block allocation */
 448                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 449                                                            RESERVED_PTT_DPC);
 450
 451                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 452                 if (rc)
 453                         goto alloc_err;
 454
 455                 rc = ecore_iov_alloc(p_hwfn);
 456                 if (rc)
 457                         goto alloc_err;
 458
 459                 /* EQ */
 460                 p_eq = ecore_eq_alloc(p_hwfn, 256);
 461                 if (!p_eq)
 462                         goto alloc_no_mem;
 463                 p_hwfn->p_eq = p_eq;
 464
 465                 p_consq = ecore_consq_alloc(p_hwfn);
 466                 if (!p_consq)
 467                         goto alloc_no_mem;
 468                 p_hwfn->p_consq = p_consq;
 469
 470 #ifdef CONFIG_ECORE_LL2
 471                 if (p_hwfn->using_ll2) {
 472                         p_ll2_info = ecore_ll2_alloc(p_hwfn);
 473                         if (!p_ll2_info)
 474                                 goto alloc_no_mem;
 475                         p_hwfn->p_ll2_info = p_ll2_info;
 476                 }
 477 #endif
 478
 479                 /* DMA info initialization */
 480                 rc = ecore_dmae_info_alloc(p_hwfn);
 481                 if (rc) {
 482                         DP_NOTICE(p_hwfn, true,
 483                                   "Failed to allocate memory for dmae_info structure\n");
 484                         goto alloc_err;
 485                 }
 486
 487                 /* DCBX initialization */
 488                 rc = ecore_dcbx_info_alloc(p_hwfn);
 489                 if (rc) {
 490                         DP_NOTICE(p_hwfn, true,
 491                                   "Failed to allocate memory for dcbx structure\n");
 492                         goto alloc_err;
 493                 }
 494         }
 495
 496         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 497                                          sizeof(struct ecore_eth_stats));
 498         if (!p_dev->reset_stats) {
 499                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 500                 goto alloc_no_mem;
 501         }
 502
 503         return ECORE_SUCCESS;
 504
 505  alloc_no_mem:
 506         rc = ECORE_NOMEM;
 507  alloc_err:
 508         ecore_resc_free(p_dev);
 509         return rc;
 510 }
 511
 512 void ecore_resc_setup(struct ecore_dev *p_dev)
 513 {
 514         int i;
 515
 516         if (IS_VF(p_dev))
 517                 return;
 518
 519         for_each_hwfn(p_dev, i) {
 520                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 521
 522                 ecore_cxt_mngr_setup(p_hwfn);
 523                 ecore_spq_setup(p_hwfn);
 524                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 525                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 526
 527                 /* Read shadow of current MFW mailbox */
 528                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 529                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 530                             p_hwfn->mcp_info->mfw_mb_cur,
 531                             p_hwfn->mcp_info->mfw_mb_length);
 532
 533                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 534
 535                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 536         }
 537 }
 538
 539 #define FINAL_CLEANUP_POLL_CNT  (100)
 540 #define FINAL_CLEANUP_POLL_TIME (10)
 541 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 542                                          struct ecore_ptt *p_ptt,
 543                                          u16 id, bool is_vf)
 544 {
 545         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 546         enum _ecore_status_t rc = ECORE_TIMEOUT;
 547
 548 #ifndef ASIC_ONLY
 549         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 550             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 551                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 552                 return ECORE_SUCCESS;
 553         }
 554 #endif
 555
 556         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 557             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 558
 559         if (is_vf)
 560                 id += 0x10;
 561
 562         command |= X_FINAL_CLEANUP_AGG_INT <<
 563             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 564         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 565         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 566         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 567
 568 /* Make sure notification is not set before initiating final cleanup */
 569
 570         if (REG_RD(p_hwfn, addr)) {
 571                 DP_NOTICE(p_hwfn, false,
 572                           "Unexpected; Found final cleanup notification");
 573                 DP_NOTICE(p_hwfn, false,
 574                           " before initiating final cleanup\n");
 575                 REG_WR(p_hwfn, addr, 0);
 576         }
 577
 578         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 579                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 580                    id, OSAL_CPU_TO_LE32(command));
 581
 582         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
 583                  OSAL_CPU_TO_LE32(command));
 584
 585         /* Poll until completion */
 586         while (!REG_RD(p_hwfn, addr) && count--)
 587                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 588
 589         if (REG_RD(p_hwfn, addr))
 590                 rc = ECORE_SUCCESS;
 591         else
 592                 DP_NOTICE(p_hwfn, true,
 593                           "Failed to receive FW final cleanup notification\n");
 594
 595         /* Cleanup afterwards */
 596         REG_WR(p_hwfn, addr, 0);
 597
 598         return rc;
 599 }
 600
 601 static void ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 602 {
 603         int hw_mode = 0;
 604
 605         if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
 606                 hw_mode |= 1 << MODE_BB_A0;
 607         } else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
 608                 hw_mode |= 1 << MODE_BB_B0;
 609         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
 610                 hw_mode |= 1 << MODE_K2;
 611         } else {
 612                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
 613                           p_hwfn->p_dev->type);
 614                 return;
 615         }
 616
 617         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 618         switch (p_hwfn->p_dev->num_ports_in_engines) {
 619         case 1:
 620                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 621                 break;
 622         case 2:
 623                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 624                 break;
 625         case 4:
 626                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 627                 break;
 628         default:
 629                 DP_NOTICE(p_hwfn, true,
 630                           "num_ports_in_engine = %d not supported\n",
 631                           p_hwfn->p_dev->num_ports_in_engines);
 632                 return;
 633         }
 634
 635         switch (p_hwfn->p_dev->mf_mode) {
 636         case ECORE_MF_DEFAULT:
 637         case ECORE_MF_NPAR:
 638                 hw_mode |= 1 << MODE_MF_SI;
 639                 break;
 640         case ECORE_MF_OVLAN:
 641                 hw_mode |= 1 << MODE_MF_SD;
 642                 break;
 643         default:
 644                 DP_NOTICE(p_hwfn, true,
 645                           "Unsupported MF mode, init as DEFAULT\n");
 646                 hw_mode |= 1 << MODE_MF_SI;
 647         }
 648
 649 #ifndef ASIC_ONLY
 650         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 651                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 652                         hw_mode |= 1 << MODE_FPGA;
 653                 } else {
 654                         if (p_hwfn->p_dev->b_is_emul_full)
 655                                 hw_mode |= 1 << MODE_EMUL_FULL;
 656                         else
 657                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 658                 }
 659         } else
 660 #endif
 661                 hw_mode |= 1 << MODE_ASIC;
 662
 663         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))
 664                 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND;
 665
 666         if (p_hwfn->p_dev->num_hwfns > 1)
 667                 hw_mode |= 1 << MODE_100G;
 668
 669         p_hwfn->hw_info.hw_mode = hw_mode;
 670
 671         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 672                    "Configuring function for hw_mode: 0x%08x\n",
 673                    p_hwfn->hw_info.hw_mode);
 674 }
 675
 676 #ifndef ASIC_ONLY
 677 /* MFW-replacement initializations for non-ASIC */
 678 static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 679                                                struct ecore_ptt *p_ptt)
 680 {
 681         u32 pl_hv = 1;
 682         int i;
 683
 684         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 685                 pl_hv |= 0x600;
 686
 687         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 688
 689         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 690                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
 691
 692         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 693         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 694         if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
 695                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
 696
 697         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
 698                 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 699                 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 700                          (p_hwfn->p_dev->num_ports_in_engines >> 1));
 701
 702                 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 703                          p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
 704         }
 705
 706         /* Poll on RBC */
 707         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 708         for (i = 0; i < 100; i++) {
 709                 OSAL_UDELAY(50);
 710                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 711                         break;
 712         }
 713         if (i == 100)
 714                 DP_NOTICE(p_hwfn, true,
 715                           "RBC done failed to complete in PSWRQ2\n");
 716 }
 717 #endif
 718
 719 /* Init run time data for all PFs and their VFs on an engine.
 720  * TBD - for VFs - Once we have parent PF info for each VF in
 721  * shmem available as CAU requires knowledge of parent PF for each VF.
 722  */
 723 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 724 {
 725         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 726         int i, sb_id;
 727
 728         for_each_hwfn(p_dev, i) {
 729                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 730                 struct ecore_igu_info *p_igu_info;
 731                 struct ecore_igu_block *p_block;
 732                 struct cau_sb_entry sb_entry;
 733
 734                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 735
 736                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 737                      sb_id++) {
 738                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 739
 740                         if (!p_block->is_pf)
 741                                 continue;
 742
 743                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 744                                                 p_block->function_id, 0, 0);
 745                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 746                 }
 747         }
 748 }
 749
 750 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 751                                                  struct ecore_ptt *p_ptt,
 752                                                  int hw_mode)
 753 {
 754         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 755         struct ecore_dev *p_dev = p_hwfn->p_dev;
 756         u8 vf_id, max_num_vfs;
 757         u16 num_pfs, pf_id;
 758         u32 concrete_fid;
 759         enum _ecore_status_t rc = ECORE_SUCCESS;
 760
 761         ecore_init_cau_rt_data(p_dev);
 762
 763         /* Program GTT windows */
 764         ecore_gtt_init(p_hwfn);
 765
 766 #ifndef ASIC_ONLY
 767         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 768                 ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 769 #endif
 770
 771         if (p_hwfn->mcp_info) {
 772                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 773                         qm_info->pf_rl_en = 1;
 774                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 775                         qm_info->pf_wfq_en = 1;
 776         }
 777
 778         ecore_qm_common_rt_init(p_hwfn,
 779                                 p_hwfn->p_dev->num_ports_in_engines,
 780                                 qm_info->max_phys_tcs_per_port,
 781                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
 782                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
 783                                 qm_info->qm_port_params);
 784
 785         ecore_cxt_hw_init_common(p_hwfn);
 786
 787         /* Close gate from NIG to BRB/Storm; By default they are open, but
 788          * we close them to prevent NIG from passing data to reset blocks.
 789          * Should have been done in the ENGINE phase, but init-tool lacks
 790          * proper port-pretend capabilities.
 791          */
 792         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 793         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 794         ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
 795         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 796         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 797         ecore_port_unpretend(p_hwfn, p_ptt);
 798
 799         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
 800         if (rc != ECORE_SUCCESS)
 801                 return rc;
 802
 803         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
 804          * need to decide with which value, maybe runtime
 805          */
 806         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
 807         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
 808
 809         if (ECORE_IS_BB(p_hwfn->p_dev)) {
 810                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
 811                 if (num_pfs == 1)
 812                         return rc;
 813                 /* pretend to original PF */
 814                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 815         }
 816
 817         /* Workaround for avoiding CCFC execution error when getting packets
 818          * with CRC errors, and allowing instead the invoking of the FW error
 819          * handler.
 820          * This is not done inside the init tool since it currently can't
 821          * perform a pretending to VFs.
 822          */
 823         max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2
 824             : MAX_NUM_VFS_BB;
 825         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
 826                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
 827                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
 828                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
 829         }
 830         /* pretend to original PF */
 831         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 832
 833         return rc;
 834 }
 835
 836 #ifndef ASIC_ONLY
 837 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
 838 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
 839
 840 #define PMEG_IF_BYTE_COUNT      8
 841
 842 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
 843                              struct ecore_ptt *p_ptt,
 844                              u32 addr, u64 data, u8 reg_type, u8 port)
 845 {
 846         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 847                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
 848                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
 849                    (8 << PMEG_IF_BYTE_COUNT),
 850                    (reg_type << 25) | (addr << 8) | port,
 851                    (u32)((data >> 32) & 0xffffffff),
 852                    (u32)(data & 0xffffffff));
 853
 854         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
 855                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
 856                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
 857         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
 858                  (reg_type << 25) | (addr << 8) | port);
 859         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
 860                  data & 0xffffffff);
 861         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
 862                  (data >> 32) & 0xffffffff);
 863 }
 864
 865 #define XLPORT_MODE_REG (0x20a)
 866 #define XLPORT_MAC_CONTROL (0x210)
 867 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
 868 #define XLPORT_ENABLE_REG (0x20b)
 869
 870 #define XLMAC_CTRL (0x600)
 871 #define XLMAC_MODE (0x601)
 872 #define XLMAC_RX_MAX_SIZE (0x608)
 873 #define XLMAC_TX_CTRL (0x604)
 874 #define XLMAC_PAUSE_CTRL (0x60d)
 875 #define XLMAC_PFC_CTRL (0x60e)
 876
 877 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
 878                                     struct ecore_ptt *p_ptt)
 879 {
 880         u8 port = p_hwfn->port_id;
 881         u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
 882
 883         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
 884                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
 885                  (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
 886                  | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
 887
 888         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
 889                  1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
 890
 891         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
 892                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
 893
 894         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
 895                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
 896
 897         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
 898                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
 899
 900         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
 901                  (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
 902                  (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
 903
 904         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
 905 }
 906
 907 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
 908                                  struct ecore_ptt *p_ptt)
 909 {
 910         u8 loopback = 0, port = p_hwfn->port_id * 2;
 911
 912         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
 913
 914         if (ECORE_IS_AH(p_hwfn->p_dev)) {
 915                 ecore_emul_link_init_ah(p_hwfn, p_ptt);
 916                 return;
 917         }
 918
 919         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
 920         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
 921                          port);
 922         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
 923         /* XLMAC: SOFT RESET */
 924         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
 925         /* XLMAC: Port Speed >= 10Gbps */
 926         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
 927         /* XLMAC: Max Size */
 928         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
 929         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
 930                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
 931                          0, port);
 932         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
 933         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
 934                          0x30ffffc000ULL, 0, port);
 935         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
 936                         port);
 937         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x1003 | (loopback << 2),
 938                         0, port);
 939         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
 940         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
 941 }
 942
 943 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
 944                             struct ecore_ptt *p_ptt, u8 port)
 945 {
 946         int port_offset = port ? 0x800 : 0;
 947         u32 xmac_rxctrl = 0;
 948
 949         /* Reset of XMAC */
 950         /* FIXME: move to common start */
 951         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
 952                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
 953         OSAL_MSLEEP(1);
 954         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
 955                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
 956
 957         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
 958
 959         /* Set the number of ports on the Warp Core to 10G */
 960         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
 961
 962         /* Soft reset of XMAC */
 963         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
 964                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
 965         OSAL_MSLEEP(1);
 966         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
 967                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
 968
 969         /* FIXME: move to common end */
 970         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 971                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
 972
 973         /* Set Max packet size: initialize XMAC block register for port 0 */
 974         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
 975
 976         /* CRC append for Tx packets: init XMAC block register for port 1 */
 977         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
 978
 979         /* Enable TX and RX: initialize XMAC block register for port 1 */
 980         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
 981                  XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
 982         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
 983         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
 984         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
 985 }
 986 #endif
 987
 988 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
 989                                                struct ecore_ptt *p_ptt,
 990                                                int hw_mode)
 991 {
 992         enum _ecore_status_t rc = ECORE_SUCCESS;
 993
 994         /* Init sequence */
 995         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
 996                             hw_mode);
 997         if (rc != ECORE_SUCCESS)
 998                 return rc;
 999
1000 #ifndef ASIC_ONLY
1001         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1002                 return ECORE_SUCCESS;
1003
1004         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1005                 if (ECORE_IS_AH(p_hwfn->p_dev))
1006                         return ECORE_SUCCESS;
1007                 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1008         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1009                 if (p_hwfn->p_dev->num_hwfns > 1) {
1010                         /* Activate OPTE in CMT */
1011                         u32 val;
1012
1013                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1014                         val |= 0x10;
1015                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1016                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1017                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1018                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1019                         ecore_wr(p_hwfn, p_ptt,
1020                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1021                         ecore_wr(p_hwfn, p_ptt,
1022                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1023                         ecore_wr(p_hwfn, p_ptt,
1024                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1025                                  0x55555555);
1026                 }
1027
1028                 ecore_emul_link_init(p_hwfn, p_ptt);
1029         } else {
1030                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1031         }
1032 #endif
1033
1034         return rc;
1035 }
1036
1037 static enum _ecore_status_t
1038 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1039                               struct ecore_ptt *p_ptt)
1040 {
1041         u32 pwm_regsize, norm_regsize;
1042         u32 non_pwm_conn, min_addr_reg1;
1043         u32 db_bar_size, n_cpus;
1044         u32 pf_dems_shift;
1045         int rc = ECORE_SUCCESS;
1046
1047         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1048         if (p_hwfn->p_dev->num_hwfns > 1)
1049                 db_bar_size /= 2;
1050
1051         /* Calculate doorbell regions
1052          * -----------------------------------
1053          * The doorbell BAR is made of two regions. The first is called normal
1054          * region and the second is called PWM region. In the normal region
1055          * each ICID has its own set of addresses so that writing to that
1056          * specific address identifies the ICID. In the Process Window Mode
1057          * region the ICID is given in the data written to the doorbell. The
1058          * above per PF register denotes the offset in the doorbell BAR in which
1059          * the PWM region begins.
1060          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1061          * non-PWM connection. The calculation below computes the total non-PWM
1062          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1063          * in units of 4,096 bytes.
1064          */
1065         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1066             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1067                                           OSAL_NULL) +
1068             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1069         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1070         min_addr_reg1 = norm_regsize / 4096;
1071         pwm_regsize = db_bar_size - norm_regsize;
1072
1073         /* Check that the normal and PWM sizes are valid */
1074         if (db_bar_size < norm_regsize) {
1075                 DP_ERR(p_hwfn->p_dev,
1076                        "Doorbell BAR size 0x%x is too"
1077                        " small (normal region is 0x%0x )\n",
1078                        db_bar_size, norm_regsize);
1079                 return ECORE_NORESOURCES;
1080         }
1081         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1082                 DP_ERR(p_hwfn->p_dev,
1083                        "PWM region size 0x%0x is too small."
1084                        " Should be at least 0x%0x (Doorbell BAR size"
1085                        " is 0x%x and normal region size is 0x%0x)\n",
1086                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1087                        norm_regsize);
1088                 return ECORE_NORESOURCES;
1089         }
1090
1091         /* Update hwfn */
1092         p_hwfn->dpi_start_offset = norm_regsize; /* this is later used to
1093                                                   * calculate the doorbell
1094                                                   * address
1095                  */
1096
1097         /* Update registers */
1098         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1099         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1100         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1101         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1102
1103         DP_INFO(p_hwfn,
1104                 "Doorbell size 0x%x, Normal region 0x%x, PWM region 0x%x\n",
1105                 db_bar_size, norm_regsize, pwm_regsize);
1106         DP_INFO(p_hwfn, "DPI size 0x%x, DPI count 0x%x\n", p_hwfn->dpi_size,
1107                 p_hwfn->dpi_count);
1108
1109         return ECORE_SUCCESS;
1110 }
1111
1112 static enum _ecore_status_t
1113 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1114                  struct ecore_ptt *p_ptt,
1115                  struct ecore_tunn_start_params *p_tunn,
1116                  int hw_mode,
1117                  bool b_hw_start,
1118                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1119 {
1120         u8 rel_pf_id = p_hwfn->rel_pf_id;
1121         u32 prs_reg;
1122         enum _ecore_status_t rc = ECORE_SUCCESS;
1123         u16 ctrl;
1124         int pos;
1125
1126         if (p_hwfn->mcp_info) {
1127                 struct ecore_mcp_function_info *p_info;
1128
1129                 p_info = &p_hwfn->mcp_info->func_info;
1130                 if (p_info->bandwidth_min)
1131                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1132
1133                 /* Update rate limit once we'll actually have a link */
1134                 p_hwfn->qm_info.pf_rl = 100;
1135         }
1136         ecore_cxt_hw_init_pf(p_hwfn);
1137
1138         ecore_int_igu_init_rt(p_hwfn);  /* @@@TBD TODO MichalS multi hwfn ?? */
1139
1140         /* Set VLAN in NIG if needed */
1141         if (hw_mode & (1 << MODE_MF_SD)) {
1142                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1143                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1144                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1145                              p_hwfn->hw_info.ovlan);
1146         }
1147
1148         /* Enable classification by MAC if needed */
1149         if (hw_mode & (1 << MODE_MF_SI)) {
1150                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1151                            "Configuring TAGMAC_CLS_TYPE\n");
1152                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1153                              1);
1154         }
1155
1156         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1157         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
1158
1159         /* perform debug configuration when chip is out of reset */
1160         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1161
1162         /* Cleanup chip from previous driver if such remains exist */
1163         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1164         if (rc != ECORE_SUCCESS) {
1165                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1166                 return rc;
1167         }
1168
1169         /* PF Init sequence */
1170         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1171         if (rc)
1172                 return rc;
1173
1174         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1175         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1176         if (rc)
1177                 return rc;
1178
1179         /* Pure runtime initializations - directly to the HW  */
1180         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1181
1182         /* PCI relaxed ordering causes a decrease in the performance on some
1183          * systems. Till a root cause is found, disable this attribute in the
1184          * PCI config space.
1185          */
1186         /* Not in use @DPDK
1187          * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1188          * if (!pos) {
1189          *      DP_NOTICE(p_hwfn, true,
1190          *                "Failed to find the PCI Express"
1191          *                " Capability structure in the PCI config space\n");
1192          *      return ECORE_IO;
1193          * }
1194          * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1195          *                           &ctrl);
1196          * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1197          * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1198          *                           &ctrl);
1199          */
1200
1201         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1202         if (rc)
1203                 return rc;
1204
1205         if (b_hw_start) {
1206                 /* enable interrupts */
1207                 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1208
1209                 /* send function start command */
1210                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1211                                        allow_npar_tx_switch);
1212                 if (rc) {
1213                         DP_NOTICE(p_hwfn, true,
1214                                   "Function start ramrod failed\n");
1215                 } else {
1216                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1217                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1218                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1219
1220                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1221                                    "PRS_REG_SEARCH register after start PFn\n");
1222                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1223                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1224                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1225                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1226                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1227                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1228                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1229                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1230                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1231                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1232                                    prs_reg);
1233                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1234                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1235                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1236                 }
1237         }
1238         return rc;
1239 }
1240
1241 static enum _ecore_status_t
1242 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1243                       struct ecore_ptt *p_ptt, u8 enable)
1244 {
1245         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1246
1247         /* Change PF in PXP */
1248         ecore_wr(p_hwfn, p_ptt,
1249                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1250
1251         /* wait until value is set - try for 1 second every 50us */
1252         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1253                 val = ecore_rd(p_hwfn, p_ptt,
1254                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1255                 if (val == set_val)
1256                         break;
1257
1258                 OSAL_UDELAY(50);
1259         }
1260
1261         if (val != set_val) {
1262                 DP_NOTICE(p_hwfn, true,
1263                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1264                 return ECORE_UNKNOWN_ERROR;
1265         }
1266
1267         return ECORE_SUCCESS;
1268 }
1269
1270 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1271                                   struct ecore_ptt *p_main_ptt)
1272 {
1273         /* Read shadow of current MFW mailbox */
1274         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1275         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1276                     p_hwfn->mcp_info->mfw_mb_cur,
1277                     p_hwfn->mcp_info->mfw_mb_length);
1278 }
1279
1280 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1281                                    struct ecore_tunn_start_params *p_tunn,
1282                                    bool b_hw_start,
1283                                    enum ecore_int_mode int_mode,
1284                                    bool allow_npar_tx_switch,
1285                                    const u8 *bin_fw_data)
1286 {
1287         enum _ecore_status_t rc, mfw_rc;
1288         u32 load_code, param;
1289         int i, j;
1290
1291         if (IS_PF(p_dev)) {
1292                 rc = ecore_init_fw_data(p_dev, bin_fw_data);
1293                 if (rc != ECORE_SUCCESS)
1294                         return rc;
1295         }
1296
1297         for_each_hwfn(p_dev, i) {
1298                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1299
1300                 if (IS_VF(p_dev)) {
1301                         rc = ecore_vf_pf_init(p_hwfn);
1302                         if (rc)
1303                                 return rc;
1304                         continue;
1305                 }
1306
1307                 /* Enable DMAE in PXP */
1308                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1309
1310                 ecore_calc_hw_mode(p_hwfn);
1311                 /* @@@TBD need to add here:
1312                  * Check for fan failure
1313                  * Prev_unload
1314                  */
1315                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1316                 if (rc) {
1317                         DP_NOTICE(p_hwfn, true,
1318                                   "Failed sending LOAD_REQ command\n");
1319                         return rc;
1320                 }
1321
1322                 /* CQ75580:
1323                  * When coming back from hiberbate state, the registers from
1324                  * which shadow is read initially are not initialized. It turns
1325                  * out that these registers get initialized during the call to
1326                  * ecore_mcp_load_req request. So we need to reread them here
1327                  * to get the proper shadow register value.
1328                  * Note: This is a workaround for the missinginig MFW
1329                  * initialization. It may be removed once the implementation
1330                  * is done.
1331                  */
1332                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1333
1334                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1335                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1336                            rc, load_code);
1337
1338                 /* Only relevant for recovery:
1339                  * Clear the indication after the LOAD_REQ command is responded
1340                  * by the MFW.
1341                  */
1342                 p_dev->recov_in_prog = false;
1343
1344                 p_hwfn->first_on_engine = (load_code ==
1345                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1346
1347                 switch (load_code) {
1348                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1349                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1350                                                   p_hwfn->hw_info.hw_mode);
1351                         if (rc)
1352                                 break;
1353                         /* Fall into */
1354                 case FW_MSG_CODE_DRV_LOAD_PORT:
1355                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1356                                                 p_hwfn->hw_info.hw_mode);
1357                         if (rc)
1358                                 break;
1359
1360 #ifndef REAL_ASIC_ONLY
1361                         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
1362                                 struct init_nig_pri_tc_map_req tc_map;
1363
1364                                 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map));
1365
1366                                 /* remove this once flow control is
1367                                  * implemented
1368                                  */
1369                                 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) {
1370                                         tc_map.pri[j].tc_id = 0;
1371                                         tc_map.pri[j].valid = 1;
1372                                 }
1373                                 ecore_init_nig_pri_tc_map(p_hwfn,
1374                                                           p_hwfn->p_main_ptt,
1375                                                           &tc_map);
1376                         }
1377 #endif
1378                         /* Fall into */
1379                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1380                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1381                                               p_tunn, p_hwfn->hw_info.hw_mode,
1382                                               b_hw_start, int_mode,
1383                                               allow_npar_tx_switch);
1384                         break;
1385                 default:
1386                         rc = ECORE_NOTIMPL;
1387                         break;
1388                 }
1389
1390                 if (rc != ECORE_SUCCESS)
1391                         DP_NOTICE(p_hwfn, true,
1392                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1393                                   load_code, rc);
1394
1395                 /* ACK mfw regardless of success or failure of initialization */
1396                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1397                                        DRV_MSG_CODE_LOAD_DONE,
1398                                        0, &load_code, &param);
1399                 if (rc != ECORE_SUCCESS)
1400                         return rc;
1401                 if (mfw_rc != ECORE_SUCCESS) {
1402                         DP_NOTICE(p_hwfn, true,
1403                                   "Failed sending LOAD_DONE command\n");
1404                         return mfw_rc;
1405                 }
1406
1407                 /* send DCBX attention request command */
1408                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1409                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1410                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1411                                        DRV_MSG_CODE_SET_DCBX,
1412                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1413                                        &load_code, &param);
1414                 if (mfw_rc != ECORE_SUCCESS) {
1415                         DP_NOTICE(p_hwfn, true,
1416                                   "Failed to send DCBX attention request\n");
1417                         return mfw_rc;
1418                 }
1419
1420                 p_hwfn->hw_init_done = true;
1421         }
1422
1423         return ECORE_SUCCESS;
1424 }
1425
1426 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1427 static OSAL_INLINE void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1428                                  struct ecore_hwfn *p_hwfn,
1429                                  struct ecore_ptt *p_ptt)
1430 {
1431         int i;
1432
1433         /* close timers */
1434         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1435         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1436         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1437                                                                         i++) {
1438                 if ((!ecore_rd(p_hwfn, p_ptt,
1439                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1440                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1441                         break;
1442
1443                 /* Dependent on number of connection/tasks, possibly
1444                  * 1ms sleep is required between polls
1445                  */
1446                 OSAL_MSLEEP(1);
1447         }
1448         if (i == ECORE_HW_STOP_RETRY_LIMIT)
1449                 DP_NOTICE(p_hwfn, true,
1450                           "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1451                           (u8)ecore_rd(p_hwfn, p_ptt,
1452                                         TM_REG_PF_SCAN_ACTIVE_CONN),
1453                           (u8)ecore_rd(p_hwfn, p_ptt,
1454                                         TM_REG_PF_SCAN_ACTIVE_TASK));
1455 }
1456
1457 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1458 {
1459         int j;
1460
1461         for_each_hwfn(p_dev, j) {
1462                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1463                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1464
1465                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1466         }
1467 }
1468
1469 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1470 {
1471         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1472         int j;
1473
1474         for_each_hwfn(p_dev, j) {
1475                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1476                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1477
1478                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1479
1480                 if (IS_VF(p_dev)) {
1481                         ecore_vf_pf_int_cleanup(p_hwfn);
1482                         continue;
1483                 }
1484
1485                 /* mark the hw as uninitialized... */
1486                 p_hwfn->hw_init_done = false;
1487
1488                 rc = ecore_sp_pf_stop(p_hwfn);
1489                 if (rc)
1490                         DP_NOTICE(p_hwfn, true,
1491                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1492
1493                 /* perform debug action after PF stop was sent */
1494                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1495
1496                 /* close NIG to BRB gate */
1497                 ecore_wr(p_hwfn, p_ptt,
1498                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1499
1500                 /* close parser */
1501                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1502                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1503                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1504
1505                 /* @@@TBD - clean transmission queues (5.b) */
1506                 /* @@@TBD - clean BTB (5.c) */
1507
1508                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1509
1510                 /* @@@TBD - verify DMAE requests are done (8) */
1511
1512                 /* Disable Attention Generation */
1513                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1514                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1515                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1516                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1517                 /* Need to wait 1ms to guarantee SBs are cleared */
1518                 OSAL_MSLEEP(1);
1519         }
1520
1521         if (IS_PF(p_dev)) {
1522                 /* Disable DMAE in PXP - in CMT, this should only be done for
1523                  * first hw-function, and only after all transactions have
1524                  * stopped for all active hw-functions.
1525                  */
1526                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1527                                              p_dev->hwfns[0].p_main_ptt, false);
1528                 if (t_rc != ECORE_SUCCESS)
1529                         rc = t_rc;
1530         }
1531
1532         return rc;
1533 }
1534
1535 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1536 {
1537         int j;
1538
1539         for_each_hwfn(p_dev, j) {
1540                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1541                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1542
1543                 if (IS_VF(p_dev)) {
1544                         ecore_vf_pf_int_cleanup(p_hwfn);
1545                         continue;
1546                 }
1547
1548                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1549                            "Shutting down the fastpath\n");
1550
1551                 ecore_wr(p_hwfn, p_ptt,
1552                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1553
1554                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1555                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1556                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1557
1558                 /* @@@TBD - clean transmission queues (5.b) */
1559                 /* @@@TBD - clean BTB (5.c) */
1560
1561                 /* @@@TBD - verify DMAE requests are done (8) */
1562
1563                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1564                 /* Need to wait 1ms to guarantee SBs are cleared */
1565                 OSAL_MSLEEP(1);
1566         }
1567 }
1568
1569 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1570 {
1571         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1572
1573         if (IS_VF(p_hwfn->p_dev))
1574                 return;
1575
1576         /* Re-open incoming traffic */
1577         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1578                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1579 }
1580
1581 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1582                                              struct ecore_ptt *p_ptt, u32 reg,
1583                                              bool expected)
1584 {
1585         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1586
1587         if (assert_val != expected) {
1588                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1589                           reg, expected);
1590                 return ECORE_UNKNOWN_ERROR;
1591         }
1592
1593         return 0;
1594 }
1595
1596 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1597 {
1598         enum _ecore_status_t rc = ECORE_SUCCESS;
1599         u32 unload_resp, unload_param;
1600         int i;
1601
1602         for_each_hwfn(p_dev, i) {
1603                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1604
1605                 if (IS_VF(p_dev)) {
1606                         rc = ecore_vf_pf_reset(p_hwfn);
1607                         if (rc)
1608                                 return rc;
1609                         continue;
1610                 }
1611
1612                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1613
1614                 /* Check for incorrect states */
1615                 if (!p_dev->recov_in_prog) {
1616                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1617                                          QM_REG_USG_CNT_PF_TX, 0);
1618                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1619                                          QM_REG_USG_CNT_PF_OTHER, 0);
1620                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1621                 }
1622
1623                 /* Disable PF in HW blocks */
1624                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1625                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1626                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1627                          TCFC_REG_STRONG_ENABLE_PF, 0);
1628                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1629                          CCFC_REG_STRONG_ENABLE_PF, 0);
1630
1631                 if (p_dev->recov_in_prog) {
1632                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1633                                    "Recovery is in progress -> skip "
1634                                    "sending unload_req/done\n");
1635                         break;
1636                 }
1637
1638                 /* Send unload command to MCP */
1639                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1640                                    DRV_MSG_CODE_UNLOAD_REQ,
1641                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
1642                                    &unload_resp, &unload_param);
1643                 if (rc != ECORE_SUCCESS) {
1644                         DP_NOTICE(p_hwfn, true,
1645                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
1646                         /* @@TBD - what to do? for now, assume ENG. */
1647                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1648                 }
1649
1650                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1651                                    DRV_MSG_CODE_UNLOAD_DONE,
1652                                    0, &unload_resp, &unload_param);
1653                 if (rc != ECORE_SUCCESS) {
1654                         DP_NOTICE(p_hwfn,
1655                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
1656                         /* @@@TBD - Should it really ASSERT here ? */
1657                         return rc;
1658                 }
1659         }
1660
1661         return rc;
1662 }
1663
1664 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1665 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
1666 {
1667         ecore_ptt_pool_free(p_hwfn);
1668         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
1669 }
1670
1671 /* Setup bar access */
1672 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
1673 {
1674         /* clear indirect access */
1675         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1676         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1677         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1678         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1679
1680         /* Clean Previous errors if such exist */
1681         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1682                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1683
1684         /* enable internal target-read */
1685         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1686                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1687 }
1688
1689 static void get_function_id(struct ecore_hwfn *p_hwfn)
1690 {
1691         /* ME Register */
1692         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
1693                                                   PXP_PF_ME_OPAQUE_ADDR);
1694
1695         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1696
1697         /* Bits 16-19 from the ME registers are the pf_num */
1698         /* @@ @TBD - check, may be wrong after B0 implementation for CMT */
1699         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1700         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1701                                       PXP_CONCRETE_FID_PFID);
1702         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1703                                     PXP_CONCRETE_FID_PORT);
1704
1705         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1706                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1707                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
1708 }
1709
1710 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
1711 {
1712         u32 *feat_num = p_hwfn->hw_info.feat_num;
1713         int num_features = 1;
1714
1715         /* L2 Queues require each: 1 status block. 1 L2 queue */
1716         feat_num[ECORE_PF_L2_QUE] =
1717             OSAL_MIN_T(u32,
1718                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
1719                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
1720
1721         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1722                    "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1723                    feat_num[ECORE_PF_L2_QUE],
1724                    RESC_NUM(p_hwfn, ECORE_SB), num_features);
1725 }
1726
1727 /* @@@TBD MK RESC: This info is currently hard code and set as if we were MF
1728  * need to read it from shmem...
1729  */
1730 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn)
1731 {
1732         u32 *resc_start = p_hwfn->hw_info.resc_start;
1733         u8 num_funcs = p_hwfn->num_funcs_on_engine;
1734         u32 *resc_num = p_hwfn->hw_info.resc_num;
1735         int i, max_vf_vlan_filters;
1736         struct ecore_sb_cnt_info sb_cnt_info;
1737         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
1738
1739                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
1740
1741 #ifdef CONFIG_ECORE_SRIOV
1742         max_vf_vlan_filters = ECORE_ETH_MAX_VF_NUM_VLAN_FILTERS;
1743 #else
1744         max_vf_vlan_filters = 0;
1745 #endif
1746
1747                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1748         resc_num[ECORE_SB] = OSAL_MIN_T(u32,
1749                                         (MAX_SB_PER_PATH_BB / num_funcs),
1750                                         sb_cnt_info.sb_cnt);
1751
1752         resc_num[ECORE_L2_QUEUE] = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
1753                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
1754         resc_num[ECORE_VPORT] = (b_ah ? MAX_NUM_VPORTS_K2 :
1755                                  MAX_NUM_VPORTS_BB) / num_funcs;
1756         resc_num[ECORE_RSS_ENG] = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
1757                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
1758         resc_num[ECORE_PQ] = (b_ah ? MAX_QM_TX_QUEUES_K2 :
1759                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
1760         resc_num[ECORE_RL] = 8;
1761         resc_num[ECORE_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1762         resc_num[ECORE_VLAN] = (ETH_NUM_VLAN_FILTERS -
1763                                 max_vf_vlan_filters +
1764                                 1 /*For vlan0 */) / num_funcs;
1765
1766         /* TODO - there will be a problem in AH - there are only 11k lines */
1767         resc_num[ECORE_ILT] = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
1768                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
1769
1770 #ifndef ASIC_ONLY
1771         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1772                 /* Reduced build contains less PQs */
1773                 if (!(p_hwfn->p_dev->b_is_emul_full))
1774                         resc_num[ECORE_PQ] = 32;
1775
1776                 /* For AH emulation, since we have a possible maximal number of
1777                  * 16 enabled PFs, in case there are not enough ILT lines -
1778                  * allocate only first PF as RoCE and have all the other ETH
1779                  * only with less ILT lines.
1780                  */
1781                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
1782                         resc_num[ECORE_ILT] = resc_num[ECORE_ILT];
1783         }
1784 #endif
1785
1786         for (i = 0; i < ECORE_MAX_RESC; i++)
1787                 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1788
1789 #ifndef ASIC_ONLY
1790         /* Correct the common ILT calculation if PF0 has more */
1791         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
1792             p_hwfn->p_dev->b_is_emul_full &&
1793             p_hwfn->rel_pf_id && resc_num[ECORE_ILT])
1794                 resc_start[ECORE_ILT] += resc_num[ECORE_ILT];
1795 #endif
1796
1797         /* Sanity for ILT */
1798         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
1799             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
1800                 DP_NOTICE(p_hwfn, true,
1801                           "Can't assign ILT pages [%08x,...,%08x]\n",
1802                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
1803                                                                   ECORE_ILT) -
1804                           1);
1805                 return ECORE_INVAL;
1806         }
1807
1808         ecore_hw_set_feat(p_hwfn);
1809
1810         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1811                    "The numbers for each resource are:\n"
1812                    "SB = %d start = %d\n"
1813                    "L2_QUEUE = %d start = %d\n"
1814                    "VPORT = %d start = %d\n"
1815                    "PQ = %d start = %d\n"
1816                    "RL = %d start = %d\n"
1817                    "MAC = %d start = %d\n"
1818                    "VLAN = %d start = %d\n"
1819                    "ILT = %d start = %d\n"
1820                    "CMDQS_CQS = %d start = %d\n",
1821                    RESC_NUM(p_hwfn, ECORE_SB), RESC_START(p_hwfn, ECORE_SB),
1822                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
1823                    RESC_START(p_hwfn, ECORE_L2_QUEUE),
1824                    RESC_NUM(p_hwfn, ECORE_VPORT),
1825                    RESC_START(p_hwfn, ECORE_VPORT),
1826                    RESC_NUM(p_hwfn, ECORE_PQ), RESC_START(p_hwfn, ECORE_PQ),
1827                    RESC_NUM(p_hwfn, ECORE_RL), RESC_START(p_hwfn, ECORE_RL),
1828                    RESC_NUM(p_hwfn, ECORE_MAC), RESC_START(p_hwfn, ECORE_MAC),
1829                    RESC_NUM(p_hwfn, ECORE_VLAN),
1830                    RESC_START(p_hwfn, ECORE_VLAN),
1831                    RESC_NUM(p_hwfn, ECORE_ILT), RESC_START(p_hwfn, ECORE_ILT),
1832                    RESC_NUM(p_hwfn, ECORE_CMDQS_CQS),
1833                    RESC_START(p_hwfn, ECORE_CMDQS_CQS));
1834
1835         return ECORE_SUCCESS;
1836 }
1837
1838 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
1839                                                   struct ecore_ptt *p_ptt)
1840 {
1841         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1842         u32 port_cfg_addr, link_temp, device_capabilities;
1843         struct ecore_mcp_link_params *link;
1844
1845         /* Read global nvm_cfg address */
1846         u32 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1847
1848         /* Verify MCP has initialized it */
1849         if (nvm_cfg_addr == 0) {
1850                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
1851                 return ECORE_INVAL;
1852         }
1853
1854 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
1855         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1856
1857         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1858             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
1859                                                        core_cfg);
1860
1861         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
1862
1863         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1864                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1865         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G:
1866                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
1867                 break;
1868         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G:
1869                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
1870                 break;
1871         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G:
1872                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
1873                 break;
1874         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F:
1875                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
1876                 break;
1877         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E:
1878                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
1879                 break;
1880         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G:
1881                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
1882                 break;
1883         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G:
1884                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
1885                 break;
1886         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G:
1887                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
1888                 break;
1889         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G:
1890                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
1891                 break;
1892         default:
1893                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
1894                           core_cfg);
1895                 break;
1896         }
1897
1898         /* Read default link configuration */
1899         link = &p_hwfn->mcp_info->link_input;
1900         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1901             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1902         link_temp = ecore_rd(p_hwfn, p_ptt,
1903                              port_cfg_addr +
1904                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
1905         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1906         link->speed.advertised_speeds = link_temp;
1907
1908         link_temp = link->speed.advertised_speeds;
1909         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
1910
1911         link_temp = ecore_rd(p_hwfn, p_ptt,
1912                              port_cfg_addr +
1913                              OFFSETOF(struct nvm_cfg1_port, link_settings));
1914         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1915                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1916         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1917                 link->speed.autoneg = true;
1918                 break;
1919         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1920                 link->speed.forced_speed = 1000;
1921                 break;
1922         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1923                 link->speed.forced_speed = 10000;
1924                 break;
1925         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1926                 link->speed.forced_speed = 25000;
1927                 break;
1928         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1929                 link->speed.forced_speed = 40000;
1930                 break;
1931         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1932                 link->speed.forced_speed = 50000;
1933                 break;
1934         case NVM_CFG1_PORT_DRV_LINK_SPEED_100G:
1935                 link->speed.forced_speed = 100000;
1936                 break;
1937         default:
1938                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
1939         }
1940
1941         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1942         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1943         link->pause.autoneg = !!(link_temp &
1944                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1945         link->pause.forced_rx = !!(link_temp &
1946                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1947         link->pause.forced_tx = !!(link_temp &
1948                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1949         link->loopback_mode = 0;
1950
1951         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1952                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1953                    link->speed.forced_speed, link->speed.advertised_speeds,
1954                    link->speed.autoneg, link->pause.autoneg);
1955
1956         /* Read Multi-function information from shmem */
1957         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1958             OFFSETOF(struct nvm_cfg1, glob) +
1959             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
1960
1961         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
1962
1963         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1964             NVM_CFG1_GLOB_MF_MODE_OFFSET;
1965
1966         switch (mf_mode) {
1967         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1968                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
1969                 break;
1970         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1971                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
1972                 break;
1973         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1974                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
1975                 break;
1976         }
1977         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1978                 p_hwfn->p_dev->mf_mode);
1979
1980         /* Read Multi-function information from shmem */
1981         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1982             OFFSETOF(struct nvm_cfg1, glob) +
1983             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
1984
1985         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
1986         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1987                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
1988                              &p_hwfn->hw_info.device_capabilities);
1989
1990         return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1991 }
1992
1993 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
1994                                 struct ecore_ptt *p_ptt)
1995 {
1996         u8 num_funcs;
1997         u32 tmp, mask;
1998
1999         num_funcs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_PFS_K2
2000             : MAX_NUM_PFS_BB;
2001
2002         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2003          * in the other bits are selected.
2004          * Bits 1-15 are for functions 1-15, respectively, and their value is
2005          * '0' only for enabled functions (function 0 always exists and
2006          * enabled).
2007          * In case of CMT, only the "even" functions are enabled, and thus the
2008          * number of functions for both hwfns is learnt from the same bits.
2009          */
2010
2011         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2012         if (tmp & 0x1) {
2013                 if (ECORE_PATH_ID(p_hwfn) && p_hwfn->p_dev->num_hwfns == 1) {
2014                         num_funcs = 0;
2015                         mask = 0xaaaa;
2016                         } else {
2017                                 num_funcs = 1;
2018                         mask = 0x5554;
2019                 }
2020
2021                 tmp = (tmp ^ 0xffffffff) & mask;
2022                 while (tmp) {
2023                         if (tmp & 0x1)
2024                                 num_funcs++;
2025                         tmp >>= 0x1;
2026                 }
2027         }
2028
2029         p_hwfn->num_funcs_on_engine = num_funcs;
2030
2031 #ifndef ASIC_ONLY
2032         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2033                 DP_NOTICE(p_hwfn, false,
2034                           "FPGA: Limit number of PFs to 4 [would affect"
2035                           " resource allocation, needed for IOV]\n");
2036                 p_hwfn->num_funcs_on_engine = 4;
2037         }
2038 #endif
2039
2040         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "num_funcs_on_engine = %d\n",
2041                    p_hwfn->num_funcs_on_engine);
2042 }
2043
2044 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2045                                       struct ecore_ptt *p_ptt)
2046 {
2047         u32 port_mode;
2048
2049 #ifndef ASIC_ONLY
2050         /* Read the port mode */
2051         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2052                 port_mode = 4;
2053         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2054                  (p_hwfn->p_dev->num_hwfns > 1))
2055                 /* In CMT on emulation, assume 1 port */
2056                 port_mode = 1;
2057         else
2058 #endif
2059                 port_mode = ecore_rd(p_hwfn, p_ptt,
2060                                      CNIG_REG_NW_PORT_MODE_BB_B0);
2061
2062         if (port_mode < 3) {
2063                 p_hwfn->p_dev->num_ports_in_engines = 1;
2064         } else if (port_mode <= 5) {
2065                 p_hwfn->p_dev->num_ports_in_engines = 2;
2066         } else {
2067                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2068                           p_hwfn->p_dev->num_ports_in_engines);
2069
2070                 /* Default num_ports_in_engines to something */
2071                 p_hwfn->p_dev->num_ports_in_engines = 1;
2072         }
2073 }
2074
2075 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2076                                       struct ecore_ptt *p_ptt)
2077 {
2078         u32 port;
2079         int i;
2080
2081         p_hwfn->p_dev->num_ports_in_engines = 0;
2082
2083                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2084                         port = ecore_rd(p_hwfn, p_ptt,
2085                                         CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2086                         if (port & 1)
2087                                 p_hwfn->p_dev->num_ports_in_engines++;
2088                 }
2089 }
2090
2091 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2092                                    struct ecore_ptt *p_ptt)
2093 {
2094         if (ECORE_IS_BB(p_hwfn->p_dev))
2095                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2096         else
2097                 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2098 }
2099
2100 static enum _ecore_status_t
2101 ecore_get_hw_info(struct ecore_hwfn *p_hwfn,
2102                   struct ecore_ptt *p_ptt,
2103                   enum ecore_pci_personality personality)
2104 {
2105         enum _ecore_status_t rc;
2106
2107         rc = ecore_iov_hw_info(p_hwfn, p_hwfn->p_main_ptt);
2108                 if (rc)
2109                         return rc;
2110
2111         /* TODO In get_hw_info, amoungst others:
2112          * Get MCP FW revision and determine according to it the supported
2113          * featrues (e.g. DCB)
2114          * Get boot mode
2115          * ecore_get_pcie_width_speed, WOL capability.
2116          * Number of global CQ-s (for storage
2117          */
2118         ecore_hw_info_port_num(p_hwfn, p_ptt);
2119
2120 #ifndef ASIC_ONLY
2121         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2122 #endif
2123                 ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2124
2125         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2126         if (rc)
2127                 return rc;
2128
2129 #ifndef ASIC_ONLY
2130         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2131 #endif
2132                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2133                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2134 #ifndef ASIC_ONLY
2135         } else {
2136                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2137
2138                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2139                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2140         }
2141 #endif
2142
2143         if (ecore_mcp_is_init(p_hwfn)) {
2144                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2145                         p_hwfn->hw_info.ovlan =
2146                             p_hwfn->mcp_info->func_info.ovlan;
2147
2148                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2149         }
2150
2151         if (personality != ECORE_PCI_DEFAULT)
2152                 p_hwfn->hw_info.personality = personality;
2153         else if (ecore_mcp_is_init(p_hwfn))
2154                 p_hwfn->hw_info.personality =
2155                     p_hwfn->mcp_info->func_info.protocol;
2156
2157 #ifndef ASIC_ONLY
2158         /* To overcome ILT lack for emulation, until at least until we'll have
2159          * a definite answer from system about it, allow only PF0 to be RoCE.
2160          */
2161         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
2162                 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2163 #endif
2164
2165         ecore_get_num_funcs(p_hwfn, p_ptt);
2166
2167         /* Feat num is dependent on personality and on the number of functions
2168          * on the engine. Therefore it should be come after personality
2169          * initialization and after getting the number of functions.
2170          */
2171         return ecore_hw_get_resc(p_hwfn);
2172 }
2173
2174 /* @TMP - this should move to a proper .h */
2175 #define CHIP_NUM_AH                     0x8070
2176
2177 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2178 {
2179         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2180         u32 tmp;
2181
2182         /* Read Vendor Id / Device Id */
2183         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2184                                   &p_dev->vendor_id);
2185         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2186                                   &p_dev->device_id);
2187
2188         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2189                                          MISCS_REG_CHIP_NUM);
2190         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2191                                          MISCS_REG_CHIP_REV);
2192
2193         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2194
2195         /* Determine type */
2196         if (p_dev->device_id == CHIP_NUM_AH)
2197                 p_dev->type = ECORE_DEV_TYPE_AH;
2198         else
2199                 p_dev->type = ECORE_DEV_TYPE_BB;
2200
2201         /* Learn number of HW-functions */
2202         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2203                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2204
2205         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2206                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2207                 p_dev->num_hwfns = 2;
2208         } else {
2209                 p_dev->num_hwfns = 1;
2210         }
2211
2212 #ifndef ASIC_ONLY
2213         if (CHIP_REV_IS_EMUL(p_dev)) {
2214                 /* For some reason we have problems with this register
2215                  * in B0 emulation; Simply assume no CMT
2216                  */
2217                 DP_NOTICE(p_dev->hwfns, false,
2218                           "device on emul - assume no CMT\n");
2219                 p_dev->num_hwfns = 1;
2220         }
2221 #endif
2222
2223         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2224                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2225         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2226         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2227                                            MISCS_REG_CHIP_METAL);
2228         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2229         DP_INFO(p_dev->hwfns,
2230                 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2231                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2232                 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2233                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2234                 p_dev->chip_metal);
2235
2236         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2237                 DP_NOTICE(p_dev->hwfns, false,
2238                           "The chip type/rev (BB A0) is not supported!\n");
2239                 return ECORE_ABORTED;
2240         }
2241 #ifndef ASIC_ONLY
2242         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2243                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2244                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2245
2246         if (CHIP_REV_IS_EMUL(p_dev)) {
2247                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2248                                MISCS_REG_ECO_RESERVED);
2249                 if (tmp & (1 << 29)) {
2250                         DP_NOTICE(p_hwfn, false,
2251                                   "Emulation: Running on a FULL build\n");
2252                         p_dev->b_is_emul_full = true;
2253                 } else {
2254                         DP_NOTICE(p_hwfn, false,
2255                                   "Emulation: Running on a REDUCED build\n");
2256                 }
2257         }
2258 #endif
2259
2260         return ECORE_SUCCESS;
2261 }
2262
2263 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2264 {
2265         int j;
2266
2267         if (IS_VF(p_dev))
2268                 return;
2269
2270         for_each_hwfn(p_dev, j) {
2271                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2272
2273                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2274                            "Mark hw/fw uninitialized\n");
2275
2276                 p_hwfn->hw_init_done = false;
2277                 p_hwfn->first_on_engine = false;
2278         }
2279 }
2280
2281 static enum _ecore_status_t
2282 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2283                         void OSAL_IOMEM *p_regview,
2284                         void OSAL_IOMEM *p_doorbells,
2285                         enum ecore_pci_personality personality)
2286 {
2287         enum _ecore_status_t rc = ECORE_SUCCESS;
2288
2289         /* Split PCI bars evenly between hwfns */
2290         p_hwfn->regview = p_regview;
2291         p_hwfn->doorbells = p_doorbells;
2292
2293         /* Validate that chip access is feasible */
2294         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2295                 DP_ERR(p_hwfn,
2296                        "Reading the ME register returns all Fs;"
2297                        " Preventing further chip access\n");
2298                 return ECORE_INVAL;
2299         }
2300
2301         get_function_id(p_hwfn);
2302
2303         /* Allocate PTT pool */
2304         rc = ecore_ptt_pool_alloc(p_hwfn);
2305         if (rc) {
2306                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2307                 goto err0;
2308         }
2309
2310         /* Allocate the main PTT */
2311         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2312
2313         /* First hwfn learns basic information, e.g., number of hwfns */
2314         if (!p_hwfn->my_id) {
2315                 rc = ecore_get_dev_info(p_hwfn->p_dev);
2316                 if (rc != ECORE_SUCCESS)
2317                         goto err1;
2318         }
2319
2320         ecore_hw_hwfn_prepare(p_hwfn);
2321
2322         /* Initialize MCP structure */
2323         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2324         if (rc) {
2325                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
2326                 goto err1;
2327         }
2328
2329         /* Read the device configuration information from the HW and SHMEM */
2330         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2331         if (rc) {
2332                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
2333                 goto err2;
2334         }
2335
2336         /* Allocate the init RT array and initialize the init-ops engine */
2337         rc = ecore_init_alloc(p_hwfn);
2338         if (rc) {
2339                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
2340                 goto err2;
2341         }
2342 #ifndef ASIC_ONLY
2343         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2344                 DP_NOTICE(p_hwfn, false,
2345                           "FPGA: workaround; Prevent DMAE parities\n");
2346                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
2347
2348                 DP_NOTICE(p_hwfn, false,
2349                           "FPGA: workaround: Set VF bar0 size\n");
2350                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2351                          PGLUE_B_REG_VF_BAR0_SIZE, 4);
2352         }
2353 #endif
2354
2355         return rc;
2356  err2:
2357         ecore_mcp_free(p_hwfn);
2358  err1:
2359         ecore_hw_hwfn_free(p_hwfn);
2360  err0:
2361         return rc;
2362 }
2363
2364 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, int personality)
2365 {
2366         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2367         enum _ecore_status_t rc;
2368
2369         if (IS_VF(p_dev))
2370                 return ecore_vf_hw_prepare(p_dev);
2371
2372         /* Store the precompiled init data ptrs */
2373                 ecore_init_iro_array(p_dev);
2374
2375         /* Initialize the first hwfn - will learn number of hwfns */
2376         rc = ecore_hw_prepare_single(p_hwfn,
2377                                      p_dev->regview,
2378                                      p_dev->doorbells, personality);
2379         if (rc != ECORE_SUCCESS)
2380                 return rc;
2381
2382         personality = p_hwfn->hw_info.personality;
2383
2384         /* initialalize 2nd hwfn if necessary */
2385         if (p_dev->num_hwfns > 1) {
2386                 void OSAL_IOMEM *p_regview, *p_doorbell;
2387                 u8 OSAL_IOMEM *addr;
2388
2389                 /* adjust bar offset for second engine */
2390                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
2391                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
2392                 p_regview = (void OSAL_IOMEM *)addr;
2393
2394                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
2395                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
2396                 p_doorbell = (void OSAL_IOMEM *)addr;
2397
2398                 /* prepare second hw function */
2399                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
2400                                              p_doorbell, personality);
2401
2402                 /* in case of error, need to free the previously
2403                  * initialiazed hwfn 0
2404                  */
2405                 if (rc != ECORE_SUCCESS) {
2406                         ecore_init_free(p_hwfn);
2407                         ecore_mcp_free(p_hwfn);
2408                         ecore_hw_hwfn_free(p_hwfn);
2409                         return rc;
2410                 }
2411         }
2412
2413         return ECORE_SUCCESS;
2414 }
2415
2416 void ecore_hw_remove(struct ecore_dev *p_dev)
2417 {
2418         int i;
2419
2420         for_each_hwfn(p_dev, i) {
2421                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2422
2423                 if (IS_VF(p_dev)) {
2424                         ecore_vf_pf_release(p_hwfn);
2425                         continue;
2426                 }
2427
2428                 ecore_init_free(p_hwfn);
2429                 ecore_hw_hwfn_free(p_hwfn);
2430                 ecore_mcp_free(p_hwfn);
2431
2432                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
2433         }
2434 }
2435
2436 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
2437                                       struct ecore_chain *p_chain)
2438 {
2439         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
2440         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2441         struct ecore_chain_next *p_next;
2442         u32 size, i;
2443
2444         if (!p_virt)
2445                 return;
2446
2447         size = p_chain->elem_size * p_chain->usable_per_page;
2448
2449         for (i = 0; i < p_chain->page_cnt; i++) {
2450                 if (!p_virt)
2451                         break;
2452
2453                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
2454                 p_virt_next = p_next->next_virt;
2455                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2456
2457                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
2458                                        ECORE_CHAIN_PAGE_SIZE);
2459
2460                 p_virt = p_virt_next;
2461                 p_phys = p_phys_next;
2462         }
2463 }
2464
2465 static void ecore_chain_free_single(struct ecore_dev *p_dev,
2466                                     struct ecore_chain *p_chain)
2467 {
2468         if (!p_chain->p_virt_addr)
2469                 return;
2470
2471         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
2472                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
2473 }
2474
2475 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
2476                                  struct ecore_chain *p_chain)
2477 {
2478         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2479         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
2480         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
2481
2482         if (!pp_virt_addr_tbl)
2483                 return;
2484
2485         if (!p_chain->pbl.p_virt_table)
2486                 goto out;
2487
2488         for (i = 0; i < page_cnt; i++) {
2489                 if (!pp_virt_addr_tbl[i])
2490                         break;
2491
2492                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
2493                                        *(dma_addr_t *)p_pbl_virt,
2494                                        ECORE_CHAIN_PAGE_SIZE);
2495
2496                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2497         }
2498
2499         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2500         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
2501                                p_chain->pbl.p_phys_table, pbl_size);
2502  out:
2503         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
2504 }
2505
2506 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2507 {
2508         switch (p_chain->mode) {
2509         case ECORE_CHAIN_MODE_NEXT_PTR:
2510                 ecore_chain_free_next_ptr(p_dev, p_chain);
2511                 break;
2512         case ECORE_CHAIN_MODE_SINGLE:
2513                 ecore_chain_free_single(p_dev, p_chain);
2514                 break;
2515         case ECORE_CHAIN_MODE_PBL:
2516                 ecore_chain_free_pbl(p_dev, p_chain);
2517                 break;
2518         }
2519 }
2520
2521 static enum _ecore_status_t
2522 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
2523                                enum ecore_chain_cnt_type cnt_type,
2524                                osal_size_t elem_size, u32 page_cnt)
2525 {
2526         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2527
2528         /* The actual chain size can be larger than the maximal possible value
2529          * after rounding up the requested elements number to pages, and after
2530          * taking into acount the unusuable elements (next-ptr elements).
2531          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2532          * size/capacity fields are of a u32 type.
2533          */
2534         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
2535              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
2536             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
2537              chain_size > ECORE_U32_MAX)) {
2538                 DP_NOTICE(p_dev, true,
2539                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
2540                           (unsigned long)chain_size);
2541                 return ECORE_INVAL;
2542         }
2543
2544         return ECORE_SUCCESS;
2545 }
2546
2547 static enum _ecore_status_t
2548 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2549 {
2550         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
2551         dma_addr_t p_phys = 0;
2552         u32 i;
2553
2554         for (i = 0; i < p_chain->page_cnt; i++) {
2555                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2556                                                  ECORE_CHAIN_PAGE_SIZE);
2557                 if (!p_virt) {
2558                         DP_NOTICE(p_dev, true,
2559                                   "Failed to allocate chain memory\n");
2560                         return ECORE_NOMEM;
2561                 }
2562
2563                 if (i == 0) {
2564                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
2565                         ecore_chain_reset(p_chain);
2566                 } else {
2567                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2568                                                        p_virt, p_phys);
2569                 }
2570
2571                 p_virt_prev = p_virt;
2572         }
2573         /* Last page's next element should point to the beginning of the
2574          * chain.
2575          */
2576         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2577                                        p_chain->p_virt_addr,
2578                                        p_chain->p_phys_addr);
2579
2580         return ECORE_SUCCESS;
2581 }
2582
2583 static enum _ecore_status_t
2584 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2585 {
2586         void *p_virt = OSAL_NULL;
2587         dma_addr_t p_phys = 0;
2588
2589         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
2590         if (!p_virt) {
2591                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
2592                 return ECORE_NOMEM;
2593         }
2594
2595         ecore_chain_init_mem(p_chain, p_virt, p_phys);
2596         ecore_chain_reset(p_chain);
2597
2598         return ECORE_SUCCESS;
2599 }
2600
2601 static enum _ecore_status_t ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
2602                                                   struct ecore_chain *p_chain)
2603 {
2604         void *p_virt = OSAL_NULL;
2605         u8 *p_pbl_virt = OSAL_NULL;
2606         void **pp_virt_addr_tbl = OSAL_NULL;
2607         dma_addr_t p_phys = 0, p_pbl_phys = 0;
2608         u32 page_cnt = p_chain->page_cnt, size, i;
2609
2610         size = page_cnt * sizeof(*pp_virt_addr_tbl);
2611         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
2612         if (!pp_virt_addr_tbl) {
2613                 DP_NOTICE(p_dev, true,
2614                           "Failed to allocate memory for the chain"
2615                           " virtual addresses table\n");
2616                 return ECORE_NOMEM;
2617         }
2618         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
2619
2620         /* The allocation of the PBL table is done with its full size, since it
2621          * is expected to be successive.
2622          */
2623         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2624         p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
2625         if (!p_pbl_virt) {
2626                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
2627                 return ECORE_NOMEM;
2628         }
2629
2630         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2631                                  pp_virt_addr_tbl);
2632
2633         for (i = 0; i < page_cnt; i++) {
2634                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2635                                                  ECORE_CHAIN_PAGE_SIZE);
2636                 if (!p_virt) {
2637                         DP_NOTICE(p_dev, true,
2638                                   "Failed to allocate chain memory\n");
2639                         return ECORE_NOMEM;
2640                 }
2641
2642                 if (i == 0) {
2643                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
2644                         ecore_chain_reset(p_chain);
2645                 }
2646
2647                 /* Fill the PBL table with the physical address of the page */
2648                 *(dma_addr_t *)p_pbl_virt = p_phys;
2649                 /* Keep the virtual address of the page */
2650                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2651
2652                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2653         }
2654
2655         return ECORE_SUCCESS;
2656 }
2657
2658 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
2659                                        enum ecore_chain_use_mode intended_use,
2660                                        enum ecore_chain_mode mode,
2661                                        enum ecore_chain_cnt_type cnt_type,
2662                                        u32 num_elems, osal_size_t elem_size,
2663                                        struct ecore_chain *p_chain)
2664 {
2665         u32 page_cnt;
2666         enum _ecore_status_t rc = ECORE_SUCCESS;
2667
2668         if (mode == ECORE_CHAIN_MODE_SINGLE)
2669                 page_cnt = 1;
2670         else
2671                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2672
2673         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
2674                                             page_cnt);
2675         if (rc) {
2676                 DP_NOTICE(p_dev, true,
2677                           "Cannot allocate a chain with the given arguments:\n"
2678                           " [use_mode %d, mode %d, cnt_type %d, num_elems %d,"
2679                           " elem_size %zu]\n",
2680                           intended_use, mode, cnt_type, num_elems, elem_size);
2681                 return rc;
2682         }
2683
2684         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
2685                                 mode, cnt_type);
2686
2687         switch (mode) {
2688         case ECORE_CHAIN_MODE_NEXT_PTR:
2689                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
2690                 break;
2691         case ECORE_CHAIN_MODE_SINGLE:
2692                 rc = ecore_chain_alloc_single(p_dev, p_chain);
2693                 break;
2694         case ECORE_CHAIN_MODE_PBL:
2695                 rc = ecore_chain_alloc_pbl(p_dev, p_chain);
2696                 break;
2697         }
2698         if (rc)
2699                 goto nomem;
2700
2701         return ECORE_SUCCESS;
2702
2703  nomem:
2704         ecore_chain_free(p_dev, p_chain);
2705         return rc;
2706 }
2707
2708 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
2709                                        u16 src_id, u16 *dst_id)
2710 {
2711         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
2712                 u16 min, max;
2713
2714                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
2715                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
2716                 DP_NOTICE(p_hwfn, true,
2717                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2718                           src_id, min, max);
2719
2720                 return ECORE_INVAL;
2721         }
2722
2723         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
2724
2725         return ECORE_SUCCESS;
2726 }
2727
2728 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
2729                                     u8 src_id, u8 *dst_id)
2730 {
2731         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
2732                 u8 min, max;
2733
2734                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
2735                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
2736                 DP_NOTICE(p_hwfn, true,
2737                           "vport id [%d] is not valid, available indices [%d - %d]\n",
2738                           src_id, min, max);
2739
2740                 return ECORE_INVAL;
2741         }
2742
2743         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
2744
2745         return ECORE_SUCCESS;
2746 }
2747
2748 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
2749                                       u8 src_id, u8 *dst_id)
2750 {
2751         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
2752                 u8 min, max;
2753
2754                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
2755                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
2756                 DP_NOTICE(p_hwfn, true,
2757                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2758                           src_id, min, max);
2759
2760                 return ECORE_INVAL;
2761         }
2762
2763         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
2764
2765         return ECORE_SUCCESS;
2766 }
2767
2768 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
2769                                               struct ecore_ptt *p_ptt,
2770                                               u8 *p_filter)
2771 {
2772         u32 high, low, en;
2773         int i;
2774
2775         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2776                 return ECORE_SUCCESS;
2777
2778         high = p_filter[1] | (p_filter[0] << 8);
2779         low = p_filter[5] | (p_filter[4] << 8) |
2780             (p_filter[3] << 16) | (p_filter[2] << 24);
2781
2782         /* Find a free entry and utilize it */
2783         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2784                 en = ecore_rd(p_hwfn, p_ptt,
2785                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2786                 if (en)
2787                         continue;
2788                 ecore_wr(p_hwfn, p_ptt,
2789                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2790                          2 * i * sizeof(u32), low);
2791                 ecore_wr(p_hwfn, p_ptt,
2792                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2793                          (2 * i + 1) * sizeof(u32), high);
2794                 ecore_wr(p_hwfn, p_ptt,
2795                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2796                 ecore_wr(p_hwfn, p_ptt,
2797                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2798                          i * sizeof(u32), 0);
2799                 ecore_wr(p_hwfn, p_ptt,
2800                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2801                 break;
2802         }
2803         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2804                 DP_NOTICE(p_hwfn, false,
2805                           "Failed to find an empty LLH filter to utilize\n");
2806                 return ECORE_INVAL;
2807         }
2808
2809         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2810                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
2811                    p_filter[0], p_filter[1], p_filter[2],
2812                    p_filter[3], p_filter[4], p_filter[5], i);
2813
2814         return ECORE_SUCCESS;
2815 }
2816
2817 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
2818                                  struct ecore_ptt *p_ptt, u8 *p_filter)
2819 {
2820         u32 high, low;
2821         int i;
2822
2823         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2824                 return;
2825
2826         high = p_filter[1] | (p_filter[0] << 8);
2827         low = p_filter[5] | (p_filter[4] << 8) |
2828             (p_filter[3] << 16) | (p_filter[2] << 24);
2829
2830         /* Find the entry and clean it */
2831         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2832                 if (ecore_rd(p_hwfn, p_ptt,
2833                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2834                              2 * i * sizeof(u32)) != low)
2835                         continue;
2836                 if (ecore_rd(p_hwfn, p_ptt,
2837                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2838                              (2 * i + 1) * sizeof(u32)) != high)
2839                         continue;
2840
2841                 ecore_wr(p_hwfn, p_ptt,
2842                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2843                 ecore_wr(p_hwfn, p_ptt,
2844                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2845                          2 * i * sizeof(u32), 0);
2846                 ecore_wr(p_hwfn, p_ptt,
2847                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2848                          (2 * i + 1) * sizeof(u32), 0);
2849                 break;
2850         }
2851         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2852                 DP_NOTICE(p_hwfn, false,
2853                           "Tried to remove a non-configured filter\n");
2854 }
2855
2856 enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn,
2857                               struct ecore_ptt *p_ptt,
2858                                                     u16 filter)
2859 {
2860         u32 high, low, en;
2861         int i;
2862
2863         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2864                 return ECORE_SUCCESS;
2865
2866         high = filter;
2867         low = 0;
2868
2869         /* Find a free entry and utilize it */
2870         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2871                 en = ecore_rd(p_hwfn, p_ptt,
2872                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2873                 if (en)
2874                         continue;
2875                 ecore_wr(p_hwfn, p_ptt,
2876                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2877                          2 * i * sizeof(u32), low);
2878                 ecore_wr(p_hwfn, p_ptt,
2879                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2880                          (2 * i + 1) * sizeof(u32), high);
2881                 ecore_wr(p_hwfn, p_ptt,
2882                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
2883                 ecore_wr(p_hwfn, p_ptt,
2884                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2885                          i * sizeof(u32), 1);
2886                 ecore_wr(p_hwfn, p_ptt,
2887                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2888                 break;
2889         }
2890         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2891                 DP_NOTICE(p_hwfn, false,
2892                           "Failed to find an empty LLH filter to utilize\n");
2893                 return ECORE_INVAL;
2894         }
2895
2896                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2897                    "ETH type: %x is added at %d\n", filter, i);
2898
2899         return ECORE_SUCCESS;
2900 }
2901
2902 void ecore_llh_remove_ethertype_filter(struct ecore_hwfn *p_hwfn,
2903                                        struct ecore_ptt *p_ptt, u16 filter)
2904 {
2905         u32 high, low;
2906         int i;
2907
2908         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2909                 return;
2910
2911         high = filter;
2912         low = 0;
2913
2914         /* Find the entry and clean it */
2915         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2916                 if (ecore_rd(p_hwfn, p_ptt,
2917                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2918                              2 * i * sizeof(u32)) != low)
2919                         continue;
2920                 if (ecore_rd(p_hwfn, p_ptt,
2921                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2922                              (2 * i + 1) * sizeof(u32)) != high)
2923                         continue;
2924
2925                 ecore_wr(p_hwfn, p_ptt,
2926                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2927                 ecore_wr(p_hwfn, p_ptt,
2928                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2929                          2 * i * sizeof(u32), 0);
2930                 ecore_wr(p_hwfn, p_ptt,
2931                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2932                          (2 * i + 1) * sizeof(u32), 0);
2933                 break;
2934         }
2935         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2936                 DP_NOTICE(p_hwfn, false,
2937                           "Tried to remove a non-configured filter\n");
2938 }
2939
2940 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
2941                                  struct ecore_ptt *p_ptt)
2942 {
2943         int i;
2944
2945         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2946                 return;
2947
2948         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2949                 ecore_wr(p_hwfn, p_ptt,
2950                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2951                 ecore_wr(p_hwfn, p_ptt,
2952                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2953                          2 * i * sizeof(u32), 0);
2954                 ecore_wr(p_hwfn, p_ptt,
2955                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2956                          (2 * i + 1) * sizeof(u32), 0);
2957         }
2958 }
2959
2960 enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn,
2961                                   struct ecore_ptt *p_ptt)
2962 {
2963         u32 reg_tbl[] = {
2964                 BRB_REG_HEADER_SIZE,
2965                 BTB_REG_HEADER_SIZE,
2966                 CAU_REG_LONG_TIMEOUT_THRESHOLD,
2967                 CCFC_REG_ACTIVITY_COUNTER,
2968                 CDU_REG_CID_ADDR_PARAMS,
2969                 DBG_REG_CLIENT_ENABLE,
2970                 DMAE_REG_INIT,
2971                 DORQ_REG_IFEN,
2972                 GRC_REG_TIMEOUT_EN,
2973                 IGU_REG_BLOCK_CONFIGURATION,
2974                 MCM_REG_INIT,
2975                 MCP2_REG_DBG_DWORD_ENABLE,
2976                 MISC_REG_PORT_MODE,
2977                 MISCS_REG_CLK_100G_MODE,
2978                 MSDM_REG_ENABLE_IN1,
2979                 MSEM_REG_ENABLE_IN,
2980                 NIG_REG_CM_HDR,
2981                 NCSI_REG_CONFIG,
2982                 PBF_REG_INIT,
2983                 PTU_REG_ATC_INIT_ARRAY,
2984                 PCM_REG_INIT,
2985                 PGLUE_B_REG_ADMIN_PER_PF_REGION,
2986                 PRM_REG_DISABLE_PRM,
2987                 PRS_REG_SOFT_RST,
2988                 PSDM_REG_ENABLE_IN1,
2989                 PSEM_REG_ENABLE_IN,
2990                 PSWRQ_REG_DBG_SELECT,
2991                 PSWRQ2_REG_CDUT_P_SIZE,
2992                 PSWHST_REG_DISCARD_INTERNAL_WRITES,
2993                 PSWHST2_REG_DBGSYN_ALMOST_FULL_THR,
2994                 PSWRD_REG_DBG_SELECT,
2995                 PSWRD2_REG_CONF11,
2996                 PSWWR_REG_USDM_FULL_TH,
2997                 PSWWR2_REG_CDU_FULL_TH2,
2998                 QM_REG_MAXPQSIZE_0,
2999                 RSS_REG_RSS_INIT_EN,
3000                 RDIF_REG_STOP_ON_ERROR,
3001                 SRC_REG_SOFT_RST,
3002                 TCFC_REG_ACTIVITY_COUNTER,
3003                 TCM_REG_INIT,
3004                 TM_REG_PXP_READ_DATA_FIFO_INIT,
3005                 TSDM_REG_ENABLE_IN1,
3006                 TSEM_REG_ENABLE_IN,
3007                 TDIF_REG_STOP_ON_ERROR,
3008                 UCM_REG_INIT,
3009                 UMAC_REG_IPG_HD_BKP_CNTL_BB_B0,
3010                 USDM_REG_ENABLE_IN1,
3011                 USEM_REG_ENABLE_IN,
3012                 XCM_REG_INIT,
3013                 XSDM_REG_ENABLE_IN1,
3014                 XSEM_REG_ENABLE_IN,
3015                 YCM_REG_INIT,
3016                 YSDM_REG_ENABLE_IN1,
3017                 YSEM_REG_ENABLE_IN,
3018                 XYLD_REG_SCBD_STRICT_PRIO,
3019                 TMLD_REG_SCBD_STRICT_PRIO,
3020                 MULD_REG_SCBD_STRICT_PRIO,
3021                 YULD_REG_SCBD_STRICT_PRIO,
3022         };
3023         u32 test_val[] = { 0x0, 0x1 };
3024         u32 val, save_val, i, j;
3025
3026         for (i = 0; i < OSAL_ARRAY_SIZE(test_val); i++) {
3027                 for (j = 0; j < OSAL_ARRAY_SIZE(reg_tbl); j++) {
3028                         save_val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
3029                         ecore_wr(p_hwfn, p_ptt, reg_tbl[j], test_val[i]);
3030                         val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
3031                         /* Restore the original register's value */
3032                         ecore_wr(p_hwfn, p_ptt, reg_tbl[j], save_val);
3033                         if (val != test_val[i]) {
3034                                 DP_INFO(p_hwfn->p_dev,
3035                                         "offset 0x%x: val 0x%x != 0x%x\n",
3036                                         reg_tbl[j], val, test_val[i]);
3037                                 return ECORE_AGAIN;
3038                         }
3039                 }
3040         }
3041                 return ECORE_SUCCESS;
3042         }
3043
3044 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3045                                                struct ecore_ptt *p_ptt,
3046                                                u32 hw_addr, void *p_qzone,
3047                                                osal_size_t qzone_size,
3048                                                u8 timeset)
3049 {
3050         struct coalescing_timeset *p_coalesce_timeset;
3051
3052         if (IS_VF(p_hwfn->p_dev)) {
3053                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3054                 return ECORE_INVAL;
3055         }
3056
3057         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3058                 DP_NOTICE(p_hwfn, true,
3059                           "Coalescing configuration not enabled\n");
3060                 return ECORE_INVAL;
3061         }
3062
3063         OSAL_MEMSET(p_qzone, 0, qzone_size);
3064         p_coalesce_timeset = p_qzone;
3065         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_qzone, qzone_size);
3066
3067         return ECORE_SUCCESS;
3068 }
3069
3070 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3071                                             struct ecore_ptt *p_ptt,
3072                                             u8 coalesce, u8 qid)
3073 {
3074         struct ustorm_eth_queue_zone qzone;
3075         u16 fw_qid = 0;
3076         u32 address;
3077         u8 timeset;
3078         enum _ecore_status_t rc;
3079
3080         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3081         if (rc != ECORE_SUCCESS)
3082                 return rc;
3083
3084         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3085         /* Translate the coalescing time into a timeset, according to:
3086          * Timeout[Rx] = TimeSet[Rx] << (TimerRes[Rx] + 1)
3087          */
3088         timeset = coalesce >> (ECORE_CAU_DEF_RX_TIMER_RES + 1);
3089
3090         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
3091                                 sizeof(struct ustorm_eth_queue_zone), timeset);
3092         if (rc != ECORE_SUCCESS)
3093                 goto out;
3094
3095         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3096  out:
3097         return rc;
3098 }
3099
3100 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3101                                             struct ecore_ptt *p_ptt,
3102                                             u8 coalesce, u8 qid)
3103 {
3104         struct ystorm_eth_queue_zone qzone;
3105         u16 fw_qid = 0;
3106         u32 address;
3107         u8 timeset;
3108         enum _ecore_status_t rc;
3109
3110         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3111         if (rc != ECORE_SUCCESS)
3112                 return rc;
3113
3114         address = BAR0_MAP_REG_YSDM_RAM + YSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3115         /* Translate the coalescing time into a timeset, according to:
3116          * Timeout[Tx] = TimeSet[Tx] << (TimerRes[Tx] + 1)
3117          */
3118         timeset = coalesce >> (ECORE_CAU_DEF_TX_TIMER_RES + 1);
3119
3120         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
3121                                 sizeof(struct ystorm_eth_queue_zone), timeset);
3122         if (rc != ECORE_SUCCESS)
3123                 goto out;
3124
3125         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3126  out:
3127         return rc;
3128 }
3129
3130 /* Calculate final WFQ values for all vports and configure it.
3131  * After this configuration each vport must have
3132  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3133  */
3134 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3135                                                struct ecore_ptt *p_ptt,
3136                                                u32 min_pf_rate)
3137 {
3138         struct init_qm_vport_params *vport_params;
3139         int i, num_vports;
3140
3141         vport_params = p_hwfn->qm_info.qm_vport_params;
3142         num_vports = p_hwfn->qm_info.num_vports;
3143
3144         for (i = 0; i < num_vports; i++) {
3145                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3146
3147                 vport_params[i].vport_wfq =
3148                     (wfq_speed * ECORE_WFQ_UNIT) / min_pf_rate;
3149                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3150                                      vport_params[i].first_tx_pq_id,
3151                                      vport_params[i].vport_wfq);
3152         }
3153 }
3154
3155 static void
3156 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3157 {
3158         int i, num_vports;
3159         u32 min_speed;
3160
3161         num_vports = p_hwfn->qm_info.num_vports;
3162         min_speed = min_pf_rate / num_vports;
3163
3164         for (i = 0; i < num_vports; i++) {
3165                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3166                 p_hwfn->qm_info.wfq_data[i].default_min_speed = min_speed;
3167         }
3168 }
3169
3170 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3171                                              struct ecore_ptt *p_ptt,
3172                                              u32 min_pf_rate)
3173 {
3174         struct init_qm_vport_params *vport_params;
3175         int i, num_vports;
3176
3177         vport_params = p_hwfn->qm_info.qm_vport_params;
3178         num_vports = p_hwfn->qm_info.num_vports;
3179
3180         for (i = 0; i < num_vports; i++) {
3181                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3182                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3183                                      vport_params[i].first_tx_pq_id,
3184                                      vport_params[i].vport_wfq);
3185         }
3186 }
3187
3188 /* validate wfq for a given vport and required min rate */
3189 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3190                                                  u16 vport_id, u32 req_rate,
3191                                                  u32 min_pf_rate)
3192 {
3193         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3194         int non_requested_count = 0, req_count = 0, i, num_vports;
3195
3196         num_vports = p_hwfn->qm_info.num_vports;
3197
3198         /* Check pre-set data for some of the vports */
3199         for (i = 0; i < num_vports; i++) {
3200                 u32 tmp_speed;
3201
3202                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3203                         req_count++;
3204                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3205                         total_req_min_rate += tmp_speed;
3206                 }
3207         }
3208
3209         /* Include current vport data as well */
3210         req_count++;
3211         total_req_min_rate += req_rate;
3212         non_requested_count = p_hwfn->qm_info.num_vports - req_count;
3213
3214         /* validate possible error cases */
3215         if (req_rate > min_pf_rate) {
3216                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3217                            "Vport [%d] - Requested rate[%d Mbps] is greater"
3218                            " than configured PF min rate[%d Mbps]\n",
3219                            vport_id, req_rate, min_pf_rate);
3220                 return ECORE_INVAL;
3221         }
3222
3223         if (req_rate * ECORE_WFQ_UNIT / min_pf_rate < 1) {
3224                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3225                            "Vport [%d] - Requested rate[%d Mbps] is less than"
3226                            " one percent of configured PF min rate[%d Mbps]\n",
3227                            vport_id, req_rate, min_pf_rate);
3228                 return ECORE_INVAL;
3229         }
3230
3231         /* TBD - for number of vports greater than 100 */
3232         if (ECORE_WFQ_UNIT / p_hwfn->qm_info.num_vports < 1) {
3233                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3234                            "Number of vports are greater than 100\n");
3235                 return ECORE_INVAL;
3236         }
3237
3238         if (total_req_min_rate > min_pf_rate) {
3239                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3240                            "Total requested min rate for all vports[%d Mbps]"
3241                            "is greater than configured PF min rate[%d Mbps]\n",
3242                            total_req_min_rate, min_pf_rate);
3243                 return ECORE_INVAL;
3244         }
3245
3246         /* Data left for non requested vports */
3247         total_left_rate = min_pf_rate - total_req_min_rate;
3248         left_rate_per_vp = total_left_rate / non_requested_count;
3249
3250         /* validate if non requested get < 1% of min bw */
3251         if (left_rate_per_vp * ECORE_WFQ_UNIT / min_pf_rate < 1)
3252                 return ECORE_INVAL;
3253
3254         /* now req_rate for given vport passes all scenarios.
3255          * assign final wfq rates to all vports.
3256          */
3257         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3258         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3259
3260         for (i = 0; i < num_vports; i++) {
3261                 if (p_hwfn->qm_info.wfq_data[i].configured)
3262                         continue;
3263
3264                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3265         }
3266
3267         return ECORE_SUCCESS;
3268 }
3269
3270 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
3271                                        struct ecore_ptt *p_ptt,
3272                                        u16 vp_id, u32 rate)
3273 {
3274         struct ecore_mcp_link_state *p_link;
3275         int rc = ECORE_SUCCESS;
3276
3277         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
3278
3279         if (!p_link->min_pf_rate) {
3280                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3281                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3282                 return rc;
3283         }
3284
3285         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3286
3287         if (rc == ECORE_SUCCESS)
3288                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3289                                                    p_link->min_pf_rate);
3290         else
3291                 DP_NOTICE(p_hwfn, false,
3292                           "Validation failed while configuring min rate\n");
3293
3294         return rc;
3295 }
3296
3297 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
3298                                                    struct ecore_ptt *p_ptt,
3299                                                    u32 min_pf_rate)
3300 {
3301         int rc = ECORE_SUCCESS;
3302         bool use_wfq = false;
3303         u16 i, num_vports;
3304
3305         num_vports = p_hwfn->qm_info.num_vports;
3306
3307         /* Validate all pre configured vports for wfq */
3308         for (i = 0; i < num_vports; i++) {
3309                 if (p_hwfn->qm_info.wfq_data[i].configured) {
3310                         u32 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3311
3312                 use_wfq = true;
3313                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3314                         if (rc == ECORE_INVAL) {
3315                         DP_NOTICE(p_hwfn, false,
3316                                           "Validation failed while"
3317                                           " configuring min rate\n");
3318                         break;
3319                 }
3320         }
3321         }
3322
3323         if (rc == ECORE_SUCCESS && use_wfq)
3324                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3325         else
3326                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3327
3328         return rc;
3329 }
3330
3331 /* Main API for ecore clients to configure vport min rate.
3332  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3333  * rate - Speed in Mbps needs to be assigned to a given vport.
3334  */
3335 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
3336 {
3337         int i, rc = ECORE_INVAL;
3338
3339         /* TBD - for multiple hardware functions - that is 100 gig */
3340         if (p_dev->num_hwfns > 1) {
3341                 DP_NOTICE(p_dev, false,
3342                           "WFQ configuration is not supported for this device\n");
3343                 return rc;
3344         }
3345
3346         for_each_hwfn(p_dev, i) {
3347                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3348                 struct ecore_ptt *p_ptt;
3349
3350                 p_ptt = ecore_ptt_acquire(p_hwfn);
3351                 if (!p_ptt)
3352                         return ECORE_TIMEOUT;
3353
3354                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3355
3356                 if (rc != ECORE_SUCCESS) {
3357                         ecore_ptt_release(p_hwfn, p_ptt);
3358                         return rc;
3359                 }
3360
3361                 ecore_ptt_release(p_hwfn, p_ptt);
3362         }
3363
3364         return rc;
3365 }
3366
3367 /* API to configure WFQ from mcp link change */
3368 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
3369                                            u32 min_pf_rate)
3370 {
3371         int i;
3372
3373         /* TBD - for multiple hardware functions - that is 100 gig */
3374         if (p_dev->num_hwfns > 1) {
3375                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
3376                            "WFQ configuration is not supported for this device\n");
3377                 return;
3378         }
3379
3380         for_each_hwfn(p_dev, i) {
3381                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3382
3383                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3384                                                         p_hwfn->p_dpc_ptt,
3385                                                         min_pf_rate);
3386         }
3387 }
3388
3389 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
3390                                        struct ecore_ptt *p_ptt,
3391                                        struct ecore_mcp_link_state *p_link,
3392                                        u8 max_bw)
3393 {
3394         int rc = ECORE_SUCCESS;
3395
3396         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3397
3398         if (!p_link->line_speed)
3399                 return rc;
3400
3401         p_link->speed = (p_link->line_speed * max_bw) / 100;
3402
3403         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, p_link->speed);
3404
3405         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3406                    "Configured MAX bandwidth to be %08x Mb/sec\n",
3407                    p_link->speed);
3408
3409         return rc;
3410 }
3411
3412 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3413 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
3414 {
3415         int i, rc = ECORE_INVAL;
3416
3417         if (max_bw < 1 || max_bw > 100) {
3418                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
3419                 return rc;
3420         }
3421
3422         for_each_hwfn(p_dev, i) {
3423                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3424                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3425                 struct ecore_mcp_link_state *p_link;
3426                 struct ecore_ptt *p_ptt;
3427
3428                 p_link = &p_lead->mcp_info->link_output;
3429
3430                 p_ptt = ecore_ptt_acquire(p_hwfn);
3431                 if (!p_ptt)
3432                         return ECORE_TIMEOUT;
3433
3434                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3435                                                         p_link, max_bw);
3436                 if (rc != ECORE_SUCCESS) {
3437                         ecore_ptt_release(p_hwfn, p_ptt);
3438                         return rc;
3439                 }
3440
3441                 ecore_ptt_release(p_hwfn, p_ptt);
3442         }
3443
3444         return rc;
3445 }
3446
3447 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
3448                                        struct ecore_ptt *p_ptt,
3449                                        struct ecore_mcp_link_state *p_link,
3450                                        u8 min_bw)
3451 {
3452         int rc = ECORE_SUCCESS;
3453
3454         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3455
3456         if (!p_link->line_speed)
3457                 return rc;
3458
3459         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3460
3461         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3462
3463         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3464                    "Configured MIN bandwidth to be %d Mb/sec\n",
3465                    p_link->min_pf_rate);
3466
3467         return rc;
3468 }
3469
3470 /* Main API to configure PF min bandwidth where bw range is [1-100] */
3471 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
3472 {
3473         int i, rc = ECORE_INVAL;
3474
3475         if (min_bw < 1 || min_bw > 100) {
3476                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
3477                 return rc;
3478         }
3479
3480         for_each_hwfn(p_dev, i) {
3481                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3482                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3483                 struct ecore_mcp_link_state *p_link;
3484                 struct ecore_ptt *p_ptt;
3485
3486                 p_link = &p_lead->mcp_info->link_output;
3487
3488                 p_ptt = ecore_ptt_acquire(p_hwfn);
3489                 if (!p_ptt)
3490                         return ECORE_TIMEOUT;
3491
3492                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
3493                                                         p_link, min_bw);
3494                 if (rc != ECORE_SUCCESS) {
3495                         ecore_ptt_release(p_hwfn, p_ptt);
3496                         return rc;
3497                 }
3498
3499                 if (p_link->min_pf_rate) {
3500                         u32 min_rate = p_link->min_pf_rate;
3501
3502                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3503                                                                      p_ptt,
3504                                                                      min_rate);
3505                 }
3506
3507                 ecore_ptt_release(p_hwfn, p_ptt);
3508         }
3509
3510         return rc;
3511 }
3512
3513 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
3514 {
3515         struct ecore_mcp_link_state *p_link;
3516
3517         p_link = &p_hwfn->mcp_info->link_output;
3518
3519         if (p_link->min_pf_rate)
3520                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
3521                                                  p_link->min_pf_rate);
3522
3523         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
3524                     sizeof(*p_hwfn->qm_info.wfq_data) *
3525                     p_hwfn->qm_info.num_vports);
3526 }
3527
3528 int ecore_device_num_engines(struct ecore_dev *p_dev)
3529 {
3530         return ECORE_IS_BB(p_dev) ? 2 : 1;
3531 }
3532
3533 int ecore_device_num_ports(struct ecore_dev *p_dev)
3534 {
3535         /* in CMT always only one port */
3536         if (p_dev->num_hwfns > 1)
3537                 return 1;
3538
3539         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
3540 }