drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_attn_values.h"
  33
  34 /* Configurable */
  35 #define ECORE_MIN_DPIS          (4)     /* The minimal number of DPIs required
  36                                          * load the driver. The number was
  37                                          * arbitrarily set.
  38                                          */
  39
  40 /* Derived */
  41 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  42
  43 enum BAR_ID {
  44         BAR_ID_0,               /* used for GRC */
  45         BAR_ID_1                /* Used for doorbells */
  46 };
  47
  48 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  49 {
  50         u32 bar_reg = (bar_id == BAR_ID_0 ?
  51                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  52         u32 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  53
  54         /* The above registers were updated in the past only in CMT mode. Since
  55          * they were found to be useful MFW started updating them from 8.7.7.0.
  56          * In older MFW versions they are set to 0 which means disabled.
  57          */
  58         if (!val) {
  59                 if (p_hwfn->p_dev->num_hwfns > 1) {
  60                         DP_NOTICE(p_hwfn, false,
  61                                   "BAR size not configured. Assuming BAR"
  62                                   " size of 256kB for GRC and 512kB for DB\n");
  63                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  64                 }
  65
  66                 DP_NOTICE(p_hwfn, false,
  67                           "BAR size not configured. Assuming BAR"
  68                           " size of 512kB for GRC and 512kB for DB\n");
  69                 return 512 * 1024;
  70         }
  71
  72         return 1 << (val + 15);
  73 }
  74
  75 void ecore_init_dp(struct ecore_dev *p_dev,
  76                    u32 dp_module, u8 dp_level, void *dp_ctx)
  77 {
  78         u32 i;
  79
  80         p_dev->dp_level = dp_level;
  81         p_dev->dp_module = dp_module;
  82         p_dev->dp_ctx = dp_ctx;
  83         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  84                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
  85
  86                 p_hwfn->dp_level = dp_level;
  87                 p_hwfn->dp_module = dp_module;
  88                 p_hwfn->dp_ctx = dp_ctx;
  89         }
  90 }
  91
  92 void ecore_init_struct(struct ecore_dev *p_dev)
  93 {
  94         u8 i;
  95
  96         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
  97                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
  98
  99                 p_hwfn->p_dev = p_dev;
 100                 p_hwfn->my_id = i;
 101                 p_hwfn->b_active = false;
 102
 103                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 104                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 105         }
 106
 107         /* hwfn 0 is always active */
 108         p_dev->hwfns[0].b_active = true;
 109
 110         /* set the default cache alignment to 128 (may be overridden later) */
 111         p_dev->cache_shift = 7;
 112 }
 113
 114 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 115 {
 116         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 117
 118         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 119         qm_info->qm_pq_params = OSAL_NULL;
 120         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 121         qm_info->qm_vport_params = OSAL_NULL;
 122         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 123         qm_info->qm_port_params = OSAL_NULL;
 124         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 125         qm_info->wfq_data = OSAL_NULL;
 126 }
 127
 128 void ecore_resc_free(struct ecore_dev *p_dev)
 129 {
 130         int i;
 131
 132         if (IS_VF(p_dev))
 133                 return;
 134
 135         OSAL_FREE(p_dev, p_dev->fw_data);
 136         p_dev->fw_data = OSAL_NULL;
 137
 138         OSAL_FREE(p_dev, p_dev->reset_stats);
 139
 140         for_each_hwfn(p_dev, i) {
 141                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 142
 143                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 144                 p_hwfn->p_tx_cids = OSAL_NULL;
 145                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 146                 p_hwfn->p_rx_cids = OSAL_NULL;
 147         }
 148
 149         for_each_hwfn(p_dev, i) {
 150                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 151
 152                 ecore_cxt_mngr_free(p_hwfn);
 153                 ecore_qm_info_free(p_hwfn);
 154                 ecore_spq_free(p_hwfn);
 155                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 156                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 157                 ecore_int_free(p_hwfn);
 158                 ecore_iov_free(p_hwfn);
 159                 ecore_dmae_info_free(p_hwfn);
 160                 /* @@@TBD Flush work-queue ? */
 161         }
 162 }
 163
 164 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 165                                                bool b_sleepable)
 166 {
 167         u8 num_vports, vf_offset = 0, i, vport_id, num_ports;
 168         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 169         struct init_qm_port_params *p_qm_port;
 170         u16 num_pqs, multi_cos_tcs = 1;
 171 #ifdef CONFIG_ECORE_SRIOV
 172         u16 num_vfs = p_hwfn->p_dev->sriov_info.total_vfs;
 173 #else
 174         u16 num_vfs = 0;
 175 #endif
 176
 177         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 178
 179 #ifndef ASIC_ONLY
 180         /* @TMP - Don't allocate QM queues for VFs on emulation */
 181         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 182                 DP_NOTICE(p_hwfn, false,
 183                           "Emulation - skip configuring QM queues for VFs\n");
 184                 num_vfs = 0;
 185         }
 186 #endif
 187
 188         num_pqs = multi_cos_tcs + num_vfs + 1;  /* The '1' is for pure-LB */
 189         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 190
 191         /* Sanity checking that setup requires legal number of resources */
 192         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 193                 DP_ERR(p_hwfn,
 194                        "Need too many Physical queues - 0x%04x when"
 195                         " only %04x are available\n",
 196                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 197                 return ECORE_INVAL;
 198         }
 199
 200         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 201          * then special queues, then per-VF PQ.
 202          */
 203         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 204                                             b_sleepable ? GFP_KERNEL :
 205                                             GFP_ATOMIC,
 206                                             sizeof(struct init_qm_pq_params) *
 207                                             num_pqs);
 208         if (!qm_info->qm_pq_params)
 209                 goto alloc_err;
 210
 211         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 212                                                b_sleepable ? GFP_KERNEL :
 213                                                GFP_ATOMIC,
 214                                                sizeof(struct
 215                                                       init_qm_vport_params) *
 216                                                num_vports);
 217         if (!qm_info->qm_vport_params)
 218                 goto alloc_err;
 219
 220         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 221                                               b_sleepable ? GFP_KERNEL :
 222                                               GFP_ATOMIC,
 223                                               sizeof(struct init_qm_port_params)
 224                                               * MAX_NUM_PORTS);
 225         if (!qm_info->qm_port_params)
 226                 goto alloc_err;
 227
 228         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 229                                         b_sleepable ? GFP_KERNEL :
 230                                         GFP_ATOMIC,
 231                                         sizeof(struct ecore_wfq_data) *
 232                                         num_vports);
 233
 234         if (!qm_info->wfq_data)
 235                 goto alloc_err;
 236
 237         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 238
 239         /* First init per-TC PQs */
 240         for (i = 0; i < multi_cos_tcs; i++) {
 241                 struct init_qm_pq_params *params = &qm_info->qm_pq_params[i];
 242
 243                 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
 244                         params->vport_id = vport_id;
 245                         params->tc_id = p_hwfn->hw_info.non_offload_tc;
 246                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 247                 } else {
 248                         params->vport_id = vport_id;
 249                         params->tc_id = p_hwfn->hw_info.offload_tc;
 250                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 251                 }
 252         }
 253
 254         /* Then init pure-LB PQ */
 255         qm_info->pure_lb_pq = i;
 256         qm_info->qm_pq_params[i].vport_id =
 257             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 258         qm_info->qm_pq_params[i].tc_id = PURE_LB_TC;
 259         qm_info->qm_pq_params[i].wrr_group = 1;
 260         i++;
 261
 262         /* Then init per-VF PQs */
 263         vf_offset = i;
 264         for (i = 0; i < num_vfs; i++) {
 265                 /* First vport is used by the PF */
 266                 qm_info->qm_pq_params[vf_offset + i].vport_id = vport_id +
 267                     i + 1;
 268                 qm_info->qm_pq_params[vf_offset + i].tc_id =
 269                     p_hwfn->hw_info.non_offload_tc;
 270                 qm_info->qm_pq_params[vf_offset + i].wrr_group = 1;
 271         };
 272
 273         qm_info->vf_queues_offset = vf_offset;
 274         qm_info->num_pqs = num_pqs;
 275         qm_info->num_vports = num_vports;
 276
 277         /* Initialize qm port parameters */
 278         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 279         for (i = 0; i < num_ports; i++) {
 280                 p_qm_port = &qm_info->qm_port_params[i];
 281                 p_qm_port->active = 1;
 282                 if (num_ports == 4)
 283                         p_qm_port->num_active_phys_tcs = 2;
 284                 else
 285                         p_qm_port->num_active_phys_tcs = 5;
 286                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 287                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 288         }
 289
 290         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 291                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 292         else
 293                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 294
 295         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 296
 297         qm_info->num_vf_pqs = num_vfs;
 298         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 299
 300         for (i = 0; i < qm_info->num_vports; i++)
 301                 qm_info->qm_vport_params[i].vport_wfq = 1;
 302
 303         qm_info->pf_wfq = 0;
 304         qm_info->pf_rl = 0;
 305         qm_info->vport_rl_en = 1;
 306         qm_info->vport_wfq_en = 1;
 307
 308         return ECORE_SUCCESS;
 309
 310 alloc_err:
 311         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 312         ecore_qm_info_free(p_hwfn);
 313         return ECORE_NOMEM;
 314 }
 315
 316 /* This function reconfigures the QM pf on the fly.
 317  * For this purpose we:
 318  * 1. reconfigure the QM database
 319  * 2. set new values to runtime arrat
 320  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 321  * 4. activate init tool in QM_PF stage
 322  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 323  */
 324 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 325                                      struct ecore_ptt *p_ptt)
 326 {
 327         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 328         enum _ecore_status_t rc;
 329         bool b_rc;
 330
 331         /* qm_info is allocated in ecore_init_qm_info() which is already called
 332          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 333          * The allocated size may change each init, so we free it before next
 334          * allocation.
 335          */
 336         ecore_qm_info_free(p_hwfn);
 337
 338         /* initialize ecore's qm data structure */
 339         rc = ecore_init_qm_info(p_hwfn, false);
 340         if (rc != ECORE_SUCCESS)
 341                 return rc;
 342
 343         /* stop PF's qm queues */
 344         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 345                                       qm_info->start_pq, qm_info->num_pqs);
 346         if (!b_rc)
 347                 return ECORE_INVAL;
 348
 349         /* clear the QM_PF runtime phase leftovers from previous init */
 350         ecore_init_clear_rt_data(p_hwfn);
 351
 352         /* prepare QM portion of runtime array */
 353         ecore_qm_init_pf(p_hwfn);
 354
 355         /* activate init tool on runtime array */
 356         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 357                             p_hwfn->hw_info.hw_mode);
 358         if (rc != ECORE_SUCCESS)
 359                 return rc;
 360
 361         /* start PF's qm queues */
 362         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 363                                       qm_info->start_pq, qm_info->num_pqs);
 364         if (!rc)
 365                 return ECORE_INVAL;
 366
 367         return ECORE_SUCCESS;
 368 }
 369
 370 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 371 {
 372         enum _ecore_status_t rc = ECORE_SUCCESS;
 373         struct ecore_consq *p_consq;
 374         struct ecore_eq *p_eq;
 375         int i;
 376
 377         if (IS_VF(p_dev))
 378                 return rc;
 379
 380         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 381                                      sizeof(struct ecore_fw_data));
 382         if (!p_dev->fw_data)
 383                 return ECORE_NOMEM;
 384
 385         /* Allocate Memory for the Queue->CID mapping */
 386         for_each_hwfn(p_dev, i) {
 387                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 388
 389                 /* @@@TMP - resc management, change to actual required size */
 390                 int tx_size = sizeof(struct ecore_hw_cid_data) *
 391                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 392                 int rx_size = sizeof(struct ecore_hw_cid_data) *
 393                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 394
 395                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 396                                                 tx_size);
 397                 if (!p_hwfn->p_tx_cids) {
 398                         DP_NOTICE(p_hwfn, true,
 399                                   "Failed to allocate memory for Tx Cids\n");
 400                         goto alloc_no_mem;
 401                 }
 402
 403                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 404                                                 rx_size);
 405                 if (!p_hwfn->p_rx_cids) {
 406                         DP_NOTICE(p_hwfn, true,
 407                                   "Failed to allocate memory for Rx Cids\n");
 408                         goto alloc_no_mem;
 409                 }
 410         }
 411
 412         for_each_hwfn(p_dev, i) {
 413                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 414
 415                 /* First allocate the context manager structure */
 416                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 417                 if (rc)
 418                         goto alloc_err;
 419
 420                 /* Set the HW cid/tid numbers (in the contest manager)
 421                  * Must be done prior to any further computations.
 422                  */
 423                 rc = ecore_cxt_set_pf_params(p_hwfn);
 424                 if (rc)
 425                         goto alloc_err;
 426
 427                 /* Prepare and process QM requirements */
 428                 rc = ecore_init_qm_info(p_hwfn, true);
 429                 if (rc)
 430                         goto alloc_err;
 431
 432                 /* Compute the ILT client partition */
 433                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 434                 if (rc)
 435                         goto alloc_err;
 436
 437                 /* CID map / ILT shadow table / T2
 438                  * The talbes sizes are determined by the computations above
 439                  */
 440                 rc = ecore_cxt_tables_alloc(p_hwfn);
 441                 if (rc)
 442                         goto alloc_err;
 443
 444                 /* SPQ, must follow ILT because initializes SPQ context */
 445                 rc = ecore_spq_alloc(p_hwfn);
 446                 if (rc)
 447                         goto alloc_err;
 448
 449                 /* SP status block allocation */
 450                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 451                                                            RESERVED_PTT_DPC);
 452
 453                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 454                 if (rc)
 455                         goto alloc_err;
 456
 457                 rc = ecore_iov_alloc(p_hwfn);
 458                 if (rc)
 459                         goto alloc_err;
 460
 461                 /* EQ */
 462                 p_eq = ecore_eq_alloc(p_hwfn, 256);
 463                 if (!p_eq)
 464                         goto alloc_no_mem;
 465                 p_hwfn->p_eq = p_eq;
 466
 467                 p_consq = ecore_consq_alloc(p_hwfn);
 468                 if (!p_consq)
 469                         goto alloc_no_mem;
 470                 p_hwfn->p_consq = p_consq;
 471
 472                 /* DMA info initialization */
 473                 rc = ecore_dmae_info_alloc(p_hwfn);
 474                 if (rc) {
 475                         DP_NOTICE(p_hwfn, true,
 476                                   "Failed to allocate memory for"
 477                                   " dmae_info structure\n");
 478                         goto alloc_err;
 479                 }
 480         }
 481
 482         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 483                                          sizeof(struct ecore_eth_stats));
 484         if (!p_dev->reset_stats) {
 485                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 486                 goto alloc_no_mem;
 487         }
 488
 489         return ECORE_SUCCESS;
 490
 491 alloc_no_mem:
 492         rc = ECORE_NOMEM;
 493 alloc_err:
 494         ecore_resc_free(p_dev);
 495         return rc;
 496 }
 497
 498 void ecore_resc_setup(struct ecore_dev *p_dev)
 499 {
 500         int i;
 501
 502         if (IS_VF(p_dev))
 503                 return;
 504
 505         for_each_hwfn(p_dev, i) {
 506                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 507
 508                 ecore_cxt_mngr_setup(p_hwfn);
 509                 ecore_spq_setup(p_hwfn);
 510                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 511                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 512
 513                 /* Read shadow of current MFW mailbox */
 514                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 515                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 516                             p_hwfn->mcp_info->mfw_mb_cur,
 517                             p_hwfn->mcp_info->mfw_mb_length);
 518
 519                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 520
 521                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 522         }
 523 }
 524
 525 #define FINAL_CLEANUP_POLL_CNT  (100)
 526 #define FINAL_CLEANUP_POLL_TIME (10)
 527 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 528                                          struct ecore_ptt *p_ptt,
 529                                          u16 id, bool is_vf)
 530 {
 531         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 532         enum _ecore_status_t rc = ECORE_TIMEOUT;
 533
 534 #ifndef ASIC_ONLY
 535         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 536             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 537                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 538                 return ECORE_SUCCESS;
 539         }
 540 #endif
 541
 542         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 543             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 544
 545         if (is_vf)
 546                 id += 0x10;
 547
 548         command |= X_FINAL_CLEANUP_AGG_INT <<
 549             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 550         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 551         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 552         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 553
 554         /* Make sure notification is not set before initiating final cleanup */
 555         if (REG_RD(p_hwfn, addr)) {
 556                 DP_NOTICE(p_hwfn, false,
 557                           "Unexpected; Found final cleanup notification "
 558                           "before initiating final cleanup\n");
 559                 REG_WR(p_hwfn, addr, 0);
 560         }
 561
 562         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 563                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 564                    id, OSAL_CPU_TO_LE32(command));
 565
 566         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
 567                  OSAL_CPU_TO_LE32(command));
 568
 569         /* Poll until completion */
 570         while (!REG_RD(p_hwfn, addr) && count--)
 571                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 572
 573         if (REG_RD(p_hwfn, addr))
 574                 rc = ECORE_SUCCESS;
 575         else
 576                 DP_NOTICE(p_hwfn, true,
 577                           "Failed to receive FW final cleanup notification\n");
 578
 579         /* Cleanup afterwards */
 580         REG_WR(p_hwfn, addr, 0);
 581
 582         return rc;
 583 }
 584
 585 static void ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 586 {
 587         int hw_mode = 0;
 588
 589         switch (ECORE_GET_TYPE(p_hwfn->p_dev)) {
 590         case CHIP_BB_A0:
 591                 hw_mode |= 1 << MODE_BB_A0;
 592                 break;
 593         case CHIP_BB_B0:
 594                 hw_mode |= 1 << MODE_BB_B0;
 595                 break;
 596         case CHIP_K2:
 597                 hw_mode |= 1 << MODE_K2;
 598                 break;
 599         default:
 600                 DP_NOTICE(p_hwfn, true, "Can't initialize chip ID %d\n",
 601                           ECORE_GET_TYPE(p_hwfn->p_dev));
 602                 return;
 603         }
 604
 605         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 606         switch (p_hwfn->p_dev->num_ports_in_engines) {
 607         case 1:
 608                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 609                 break;
 610         case 2:
 611                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 612                 break;
 613         case 4:
 614                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 615                 break;
 616         default:
 617                 DP_NOTICE(p_hwfn, true,
 618                           "num_ports_in_engine = %d not supported\n",
 619                           p_hwfn->p_dev->num_ports_in_engines);
 620                 return;
 621         }
 622
 623         switch (p_hwfn->p_dev->mf_mode) {
 624         case ECORE_MF_DEFAULT:
 625         case ECORE_MF_NPAR:
 626                 hw_mode |= 1 << MODE_MF_SI;
 627                 break;
 628         case ECORE_MF_OVLAN:
 629                 hw_mode |= 1 << MODE_MF_SD;
 630                 break;
 631         default:
 632                 DP_NOTICE(p_hwfn, true,
 633                           "Unsupported MF mode, init as DEFAULT\n");
 634                 hw_mode |= 1 << MODE_MF_SI;
 635         }
 636
 637 #ifndef ASIC_ONLY
 638         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 639                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 640                         hw_mode |= 1 << MODE_FPGA;
 641                 } else {
 642                         if (p_hwfn->p_dev->b_is_emul_full)
 643                                 hw_mode |= 1 << MODE_EMUL_FULL;
 644                         else
 645                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 646                 }
 647         } else
 648 #endif
 649                 hw_mode |= 1 << MODE_ASIC;
 650
 651         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))
 652                 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND;
 653
 654         if (p_hwfn->p_dev->num_hwfns > 1)
 655                 hw_mode |= 1 << MODE_100G;
 656
 657         p_hwfn->hw_info.hw_mode = hw_mode;
 658
 659         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 660                    "Configuring function for hw_mode: 0x%08x\n",
 661                    p_hwfn->hw_info.hw_mode);
 662 }
 663
 664 #ifndef ASIC_ONLY
 665 /* MFW-replacement initializations for non-ASIC */
 666 static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 667                                struct ecore_ptt *p_ptt)
 668 {
 669         u32 pl_hv = 1;
 670         int i;
 671
 672         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 673                 pl_hv |= 0x600;
 674
 675         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 676
 677         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 678                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
 679
 680         /* initialize interrupt masks */
 681         for (i = 0;
 682              i <
 683              attn_blocks[BLOCK_MISCS].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
 684              num_of_int_regs; i++)
 685                 ecore_wr(p_hwfn, p_ptt,
 686                          attn_blocks[BLOCK_MISCS].
 687                          chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[i]->
 688                          mask_addr, 0);
 689
 690         if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
 691                 ecore_wr(p_hwfn, p_ptt,
 692                          attn_blocks[BLOCK_CNIG].
 693                          chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
 694                          mask_addr, 0);
 695         ecore_wr(p_hwfn, p_ptt,
 696                  attn_blocks[BLOCK_PGLCS].
 697                  chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
 698                  mask_addr, 0);
 699         ecore_wr(p_hwfn, p_ptt,
 700                  attn_blocks[BLOCK_CPMU].
 701                  chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
 702                  mask_addr, 0);
 703         /* Currently A0 and B0 interrupt bits are the same in pglue_b;
 704          * If this changes, need to set this according to chip type. <14/09/23>
 705          */
 706         ecore_wr(p_hwfn, p_ptt,
 707                  attn_blocks[BLOCK_PGLUE_B].
 708                  chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
 709                  mask_addr, 0x80000);
 710
 711         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 712         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 713         if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
 714                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
 715
 716         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
 717                 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 718                 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 719                          (p_hwfn->p_dev->num_ports_in_engines >> 1));
 720
 721                 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 722                          p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
 723         }
 724
 725         /* Poll on RBC */
 726         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 727         for (i = 0; i < 100; i++) {
 728                 OSAL_UDELAY(50);
 729                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 730                         break;
 731         }
 732         if (i == 100)
 733                 DP_NOTICE(p_hwfn, true,
 734                           "RBC done failed to complete in PSWRQ2\n");
 735 }
 736 #endif
 737
 738 /* Init run time data for all PFs and their VFs on an engine.
 739  * TBD - for VFs - Once we have parent PF info for each VF in
 740  * shmem available as CAU requires knowledge of parent PF for each VF.
 741  */
 742 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 743 {
 744         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 745         int i, sb_id;
 746
 747         for_each_hwfn(p_dev, i) {
 748                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 749                 struct ecore_igu_info *p_igu_info;
 750                 struct ecore_igu_block *p_block;
 751                 struct cau_sb_entry sb_entry;
 752
 753                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 754
 755                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 756                      sb_id++) {
 757                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 758
 759                         if (!p_block->is_pf)
 760                                 continue;
 761
 762                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 763                                                 p_block->function_id, 0, 0);
 764                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 765                 }
 766         }
 767 }
 768
 769 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 770                                                  struct ecore_ptt *p_ptt,
 771                                                  int hw_mode)
 772 {
 773         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 774         enum _ecore_status_t rc = ECORE_SUCCESS;
 775         struct ecore_dev *p_dev = p_hwfn->p_dev;
 776         u8 vf_id, max_num_vfs;
 777         u16 num_pfs, pf_id;
 778         u32 concrete_fid;
 779
 780         ecore_init_cau_rt_data(p_dev);
 781
 782         /* Program GTT windows */
 783         ecore_gtt_init(p_hwfn);
 784
 785 #ifndef ASIC_ONLY
 786         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 787                 ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 788 #endif
 789
 790         if (p_hwfn->mcp_info) {
 791                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 792                         qm_info->pf_rl_en = 1;
 793                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 794                         qm_info->pf_wfq_en = 1;
 795         }
 796
 797         ecore_qm_common_rt_init(p_hwfn,
 798                                 p_hwfn->p_dev->num_ports_in_engines,
 799                                 qm_info->max_phys_tcs_per_port,
 800                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
 801                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
 802                                 qm_info->qm_port_params);
 803
 804         ecore_cxt_hw_init_common(p_hwfn);
 805
 806         /* Close gate from NIG to BRB/Storm; By default they are open, but
 807          * we close them to prevent NIG from passing data to reset blocks.
 808          * Should have been done in the ENGINE phase, but init-tool lacks
 809          * proper port-pretend capabilities.
 810          */
 811         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 812         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 813         ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
 814         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
 815         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
 816         ecore_port_unpretend(p_hwfn, p_ptt);
 817
 818         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
 819         if (rc != ECORE_SUCCESS)
 820                 return rc;
 821
 822         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
 823          * need to decide with which value, maybe runtime
 824          */
 825         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
 826         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
 827
 828         if (ECORE_IS_BB(p_hwfn->p_dev)) {
 829                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
 830                 if (num_pfs == 1)
 831                         return rc;
 832                 /* pretend to original PF */
 833                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 834         }
 835
 836         /* Workaround for avoiding CCFC execution error when getting packets
 837          * with CRC errors, and allowing instead the invoking of the FW error
 838          * handler.
 839          * This is not done inside the init tool since it currently can't
 840          * perform a pretending to VFs.
 841          */
 842         max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2
 843             : MAX_NUM_VFS_BB;
 844         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
 845                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
 846                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
 847                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
 848         }
 849         /* pretend to original PF */
 850         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
 851
 852         return rc;
 853 }
 854
 855 #ifndef ASIC_ONLY
 856 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
 857 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
 858
 859 #define PMEG_IF_BYTE_COUNT      8
 860
 861 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
 862                              struct ecore_ptt *p_ptt,
 863                              u32 addr, u64 data, u8 reg_type, u8 port)
 864 {
 865         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 866                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
 867                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
 868                    (8 << PMEG_IF_BYTE_COUNT),
 869                    (reg_type << 25) | (addr << 8) | port,
 870                    (u32)((data >> 32) & 0xffffffff),
 871                    (u32)(data & 0xffffffff));
 872
 873         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
 874                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
 875                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
 876         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
 877                  (reg_type << 25) | (addr << 8) | port);
 878         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
 879                  data & 0xffffffff);
 880         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
 881                  (data >> 32) & 0xffffffff);
 882 }
 883
 884 #define XLPORT_MODE_REG (0x20a)
 885 #define XLPORT_MAC_CONTROL (0x210)
 886 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
 887 #define XLPORT_ENABLE_REG (0x20b)
 888
 889 #define XLMAC_CTRL (0x600)
 890 #define XLMAC_MODE (0x601)
 891 #define XLMAC_RX_MAX_SIZE (0x608)
 892 #define XLMAC_TX_CTRL (0x604)
 893 #define XLMAC_PAUSE_CTRL (0x60d)
 894 #define XLMAC_PFC_CTRL (0x60e)
 895
 896 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
 897                                     struct ecore_ptt *p_ptt)
 898 {
 899         u8 port = p_hwfn->port_id;
 900         u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
 901
 902         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
 903                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
 904                  (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
 905                  | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
 906
 907         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
 908                  1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
 909
 910         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
 911                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
 912
 913         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
 914                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
 915
 916         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
 917                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
 918
 919         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
 920                  (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
 921                  (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
 922
 923         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
 924 }
 925
 926 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
 927                                  struct ecore_ptt *p_ptt)
 928 {
 929         u8 loopback = 0, port = p_hwfn->port_id * 2;
 930
 931         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
 932
 933         if (ECORE_IS_AH(p_hwfn->p_dev)) {
 934                 ecore_emul_link_init_ah(p_hwfn, p_ptt);
 935                 return;
 936         }
 937
 938         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
 939                                 port);
 940         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
 941         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
 942         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
 943         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
 944         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
 945                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
 946                          0, port);
 947         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
 948         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
 949                          0x30ffffc000ULL, 0, port);
 950         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
 951                         port);
 952         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x1003 | (loopback << 2),
 953                         0, port);
 954         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
 955         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
 956 }
 957
 958 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
 959                             struct ecore_ptt *p_ptt, u8 port)
 960 {
 961         int port_offset = port ? 0x800 : 0;
 962         u32 xmac_rxctrl = 0;
 963
 964         /* Reset of XMAC */
 965         /* FIXME: move to common start */
 966         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
 967                 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
 968         OSAL_MSLEEP(1);
 969         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
 970                 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
 971
 972         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
 973
 974         /* Set the number of ports on the Warp Core to 10G */
 975         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
 976
 977         /* Soft reset of XMAC */
 978         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
 979                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
 980         OSAL_MSLEEP(1);
 981         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
 982                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
 983
 984         /* FIXME: move to common end */
 985         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 986                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
 987
 988         /* Set Max packet size: initialize XMAC block register for port 0 */
 989         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
 990
 991         /* CRC append for Tx packets: init XMAC block register for port 1 */
 992         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
 993
 994         /* Enable TX and RX: initialize XMAC block register for port 1 */
 995         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
 996                  XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
 997         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
 998         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
 999         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1000 }
1001 #endif
1002
1003 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1004                                                struct ecore_ptt *p_ptt,
1005                                                int hw_mode)
1006 {
1007         enum _ecore_status_t rc = ECORE_SUCCESS;
1008
1009         /* Init sequence */
1010         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1011                             hw_mode);
1012         if (rc != ECORE_SUCCESS)
1013                 return rc;
1014
1015 #ifndef ASIC_ONLY
1016         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1017                 return ECORE_SUCCESS;
1018
1019         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1020                 if (ECORE_IS_AH(p_hwfn->p_dev))
1021                         return ECORE_SUCCESS;
1022                 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1023         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1024                 if (p_hwfn->p_dev->num_hwfns > 1) {
1025                         /* Activate OPTE in CMT */
1026                         u32 val;
1027
1028                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1029                         val |= 0x10;
1030                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1031                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1032                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1033                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1034                         ecore_wr(p_hwfn, p_ptt,
1035                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1036                         ecore_wr(p_hwfn, p_ptt,
1037                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1038                         ecore_wr(p_hwfn, p_ptt,
1039                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1040                                  0x55555555);
1041                 }
1042
1043                 ecore_emul_link_init(p_hwfn, p_ptt);
1044         } else {
1045                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1046         }
1047 #endif
1048
1049         return rc;
1050 }
1051
1052 static enum _ecore_status_t
1053 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1054                               struct ecore_ptt *p_ptt)
1055 {
1056         u32 pwm_regsize, norm_regsize;
1057         u32 non_pwm_conn, min_addr_reg1;
1058         u32 db_bar_size, n_cpus;
1059         u32 pf_dems_shift;
1060         int rc = ECORE_SUCCESS;
1061
1062         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1063         if (p_hwfn->p_dev->num_hwfns > 1)
1064                 db_bar_size /= 2;
1065
1066         /* Calculate doorbell regions
1067          * -----------------------------------
1068          * The doorbell BAR is made of two regions. The first is called normal
1069          * region and the second is called PWM region. In the normal region
1070          * each ICID has its own set of addresses so that writing to that
1071          * specific address identifies the ICID. In the Process Window Mode
1072          * region the ICID is given in the data written to the doorbell. The
1073          * above per PF register denotes the offset in the doorbell BAR in which
1074          * the PWM region begins.
1075          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1076          * non-PWM connection. The calculation below computes the total non-PWM
1077          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1078          * in units of 4,096 bytes.
1079          */
1080         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1081             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1082                                           OSAL_NULL) +
1083             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1084         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1085         min_addr_reg1 = norm_regsize / 4096;
1086         pwm_regsize = db_bar_size - norm_regsize;
1087
1088         /* Check that the normal and PWM sizes are valid */
1089         if (db_bar_size < norm_regsize) {
1090                 DP_ERR(p_hwfn->p_dev,
1091                        "Doorbell BAR size 0x%x is too"
1092                        " small (normal region is 0x%0x )\n",
1093                        db_bar_size, norm_regsize);
1094                 return ECORE_NORESOURCES;
1095         }
1096         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1097                 DP_ERR(p_hwfn->p_dev,
1098                        "PWM region size 0x%0x is too small."
1099                        " Should be at least 0x%0x (Doorbell BAR size"
1100                        " is 0x%x and normal region size is 0x%0x)\n",
1101                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1102                        norm_regsize);
1103                 return ECORE_NORESOURCES;
1104         }
1105
1106         /* Update hwfn */
1107         p_hwfn->dpi_start_offset = norm_regsize; /* this is later used to
1108                                                   * calculate the doorbell
1109                                                   * address
1110                                                   */
1111
1112         /* Update registers */
1113         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1114         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1115         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1116         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1117
1118         DP_INFO(p_hwfn,
1119                 "Doorbell size 0x%x, Normal region 0x%x, PWM region 0x%x\n",
1120                 db_bar_size, norm_regsize, pwm_regsize);
1121         DP_INFO(p_hwfn, "DPI size 0x%x, DPI count 0x%x\n", p_hwfn->dpi_size,
1122                 p_hwfn->dpi_count);
1123
1124         return ECORE_SUCCESS;
1125 }
1126
1127 static enum _ecore_status_t
1128 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1129                  struct ecore_ptt *p_ptt,
1130                  struct ecore_tunn_start_params *p_tunn,
1131                  int hw_mode,
1132                  bool b_hw_start,
1133                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1134 {
1135         enum _ecore_status_t rc = ECORE_SUCCESS;
1136         u8 rel_pf_id = p_hwfn->rel_pf_id;
1137         u32 prs_reg;
1138         u16 ctrl;
1139         int pos;
1140
1141         /* ILT/DQ/CM/QM */
1142         if (p_hwfn->mcp_info) {
1143                 struct ecore_mcp_function_info *p_info;
1144
1145                 p_info = &p_hwfn->mcp_info->func_info;
1146                 if (p_info->bandwidth_min)
1147                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1148
1149                 /* Update rate limit once we'll actually have a link */
1150                 p_hwfn->qm_info.pf_rl = 100;
1151         }
1152         ecore_cxt_hw_init_pf(p_hwfn);
1153
1154         ecore_int_igu_init_rt(p_hwfn);  /* @@@TBD TODO MichalS multi hwfn ?? */
1155
1156         /* Set VLAN in NIG if needed */
1157         if (hw_mode & (1 << MODE_MF_SD)) {
1158                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1159                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1160                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1161                              p_hwfn->hw_info.ovlan);
1162         }
1163
1164         /* Enable classification by MAC if needed */
1165         if (hw_mode & (1 << MODE_MF_SI)) {
1166                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1167                            "Configuring TAGMAC_CLS_TYPE\n");
1168                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1169                              1);
1170         }
1171
1172         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1173         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
1174
1175         /* perform debug configuration when chip is out of reset */
1176         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1177
1178         /* Cleanup chip from previous driver if such remains exist */
1179         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1180         if (rc != ECORE_SUCCESS) {
1181                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1182                 return rc;
1183         }
1184
1185         /* PF Init sequence */
1186         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1187         if (rc)
1188                 return rc;
1189
1190         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1191         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1192         if (rc)
1193                 return rc;
1194
1195         /* Pure runtime initializations - directly to the HW  */
1196         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1197
1198         /* PCI relaxed ordering causes a decrease in the performance on some
1199          * systems. Till a root cause is found, disable this attribute in the
1200          * PCI config space.
1201          */
1202         /* Not in use @DPDK
1203          * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1204          * if (!pos) {
1205          *      DP_NOTICE(p_hwfn, true,
1206          *                "Failed to find the PCI Express"
1207          *                " Capability structure in the PCI config space\n");
1208          *      return ECORE_IO;
1209          * }
1210          * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1211          *                           &ctrl);
1212          * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1213          * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL,
1214          *                           &ctrl);
1215          */
1216
1217 #ifndef ASIC_ONLY
1218         /*@@TMP - On B0 build 1, need to mask the datapath_registers parity */
1219         if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev) &&
1220             (p_hwfn->p_dev->chip_metal == 1)) {
1221                 u32 reg_addr, tmp;
1222
1223                 reg_addr =
1224                     attn_blocks[BLOCK_PGLUE_B].
1225                     chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].prty_regs[0]->
1226                     mask_addr;
1227                 DP_NOTICE(p_hwfn, false,
1228                           "Masking datapath registers parity on"
1229                           " B0 emulation [build 1]\n");
1230                 tmp = ecore_rd(p_hwfn, p_ptt, reg_addr);
1231                 tmp |= (1 << 0);        /* Was PRTY_MASK_DATAPATH_REGISTERS */
1232                 ecore_wr(p_hwfn, p_ptt, reg_addr, tmp);
1233         }
1234 #endif
1235
1236         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1237         if (rc)
1238                 return rc;
1239
1240         if (b_hw_start) {
1241                 /* enable interrupts */
1242                 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1243
1244                 /* send function start command */
1245                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1246                                        allow_npar_tx_switch);
1247                 if (rc) {
1248                         DP_NOTICE(p_hwfn, true,
1249                                   "Function start ramrod failed\n");
1250                 } else {
1251                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1252                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1253                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1254
1255                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1256                                    "PRS_REG_SEARCH register after start PFn\n");
1257                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1258                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1259                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1260                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1261                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1262                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1263                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1264                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1265                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1266                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1267                                    prs_reg);
1268                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1269                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1270                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1271                 }
1272         }
1273         return rc;
1274 }
1275
1276 static enum _ecore_status_t
1277 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1278                       struct ecore_ptt *p_ptt, u8 enable)
1279 {
1280         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1281
1282         /* Change PF in PXP */
1283         ecore_wr(p_hwfn, p_ptt,
1284                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1285
1286         /* wait until value is set - try for 1 second every 50us */
1287         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1288                 val = ecore_rd(p_hwfn, p_ptt,
1289                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1290                 if (val == set_val)
1291                         break;
1292
1293                 OSAL_UDELAY(50);
1294         }
1295
1296         if (val != set_val) {
1297                 DP_NOTICE(p_hwfn, true,
1298                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1299                 return ECORE_UNKNOWN_ERROR;
1300         }
1301
1302         return ECORE_SUCCESS;
1303 }
1304
1305 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1306                                   struct ecore_ptt *p_main_ptt)
1307 {
1308         /* Read shadow of current MFW mailbox */
1309         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1310         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1311                     p_hwfn->mcp_info->mfw_mb_cur,
1312                     p_hwfn->mcp_info->mfw_mb_length);
1313 }
1314
1315 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1316                                    struct ecore_tunn_start_params *p_tunn,
1317                                    bool b_hw_start,
1318                                    enum ecore_int_mode int_mode,
1319                                    bool allow_npar_tx_switch,
1320                                    const u8 *bin_fw_data)
1321 {
1322         enum _ecore_status_t rc, mfw_rc;
1323         u32 load_code, param;
1324         int i, j;
1325
1326         if (IS_PF(p_dev)) {
1327                 rc = ecore_init_fw_data(p_dev, bin_fw_data);
1328                 if (rc != ECORE_SUCCESS)
1329                         return rc;
1330         }
1331
1332         for_each_hwfn(p_dev, i) {
1333                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1334
1335                 if (IS_VF(p_dev)) {
1336                         rc = ecore_vf_pf_init(p_hwfn);
1337                         if (rc)
1338                                 return rc;
1339                         continue;
1340                 }
1341
1342                 /* Enable DMAE in PXP */
1343                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1344
1345                 ecore_calc_hw_mode(p_hwfn);
1346                 /* @@@TBD need to add here:
1347                  * Check for fan failure
1348                  * Prev_unload
1349                  */
1350                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1351                 if (rc) {
1352                         DP_NOTICE(p_hwfn, true,
1353                                   "Failed sending LOAD_REQ command\n");
1354                         return rc;
1355                 }
1356
1357                 /* CQ75580:
1358                  * When coming back from hiberbate state, the registers from
1359                  * which shadow is read initially are not initialized. It turns
1360                  * out that these registers get initialized during the call to
1361                  * ecore_mcp_load_req request. So we need to reread them here
1362                  * to get the proper shadow register value.
1363                  * Note: This is a workaround for the missinginig MFW
1364                  * initialization. It may be removed once the implementation
1365                  * is done.
1366                  */
1367                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1368
1369                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1370                            "Load request was sent.Resp:0x%x, Load code: 0x%x\n",
1371                            rc, load_code);
1372
1373                 /* Only relevant for recovery:
1374                  * Clear the indication after the LOAD_REQ command is responded
1375                  * by the MFW.
1376                  */
1377                 p_dev->recov_in_prog = false;
1378
1379                 p_hwfn->first_on_engine = (load_code ==
1380                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1381
1382                 switch (load_code) {
1383                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1384                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1385                                                   p_hwfn->hw_info.hw_mode);
1386                         if (rc)
1387                                 break;
1388                         /* Fall into */
1389                 case FW_MSG_CODE_DRV_LOAD_PORT:
1390                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1391                                                 p_hwfn->hw_info.hw_mode);
1392                         if (rc)
1393                                 break;
1394
1395                         if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
1396                                 struct init_nig_pri_tc_map_req tc_map;
1397
1398                                 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map));
1399
1400                                 /* remove this once flow control is
1401                                  * implemented
1402                                  */
1403                                 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) {
1404                                         tc_map.pri[j].tc_id = 0;
1405                                         tc_map.pri[j].valid = 1;
1406                                 }
1407                                 ecore_init_nig_pri_tc_map(p_hwfn,
1408                                                           p_hwfn->p_main_ptt,
1409                                                           &tc_map);
1410                         }
1411                         /* fallthrough */
1412                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1413                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1414                                               p_tunn, p_hwfn->hw_info.hw_mode,
1415                                               b_hw_start, int_mode,
1416                                               allow_npar_tx_switch);
1417                         break;
1418                 default:
1419                         rc = ECORE_NOTIMPL;
1420                         break;
1421                 }
1422
1423                 if (rc != ECORE_SUCCESS)
1424                         DP_NOTICE(p_hwfn, true,
1425                                   "init phase failed loadcode 0x%x (rc %d)\n",
1426                                   load_code, rc);
1427
1428                 /* ACK mfw regardless of success or failure of initialization */
1429                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1430                                        DRV_MSG_CODE_LOAD_DONE,
1431                                        0, &load_code, &param);
1432                 if (rc != ECORE_SUCCESS)
1433                         return rc;
1434                 if (mfw_rc != ECORE_SUCCESS) {
1435                         DP_NOTICE(p_hwfn, true,
1436                                   "Failed sending LOAD_DONE command\n");
1437                         return mfw_rc;
1438                 }
1439
1440                 p_hwfn->hw_init_done = true;
1441         }
1442
1443         return ECORE_SUCCESS;
1444 }
1445
1446 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1447 static OSAL_INLINE void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1448                                              struct ecore_hwfn *p_hwfn,
1449                                              struct ecore_ptt *p_ptt)
1450 {
1451         int i;
1452
1453         /* close timers */
1454         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1455         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1456         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT &&
1457                                         !p_dev->recov_in_prog; i++) {
1458                 if ((!ecore_rd(p_hwfn, p_ptt,
1459                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1460                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1461                         break;
1462
1463                 /* Dependent on number of connection/tasks, possibly
1464                  * 1ms sleep is required between polls
1465                  */
1466                 OSAL_MSLEEP(1);
1467         }
1468         if (i == ECORE_HW_STOP_RETRY_LIMIT)
1469                 DP_NOTICE(p_hwfn, true,
1470                           "Timers linear scans are not over"
1471                           " [Connection %02x Tasks %02x]\n",
1472                           (u8)ecore_rd(p_hwfn, p_ptt,
1473                                        TM_REG_PF_SCAN_ACTIVE_CONN),
1474                           (u8)ecore_rd(p_hwfn, p_ptt,
1475                                        TM_REG_PF_SCAN_ACTIVE_TASK));
1476 }
1477
1478 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1479 {
1480         int j;
1481
1482         for_each_hwfn(p_dev, j) {
1483                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1484                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1485
1486                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1487         }
1488 }
1489
1490 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1491 {
1492         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1493         int j;
1494
1495         for_each_hwfn(p_dev, j) {
1496                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1497                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1498
1499                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1500
1501                 if (IS_VF(p_dev)) {
1502                         ecore_vf_pf_int_cleanup(p_hwfn);
1503                         continue;
1504                 }
1505
1506                 /* mark the hw as uninitialized... */
1507                 p_hwfn->hw_init_done = false;
1508
1509                 rc = ecore_sp_pf_stop(p_hwfn);
1510                 if (rc)
1511                         DP_NOTICE(p_hwfn, true,
1512                                   "Failed to close PF against FW. Continue to"
1513                                   " stop HW to prevent illegal host access"
1514                                   " by the device\n");
1515
1516                 /* perform debug action after PF stop was sent */
1517                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1518
1519                 /* close NIG to BRB gate */
1520                 ecore_wr(p_hwfn, p_ptt,
1521                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1522
1523                 /* close parser */
1524                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1525                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1526                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1527
1528                 /* @@@TBD - clean transmission queues (5.b) */
1529                 /* @@@TBD - clean BTB (5.c) */
1530
1531                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1532
1533                 /* @@@TBD - verify DMAE requests are done (8) */
1534
1535                 /* Disable Attention Generation */
1536                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1537                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1538                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1539                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1540                 /* Need to wait 1ms to guarantee SBs are cleared */
1541                 OSAL_MSLEEP(1);
1542         }
1543
1544         if (IS_PF(p_dev)) {
1545                 /* Disable DMAE in PXP - in CMT, this should only be done for
1546                  * first hw-function, and only after all transactions have
1547                  * stopped for all active hw-functions.
1548                  */
1549                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1550                                              p_dev->hwfns[0].p_main_ptt, false);
1551                 if (t_rc != ECORE_SUCCESS)
1552                         rc = t_rc;
1553         }
1554
1555         return rc;
1556 }
1557
1558 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1559 {
1560         int j;
1561
1562         for_each_hwfn(p_dev, j) {
1563                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1564                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1565
1566                 if (IS_VF(p_dev)) {
1567                         ecore_vf_pf_int_cleanup(p_hwfn);
1568                         continue;
1569                 }
1570
1571                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1572                            "Shutting down the fastpath\n");
1573
1574                 ecore_wr(p_hwfn, p_ptt,
1575                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1576
1577                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1578                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1579                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1580
1581                 /* @@@TBD - clean transmission queues (5.b) */
1582                 /* @@@TBD - clean BTB (5.c) */
1583
1584                 /* @@@TBD - verify DMAE requests are done (8) */
1585
1586                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1587                 /* Need to wait 1ms to guarantee SBs are cleared */
1588                 OSAL_MSLEEP(1);
1589         }
1590 }
1591
1592 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1593 {
1594         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1595
1596         if (IS_VF(p_hwfn->p_dev))
1597                 return;
1598
1599         /* Re-open incoming traffic */
1600         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1601                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1602 }
1603
1604 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1605                                              struct ecore_ptt *p_ptt, u32 reg,
1606                                              bool expected)
1607 {
1608         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1609
1610         if (assert_val != expected) {
1611                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1612                           reg, expected);
1613                 return ECORE_UNKNOWN_ERROR;
1614         }
1615
1616         return 0;
1617 }
1618
1619 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1620 {
1621         enum _ecore_status_t rc = ECORE_SUCCESS;
1622         u32 unload_resp, unload_param;
1623         int i;
1624
1625         for_each_hwfn(p_dev, i) {
1626                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1627
1628                 if (IS_VF(p_dev)) {
1629                         rc = ecore_vf_pf_reset(p_hwfn);
1630                         if (rc)
1631                                 return rc;
1632                         continue;
1633                 }
1634
1635                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1636
1637                 /* Check for incorrect states */
1638                 if (!p_dev->recov_in_prog) {
1639                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1640                                          QM_REG_USG_CNT_PF_TX, 0);
1641                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1642                                          QM_REG_USG_CNT_PF_OTHER, 0);
1643                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1644                 }
1645
1646                 /* Disable PF in HW blocks */
1647                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1648                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1649                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1650                          TCFC_REG_STRONG_ENABLE_PF, 0);
1651                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1652                          CCFC_REG_STRONG_ENABLE_PF, 0);
1653
1654                 if (p_dev->recov_in_prog) {
1655                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1656                                    "Recovery is in progress -> skip "
1657                                    "sending unload_req/done\n");
1658                         break;
1659                 }
1660
1661                 /* Send unload command to MCP */
1662                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1663                                    DRV_MSG_CODE_UNLOAD_REQ,
1664                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
1665                                    &unload_resp, &unload_param);
1666                 if (rc != ECORE_SUCCESS) {
1667                         DP_NOTICE(p_hwfn, true,
1668                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
1669                         /* @@TBD - what to do? for now, assume ENG. */
1670                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1671                 }
1672
1673                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1674                                    DRV_MSG_CODE_UNLOAD_DONE,
1675                                    0, &unload_resp, &unload_param);
1676                 if (rc != ECORE_SUCCESS) {
1677                         DP_NOTICE(p_hwfn,
1678                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
1679                         /* @@@TBD - Should it really ASSERT here ? */
1680                         return rc;
1681                 }
1682         }
1683
1684         return rc;
1685 }
1686
1687 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1688 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
1689 {
1690         ecore_ptt_pool_free(p_hwfn);
1691         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
1692 }
1693
1694 /* Setup bar access */
1695 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
1696 {
1697         /* clear indirect access */
1698         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1699         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1700         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1701         ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1702
1703         /* Clean Previous errors if such exist */
1704         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1705                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1706
1707         /* enable internal target-read */
1708         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1709                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1710 }
1711
1712 static void get_function_id(struct ecore_hwfn *p_hwfn)
1713 {
1714         /* ME Register */
1715         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
1716                                                  PXP_PF_ME_OPAQUE_ADDR);
1717
1718         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1719
1720         /* Bits 16-19 from the ME registers are the pf_num */
1721         /* @@ @TBD - check, may be wrong after B0 implementation for CMT */
1722         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1723         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1724                                       PXP_CONCRETE_FID_PFID);
1725         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1726                                     PXP_CONCRETE_FID_PORT);
1727
1728         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1729                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1730                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
1731 }
1732
1733 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
1734 {
1735         u32 *feat_num = p_hwfn->hw_info.feat_num;
1736         int num_features = 1;
1737
1738         /* L2 Queues require each: 1 status block. 1 L2 queue */
1739         feat_num[ECORE_PF_L2_QUE] =
1740             OSAL_MIN_T(u32,
1741                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
1742                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
1743
1744         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1745                    "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1746                    feat_num[ECORE_PF_L2_QUE],
1747                    RESC_NUM(p_hwfn, ECORE_SB), num_features);
1748 }
1749
1750 /* @@@TBD MK RESC: This info is currently hard code and set as if we were MF
1751  * need to read it from shmem...
1752  */
1753 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn)
1754 {
1755         u32 *resc_start = p_hwfn->hw_info.resc_start;
1756         u8 num_funcs = p_hwfn->num_funcs_on_engine;
1757         u32 *resc_num = p_hwfn->hw_info.resc_num;
1758         int i, max_vf_vlan_filters;
1759         struct ecore_sb_cnt_info sb_cnt_info;
1760         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
1761
1762         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
1763
1764 #ifdef CONFIG_ECORE_SRIOV
1765         max_vf_vlan_filters = ECORE_ETH_MAX_VF_NUM_VLAN_FILTERS;
1766 #else
1767         max_vf_vlan_filters = 0;
1768 #endif
1769
1770         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1771         resc_num[ECORE_SB] = OSAL_MIN_T(u32,
1772                                         (MAX_SB_PER_PATH_BB / num_funcs),
1773                                         sb_cnt_info.sb_cnt);
1774
1775         resc_num[ECORE_L2_QUEUE] = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
1776                                     MAX_NUM_L2_QUEUES_BB) / num_funcs;
1777         resc_num[ECORE_VPORT] = (b_ah ? MAX_NUM_VPORTS_K2 :
1778                                  MAX_NUM_VPORTS_BB) / num_funcs;
1779         resc_num[ECORE_RSS_ENG] = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
1780                                    ETH_RSS_ENGINE_NUM_BB) / num_funcs;
1781         resc_num[ECORE_PQ] = (b_ah ? MAX_QM_TX_QUEUES_K2 :
1782                               MAX_QM_TX_QUEUES_BB) / num_funcs;
1783         resc_num[ECORE_RL] = 8;
1784         resc_num[ECORE_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1785         resc_num[ECORE_VLAN] = (ETH_NUM_VLAN_FILTERS -
1786                                 max_vf_vlan_filters +
1787                                 1 /*For vlan0 */) / num_funcs;
1788
1789         /* TODO - there will be a problem in AH - there are only 11k lines */
1790         resc_num[ECORE_ILT] = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
1791                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
1792
1793 #ifndef ASIC_ONLY
1794         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1795                 /* Reduced build contains less PQs */
1796                 if (!(p_hwfn->p_dev->b_is_emul_full))
1797                         resc_num[ECORE_PQ] = 32;
1798
1799                 /* For AH emulation, since we have a possible maximal number of
1800                  * 16 enabled PFs, in case there are not enough ILT lines -
1801                  * allocate only first PF as RoCE and have all the other ETH
1802                  * only with less ILT lines.
1803                  */
1804                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
1805                         resc_num[ECORE_ILT] = resc_num[ECORE_ILT];
1806         }
1807 #endif
1808
1809         for (i = 0; i < ECORE_MAX_RESC; i++)
1810                 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1811
1812 #ifndef ASIC_ONLY
1813         /* Correct the common ILT calculation if PF0 has more */
1814         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
1815             p_hwfn->p_dev->b_is_emul_full &&
1816             p_hwfn->rel_pf_id && resc_num[ECORE_ILT])
1817                 resc_start[ECORE_ILT] += resc_num[ECORE_ILT];
1818 #endif
1819
1820         /* Sanity for ILT */
1821         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
1822             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
1823                 DP_NOTICE(p_hwfn, true,
1824                           "Can't assign ILT pages [%08x,...,%08x]\n",
1825                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
1826                                                                   ECORE_ILT) -
1827                           1);
1828                 return ECORE_INVAL;
1829         }
1830
1831         ecore_hw_set_feat(p_hwfn);
1832
1833         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
1834                    "The numbers for each resource are:\n"
1835                    "SB = %d start = %d\n"
1836                    "L2_QUEUE = %d start = %d\n"
1837                    "VPORT = %d start = %d\n"
1838                    "PQ = %d start = %d\n"
1839                    "RL = %d start = %d\n"
1840                    "MAC = %d start = %d\n"
1841                    "VLAN = %d start = %d\n"
1842                    "ILT = %d start = %d\n"
1843                    "CMDQS_CQS = %d start = %d\n",
1844                    RESC_NUM(p_hwfn, ECORE_SB), RESC_START(p_hwfn, ECORE_SB),
1845                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
1846                    RESC_START(p_hwfn, ECORE_L2_QUEUE),
1847                    RESC_NUM(p_hwfn, ECORE_VPORT),
1848                    RESC_START(p_hwfn, ECORE_VPORT),
1849                    RESC_NUM(p_hwfn, ECORE_PQ), RESC_START(p_hwfn, ECORE_PQ),
1850                    RESC_NUM(p_hwfn, ECORE_RL), RESC_START(p_hwfn, ECORE_RL),
1851                    RESC_NUM(p_hwfn, ECORE_MAC), RESC_START(p_hwfn, ECORE_MAC),
1852                    RESC_NUM(p_hwfn, ECORE_VLAN),
1853                    RESC_START(p_hwfn, ECORE_VLAN),
1854                    RESC_NUM(p_hwfn, ECORE_ILT), RESC_START(p_hwfn, ECORE_ILT),
1855                    RESC_NUM(p_hwfn, ECORE_CMDQS_CQS),
1856                    RESC_START(p_hwfn, ECORE_CMDQS_CQS));
1857
1858         return ECORE_SUCCESS;
1859 }
1860
1861 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
1862                                                   struct ecore_ptt *p_ptt)
1863 {
1864         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1865         u32 port_cfg_addr, link_temp, device_capabilities;
1866         struct ecore_mcp_link_params *link;
1867
1868         /* Read global nvm_cfg address */
1869         u32 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1870
1871         /* Verify MCP has initialized it */
1872         if (nvm_cfg_addr == 0) {
1873                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
1874                 return ECORE_INVAL;
1875         }
1876
1877         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
1878         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1879
1880         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1881             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
1882                                                        core_cfg);
1883
1884         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
1885
1886         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1887                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1888         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G:
1889                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
1890                 break;
1891         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G:
1892                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
1893                 break;
1894         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G:
1895                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
1896                 break;
1897         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F:
1898                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
1899                 break;
1900         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E:
1901                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
1902                 break;
1903         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G:
1904                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
1905                 break;
1906         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G:
1907                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
1908                 break;
1909         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G:
1910                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
1911                 break;
1912         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G:
1913                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
1914                 break;
1915         default:
1916                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
1917                           core_cfg);
1918                 break;
1919         }
1920
1921         /* Read default link configuration */
1922         link = &p_hwfn->mcp_info->link_input;
1923         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1924             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1925         link_temp = ecore_rd(p_hwfn, p_ptt,
1926                              port_cfg_addr +
1927                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
1928         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1929         link->speed.advertised_speeds = link_temp;
1930
1931         link_temp = link->speed.advertised_speeds;
1932         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
1933
1934         link_temp = ecore_rd(p_hwfn, p_ptt,
1935                              port_cfg_addr +
1936                              OFFSETOF(struct nvm_cfg1_port, link_settings));
1937         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1938                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1939         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1940                 link->speed.autoneg = true;
1941                 break;
1942         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1943                 link->speed.forced_speed = 1000;
1944                 break;
1945         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1946                 link->speed.forced_speed = 10000;
1947                 break;
1948         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1949                 link->speed.forced_speed = 25000;
1950                 break;
1951         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1952                 link->speed.forced_speed = 40000;
1953                 break;
1954         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1955                 link->speed.forced_speed = 50000;
1956                 break;
1957         case NVM_CFG1_PORT_DRV_LINK_SPEED_100G:
1958                 link->speed.forced_speed = 100000;
1959                 break;
1960         default:
1961                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
1962         }
1963
1964         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1965         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1966         link->pause.autoneg = !!(link_temp &
1967                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1968         link->pause.forced_rx = !!(link_temp &
1969                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1970         link->pause.forced_tx = !!(link_temp &
1971                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1972         link->loopback_mode = 0;
1973
1974         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1975                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x,"
1976                    " AN: 0x%02x, PAUSE AN: 0x%02x\n",
1977                    link->speed.forced_speed, link->speed.advertised_speeds,
1978                    link->speed.autoneg, link->pause.autoneg);
1979
1980         /* Read Multi-function information from shmem */
1981         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1982             OFFSETOF(struct nvm_cfg1, glob) +
1983             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
1984
1985         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
1986
1987         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1988             NVM_CFG1_GLOB_MF_MODE_OFFSET;
1989
1990         switch (mf_mode) {
1991         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1992                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
1993                 break;
1994         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1995                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
1996                 break;
1997         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1998                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
1999                 break;
2000         }
2001         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2002                 p_hwfn->p_dev->mf_mode);
2003
2004         /* Read Multi-function information from shmem */
2005         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2006             OFFSETOF(struct nvm_cfg1, glob) +
2007             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2008
2009         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2010         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2011                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2012                              &p_hwfn->hw_info.device_capabilities);
2013
2014         return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2015 }
2016
2017 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2018                                 struct ecore_ptt *p_ptt)
2019 {
2020         u8 num_funcs;
2021         u32 tmp, mask;
2022
2023         num_funcs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_PFS_K2
2024             : MAX_NUM_PFS_BB;
2025
2026         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2027          * in the other bits are selected.
2028          * Bits 1-15 are for functions 1-15, respectively, and their value is
2029          * '0' only for enabled functions (function 0 always exists and
2030          * enabled).
2031          * In case of CMT, only the "even" functions are enabled, and thus the
2032          * number of functions for both hwfns is learnt from the same bits.
2033          */
2034
2035         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2036         if (tmp & 0x1) {
2037                 if (ECORE_PATH_ID(p_hwfn) && p_hwfn->p_dev->num_hwfns == 1) {
2038                         num_funcs = 0;
2039                         mask = 0xaaaa;
2040                 } else {
2041                         num_funcs = 1;
2042                         mask = 0x5554;
2043                 }
2044
2045                 tmp = (tmp ^ 0xffffffff) & mask;
2046                 while (tmp) {
2047                         if (tmp & 0x1)
2048                                 num_funcs++;
2049                         tmp >>= 0x1;
2050                 }
2051         }
2052
2053         p_hwfn->num_funcs_on_engine = num_funcs;
2054
2055 #ifndef ASIC_ONLY
2056         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2057                 DP_NOTICE(p_hwfn, false,
2058                           "FPGA: Limit number of PFs to 4 [would affect"
2059                           " resource allocation, needed for IOV]\n");
2060                 p_hwfn->num_funcs_on_engine = 4;
2061         }
2062 #endif
2063
2064         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "num_funcs_on_engine = %d\n",
2065                    p_hwfn->num_funcs_on_engine);
2066 }
2067
2068 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2069                                       struct ecore_ptt *p_ptt)
2070 {
2071         u32 port_mode;
2072
2073 #ifndef ASIC_ONLY
2074         /* Read the port mode */
2075         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2076                 port_mode = 4;
2077         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2078                  (p_hwfn->p_dev->num_hwfns > 1))
2079                 /* In CMT on emulation, assume 1 port */
2080                 port_mode = 1;
2081         else
2082 #endif
2083                 port_mode = ecore_rd(p_hwfn, p_ptt,
2084                                      CNIG_REG_NW_PORT_MODE_BB_B0);
2085
2086         if (port_mode < 3) {
2087                 p_hwfn->p_dev->num_ports_in_engines = 1;
2088         } else if (port_mode <= 5) {
2089                 p_hwfn->p_dev->num_ports_in_engines = 2;
2090         } else {
2091                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2092                           p_hwfn->p_dev->num_ports_in_engines);
2093
2094                 /* Default num_ports_in_engines to something */
2095                 p_hwfn->p_dev->num_ports_in_engines = 1;
2096         }
2097 }
2098
2099 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2100                                       struct ecore_ptt *p_ptt)
2101 {
2102         u32 port;
2103         int i;
2104
2105         p_hwfn->p_dev->num_ports_in_engines = 0;
2106
2107         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2108                 port = ecore_rd(p_hwfn, p_ptt,
2109                                 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2110                 if (port & 1)
2111                         p_hwfn->p_dev->num_ports_in_engines++;
2112         }
2113 }
2114
2115 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2116                                    struct ecore_ptt *p_ptt)
2117 {
2118         if (ECORE_IS_BB(p_hwfn->p_dev))
2119                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2120         else
2121                 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2122 }
2123
2124 static enum _ecore_status_t
2125 ecore_get_hw_info(struct ecore_hwfn *p_hwfn,
2126                   struct ecore_ptt *p_ptt,
2127                   enum ecore_pci_personality personality)
2128 {
2129         enum _ecore_status_t rc;
2130
2131         rc = ecore_iov_hw_info(p_hwfn, p_hwfn->p_main_ptt);
2132         if (rc)
2133                 return rc;
2134
2135         /* TODO In get_hw_info, amoungst others:
2136          * Get MCP FW revision and determine according to it the supported
2137          * featrues (e.g. DCB)
2138          * Get boot mode
2139          * ecore_get_pcie_width_speed, WOL capability.
2140          * Number of global CQ-s (for storage
2141          */
2142         ecore_hw_info_port_num(p_hwfn, p_ptt);
2143
2144 #ifndef ASIC_ONLY
2145         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2146 #endif
2147                 ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2148
2149         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2150         if (rc)
2151                 return rc;
2152
2153 #ifndef ASIC_ONLY
2154         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2155 #endif
2156                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2157                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2158 #ifndef ASIC_ONLY
2159         } else {
2160                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2161
2162                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2163                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2164         }
2165 #endif
2166
2167         if (ecore_mcp_is_init(p_hwfn)) {
2168                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2169                         p_hwfn->hw_info.ovlan =
2170                             p_hwfn->mcp_info->func_info.ovlan;
2171
2172                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2173         }
2174
2175         if (personality != ECORE_PCI_DEFAULT)
2176                 p_hwfn->hw_info.personality = personality;
2177         else if (ecore_mcp_is_init(p_hwfn))
2178                 p_hwfn->hw_info.personality =
2179                     p_hwfn->mcp_info->func_info.protocol;
2180
2181 #ifndef ASIC_ONLY
2182         /* To overcome ILT lack for emulation, until at least until we'll have
2183          * a definite answer from system about it, allow only PF0 to be RoCE.
2184          */
2185         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
2186                 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2187 #endif
2188
2189         ecore_get_num_funcs(p_hwfn, p_ptt);
2190
2191         /* Feat num is dependent on personality and on the number of functions
2192          * on the engine. Therefore it should be come after personality
2193          * initialization and after getting the number of functions.
2194          */
2195         return ecore_hw_get_resc(p_hwfn);
2196 }
2197
2198 /* @TMP - this should move to a proper .h */
2199 #define CHIP_NUM_AH                     0x8070
2200
2201 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2202 {
2203         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2204         u32 tmp;
2205
2206         /* Read Vendor Id / Device Id */
2207         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2208                                   &p_dev->vendor_id);
2209         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2210                                   &p_dev->device_id);
2211
2212         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2213                                          MISCS_REG_CHIP_NUM);
2214         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2215                                         MISCS_REG_CHIP_REV);
2216
2217         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2218
2219         /* Determine type */
2220         if (p_dev->device_id == CHIP_NUM_AH)
2221                 p_dev->type = ECORE_DEV_TYPE_AH;
2222         else
2223                 p_dev->type = ECORE_DEV_TYPE_BB;
2224
2225         /* Learn number of HW-functions */
2226         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2227                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2228
2229         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2230                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2231                 p_dev->num_hwfns = 2;
2232         } else {
2233                 p_dev->num_hwfns = 1;
2234         }
2235
2236 #ifndef ASIC_ONLY
2237         if (CHIP_REV_IS_EMUL(p_dev)) {
2238                 /* For some reason we have problems with this register
2239                  * in B0 emulation; Simply assume no CMT
2240                  */
2241                 DP_NOTICE(p_dev->hwfns, false,
2242                           "device on emul - assume no CMT\n");
2243                 p_dev->num_hwfns = 1;
2244         }
2245 #endif
2246
2247         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2248                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2249         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2250         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2251                                           MISCS_REG_CHIP_METAL);
2252         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2253         DP_INFO(p_dev->hwfns,
2254                 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x"
2255                 " Metal: %04x\n",
2256                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2257                 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2258                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2259                 p_dev->chip_metal);
2260
2261         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2262                 DP_NOTICE(p_dev->hwfns, false,
2263                           "The chip type/rev (BB A0) is not supported!\n");
2264                 return ECORE_ABORTED;
2265         }
2266 #ifndef ASIC_ONLY
2267         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2268                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2269                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2270
2271         if (CHIP_REV_IS_EMUL(p_dev)) {
2272                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2273                                MISCS_REG_ECO_RESERVED);
2274                 if (tmp & (1 << 29)) {
2275                         DP_NOTICE(p_hwfn, false,
2276                                   "Emulation: Running on a FULL build\n");
2277                         p_dev->b_is_emul_full = true;
2278                 } else {
2279                         DP_NOTICE(p_hwfn, false,
2280                                   "Emulation: Running on a REDUCED build\n");
2281                 }
2282         }
2283 #endif
2284
2285         return ECORE_SUCCESS;
2286 }
2287
2288 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2289 {
2290         int j;
2291
2292         if (IS_VF(p_dev))
2293                 return;
2294
2295         for_each_hwfn(p_dev, j) {
2296                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2297
2298                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2299                            "Mark hw/fw uninitialized\n");
2300
2301                 p_hwfn->hw_init_done = false;
2302                 p_hwfn->first_on_engine = false;
2303         }
2304 }
2305
2306 static enum _ecore_status_t
2307 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2308                         void OSAL_IOMEM *p_regview,
2309                         void OSAL_IOMEM *p_doorbells,
2310                         enum ecore_pci_personality personality)
2311 {
2312         enum _ecore_status_t rc = ECORE_SUCCESS;
2313
2314         /* Split PCI bars evenly between hwfns */
2315         p_hwfn->regview = p_regview;
2316         p_hwfn->doorbells = p_doorbells;
2317
2318         /* Validate that chip access is feasible */
2319         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2320                 DP_ERR(p_hwfn,
2321                        "Reading the ME register returns all Fs;"
2322                        " Preventing further chip access\n");
2323                 return ECORE_INVAL;
2324         }
2325
2326         get_function_id(p_hwfn);
2327
2328         /* Allocate PTT pool */
2329         rc = ecore_ptt_pool_alloc(p_hwfn);
2330         if (rc) {
2331                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2332                 goto err0;
2333         }
2334
2335         /* Allocate the main PTT */
2336         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2337
2338         /* First hwfn learns basic information, e.g., number of hwfns */
2339         if (!p_hwfn->my_id) {
2340                 rc = ecore_get_dev_info(p_hwfn->p_dev);
2341                 if (rc != ECORE_SUCCESS)
2342                         goto err1;
2343         }
2344
2345         ecore_hw_hwfn_prepare(p_hwfn);
2346
2347         /* Initialize MCP structure */
2348         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2349         if (rc) {
2350                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
2351                 goto err1;
2352         }
2353
2354         /* Read the device configuration information from the HW and SHMEM */
2355         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2356         if (rc) {
2357                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
2358                 goto err2;
2359         }
2360
2361         /* Allocate the init RT array and initialize the init-ops engine */
2362         rc = ecore_init_alloc(p_hwfn);
2363         if (rc) {
2364                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
2365                 goto err2;
2366         }
2367 #ifndef ASIC_ONLY
2368         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2369                 DP_NOTICE(p_hwfn, false,
2370                           "FPGA: workaround; Prevent DMAE parities\n");
2371                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
2372
2373                 DP_NOTICE(p_hwfn, false,
2374                           "FPGA: workaround: Set VF bar0 size\n");
2375                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2376                          PGLUE_B_REG_VF_BAR0_SIZE, 4);
2377         }
2378 #endif
2379
2380         return rc;
2381 err2:
2382         ecore_mcp_free(p_hwfn);
2383 err1:
2384         ecore_hw_hwfn_free(p_hwfn);
2385 err0:
2386         return rc;
2387 }
2388
2389 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, int personality)
2390 {
2391         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2392         enum _ecore_status_t rc;
2393
2394         if (IS_VF(p_dev))
2395                 return ecore_vf_hw_prepare(p_dev);
2396
2397         /* Store the precompiled init data ptrs */
2398         ecore_init_iro_array(p_dev);
2399
2400         /* Initialize the first hwfn - will learn number of hwfns */
2401         rc = ecore_hw_prepare_single(p_hwfn,
2402                                      p_dev->regview,
2403                                      p_dev->doorbells, personality);
2404         if (rc != ECORE_SUCCESS)
2405                 return rc;
2406
2407         personality = p_hwfn->hw_info.personality;
2408
2409         /* initialalize 2nd hwfn if necessary */
2410         if (p_dev->num_hwfns > 1) {
2411                 void OSAL_IOMEM *p_regview, *p_doorbell;
2412                 u8 OSAL_IOMEM *addr;
2413
2414                 /* adjust bar offset for second engine */
2415                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
2416                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
2417                 p_regview = (void OSAL_IOMEM *)addr;
2418
2419                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
2420                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
2421                 p_doorbell = (void OSAL_IOMEM *)addr;
2422
2423                 /* prepare second hw function */
2424                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
2425                                              p_doorbell, personality);
2426
2427                 /* in case of error, need to free the previously
2428                  * initialiazed hwfn 0
2429                  */
2430                 if (rc != ECORE_SUCCESS) {
2431                         ecore_init_free(p_hwfn);
2432                         ecore_mcp_free(p_hwfn);
2433                         ecore_hw_hwfn_free(p_hwfn);
2434                         return rc;
2435                 }
2436         }
2437
2438         return ECORE_SUCCESS;
2439 }
2440
2441 void ecore_hw_remove(struct ecore_dev *p_dev)
2442 {
2443         int i;
2444
2445         for_each_hwfn(p_dev, i) {
2446                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2447
2448                 if (IS_VF(p_dev)) {
2449                         ecore_vf_pf_release(p_hwfn);
2450                         continue;
2451                 }
2452
2453                 ecore_init_free(p_hwfn);
2454                 ecore_hw_hwfn_free(p_hwfn);
2455                 ecore_mcp_free(p_hwfn);
2456
2457                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
2458         }
2459 }
2460
2461 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
2462                                       struct ecore_chain *p_chain)
2463 {
2464         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
2465         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2466         struct ecore_chain_next *p_next;
2467         u32 size, i;
2468
2469         if (!p_virt)
2470                 return;
2471
2472         size = p_chain->elem_size * p_chain->usable_per_page;
2473
2474         for (i = 0; i < p_chain->page_cnt; i++) {
2475                 if (!p_virt)
2476                         break;
2477
2478                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
2479                 p_virt_next = p_next->next_virt;
2480                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2481
2482                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
2483                                        ECORE_CHAIN_PAGE_SIZE);
2484
2485                 p_virt = p_virt_next;
2486                 p_phys = p_phys_next;
2487         }
2488 }
2489
2490 static void ecore_chain_free_single(struct ecore_dev *p_dev,
2491                                     struct ecore_chain *p_chain)
2492 {
2493         if (!p_chain->p_virt_addr)
2494                 return;
2495
2496         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
2497                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
2498 }
2499
2500 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
2501                                  struct ecore_chain *p_chain)
2502 {
2503         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2504         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
2505         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
2506
2507         if (!pp_virt_addr_tbl)
2508                 return;
2509
2510         if (!p_chain->pbl.p_virt_table)
2511                 goto out;
2512
2513         for (i = 0; i < page_cnt; i++) {
2514                 if (!pp_virt_addr_tbl[i])
2515                         break;
2516
2517                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
2518                                        *(dma_addr_t *)p_pbl_virt,
2519                                        ECORE_CHAIN_PAGE_SIZE);
2520
2521                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2522         }
2523
2524         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2525         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
2526                                p_chain->pbl.p_phys_table, pbl_size);
2527 out:
2528         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
2529 }
2530
2531 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2532 {
2533         switch (p_chain->mode) {
2534         case ECORE_CHAIN_MODE_NEXT_PTR:
2535                 ecore_chain_free_next_ptr(p_dev, p_chain);
2536                 break;
2537         case ECORE_CHAIN_MODE_SINGLE:
2538                 ecore_chain_free_single(p_dev, p_chain);
2539                 break;
2540         case ECORE_CHAIN_MODE_PBL:
2541                 ecore_chain_free_pbl(p_dev, p_chain);
2542                 break;
2543         }
2544 }
2545
2546 static enum _ecore_status_t
2547 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
2548                                enum ecore_chain_cnt_type cnt_type,
2549                                osal_size_t elem_size, u32 page_cnt)
2550 {
2551         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2552
2553         /* The actual chain size can be larger than the maximal possible value
2554          * after rounding up the requested elements number to pages, and after
2555          * taking into acount the unusuable elements (next-ptr elements).
2556          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2557          * size/capacity fields are of a u32 type.
2558          */
2559         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
2560              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
2561             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
2562              chain_size > ECORE_U32_MAX)) {
2563                 DP_NOTICE(p_dev, true,
2564                           "The actual chain size (0x%lx) is larger than"
2565                           " the maximal possible value\n",
2566                           (unsigned long)chain_size);
2567                 return ECORE_INVAL;
2568         }
2569
2570         return ECORE_SUCCESS;
2571 }
2572
2573 static enum _ecore_status_t
2574 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2575 {
2576         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
2577         dma_addr_t p_phys = 0;
2578         u32 i;
2579
2580         for (i = 0; i < p_chain->page_cnt; i++) {
2581                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2582                                                  ECORE_CHAIN_PAGE_SIZE);
2583                 if (!p_virt) {
2584                         DP_NOTICE(p_dev, true,
2585                                   "Failed to allocate chain memory\n");
2586                         return ECORE_NOMEM;
2587                 }
2588
2589                 if (i == 0) {
2590                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
2591                         ecore_chain_reset(p_chain);
2592                 } else {
2593                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2594                                                        p_virt, p_phys);
2595                 }
2596
2597                 p_virt_prev = p_virt;
2598         }
2599         /* Last page's next element should point to the beginning of the
2600          * chain.
2601          */
2602         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2603                                        p_chain->p_virt_addr,
2604                                        p_chain->p_phys_addr);
2605
2606         return ECORE_SUCCESS;
2607 }
2608
2609 static enum _ecore_status_t
2610 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
2611 {
2612         void *p_virt = OSAL_NULL;
2613         dma_addr_t p_phys = 0;
2614
2615         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
2616         if (!p_virt) {
2617                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
2618                 return ECORE_NOMEM;
2619         }
2620
2621         ecore_chain_init_mem(p_chain, p_virt, p_phys);
2622         ecore_chain_reset(p_chain);
2623
2624         return ECORE_SUCCESS;
2625 }
2626
2627 static enum _ecore_status_t ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
2628                                                   struct ecore_chain *p_chain)
2629 {
2630         void *p_virt = OSAL_NULL;
2631         u8 *p_pbl_virt = OSAL_NULL;
2632         void **pp_virt_addr_tbl = OSAL_NULL;
2633         dma_addr_t p_phys = 0, p_pbl_phys = 0;
2634         u32 page_cnt = p_chain->page_cnt, size, i;
2635
2636         size = page_cnt * sizeof(*pp_virt_addr_tbl);
2637         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
2638         if (!pp_virt_addr_tbl) {
2639                 DP_NOTICE(p_dev, true,
2640                           "Failed to allocate memory for the chain"
2641                           " virtual addresses table\n");
2642                 return ECORE_NOMEM;
2643         }
2644         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
2645
2646         /* The allocation of the PBL table is done with its full size, since it
2647          * is expected to be successive.
2648          */
2649         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
2650         p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
2651         if (!p_pbl_virt) {
2652                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
2653                 return ECORE_NOMEM;
2654         }
2655
2656         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2657                                  pp_virt_addr_tbl);
2658
2659         for (i = 0; i < page_cnt; i++) {
2660                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
2661                                                  ECORE_CHAIN_PAGE_SIZE);
2662                 if (!p_virt) {
2663                         DP_NOTICE(p_dev, true,
2664                                   "Failed to allocate chain memory\n");
2665                         return ECORE_NOMEM;
2666                 }
2667
2668                 if (i == 0) {
2669                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
2670                         ecore_chain_reset(p_chain);
2671                 }
2672
2673                 /* Fill the PBL table with the physical address of the page */
2674                 *(dma_addr_t *)p_pbl_virt = p_phys;
2675                 /* Keep the virtual address of the page */
2676                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2677
2678                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
2679         }
2680
2681         return ECORE_SUCCESS;
2682 }
2683
2684 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
2685                                        enum ecore_chain_use_mode intended_use,
2686                                        enum ecore_chain_mode mode,
2687                                        enum ecore_chain_cnt_type cnt_type,
2688                                        u32 num_elems, osal_size_t elem_size,
2689                                        struct ecore_chain *p_chain)
2690 {
2691         u32 page_cnt;
2692         enum _ecore_status_t rc = ECORE_SUCCESS;
2693
2694         if (mode == ECORE_CHAIN_MODE_SINGLE)
2695                 page_cnt = 1;
2696         else
2697                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2698
2699         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
2700                                             page_cnt);
2701         if (rc) {
2702                 DP_NOTICE(p_dev, true,
2703                           "Cannot allocate a chain with the given arguments:\n"
2704                           " [use_mode %d, mode %d, cnt_type %d, num_elems %d,"
2705                           " elem_size %zu]\n",
2706                           intended_use, mode, cnt_type, num_elems, elem_size);
2707                 return rc;
2708         }
2709
2710         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
2711                                 mode, cnt_type);
2712
2713         switch (mode) {
2714         case ECORE_CHAIN_MODE_NEXT_PTR:
2715                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
2716                 break;
2717         case ECORE_CHAIN_MODE_SINGLE:
2718                 rc = ecore_chain_alloc_single(p_dev, p_chain);
2719                 break;
2720         case ECORE_CHAIN_MODE_PBL:
2721                 rc = ecore_chain_alloc_pbl(p_dev, p_chain);
2722                 break;
2723         }
2724         if (rc)
2725                 goto nomem;
2726
2727         return ECORE_SUCCESS;
2728
2729 nomem:
2730         ecore_chain_free(p_dev, p_chain);
2731         return rc;
2732 }
2733
2734 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
2735                                        u16 src_id, u16 *dst_id)
2736 {
2737         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
2738                 u16 min, max;
2739
2740                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
2741                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
2742                 DP_NOTICE(p_hwfn, true,
2743                           "l2_queue id [%d] is not valid, available"
2744                           " indices [%d - %d]\n",
2745                           src_id, min, max);
2746
2747                 return ECORE_INVAL;
2748         }
2749
2750         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
2751
2752         return ECORE_SUCCESS;
2753 }
2754
2755 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
2756                                     u8 src_id, u8 *dst_id)
2757 {
2758         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
2759                 u8 min, max;
2760
2761                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
2762                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
2763                 DP_NOTICE(p_hwfn, true,
2764                           "vport id [%d] is not valid, available"
2765                           " indices [%d - %d]\n",
2766                           src_id, min, max);
2767
2768                 return ECORE_INVAL;
2769         }
2770
2771         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
2772
2773         return ECORE_SUCCESS;
2774 }
2775
2776 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
2777                                       u8 src_id, u8 *dst_id)
2778 {
2779         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
2780                 u8 min, max;
2781
2782                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
2783                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
2784                 DP_NOTICE(p_hwfn, true,
2785                           "rss_eng id [%d] is not valid,avail idx [%d - %d]\n",
2786                           src_id, min, max);
2787
2788                 return ECORE_INVAL;
2789         }
2790
2791         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
2792
2793         return ECORE_SUCCESS;
2794 }
2795
2796 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
2797                                               struct ecore_ptt *p_ptt,
2798                                               u8 *p_filter)
2799 {
2800         u32 high, low, en;
2801         int i;
2802
2803         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2804                 return ECORE_SUCCESS;
2805
2806         high = p_filter[1] | (p_filter[0] << 8);
2807         low = p_filter[5] | (p_filter[4] << 8) |
2808             (p_filter[3] << 16) | (p_filter[2] << 24);
2809
2810         /* Find a free entry and utilize it */
2811         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2812                 en = ecore_rd(p_hwfn, p_ptt,
2813                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2814                 if (en)
2815                         continue;
2816                 ecore_wr(p_hwfn, p_ptt,
2817                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2818                          2 * i * sizeof(u32), low);
2819                 ecore_wr(p_hwfn, p_ptt,
2820                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2821                          (2 * i + 1) * sizeof(u32), high);
2822                 ecore_wr(p_hwfn, p_ptt,
2823                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2824                 ecore_wr(p_hwfn, p_ptt,
2825                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2826                          i * sizeof(u32), 0);
2827                 ecore_wr(p_hwfn, p_ptt,
2828                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2829                 break;
2830         }
2831         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2832                 DP_NOTICE(p_hwfn, false,
2833                           "Failed to find an empty LLH filter to utilize\n");
2834                 return ECORE_INVAL;
2835         }
2836
2837         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2838                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
2839                    p_filter[0], p_filter[1], p_filter[2],
2840                    p_filter[3], p_filter[4], p_filter[5], i);
2841
2842         return ECORE_SUCCESS;
2843 }
2844
2845 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
2846                                  struct ecore_ptt *p_ptt, u8 *p_filter)
2847 {
2848         u32 high, low;
2849         int i;
2850
2851         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2852                 return;
2853
2854         high = p_filter[1] | (p_filter[0] << 8);
2855         low = p_filter[5] | (p_filter[4] << 8) |
2856             (p_filter[3] << 16) | (p_filter[2] << 24);
2857
2858         /* Find the entry and clean it */
2859         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2860                 if (ecore_rd(p_hwfn, p_ptt,
2861                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2862                              2 * i * sizeof(u32)) != low)
2863                         continue;
2864                 if (ecore_rd(p_hwfn, p_ptt,
2865                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2866                              (2 * i + 1) * sizeof(u32)) != high)
2867                         continue;
2868
2869                 ecore_wr(p_hwfn, p_ptt,
2870                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2871                 ecore_wr(p_hwfn, p_ptt,
2872                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2873                          2 * i * sizeof(u32), 0);
2874                 ecore_wr(p_hwfn, p_ptt,
2875                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2876                          (2 * i + 1) * sizeof(u32), 0);
2877                 break;
2878         }
2879         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2880                 DP_NOTICE(p_hwfn, false,
2881                           "Tried to remove a non-configured filter\n");
2882 }
2883
2884 enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn,
2885                                                     struct ecore_ptt *p_ptt,
2886                                                     u16 filter)
2887 {
2888         u32 high, low, en;
2889         int i;
2890
2891         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2892                 return ECORE_SUCCESS;
2893
2894         high = filter;
2895         low = 0;
2896
2897         /* Find a free entry and utilize it */
2898         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2899                 en = ecore_rd(p_hwfn, p_ptt,
2900                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2901                 if (en)
2902                         continue;
2903                 ecore_wr(p_hwfn, p_ptt,
2904                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2905                          2 * i * sizeof(u32), low);
2906                 ecore_wr(p_hwfn, p_ptt,
2907                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2908                          (2 * i + 1) * sizeof(u32), high);
2909                 ecore_wr(p_hwfn, p_ptt,
2910                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
2911                 ecore_wr(p_hwfn, p_ptt,
2912                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2913                          i * sizeof(u32), 1);
2914                 ecore_wr(p_hwfn, p_ptt,
2915                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2916                 break;
2917         }
2918         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2919                 DP_NOTICE(p_hwfn, false,
2920                           "Failed to find an empty LLH filter to utilize\n");
2921                 return ECORE_INVAL;
2922         }
2923
2924         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2925                    "ETH type: %x is added at %d\n", filter, i);
2926
2927         return ECORE_SUCCESS;
2928 }
2929
2930 void ecore_llh_remove_ethertype_filter(struct ecore_hwfn *p_hwfn,
2931                                        struct ecore_ptt *p_ptt, u16 filter)
2932 {
2933         u32 high, low;
2934         int i;
2935
2936         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2937                 return;
2938
2939         high = filter;
2940         low = 0;
2941
2942         /* Find the entry and clean it */
2943         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2944                 if (ecore_rd(p_hwfn, p_ptt,
2945                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2946                              2 * i * sizeof(u32)) != low)
2947                         continue;
2948                 if (ecore_rd(p_hwfn, p_ptt,
2949                              NIG_REG_LLH_FUNC_FILTER_VALUE +
2950                              (2 * i + 1) * sizeof(u32)) != high)
2951                         continue;
2952
2953                 ecore_wr(p_hwfn, p_ptt,
2954                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2955                 ecore_wr(p_hwfn, p_ptt,
2956                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2957                          2 * i * sizeof(u32), 0);
2958                 ecore_wr(p_hwfn, p_ptt,
2959                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2960                          (2 * i + 1) * sizeof(u32), 0);
2961                 break;
2962         }
2963         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2964                 DP_NOTICE(p_hwfn, false,
2965                           "Tried to remove a non-configured filter\n");
2966 }
2967
2968 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
2969                                  struct ecore_ptt *p_ptt)
2970 {
2971         int i;
2972
2973         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2974                 return;
2975
2976         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2977                 ecore_wr(p_hwfn, p_ptt,
2978                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2979                 ecore_wr(p_hwfn, p_ptt,
2980                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2981                          2 * i * sizeof(u32), 0);
2982                 ecore_wr(p_hwfn, p_ptt,
2983                          NIG_REG_LLH_FUNC_FILTER_VALUE +
2984                          (2 * i + 1) * sizeof(u32), 0);
2985         }
2986 }
2987
2988 enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn,
2989                                           struct ecore_ptt *p_ptt)
2990 {
2991         u32 reg_tbl[] = {
2992                 BRB_REG_HEADER_SIZE,
2993                 BTB_REG_HEADER_SIZE,
2994                 CAU_REG_LONG_TIMEOUT_THRESHOLD,
2995                 CCFC_REG_ACTIVITY_COUNTER,
2996                 CDU_REG_CID_ADDR_PARAMS,
2997                 DBG_REG_CLIENT_ENABLE,
2998                 DMAE_REG_INIT,
2999                 DORQ_REG_IFEN,
3000                 GRC_REG_TIMEOUT_EN,
3001                 IGU_REG_BLOCK_CONFIGURATION,
3002                 MCM_REG_INIT,
3003                 MCP2_REG_DBG_DWORD_ENABLE,
3004                 MISC_REG_PORT_MODE,
3005                 MISCS_REG_CLK_100G_MODE,
3006                 MSDM_REG_ENABLE_IN1,
3007                 MSEM_REG_ENABLE_IN,
3008                 NIG_REG_CM_HDR,
3009                 NCSI_REG_CONFIG,
3010                 PBF_REG_INIT,
3011                 PTU_REG_ATC_INIT_ARRAY,
3012                 PCM_REG_INIT,
3013                 PGLUE_B_REG_ADMIN_PER_PF_REGION,
3014                 PRM_REG_DISABLE_PRM,
3015                 PRS_REG_SOFT_RST,
3016                 PSDM_REG_ENABLE_IN1,
3017                 PSEM_REG_ENABLE_IN,
3018                 PSWRQ_REG_DBG_SELECT,
3019                 PSWRQ2_REG_CDUT_P_SIZE,
3020                 PSWHST_REG_DISCARD_INTERNAL_WRITES,
3021                 PSWHST2_REG_DBGSYN_ALMOST_FULL_THR,
3022                 PSWRD_REG_DBG_SELECT,
3023                 PSWRD2_REG_CONF11,
3024                 PSWWR_REG_USDM_FULL_TH,
3025                 PSWWR2_REG_CDU_FULL_TH2,
3026                 QM_REG_MAXPQSIZE_0,
3027                 RSS_REG_RSS_INIT_EN,
3028                 RDIF_REG_STOP_ON_ERROR,
3029                 SRC_REG_SOFT_RST,
3030                 TCFC_REG_ACTIVITY_COUNTER,
3031                 TCM_REG_INIT,
3032                 TM_REG_PXP_READ_DATA_FIFO_INIT,
3033                 TSDM_REG_ENABLE_IN1,
3034                 TSEM_REG_ENABLE_IN,
3035                 TDIF_REG_STOP_ON_ERROR,
3036                 UCM_REG_INIT,
3037                 UMAC_REG_IPG_HD_BKP_CNTL_BB_B0,
3038                 USDM_REG_ENABLE_IN1,
3039                 USEM_REG_ENABLE_IN,
3040                 XCM_REG_INIT,
3041                 XSDM_REG_ENABLE_IN1,
3042                 XSEM_REG_ENABLE_IN,
3043                 YCM_REG_INIT,
3044                 YSDM_REG_ENABLE_IN1,
3045                 YSEM_REG_ENABLE_IN,
3046                 XYLD_REG_SCBD_STRICT_PRIO,
3047                 TMLD_REG_SCBD_STRICT_PRIO,
3048                 MULD_REG_SCBD_STRICT_PRIO,
3049                 YULD_REG_SCBD_STRICT_PRIO,
3050         };
3051         u32 test_val[] = { 0x0, 0x1 };
3052         u32 val, save_val, i, j;
3053
3054         for (i = 0; i < OSAL_ARRAY_SIZE(test_val); i++) {
3055                 for (j = 0; j < OSAL_ARRAY_SIZE(reg_tbl); j++) {
3056                         save_val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
3057                         ecore_wr(p_hwfn, p_ptt, reg_tbl[j], test_val[i]);
3058                         val = ecore_rd(p_hwfn, p_ptt, reg_tbl[j]);
3059                         /* Restore the original register's value */
3060                         ecore_wr(p_hwfn, p_ptt, reg_tbl[j], save_val);
3061                         if (val != test_val[i]) {
3062                                 DP_INFO(p_hwfn->p_dev,
3063                                         "offset 0x%x: val 0x%x != 0x%x\n",
3064                                         reg_tbl[j], val, test_val[i]);
3065                                 return ECORE_AGAIN;
3066                         }
3067                 }
3068         }
3069         return ECORE_SUCCESS;
3070 }
3071
3072 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3073                                                struct ecore_ptt *p_ptt,
3074                                                u32 hw_addr, void *p_qzone,
3075                                                osal_size_t qzone_size,
3076                                                u8 timeset)
3077 {
3078         struct coalescing_timeset *p_coalesce_timeset;
3079
3080         if (IS_VF(p_hwfn->p_dev)) {
3081                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3082                 return ECORE_INVAL;
3083         }
3084
3085         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3086                 DP_NOTICE(p_hwfn, true,
3087                           "Coalescing configuration not enabled\n");
3088                 return ECORE_INVAL;
3089         }
3090
3091         OSAL_MEMSET(p_qzone, 0, qzone_size);
3092         p_coalesce_timeset = p_qzone;
3093         p_coalesce_timeset->timeset = timeset;
3094         p_coalesce_timeset->valid = 1;
3095         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_qzone, qzone_size);
3096
3097         return ECORE_SUCCESS;
3098 }
3099
3100 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3101                                             struct ecore_ptt *p_ptt,
3102                                             u8 coalesce, u8 qid)
3103 {
3104         struct ustorm_eth_queue_zone qzone;
3105         u16 fw_qid = 0;
3106         u32 address;
3107         u8 timeset;
3108         enum _ecore_status_t rc;
3109
3110         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3111         if (rc != ECORE_SUCCESS)
3112                 return rc;
3113
3114         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3115         /* Translate the coalescing time into a timeset, according to:
3116          * Timeout[Rx] = TimeSet[Rx] << (TimerRes[Rx] + 1)
3117          */
3118         timeset = coalesce >> (ECORE_CAU_DEF_RX_TIMER_RES + 1);
3119
3120         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
3121                                 sizeof(struct ustorm_eth_queue_zone), timeset);
3122         if (rc != ECORE_SUCCESS)
3123                 goto out;
3124
3125         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3126 out:
3127         return rc;
3128 }
3129
3130 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3131                                             struct ecore_ptt *p_ptt,
3132                                             u8 coalesce, u8 qid)
3133 {
3134         struct ystorm_eth_queue_zone qzone;
3135         u16 fw_qid = 0;
3136         u32 address;
3137         u8 timeset;
3138         enum _ecore_status_t rc;
3139
3140         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3141         if (rc != ECORE_SUCCESS)
3142                 return rc;
3143
3144         address = BAR0_MAP_REG_YSDM_RAM + YSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3145         /* Translate the coalescing time into a timeset, according to:
3146          * Timeout[Tx] = TimeSet[Tx] << (TimerRes[Tx] + 1)
3147          */
3148         timeset = coalesce >> (ECORE_CAU_DEF_TX_TIMER_RES + 1);
3149
3150         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &qzone,
3151                                 sizeof(struct ystorm_eth_queue_zone), timeset);
3152         if (rc != ECORE_SUCCESS)
3153                 goto out;
3154
3155         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3156 out:
3157         return rc;
3158 }
3159
3160 /* Calculate final WFQ values for all vports and configure it.
3161  * After this configuration each vport must have
3162  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3163  */
3164 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3165                                                struct ecore_ptt *p_ptt,
3166                                                u32 min_pf_rate)
3167 {
3168         struct init_qm_vport_params *vport_params;
3169         int i, num_vports;
3170
3171         vport_params = p_hwfn->qm_info.qm_vport_params;
3172         num_vports = p_hwfn->qm_info.num_vports;
3173
3174         for (i = 0; i < num_vports; i++) {
3175                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3176
3177                 vport_params[i].vport_wfq =
3178                     (wfq_speed * ECORE_WFQ_UNIT) / min_pf_rate;
3179                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3180                                      vport_params[i].first_tx_pq_id,
3181                                      vport_params[i].vport_wfq);
3182         }
3183 }
3184
3185 static void
3186 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3187 {
3188         int i, num_vports;
3189         u32 min_speed;
3190
3191         num_vports = p_hwfn->qm_info.num_vports;
3192         min_speed = min_pf_rate / num_vports;
3193
3194         for (i = 0; i < num_vports; i++) {
3195                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3196                 p_hwfn->qm_info.wfq_data[i].default_min_speed = min_speed;
3197         }
3198 }
3199
3200 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3201                                              struct ecore_ptt *p_ptt,
3202                                              u32 min_pf_rate)
3203 {
3204         struct init_qm_vport_params *vport_params;
3205         int i, num_vports;
3206
3207         vport_params = p_hwfn->qm_info.qm_vport_params;
3208         num_vports = p_hwfn->qm_info.num_vports;
3209
3210         for (i = 0; i < num_vports; i++) {
3211                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3212                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3213                                      vport_params[i].first_tx_pq_id,
3214                                      vport_params[i].vport_wfq);
3215         }
3216 }
3217
3218 /* validate wfq for a given vport and required min rate */
3219 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3220                                                  u16 vport_id, u32 req_rate,
3221                                                  u32 min_pf_rate)
3222 {
3223         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3224         int non_requested_count = 0, req_count = 0, i, num_vports;
3225
3226         num_vports = p_hwfn->qm_info.num_vports;
3227
3228         /* Check pre-set data for some of the vports */
3229         for (i = 0; i < num_vports; i++) {
3230                 u32 tmp_speed;
3231
3232                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3233                         req_count++;
3234                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3235                         total_req_min_rate += tmp_speed;
3236                 }
3237         }
3238
3239         /* Include current vport data as well */
3240         req_count++;
3241         total_req_min_rate += req_rate;
3242         non_requested_count = p_hwfn->qm_info.num_vports - req_count;
3243
3244         /* validate possible error cases */
3245         if (req_rate > min_pf_rate) {
3246                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3247                            "Vport [%d] - Requested rate[%d Mbps] is greater"
3248                            " than configured PF min rate[%d Mbps]\n",
3249                            vport_id, req_rate, min_pf_rate);
3250                 return ECORE_INVAL;
3251         }
3252
3253         if (req_rate * ECORE_WFQ_UNIT / min_pf_rate < 1) {
3254                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3255                            "Vport [%d] - Requested rate[%d Mbps] is less than"
3256                            " one percent of configured PF min rate[%d Mbps]\n",
3257                            vport_id, req_rate, min_pf_rate);
3258                 return ECORE_INVAL;
3259         }
3260
3261         /* TBD - for number of vports greater than 100 */
3262         if (ECORE_WFQ_UNIT / p_hwfn->qm_info.num_vports < 1) {
3263                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3264                            "Number of vports are greater than 100\n");
3265                 return ECORE_INVAL;
3266         }
3267
3268         if (total_req_min_rate > min_pf_rate) {
3269                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3270                            "Total requested min rate for all vports[%d Mbps]"
3271                            "is greater than configured PF min rate[%d Mbps]\n",
3272                            total_req_min_rate, min_pf_rate);
3273                 return ECORE_INVAL;
3274         }
3275
3276         /* Data left for non requested vports */
3277         total_left_rate = min_pf_rate - total_req_min_rate;
3278         left_rate_per_vp = total_left_rate / non_requested_count;
3279
3280         /* validate if non requested get < 1% of min bw */
3281         if (left_rate_per_vp * ECORE_WFQ_UNIT / min_pf_rate < 1)
3282                 return ECORE_INVAL;
3283
3284         /* now req_rate for given vport passes all scenarios.
3285          * assign final wfq rates to all vports.
3286          */
3287         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3288         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3289
3290         for (i = 0; i < num_vports; i++) {
3291                 if (p_hwfn->qm_info.wfq_data[i].configured)
3292                         continue;
3293
3294                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3295         }
3296
3297         return ECORE_SUCCESS;
3298 }
3299
3300 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
3301                                        struct ecore_ptt *p_ptt,
3302                                        u16 vp_id, u32 rate)
3303 {
3304         struct ecore_mcp_link_state *p_link;
3305         int rc = ECORE_SUCCESS;
3306
3307         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
3308
3309         if (!p_link->min_pf_rate) {
3310                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3311                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3312                 return rc;
3313         }
3314
3315         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3316
3317         if (rc == ECORE_SUCCESS)
3318                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3319                                                    p_link->min_pf_rate);
3320         else
3321                 DP_NOTICE(p_hwfn, false,
3322                           "Validation failed while configuring min rate\n");
3323
3324         return rc;
3325 }
3326
3327 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
3328                                                    struct ecore_ptt *p_ptt,
3329                                                    u32 min_pf_rate)
3330 {
3331         int rc = ECORE_SUCCESS;
3332         bool use_wfq = false;
3333         u16 i, num_vports;
3334
3335         num_vports = p_hwfn->qm_info.num_vports;
3336
3337         /* Validate all pre configured vports for wfq */
3338         for (i = 0; i < num_vports; i++) {
3339                 if (p_hwfn->qm_info.wfq_data[i].configured) {
3340                         u32 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3341
3342                         use_wfq = true;
3343                         rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3344                         if (rc == ECORE_INVAL) {
3345                                 DP_NOTICE(p_hwfn, false,
3346                                           "Validation failed while"
3347                                           " configuring min rate\n");
3348                                 break;
3349                         }
3350                 }
3351         }
3352
3353         if (rc == ECORE_SUCCESS && use_wfq)
3354                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3355         else
3356                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3357
3358         return rc;
3359 }
3360
3361 /* Main API for ecore clients to configure vport min rate.
3362  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3363  * rate - Speed in Mbps needs to be assigned to a given vport.
3364  */
3365 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
3366 {
3367         int i, rc = ECORE_INVAL;
3368
3369         /* TBD - for multiple hardware functions - that is 100 gig */
3370         if (p_dev->num_hwfns > 1) {
3371                 DP_NOTICE(p_dev, false,
3372                           "WFQ configuration is not supported for this dev\n");
3373                 return rc;
3374         }
3375
3376         for_each_hwfn(p_dev, i) {
3377                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3378                 struct ecore_ptt *p_ptt;
3379
3380                 p_ptt = ecore_ptt_acquire(p_hwfn);
3381                 if (!p_ptt)
3382                         return ECORE_TIMEOUT;
3383
3384                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3385
3386                 if (rc != ECORE_SUCCESS) {
3387                         ecore_ptt_release(p_hwfn, p_ptt);
3388                         return rc;
3389                 }
3390
3391                 ecore_ptt_release(p_hwfn, p_ptt);
3392         }
3393
3394         return rc;
3395 }
3396
3397 /* API to configure WFQ from mcp link change */
3398 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
3399                                            u32 min_pf_rate)
3400 {
3401         int i;
3402
3403         /* TBD - for multiple hardware functions - that is 100 gig */
3404         if (p_dev->num_hwfns > 1) {
3405                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
3406                            "WFQ configuration is not supported for this dev\n");
3407                 return;
3408         }
3409
3410         for_each_hwfn(p_dev, i) {
3411                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3412
3413                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3414                                                         p_hwfn->p_dpc_ptt,
3415                                                         min_pf_rate);
3416         }
3417 }
3418
3419 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
3420                                        struct ecore_ptt *p_ptt,
3421                                        struct ecore_mcp_link_state *p_link,
3422                                        u8 max_bw)
3423 {
3424         int rc = ECORE_SUCCESS;
3425
3426         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3427
3428         if (!p_link->line_speed)
3429                 return rc;
3430
3431         p_link->speed = (p_link->line_speed * max_bw) / 100;
3432
3433         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, p_link->speed);
3434
3435         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3436                    "Configured MAX bandwidth to be %08x Mb/sec\n",
3437                    p_link->speed);
3438
3439         return rc;
3440 }
3441
3442 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3443 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
3444 {
3445         int i, rc = ECORE_INVAL;
3446
3447         if (max_bw < 1 || max_bw > 100) {
3448                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
3449                 return rc;
3450         }
3451
3452         for_each_hwfn(p_dev, i) {
3453                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3454                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3455                 struct ecore_mcp_link_state *p_link;
3456                 struct ecore_ptt *p_ptt;
3457
3458                 p_link = &p_lead->mcp_info->link_output;
3459
3460                 p_ptt = ecore_ptt_acquire(p_hwfn);
3461                 if (!p_ptt)
3462                         return ECORE_TIMEOUT;
3463
3464                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3465                                                         p_link, max_bw);
3466                 if (rc != ECORE_SUCCESS) {
3467                         ecore_ptt_release(p_hwfn, p_ptt);
3468                         return rc;
3469                 }
3470
3471                 ecore_ptt_release(p_hwfn, p_ptt);
3472         }
3473
3474         return rc;
3475 }
3476
3477 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
3478                                        struct ecore_ptt *p_ptt,
3479                                        struct ecore_mcp_link_state *p_link,
3480                                        u8 min_bw)
3481 {
3482         int rc = ECORE_SUCCESS;
3483
3484         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3485
3486         if (!p_link->line_speed)
3487                 return rc;
3488
3489         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3490
3491         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3492
3493         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3494                    "Configured MIN bandwidth to be %d Mb/sec\n",
3495                    p_link->min_pf_rate);
3496
3497         return rc;
3498 }
3499
3500 /* Main API to configure PF min bandwidth where bw range is [1-100] */
3501 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
3502 {
3503         int i, rc = ECORE_INVAL;
3504
3505         if (min_bw < 1 || min_bw > 100) {
3506                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
3507                 return rc;
3508         }
3509
3510         for_each_hwfn(p_dev, i) {
3511                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3512                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
3513                 struct ecore_mcp_link_state *p_link;
3514                 struct ecore_ptt *p_ptt;
3515
3516                 p_link = &p_lead->mcp_info->link_output;
3517
3518                 p_ptt = ecore_ptt_acquire(p_hwfn);
3519                 if (!p_ptt)
3520                         return ECORE_TIMEOUT;
3521
3522                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
3523                                                         p_link, min_bw);
3524                 if (rc != ECORE_SUCCESS) {
3525                         ecore_ptt_release(p_hwfn, p_ptt);
3526                         return rc;
3527                 }
3528
3529                 if (p_link->min_pf_rate) {
3530                         u32 min_rate = p_link->min_pf_rate;
3531
3532                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
3533                                                                      p_ptt,
3534                                                                      min_rate);
3535                 }
3536
3537                 ecore_ptt_release(p_hwfn, p_ptt);
3538         }
3539
3540         return rc;
3541 }
3542
3543 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
3544 {
3545         struct ecore_mcp_link_state *p_link;
3546
3547         p_link = &p_hwfn->mcp_info->link_output;
3548
3549         if (p_link->min_pf_rate)
3550                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
3551                                                  p_link->min_pf_rate);
3552
3553         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
3554                     sizeof(*p_hwfn->qm_info.wfq_data) *
3555                     p_hwfn->qm_info.num_vports);
3556 }
3557
3558 int ecore_device_num_engines(struct ecore_dev *p_dev)
3559 {
3560         return ECORE_IS_BB(p_dev) ? 2 : 1;
3561 }
3562
3563 int ecore_device_num_ports(struct ecore_dev *p_dev)
3564 {
3565         /* in CMT always only one port */
3566         if (p_dev->num_hwfns > 1)
3567                 return 1;
3568
3569         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
3570 }