drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /* Configurable */
  46 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  47                                          * load the driver. The number was
  48                                          * arbitrarily set.
  49                                          */
  50
  51 /* Derived */
  52 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  53
  54 enum BAR_ID {
  55         BAR_ID_0,               /* used for GRC */
  56         BAR_ID_1                /* Used for doorbells */
  57 };
  58
  59 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  60 {
  61         u32 bar_reg = (bar_id == BAR_ID_0 ?
  62                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  63         u32 val;
  64
  65         if (IS_VF(p_hwfn->p_dev)) {
  66                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  67                  * read from actual register, but we're currently not using
  68                  * it for actual doorbelling.
  69                  */
  70                 return 1 << 17;
  71         }
  72
  73         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  74         if (val)
  75                 return 1 << (val + 15);
  76
  77         /* The above registers were updated in the past only in CMT mode. Since
  78          * they were found to be useful MFW started updating them from 8.7.7.0.
  79          * In older MFW versions they are set to 0 which means disabled.
  80          */
  81         if (p_hwfn->p_dev->num_hwfns > 1) {
  82                 DP_NOTICE(p_hwfn, false,
  83                           "BAR size not configured. Assuming BAR size of 256kB"
  84                           " for GRC and 512kB for DB\n");
  85                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  86         } else {
  87                 DP_NOTICE(p_hwfn, false,
  88                           "BAR size not configured. Assuming BAR size of 512kB"
  89                           " for GRC and 512kB for DB\n");
  90                 val = 512 * 1024;
  91         }
  92
  93         return val;
  94 }
  95
  96 void ecore_init_dp(struct ecore_dev *p_dev,
  97                    u32 dp_module, u8 dp_level, void *dp_ctx)
  98 {
  99         u32 i;
 100
 101         p_dev->dp_level = dp_level;
 102         p_dev->dp_module = dp_module;
 103         p_dev->dp_ctx = dp_ctx;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109                 p_hwfn->dp_ctx = dp_ctx;
 110         }
 111 }
 112
 113 void ecore_init_struct(struct ecore_dev *p_dev)
 114 {
 115         u8 i;
 116
 117         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 118                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 119
 120                 p_hwfn->p_dev = p_dev;
 121                 p_hwfn->my_id = i;
 122                 p_hwfn->b_active = false;
 123
 124                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 125                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 126         }
 127
 128         /* hwfn 0 is always active */
 129         p_dev->hwfns[0].b_active = true;
 130
 131         /* set the default cache alignment to 128 (may be overridden later) */
 132         p_dev->cache_shift = 7;
 133 }
 134
 135 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 136 {
 137         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 138
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 142         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 143 }
 144
 145 void ecore_resc_free(struct ecore_dev *p_dev)
 146 {
 147         int i;
 148
 149         if (IS_VF(p_dev)) {
 150                 for_each_hwfn(p_dev, i)
 151                         ecore_l2_free(&p_dev->hwfns[i]);
 152                 return;
 153         }
 154
 155         OSAL_FREE(p_dev, p_dev->fw_data);
 156
 157         OSAL_FREE(p_dev, p_dev->reset_stats);
 158
 159         for_each_hwfn(p_dev, i) {
 160                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 161
 162                 ecore_cxt_mngr_free(p_hwfn);
 163                 ecore_qm_info_free(p_hwfn);
 164                 ecore_spq_free(p_hwfn);
 165                 ecore_eq_free(p_hwfn);
 166                 ecore_consq_free(p_hwfn);
 167                 ecore_int_free(p_hwfn);
 168                 ecore_iov_free(p_hwfn);
 169                 ecore_l2_free(p_hwfn);
 170                 ecore_dmae_info_free(p_hwfn);
 171                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 172                 /* @@@TBD Flush work-queue ? */
 173         }
 174 }
 175
 176 /******************** QM initialization *******************/
 177
 178 /* bitmaps for indicating active traffic classes.
 179  * Special case for Arrowhead 4 port
 180  */
 181 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 182 #define ACTIVE_TCS_BMAP 0x9f
 183 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 184 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 185
 186 /* determines the physical queue flags for a given PF. */
 187 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 188 {
 189         u32 flags;
 190
 191         /* common flags */
 192         flags = PQ_FLAGS_LB;
 193
 194         /* feature flags */
 195         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 196                 flags |= PQ_FLAGS_VFS;
 197
 198         /* protocol flags */
 199         switch (p_hwfn->hw_info.personality) {
 200         case ECORE_PCI_ETH:
 201                 flags |= PQ_FLAGS_MCOS;
 202                 break;
 203         case ECORE_PCI_FCOE:
 204                 flags |= PQ_FLAGS_OFLD;
 205                 break;
 206         case ECORE_PCI_ISCSI:
 207                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 208                 break;
 209         case ECORE_PCI_ETH_ROCE:
 210                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 211                 break;
 212         case ECORE_PCI_ETH_IWARP:
 213                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 214                          PQ_FLAGS_OFLD;
 215                 break;
 216         default:
 217                 DP_ERR(p_hwfn, "unknown personality %d\n",
 218                        p_hwfn->hw_info.personality);
 219                 return 0;
 220         }
 221         return flags;
 222 }
 223
 224 /* Getters for resource amounts necessary for qm initialization */
 225 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 226 {
 227         return p_hwfn->hw_info.num_hw_tc;
 228 }
 229
 230 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 231 {
 232         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 233                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 234 }
 235
 236 #define NUM_DEFAULT_RLS 1
 237
 238 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 239 {
 240         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 241
 242         /* @DPDK */
 243         /* num RLs can't exceed resource amount of rls or vports or the
 244          * dcqcn qps
 245          */
 246         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 247                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 248
 249         /* make sure after we reserve the default and VF rls we'll have
 250          * something left
 251          */
 252         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 253                 DP_NOTICE(p_hwfn, false,
 254                           "no rate limiters left for PF rate limiting"
 255                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 256                 return 0;
 257         }
 258
 259         /* subtract rls necessary for VFs and one default one for the PF */
 260         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 261
 262         return num_pf_rls;
 263 }
 264
 265 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 266 {
 267         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 268
 269         /* all pqs share the same vport (hence the 1 below), except for vfs
 270          * and pf_rl pqs
 271          */
 272         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 273                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 274                (!!(PQ_FLAGS_VFS & pq_flags)) *
 275                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 276 }
 277
 278 /* calc amount of PQs according to the requested flags */
 279 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 280 {
 281         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 282
 283         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 284                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 285                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 286                 ecore_init_qm_get_num_tcs(p_hwfn) +
 287                (!!(PQ_FLAGS_LB & pq_flags)) +
 288                (!!(PQ_FLAGS_OOO & pq_flags)) +
 289                (!!(PQ_FLAGS_ACK & pq_flags)) +
 290                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 291                (!!(PQ_FLAGS_VFS & pq_flags)) *
 292                 ecore_init_qm_get_num_vfs(p_hwfn);
 293 }
 294
 295 /* initialize the top level QM params */
 296 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 297 {
 298         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 299         bool four_port;
 300
 301         /* pq and vport bases for this PF */
 302         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 303         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 304
 305         /* rate limiting and weighted fair queueing are always enabled */
 306         qm_info->vport_rl_en = 1;
 307         qm_info->vport_wfq_en = 1;
 308
 309         /* TC config is different for AH 4 port */
 310         four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
 311
 312         /* in AH 4 port we have fewer TCs per port */
 313         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 314                                                      NUM_OF_PHYS_TCS;
 315
 316         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 317          * 4 otherwise
 318          */
 319         if (!qm_info->ooo_tc)
 320                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 321                                               DCBX_TCP_OOO_TC;
 322 }
 323
 324 /* initialize qm vport params */
 325 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 326 {
 327         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 328         u8 i;
 329
 330         /* all vports participate in weighted fair queueing */
 331         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 332                 qm_info->qm_vport_params[i].vport_wfq = 1;
 333 }
 334
 335 /* initialize qm port params */
 336 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 337 {
 338         /* Initialize qm port parameters */
 339         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
 340
 341         /* indicate how ooo and high pri traffic is dealt with */
 342         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 343                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 344
 345         for (i = 0; i < num_ports; i++) {
 346                 struct init_qm_port_params *p_qm_port =
 347                         &p_hwfn->qm_info.qm_port_params[i];
 348
 349                 p_qm_port->active = 1;
 350                 p_qm_port->active_phys_tcs = active_phys_tcs;
 351                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 352                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 353         }
 354 }
 355
 356 /* Reset the params which must be reset for qm init. QM init may be called as
 357  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 358  * params may be affected by the init but would simply recalculate to the same
 359  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 360  * affected as these amounts stay the same.
 361  */
 362 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 363 {
 364         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 365
 366         qm_info->num_pqs = 0;
 367         qm_info->num_vports = 0;
 368         qm_info->num_pf_rls = 0;
 369         qm_info->num_vf_pqs = 0;
 370         qm_info->first_vf_pq = 0;
 371         qm_info->first_mcos_pq = 0;
 372         qm_info->first_rl_pq = 0;
 373 }
 374
 375 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 376 {
 377         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 378
 379         qm_info->num_vports++;
 380
 381         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 382                 DP_ERR(p_hwfn,
 383                        "vport overflow! qm_info->num_vports %d,"
 384                        " qm_init_get_num_vports() %d\n",
 385                        qm_info->num_vports,
 386                        ecore_init_qm_get_num_vports(p_hwfn));
 387 }
 388
 389 /* initialize a single pq and manage qm_info resources accounting.
 390  * The pq_init_flags param determines whether the PQ is rate limited
 391  * (for VF or PF)
 392  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 393  * shared)
 394  */
 395
 396 /* flags for pq init */
 397 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 398 #define PQ_INIT_PF_RL           (1 << 1)
 399 #define PQ_INIT_VF_RL           (1 << 2)
 400
 401 /* defines for pq init */
 402 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 403 #define PQ_INIT_DEFAULT_TC              0
 404 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 405
 406 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 407                              struct ecore_qm_info *qm_info,
 408                              u8 tc, u32 pq_init_flags)
 409 {
 410         u16 pq_idx = qm_info->num_pqs, max_pq =
 411                                         ecore_init_qm_get_num_pqs(p_hwfn);
 412
 413         if (pq_idx > max_pq)
 414                 DP_ERR(p_hwfn,
 415                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 416
 417         /* init pq params */
 418         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 419                                                  qm_info->num_vports;
 420         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 421         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 422         qm_info->qm_pq_params[pq_idx].rl_valid =
 423                 (pq_init_flags & PQ_INIT_PF_RL ||
 424                  pq_init_flags & PQ_INIT_VF_RL);
 425
 426         /* qm params accounting */
 427         qm_info->num_pqs++;
 428         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 429                 qm_info->num_vports++;
 430
 431         if (pq_init_flags & PQ_INIT_PF_RL)
 432                 qm_info->num_pf_rls++;
 433
 434         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 435                 DP_ERR(p_hwfn,
 436                        "vport overflow! qm_info->num_vports %d,"
 437                        " qm_init_get_num_vports() %d\n",
 438                        qm_info->num_vports,
 439                        ecore_init_qm_get_num_vports(p_hwfn));
 440
 441         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 442                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 443                        " qm_init_get_num_pf_rls() %d\n",
 444                        qm_info->num_pf_rls,
 445                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 446 }
 447
 448 /* get pq index according to PQ_FLAGS */
 449 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 450                                              u32 pq_flags)
 451 {
 452         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 453
 454         /* Can't have multiple flags set here */
 455         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 456                                 sizeof(pq_flags)) > 1)
 457                 goto err;
 458
 459         switch (pq_flags) {
 460         case PQ_FLAGS_RLS:
 461                 return &qm_info->first_rl_pq;
 462         case PQ_FLAGS_MCOS:
 463                 return &qm_info->first_mcos_pq;
 464         case PQ_FLAGS_LB:
 465                 return &qm_info->pure_lb_pq;
 466         case PQ_FLAGS_OOO:
 467                 return &qm_info->ooo_pq;
 468         case PQ_FLAGS_ACK:
 469                 return &qm_info->pure_ack_pq;
 470         case PQ_FLAGS_OFLD:
 471                 return &qm_info->offload_pq;
 472         case PQ_FLAGS_VFS:
 473                 return &qm_info->first_vf_pq;
 474         default:
 475                 goto err;
 476         }
 477
 478 err:
 479         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 480         return OSAL_NULL;
 481 }
 482
 483 /* save pq index in qm info */
 484 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 485                                   u32 pq_flags, u16 pq_val)
 486 {
 487         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 488
 489         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 490 }
 491
 492 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 493 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 494 {
 495         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 496
 497         return *base_pq_idx + CM_TX_PQ_BASE;
 498 }
 499
 500 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 501 {
 502         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 503
 504         if (tc > max_tc)
 505                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 506
 507         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 508 }
 509
 510 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 511 {
 512         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 513
 514         if (vf > max_vf)
 515                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 516
 517         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 518 }
 519
 520 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 521 {
 522         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 523
 524         if (rl > max_rl)
 525                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 526
 527         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 528 }
 529
 530 /* Functions for creating specific types of pqs */
 531 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 532 {
 533         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 534
 535         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 536                 return;
 537
 538         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 539         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 540 }
 541
 542 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 543 {
 544         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 545
 546         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 547                 return;
 548
 549         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 550         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 551 }
 552
 553 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 554 {
 555         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 556
 557         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 558                 return;
 559
 560         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 561         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 562 }
 563
 564 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 565 {
 566         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 567
 568         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 569                 return;
 570
 571         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 572         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 573 }
 574
 575 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 576 {
 577         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 578         u8 tc_idx;
 579
 580         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 581                 return;
 582
 583         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 584         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 585                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 586 }
 587
 588 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 589 {
 590         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 591         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 592
 593         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 594                 return;
 595
 596         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 597
 598         qm_info->num_vf_pqs = num_vfs;
 599         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 600                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 601                                  PQ_INIT_VF_RL);
 602 }
 603
 604 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 605 {
 606         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 607         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 608
 609         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 610                 return;
 611
 612         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 613         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 614                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 615                                  PQ_INIT_PF_RL);
 616 }
 617
 618 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 619 {
 620         /* rate limited pqs, must come first (FW assumption) */
 621         ecore_init_qm_rl_pqs(p_hwfn);
 622
 623         /* pqs for multi cos */
 624         ecore_init_qm_mcos_pqs(p_hwfn);
 625
 626         /* pure loopback pq */
 627         ecore_init_qm_lb_pq(p_hwfn);
 628
 629         /* out of order pq */
 630         ecore_init_qm_ooo_pq(p_hwfn);
 631
 632         /* pure ack pq */
 633         ecore_init_qm_pure_ack_pq(p_hwfn);
 634
 635         /* pq for offloaded protocol */
 636         ecore_init_qm_offload_pq(p_hwfn);
 637
 638         /* done sharing vports */
 639         ecore_init_qm_advance_vport(p_hwfn);
 640
 641         /* pqs for vfs */
 642         ecore_init_qm_vf_pqs(p_hwfn);
 643 }
 644
 645 /* compare values of getters against resources amounts */
 646 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 647 {
 648         if (ecore_init_qm_get_num_vports(p_hwfn) >
 649             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 650                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 651                 return ECORE_INVAL;
 652         }
 653
 654         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 655                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 656                 return ECORE_INVAL;
 657         }
 658
 659         return ECORE_SUCCESS;
 660 }
 661
 662 /*
 663  * Function for verbose printing of the qm initialization results
 664  */
 665 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 666 {
 667         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 668         struct init_qm_vport_params *vport;
 669         struct init_qm_port_params *port;
 670         struct init_qm_pq_params *pq;
 671         int i, tc;
 672
 673         /* top level params */
 674         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 675                    "qm init top level params: start_pq %d, start_vport %d,"
 676                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 677                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 678                    qm_info->offload_pq, qm_info->pure_ack_pq);
 679         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 680                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 681                    " num_vports %d, max_phys_tcs_per_port %d\n",
 682                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 683                    qm_info->num_vf_pqs, qm_info->num_vports,
 684                    qm_info->max_phys_tcs_per_port);
 685         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 686                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 687                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 688                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 689                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 690                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 691
 692         /* port table */
 693         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
 694                 port = &qm_info->qm_port_params[i];
 695                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 696                            "port idx %d, active %d, active_phys_tcs %d,"
 697                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
 698                            " reserved %d\n",
 699                            i, port->active, port->active_phys_tcs,
 700                            port->num_pbf_cmd_lines, port->num_btb_blocks,
 701                            port->reserved);
 702         }
 703
 704         /* vport table */
 705         for (i = 0; i < qm_info->num_vports; i++) {
 706                 vport = &qm_info->qm_vport_params[i];
 707                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 708                            "vport idx %d, vport_rl %d, wfq %d,"
 709                            " first_tx_pq_id [ ",
 710                            qm_info->start_vport + i, vport->vport_rl,
 711                            vport->vport_wfq);
 712                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 713                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
 714                                    vport->first_tx_pq_id[tc]);
 715                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
 716         }
 717
 718         /* pq table */
 719         for (i = 0; i < qm_info->num_pqs; i++) {
 720                 pq = &qm_info->qm_pq_params[i];
 721                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 722                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
 723                            " rl_valid %d\n",
 724                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
 725                            pq->wrr_group, pq->rl_valid);
 726         }
 727 }
 728
 729 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
 730 {
 731         /* reset params required for init run */
 732         ecore_init_qm_reset_params(p_hwfn);
 733
 734         /* init QM top level params */
 735         ecore_init_qm_params(p_hwfn);
 736
 737         /* init QM port params */
 738         ecore_init_qm_port_params(p_hwfn);
 739
 740         /* init QM vport params */
 741         ecore_init_qm_vport_params(p_hwfn);
 742
 743         /* init QM physical queue params */
 744         ecore_init_qm_pq_params(p_hwfn);
 745
 746         /* display all that init */
 747         ecore_dp_init_qm_params(p_hwfn);
 748 }
 749
 750 /* This function reconfigures the QM pf on the fly.
 751  * For this purpose we:
 752  * 1. reconfigure the QM database
 753  * 2. set new values to runtime array
 754  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 755  * 4. activate init tool in QM_PF stage
 756  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 757  */
 758 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 759                                      struct ecore_ptt *p_ptt)
 760 {
 761         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 762         enum _ecore_status_t rc;
 763         bool b_rc;
 764
 765         /* initialize ecore's qm data structure */
 766         ecore_init_qm_info(p_hwfn);
 767
 768         /* stop PF's qm queues */
 769         OSAL_SPIN_LOCK(&qm_lock);
 770         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 771                                       qm_info->start_pq, qm_info->num_pqs);
 772         OSAL_SPIN_UNLOCK(&qm_lock);
 773         if (!b_rc)
 774                 return ECORE_INVAL;
 775
 776         /* clear the QM_PF runtime phase leftovers from previous init */
 777         ecore_init_clear_rt_data(p_hwfn);
 778
 779         /* prepare QM portion of runtime array */
 780         ecore_qm_init_pf(p_hwfn);
 781
 782         /* activate init tool on runtime array */
 783         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 784                             p_hwfn->hw_info.hw_mode);
 785         if (rc != ECORE_SUCCESS)
 786                 return rc;
 787
 788         /* start PF's qm queues */
 789         OSAL_SPIN_LOCK(&qm_lock);
 790         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 791                                       qm_info->start_pq, qm_info->num_pqs);
 792         OSAL_SPIN_UNLOCK(&qm_lock);
 793         if (!b_rc)
 794                 return ECORE_INVAL;
 795
 796         return ECORE_SUCCESS;
 797 }
 798
 799 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
 800 {
 801         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 802         enum _ecore_status_t rc;
 803
 804         rc = ecore_init_qm_sanity(p_hwfn);
 805         if (rc != ECORE_SUCCESS)
 806                 goto alloc_err;
 807
 808         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 809                                             sizeof(struct init_qm_pq_params) *
 810                                             ecore_init_qm_get_num_pqs(p_hwfn));
 811         if (!qm_info->qm_pq_params)
 812                 goto alloc_err;
 813
 814         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 815                                        sizeof(struct init_qm_vport_params) *
 816                                        ecore_init_qm_get_num_vports(p_hwfn));
 817         if (!qm_info->qm_vport_params)
 818                 goto alloc_err;
 819
 820         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 821                                       sizeof(struct init_qm_port_params) *
 822                                       p_hwfn->p_dev->num_ports_in_engines);
 823         if (!qm_info->qm_port_params)
 824                 goto alloc_err;
 825
 826         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 827                                         sizeof(struct ecore_wfq_data) *
 828                                         ecore_init_qm_get_num_vports(p_hwfn));
 829         if (!qm_info->wfq_data)
 830                 goto alloc_err;
 831
 832         return ECORE_SUCCESS;
 833
 834 alloc_err:
 835         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 836         ecore_qm_info_free(p_hwfn);
 837         return ECORE_NOMEM;
 838 }
 839 /******************** End QM initialization ***************/
 840
 841 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 842 {
 843         enum _ecore_status_t rc = ECORE_SUCCESS;
 844         int i;
 845
 846         if (IS_VF(p_dev)) {
 847                 for_each_hwfn(p_dev, i) {
 848                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
 849                         if (rc != ECORE_SUCCESS)
 850                                 return rc;
 851                 }
 852                 return rc;
 853         }
 854
 855         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 856                                      sizeof(*p_dev->fw_data));
 857         if (!p_dev->fw_data)
 858                 return ECORE_NOMEM;
 859
 860         for_each_hwfn(p_dev, i) {
 861                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 862                 u32 n_eqes, num_cons;
 863
 864                 /* First allocate the context manager structure */
 865                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 866                 if (rc)
 867                         goto alloc_err;
 868
 869                 /* Set the HW cid/tid numbers (in the contest manager)
 870                  * Must be done prior to any further computations.
 871                  */
 872                 rc = ecore_cxt_set_pf_params(p_hwfn);
 873                 if (rc)
 874                         goto alloc_err;
 875
 876                 rc = ecore_alloc_qm_data(p_hwfn);
 877                 if (rc)
 878                         goto alloc_err;
 879
 880                 /* init qm info */
 881                 ecore_init_qm_info(p_hwfn);
 882
 883                 /* Compute the ILT client partition */
 884                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 885                 if (rc)
 886                         goto alloc_err;
 887
 888                 /* CID map / ILT shadow table / T2
 889                  * The talbes sizes are determined by the computations above
 890                  */
 891                 rc = ecore_cxt_tables_alloc(p_hwfn);
 892                 if (rc)
 893                         goto alloc_err;
 894
 895                 /* SPQ, must follow ILT because initializes SPQ context */
 896                 rc = ecore_spq_alloc(p_hwfn);
 897                 if (rc)
 898                         goto alloc_err;
 899
 900                 /* SP status block allocation */
 901                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 902                                                            RESERVED_PTT_DPC);
 903
 904                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 905                 if (rc)
 906                         goto alloc_err;
 907
 908                 rc = ecore_iov_alloc(p_hwfn);
 909                 if (rc)
 910                         goto alloc_err;
 911
 912                 /* EQ */
 913                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 914                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 915                         /* Calculate the EQ size
 916                          * ---------------------
 917                          * Each ICID may generate up to one event at a time i.e.
 918                          * the event must be handled/cleared before a new one
 919                          * can be generated. We calculate the sum of events per
 920                          * protocol and create an EQ deep enough to handle the
 921                          * worst case:
 922                          * - Core - according to SPQ.
 923                          * - RoCE - per QP there are a couple of ICIDs, one
 924                          *        responder and one requester, each can
 925                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
 926                          *        Each CQ can generate an EQE. There are 2 CQs
 927                          *        per QP => n_eqes_cq = 2 * n_qp.
 928                          *        Hence the RoCE total is 4 * n_qp or
 929                          *        2 * num_cons.
 930                          * - ENet - There can be up to two events per VF. One
 931                          *        for VF-PF channel and another for VF FLR
 932                          *        initial cleanup. The number of VFs is
 933                          *        bounded by MAX_NUM_VFS_BB, and is much
 934                          *        smaller than RoCE's so we avoid exact
 935                          *        calculation.
 936                          */
 937                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 938                                 num_cons =
 939                                     ecore_cxt_get_proto_cid_count(
 940                                                 p_hwfn,
 941                                                 PROTOCOLID_ROCE,
 942                                                 OSAL_NULL);
 943                                 num_cons *= 2;
 944                         } else {
 945                                 num_cons = ecore_cxt_get_proto_cid_count(
 946                                                 p_hwfn,
 947                                                 PROTOCOLID_IWARP,
 948                                                 OSAL_NULL);
 949                         }
 950                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 951                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 952                         num_cons =
 953                             ecore_cxt_get_proto_cid_count(p_hwfn,
 954                                                           PROTOCOLID_ISCSI,
 955                                                           OSAL_NULL);
 956                         n_eqes += 2 * num_cons;
 957                 }
 958
 959                 if (n_eqes > 0xFFFF) {
 960                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 961                                        "The maximum of a u16 chain is 0x%x\n",
 962                                n_eqes, 0xFFFF);
 963                         goto alloc_no_mem;
 964                 }
 965
 966                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 967                 if (rc)
 968                         goto alloc_err;
 969
 970                 rc = ecore_consq_alloc(p_hwfn);
 971                 if (rc)
 972                         goto alloc_err;
 973
 974                 rc = ecore_l2_alloc(p_hwfn);
 975                 if (rc != ECORE_SUCCESS)
 976                         goto alloc_err;
 977
 978                 /* DMA info initialization */
 979                 rc = ecore_dmae_info_alloc(p_hwfn);
 980                 if (rc) {
 981                         DP_NOTICE(p_hwfn, true,
 982                                   "Failed to allocate memory for dmae_info"
 983                                   " structure\n");
 984                         goto alloc_err;
 985                 }
 986
 987                 /* DCBX initialization */
 988                 rc = ecore_dcbx_info_alloc(p_hwfn);
 989                 if (rc) {
 990                         DP_NOTICE(p_hwfn, true,
 991                                   "Failed to allocate memory for dcbx structure\n");
 992                         goto alloc_err;
 993                 }
 994         }
 995
 996         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 997                                          sizeof(*p_dev->reset_stats));
 998         if (!p_dev->reset_stats) {
 999                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1000                 goto alloc_no_mem;
1001         }
1002
1003         return ECORE_SUCCESS;
1004
1005 alloc_no_mem:
1006         rc = ECORE_NOMEM;
1007 alloc_err:
1008         ecore_resc_free(p_dev);
1009         return rc;
1010 }
1011
1012 void ecore_resc_setup(struct ecore_dev *p_dev)
1013 {
1014         int i;
1015
1016         if (IS_VF(p_dev)) {
1017                 for_each_hwfn(p_dev, i)
1018                         ecore_l2_setup(&p_dev->hwfns[i]);
1019                 return;
1020         }
1021
1022         for_each_hwfn(p_dev, i) {
1023                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1024
1025                 ecore_cxt_mngr_setup(p_hwfn);
1026                 ecore_spq_setup(p_hwfn);
1027                 ecore_eq_setup(p_hwfn);
1028                 ecore_consq_setup(p_hwfn);
1029
1030                 /* Read shadow of current MFW mailbox */
1031                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1032                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1033                             p_hwfn->mcp_info->mfw_mb_cur,
1034                             p_hwfn->mcp_info->mfw_mb_length);
1035
1036                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1037
1038                 ecore_l2_setup(p_hwfn);
1039                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1040         }
1041 }
1042
1043 #define FINAL_CLEANUP_POLL_CNT  (100)
1044 #define FINAL_CLEANUP_POLL_TIME (10)
1045 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1046                                          struct ecore_ptt *p_ptt,
1047                                          u16 id, bool is_vf)
1048 {
1049         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1050         enum _ecore_status_t rc = ECORE_TIMEOUT;
1051
1052 #ifndef ASIC_ONLY
1053         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1054             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1055                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1056                 return ECORE_SUCCESS;
1057         }
1058 #endif
1059
1060         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1061             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1062
1063         if (is_vf)
1064                 id += 0x10;
1065
1066         command |= X_FINAL_CLEANUP_AGG_INT <<
1067             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1068         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1069         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1070         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1071
1072 /* Make sure notification is not set before initiating final cleanup */
1073
1074         if (REG_RD(p_hwfn, addr)) {
1075                 DP_NOTICE(p_hwfn, false,
1076                           "Unexpected; Found final cleanup notification");
1077                 DP_NOTICE(p_hwfn, false,
1078                           " before initiating final cleanup\n");
1079                 REG_WR(p_hwfn, addr, 0);
1080         }
1081
1082         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1083                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1084                    id, command);
1085
1086         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1087
1088         /* Poll until completion */
1089         while (!REG_RD(p_hwfn, addr) && count--)
1090                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1091
1092         if (REG_RD(p_hwfn, addr))
1093                 rc = ECORE_SUCCESS;
1094         else
1095                 DP_NOTICE(p_hwfn, true,
1096                           "Failed to receive FW final cleanup notification\n");
1097
1098         /* Cleanup afterwards */
1099         REG_WR(p_hwfn, addr, 0);
1100
1101         return rc;
1102 }
1103
1104 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1105 {
1106         int hw_mode = 0;
1107
1108         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1109                 hw_mode |= 1 << MODE_BB;
1110         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1111                 hw_mode |= 1 << MODE_K2;
1112         } else {
1113                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1114                           p_hwfn->p_dev->type);
1115                 return ECORE_INVAL;
1116         }
1117
1118         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1119         switch (p_hwfn->p_dev->num_ports_in_engines) {
1120         case 1:
1121                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1122                 break;
1123         case 2:
1124                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1125                 break;
1126         case 4:
1127                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1128                 break;
1129         default:
1130                 DP_NOTICE(p_hwfn, true,
1131                           "num_ports_in_engine = %d not supported\n",
1132                           p_hwfn->p_dev->num_ports_in_engines);
1133                 return ECORE_INVAL;
1134         }
1135
1136         switch (p_hwfn->p_dev->mf_mode) {
1137         case ECORE_MF_DEFAULT:
1138         case ECORE_MF_NPAR:
1139                 hw_mode |= 1 << MODE_MF_SI;
1140                 break;
1141         case ECORE_MF_OVLAN:
1142                 hw_mode |= 1 << MODE_MF_SD;
1143                 break;
1144         default:
1145                 DP_NOTICE(p_hwfn, true,
1146                           "Unsupported MF mode, init as DEFAULT\n");
1147                 hw_mode |= 1 << MODE_MF_SI;
1148         }
1149
1150 #ifndef ASIC_ONLY
1151         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1152                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1153                         hw_mode |= 1 << MODE_FPGA;
1154                 } else {
1155                         if (p_hwfn->p_dev->b_is_emul_full)
1156                                 hw_mode |= 1 << MODE_EMUL_FULL;
1157                         else
1158                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1159                 }
1160         } else
1161 #endif
1162                 hw_mode |= 1 << MODE_ASIC;
1163
1164         if (p_hwfn->p_dev->num_hwfns > 1)
1165                 hw_mode |= 1 << MODE_100G;
1166
1167         p_hwfn->hw_info.hw_mode = hw_mode;
1168
1169         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1170                    "Configuring function for hw_mode: 0x%08x\n",
1171                    p_hwfn->hw_info.hw_mode);
1172
1173         return ECORE_SUCCESS;
1174 }
1175
1176 #ifndef ASIC_ONLY
1177 /* MFW-replacement initializations for non-ASIC */
1178 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1179                                                struct ecore_ptt *p_ptt)
1180 {
1181         struct ecore_dev *p_dev = p_hwfn->p_dev;
1182         u32 pl_hv = 1;
1183         int i;
1184
1185         if (CHIP_REV_IS_EMUL(p_dev)) {
1186                 if (ECORE_IS_AH(p_dev))
1187                         pl_hv |= 0x600;
1188         }
1189
1190         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1191
1192         if (CHIP_REV_IS_EMUL(p_dev) &&
1193             (ECORE_IS_AH(p_dev)))
1194                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1195                          0x3ffffff);
1196
1197         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1198         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1199         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1200                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1201
1202         if (CHIP_REV_IS_EMUL(p_dev)) {
1203                 if (ECORE_IS_AH(p_dev)) {
1204                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1205                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1206                                  (p_dev->num_ports_in_engines >> 1));
1207
1208                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1209                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
1210                 }
1211         }
1212
1213         /* Poll on RBC */
1214         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1215         for (i = 0; i < 100; i++) {
1216                 OSAL_UDELAY(50);
1217                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1218                         break;
1219         }
1220         if (i == 100)
1221                 DP_NOTICE(p_hwfn, true,
1222                           "RBC done failed to complete in PSWRQ2\n");
1223
1224         return ECORE_SUCCESS;
1225 }
1226 #endif
1227
1228 /* Init run time data for all PFs and their VFs on an engine.
1229  * TBD - for VFs - Once we have parent PF info for each VF in
1230  * shmem available as CAU requires knowledge of parent PF for each VF.
1231  */
1232 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1233 {
1234         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1235         int i, sb_id;
1236
1237         for_each_hwfn(p_dev, i) {
1238                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1239                 struct ecore_igu_info *p_igu_info;
1240                 struct ecore_igu_block *p_block;
1241                 struct cau_sb_entry sb_entry;
1242
1243                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1244
1245                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1246                      sb_id++) {
1247                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1248
1249                         if (!p_block->is_pf)
1250                                 continue;
1251
1252                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1253                                                 p_block->function_id, 0, 0);
1254                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1255                 }
1256         }
1257 }
1258
1259 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1260                                                  struct ecore_ptt *p_ptt,
1261                                                  int hw_mode)
1262 {
1263         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1264         struct ecore_dev *p_dev = p_hwfn->p_dev;
1265         u8 vf_id, max_num_vfs;
1266         u16 num_pfs, pf_id;
1267         u32 concrete_fid;
1268         enum _ecore_status_t rc = ECORE_SUCCESS;
1269
1270         ecore_init_cau_rt_data(p_dev);
1271
1272         /* Program GTT windows */
1273         ecore_gtt_init(p_hwfn);
1274
1275 #ifndef ASIC_ONLY
1276         if (CHIP_REV_IS_EMUL(p_dev)) {
1277                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1278                 if (rc != ECORE_SUCCESS)
1279                         return rc;
1280         }
1281 #endif
1282
1283         if (p_hwfn->mcp_info) {
1284                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1285                         qm_info->pf_rl_en = 1;
1286                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1287                         qm_info->pf_wfq_en = 1;
1288         }
1289
1290         ecore_qm_common_rt_init(p_hwfn,
1291                                 p_dev->num_ports_in_engines,
1292                                 qm_info->max_phys_tcs_per_port,
1293                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1294                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1295                                 qm_info->qm_port_params);
1296
1297         ecore_cxt_hw_init_common(p_hwfn);
1298
1299         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1300         if (rc != ECORE_SUCCESS)
1301                 return rc;
1302
1303         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1304          * need to decide with which value, maybe runtime
1305          */
1306         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1307         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1308
1309         if (ECORE_IS_BB(p_dev)) {
1310                 /* Workaround clears ROCE search for all functions to prevent
1311                  * involving non initialized function in processing ROCE packet.
1312                  */
1313                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1314                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1315                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1316                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1317                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1318                 }
1319                 /* pretend to original PF */
1320                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1321         }
1322
1323         /* Workaround for avoiding CCFC execution error when getting packets
1324          * with CRC errors, and allowing instead the invoking of the FW error
1325          * handler.
1326          * This is not done inside the init tool since it currently can't
1327          * perform a pretending to VFs.
1328          */
1329         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1330         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1331                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1332                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1333                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1334                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1335                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1336                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1337         }
1338         /* pretend to original PF */
1339         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1340
1341         return rc;
1342 }
1343
1344 #ifndef ASIC_ONLY
1345 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1346 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1347
1348 #define PMEG_IF_BYTE_COUNT      8
1349
1350 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1351                              struct ecore_ptt *p_ptt,
1352                              u32 addr, u64 data, u8 reg_type, u8 port)
1353 {
1354         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1355                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1356                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1357                    (8 << PMEG_IF_BYTE_COUNT),
1358                    (reg_type << 25) | (addr << 8) | port,
1359                    (u32)((data >> 32) & 0xffffffff),
1360                    (u32)(data & 0xffffffff));
1361
1362         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1363                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1364                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1365         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1366                  (reg_type << 25) | (addr << 8) | port);
1367         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1368         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1369                  (data >> 32) & 0xffffffff);
1370 }
1371
1372 #define XLPORT_MODE_REG (0x20a)
1373 #define XLPORT_MAC_CONTROL (0x210)
1374 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1375 #define XLPORT_ENABLE_REG (0x20b)
1376
1377 #define XLMAC_CTRL (0x600)
1378 #define XLMAC_MODE (0x601)
1379 #define XLMAC_RX_MAX_SIZE (0x608)
1380 #define XLMAC_TX_CTRL (0x604)
1381 #define XLMAC_PAUSE_CTRL (0x60d)
1382 #define XLMAC_PFC_CTRL (0x60e)
1383
1384 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1385                                     struct ecore_ptt *p_ptt)
1386 {
1387         u8 loopback = 0, port = p_hwfn->port_id * 2;
1388
1389         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1390
1391         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1392         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1393                          port);
1394         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1395         /* XLMAC: SOFT RESET */
1396         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1397         /* XLMAC: Port Speed >= 10Gbps */
1398         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1399         /* XLMAC: Max Size */
1400         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1401         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1402                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1403                          0, port);
1404         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1405         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1406                          0x30ffffc000ULL, 0, port);
1407         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1408                          port); /* XLMAC: TX_EN, RX_EN */
1409         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1410         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1411                          0x1003 | (loopback << 2), 0, port);
1412         /* Enabled Parallel PFC interface */
1413         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1414
1415         /* XLPORT port enable */
1416         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1417 }
1418
1419 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1420                                        struct ecore_ptt *p_ptt)
1421 {
1422         u8 port = p_hwfn->port_id;
1423         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1424
1425         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1426
1427         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1428                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1429                  (port <<
1430                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1431                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1432
1433         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1434                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1435
1436         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1437                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1438
1439         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1440                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1441
1442         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1443                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1444
1445         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1446                  (0xA <<
1447                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1448                  (8 <<
1449                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1450
1451         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1452                  0xa853);
1453 }
1454
1455 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1456                                  struct ecore_ptt *p_ptt)
1457 {
1458         if (ECORE_IS_AH(p_hwfn->p_dev))
1459                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1460         else /* BB */
1461                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1462 }
1463
1464 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1465                                struct ecore_ptt *p_ptt,  u8 port)
1466 {
1467         int port_offset = port ? 0x800 : 0;
1468         u32 xmac_rxctrl = 0;
1469
1470         /* Reset of XMAC */
1471         /* FIXME: move to common start */
1472         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1473                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1474         OSAL_MSLEEP(1);
1475         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1476                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1477
1478         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1479
1480         /* Set the number of ports on the Warp Core to 10G */
1481         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1482
1483         /* Soft reset of XMAC */
1484         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1485                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1486         OSAL_MSLEEP(1);
1487         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1488                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1489
1490         /* FIXME: move to common end */
1491         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1492                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1493
1494         /* Set Max packet size: initialize XMAC block register for port 0 */
1495         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1496
1497         /* CRC append for Tx packets: init XMAC block register for port 1 */
1498         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1499
1500         /* Enable TX and RX: initialize XMAC block register for port 1 */
1501         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1502                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1503         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1504                                XMAC_REG_RX_CTRL_BB + port_offset);
1505         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1506         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1507 }
1508 #endif
1509
1510 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1511                                                struct ecore_ptt *p_ptt,
1512                                                int hw_mode)
1513 {
1514         enum _ecore_status_t rc = ECORE_SUCCESS;
1515
1516         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1517                             hw_mode);
1518         if (rc != ECORE_SUCCESS)
1519                 return rc;
1520 #ifndef ASIC_ONLY
1521         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1522                 return ECORE_SUCCESS;
1523
1524         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1525                 if (ECORE_IS_AH(p_hwfn->p_dev))
1526                         return ECORE_SUCCESS;
1527                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1528                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1529         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1530                 if (p_hwfn->p_dev->num_hwfns > 1) {
1531                         /* Activate OPTE in CMT */
1532                         u32 val;
1533
1534                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1535                         val |= 0x10;
1536                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1537                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1538                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1539                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1540                         ecore_wr(p_hwfn, p_ptt,
1541                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1542                         ecore_wr(p_hwfn, p_ptt,
1543                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1544                         ecore_wr(p_hwfn, p_ptt,
1545                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1546                                  0x55555555);
1547                 }
1548
1549                 ecore_emul_link_init(p_hwfn, p_ptt);
1550         } else {
1551                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1552         }
1553 #endif
1554
1555         return rc;
1556 }
1557
1558 static enum _ecore_status_t
1559 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1560                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1561 {
1562         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1563         u32 dpi_bit_shift, dpi_count;
1564         u32 min_dpis;
1565
1566         /* Calculate DPI size
1567          * ------------------
1568          * The PWM region contains Doorbell Pages. The first is reserverd for
1569          * the kernel for, e.g, L2. The others are free to be used by non-
1570          * trusted applications, typically from user space. Each page, called a
1571          * doorbell page is sectioned into windows that allow doorbells to be
1572          * issued in parallel by the kernel/application. The size of such a
1573          * window (a.k.a. WID) is 1kB.
1574          * Summary:
1575          *    1kB WID x N WIDS = DPI page size
1576          *    DPI page size x N DPIs = PWM region size
1577          * Notes:
1578          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1579          * in order to ensure that two applications won't share the same page.
1580          * It also must contain at least one WID per CPU to allow parallelism.
1581          * It also must be a power of 2, since it is stored as a bit shift.
1582          *
1583          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1584          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1585          * containing 4 WIDs.
1586          */
1587         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1588         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1589         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1590         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1591         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1592
1593         dpi_count = pwm_region_size / dpi_page_size;
1594
1595         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1596         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1597
1598         /* Update hwfn */
1599         p_hwfn->dpi_size = dpi_page_size;
1600         p_hwfn->dpi_count = dpi_count;
1601
1602         /* Update registers */
1603         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1604
1605         if (dpi_count < min_dpis)
1606                 return ECORE_NORESOURCES;
1607
1608         return ECORE_SUCCESS;
1609 }
1610
1611 enum ECORE_ROCE_EDPM_MODE {
1612         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1613         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1614         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1615 };
1616
1617 static enum _ecore_status_t
1618 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1619                               struct ecore_ptt *p_ptt)
1620 {
1621         u32 pwm_regsize, norm_regsize;
1622         u32 non_pwm_conn, min_addr_reg1;
1623         u32 db_bar_size, n_cpus;
1624         u32 roce_edpm_mode;
1625         u32 pf_dems_shift;
1626         int rc = ECORE_SUCCESS;
1627         u8 cond;
1628
1629         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1630         if (p_hwfn->p_dev->num_hwfns > 1)
1631                 db_bar_size /= 2;
1632
1633         /* Calculate doorbell regions
1634          * -----------------------------------
1635          * The doorbell BAR is made of two regions. The first is called normal
1636          * region and the second is called PWM region. In the normal region
1637          * each ICID has its own set of addresses so that writing to that
1638          * specific address identifies the ICID. In the Process Window Mode
1639          * region the ICID is given in the data written to the doorbell. The
1640          * above per PF register denotes the offset in the doorbell BAR in which
1641          * the PWM region begins.
1642          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1643          * non-PWM connection. The calculation below computes the total non-PWM
1644          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1645          * in units of 4,096 bytes.
1646          */
1647         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1648             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1649                                           OSAL_NULL) +
1650             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1651         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1652         min_addr_reg1 = norm_regsize / 4096;
1653         pwm_regsize = db_bar_size - norm_regsize;
1654
1655         /* Check that the normal and PWM sizes are valid */
1656         if (db_bar_size < norm_regsize) {
1657                 DP_ERR(p_hwfn->p_dev,
1658                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1659                        db_bar_size, norm_regsize);
1660                 return ECORE_NORESOURCES;
1661         }
1662         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1663                 DP_ERR(p_hwfn->p_dev,
1664                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1665                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1666                        norm_regsize);
1667                 return ECORE_NORESOURCES;
1668         }
1669
1670         /* Calculate number of DPIs */
1671         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1672         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1673             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1674                 /* Either EDPM is mandatory, or we are attempting to allocate a
1675                  * WID per CPU.
1676                  */
1677                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1678                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1679         }
1680
1681         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1682             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1683         if (cond || p_hwfn->dcbx_no_edpm) {
1684                 /* Either EDPM is disabled from user configuration, or it is
1685                  * disabled via DCBx, or it is not mandatory and we failed to
1686                  * allocated a WID per CPU.
1687                  */
1688                 n_cpus = 1;
1689                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1690
1691                 /* If we entered this flow due to DCBX then the DPM register is
1692                  * already configured.
1693                  */
1694         }
1695
1696         DP_INFO(p_hwfn,
1697                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1698                 norm_regsize, pwm_regsize);
1699         DP_INFO(p_hwfn,
1700                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1701                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1702                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1703                 "disabled" : "enabled");
1704
1705         /* Check return codes from above calls */
1706         if (rc) {
1707                 DP_ERR(p_hwfn,
1708                        "Failed to allocate enough DPIs\n");
1709                 return ECORE_NORESOURCES;
1710         }
1711
1712         /* Update hwfn */
1713         p_hwfn->dpi_start_offset = norm_regsize;
1714
1715         /* Update registers */
1716         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1717         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1718         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1719         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1720
1721         return ECORE_SUCCESS;
1722 }
1723
1724 static enum _ecore_status_t
1725 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1726                  struct ecore_ptt *p_ptt,
1727                  struct ecore_tunnel_info *p_tunn,
1728                  int hw_mode,
1729                  bool b_hw_start,
1730                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1731 {
1732         u8 rel_pf_id = p_hwfn->rel_pf_id;
1733         u32 prs_reg;
1734         enum _ecore_status_t rc = ECORE_SUCCESS;
1735         u16 ctrl;
1736         int pos;
1737
1738         if (p_hwfn->mcp_info) {
1739                 struct ecore_mcp_function_info *p_info;
1740
1741                 p_info = &p_hwfn->mcp_info->func_info;
1742                 if (p_info->bandwidth_min)
1743                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1744
1745                 /* Update rate limit once we'll actually have a link */
1746                 p_hwfn->qm_info.pf_rl = 100000;
1747         }
1748         ecore_cxt_hw_init_pf(p_hwfn);
1749
1750         ecore_int_igu_init_rt(p_hwfn);
1751
1752         /* Set VLAN in NIG if needed */
1753         if (hw_mode & (1 << MODE_MF_SD)) {
1754                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1755                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1756                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1757                              p_hwfn->hw_info.ovlan);
1758         }
1759
1760         /* Enable classification by MAC if needed */
1761         if (hw_mode & (1 << MODE_MF_SI)) {
1762                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1763                            "Configuring TAGMAC_CLS_TYPE\n");
1764                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1765                              1);
1766         }
1767
1768         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1769         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1770                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1771         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1772                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1773         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1774
1775         /* perform debug configuration when chip is out of reset */
1776         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1777
1778         /* Cleanup chip from previous driver if such remains exist */
1779         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1780         if (rc != ECORE_SUCCESS) {
1781                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1782                 return rc;
1783         }
1784
1785         /* PF Init sequence */
1786         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1787         if (rc)
1788                 return rc;
1789
1790         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1791         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1792         if (rc)
1793                 return rc;
1794
1795         /* Pure runtime initializations - directly to the HW  */
1796         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1797
1798         /* PCI relaxed ordering causes a decrease in the performance on some
1799          * systems. Till a root cause is found, disable this attribute in the
1800          * PCI config space.
1801          */
1802         /* Not in use @DPDK
1803         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1804         * if (!pos) {
1805         *       DP_NOTICE(p_hwfn, true,
1806         *                 "Failed to find the PCIe Cap\n");
1807         *       return ECORE_IO;
1808         * }
1809         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1810         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1811         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1812         */
1813
1814         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1815         if (rc)
1816                 return rc;
1817         if (b_hw_start) {
1818                 /* enable interrupts */
1819                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1820                 if (rc != ECORE_SUCCESS)
1821                         return rc;
1822
1823                 /* send function start command */
1824                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1825                                        allow_npar_tx_switch);
1826                 if (rc) {
1827                         DP_NOTICE(p_hwfn, true,
1828                                   "Function start ramrod failed\n");
1829                 } else {
1830                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1831                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1832                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1833
1834                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1835                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1836                                          (1 << 2));
1837                                 ecore_wr(p_hwfn, p_ptt,
1838                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1839                                     0x100);
1840                         }
1841                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1842                                    "PRS_REG_SEARCH registers after start PFn\n");
1843                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1844                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1845                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1846                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1847                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1848                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1849                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1850                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1851                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1852                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1853                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1854                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1855                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1856                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1857                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1858                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1859                                    prs_reg);
1860                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1861                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1862                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1863                 }
1864         }
1865         return rc;
1866 }
1867
1868 static enum _ecore_status_t
1869 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1870                       struct ecore_ptt *p_ptt, u8 enable)
1871 {
1872         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1873
1874         /* Change PF in PXP */
1875         ecore_wr(p_hwfn, p_ptt,
1876                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1877
1878         /* wait until value is set - try for 1 second every 50us */
1879         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1880                 val = ecore_rd(p_hwfn, p_ptt,
1881                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1882                 if (val == set_val)
1883                         break;
1884
1885                 OSAL_UDELAY(50);
1886         }
1887
1888         if (val != set_val) {
1889                 DP_NOTICE(p_hwfn, true,
1890                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1891                 return ECORE_UNKNOWN_ERROR;
1892         }
1893
1894         return ECORE_SUCCESS;
1895 }
1896
1897 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1898                                   struct ecore_ptt *p_main_ptt)
1899 {
1900         /* Read shadow of current MFW mailbox */
1901         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1902         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1903                     p_hwfn->mcp_info->mfw_mb_cur,
1904                     p_hwfn->mcp_info->mfw_mb_length);
1905 }
1906
1907 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1908                                     struct ecore_hw_init_params *p_params)
1909 {
1910         if (p_params->p_tunn) {
1911                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1912                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1913         }
1914
1915         p_hwfn->b_int_enabled = 1;
1916
1917         return ECORE_SUCCESS;
1918 }
1919
1920 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1921                                    struct ecore_hw_init_params *p_params)
1922 {
1923         struct ecore_load_req_params load_req_params;
1924         u32 load_code, param, drv_mb_param;
1925         struct ecore_hwfn *p_hwfn;
1926         bool b_default_mtu = true;
1927         enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1928         int i;
1929
1930         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1931             (p_dev->num_hwfns > 1)) {
1932                 DP_NOTICE(p_dev, false,
1933                           "MSI mode is not supported for CMT devices\n");
1934                 return ECORE_INVAL;
1935         }
1936
1937         if (IS_PF(p_dev)) {
1938                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1939                 if (rc != ECORE_SUCCESS)
1940                         return rc;
1941         }
1942
1943         for_each_hwfn(p_dev, i) {
1944                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1945
1946                 /* If management didn't provide a default, set one of our own */
1947                 if (!p_hwfn->hw_info.mtu) {
1948                         p_hwfn->hw_info.mtu = 1500;
1949                         b_default_mtu = false;
1950                 }
1951
1952                 if (IS_VF(p_dev)) {
1953                         ecore_vf_start(p_hwfn, p_params);
1954                         continue;
1955                 }
1956
1957                 /* Enable DMAE in PXP */
1958                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1959                 if (rc != ECORE_SUCCESS)
1960                         return rc;
1961
1962                 rc = ecore_calc_hw_mode(p_hwfn);
1963                 if (rc != ECORE_SUCCESS)
1964                         return rc;
1965
1966                 OSAL_MEM_ZERO(&load_req_params, sizeof(load_req_params));
1967                 load_req_params.drv_role = p_params->is_crash_kernel ?
1968                                            ECORE_DRV_ROLE_KDUMP :
1969                                            ECORE_DRV_ROLE_OS;
1970                 load_req_params.timeout_val = p_params->mfw_timeout_val;
1971                 load_req_params.avoid_eng_reset = p_params->avoid_eng_reset;
1972                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1973                                         &load_req_params);
1974                 if (rc != ECORE_SUCCESS) {
1975                         DP_NOTICE(p_hwfn, true,
1976                                   "Failed sending a LOAD_REQ command\n");
1977                         return rc;
1978                 }
1979
1980                 load_code = load_req_params.load_code;
1981                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1982                            "Load request was sent. Load code: 0x%x\n",
1983                            load_code);
1984
1985                 /* CQ75580:
1986                  * When coming back from hiberbate state, the registers from
1987                  * which shadow is read initially are not initialized. It turns
1988                  * out that these registers get initialized during the call to
1989                  * ecore_mcp_load_req request. So we need to reread them here
1990                  * to get the proper shadow register value.
1991                  * Note: This is a workaround for the missing MFW
1992                  * initialization. It may be removed once the implementation
1993                  * is done.
1994                  */
1995                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1996
1997                 /* Only relevant for recovery:
1998                  * Clear the indication after the LOAD_REQ command is responded
1999                  * by the MFW.
2000                  */
2001                 p_dev->recov_in_prog = false;
2002
2003                 p_hwfn->first_on_engine = (load_code ==
2004                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2005
2006                 if (!qm_lock_init) {
2007                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2008                         qm_lock_init = true;
2009                 }
2010
2011                 switch (load_code) {
2012                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2013                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2014                                                   p_hwfn->hw_info.hw_mode);
2015                         if (rc != ECORE_SUCCESS)
2016                                 break;
2017                         /* Fall into */
2018                 case FW_MSG_CODE_DRV_LOAD_PORT:
2019                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2020                                                 p_hwfn->hw_info.hw_mode);
2021                         if (rc != ECORE_SUCCESS)
2022                                 break;
2023                         /* Fall into */
2024                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2025                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2026                                               p_params->p_tunn,
2027                                               p_hwfn->hw_info.hw_mode,
2028                                               p_params->b_hw_start,
2029                                               p_params->int_mode,
2030                                               p_params->allow_npar_tx_switch);
2031                         break;
2032                 default:
2033                         DP_NOTICE(p_hwfn, false,
2034                                   "Unexpected load code [0x%08x]", load_code);
2035                         rc = ECORE_NOTIMPL;
2036                         break;
2037                 }
2038
2039                 if (rc != ECORE_SUCCESS)
2040                         DP_NOTICE(p_hwfn, true,
2041                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2042                                   load_code, rc);
2043
2044                 /* ACK mfw regardless of success or failure of initialization */
2045                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2046                                        DRV_MSG_CODE_LOAD_DONE,
2047                                        0, &load_code, &param);
2048                 if (rc != ECORE_SUCCESS)
2049                         return rc;
2050
2051                 if (mfw_rc != ECORE_SUCCESS) {
2052                         DP_NOTICE(p_hwfn, true,
2053                                   "Failed sending LOAD_DONE command\n");
2054                         return mfw_rc;
2055                 }
2056
2057                 /* send DCBX attention request command */
2058                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2059                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2060                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2061                                        DRV_MSG_CODE_SET_DCBX,
2062                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2063                                        &load_code, &param);
2064                 if (mfw_rc != ECORE_SUCCESS) {
2065                         DP_NOTICE(p_hwfn, true,
2066                                   "Failed to send DCBX attention request\n");
2067                         return mfw_rc;
2068                 }
2069
2070                 p_hwfn->hw_init_done = true;
2071         }
2072
2073         if (IS_PF(p_dev)) {
2074                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2075                 drv_mb_param = STORM_FW_VERSION;
2076                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2077                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2078                                    drv_mb_param, &load_code, &param);
2079                 if (rc != ECORE_SUCCESS)
2080                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2081
2082                 if (!b_default_mtu)
2083                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2084                                                       p_hwfn->hw_info.mtu);
2085                 if (rc != ECORE_SUCCESS)
2086                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2087
2088                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2089                                                       p_hwfn->p_main_ptt,
2090                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2091                 if (rc != ECORE_SUCCESS)
2092                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2093         }
2094
2095         return rc;
2096 }
2097
2098 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2099 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2100                                  struct ecore_hwfn *p_hwfn,
2101                                  struct ecore_ptt *p_ptt)
2102 {
2103         int i;
2104
2105         /* close timers */
2106         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2107         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2108         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2109                                                                         i++) {
2110                 if ((!ecore_rd(p_hwfn, p_ptt,
2111                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2112                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2113                         break;
2114
2115                 /* Dependent on number of connection/tasks, possibly
2116                  * 1ms sleep is required between polls
2117                  */
2118                 OSAL_MSLEEP(1);
2119         }
2120
2121         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2122                 return;
2123
2124         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2125                   " [Connection %02x Tasks %02x]\n",
2126                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2127                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2128 }
2129
2130 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2131 {
2132         int j;
2133
2134         for_each_hwfn(p_dev, j) {
2135                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2136                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2137
2138                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2139         }
2140 }
2141
2142 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2143 {
2144         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
2145         int j;
2146
2147         for_each_hwfn(p_dev, j) {
2148                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2149                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2150
2151                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2152
2153                 if (IS_VF(p_dev)) {
2154                         ecore_vf_pf_int_cleanup(p_hwfn);
2155                         continue;
2156                 }
2157
2158                 /* mark the hw as uninitialized... */
2159                 p_hwfn->hw_init_done = false;
2160
2161                 rc = ecore_sp_pf_stop(p_hwfn);
2162                 if (rc)
2163                         DP_NOTICE(p_hwfn, true,
2164                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
2165
2166                 /* perform debug action after PF stop was sent */
2167                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
2168
2169                 /* close NIG to BRB gate */
2170                 ecore_wr(p_hwfn, p_ptt,
2171                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2172
2173                 /* close parser */
2174                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2175                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2176                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2177                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2178                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2179
2180                 /* @@@TBD - clean transmission queues (5.b) */
2181                 /* @@@TBD - clean BTB (5.c) */
2182
2183                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2184
2185                 /* @@@TBD - verify DMAE requests are done (8) */
2186
2187                 /* Disable Attention Generation */
2188                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2189                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2190                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2191                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2192                 /* Need to wait 1ms to guarantee SBs are cleared */
2193                 OSAL_MSLEEP(1);
2194         }
2195
2196         if (IS_PF(p_dev)) {
2197                 /* Disable DMAE in PXP - in CMT, this should only be done for
2198                  * first hw-function, and only after all transactions have
2199                  * stopped for all active hw-functions.
2200                  */
2201                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
2202                                              p_dev->hwfns[0].p_main_ptt, false);
2203                 if (t_rc != ECORE_SUCCESS)
2204                         rc = t_rc;
2205         }
2206
2207         return rc;
2208 }
2209
2210 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2211 {
2212         int j;
2213
2214         for_each_hwfn(p_dev, j) {
2215                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2216                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2217
2218                 if (IS_VF(p_dev)) {
2219                         ecore_vf_pf_int_cleanup(p_hwfn);
2220                         continue;
2221                 }
2222
2223                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2224                            "Shutting down the fastpath\n");
2225
2226                 ecore_wr(p_hwfn, p_ptt,
2227                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2228
2229                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2230                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2231                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2232                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2233                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2234
2235                 /* @@@TBD - clean transmission queues (5.b) */
2236                 /* @@@TBD - clean BTB (5.c) */
2237
2238                 /* @@@TBD - verify DMAE requests are done (8) */
2239
2240                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2241                 /* Need to wait 1ms to guarantee SBs are cleared */
2242                 OSAL_MSLEEP(1);
2243         }
2244 }
2245
2246 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2247 {
2248         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2249
2250         if (IS_VF(p_hwfn->p_dev))
2251                 return;
2252
2253         /* If roce info is allocated it means roce is initialized and should
2254          * be enabled in searcher.
2255          */
2256         if (p_hwfn->p_rdma_info) {
2257                 if (p_hwfn->b_rdma_enabled_in_prs)
2258                         ecore_wr(p_hwfn, p_ptt,
2259                                  p_hwfn->rdma_prs_search_reg, 0x1);
2260                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2261         }
2262
2263         /* Re-open incoming traffic */
2264         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2265                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2266 }
2267
2268 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
2269                                              struct ecore_ptt *p_ptt, u32 reg,
2270                                              bool expected)
2271 {
2272         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
2273
2274         if (assert_val != expected) {
2275                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
2276                           reg, expected);
2277                 return ECORE_UNKNOWN_ERROR;
2278         }
2279
2280         return 0;
2281 }
2282
2283 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
2284 {
2285         enum _ecore_status_t rc = ECORE_SUCCESS;
2286         u32 unload_resp, unload_param;
2287         int i;
2288
2289         for_each_hwfn(p_dev, i) {
2290                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2291
2292                 if (IS_VF(p_dev)) {
2293                         rc = ecore_vf_pf_reset(p_hwfn);
2294                         if (rc)
2295                                 return rc;
2296                         continue;
2297                 }
2298
2299                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
2300
2301                 /* Check for incorrect states */
2302                 if (!p_dev->recov_in_prog) {
2303                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2304                                          QM_REG_USG_CNT_PF_TX, 0);
2305                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2306                                          QM_REG_USG_CNT_PF_OTHER, 0);
2307                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2308                 }
2309
2310                 /* Disable PF in HW blocks */
2311                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2312                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2313
2314                 if (p_dev->recov_in_prog) {
2315                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2316                                    "Recovery is in progress -> skip sending unload_req/done\n");
2317                         break;
2318                 }
2319
2320                 /* Send unload command to MCP */
2321                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2322                                    DRV_MSG_CODE_UNLOAD_REQ,
2323                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
2324                                    &unload_resp, &unload_param);
2325                 if (rc != ECORE_SUCCESS) {
2326                         DP_NOTICE(p_hwfn, true,
2327                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
2328                         /* @@TBD - what to do? for now, assume ENG. */
2329                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2330                 }
2331
2332                 rc = ecore_mcp_unload_done(p_hwfn, p_hwfn->p_main_ptt);
2333                 if (rc != ECORE_SUCCESS) {
2334                         DP_NOTICE(p_hwfn,
2335                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2336                         /* @@@TBD - Should it really ASSERT here ? */
2337                         return rc;
2338                 }
2339         }
2340
2341         return rc;
2342 }
2343
2344 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2345 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2346 {
2347         ecore_ptt_pool_free(p_hwfn);
2348         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2349 }
2350
2351 /* Setup bar access */
2352 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2353 {
2354         /* clear indirect access */
2355         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2356                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2357                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2358                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2359                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2360                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2361                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2362                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2363                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2364         } else {
2365                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2366                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2367                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2368                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2369                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2370                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2371                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2372                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2373         }
2374
2375         /* Clean Previous errors if such exist */
2376         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2377                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2378
2379         /* enable internal target-read */
2380         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2381                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2382 }
2383
2384 static void get_function_id(struct ecore_hwfn *p_hwfn)
2385 {
2386         /* ME Register */
2387         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2388                                                   PXP_PF_ME_OPAQUE_ADDR);
2389
2390         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2391
2392         /* Bits 16-19 from the ME registers are the pf_num */
2393         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2394         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2395                                       PXP_CONCRETE_FID_PFID);
2396         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2397                                     PXP_CONCRETE_FID_PORT);
2398
2399         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2400                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2401                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2402 }
2403
2404 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2405 {
2406         u32 *feat_num = p_hwfn->hw_info.feat_num;
2407         struct ecore_sb_cnt_info sb_cnt_info;
2408         int num_features = 1;
2409
2410         /* L2 Queues require each: 1 status block. 1 L2 queue */
2411         feat_num[ECORE_PF_L2_QUE] =
2412             OSAL_MIN_T(u32,
2413                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2414                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2415
2416         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2417         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2418         feat_num[ECORE_VF_L2_QUE] =
2419                 OSAL_MIN_T(u32,
2420                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2421                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2422                            sb_cnt_info.sb_iov_cnt);
2423
2424         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2425                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2426         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2427                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2428
2429         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2430                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2431                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2432                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2433                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2434                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2435                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2436                    RESC_NUM(p_hwfn, ECORE_SB));
2437 }
2438
2439 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2440 {
2441         switch (res_id) {
2442         case ECORE_SB:
2443                 return "SB";
2444         case ECORE_L2_QUEUE:
2445                 return "L2_QUEUE";
2446         case ECORE_VPORT:
2447                 return "VPORT";
2448         case ECORE_RSS_ENG:
2449                 return "RSS_ENG";
2450         case ECORE_PQ:
2451                 return "PQ";
2452         case ECORE_RL:
2453                 return "RL";
2454         case ECORE_MAC:
2455                 return "MAC";
2456         case ECORE_VLAN:
2457                 return "VLAN";
2458         case ECORE_RDMA_CNQ_RAM:
2459                 return "RDMA_CNQ_RAM";
2460         case ECORE_ILT:
2461                 return "ILT";
2462         case ECORE_LL2_QUEUE:
2463                 return "LL2_QUEUE";
2464         case ECORE_CMDQS_CQS:
2465                 return "CMDQS_CQS";
2466         case ECORE_RDMA_STATS_QUEUE:
2467                 return "RDMA_STATS_QUEUE";
2468         case ECORE_BDQ:
2469                 return "BDQ";
2470         default:
2471                 return "UNKNOWN_RESOURCE";
2472         }
2473 }
2474
2475 static enum _ecore_status_t
2476 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2477                               enum ecore_resources res_id, u32 resc_max_val,
2478                               u32 *p_mcp_resp)
2479 {
2480         enum _ecore_status_t rc;
2481
2482         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_hwfn->p_main_ptt, res_id,
2483                                         resc_max_val, p_mcp_resp);
2484         if (rc != ECORE_SUCCESS) {
2485                 DP_NOTICE(p_hwfn, true,
2486                           "MFW response failure for a max value setting of resource %d [%s]\n",
2487                           res_id, ecore_hw_get_resc_name(res_id));
2488                 return rc;
2489         }
2490
2491         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2492                 DP_INFO(p_hwfn,
2493                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2494                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2495
2496         return ECORE_SUCCESS;
2497 }
2498
2499 static enum _ecore_status_t
2500 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn)
2501 {
2502         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2503         u32 resc_max_val, mcp_resp;
2504         u8 res_id;
2505         enum _ecore_status_t rc;
2506
2507         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2508                 /* @DPDK */
2509                 switch (res_id) {
2510                 case ECORE_LL2_QUEUE:
2511                 case ECORE_RDMA_CNQ_RAM:
2512                 case ECORE_RDMA_STATS_QUEUE:
2513                 case ECORE_BDQ:
2514                         resc_max_val = 0;
2515                         break;
2516                 default:
2517                         continue;
2518                 }
2519
2520                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, res_id,
2521                                                    resc_max_val, &mcp_resp);
2522                 if (rc != ECORE_SUCCESS)
2523                         return rc;
2524
2525                 /* There's no point to continue to the next resource if the
2526                  * command is not supported by the MFW.
2527                  * We do continue if the command is supported but the resource
2528                  * is unknown to the MFW. Such a resource will be later
2529                  * configured with the default allocation values.
2530                  */
2531                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2532                         return ECORE_NOTIMPL;
2533         }
2534
2535         return ECORE_SUCCESS;
2536 }
2537
2538 static
2539 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2540                                             enum ecore_resources res_id,
2541                                             u32 *p_resc_num, u32 *p_resc_start)
2542 {
2543         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2544         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2545         struct ecore_sb_cnt_info sb_cnt_info;
2546
2547         switch (res_id) {
2548         case ECORE_SB:
2549                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2550                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2551                 *p_resc_num = sb_cnt_info.sb_cnt;
2552                 break;
2553         case ECORE_L2_QUEUE:
2554                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2555                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2556                 break;
2557         case ECORE_VPORT:
2558                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2559                                  MAX_NUM_VPORTS_BB) / num_funcs;
2560                 break;
2561         case ECORE_RSS_ENG:
2562                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2563                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2564                 break;
2565         case ECORE_PQ:
2566                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2567                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2568                 break;
2569         case ECORE_RL:
2570                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2571                 break;
2572         case ECORE_MAC:
2573         case ECORE_VLAN:
2574                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2575                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2576                 break;
2577         case ECORE_ILT:
2578                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2579                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2580                 break;
2581         case ECORE_LL2_QUEUE:
2582                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2583                 break;
2584         case ECORE_RDMA_CNQ_RAM:
2585         case ECORE_CMDQS_CQS:
2586                 /* CNQ/CMDQS are the same resource */
2587                 /* @DPDK */
2588                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2589                 break;
2590         case ECORE_RDMA_STATS_QUEUE:
2591                 /* @DPDK */
2592                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2593                                  MAX_NUM_VPORTS_BB) / num_funcs;
2594                 break;
2595         case ECORE_BDQ:
2596                 /* @DPDK */
2597                 *p_resc_num = 0;
2598                 break;
2599         default:
2600                 break;
2601         }
2602
2603
2604         switch (res_id) {
2605         case ECORE_BDQ:
2606                 if (!*p_resc_num)
2607                         *p_resc_start = 0;
2608                 break;
2609         default:
2610                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2611                 break;
2612         }
2613
2614         return ECORE_SUCCESS;
2615 }
2616
2617 static enum _ecore_status_t
2618 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
2619                          bool drv_resc_alloc)
2620 {
2621         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2622         u32 mcp_resp, *p_resc_num, *p_resc_start;
2623         enum _ecore_status_t rc;
2624
2625         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2626         p_resc_start = &RESC_START(p_hwfn, res_id);
2627
2628         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2629                                     &dflt_resc_start);
2630         if (rc != ECORE_SUCCESS) {
2631                 DP_ERR(p_hwfn,
2632                        "Failed to get default amount for resource %d [%s]\n",
2633                         res_id, ecore_hw_get_resc_name(res_id));
2634                 return rc;
2635         }
2636
2637 #ifndef ASIC_ONLY
2638         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2639                 *p_resc_num = dflt_resc_num;
2640                 *p_resc_start = dflt_resc_start;
2641                 goto out;
2642         }
2643 #endif
2644
2645         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2646                                      &mcp_resp, p_resc_num, p_resc_start);
2647         if (rc != ECORE_SUCCESS) {
2648                 DP_NOTICE(p_hwfn, true,
2649                           "MFW response failure for an allocation request for"
2650                           " resource %d [%s]\n",
2651                           res_id, ecore_hw_get_resc_name(res_id));
2652                 return rc;
2653         }
2654
2655         /* Default driver values are applied in the following cases:
2656          * - The resource allocation MB command is not supported by the MFW
2657          * - There is an internal error in the MFW while processing the request
2658          * - The resource ID is unknown to the MFW
2659          */
2660         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2661                 DP_INFO(p_hwfn,
2662                         "Failed to receive allocation info for resource %d [%s]."
2663                         " mcp_resp = 0x%x. Applying default values"
2664                         " [%d,%d].\n",
2665                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2666                         dflt_resc_num, dflt_resc_start);
2667
2668                 *p_resc_num = dflt_resc_num;
2669                 *p_resc_start = dflt_resc_start;
2670                 goto out;
2671         }
2672
2673         /* TBD - remove this when revising the handling of the SB resource */
2674         if (res_id == ECORE_SB) {
2675                 /* Excluding the slowpath SB */
2676                 *p_resc_num -= 1;
2677                 *p_resc_start -= p_hwfn->enabled_func_idx;
2678         }
2679
2680         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2681                 DP_INFO(p_hwfn,
2682                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
2683                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2684                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2685                         drv_resc_alloc ? " - Applying default values" : "");
2686                 if (drv_resc_alloc) {
2687                         *p_resc_num = dflt_resc_num;
2688                         *p_resc_start = dflt_resc_start;
2689                 }
2690         }
2691 out:
2692         return ECORE_SUCCESS;
2693 }
2694
2695 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2696                                                    bool drv_resc_alloc)
2697 {
2698         enum _ecore_status_t rc;
2699         u8 res_id;
2700
2701         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2702                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2703                 if (rc != ECORE_SUCCESS)
2704                         return rc;
2705         }
2706
2707         return ECORE_SUCCESS;
2708 }
2709
2710 #define ECORE_RESC_ALLOC_LOCK_RETRY_CNT         10
2711 #define ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US    10000 /* 10 msec */
2712
2713 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2714                                               bool drv_resc_alloc)
2715 {
2716         struct ecore_resc_unlock_params resc_unlock_params;
2717         struct ecore_resc_lock_params resc_lock_params;
2718         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2719         u8 res_id;
2720         enum _ecore_status_t rc;
2721 #ifndef ASIC_ONLY
2722         u32 *resc_start = p_hwfn->hw_info.resc_start;
2723         u32 *resc_num = p_hwfn->hw_info.resc_num;
2724         /* For AH, an equal share of the ILT lines between the maximal number of
2725          * PFs is not enough for RoCE. This would be solved by the future
2726          * resource allocation scheme, but isn't currently present for
2727          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2728          * to work - the BB number of ILT lines divided by its max PFs number.
2729          */
2730         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2731 #endif
2732
2733         /* Setting the max values of the soft resources and the following
2734          * resources allocation queries should be atomic. Since several PFs can
2735          * run in parallel - a resource lock is needed.
2736          * If either the resource lock or resource set value commands are not
2737          * supported - skip the the max values setting, release the lock if
2738          * needed, and proceed to the queries. Other failures, including a
2739          * failure to acquire the lock, will cause this function to fail.
2740          * Old drivers that don't acquire the lock can run in parallel, and
2741          * their allocation values won't be affected by the updated max values.
2742          */
2743         OSAL_MEM_ZERO(&resc_lock_params, sizeof(resc_lock_params));
2744         resc_lock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2745         resc_lock_params.retry_num = ECORE_RESC_ALLOC_LOCK_RETRY_CNT;
2746         resc_lock_params.retry_interval = ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2747         resc_lock_params.sleep_b4_retry = true;
2748         OSAL_MEM_ZERO(&resc_unlock_params, sizeof(resc_unlock_params));
2749         resc_unlock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2750
2751         rc = ecore_mcp_resc_lock(p_hwfn, p_hwfn->p_main_ptt, &resc_lock_params);
2752         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2753                 return rc;
2754         } else if (rc == ECORE_NOTIMPL) {
2755                 DP_INFO(p_hwfn,
2756                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2757         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
2758                 DP_NOTICE(p_hwfn, false,
2759                           "Failed to acquire the resource lock for the resource allocation commands\n");
2760                 rc = ECORE_BUSY;
2761                 goto unlock_and_exit;
2762         } else {
2763                 rc = ecore_hw_set_soft_resc_size(p_hwfn);
2764                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2765                         DP_NOTICE(p_hwfn, false,
2766                                   "Failed to set the max values of the soft resources\n");
2767                         goto unlock_and_exit;
2768                 } else if (rc == ECORE_NOTIMPL) {
2769                         DP_INFO(p_hwfn,
2770                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2771                         rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2772                                                    &resc_unlock_params);
2773                         if (rc != ECORE_SUCCESS)
2774                                 DP_INFO(p_hwfn,
2775                                         "Failed to release the resource lock for the resource allocation commands\n");
2776                 }
2777         }
2778
2779         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
2780         if (rc != ECORE_SUCCESS)
2781                 goto unlock_and_exit;
2782
2783         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2784                 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2785                                            &resc_unlock_params);
2786                 if (rc != ECORE_SUCCESS)
2787                         DP_INFO(p_hwfn,
2788                                 "Failed to release the resource lock for the resource allocation commands\n");
2789         }
2790
2791 #ifndef ASIC_ONLY
2792         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2793                 /* Reduced build contains less PQs */
2794                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2795                         resc_num[ECORE_PQ] = 32;
2796                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2797                             p_hwfn->enabled_func_idx;
2798                 }
2799
2800                 /* For AH emulation, since we have a possible maximal number of
2801                  * 16 enabled PFs, in case there are not enough ILT lines -
2802                  * allocate only first PF as RoCE and have all the other ETH
2803                  * only with less ILT lines.
2804                  */
2805                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2806                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2807                                                          resc_num[ECORE_ILT],
2808                                                          roce_min_ilt_lines);
2809         }
2810
2811         /* Correct the common ILT calculation if PF0 has more */
2812         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2813             p_hwfn->p_dev->b_is_emul_full &&
2814             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2815                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2816                     resc_num[ECORE_ILT];
2817 #endif
2818
2819         /* Sanity for ILT */
2820         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2821             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2822                 DP_NOTICE(p_hwfn, true,
2823                           "Can't assign ILT pages [%08x,...,%08x]\n",
2824                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2825                                                                   ECORE_ILT) -
2826                           1);
2827                 return ECORE_INVAL;
2828         }
2829
2830         ecore_hw_set_feat(p_hwfn);
2831
2832         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2833                    "The numbers for each resource are:\n");
2834         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2835                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2836                            ecore_hw_get_resc_name(res_id),
2837                            RESC_NUM(p_hwfn, res_id),
2838                            RESC_START(p_hwfn, res_id));
2839
2840         return ECORE_SUCCESS;
2841
2842 unlock_and_exit:
2843         ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt, &resc_unlock_params);
2844         return rc;
2845 }
2846
2847 static enum _ecore_status_t
2848 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2849                       struct ecore_ptt *p_ptt,
2850                       struct ecore_hw_prepare_params *p_params)
2851 {
2852         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2853         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2854         struct ecore_mcp_link_params *link;
2855         enum _ecore_status_t rc;
2856
2857         /* Read global nvm_cfg address */
2858         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2859
2860         /* Verify MCP has initialized it */
2861         if (!nvm_cfg_addr) {
2862                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2863                 if (p_params->b_relaxed_probe)
2864                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2865                 return ECORE_INVAL;
2866         }
2867
2868 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2869
2870         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2871
2872         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2873             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2874                                                        core_cfg);
2875
2876         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2877
2878         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2879                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2880         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2881                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2882                 break;
2883         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2884                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2885                 break;
2886         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2887                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2888                 break;
2889         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2890                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2891                 break;
2892         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2893                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2894                 break;
2895         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2896                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2897                 break;
2898         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2899                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2900                 break;
2901         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2902                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2903                 break;
2904         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2905                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2906                 break;
2907         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2908                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2909                 break;
2910         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2911                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2912                 break;
2913         default:
2914                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2915                           core_cfg);
2916                 break;
2917         }
2918
2919         /* Read DCBX configuration */
2920         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2921                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2922         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2923                              port_cfg_addr +
2924                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2925         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2926                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2927         switch (dcbx_mode) {
2928         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2929                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2930                 break;
2931         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2932                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2933                 break;
2934         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2935                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2936                 break;
2937         default:
2938                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2939         }
2940
2941         /* Read default link configuration */
2942         link = &p_hwfn->mcp_info->link_input;
2943         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2944             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2945         link_temp = ecore_rd(p_hwfn, p_ptt,
2946                              port_cfg_addr +
2947                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2948         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2949         link->speed.advertised_speeds = link_temp;
2950
2951         link_temp = link->speed.advertised_speeds;
2952         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2953
2954         link_temp = ecore_rd(p_hwfn, p_ptt,
2955                              port_cfg_addr +
2956                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2957         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2958                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2959         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2960                 link->speed.autoneg = true;
2961                 break;
2962         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2963                 link->speed.forced_speed = 1000;
2964                 break;
2965         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2966                 link->speed.forced_speed = 10000;
2967                 break;
2968         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2969                 link->speed.forced_speed = 25000;
2970                 break;
2971         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2972                 link->speed.forced_speed = 40000;
2973                 break;
2974         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2975                 link->speed.forced_speed = 50000;
2976                 break;
2977         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2978                 link->speed.forced_speed = 100000;
2979                 break;
2980         default:
2981                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2982         }
2983
2984         p_hwfn->mcp_info->link_capabilities.default_speed =
2985             link->speed.forced_speed;
2986         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2987             link->speed.autoneg;
2988
2989         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2990         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2991         link->pause.autoneg = !!(link_temp &
2992                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2993         link->pause.forced_rx = !!(link_temp &
2994                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2995         link->pause.forced_tx = !!(link_temp &
2996                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2997         link->loopback_mode = 0;
2998
2999         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3000                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
3001                    link->speed.forced_speed, link->speed.advertised_speeds,
3002                    link->speed.autoneg, link->pause.autoneg);
3003
3004         /* Read Multi-function information from shmem */
3005         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3006             OFFSETOF(struct nvm_cfg1, glob) +
3007             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3008
3009         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3010
3011         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3012             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3013
3014         switch (mf_mode) {
3015         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3016                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3017                 break;
3018         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3019                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3020                 break;
3021         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3022                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3023                 break;
3024         }
3025         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3026                 p_hwfn->p_dev->mf_mode);
3027
3028         /* Read Multi-function information from shmem */
3029         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3030             OFFSETOF(struct nvm_cfg1, glob) +
3031             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3032
3033         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3034         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3035                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3036                              &p_hwfn->hw_info.device_capabilities);
3037         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3038                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3039                              &p_hwfn->hw_info.device_capabilities);
3040         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3041                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3042                              &p_hwfn->hw_info.device_capabilities);
3043         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3044                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3045                              &p_hwfn->hw_info.device_capabilities);
3046         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3047                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3048                              &p_hwfn->hw_info.device_capabilities);
3049
3050         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3051         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3052                 rc = ECORE_SUCCESS;
3053                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3054         }
3055
3056         return rc;
3057 }
3058
3059 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3060                                 struct ecore_ptt *p_ptt)
3061 {
3062         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3063         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3064         struct ecore_dev *p_dev = p_hwfn->p_dev;
3065
3066         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3067
3068         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3069          * in the other bits are selected.
3070          * Bits 1-15 are for functions 1-15, respectively, and their value is
3071          * '0' only for enabled functions (function 0 always exists and
3072          * enabled).
3073          * In case of CMT in BB, only the "even" functions are enabled, and thus
3074          * the number of functions for both hwfns is learnt from the same bits.
3075          */
3076         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3077                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3078                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3079         } else { /* E5 */
3080                 reg_function_hide = 0;
3081         }
3082
3083         if (reg_function_hide & 0x1) {
3084                 if (ECORE_IS_BB(p_dev)) {
3085                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3086                                 num_funcs = 0;
3087                                 eng_mask = 0xaaaa;
3088                         } else {
3089                                 num_funcs = 1;
3090                                 eng_mask = 0x5554;
3091                         }
3092                 } else {
3093                         num_funcs = 1;
3094                         eng_mask = 0xfffe;
3095                 }
3096
3097                 /* Get the number of the enabled functions on the engine */
3098                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3099                 while (tmp) {
3100                         if (tmp & 0x1)
3101                                 num_funcs++;
3102                         tmp >>= 0x1;
3103                 }
3104
3105                 /* Get the PF index within the enabled functions */
3106                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3107                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3108                 while (tmp) {
3109                         if (tmp & 0x1)
3110                                 enabled_func_idx--;
3111                         tmp >>= 0x1;
3112                 }
3113         }
3114
3115         p_hwfn->num_funcs_on_engine = num_funcs;
3116         p_hwfn->enabled_func_idx = enabled_func_idx;
3117
3118 #ifndef ASIC_ONLY
3119         if (CHIP_REV_IS_FPGA(p_dev)) {
3120                 DP_NOTICE(p_hwfn, false,
3121                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3122                 p_hwfn->num_funcs_on_engine = 4;
3123         }
3124 #endif
3125
3126         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3127                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3128                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3129                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3130 }
3131
3132 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3133                                       struct ecore_ptt *p_ptt)
3134 {
3135         u32 port_mode;
3136
3137 #ifndef ASIC_ONLY
3138         /* Read the port mode */
3139         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3140                 port_mode = 4;
3141         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3142                  (p_hwfn->p_dev->num_hwfns > 1))
3143                 /* In CMT on emulation, assume 1 port */
3144                 port_mode = 1;
3145         else
3146 #endif
3147         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3148
3149         if (port_mode < 3) {
3150                 p_hwfn->p_dev->num_ports_in_engines = 1;
3151         } else if (port_mode <= 5) {
3152                 p_hwfn->p_dev->num_ports_in_engines = 2;
3153         } else {
3154                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3155                           p_hwfn->p_dev->num_ports_in_engines);
3156
3157                 /* Default num_ports_in_engines to something */
3158                 p_hwfn->p_dev->num_ports_in_engines = 1;
3159         }
3160 }
3161
3162 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3163                                          struct ecore_ptt *p_ptt)
3164 {
3165         u32 port;
3166         int i;
3167
3168         p_hwfn->p_dev->num_ports_in_engines = 0;
3169
3170 #ifndef ASIC_ONLY
3171         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3172                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3173                 switch ((port & 0xf000) >> 12) {
3174                 case 1:
3175                         p_hwfn->p_dev->num_ports_in_engines = 1;
3176                         break;
3177                 case 3:
3178                         p_hwfn->p_dev->num_ports_in_engines = 2;
3179                         break;
3180                 case 0xf:
3181                         p_hwfn->p_dev->num_ports_in_engines = 4;
3182                         break;
3183                 default:
3184                         DP_NOTICE(p_hwfn, false,
3185                                   "Unknown port mode in ECO_RESERVED %08x\n",
3186                                   port);
3187                 }
3188         } else
3189 #endif
3190                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3191                         port = ecore_rd(p_hwfn, p_ptt,
3192                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3193                                         (i * 4));
3194                         if (port & 1)
3195                                 p_hwfn->p_dev->num_ports_in_engines++;
3196                 }
3197 }
3198
3199 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3200                                    struct ecore_ptt *p_ptt)
3201 {
3202         if (ECORE_IS_BB(p_hwfn->p_dev))
3203                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3204         else
3205                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3206 }
3207
3208 static enum _ecore_status_t
3209 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3210                   enum ecore_pci_personality personality,
3211                   struct ecore_hw_prepare_params *p_params)
3212 {
3213         bool drv_resc_alloc = p_params->drv_resc_alloc;
3214         enum _ecore_status_t rc;
3215
3216         /* Since all information is common, only first hwfns should do this */
3217         if (IS_LEAD_HWFN(p_hwfn)) {
3218                 rc = ecore_iov_hw_info(p_hwfn);
3219                 if (rc != ECORE_SUCCESS) {
3220                         if (p_params->b_relaxed_probe)
3221                                 p_params->p_relaxed_res =
3222                                                 ECORE_HW_PREPARE_BAD_IOV;
3223                         else
3224                                 return rc;
3225                 }
3226         }
3227
3228         /* TODO In get_hw_info, amoungst others:
3229          * Get MCP FW revision and determine according to it the supported
3230          * featrues (e.g. DCB)
3231          * Get boot mode
3232          * ecore_get_pcie_width_speed, WOL capability.
3233          * Number of global CQ-s (for storage
3234          */
3235         ecore_hw_info_port_num(p_hwfn, p_ptt);
3236
3237 #ifndef ASIC_ONLY
3238         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3239 #endif
3240         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3241         if (rc != ECORE_SUCCESS)
3242                 return rc;
3243 #ifndef ASIC_ONLY
3244         }
3245 #endif
3246
3247         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3248         if (rc != ECORE_SUCCESS) {
3249                 if (p_params->b_relaxed_probe)
3250                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3251                 else
3252                         return rc;
3253         }
3254
3255 #ifndef ASIC_ONLY
3256         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3257 #endif
3258                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3259                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3260 #ifndef ASIC_ONLY
3261         } else {
3262                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3263
3264                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3265                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3266         }
3267 #endif
3268
3269         if (ecore_mcp_is_init(p_hwfn)) {
3270                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3271                         p_hwfn->hw_info.ovlan =
3272                             p_hwfn->mcp_info->func_info.ovlan;
3273
3274                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3275         }
3276
3277         if (personality != ECORE_PCI_DEFAULT) {
3278                 p_hwfn->hw_info.personality = personality;
3279         } else if (ecore_mcp_is_init(p_hwfn)) {
3280                 enum ecore_pci_personality protocol;
3281
3282                 protocol = p_hwfn->mcp_info->func_info.protocol;
3283                 p_hwfn->hw_info.personality = protocol;
3284         }
3285
3286 #ifndef ASIC_ONLY
3287         /* To overcome ILT lack for emulation, until at least until we'll have
3288          * a definite answer from system about it, allow only PF0 to be RoCE.
3289          */
3290         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3291                 if (!p_hwfn->rel_pf_id)
3292                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3293                 else
3294                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3295         }
3296 #endif
3297
3298         /* although in BB some constellations may support more than 4 tcs,
3299          * that can result in performance penalty in some cases. 4
3300          * represents a good tradeoff between performance and flexibility.
3301          */
3302         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3303
3304         /* start out with a single active tc. This can be increased either
3305          * by dcbx negotiation or by upper layer driver
3306          */
3307         p_hwfn->hw_info.num_active_tc = 1;
3308
3309         ecore_get_num_funcs(p_hwfn, p_ptt);
3310
3311         if (ecore_mcp_is_init(p_hwfn))
3312                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3313
3314         /* In case of forcing the driver's default resource allocation, calling
3315          * ecore_hw_get_resc() should come after initializing the personality
3316          * and after getting the number of functions, since the calculation of
3317          * the resources/features depends on them.
3318          * This order is not harmful if not forcing.
3319          */
3320         rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3321         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3322                 rc = ECORE_SUCCESS;
3323                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3324         }
3325
3326         return rc;
3327 }
3328
3329 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3330 {
3331         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3332         u32 tmp;
3333
3334         /* Read Vendor Id / Device Id */
3335         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3336                                   &p_dev->vendor_id);
3337         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3338                                   &p_dev->device_id);
3339
3340         /* Determine type */
3341         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3342                 p_dev->type = ECORE_DEV_TYPE_AH;
3343         else
3344                 p_dev->type = ECORE_DEV_TYPE_BB;
3345
3346         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3347                                          MISCS_REG_CHIP_NUM);
3348         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3349                                          MISCS_REG_CHIP_REV);
3350
3351         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3352
3353         /* Learn number of HW-functions */
3354         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3355                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
3356
3357         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3358                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3359                 p_dev->num_hwfns = 2;
3360         } else {
3361                 p_dev->num_hwfns = 1;
3362         }
3363
3364 #ifndef ASIC_ONLY
3365         if (CHIP_REV_IS_EMUL(p_dev)) {
3366                 /* For some reason we have problems with this register
3367                  * in B0 emulation; Simply assume no CMT
3368                  */
3369                 DP_NOTICE(p_dev->hwfns, false,
3370                           "device on emul - assume no CMT\n");
3371                 p_dev->num_hwfns = 1;
3372         }
3373 #endif
3374
3375         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3376                                        MISCS_REG_CHIP_TEST_REG) >> 4;
3377         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3378         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3379                                            MISCS_REG_CHIP_METAL);
3380         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3381         DP_INFO(p_dev->hwfns,
3382                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3383                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3384                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3385                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3386                 p_dev->chip_metal);
3387
3388         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3389                 DP_NOTICE(p_dev->hwfns, false,
3390                           "The chip type/rev (BB A0) is not supported!\n");
3391                 return ECORE_ABORTED;
3392         }
3393 #ifndef ASIC_ONLY
3394         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3395                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3396                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3397
3398         if (CHIP_REV_IS_EMUL(p_dev)) {
3399                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3400                                MISCS_REG_ECO_RESERVED);
3401                 if (tmp & (1 << 29)) {
3402                         DP_NOTICE(p_hwfn, false,
3403                                   "Emulation: Running on a FULL build\n");
3404                         p_dev->b_is_emul_full = true;
3405                 } else {
3406                         DP_NOTICE(p_hwfn, false,
3407                                   "Emulation: Running on a REDUCED build\n");
3408                 }
3409         }
3410 #endif
3411
3412         return ECORE_SUCCESS;
3413 }
3414
3415 #ifndef LINUX_REMOVE
3416 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3417 {
3418         int j;
3419
3420         if (IS_VF(p_dev))
3421                 return;
3422
3423         for_each_hwfn(p_dev, j) {
3424                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3425
3426                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3427                            "Mark hw/fw uninitialized\n");
3428
3429                 p_hwfn->hw_init_done = false;
3430                 p_hwfn->first_on_engine = false;
3431
3432                 ecore_ptt_invalidate(p_hwfn);
3433         }
3434 }
3435 #endif
3436
3437 static enum _ecore_status_t
3438 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3439                         void OSAL_IOMEM * p_regview,
3440                         void OSAL_IOMEM * p_doorbells,
3441                         struct ecore_hw_prepare_params *p_params)
3442 {
3443         struct ecore_dev *p_dev = p_hwfn->p_dev;
3444         struct ecore_mdump_info mdump_info;
3445         enum _ecore_status_t rc = ECORE_SUCCESS;
3446
3447         /* Split PCI bars evenly between hwfns */
3448         p_hwfn->regview = p_regview;
3449         p_hwfn->doorbells = p_doorbells;
3450
3451         if (IS_VF(p_dev))
3452                 return ecore_vf_hw_prepare(p_hwfn);
3453
3454         /* Validate that chip access is feasible */
3455         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3456                 DP_ERR(p_hwfn,
3457                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3458                 if (p_params->b_relaxed_probe)
3459                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3460                 return ECORE_INVAL;
3461         }
3462
3463         get_function_id(p_hwfn);
3464
3465         /* Allocate PTT pool */
3466         rc = ecore_ptt_pool_alloc(p_hwfn);
3467         if (rc) {
3468                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3469                 if (p_params->b_relaxed_probe)
3470                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3471                 goto err0;
3472         }
3473
3474         /* Allocate the main PTT */
3475         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3476
3477         /* First hwfn learns basic information, e.g., number of hwfns */
3478         if (!p_hwfn->my_id) {
3479                 rc = ecore_get_dev_info(p_dev);
3480                 if (rc != ECORE_SUCCESS) {
3481                         if (p_params->b_relaxed_probe)
3482                                 p_params->p_relaxed_res =
3483                                         ECORE_HW_PREPARE_FAILED_DEV;
3484                         goto err1;
3485                 }
3486         }
3487
3488         ecore_hw_hwfn_prepare(p_hwfn);
3489
3490         /* Initialize MCP structure */
3491         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3492         if (rc) {
3493                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3494                 if (p_params->b_relaxed_probe)
3495                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3496                 goto err1;
3497         }
3498
3499         /* Read the device configuration information from the HW and SHMEM */
3500         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3501                                p_params->personality, p_params);
3502         if (rc) {
3503                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3504                 goto err2;
3505         }
3506
3507         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3508          * called, since among others it sets the ports number in an engine.
3509          */
3510         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3511             !p_dev->recov_in_prog) {
3512                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3513                 if (rc != ECORE_SUCCESS)
3514                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3515         }
3516
3517         /* Check if mdump logs are present and update the epoch value */
3518         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3519                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3520                                               &mdump_info);
3521                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3522                         DP_NOTICE(p_hwfn, false,
3523                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3524                 }
3525
3526                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3527                                            p_params->epoch);
3528         }
3529
3530         /* Allocate the init RT array and initialize the init-ops engine */
3531         rc = ecore_init_alloc(p_hwfn);
3532         if (rc) {
3533                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3534                 if (p_params->b_relaxed_probe)
3535                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3536                 goto err2;
3537         }
3538 #ifndef ASIC_ONLY
3539         if (CHIP_REV_IS_FPGA(p_dev)) {
3540                 DP_NOTICE(p_hwfn, false,
3541                           "FPGA: workaround; Prevent DMAE parities\n");
3542                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3543                          7);
3544
3545                 DP_NOTICE(p_hwfn, false,
3546                           "FPGA: workaround: Set VF bar0 size\n");
3547                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3548                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3549         }
3550 #endif
3551
3552         return rc;
3553 err2:
3554         if (IS_LEAD_HWFN(p_hwfn))
3555                 ecore_iov_free_hw_info(p_dev);
3556         ecore_mcp_free(p_hwfn);
3557 err1:
3558         ecore_hw_hwfn_free(p_hwfn);
3559 err0:
3560         return rc;
3561 }
3562
3563 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3564                                       struct ecore_hw_prepare_params *p_params)
3565 {
3566         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3567         enum _ecore_status_t rc;
3568
3569         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3570
3571         if (p_params->b_relaxed_probe)
3572                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3573
3574         /* Store the precompiled init data ptrs */
3575         if (IS_PF(p_dev))
3576                 ecore_init_iro_array(p_dev);
3577
3578         /* Initialize the first hwfn - will learn number of hwfns */
3579         rc = ecore_hw_prepare_single(p_hwfn,
3580                                      p_dev->regview,
3581                                      p_dev->doorbells, p_params);
3582         if (rc != ECORE_SUCCESS)
3583                 return rc;
3584
3585         p_params->personality = p_hwfn->hw_info.personality;
3586
3587         /* initilalize 2nd hwfn if necessary */
3588         if (p_dev->num_hwfns > 1) {
3589                 void OSAL_IOMEM *p_regview, *p_doorbell;
3590                 u8 OSAL_IOMEM *addr;
3591
3592                 /* adjust bar offset for second engine */
3593                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3594                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3595                 p_regview = (void OSAL_IOMEM *)addr;
3596
3597                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3598                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3599                 p_doorbell = (void OSAL_IOMEM *)addr;
3600
3601                 /* prepare second hw function */
3602                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3603                                              p_doorbell, p_params);
3604
3605                 /* in case of error, need to free the previously
3606                  * initiliazed hwfn 0.
3607                  */
3608                 if (rc != ECORE_SUCCESS) {
3609                         if (p_params->b_relaxed_probe)
3610                                 p_params->p_relaxed_res =
3611                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3612
3613                         if (IS_PF(p_dev)) {
3614                                 ecore_init_free(p_hwfn);
3615                                 ecore_mcp_free(p_hwfn);
3616                                 ecore_hw_hwfn_free(p_hwfn);
3617                         } else {
3618                                 DP_NOTICE(p_dev, true,
3619                                           "What do we need to free when VF hwfn1 init fails\n");
3620                         }
3621                         return rc;
3622                 }
3623         }
3624
3625         return rc;
3626 }
3627
3628 void ecore_hw_remove(struct ecore_dev *p_dev)
3629 {
3630         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3631         int i;
3632
3633         if (IS_PF(p_dev))
3634                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3635                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3636
3637         for_each_hwfn(p_dev, i) {
3638                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3639
3640                 if (IS_VF(p_dev)) {
3641                         ecore_vf_pf_release(p_hwfn);
3642                         continue;
3643                 }
3644
3645                 ecore_init_free(p_hwfn);
3646                 ecore_hw_hwfn_free(p_hwfn);
3647                 ecore_mcp_free(p_hwfn);
3648
3649                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3650         }
3651
3652         ecore_iov_free_hw_info(p_dev);
3653 }
3654
3655 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3656                                       struct ecore_chain *p_chain)
3657 {
3658         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3659         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3660         struct ecore_chain_next *p_next;
3661         u32 size, i;
3662
3663         if (!p_virt)
3664                 return;
3665
3666         size = p_chain->elem_size * p_chain->usable_per_page;
3667
3668         for (i = 0; i < p_chain->page_cnt; i++) {
3669                 if (!p_virt)
3670                         break;
3671
3672                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3673                 p_virt_next = p_next->next_virt;
3674                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3675
3676                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3677                                        ECORE_CHAIN_PAGE_SIZE);
3678
3679                 p_virt = p_virt_next;
3680                 p_phys = p_phys_next;
3681         }
3682 }
3683
3684 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3685                                     struct ecore_chain *p_chain)
3686 {
3687         if (!p_chain->p_virt_addr)
3688                 return;
3689
3690         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3691                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3692 }
3693
3694 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3695                                  struct ecore_chain *p_chain)
3696 {
3697         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3698         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3699         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3700
3701         if (!pp_virt_addr_tbl)
3702                 return;
3703
3704         if (!p_pbl_virt)
3705                 goto out;
3706
3707         for (i = 0; i < page_cnt; i++) {
3708                 if (!pp_virt_addr_tbl[i])
3709                         break;
3710
3711                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3712                                        *(dma_addr_t *)p_pbl_virt,
3713                                        ECORE_CHAIN_PAGE_SIZE);
3714
3715                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3716         }
3717
3718         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3719
3720         if (!p_chain->b_external_pbl)
3721                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3722                                        p_chain->pbl_sp.p_phys_table, pbl_size);
3723  out:
3724         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3725 }
3726
3727 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3728 {
3729         switch (p_chain->mode) {
3730         case ECORE_CHAIN_MODE_NEXT_PTR:
3731                 ecore_chain_free_next_ptr(p_dev, p_chain);
3732                 break;
3733         case ECORE_CHAIN_MODE_SINGLE:
3734                 ecore_chain_free_single(p_dev, p_chain);
3735                 break;
3736         case ECORE_CHAIN_MODE_PBL:
3737                 ecore_chain_free_pbl(p_dev, p_chain);
3738                 break;
3739         }
3740 }
3741
3742 static enum _ecore_status_t
3743 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3744                                enum ecore_chain_cnt_type cnt_type,
3745                                osal_size_t elem_size, u32 page_cnt)
3746 {
3747         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3748
3749         /* The actual chain size can be larger than the maximal possible value
3750          * after rounding up the requested elements number to pages, and after
3751          * taking into acount the unusuable elements (next-ptr elements).
3752          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3753          * size/capacity fields are of a u32 type.
3754          */
3755         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3756              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3757             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3758              chain_size > ECORE_U32_MAX)) {
3759                 DP_NOTICE(p_dev, true,
3760                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3761                           (unsigned long)chain_size);
3762                 return ECORE_INVAL;
3763         }
3764
3765         return ECORE_SUCCESS;
3766 }
3767
3768 static enum _ecore_status_t
3769 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3770 {
3771         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3772         dma_addr_t p_phys = 0;
3773         u32 i;
3774
3775         for (i = 0; i < p_chain->page_cnt; i++) {
3776                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3777                                                  ECORE_CHAIN_PAGE_SIZE);
3778                 if (!p_virt) {
3779                         DP_NOTICE(p_dev, true,
3780                                   "Failed to allocate chain memory\n");
3781                         return ECORE_NOMEM;
3782                 }
3783
3784                 if (i == 0) {
3785                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3786                         ecore_chain_reset(p_chain);
3787                 } else {
3788                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3789                                                        p_virt, p_phys);
3790                 }
3791
3792                 p_virt_prev = p_virt;
3793         }
3794         /* Last page's next element should point to the beginning of the
3795          * chain.
3796          */
3797         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3798                                        p_chain->p_virt_addr,
3799                                        p_chain->p_phys_addr);
3800
3801         return ECORE_SUCCESS;
3802 }
3803
3804 static enum _ecore_status_t
3805 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3806 {
3807         dma_addr_t p_phys = 0;
3808         void *p_virt = OSAL_NULL;
3809
3810         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3811         if (!p_virt) {
3812                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3813                 return ECORE_NOMEM;
3814         }
3815
3816         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3817         ecore_chain_reset(p_chain);
3818
3819         return ECORE_SUCCESS;
3820 }
3821
3822 static enum _ecore_status_t
3823 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3824                       struct ecore_chain *p_chain,
3825                       struct ecore_chain_ext_pbl *ext_pbl)
3826 {
3827         void *p_virt = OSAL_NULL;
3828         u8 *p_pbl_virt = OSAL_NULL;
3829         void **pp_virt_addr_tbl = OSAL_NULL;
3830         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3831         u32 page_cnt = p_chain->page_cnt, size, i;
3832
3833         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3834         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
3835         if (!pp_virt_addr_tbl) {
3836                 DP_NOTICE(p_dev, true,
3837                           "Failed to allocate memory for the chain virtual addresses table\n");
3838                 return ECORE_NOMEM;
3839         }
3840
3841         /* The allocation of the PBL table is done with its full size, since it
3842          * is expected to be successive.
3843          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3844          * failure, since pp_virt_addr_tbl was previously allocated, and it
3845          * should be saved to allow its freeing during the error flow.
3846          */
3847         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3848
3849         if (ext_pbl == OSAL_NULL) {
3850                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3851         } else {
3852                 p_pbl_virt = ext_pbl->p_pbl_virt;
3853                 p_pbl_phys = ext_pbl->p_pbl_phys;
3854                 p_chain->b_external_pbl = true;
3855         }
3856
3857         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3858                                  pp_virt_addr_tbl);
3859         if (!p_pbl_virt) {
3860                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3861                 return ECORE_NOMEM;
3862         }
3863
3864         for (i = 0; i < page_cnt; i++) {
3865                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3866                                                  ECORE_CHAIN_PAGE_SIZE);
3867                 if (!p_virt) {
3868                         DP_NOTICE(p_dev, true,
3869                                   "Failed to allocate chain memory\n");
3870                         return ECORE_NOMEM;
3871                 }
3872
3873                 if (i == 0) {
3874                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3875                         ecore_chain_reset(p_chain);
3876                 }
3877
3878                 /* Fill the PBL table with the physical address of the page */
3879                 *(dma_addr_t *)p_pbl_virt = p_phys;
3880                 /* Keep the virtual address of the page */
3881                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3882
3883                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3884         }
3885
3886         return ECORE_SUCCESS;
3887 }
3888
3889 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3890                                        enum ecore_chain_use_mode intended_use,
3891                                        enum ecore_chain_mode mode,
3892                                        enum ecore_chain_cnt_type cnt_type,
3893                                        u32 num_elems, osal_size_t elem_size,
3894                                        struct ecore_chain *p_chain,
3895                                        struct ecore_chain_ext_pbl *ext_pbl)
3896 {
3897         u32 page_cnt;
3898         enum _ecore_status_t rc = ECORE_SUCCESS;
3899
3900         if (mode == ECORE_CHAIN_MODE_SINGLE)
3901                 page_cnt = 1;
3902         else
3903                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3904
3905         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3906                                             page_cnt);
3907         if (rc) {
3908                 DP_NOTICE(p_dev, true,
3909                           "Cannot allocate a chain with the given arguments:\n"
3910                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3911                           intended_use, mode, cnt_type, num_elems, elem_size);
3912                 return rc;
3913         }
3914
3915         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3916                                 mode, cnt_type, p_dev->dp_ctx);
3917
3918         switch (mode) {
3919         case ECORE_CHAIN_MODE_NEXT_PTR:
3920                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3921                 break;
3922         case ECORE_CHAIN_MODE_SINGLE:
3923                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3924                 break;
3925         case ECORE_CHAIN_MODE_PBL:
3926                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3927                 break;
3928         }
3929         if (rc)
3930                 goto nomem;
3931
3932         return ECORE_SUCCESS;
3933
3934 nomem:
3935         ecore_chain_free(p_dev, p_chain);
3936         return rc;
3937 }
3938
3939 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3940                                        u16 src_id, u16 *dst_id)
3941 {
3942         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3943                 u16 min, max;
3944
3945                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3946                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3947                 DP_NOTICE(p_hwfn, true,
3948                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3949                           src_id, min, max);
3950
3951                 return ECORE_INVAL;
3952         }
3953
3954         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3955
3956         return ECORE_SUCCESS;
3957 }
3958
3959 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3960                                     u8 src_id, u8 *dst_id)
3961 {
3962         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3963                 u8 min, max;
3964
3965                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3966                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3967                 DP_NOTICE(p_hwfn, true,
3968                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3969                           src_id, min, max);
3970
3971                 return ECORE_INVAL;
3972         }
3973
3974         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3975
3976         return ECORE_SUCCESS;
3977 }
3978
3979 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3980                                       u8 src_id, u8 *dst_id)
3981 {
3982         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3983                 u8 min, max;
3984
3985                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3986                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3987                 DP_NOTICE(p_hwfn, true,
3988                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3989                           src_id, min, max);
3990
3991                 return ECORE_INVAL;
3992         }
3993
3994         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3995
3996         return ECORE_SUCCESS;
3997 }
3998
3999 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4000                                               struct ecore_ptt *p_ptt,
4001                                               u8 *p_filter)
4002 {
4003         u32 high, low, en;
4004         int i;
4005
4006         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4007                 return ECORE_SUCCESS;
4008
4009         high = p_filter[1] | (p_filter[0] << 8);
4010         low = p_filter[5] | (p_filter[4] << 8) |
4011             (p_filter[3] << 16) | (p_filter[2] << 24);
4012
4013         /* Find a free entry and utilize it */
4014         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4015                 en = ecore_rd(p_hwfn, p_ptt,
4016                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4017                 if (en)
4018                         continue;
4019                 ecore_wr(p_hwfn, p_ptt,
4020                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4021                          2 * i * sizeof(u32), low);
4022                 ecore_wr(p_hwfn, p_ptt,
4023                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4024                          (2 * i + 1) * sizeof(u32), high);
4025                 ecore_wr(p_hwfn, p_ptt,
4026                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4027                 ecore_wr(p_hwfn, p_ptt,
4028                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4029                          i * sizeof(u32), 0);
4030                 ecore_wr(p_hwfn, p_ptt,
4031                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4032                 break;
4033         }
4034         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4035                 DP_NOTICE(p_hwfn, false,
4036                           "Failed to find an empty LLH filter to utilize\n");
4037                 return ECORE_INVAL;
4038         }
4039
4040         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4041                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
4042                    p_filter[0], p_filter[1], p_filter[2],
4043                    p_filter[3], p_filter[4], p_filter[5], i);
4044
4045         return ECORE_SUCCESS;
4046 }
4047
4048 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4049                                  struct ecore_ptt *p_ptt, u8 *p_filter)
4050 {
4051         u32 high, low;
4052         int i;
4053
4054         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4055                 return;
4056
4057         high = p_filter[1] | (p_filter[0] << 8);
4058         low = p_filter[5] | (p_filter[4] << 8) |
4059             (p_filter[3] << 16) | (p_filter[2] << 24);
4060
4061         /* Find the entry and clean it */
4062         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4063                 if (ecore_rd(p_hwfn, p_ptt,
4064                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4065                              2 * i * sizeof(u32)) != low)
4066                         continue;
4067                 if (ecore_rd(p_hwfn, p_ptt,
4068                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4069                              (2 * i + 1) * sizeof(u32)) != high)
4070                         continue;
4071
4072                 ecore_wr(p_hwfn, p_ptt,
4073                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4074                 ecore_wr(p_hwfn, p_ptt,
4075                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4076                          2 * i * sizeof(u32), 0);
4077                 ecore_wr(p_hwfn, p_ptt,
4078                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4079                          (2 * i + 1) * sizeof(u32), 0);
4080                 break;
4081         }
4082         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4083                 DP_NOTICE(p_hwfn, false,
4084                           "Tried to remove a non-configured filter\n");
4085 }
4086
4087 enum _ecore_status_t
4088 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4089                               struct ecore_ptt *p_ptt,
4090                               u16 source_port_or_eth_type,
4091                               u16 dest_port,
4092                               enum ecore_llh_port_filter_type_t type)
4093 {
4094         u32 high, low, en;
4095         int i;
4096
4097         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4098                 return ECORE_SUCCESS;
4099
4100         high = 0;
4101         low = 0;
4102         switch (type) {
4103         case ECORE_LLH_FILTER_ETHERTYPE:
4104                 high = source_port_or_eth_type;
4105                 break;
4106         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4107         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4108                 low = source_port_or_eth_type << 16;
4109                 break;
4110         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4111         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4112                 low = dest_port;
4113                 break;
4114         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4115         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4116                 low = (source_port_or_eth_type << 16) | dest_port;
4117                 break;
4118         default:
4119                 DP_NOTICE(p_hwfn, true,
4120                           "Non valid LLH protocol filter type %d\n", type);
4121                 return ECORE_INVAL;
4122         }
4123         /* Find a free entry and utilize it */
4124         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4125                 en = ecore_rd(p_hwfn, p_ptt,
4126                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4127                 if (en)
4128                         continue;
4129                 ecore_wr(p_hwfn, p_ptt,
4130                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4131                          2 * i * sizeof(u32), low);
4132                 ecore_wr(p_hwfn, p_ptt,
4133                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4134                          (2 * i + 1) * sizeof(u32), high);
4135                 ecore_wr(p_hwfn, p_ptt,
4136                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4137                 ecore_wr(p_hwfn, p_ptt,
4138                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4139                          i * sizeof(u32), 1 << type);
4140                 ecore_wr(p_hwfn, p_ptt,
4141                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4142                 break;
4143         }
4144         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4145                 DP_NOTICE(p_hwfn, false,
4146                           "Failed to find an empty LLH filter to utilize\n");
4147                 return ECORE_NORESOURCES;
4148         }
4149         switch (type) {
4150         case ECORE_LLH_FILTER_ETHERTYPE:
4151                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4152                            "ETH type %x is added at %d\n",
4153                            source_port_or_eth_type, i);
4154                 break;
4155         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4156                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4157                            "TCP src port %x is added at %d\n",
4158                            source_port_or_eth_type, i);
4159                 break;
4160         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4161                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4162                            "UDP src port %x is added at %d\n",
4163                            source_port_or_eth_type, i);
4164                 break;
4165         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4166                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4167                            "TCP dst port %x is added at %d\n", dest_port, i);
4168                 break;
4169         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4170                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4171                            "UDP dst port %x is added at %d\n", dest_port, i);
4172                 break;
4173         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4174                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4175                            "TCP src/dst ports %x/%x are added at %d\n",
4176                            source_port_or_eth_type, dest_port, i);
4177                 break;
4178         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4179                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4180                            "UDP src/dst ports %x/%x are added at %d\n",
4181                            source_port_or_eth_type, dest_port, i);
4182                 break;
4183         }
4184         return ECORE_SUCCESS;
4185 }
4186
4187 void
4188 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4189                                  struct ecore_ptt *p_ptt,
4190                                  u16 source_port_or_eth_type,
4191                                  u16 dest_port,
4192                                  enum ecore_llh_port_filter_type_t type)
4193 {
4194         u32 high, low;
4195         int i;
4196
4197         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4198                 return;
4199
4200         high = 0;
4201         low = 0;
4202         switch (type) {
4203         case ECORE_LLH_FILTER_ETHERTYPE:
4204                 high = source_port_or_eth_type;
4205                 break;
4206         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4207         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4208                 low = source_port_or_eth_type << 16;
4209                 break;
4210         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4211         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4212                 low = dest_port;
4213                 break;
4214         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4215         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4216                 low = (source_port_or_eth_type << 16) | dest_port;
4217                 break;
4218         default:
4219                 DP_NOTICE(p_hwfn, true,
4220                           "Non valid LLH protocol filter type %d\n", type);
4221                 return;
4222         }
4223
4224         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4225                 if (!ecore_rd(p_hwfn, p_ptt,
4226                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4227                         continue;
4228                 if (!ecore_rd(p_hwfn, p_ptt,
4229                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4230                         continue;
4231                 if (!(ecore_rd(p_hwfn, p_ptt,
4232                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4233                                i * sizeof(u32)) & (1 << type)))
4234                         continue;
4235                 if (ecore_rd(p_hwfn, p_ptt,
4236                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4237                              2 * i * sizeof(u32)) != low)
4238                         continue;
4239                 if (ecore_rd(p_hwfn, p_ptt,
4240                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4241                              (2 * i + 1) * sizeof(u32)) != high)
4242                         continue;
4243
4244                 ecore_wr(p_hwfn, p_ptt,
4245                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4246                 ecore_wr(p_hwfn, p_ptt,
4247                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4248                 ecore_wr(p_hwfn, p_ptt,
4249                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4250                          i * sizeof(u32), 0);
4251                 ecore_wr(p_hwfn, p_ptt,
4252                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4253                          2 * i * sizeof(u32), 0);
4254                 ecore_wr(p_hwfn, p_ptt,
4255                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4256                          (2 * i + 1) * sizeof(u32), 0);
4257                 break;
4258         }
4259
4260         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4261                 DP_NOTICE(p_hwfn, false,
4262                           "Tried to remove a non-configured filter\n");
4263 }
4264
4265 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4266                                  struct ecore_ptt *p_ptt)
4267 {
4268         int i;
4269
4270         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4271                 return;
4272
4273         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4274                 ecore_wr(p_hwfn, p_ptt,
4275                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4276                 ecore_wr(p_hwfn, p_ptt,
4277                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4278                          2 * i * sizeof(u32), 0);
4279                 ecore_wr(p_hwfn, p_ptt,
4280                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4281                          (2 * i + 1) * sizeof(u32), 0);
4282         }
4283 }
4284
4285 enum _ecore_status_t
4286 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4287                                   struct ecore_ptt *p_ptt)
4288 {
4289         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4290                 ecore_wr(p_hwfn, p_ptt,
4291                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4292                          1 << p_hwfn->abs_pf_id / 2);
4293                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4294                 return ECORE_SUCCESS;
4295         }
4296
4297         DP_NOTICE(p_hwfn, false,
4298                   "This function can't be set as default\n");
4299         return ECORE_INVAL;
4300 }
4301
4302 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4303                                                struct ecore_ptt *p_ptt,
4304                                                u32 hw_addr, void *p_eth_qzone,
4305                                                osal_size_t eth_qzone_size,
4306                                                u8 timeset)
4307 {
4308         struct coalescing_timeset *p_coal_timeset;
4309
4310         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4311                 DP_NOTICE(p_hwfn, true,
4312                           "Coalescing configuration not enabled\n");
4313                 return ECORE_INVAL;
4314         }
4315
4316         p_coal_timeset = p_eth_qzone;
4317         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4318         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4319         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4320         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4321
4322         return ECORE_SUCCESS;
4323 }
4324
4325 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4326                                               u16 rx_coal, u16 tx_coal,
4327                                               void *p_handle)
4328 {
4329         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4330         enum _ecore_status_t rc = ECORE_SUCCESS;
4331         struct ecore_ptt *p_ptt;
4332
4333         /* TODO - Configuring a single queue's coalescing but
4334          * claiming all queues are abiding same configuration
4335          * for PF and VF both.
4336          */
4337
4338         if (IS_VF(p_hwfn->p_dev))
4339                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4340                                                 tx_coal, p_cid);
4341
4342         p_ptt = ecore_ptt_acquire(p_hwfn);
4343         if (!p_ptt)
4344                 return ECORE_AGAIN;
4345
4346         if (rx_coal) {
4347                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4348                 if (rc)
4349                         goto out;
4350                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
4351         }
4352
4353         if (tx_coal) {
4354                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4355                 if (rc)
4356                         goto out;
4357                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
4358         }
4359 out:
4360         ecore_ptt_release(p_hwfn, p_ptt);
4361
4362         return rc;
4363 }
4364
4365 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4366                                             struct ecore_ptt *p_ptt,
4367                                             u16 coalesce,
4368                                             struct ecore_queue_cid *p_cid)
4369 {
4370         struct ustorm_eth_queue_zone eth_qzone;
4371         u8 timeset, timer_res;
4372         u32 address;
4373         enum _ecore_status_t rc;
4374
4375         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4376         if (coalesce <= 0x7F) {
4377                 timer_res = 0;
4378         } else if (coalesce <= 0xFF) {
4379                 timer_res = 1;
4380         } else if (coalesce <= 0x1FF) {
4381                 timer_res = 2;
4382         } else {
4383                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4384                 return ECORE_INVAL;
4385         }
4386         timeset = (u8)(coalesce >> timer_res);
4387
4388         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4389                                      p_cid->abs.sb_idx, false);
4390         if (rc != ECORE_SUCCESS)
4391                 goto out;
4392
4393         address = BAR0_MAP_REG_USDM_RAM +
4394                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4395
4396         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4397                                 sizeof(struct ustorm_eth_queue_zone), timeset);
4398         if (rc != ECORE_SUCCESS)
4399                 goto out;
4400
4401  out:
4402         return rc;
4403 }
4404
4405 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4406                                             struct ecore_ptt *p_ptt,
4407                                             u16 coalesce,
4408                                             struct ecore_queue_cid *p_cid)
4409 {
4410         struct xstorm_eth_queue_zone eth_qzone;
4411         u8 timeset, timer_res;
4412         u32 address;
4413         enum _ecore_status_t rc;
4414
4415         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4416         if (coalesce <= 0x7F) {
4417                 timer_res = 0;
4418         } else if (coalesce <= 0xFF) {
4419                 timer_res = 1;
4420         } else if (coalesce <= 0x1FF) {
4421                 timer_res = 2;
4422         } else {
4423                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4424                 return ECORE_INVAL;
4425         }
4426
4427         timeset = (u8)(coalesce >> timer_res);
4428
4429         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4430                                      p_cid->abs.sb_idx, true);
4431         if (rc != ECORE_SUCCESS)
4432                 goto out;
4433
4434         address = BAR0_MAP_REG_XSDM_RAM +
4435                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4436
4437         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4438                                 sizeof(struct xstorm_eth_queue_zone), timeset);
4439  out:
4440         return rc;
4441 }
4442
4443 /* Calculate final WFQ values for all vports and configure it.
4444  * After this configuration each vport must have
4445  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4446  */
4447 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4448                                                struct ecore_ptt *p_ptt,
4449                                                u32 min_pf_rate)
4450 {
4451         struct init_qm_vport_params *vport_params;
4452         int i;
4453
4454         vport_params = p_hwfn->qm_info.qm_vport_params;
4455
4456         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4457                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4458
4459                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4460                     min_pf_rate;
4461                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4462                                      vport_params[i].first_tx_pq_id,
4463                                      vport_params[i].vport_wfq);
4464         }
4465 }
4466
4467 static void
4468 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4469 {
4470         int i;
4471
4472         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4473                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4474 }
4475
4476 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4477                                              struct ecore_ptt *p_ptt,
4478                                              u32 min_pf_rate)
4479 {
4480         struct init_qm_vport_params *vport_params;
4481         int i;
4482
4483         vport_params = p_hwfn->qm_info.qm_vport_params;
4484
4485         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4486                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4487                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4488                                      vport_params[i].first_tx_pq_id,
4489                                      vport_params[i].vport_wfq);
4490         }
4491 }
4492
4493 /* This function performs several validations for WFQ
4494  * configuration and required min rate for a given vport
4495  * 1. req_rate must be greater than one percent of min_pf_rate.
4496  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4497  *    rates to get less than one percent of min_pf_rate.
4498  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4499  */
4500 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4501                                                  u16 vport_id, u32 req_rate,
4502                                                  u32 min_pf_rate)
4503 {
4504         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4505         int non_requested_count = 0, req_count = 0, i, num_vports;
4506
4507         num_vports = p_hwfn->qm_info.num_vports;
4508
4509 /* Accounting for the vports which are configured for WFQ explicitly */
4510
4511         for (i = 0; i < num_vports; i++) {
4512                 u32 tmp_speed;
4513
4514                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4515                         req_count++;
4516                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4517                         total_req_min_rate += tmp_speed;
4518                 }
4519         }
4520
4521         /* Include current vport data as well */
4522         req_count++;
4523         total_req_min_rate += req_rate;
4524         non_requested_count = num_vports - req_count;
4525
4526         /* validate possible error cases */
4527         if (req_rate > min_pf_rate) {
4528                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4529                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4530                            vport_id, req_rate, min_pf_rate);
4531                 return ECORE_INVAL;
4532         }
4533
4534         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4535                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4536                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4537                            vport_id, req_rate, min_pf_rate);
4538                 return ECORE_INVAL;
4539         }
4540
4541         /* TBD - for number of vports greater than 100 */
4542         if (num_vports > ECORE_WFQ_UNIT) {
4543                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4544                            "Number of vports is greater than %d\n",
4545                            ECORE_WFQ_UNIT);
4546                 return ECORE_INVAL;
4547         }
4548
4549         if (total_req_min_rate > min_pf_rate) {
4550                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4551                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4552                            total_req_min_rate, min_pf_rate);
4553                 return ECORE_INVAL;
4554         }
4555
4556         /* Data left for non requested vports */
4557         total_left_rate = min_pf_rate - total_req_min_rate;
4558         left_rate_per_vp = total_left_rate / non_requested_count;
4559
4560         /* validate if non requested get < 1% of min bw */
4561         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4562                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4563                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4564                            left_rate_per_vp, min_pf_rate);
4565                 return ECORE_INVAL;
4566         }
4567
4568         /* now req_rate for given vport passes all scenarios.
4569          * assign final wfq rates to all vports.
4570          */
4571         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4572         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4573
4574         for (i = 0; i < num_vports; i++) {
4575                 if (p_hwfn->qm_info.wfq_data[i].configured)
4576                         continue;
4577
4578                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4579         }
4580
4581         return ECORE_SUCCESS;
4582 }
4583
4584 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4585                                        struct ecore_ptt *p_ptt,
4586                                        u16 vp_id, u32 rate)
4587 {
4588         struct ecore_mcp_link_state *p_link;
4589         int rc = ECORE_SUCCESS;
4590
4591         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4592
4593         if (!p_link->min_pf_rate) {
4594                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4595                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4596                 return rc;
4597         }
4598
4599         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4600
4601         if (rc == ECORE_SUCCESS)
4602                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4603                                                    p_link->min_pf_rate);
4604         else
4605                 DP_NOTICE(p_hwfn, false,
4606                           "Validation failed while configuring min rate\n");
4607
4608         return rc;
4609 }
4610
4611 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4612                                                    struct ecore_ptt *p_ptt,
4613                                                    u32 min_pf_rate)
4614 {
4615         bool use_wfq = false;
4616         int rc = ECORE_SUCCESS;
4617         u16 i;
4618
4619         /* Validate all pre configured vports for wfq */
4620         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4621                 u32 rate;
4622
4623                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4624                         continue;
4625
4626                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4627                 use_wfq = true;
4628
4629                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4630                 if (rc != ECORE_SUCCESS) {
4631                         DP_NOTICE(p_hwfn, false,
4632                                   "WFQ validation failed while configuring min rate\n");
4633                         break;
4634                 }
4635         }
4636
4637         if (rc == ECORE_SUCCESS && use_wfq)
4638                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4639         else
4640                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4641
4642         return rc;
4643 }
4644
4645 /* Main API for ecore clients to configure vport min rate.
4646  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4647  * rate - Speed in Mbps needs to be assigned to a given vport.
4648  */
4649 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4650 {
4651         int i, rc = ECORE_INVAL;
4652
4653         /* TBD - for multiple hardware functions - that is 100 gig */
4654         if (p_dev->num_hwfns > 1) {
4655                 DP_NOTICE(p_dev, false,
4656                           "WFQ configuration is not supported for this device\n");
4657                 return rc;
4658         }
4659
4660         for_each_hwfn(p_dev, i) {
4661                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4662                 struct ecore_ptt *p_ptt;
4663
4664                 p_ptt = ecore_ptt_acquire(p_hwfn);
4665                 if (!p_ptt)
4666                         return ECORE_TIMEOUT;
4667
4668                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4669
4670                 if (rc != ECORE_SUCCESS) {
4671                         ecore_ptt_release(p_hwfn, p_ptt);
4672                         return rc;
4673                 }
4674
4675                 ecore_ptt_release(p_hwfn, p_ptt);
4676         }
4677
4678         return rc;
4679 }
4680
4681 /* API to configure WFQ from mcp link change */
4682 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4683                                            u32 min_pf_rate)
4684 {
4685         int i;
4686
4687         /* TBD - for multiple hardware functions - that is 100 gig */
4688         if (p_dev->num_hwfns > 1) {
4689                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4690                            "WFQ configuration is not supported for this device\n");
4691                 return;
4692         }
4693
4694         for_each_hwfn(p_dev, i) {
4695                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4696
4697                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4698                                                         p_hwfn->p_dpc_ptt,
4699                                                         min_pf_rate);
4700         }
4701 }
4702
4703 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4704                                        struct ecore_ptt *p_ptt,
4705                                        struct ecore_mcp_link_state *p_link,
4706                                        u8 max_bw)
4707 {
4708         int rc = ECORE_SUCCESS;
4709
4710         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4711
4712         if (!p_link->line_speed && (max_bw != 100))
4713                 return rc;
4714
4715         p_link->speed = (p_link->line_speed * max_bw) / 100;
4716         p_hwfn->qm_info.pf_rl = p_link->speed;
4717
4718         /* Since the limiter also affects Tx-switched traffic, we don't want it
4719          * to limit such traffic in case there's no actual limit.
4720          * In that case, set limit to imaginary high boundary.
4721          */
4722         if (max_bw == 100)
4723                 p_hwfn->qm_info.pf_rl = 100000;
4724
4725         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4726                               p_hwfn->qm_info.pf_rl);
4727
4728         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4729                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4730                    p_link->speed);
4731
4732         return rc;
4733 }
4734
4735 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4736 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4737 {
4738         int i, rc = ECORE_INVAL;
4739
4740         if (max_bw < 1 || max_bw > 100) {
4741                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4742                 return rc;
4743         }
4744
4745         for_each_hwfn(p_dev, i) {
4746                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4747                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4748                 struct ecore_mcp_link_state *p_link;
4749                 struct ecore_ptt *p_ptt;
4750
4751                 p_link = &p_lead->mcp_info->link_output;
4752
4753                 p_ptt = ecore_ptt_acquire(p_hwfn);
4754                 if (!p_ptt)
4755                         return ECORE_TIMEOUT;
4756
4757                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4758                                                         p_link, max_bw);
4759
4760                 ecore_ptt_release(p_hwfn, p_ptt);
4761
4762                 if (rc != ECORE_SUCCESS)
4763                         break;
4764         }
4765
4766         return rc;
4767 }
4768
4769 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4770                                        struct ecore_ptt *p_ptt,
4771                                        struct ecore_mcp_link_state *p_link,
4772                                        u8 min_bw)
4773 {
4774         int rc = ECORE_SUCCESS;
4775
4776         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4777         p_hwfn->qm_info.pf_wfq = min_bw;
4778
4779         if (!p_link->line_speed)
4780                 return rc;
4781
4782         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4783
4784         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4785
4786         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4787                    "Configured MIN bandwidth to be %d Mb/sec\n",
4788                    p_link->min_pf_rate);
4789
4790         return rc;
4791 }
4792
4793 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4794 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4795 {
4796         int i, rc = ECORE_INVAL;
4797
4798         if (min_bw < 1 || min_bw > 100) {
4799                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4800                 return rc;
4801         }
4802
4803         for_each_hwfn(p_dev, i) {
4804                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4805                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4806                 struct ecore_mcp_link_state *p_link;
4807                 struct ecore_ptt *p_ptt;
4808
4809                 p_link = &p_lead->mcp_info->link_output;
4810
4811                 p_ptt = ecore_ptt_acquire(p_hwfn);
4812                 if (!p_ptt)
4813                         return ECORE_TIMEOUT;
4814
4815                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4816                                                         p_link, min_bw);
4817                 if (rc != ECORE_SUCCESS) {
4818                         ecore_ptt_release(p_hwfn, p_ptt);
4819                         return rc;
4820                 }
4821
4822                 if (p_link->min_pf_rate) {
4823                         u32 min_rate = p_link->min_pf_rate;
4824
4825                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4826                                                                      p_ptt,
4827                                                                      min_rate);
4828                 }
4829
4830                 ecore_ptt_release(p_hwfn, p_ptt);
4831         }
4832
4833         return rc;
4834 }
4835
4836 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4837 {
4838         struct ecore_mcp_link_state *p_link;
4839
4840         p_link = &p_hwfn->mcp_info->link_output;
4841
4842         if (p_link->min_pf_rate)
4843                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4844                                                  p_link->min_pf_rate);
4845
4846         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4847                     sizeof(*p_hwfn->qm_info.wfq_data) *
4848                     p_hwfn->qm_info.num_vports);
4849 }
4850
4851 int ecore_device_num_engines(struct ecore_dev *p_dev)
4852 {
4853         return ECORE_IS_BB(p_dev) ? 2 : 1;
4854 }
4855
4856 int ecore_device_num_ports(struct ecore_dev *p_dev)
4857 {
4858         /* in CMT always only one port */
4859         if (p_dev->num_hwfns > 1)
4860                 return 1;
4861
4862         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4863 }
4864
4865 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4866                           __le16 *fw_mid,
4867                           __le16 *fw_lsb,
4868                           u8 *mac)
4869 {
4870         ((u8 *)fw_msb)[0] = mac[1];
4871         ((u8 *)fw_msb)[1] = mac[0];
4872         ((u8 *)fw_mid)[0] = mac[3];
4873         ((u8 *)fw_mid)[1] = mac[2];
4874         ((u8 *)fw_lsb)[0] = mac[5];
4875         ((u8 *)fw_lsb)[1] = mac[4];
4876 }