drivers/net/qede/base/ecore_int.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include <rte_string_fns.h>
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_spq.h"
  12 #include "ecore_gtt_reg_addr.h"
  13 #include "ecore_init_ops.h"
  14 #include "ecore_rt_defs.h"
  15 #include "ecore_int.h"
  16 #include "reg_addr.h"
  17 #include "ecore_hw.h"
  18 #include "ecore_sriov.h"
  19 #include "ecore_vf.h"
  20 #include "ecore_hw_defs.h"
  21 #include "ecore_hsi_common.h"
  22 #include "ecore_mcp.h"
  23
  24 struct ecore_pi_info {
  25         ecore_int_comp_cb_t comp_cb;
  26         void *cookie;           /* Will be sent to the compl cb function */
  27 };
  28
  29 struct ecore_sb_sp_info {
  30         struct ecore_sb_info sb_info;
  31
  32         /* Per protocol index data */
  33         struct ecore_pi_info pi_info_arr[MAX_PIS_PER_SB];
  34         osal_size_t pi_info_arr_size;
  35 };
  36
  37 enum ecore_attention_type {
  38         ECORE_ATTN_TYPE_ATTN,
  39         ECORE_ATTN_TYPE_PARITY,
  40 };
  41
  42 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  43         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  44
  45 struct aeu_invert_reg_bit {
  46         char bit_name[30];
  47
  48 #define ATTENTION_PARITY                (1 << 0)
  49
  50 #define ATTENTION_LENGTH_MASK           (0x00000ff0)
  51 #define ATTENTION_LENGTH_SHIFT          (4)
  52 #define ATTENTION_LENGTH(flags)         (((flags) & ATTENTION_LENGTH_MASK) >> \
  53                                          ATTENTION_LENGTH_SHIFT)
  54 #define ATTENTION_SINGLE                (1 << ATTENTION_LENGTH_SHIFT)
  55 #define ATTENTION_PAR                   (ATTENTION_SINGLE | ATTENTION_PARITY)
  56 #define ATTENTION_PAR_INT               ((2 << ATTENTION_LENGTH_SHIFT) | \
  57                                          ATTENTION_PARITY)
  58
  59 /* Multiple bits start with this offset */
  60 #define ATTENTION_OFFSET_MASK           (0x000ff000)
  61 #define ATTENTION_OFFSET_SHIFT          (12)
  62
  63 #define ATTENTION_BB_MASK               (0xf)
  64 #define ATTENTION_BB_SHIFT              (20)
  65 #define ATTENTION_BB(value)             ((value) << ATTENTION_BB_SHIFT)
  66 #define ATTENTION_BB_DIFFERENT          (1 << 24)
  67
  68 #define ATTENTION_CLEAR_ENABLE          (1 << 28)
  69         unsigned int flags;
  70
  71         /* Callback to call if attention will be triggered */
  72         enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
  73
  74         enum block_id block_index;
  75 };
  76
  77 struct aeu_invert_reg {
  78         struct aeu_invert_reg_bit bits[32];
  79 };
  80
  81 #define MAX_ATTN_GRPS           (8)
  82 #define NUM_ATTN_REGS           (9)
  83
  84 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
  85 {
  86         u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
  87
  88         DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", tmp);
  89         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 0xffffffff);
  90
  91         return ECORE_SUCCESS;
  92 }
  93
  94 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK         (0x3c000)
  95 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT        (14)
  96 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK         (0x03fc0)
  97 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT        (6)
  98 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK      (0x00020)
  99 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT     (5)
 100 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK     (0x0001e)
 101 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT    (1)
 102 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK      (0x1)
 103 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT     (0)
 104 #define ECORE_PSWHST_ATTENTION_VF_DISABLED              (0x1)
 105 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS         (0x1)
 106 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK         (0x1)
 107 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT        (0)
 108 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK     (0x1e)
 109 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT    (1)
 110 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK   (0x20)
 111 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT  (5)
 112 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK      (0x3fc0)
 113 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT     (6)
 114 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK      (0x3c000)
 115 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT     (14)
 116 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK    (0x3fc0000)
 117 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT   (18)
 118 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
 119 {
 120         u32 tmp =
 121             ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 122                      PSWHST_REG_VF_DISABLED_ERROR_VALID);
 123
 124         /* Disabled VF access */
 125         if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
 126                 u32 addr, data;
 127
 128                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 129                                 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
 130                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 131                                 PSWHST_REG_VF_DISABLED_ERROR_DATA);
 132                 DP_INFO(p_hwfn->p_dev,
 133                         "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x]"
 134                         " Write [0x%02x] Addr [0x%08x]\n",
 135                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK)
 136                              >> ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
 137                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK)
 138                              >> ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
 139                         (u8)((data &
 140                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
 141                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
 142                         (u8)((data &
 143                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
 144                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
 145                         (u8)((data &
 146                               ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
 147                               ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
 148                         addr);
 149         }
 150
 151         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 152                        PSWHST_REG_INCORRECT_ACCESS_VALID);
 153         if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
 154                 u32 addr, data, length;
 155
 156                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 157                                 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
 158                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 159                                 PSWHST_REG_INCORRECT_ACCESS_DATA);
 160                 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 161                                   PSWHST_REG_INCORRECT_ACCESS_LENGTH);
 162
 163                 DP_INFO(p_hwfn->p_dev,
 164                         "Incorrect access to %08x of length %08x - PF [%02x]"
 165                         " VF [%04x] [valid %02x] client [%02x] write [%02x]"
 166                         " Byte-Enable [%04x] [%08x]\n",
 167                         addr, length,
 168                         (u8)((data &
 169                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
 170                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
 171                         (u8)((data &
 172                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
 173                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
 174                         (u8)((data &
 175                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
 176                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
 177                         (u8)((data &
 178                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
 179                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
 180                         (u8)((data &
 181                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
 182                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
 183                         (u8)((data &
 184                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
 185                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
 186                         data);
 187         }
 188
 189         /* TODO - We know 'some' of these are legal due to virtualization,
 190          * but is it true for all of them?
 191          */
 192         return ECORE_SUCCESS;
 193 }
 194
 195 #define ECORE_GRC_ATTENTION_VALID_BIT           (1 << 0)
 196 #define ECORE_GRC_ATTENTION_ADDRESS_MASK        (0x7fffff << 0)
 197 #define ECORE_GRC_ATTENTION_RDWR_BIT            (1 << 23)
 198 #define ECORE_GRC_ATTENTION_MASTER_MASK         (0xf << 24)
 199 #define ECORE_GRC_ATTENTION_MASTER_SHIFT        (24)
 200 #define ECORE_GRC_ATTENTION_PF_MASK             (0xf)
 201 #define ECORE_GRC_ATTENTION_VF_MASK             (0xff << 4)
 202 #define ECORE_GRC_ATTENTION_VF_SHIFT            (4)
 203 #define ECORE_GRC_ATTENTION_PRIV_MASK           (0x3 << 14)
 204 #define ECORE_GRC_ATTENTION_PRIV_SHIFT          (14)
 205 #define ECORE_GRC_ATTENTION_PRIV_VF             (0)
 206 static const char *grc_timeout_attn_master_to_str(u8 master)
 207 {
 208         switch (master) {
 209         case 1:
 210                 return "PXP";
 211         case 2:
 212                 return "MCP";
 213         case 3:
 214                 return "MSDM";
 215         case 4:
 216                 return "PSDM";
 217         case 5:
 218                 return "YSDM";
 219         case 6:
 220                 return "USDM";
 221         case 7:
 222                 return "TSDM";
 223         case 8:
 224                 return "XSDM";
 225         case 9:
 226                 return "DBU";
 227         case 10:
 228                 return "DMAE";
 229         default:
 230                 return "Unknown";
 231         }
 232 }
 233
 234 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
 235 {
 236         enum _ecore_status_t rc = ECORE_SUCCESS;
 237         u32 tmp, tmp2;
 238
 239         /* We've already cleared the timeout interrupt register, so we learn
 240          * of interrupts via the validity register.
 241          * Any attention which is not for a timeout event is treated as fatal.
 242          */
 243         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 244                        GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
 245         if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT)) {
 246                 rc = ECORE_INVAL;
 247                 goto out;
 248         }
 249
 250         /* Read the GRC timeout information */
 251         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 252                        GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
 253         tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 254                         GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
 255
 256         DP_NOTICE(p_hwfn->p_dev, false,
 257                   "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
 258                   tmp2, tmp,
 259                   (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to"
 260                                                        : "Read from",
 261                   (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
 262                   grc_timeout_attn_master_to_str(
 263                         (tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >>
 264                          ECORE_GRC_ATTENTION_MASTER_SHIFT),
 265                   (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
 266                   (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
 267                   ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
 268                   ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
 269                   (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
 270                   ECORE_GRC_ATTENTION_VF_SHIFT);
 271
 272         /* Clean the validity bit */
 273         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 274                  GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
 275 out:
 276         return rc;
 277 }
 278
 279 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
 280 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
 281 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
 282 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
 283 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
 284 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
 285 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
 286 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
 287 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME      (1 << 22)
 288 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
 289 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
 290 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
 291 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
 292
 293 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
 294                                                    struct ecore_ptt *p_ptt,
 295                                                    bool is_hw_init)
 296 {
 297         u32 tmp;
 298         char str[512] = {0};
 299
 300         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
 301         if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
 302                 u32 addr_lo, addr_hi, details;
 303
 304                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 305                                    PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
 306                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 307                                    PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
 308                 details = ecore_rd(p_hwfn, p_ptt,
 309                                    PGLUE_B_REG_TX_ERR_WR_DETAILS);
 310                 OSAL_SNPRINTF(str, 512,
 311                          "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 312                           addr_hi, addr_lo, details,
 313                           (u8)((details &
 314                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 315                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 316                           (u8)((details &
 317                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 318                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 319                           (u8)((details &
 320                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 321                           tmp,
 322                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 323                                 1 : 0),
 324                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 325                                 1 : 0),
 326                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 327                                 1 : 0));
 328                 if (is_hw_init)
 329                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "%s", str);
 330                 else
 331                         DP_NOTICE(p_hwfn, false, "%s", str);
 332         }
 333
 334         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
 335         if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
 336                 u32 addr_lo, addr_hi, details;
 337
 338                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 339                                    PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
 340                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 341                                    PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
 342                 details = ecore_rd(p_hwfn, p_ptt,
 343                                    PGLUE_B_REG_TX_ERR_RD_DETAILS);
 344
 345                 DP_NOTICE(p_hwfn, false,
 346                           "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 347                           addr_hi, addr_lo, details,
 348                           (u8)((details &
 349                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 350                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 351                           (u8)((details &
 352                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 353                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 354                           (u8)((details &
 355                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 356                           tmp,
 357                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 358                                 1 : 0),
 359                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 360                                 1 : 0),
 361                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 362                                 1 : 0));
 363         }
 364
 365         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
 366         if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
 367                 DP_NOTICE(p_hwfn, false, "ICPL erorr - %08x\n", tmp);
 368
 369         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
 370         if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
 371                 u32 addr_hi, addr_lo;
 372
 373                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 374                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
 375                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 376                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
 377
 378                 DP_NOTICE(p_hwfn, false,
 379                           "ICPL erorr - %08x [Address %08x:%08x]\n",
 380                           tmp, addr_hi, addr_lo);
 381         }
 382
 383         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
 384         if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
 385                 u32 addr_hi, addr_lo, details;
 386
 387                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 388                                    PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
 389                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 390                                    PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
 391                 details = ecore_rd(p_hwfn, p_ptt,
 392                                    PGLUE_B_REG_VF_ILT_ERR_DETAILS);
 393
 394                 DP_NOTICE(p_hwfn, false,
 395                           "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
 396                           details, tmp, addr_hi, addr_lo);
 397         }
 398
 399         /* Clear the indications */
 400         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
 401
 402         return ECORE_SUCCESS;
 403 }
 404
 405 static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
 406 {
 407         return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false);
 408 }
 409
 410 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
 411 {
 412         DP_NOTICE(p_hwfn, false, "FW assertion!\n");
 413
 414         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
 415
 416         return ECORE_INVAL;
 417 }
 418
 419 static enum _ecore_status_t
 420 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
 421 {
 422         DP_INFO(p_hwfn, "General attention 35!\n");
 423
 424         return ECORE_SUCCESS;
 425 }
 426
 427 #define ECORE_DORQ_ATTENTION_REASON_MASK        (0xfffff)
 428 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK        (0xffff)
 429 #define ECORE_DORQ_ATTENTION_OPAQUE_SHIFT       (0x0)
 430 #define ECORE_DORQ_ATTENTION_SIZE_MASK          (0x7f)
 431 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT         (16)
 432
 433 #define ECORE_DB_REC_COUNT                      1000
 434 #define ECORE_DB_REC_INTERVAL                   100
 435
 436 static enum _ecore_status_t ecore_db_rec_flush_queue(struct ecore_hwfn *p_hwfn,
 437                                                      struct ecore_ptt *p_ptt)
 438 {
 439         u32 count = ECORE_DB_REC_COUNT;
 440         u32 usage = 1;
 441
 442         /* wait for usage to zero or count to run out. This is necessary since
 443          * EDPM doorbell transactions can take multiple 64b cycles, and as such
 444          * can "split" over the pci. Possibly, the doorbell drop can happen with
 445          * half an EDPM in the queue and other half dropped. Another EDPM
 446          * doorbell to the same address (from doorbell recovery mechanism or
 447          * from the doorbelling entity) could have first half dropped and second
 448          * half interperted as continuation of the first. To prevent such
 449          * malformed doorbells from reaching the device, flush the queue before
 450          * releaseing the overflow sticky indication.
 451          */
 452         while (count-- && usage) {
 453                 usage = ecore_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
 454                 OSAL_UDELAY(ECORE_DB_REC_INTERVAL);
 455         }
 456
 457         /* should have been depleted by now */
 458         if (usage) {
 459                 DP_NOTICE(p_hwfn->p_dev, false,
 460                           "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n",
 461                           ECORE_DB_REC_INTERVAL * ECORE_DB_REC_COUNT, usage);
 462                 return ECORE_TIMEOUT;
 463         }
 464
 465         return ECORE_SUCCESS;
 466 }
 467
 468 enum _ecore_status_t ecore_db_rec_handler(struct ecore_hwfn *p_hwfn,
 469                                           struct ecore_ptt *p_ptt)
 470 {
 471         u32 overflow;
 472         enum _ecore_status_t rc;
 473
 474         overflow = ecore_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY);
 475         DP_NOTICE(p_hwfn, false, "PF Overflow sticky 0x%x\n", overflow);
 476         if (!overflow) {
 477                 ecore_db_recovery_execute(p_hwfn, DB_REC_ONCE);
 478                 return ECORE_SUCCESS;
 479         }
 480
 481         if (ecore_edpm_enabled(p_hwfn)) {
 482                 rc = ecore_db_rec_flush_queue(p_hwfn, p_ptt);
 483                 if (rc != ECORE_SUCCESS)
 484                         return rc;
 485         }
 486
 487         /* flush any pedning (e)dpm as they may never arrive */
 488         ecore_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1);
 489
 490         /* release overflow sticky indication (stop silently dropping
 491          * everything)
 492          */
 493         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
 494
 495         /* repeat all last doorbells (doorbell drop recovery) */
 496         ecore_db_recovery_execute(p_hwfn, DB_REC_REAL_DEAL);
 497
 498         return ECORE_SUCCESS;
 499 }
 500
 501 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
 502 {
 503         u32 int_sts, first_drop_reason, details, address, all_drops_reason;
 504         struct ecore_ptt *p_ptt = p_hwfn->p_dpc_ptt;
 505         enum _ecore_status_t rc;
 506
 507         int_sts = ecore_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
 508         DP_NOTICE(p_hwfn->p_dev, false, "DORQ attention. int_sts was %x\n",
 509                   int_sts);
 510
 511         /* int_sts may be zero since all PFs were interrupted for doorbell
 512          * overflow but another one already handled it. Can abort here. If
 513          * This PF also requires overflow recovery we will be interrupted again
 514          */
 515         if (!int_sts)
 516                 return ECORE_SUCCESS;
 517
 518         /* check if db_drop or overflow happened */
 519         if (int_sts & (DORQ_REG_INT_STS_DB_DROP |
 520                        DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) {
 521                 /* obtain data about db drop/overflow */
 522                 first_drop_reason = ecore_rd(p_hwfn, p_ptt,
 523                                   DORQ_REG_DB_DROP_REASON) &
 524                                   ECORE_DORQ_ATTENTION_REASON_MASK;
 525                 details = ecore_rd(p_hwfn, p_ptt,
 526                                    DORQ_REG_DB_DROP_DETAILS);
 527                 address = ecore_rd(p_hwfn, p_ptt,
 528                                    DORQ_REG_DB_DROP_DETAILS_ADDRESS);
 529                 all_drops_reason = ecore_rd(p_hwfn, p_ptt,
 530                                             DORQ_REG_DB_DROP_DETAILS_REASON);
 531
 532                 /* log info */
 533                 DP_NOTICE(p_hwfn->p_dev, false,
 534                           "Doorbell drop occurred\n"
 535                           "Address\t\t0x%08x\t(second BAR address)\n"
 536                           "FID\t\t0x%04x\t\t(Opaque FID)\n"
 537                           "Size\t\t0x%04x\t\t(in bytes)\n"
 538                           "1st drop reason\t0x%08x\t(details on first drop since last handling)\n"
 539                           "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n",
 540                           address,
 541                           GET_FIELD(details, ECORE_DORQ_ATTENTION_OPAQUE),
 542                           GET_FIELD(details, ECORE_DORQ_ATTENTION_SIZE) * 4,
 543                           first_drop_reason, all_drops_reason);
 544
 545                 rc = ecore_db_rec_handler(p_hwfn, p_ptt);
 546                 OSAL_DB_REC_OCCURRED(p_hwfn);
 547                 if (rc != ECORE_SUCCESS)
 548                         return rc;
 549
 550                 /* clear the doorbell drop details and prepare for next drop */
 551                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0);
 552
 553                 /* mark interrupt as handeld (note: even if drop was due to a
 554                  * different reason than overflow we mark as handled)
 555                  */
 556                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_INT_STS_WR,
 557                          DORQ_REG_INT_STS_DB_DROP |
 558                          DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR);
 559
 560                 /* if there are no indications otherthan drop indications,
 561                  * success
 562                  */
 563                 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP |
 564                                  DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR |
 565                                  DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0)
 566                         return ECORE_SUCCESS;
 567         }
 568
 569         /* some other indication was present - non recoverable */
 570         DP_INFO(p_hwfn, "DORQ fatal attention\n");
 571
 572         return ECORE_INVAL;
 573 }
 574
 575 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
 576 {
 577 #ifndef ASIC_ONLY
 578         if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
 579                 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 580                                    TM_REG_INT_STS_1);
 581
 582                 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
 583                             TM_REG_INT_STS_1_PEND_CONN_SCAN))
 584                         return ECORE_INVAL;
 585
 586                 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
 587                            TM_REG_INT_STS_1_PEND_CONN_SCAN))
 588                         DP_INFO(p_hwfn,
 589                                 "TM attention on emulation - most likely"
 590                                 " results of clock-ratios\n");
 591                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
 592                 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
 593                     TM_REG_INT_MASK_1_PEND_TASK_SCAN;
 594                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
 595
 596                 return ECORE_SUCCESS;
 597         }
 598 #endif
 599
 600         return ECORE_INVAL;
 601 }
 602
 603 /* Instead of major changes to the data-structure, we have a some 'special'
 604  * identifiers for sources that changed meaning between adapters.
 605  */
 606 enum aeu_invert_reg_special_type {
 607         AEU_INVERT_REG_SPECIAL_CNIG_0,
 608         AEU_INVERT_REG_SPECIAL_CNIG_1,
 609         AEU_INVERT_REG_SPECIAL_CNIG_2,
 610         AEU_INVERT_REG_SPECIAL_CNIG_3,
 611         AEU_INVERT_REG_SPECIAL_MCP_UMP_TX,
 612         AEU_INVERT_REG_SPECIAL_MCP_SCPAD,
 613         AEU_INVERT_REG_SPECIAL_MAX,
 614 };
 615
 616 static struct aeu_invert_reg_bit
 617 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
 618         {"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 619         {"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 620         {"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 621         {"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 622         {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 623         {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 624 };
 625
 626 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
 627 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
 628         {
 629          {                      /* After Invert 1 */
 630           {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 631            MAX_BLOCK_ID},
 632           }
 633          },
 634
 635         {
 636          {                      /* After Invert 2 */
 637           {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 638           {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 639           {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglueb_rbc_attn_cb,
 640            BLOCK_PGLUE_B},
 641           {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 642           {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 643           {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 644           {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 645           {"SW timers #%d",
 646            (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT),
 647            OSAL_NULL, MAX_BLOCK_ID},
 648           {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 649            BLOCK_PGLCS},
 650           }
 651          },
 652
 653         {
 654          {                      /* After Invert 3 */
 655           {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 656            MAX_BLOCK_ID},
 657           }
 658          },
 659
 660         {
 661          {                      /* After Invert 4 */
 662           {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 663            ecore_fw_assertion, MAX_BLOCK_ID},
 664           {"General Attention %d",
 665            (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT),
 666            OSAL_NULL, MAX_BLOCK_ID},
 667           {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 668            ecore_general_attention_35, MAX_BLOCK_ID},
 669           {"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 670                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
 671                          OSAL_NULL, BLOCK_NWS},
 672           {"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 673                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
 674                             OSAL_NULL, BLOCK_NWS},
 675           {"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 676                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
 677                          OSAL_NULL, BLOCK_NWM},
 678           {"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 679                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
 680                             OSAL_NULL, BLOCK_NWM},
 681           {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
 682           {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 683           {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 684           {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 685           {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 686           {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 687                         {"OPTE", ATTENTION_PAR, OSAL_NULL, BLOCK_OPTE},
 688                         {"MCP", ATTENTION_PAR, OSAL_NULL, BLOCK_MCP},
 689                         {"MS", ATTENTION_SINGLE, OSAL_NULL, BLOCK_MS},
 690                         {"UMAC", ATTENTION_SINGLE, OSAL_NULL, BLOCK_UMAC},
 691                         {"LED", ATTENTION_SINGLE, OSAL_NULL, BLOCK_LED},
 692                         {"BMBN", ATTENTION_SINGLE, OSAL_NULL, BLOCK_BMBN},
 693           {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
 694           {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
 695                         {"BMB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
 696           {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
 697           {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
 698           {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
 699           }
 700          },
 701
 702         {
 703          {                      /* After Invert 5 */
 704           {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
 705           {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
 706           {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
 707           {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
 708           {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
 709           {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
 710           {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
 711           {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
 712           {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
 713           {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
 714           {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
 715           {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
 716           {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
 717           {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
 718           {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
 719           {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM},
 720           }
 721          },
 722
 723         {
 724          {                      /* After Invert 6 */
 725           {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
 726           {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
 727           {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
 728           {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
 729           {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
 730           {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
 731           {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
 732           {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
 733           {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
 734           {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
 735           {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
 736           {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
 737           {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
 738           {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
 739           {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
 740           {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
 741           }
 742          },
 743
 744         {
 745          {                      /* After Invert 7 */
 746           {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
 747           {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
 748           {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
 749           {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
 750           {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 751           {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
 752           {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
 753           {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
 754           {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
 755           {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
 756           {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
 757           {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
 758           {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
 759           {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
 760           {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
 761           {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 762           {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
 763           }
 764          },
 765
 766         {
 767          {                      /* After Invert 8 */
 768           {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
 769           {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
 770           {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
 771           {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
 772           {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
 773           {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
 774           {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
 775           {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
 776           {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
 777           {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
 778           {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 779           {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 780           {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 781           {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 782           {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 783           {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 784           {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
 785           {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 786           {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 787           {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 788           {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 789            MAX_BLOCK_ID},
 790           }
 791          },
 792
 793         {
 794          {                      /* After Invert 9 */
 795           {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 796           {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL,
 797            MAX_BLOCK_ID},
 798           {"AVS", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 799            ATTENTION_BB(AEU_INVERT_REG_SPECIAL_MCP_UMP_TX), OSAL_NULL,
 800            BLOCK_AVS_WRAP},
 801           {"AVS", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 802            ATTENTION_BB(AEU_INVERT_REG_SPECIAL_MCP_SCPAD), OSAL_NULL,
 803            BLOCK_AVS_WRAP},
 804           {"PCIe core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 805           {"PCIe link up", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 806           {"PCIe hot reset", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 807           {"Reserved %d", (9 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 808             MAX_BLOCK_ID},
 809           }
 810          },
 811
 812 };
 813
 814 static struct aeu_invert_reg_bit *
 815 ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
 816                         struct aeu_invert_reg_bit *p_bit)
 817 {
 818         if (!ECORE_IS_BB(p_hwfn->p_dev))
 819                 return p_bit;
 820
 821         if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
 822                 return p_bit;
 823
 824         return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
 825                                   ATTENTION_BB_SHIFT];
 826 }
 827
 828 static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
 829                                      struct aeu_invert_reg_bit *p_bit)
 830 {
 831         return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
 832                   ATTENTION_PARITY);
 833 }
 834
 835 #define ATTN_STATE_BITS         (0xfff)
 836 #define ATTN_BITS_MASKABLE      (0x3ff)
 837 struct ecore_sb_attn_info {
 838         /* Virtual & Physical address of the SB */
 839         struct atten_status_block *sb_attn;
 840         dma_addr_t sb_phys;
 841
 842         /* Last seen running index */
 843         u16 index;
 844
 845         /* A mask of the AEU bits resulting in a parity error */
 846         u32 parity_mask[NUM_ATTN_REGS];
 847
 848         /* A pointer to the attention description structure */
 849         struct aeu_invert_reg *p_aeu_desc;
 850
 851         /* Previously asserted attentions, which are still unasserted */
 852         u16 known_attn;
 853
 854         /* Cleanup address for the link's general hw attention */
 855         u32 mfw_attn_addr;
 856 };
 857
 858 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
 859                                  struct ecore_sb_attn_info *p_sb_desc)
 860 {
 861         u16 rc = 0, index;
 862
 863         OSAL_MMIOWB(p_hwfn->p_dev);
 864
 865         index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
 866         if (p_sb_desc->index != index) {
 867                 p_sb_desc->index = index;
 868                 rc = ECORE_SB_ATT_IDX;
 869         }
 870
 871         OSAL_MMIOWB(p_hwfn->p_dev);
 872
 873         return rc;
 874 }
 875
 876 /**
 877  * @brief ecore_int_assertion - handles asserted attention bits
 878  *
 879  * @param p_hwfn
 880  * @param asserted_bits newly asserted bits
 881  * @return enum _ecore_status_t
 882  */
 883 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
 884                                                 u16 asserted_bits)
 885 {
 886         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 887         u32 igu_mask;
 888
 889         /* Mask the source of the attention in the IGU */
 890         igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 891                             IGU_REG_ATTENTION_ENABLE);
 892         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 893                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 894         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 895         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 896
 897         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 898                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 899                    sb_attn_sw->known_attn,
 900                    sb_attn_sw->known_attn | asserted_bits);
 901         sb_attn_sw->known_attn |= asserted_bits;
 902
 903         /* Handle MCP events */
 904         if (asserted_bits & 0x100) {
 905                 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 906                 /* Clean the MCP attention */
 907                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 908                          sb_attn_sw->mfw_attn_addr, 0);
 909         }
 910
 911         /* FIXME - this will change once we'll have GOOD gtt definitions */
 912         DIRECT_REG_WR(p_hwfn,
 913                       (u8 OSAL_IOMEM *) p_hwfn->regview +
 914                       GTT_BAR0_MAP_REG_IGU_CMD +
 915                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 916                         IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
 917
 918         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
 919                    asserted_bits);
 920
 921         return ECORE_SUCCESS;
 922 }
 923
 924 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
 925                                  enum block_id id, enum dbg_attn_type type,
 926                                  bool b_clear)
 927 {
 928         /* @DPDK */
 929         DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n", id, type);
 930 }
 931
 932 /**
 933  * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
 934  * cause of the attention
 935  *
 936  * @param p_hwfn
 937  * @param p_aeu - descriptor of an AEU bit which caused the attention
 938  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
 939  *  this bit to this group.
 940  * @param bit_index - index of this bit in the aeu_en_reg
 941  *
 942  * @return enum _ecore_status_t
 943  */
 944 static enum _ecore_status_t
 945 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
 946                               struct aeu_invert_reg_bit *p_aeu,
 947                               u32 aeu_en_reg,
 948                               const char *p_bit_name,
 949                               u32 bitmask)
 950 {
 951         enum _ecore_status_t rc = ECORE_INVAL;
 952         bool b_fatal = false;
 953
 954         DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
 955                 p_bit_name, bitmask);
 956
 957         /* Call callback before clearing the interrupt status */
 958         if (p_aeu->cb) {
 959                 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
 960                         p_bit_name);
 961                 rc = p_aeu->cb(p_hwfn);
 962         }
 963
 964         if (rc != ECORE_SUCCESS)
 965                 b_fatal = true;
 966
 967         /* Print HW block interrupt registers */
 968         if (p_aeu->block_index != MAX_BLOCK_ID) {
 969                 ecore_int_attn_print(p_hwfn, p_aeu->block_index,
 970                                      ATTN_TYPE_INTERRUPT, !b_fatal);
 971 }
 972
 973         /* @DPDK */
 974         /* Reach assertion if attention is fatal */
 975         if (b_fatal || (strcmp(p_bit_name, "PGLUE B RBC") == 0)) {
 976 #ifndef ASIC_ONLY
 977                 DP_NOTICE(p_hwfn, !CHIP_REV_IS_EMUL(p_hwfn->p_dev),
 978                           "`%s': Fatal attention\n", p_bit_name);
 979 #else
 980                 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
 981                           p_bit_name);
 982 #endif
 983
 984                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
 985         }
 986
 987         /* Prevent this Attention from being asserted in the future */
 988         if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
 989 #ifndef ASIC_ONLY
 990             CHIP_REV_IS_EMUL(p_hwfn->p_dev) ||
 991 #endif
 992             p_hwfn->p_dev->attn_clr_en) {
 993                 u32 val;
 994                 u32 mask = ~bitmask;
 995                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 996                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
 997                 DP_ERR(p_hwfn, "`%s' - Disabled future attentions\n",
 998                         p_bit_name);
 999         }
1000
1001         return rc;
1002 }
1003
1004 /**
1005  * @brief ecore_int_deassertion_parity - handle a single parity AEU source
1006  *
1007  * @param p_hwfn
1008  * @param p_aeu - descriptor of an AEU bit which caused the parity
1009  * @param aeu_en_reg - address of the AEU enable register
1010  * @param bit_index
1011  */
1012 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
1013                                          struct aeu_invert_reg_bit *p_aeu,
1014                                          u32 aeu_en_reg, u8 bit_index)
1015 {
1016         u32 block_id = p_aeu->block_index, mask, val;
1017
1018         DP_NOTICE(p_hwfn->p_dev, false,
1019                   "%s parity attention is set [address 0x%08x, bit %d]\n",
1020                   p_aeu->bit_name, aeu_en_reg, bit_index);
1021
1022         if (block_id != MAX_BLOCK_ID) {
1023                 ecore_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
1024
1025                 /* In A0, there's a single parity bit for several blocks */
1026                 if (block_id == BLOCK_BTB) {
1027                         ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
1028                                              ATTN_TYPE_PARITY, false);
1029                         ecore_int_attn_print(p_hwfn, BLOCK_MCP,
1030                                              ATTN_TYPE_PARITY, false);
1031                 }
1032         }
1033
1034         /* Prevent this parity error from being re-asserted */
1035         mask = ~(0x1 << bit_index);
1036         val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
1037         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
1038         DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
1039                 p_aeu->bit_name);
1040 }
1041
1042 #define MISC_REG_AEU_AFTER_INVERT_IGU(n) \
1043         (MISC_REG_AEU_AFTER_INVERT_1_IGU + (n) * 0x4)
1044
1045 #define MISC_REG_AEU_ENABLE_IGU_OUT(n, group) \
1046         (MISC_REG_AEU_ENABLE1_IGU_OUT_0 + (n) * 0x4 + \
1047          (group) * 0x4 * NUM_ATTN_REGS)
1048
1049 /**
1050  * @brief - handles deassertion of previously asserted attentions.
1051  *
1052  * @param p_hwfn
1053  * @param deasserted_bits - newly deasserted bits
1054  * @return enum _ecore_status_t
1055  *
1056  */
1057 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
1058                                                   u16 deasserted_bits)
1059 {
1060         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1061         u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
1062         u8 i, j, k, bit_idx;
1063         enum _ecore_status_t rc = ECORE_SUCCESS;
1064
1065         /* Read the attention registers in the AEU */
1066         for (i = 0; i < NUM_ATTN_REGS; i++) {
1067                 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1068                                           MISC_REG_AEU_AFTER_INVERT_IGU(i));
1069                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1070                            "Deasserted bits [%d]: %08x\n", i, aeu_inv_arr[i]);
1071         }
1072
1073         /* Handle parity attentions first */
1074         for (i = 0; i < NUM_ATTN_REGS; i++) {
1075                 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
1076                 u32 parities;
1077
1078                 aeu_en = MISC_REG_AEU_ENABLE_IGU_OUT(i, 0);
1079                 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1080                 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
1081
1082                 /* Skip register in which no parity bit is currently set */
1083                 if (!parities)
1084                         continue;
1085
1086                 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1087                         struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
1088
1089                         if (ecore_int_is_parity_flag(p_hwfn, p_bit) &&
1090                             !!(parities & (1 << bit_idx)))
1091                                 ecore_int_deassertion_parity(p_hwfn, p_bit,
1092                                                              aeu_en, bit_idx);
1093
1094                         bit_idx += ATTENTION_LENGTH(p_bit->flags);
1095                 }
1096         }
1097
1098         /* Find non-parity cause for attention and act */
1099         for (k = 0; k < MAX_ATTN_GRPS; k++) {
1100                 struct aeu_invert_reg_bit *p_aeu;
1101
1102                 /* Handle only groups whose attention is currently deasserted */
1103                 if (!(deasserted_bits & (1 << k)))
1104                         continue;
1105
1106                 for (i = 0; i < NUM_ATTN_REGS; i++) {
1107                         u32 bits;
1108
1109                         aeu_en = MISC_REG_AEU_ENABLE_IGU_OUT(i, k);
1110                         en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1111                         bits = aeu_inv_arr[i] & en;
1112
1113                         /* Skip if no bit from this group is currently set */
1114                         if (!bits)
1115                                 continue;
1116
1117                         /* Find all set bits from current register which belong
1118                          * to current group, making them responsible for the
1119                          * previous assertion.
1120                          */
1121                         for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1122                                 unsigned long int bitmask;
1123                                 u8 bit, bit_len;
1124
1125                                 /* Need to account bits with changed meaning */
1126                                 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1127
1128                                 bit = bit_idx;
1129                                 bit_len = ATTENTION_LENGTH(p_aeu->flags);
1130                                 if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) {
1131                                         /* Skip Parity */
1132                                         bit++;
1133                                         bit_len--;
1134                                 }
1135
1136                                 /* Find the bits relating to HW-block, then
1137                                  * shift so they'll become LSB.
1138                                  */
1139                                 bitmask = bits & (((1 << bit_len) - 1) << bit);
1140                                 bitmask >>= bit;
1141
1142                                 if (bitmask) {
1143                                         u32 flags = p_aeu->flags;
1144                                         char bit_name[30];
1145                                         u8 num;
1146
1147                                         num = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
1148                                                                 bit_len);
1149
1150                                         /* Some bits represent more than a
1151                                          * a single interrupt. Correctly print
1152                                          * their name.
1153                                          */
1154                                         if (ATTENTION_LENGTH(flags) > 2 ||
1155                                             ((flags & ATTENTION_PAR_INT) &&
1156                                             ATTENTION_LENGTH(flags) > 1))
1157                                                 OSAL_SNPRINTF(bit_name, 30,
1158                                                               p_aeu->bit_name,
1159                                                               num);
1160                                         else
1161                                                 strlcpy(bit_name,
1162                                                         p_aeu->bit_name,
1163                                                         sizeof(bit_name));
1164
1165                                         /* We now need to pass bitmask in its
1166                                          * correct position.
1167                                          */
1168                                         bitmask <<= bit;
1169
1170                                         /* Handle source of the attention */
1171                                         ecore_int_deassertion_aeu_bit(p_hwfn,
1172                                                                       p_aeu,
1173                                                                       aeu_en,
1174                                                                       bit_name,
1175                                                                       bitmask);
1176                                 }
1177
1178                                 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1179                         }
1180                 }
1181         }
1182
1183         /* Clear IGU indication for the deasserted bits */
1184         /* FIXME - this will change once we'll have GOOD gtt definitions */
1185         DIRECT_REG_WR(p_hwfn,
1186                       (u8 OSAL_IOMEM *) p_hwfn->regview +
1187                       GTT_BAR0_MAP_REG_IGU_CMD +
1188                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1189                         IGU_CMD_INT_ACK_BASE) << 3), ~((u32)deasserted_bits));
1190
1191         /* Unmask deasserted attentions in IGU */
1192         aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1193                             IGU_REG_ATTENTION_ENABLE);
1194         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1195         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1196
1197         /* Clear deassertion from inner state */
1198         sb_attn_sw->known_attn &= ~deasserted_bits;
1199
1200         return rc;
1201 }
1202
1203 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
1204 {
1205         struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1206         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1207         u16 index = 0, asserted_bits, deasserted_bits;
1208         u32 attn_bits = 0, attn_acks = 0;
1209         enum _ecore_status_t rc = ECORE_SUCCESS;
1210
1211         /* Read current attention bits/acks - safeguard against attentions
1212          * by guaranting work on a synchronized timeframe
1213          */
1214         do {
1215                 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1216                 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1217                 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1218         } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1219         p_sb_attn->sb_index = index;
1220
1221         /* Attention / Deassertion are meaningful (and in correct state)
1222          * only when they differ and consistent with known state - deassertion
1223          * when previous attention & current ack, and assertion when current
1224          * attention with no previous attention
1225          */
1226         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1227             ~p_sb_attn_sw->known_attn;
1228         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1229             p_sb_attn_sw->known_attn;
1230
1231         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1232                 DP_INFO(p_hwfn,
1233                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1234                         index, attn_bits, attn_acks, asserted_bits,
1235                         deasserted_bits, p_sb_attn_sw->known_attn);
1236         else if (asserted_bits == 0x100)
1237                 DP_INFO(p_hwfn, "MFW indication via attention\n");
1238         else
1239                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1240                            "MFW indication [deassertion]\n");
1241
1242         if (asserted_bits) {
1243                 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1244                 if (rc)
1245                         return rc;
1246         }
1247
1248         if (deasserted_bits)
1249                 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1250
1251         return rc;
1252 }
1253
1254 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1255                               void OSAL_IOMEM *igu_addr, u32 ack_cons)
1256 {
1257         struct igu_prod_cons_update igu_ack;
1258
1259         OSAL_MEMSET(&igu_ack, 0, sizeof(struct igu_prod_cons_update));
1260         igu_ack.sb_id_and_flags =
1261             ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1262              (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1263              (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1264              (IGU_SEG_ACCESS_ATTN <<
1265               IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1266
1267         DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1268
1269         /* Both segments (interrupts & acks) are written to same place address;
1270          * Need to guarantee all commands will be received (in-order) by HW.
1271          */
1272         OSAL_MMIOWB(p_hwfn->p_dev);
1273         OSAL_BARRIER(p_hwfn->p_dev);
1274 }
1275
1276 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1277 {
1278         struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1279         struct ecore_pi_info *pi_info = OSAL_NULL;
1280         struct ecore_sb_attn_info *sb_attn;
1281         struct ecore_sb_info *sb_info;
1282         u16 rc = 0;
1283
1284         if (!p_hwfn)
1285                 return;
1286
1287         if (!p_hwfn->p_sp_sb) {
1288                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1289                 return;
1290         }
1291
1292         sb_info = &p_hwfn->p_sp_sb->sb_info;
1293         if (!sb_info) {
1294                 DP_ERR(p_hwfn->p_dev,
1295                        "Status block is NULL - cannot ack interrupts\n");
1296                 return;
1297         }
1298
1299         if (!p_hwfn->p_sb_attn) {
1300                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1301                 return;
1302         }
1303         sb_attn = p_hwfn->p_sb_attn;
1304
1305         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1306                    p_hwfn, p_hwfn->my_id);
1307
1308         /* Disable ack for def status block. Required both for msix +
1309          * inta in non-mask mode, in inta does no harm.
1310          */
1311         ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1312
1313         /* Gather Interrupts/Attentions information */
1314         if (!sb_info->sb_virt) {
1315                 DP_ERR(p_hwfn->p_dev,
1316                        "Interrupt Status block is NULL -"
1317                        " cannot check for new interrupts!\n");
1318         } else {
1319                 u32 tmp_index = sb_info->sb_ack;
1320                 rc = ecore_sb_update_sb_idx(sb_info);
1321                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1322                            "Interrupt indices: 0x%08x --> 0x%08x\n",
1323                            tmp_index, sb_info->sb_ack);
1324         }
1325
1326         if (!sb_attn || !sb_attn->sb_attn) {
1327                 DP_ERR(p_hwfn->p_dev,
1328                        "Attentions Status block is NULL -"
1329                        " cannot check for new attentions!\n");
1330         } else {
1331                 u16 tmp_index = sb_attn->index;
1332
1333                 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1334                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1335                            "Attention indices: 0x%08x --> 0x%08x\n",
1336                            tmp_index, sb_attn->index);
1337         }
1338
1339         /* Check if we expect interrupts at this time. if not just ack them */
1340         if (!(rc & ECORE_SB_EVENT_MASK)) {
1341                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1342                 return;
1343         }
1344
1345 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1346
1347         if (!p_hwfn->p_dpc_ptt) {
1348                 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1349                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1350                 return;
1351         }
1352
1353         if (rc & ECORE_SB_ATT_IDX)
1354                 ecore_int_attentions(p_hwfn);
1355
1356         if (rc & ECORE_SB_IDX) {
1357                 osal_size_t pi;
1358
1359                 /* Since we only looked at the SB index, it's possible more
1360                  * than a single protocol-index on the SB incremented.
1361                  * Iterate over all configured protocol indices and check
1362                  * whether something happened for each.
1363                  */
1364                 for (pi = 0; pi < p_hwfn->p_sp_sb->pi_info_arr_size; pi++) {
1365                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1366                         if (pi_info->comp_cb != OSAL_NULL)
1367                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1368                 }
1369         }
1370
1371         if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1372                 /* This should be done before the interrupts are enabled,
1373                  * since otherwise a new attention will be generated.
1374                  */
1375                 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1376         }
1377
1378         ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1379 }
1380
1381 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1382 {
1383         struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1384
1385         if (!p_sb)
1386                 return;
1387
1388         if (p_sb->sb_attn) {
1389                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1390                                        p_sb->sb_phys,
1391                                        SB_ATTN_ALIGNED_SIZE(p_hwfn));
1392         }
1393         OSAL_FREE(p_hwfn->p_dev, p_sb);
1394 }
1395
1396 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1397                                     struct ecore_ptt *p_ptt)
1398 {
1399         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1400
1401         OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1402
1403         sb_info->index = 0;
1404         sb_info->known_attn = 0;
1405
1406         /* Configure Attention Status Block in IGU */
1407         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1408                  DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1409         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1410                  DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1411 }
1412
1413 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1414                                    struct ecore_ptt *p_ptt,
1415                                    void *sb_virt_addr, dma_addr_t sb_phy_addr)
1416 {
1417         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1418         int i, j, k;
1419
1420         sb_info->sb_attn = sb_virt_addr;
1421         sb_info->sb_phys = sb_phy_addr;
1422
1423         /* Set the pointer to the AEU descriptors */
1424         sb_info->p_aeu_desc = aeu_descs;
1425
1426         /* Calculate Parity Masks */
1427         OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1428         for (i = 0; i < NUM_ATTN_REGS; i++) {
1429                 /* j is array index, k is bit index */
1430                 for (j = 0, k = 0; k < 32; j++) {
1431                         struct aeu_invert_reg_bit *p_aeu;
1432
1433                         p_aeu = &aeu_descs[i].bits[j];
1434                         if (ecore_int_is_parity_flag(p_hwfn, p_aeu))
1435                                 sb_info->parity_mask[i] |= 1 << k;
1436
1437                         k += ATTENTION_LENGTH(p_aeu->flags);
1438                 }
1439                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1440                            "Attn Mask [Reg %d]: 0x%08x\n",
1441                            i, sb_info->parity_mask[i]);
1442         }
1443
1444         /* Set the address of cleanup for the mcp attention */
1445         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1446             MISC_REG_AEU_GENERAL_ATTN_0;
1447
1448         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1449 }
1450
1451 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1452                                                     struct ecore_ptt *p_ptt)
1453 {
1454         struct ecore_dev *p_dev = p_hwfn->p_dev;
1455         struct ecore_sb_attn_info *p_sb;
1456         dma_addr_t p_phys = 0;
1457         void *p_virt;
1458
1459         /* SB struct */
1460         p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1461         if (!p_sb) {
1462                 DP_NOTICE(p_dev, false, "Failed to allocate `struct ecore_sb_attn_info'\n");
1463                 return ECORE_NOMEM;
1464         }
1465
1466         /* SB ring  */
1467         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1468                                          SB_ATTN_ALIGNED_SIZE(p_hwfn));
1469         if (!p_virt) {
1470                 DP_NOTICE(p_dev, false, "Failed to allocate status block (attentions)\n");
1471                 OSAL_FREE(p_dev, p_sb);
1472                 return ECORE_NOMEM;
1473         }
1474
1475         /* Attention setup */
1476         p_hwfn->p_sb_attn = p_sb;
1477         ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1478
1479         return ECORE_SUCCESS;
1480 }
1481
1482 /* coalescing timeout = timeset << (timer_res + 1) */
1483 #define ECORE_CAU_DEF_RX_USECS 24
1484 #define ECORE_CAU_DEF_TX_USECS 48
1485
1486 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1487                              struct cau_sb_entry *p_sb_entry,
1488                              u8 pf_id, u16 vf_number, u8 vf_valid)
1489 {
1490         struct ecore_dev *p_dev = p_hwfn->p_dev;
1491         u32 cau_state;
1492         u8 timer_res;
1493
1494         OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1495
1496         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1497         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1498         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1499         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1500         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1501
1502         cau_state = CAU_HC_DISABLE_STATE;
1503
1504         if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1505                 cau_state = CAU_HC_ENABLE_STATE;
1506                 if (!p_dev->rx_coalesce_usecs)
1507                         p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1508                 if (!p_dev->tx_coalesce_usecs)
1509                         p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1510         }
1511
1512         /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1513         if (p_dev->rx_coalesce_usecs <= 0x7F)
1514                 timer_res = 0;
1515         else if (p_dev->rx_coalesce_usecs <= 0xFF)
1516                 timer_res = 1;
1517         else
1518                 timer_res = 2;
1519         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1520
1521         if (p_dev->tx_coalesce_usecs <= 0x7F)
1522                 timer_res = 0;
1523         else if (p_dev->tx_coalesce_usecs <= 0xFF)
1524                 timer_res = 1;
1525         else
1526                 timer_res = 2;
1527         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1528
1529         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1530         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1531 }
1532
1533 static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1534                                    struct ecore_ptt *p_ptt,
1535                                    u16 igu_sb_id, u32 pi_index,
1536                                    enum ecore_coalescing_fsm coalescing_fsm,
1537                                    u8 timeset)
1538 {
1539         struct cau_pi_entry pi_entry;
1540         u32 sb_offset, pi_offset;
1541
1542         if (IS_VF(p_hwfn->p_dev))
1543                 return;/* @@@TBD MichalK- VF CAU... */
1544
1545         sb_offset = igu_sb_id * PIS_PER_SB;
1546         OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1547
1548         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1549         if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1550                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1551         else
1552                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1553
1554         pi_offset = sb_offset + pi_index;
1555         if (p_hwfn->hw_init_done) {
1556                 ecore_wr(p_hwfn, p_ptt,
1557                          CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1558                          *((u32 *)&(pi_entry)));
1559         } else {
1560                 STORE_RT_REG(p_hwfn,
1561                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1562                              *((u32 *)&(pi_entry)));
1563         }
1564 }
1565
1566 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1567                            struct ecore_ptt *p_ptt,
1568                            struct ecore_sb_info *p_sb, u32 pi_index,
1569                            enum ecore_coalescing_fsm coalescing_fsm,
1570                            u8 timeset)
1571 {
1572         _ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id,
1573                                pi_index, coalescing_fsm, timeset);
1574 }
1575
1576 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1577                            struct ecore_ptt *p_ptt,
1578                            dma_addr_t sb_phys, u16 igu_sb_id,
1579                            u16 vf_number, u8 vf_valid)
1580 {
1581         struct cau_sb_entry sb_entry;
1582
1583         ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1584                                 vf_number, vf_valid);
1585
1586         if (p_hwfn->hw_init_done) {
1587                 /* Wide-bus, initialize via DMAE */
1588                 u64 phys_addr = (u64)sb_phys;
1589
1590                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1591                                     (u64)(osal_uintptr_t)&phys_addr,
1592                                     CAU_REG_SB_ADDR_MEMORY +
1593                                     igu_sb_id * sizeof(u64), 2,
1594                                     OSAL_NULL /* default parameters */);
1595                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1596                                     (u64)(osal_uintptr_t)&sb_entry,
1597                                     CAU_REG_SB_VAR_MEMORY +
1598                                     igu_sb_id * sizeof(u64), 2,
1599                                     OSAL_NULL /* default parameters */);
1600         } else {
1601                 /* Initialize Status Block Address */
1602                 STORE_RT_REG_AGG(p_hwfn,
1603                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1604                                  igu_sb_id * 2, sb_phys);
1605
1606                 STORE_RT_REG_AGG(p_hwfn,
1607                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1608                                  igu_sb_id * 2, sb_entry);
1609         }
1610
1611         /* Configure pi coalescing if set */
1612         if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1613                 /* eth will open queues for all tcs, so configure all of them
1614                  * properly, rather than just the active ones
1615                  */
1616                 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1617
1618                 u8 timeset, timer_res;
1619                 u8 i;
1620
1621                 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1622                 if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1623                         timer_res = 0;
1624                 else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1625                         timer_res = 1;
1626                 else
1627                         timer_res = 2;
1628                 timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1629                 _ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1630                                        ECORE_COAL_RX_STATE_MACHINE,
1631                                        timeset);
1632
1633                 if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1634                         timer_res = 0;
1635                 else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1636                         timer_res = 1;
1637                 else
1638                         timer_res = 2;
1639                 timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1640                 for (i = 0; i < num_tc; i++) {
1641                         _ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1642                                                igu_sb_id, TX_PI(i),
1643                                                ECORE_COAL_TX_STATE_MACHINE,
1644                                                timeset);
1645                 }
1646         }
1647 }
1648
1649 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1650                         struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info)
1651 {
1652         /* zero status block and ack counter */
1653         sb_info->sb_ack = 0;
1654         OSAL_MEMSET(sb_info->sb_virt, 0, sb_info->sb_size);
1655
1656         if (IS_PF(p_hwfn->p_dev))
1657                 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1658                                       sb_info->igu_sb_id, 0, 0);
1659 }
1660
1661 struct ecore_igu_block *
1662 ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf)
1663 {
1664         struct ecore_igu_block *p_block;
1665         u16 igu_id;
1666
1667         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1668              igu_id++) {
1669                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1670
1671                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1672                     !(p_block->status & ECORE_IGU_STATUS_FREE))
1673                         continue;
1674
1675                 if (!!(p_block->status & ECORE_IGU_STATUS_PF) ==
1676                     b_is_pf)
1677                         return p_block;
1678         }
1679
1680         return OSAL_NULL;
1681 }
1682
1683 static u16 ecore_get_pf_igu_sb_id(struct ecore_hwfn *p_hwfn,
1684                                   u16 vector_id)
1685 {
1686         struct ecore_igu_block *p_block;
1687         u16 igu_id;
1688
1689         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1690              igu_id++) {
1691                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1692
1693                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1694                     !p_block->is_pf ||
1695                     p_block->vector_number != vector_id)
1696                         continue;
1697
1698                 return igu_id;
1699         }
1700
1701         return ECORE_SB_INVALID_IDX;
1702 }
1703
1704 u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1705 {
1706         u16 igu_sb_id;
1707
1708         /* Assuming continuous set of IGU SBs dedicated for given PF */
1709         if (sb_id == ECORE_SP_SB_ID)
1710                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1711         else if (IS_PF(p_hwfn->p_dev))
1712                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1713         else
1714                 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1715
1716         if (igu_sb_id == ECORE_SB_INVALID_IDX)
1717                 DP_NOTICE(p_hwfn, true,
1718                           "Slowpath SB vector %04x doesn't exist\n",
1719                           sb_id);
1720         else if (sb_id == ECORE_SP_SB_ID)
1721                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1722                            "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1723         else
1724                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1725                            "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1726
1727         return igu_sb_id;
1728 }
1729
1730 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1731                                        struct ecore_ptt *p_ptt,
1732                                        struct ecore_sb_info *sb_info,
1733                                        void *sb_virt_addr,
1734                                        dma_addr_t sb_phy_addr, u16 sb_id)
1735 {
1736         sb_info->sb_virt = sb_virt_addr;
1737         struct status_block *sb_virt;
1738
1739         sb_virt = (struct status_block *)sb_info->sb_virt;
1740
1741         sb_info->sb_size = sizeof(*sb_virt);
1742         sb_info->sb_pi_array = sb_virt->pi_array;
1743         sb_info->sb_prod_index = &sb_virt->prod_index;
1744
1745         sb_info->sb_phys = sb_phy_addr;
1746
1747         sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1748
1749         if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX)
1750                 return ECORE_INVAL;
1751
1752         /* Let the igu info reference the client's SB info */
1753         if (sb_id != ECORE_SP_SB_ID) {
1754                 if (IS_PF(p_hwfn->p_dev)) {
1755                         struct ecore_igu_info *p_info;
1756                         struct ecore_igu_block *p_block;
1757
1758                         p_info = p_hwfn->hw_info.p_igu_info;
1759                         p_block = &p_info->entry[sb_info->igu_sb_id];
1760
1761                         p_block->sb_info = sb_info;
1762                         p_block->status &= ~ECORE_IGU_STATUS_FREE;
1763                         p_info->usage.free_cnt--;
1764                 } else {
1765                         ecore_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1766                 }
1767         }
1768 #ifdef ECORE_CONFIG_DIRECT_HWFN
1769         sb_info->p_hwfn = p_hwfn;
1770 #endif
1771         sb_info->p_dev = p_hwfn->p_dev;
1772
1773         /* The igu address will hold the absolute address that needs to be
1774          * written to for a specific status block
1775          */
1776         if (IS_PF(p_hwfn->p_dev))
1777                 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1778                                      GTT_BAR0_MAP_REG_IGU_CMD +
1779                                      (sb_info->igu_sb_id << 3);
1780
1781         else
1782                 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1783                     PXP_VF_BAR0_START_IGU +
1784                                      ((IGU_CMD_INT_ACK_BASE +
1785                                        sb_info->igu_sb_id) << 3);
1786
1787         sb_info->flags |= ECORE_SB_INFO_INIT;
1788
1789         ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1790
1791         return ECORE_SUCCESS;
1792 }
1793
1794 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1795                                           struct ecore_sb_info *sb_info,
1796                                           u16 sb_id)
1797 {
1798         struct ecore_igu_info *p_info;
1799         struct ecore_igu_block *p_block;
1800
1801         if (sb_info == OSAL_NULL)
1802                 return ECORE_SUCCESS;
1803
1804         /* zero status block and ack counter */
1805         sb_info->sb_ack = 0;
1806         OSAL_MEMSET(sb_info->sb_virt, 0, sb_info->sb_size);
1807
1808         if (IS_VF(p_hwfn->p_dev)) {
1809                 ecore_vf_set_sb_info(p_hwfn, sb_id, OSAL_NULL);
1810                 return ECORE_SUCCESS;
1811         }
1812
1813         p_info = p_hwfn->hw_info.p_igu_info;
1814         p_block = &p_info->entry[sb_info->igu_sb_id];
1815
1816         /* Vector 0 is reserved to Default SB */
1817         if (p_block->vector_number == 0) {
1818                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1819                 return ECORE_INVAL;
1820         }
1821
1822         /* Lose reference to client's SB info, and fix counters */
1823         p_block->sb_info = OSAL_NULL;
1824         p_block->status |= ECORE_IGU_STATUS_FREE;
1825         p_info->usage.free_cnt++;
1826
1827         return ECORE_SUCCESS;
1828 }
1829
1830 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1831 {
1832         struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1833
1834         if (!p_sb)
1835                 return;
1836
1837         if (p_sb->sb_info.sb_virt) {
1838                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1839                                        p_sb->sb_info.sb_virt,
1840                                        p_sb->sb_info.sb_phys,
1841                                        SB_ALIGNED_SIZE(p_hwfn));
1842         }
1843
1844         OSAL_FREE(p_hwfn->p_dev, p_sb);
1845 }
1846
1847 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1848                                                   struct ecore_ptt *p_ptt)
1849 {
1850         struct ecore_sb_sp_info *p_sb;
1851         dma_addr_t p_phys = 0;
1852         void *p_virt;
1853
1854         /* SB struct */
1855         p_sb = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_sb));
1856         if (!p_sb) {
1857                 DP_NOTICE(p_hwfn, false,
1858                           "Failed to allocate `struct ecore_sb_info'\n");
1859                 return ECORE_NOMEM;
1860         }
1861
1862         /* SB ring  */
1863         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1864                                          &p_phys, SB_ALIGNED_SIZE(p_hwfn));
1865         if (!p_virt) {
1866                 DP_NOTICE(p_hwfn, false, "Failed to allocate status block\n");
1867                 OSAL_FREE(p_hwfn->p_dev, p_sb);
1868                 return ECORE_NOMEM;
1869         }
1870
1871         /* Status Block setup */
1872         p_hwfn->p_sp_sb = p_sb;
1873         ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1874                           p_virt, p_phys, ECORE_SP_SB_ID);
1875
1876         p_sb->pi_info_arr_size = PIS_PER_SB;
1877
1878         return ECORE_SUCCESS;
1879 }
1880
1881 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1882                                            ecore_int_comp_cb_t comp_cb,
1883                                            void *cookie,
1884                                            u8 *sb_idx, __le16 **p_fw_cons)
1885 {
1886         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1887         enum _ecore_status_t rc = ECORE_NOMEM;
1888         u8 pi;
1889
1890         /* Look for a free index */
1891         for (pi = 0; pi < p_sp_sb->pi_info_arr_size; pi++) {
1892                 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1893                         continue;
1894
1895                 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1896                 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1897                 *sb_idx = pi;
1898                 *p_fw_cons = &p_sp_sb->sb_info.sb_pi_array[pi];
1899                 rc = ECORE_SUCCESS;
1900                 break;
1901         }
1902
1903         return rc;
1904 }
1905
1906 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi)
1907 {
1908         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1909
1910         if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1911                 return ECORE_NOMEM;
1912
1913         p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1914         p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1915         return ECORE_SUCCESS;
1916 }
1917
1918 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1919 {
1920         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1921 }
1922
1923 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1924                               struct ecore_ptt *p_ptt,
1925                               enum ecore_int_mode int_mode)
1926 {
1927         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1928
1929 #ifndef ASIC_ONLY
1930         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1931                 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1932                 igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1933         }
1934 #endif
1935
1936         p_hwfn->p_dev->int_mode = int_mode;
1937         switch (p_hwfn->p_dev->int_mode) {
1938         case ECORE_INT_MODE_INTA:
1939                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1940                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1941                 break;
1942
1943         case ECORE_INT_MODE_MSI:
1944                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1945                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1946                 break;
1947
1948         case ECORE_INT_MODE_MSIX:
1949                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1950                 break;
1951         case ECORE_INT_MODE_POLL:
1952                 break;
1953         }
1954
1955         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1956 }
1957
1958 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1959                                       struct ecore_ptt *p_ptt)
1960 {
1961 #ifndef ASIC_ONLY
1962         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1963                 DP_INFO(p_hwfn,
1964                         "FPGA - Don't enable Attentions in IGU and MISC\n");
1965                 return;
1966         }
1967 #endif
1968
1969         /* Configure AEU signal change to produce attentions */
1970         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1971         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1972         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1973         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1974
1975         /* Flush the writes to IGU */
1976         OSAL_MMIOWB(p_hwfn->p_dev);
1977
1978         /* Unmask AEU signals toward IGU */
1979         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1980 }
1981
1982 enum _ecore_status_t
1983 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1984                           enum ecore_int_mode int_mode)
1985 {
1986         enum _ecore_status_t rc = ECORE_SUCCESS;
1987
1988         ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1989
1990         if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1991                 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1992                 if (rc != ECORE_SUCCESS) {
1993                         DP_NOTICE(p_hwfn, true,
1994                                   "Slowpath IRQ request failed\n");
1995                         return ECORE_NORESOURCES;
1996                 }
1997                 p_hwfn->b_int_requested = true;
1998         }
1999
2000         /* Enable interrupt Generation */
2001         ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
2002
2003         p_hwfn->b_int_enabled = 1;
2004
2005         return rc;
2006 }
2007
2008 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
2009                                struct ecore_ptt *p_ptt)
2010 {
2011         p_hwfn->b_int_enabled = 0;
2012
2013         if (IS_VF(p_hwfn->p_dev))
2014                 return;
2015
2016         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
2017 }
2018
2019 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
2020 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
2021                                      struct ecore_ptt *p_ptt,
2022                                      u32 igu_sb_id,
2023                                      bool cleanup_set,
2024                                      u16 opaque_fid)
2025 {
2026         u32 data = 0, cmd_ctrl = 0, sb_bit, sb_bit_addr, pxp_addr;
2027         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH, val;
2028         u8 type = 0;
2029
2030         OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
2031                            IGU_REG_CLEANUP_STATUS_0) != 0x200);
2032
2033         /* USE Control Command Register to perform cleanup. There is an
2034          * option to do this using IGU bar, but then it can't be used for VFs.
2035          */
2036
2037         /* Set the data field */
2038         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
2039         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
2040         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
2041
2042         /* Set the control register */
2043         pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
2044         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
2045         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
2046         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
2047
2048         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
2049
2050         OSAL_BARRIER(p_hwfn->p_dev);
2051
2052         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
2053
2054         /* Flush the write to IGU */
2055         OSAL_MMIOWB(p_hwfn->p_dev);
2056
2057         /* calculate where to read the status bit from */
2058         sb_bit = 1 << (igu_sb_id % 32);
2059         sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
2060
2061         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
2062
2063         /* Now wait for the command to complete */
2064         while (--sleep_cnt) {
2065                 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
2066                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
2067                         break;
2068                 OSAL_MSLEEP(5);
2069         }
2070
2071         if (!sleep_cnt)
2072                 DP_NOTICE(p_hwfn, true,
2073                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
2074                           val, igu_sb_id);
2075 }
2076
2077 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
2078                                        struct ecore_ptt *p_ptt,
2079                                        u16 igu_sb_id, u16 opaque, bool b_set)
2080 {
2081         struct ecore_igu_block *p_block;
2082         int pi, i;
2083
2084         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2085         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2086                    "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
2087                    igu_sb_id, p_block->function_id, p_block->is_pf,
2088                    p_block->vector_number);
2089
2090         /* Set */
2091         if (b_set)
2092                 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
2093
2094         /* Clear */
2095         ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
2096
2097         /* Wait for the IGU SB to cleanup */
2098         for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
2099                 u32 val;
2100
2101                 val = ecore_rd(p_hwfn, p_ptt,
2102                                IGU_REG_WRITE_DONE_PENDING +
2103                                ((igu_sb_id / 32) * 4));
2104                 if (val & (1 << (igu_sb_id % 32)))
2105                         OSAL_UDELAY(10);
2106                 else
2107                         break;
2108         }
2109         if (i == IGU_CLEANUP_SLEEP_LENGTH)
2110                 DP_NOTICE(p_hwfn, true,
2111                           "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
2112                           igu_sb_id);
2113
2114         /* Clear the CAU for the SB */
2115         for (pi = 0; pi < PIS_PER_SB; pi++)
2116                 ecore_wr(p_hwfn, p_ptt,
2117                          CAU_REG_PI_MEMORY +
2118                          (igu_sb_id * PIS_PER_SB + pi) * 4,
2119                          0);
2120 }
2121
2122 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
2123                                 struct ecore_ptt *p_ptt,
2124                                 bool b_set, bool b_slowpath)
2125 {
2126         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2127         struct ecore_igu_block *p_block;
2128         u16 igu_sb_id = 0;
2129         u32 val = 0;
2130
2131         /* @@@TBD MichalK temporary... should be moved to init-tool... */
2132         val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2133         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2134         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2135         ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2136         /* end temporary */
2137
2138         for (igu_sb_id = 0;
2139              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2140              igu_sb_id++) {
2141                 p_block = &p_info->entry[igu_sb_id];
2142
2143                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2144                     !p_block->is_pf ||
2145                     (p_block->status & ECORE_IGU_STATUS_DSB))
2146                         continue;
2147
2148                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2149                                                   p_hwfn->hw_info.opaque_fid,
2150                                                   b_set);
2151         }
2152
2153         if (b_slowpath)
2154                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2155                                                   p_info->igu_dsb_id,
2156                                                   p_hwfn->hw_info.opaque_fid,
2157                                                   b_set);
2158 }
2159
2160 int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn,
2161                             struct ecore_ptt *p_ptt)
2162 {
2163         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2164         struct ecore_igu_block *p_block;
2165         int pf_sbs, vf_sbs;
2166         u16 igu_sb_id;
2167         u32 val, rval;
2168
2169         if (!RESC_NUM(p_hwfn, ECORE_SB)) {
2170                 /* We're using an old MFW - have to prevent any switching
2171                  * of SBs between PF and VFs as later driver wouldn't be
2172                  * able to tell which belongs to which.
2173                  */
2174                 p_info->b_allow_pf_vf_change = false;
2175         } else {
2176                 /* Use the numbers the MFW have provided -
2177                  * don't forget MFW accounts for the default SB as well.
2178                  */
2179                 p_info->b_allow_pf_vf_change = true;
2180
2181                 if (p_info->usage.cnt != RESC_NUM(p_hwfn, ECORE_SB) - 1) {
2182                         DP_INFO(p_hwfn,
2183                                 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2184                                 RESC_NUM(p_hwfn, ECORE_SB) - 1,
2185                                 p_info->usage.cnt);
2186                         p_info->usage.cnt = RESC_NUM(p_hwfn, ECORE_SB) - 1;
2187                 }
2188
2189                 /* TODO - how do we learn about VF SBs from MFW? */
2190                 if (IS_PF_SRIOV(p_hwfn)) {
2191                         u16 vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
2192
2193                         if (vfs != p_info->usage.iov_cnt)
2194                                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2195                                            "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2196                                            p_info->usage.iov_cnt, vfs);
2197
2198                         /* At this point we know how many SBs we have totally
2199                          * in IGU + number of PF SBs. So we can validate that
2200                          * we'd have sufficient for VF.
2201                          */
2202                         if (vfs > p_info->usage.free_cnt +
2203                                   p_info->usage.free_cnt_iov -
2204                                   p_info->usage.cnt) {
2205                                 DP_NOTICE(p_hwfn, true,
2206                                           "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2207                                           p_info->usage.free_cnt +
2208                                           p_info->usage.free_cnt_iov,
2209                                           p_info->usage.cnt, vfs);
2210                                 return ECORE_INVAL;
2211                         }
2212                 }
2213         }
2214
2215         /* Cap the number of VFs SBs by the number of VFs */
2216         if (IS_PF_SRIOV(p_hwfn))
2217                 p_info->usage.iov_cnt = p_hwfn->p_dev->p_iov_info->total_vfs;
2218
2219         /* Mark all SBs as free, now in the right PF/VFs division */
2220         p_info->usage.free_cnt = p_info->usage.cnt;
2221         p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2222         p_info->usage.orig = p_info->usage.cnt;
2223         p_info->usage.iov_orig = p_info->usage.iov_cnt;
2224
2225         /* We now proceed to re-configure the IGU cam to reflect the initial
2226          * configuration. We can start with the Default SB.
2227          */
2228         pf_sbs = p_info->usage.cnt;
2229         vf_sbs = p_info->usage.iov_cnt;
2230
2231         for (igu_sb_id = p_info->igu_dsb_id;
2232              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2233              igu_sb_id++) {
2234                 p_block = &p_info->entry[igu_sb_id];
2235                 val = 0;
2236
2237                 if (!(p_block->status & ECORE_IGU_STATUS_VALID))
2238                         continue;
2239
2240                 if (p_block->status & ECORE_IGU_STATUS_DSB) {
2241                         p_block->function_id = p_hwfn->rel_pf_id;
2242                         p_block->is_pf = 1;
2243                         p_block->vector_number = 0;
2244                         p_block->status = ECORE_IGU_STATUS_VALID |
2245                                           ECORE_IGU_STATUS_PF |
2246                                           ECORE_IGU_STATUS_DSB;
2247                 } else if (pf_sbs) {
2248                         pf_sbs--;
2249                         p_block->function_id = p_hwfn->rel_pf_id;
2250                         p_block->is_pf = 1;
2251                         p_block->vector_number = p_info->usage.cnt - pf_sbs;
2252                         p_block->status = ECORE_IGU_STATUS_VALID |
2253                                           ECORE_IGU_STATUS_PF |
2254                                           ECORE_IGU_STATUS_FREE;
2255                 } else if (vf_sbs) {
2256                         p_block->function_id =
2257                                 p_hwfn->p_dev->p_iov_info->first_vf_in_pf +
2258                                 p_info->usage.iov_cnt - vf_sbs;
2259                         p_block->is_pf = 0;
2260                         p_block->vector_number = 0;
2261                         p_block->status = ECORE_IGU_STATUS_VALID |
2262                                           ECORE_IGU_STATUS_FREE;
2263                         vf_sbs--;
2264                 } else {
2265                         p_block->function_id = 0;
2266                         p_block->is_pf = 0;
2267                         p_block->vector_number = 0;
2268                 }
2269
2270                 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2271                           p_block->function_id);
2272                 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2273                 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2274                           p_block->vector_number);
2275
2276                 /* VF entries would be enabled when VF is initializaed */
2277                 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2278
2279                 rval = ecore_rd(p_hwfn, p_ptt,
2280                                 IGU_REG_MAPPING_MEMORY +
2281                                 sizeof(u32) * igu_sb_id);
2282
2283                 if (rval != val) {
2284                         ecore_wr(p_hwfn, p_ptt,
2285                                  IGU_REG_MAPPING_MEMORY +
2286                                  sizeof(u32) * igu_sb_id,
2287                                  val);
2288
2289                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2290                                    "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2291                                    igu_sb_id, p_block->function_id,
2292                                    p_block->is_pf, p_block->vector_number,
2293                                    rval, val);
2294                 }
2295         }
2296
2297         return 0;
2298 }
2299
2300 int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn,
2301                                     struct ecore_ptt *p_ptt)
2302 {
2303         struct ecore_sb_cnt_info *p_cnt = &p_hwfn->hw_info.p_igu_info->usage;
2304
2305         /* Return all the usage indications to default prior to the reset;
2306          * The reset expects the !orig to reflect the initial status of the
2307          * SBs, and would re-calculate the originals based on those.
2308          */
2309         p_cnt->cnt = p_cnt->orig;
2310         p_cnt->free_cnt = p_cnt->orig;
2311         p_cnt->iov_cnt = p_cnt->iov_orig;
2312         p_cnt->free_cnt_iov = p_cnt->iov_orig;
2313         p_cnt->orig = 0;
2314         p_cnt->iov_orig = 0;
2315
2316         /* TODO - we probably need to re-configure the CAU as well... */
2317         return ecore_int_igu_reset_cam(p_hwfn, p_ptt);
2318 }
2319
2320 static void ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
2321                                          struct ecore_ptt *p_ptt,
2322                                          u16 igu_sb_id)
2323 {
2324         u32 val = ecore_rd(p_hwfn, p_ptt,
2325                            IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2326         struct ecore_igu_block *p_block;
2327
2328         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2329
2330         /* Fill the block information */
2331         p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
2332         p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2333         p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
2334
2335         p_block->igu_sb_id = igu_sb_id;
2336 }
2337
2338 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
2339                                             struct ecore_ptt *p_ptt)
2340 {
2341         struct ecore_igu_info *p_igu_info;
2342         struct ecore_igu_block *p_block;
2343         u32 min_vf = 0, max_vf = 0;
2344         u16 igu_sb_id;
2345
2346         p_hwfn->hw_info.p_igu_info = OSAL_ZALLOC(p_hwfn->p_dev,
2347                                                  GFP_KERNEL,
2348                                                  sizeof(*p_igu_info));
2349         if (!p_hwfn->hw_info.p_igu_info)
2350                 return ECORE_NOMEM;
2351         p_igu_info = p_hwfn->hw_info.p_igu_info;
2352
2353         /* Distinguish between existent and onn-existent default SB */
2354         p_igu_info->igu_dsb_id = ECORE_SB_INVALID_IDX;
2355
2356         /* Find the range of VF ids whose SB belong to this PF */
2357         if (p_hwfn->p_dev->p_iov_info) {
2358                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
2359
2360                 min_vf = p_iov->first_vf_in_pf;
2361                 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2362         }
2363
2364         for (igu_sb_id = 0;
2365              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2366              igu_sb_id++) {
2367                 /* Read current entry; Notice it might not belong to this PF */
2368                 ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2369                 p_block = &p_igu_info->entry[igu_sb_id];
2370
2371                 if ((p_block->is_pf) &&
2372                     (p_block->function_id == p_hwfn->rel_pf_id)) {
2373                         p_block->status = ECORE_IGU_STATUS_PF |
2374                                           ECORE_IGU_STATUS_VALID |
2375                                           ECORE_IGU_STATUS_FREE;
2376
2377                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2378                                 p_igu_info->usage.cnt++;
2379                 } else if (!(p_block->is_pf) &&
2380                            (p_block->function_id >= min_vf) &&
2381                            (p_block->function_id < max_vf)) {
2382                         /* Available for VFs of this PF */
2383                         p_block->status = ECORE_IGU_STATUS_VALID |
2384                                           ECORE_IGU_STATUS_FREE;
2385
2386                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2387                                 p_igu_info->usage.iov_cnt++;
2388                 }
2389
2390                 /* Mark the First entry belonging to the PF or its VFs
2391                  * as the default SB [we'll reset IGU prior to first usage].
2392                  */
2393                 if ((p_block->status & ECORE_IGU_STATUS_VALID) &&
2394                     (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX)) {
2395                         p_igu_info->igu_dsb_id = igu_sb_id;
2396                         p_block->status |= ECORE_IGU_STATUS_DSB;
2397                 }
2398
2399                 /* While this isn't suitable for all clients, limit number
2400                  * of prints by having each PF print only its entries with the
2401                  * exception of PF0 which would print everything.
2402                  */
2403                 if ((p_block->status & ECORE_IGU_STATUS_VALID) ||
2404                     (p_hwfn->abs_pf_id == 0))
2405                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2406                                    "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2407                                    igu_sb_id, p_block->function_id,
2408                                    p_block->is_pf, p_block->vector_number);
2409         }
2410
2411         if (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX) {
2412                 DP_NOTICE(p_hwfn, true,
2413                           "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2414                           p_igu_info->igu_dsb_id);
2415                 return ECORE_INVAL;
2416         }
2417
2418         /* All non default SB are considered free at this point */
2419         p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2420         p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2421
2422         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2423                    "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2424                    p_igu_info->igu_dsb_id, p_igu_info->usage.cnt,
2425                    p_igu_info->usage.iov_cnt);
2426
2427         return ECORE_SUCCESS;
2428 }
2429
2430 enum _ecore_status_t
2431 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2432                           u16 sb_id, bool b_to_vf)
2433 {
2434         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2435         struct ecore_igu_block *p_block = OSAL_NULL;
2436         u16 igu_sb_id = 0, vf_num = 0;
2437         u32 val = 0;
2438
2439         if (IS_VF(p_hwfn->p_dev) || !IS_PF_SRIOV(p_hwfn))
2440                 return ECORE_INVAL;
2441
2442         if (sb_id == ECORE_SP_SB_ID)
2443                 return ECORE_INVAL;
2444
2445         if (!p_info->b_allow_pf_vf_change) {
2446                 DP_INFO(p_hwfn, "Can't relocate SBs as MFW is too old.\n");
2447                 return ECORE_INVAL;
2448         }
2449
2450         /* If we're moving a SB from PF to VF, the client had to specify
2451          * which vector it wants to move.
2452          */
2453         if (b_to_vf) {
2454                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
2455                 if (igu_sb_id == ECORE_SB_INVALID_IDX)
2456                         return ECORE_INVAL;
2457         }
2458
2459         /* If we're moving a SB from VF to PF, need to validate there isn't
2460          * already a line configured for that vector.
2461          */
2462         if (!b_to_vf) {
2463                 if (ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1) !=
2464                     ECORE_SB_INVALID_IDX)
2465                         return ECORE_INVAL;
2466         }
2467
2468         /* We need to validate that the SB can actually be relocated.
2469          * This would also handle the previous case where we've explicitly
2470          * stated which IGU SB needs to move.
2471          */
2472         for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2473              igu_sb_id++) {
2474                 p_block = &p_info->entry[igu_sb_id];
2475
2476                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2477                     !(p_block->status & ECORE_IGU_STATUS_FREE) ||
2478                     (!!(p_block->status & ECORE_IGU_STATUS_PF) != b_to_vf)) {
2479                         if (b_to_vf)
2480                                 return ECORE_INVAL;
2481                         else
2482                                 continue;
2483                 }
2484
2485                 break;
2486         }
2487
2488         if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) {
2489                 DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
2490                            "Failed to find a free SB to move\n");
2491                 return ECORE_INVAL;
2492         }
2493
2494         /* At this point, p_block points to the SB we want to relocate */
2495         if (b_to_vf) {
2496                 p_block->status &= ~ECORE_IGU_STATUS_PF;
2497
2498                 /* It doesn't matter which VF number we choose, since we're
2499                  * going to disable the line; But let's keep it in range.
2500                  */
2501                 vf_num = (u16)p_hwfn->p_dev->p_iov_info->first_vf_in_pf;
2502
2503                 p_block->function_id = (u8)vf_num;
2504                 p_block->is_pf = 0;
2505                 p_block->vector_number = 0;
2506
2507                 p_info->usage.cnt--;
2508                 p_info->usage.free_cnt--;
2509                 p_info->usage.iov_cnt++;
2510                 p_info->usage.free_cnt_iov++;
2511
2512                 /* TODO - if SBs aren't really the limiting factor,
2513                  * then it might not be accurate [in the since that
2514                  * we might not need decrement the feature].
2515                  */
2516                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]--;
2517                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]++;
2518         } else {
2519                 p_block->status |= ECORE_IGU_STATUS_PF;
2520                 p_block->function_id = p_hwfn->rel_pf_id;
2521                 p_block->is_pf = 1;
2522                 p_block->vector_number = sb_id + 1;
2523
2524                 p_info->usage.cnt++;
2525                 p_info->usage.free_cnt++;
2526                 p_info->usage.iov_cnt--;
2527                 p_info->usage.free_cnt_iov--;
2528
2529                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]++;
2530                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]--;
2531         }
2532
2533         /* Update the IGU and CAU with the new configuration */
2534         SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2535                   p_block->function_id);
2536         SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2537         SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2538         SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2539                   p_block->vector_number);
2540
2541         ecore_wr(p_hwfn, p_ptt,
2542                  IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id,
2543                  val);
2544
2545         ecore_int_cau_conf_sb(p_hwfn, p_ptt, 0,
2546                               igu_sb_id, vf_num,
2547                               p_block->is_pf ? 0 : 1);
2548
2549         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2550                    "Relocation: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2551                    igu_sb_id, p_block->function_id,
2552                    p_block->is_pf, p_block->vector_number);
2553
2554         return ECORE_SUCCESS;
2555 }
2556
2557 /**
2558  * @brief Initialize igu runtime registers
2559  *
2560  * @param p_hwfn
2561  */
2562 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2563 {
2564         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2565
2566         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2567 }
2568
2569 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2570                           IGU_CMD_INT_ACK_BASE)
2571 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2572                           IGU_CMD_INT_ACK_BASE)
2573 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2574 {
2575         u32 intr_status_hi = 0, intr_status_lo = 0;
2576         u64 intr_status = 0;
2577
2578         intr_status_lo = REG_RD(p_hwfn,
2579                                 GTT_BAR0_MAP_REG_IGU_CMD +
2580                                 LSB_IGU_CMD_ADDR * 8);
2581         intr_status_hi = REG_RD(p_hwfn,
2582                                 GTT_BAR0_MAP_REG_IGU_CMD +
2583                                 MSB_IGU_CMD_ADDR * 8);
2584         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2585
2586         return intr_status;
2587 }
2588
2589 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2590 {
2591         OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2592         p_hwfn->b_sp_dpc_enabled = true;
2593 }
2594
2595 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2596 {
2597         p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2598         if (!p_hwfn->sp_dpc)
2599                 return ECORE_NOMEM;
2600
2601         return ECORE_SUCCESS;
2602 }
2603
2604 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2605 {
2606         OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2607 }
2608
2609 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2610                                      struct ecore_ptt *p_ptt)
2611 {
2612         enum _ecore_status_t rc = ECORE_SUCCESS;
2613
2614         rc = ecore_int_sp_dpc_alloc(p_hwfn);
2615         if (rc != ECORE_SUCCESS) {
2616                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2617                 return rc;
2618         }
2619
2620         rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2621         if (rc != ECORE_SUCCESS) {
2622                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2623                 return rc;
2624         }
2625
2626         rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2627         if (rc != ECORE_SUCCESS)
2628                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2629
2630         return rc;
2631 }
2632
2633 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2634 {
2635         ecore_int_sp_sb_free(p_hwfn);
2636         ecore_int_sb_attn_free(p_hwfn);
2637         ecore_int_sp_dpc_free(p_hwfn);
2638 }
2639
2640 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2641 {
2642         if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2643                 return;
2644
2645         ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2646         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2647         ecore_int_sp_dpc_setup(p_hwfn);
2648 }
2649
2650 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2651                            struct ecore_sb_cnt_info *p_sb_cnt_info)
2652 {
2653         struct ecore_igu_info *p_igu_info = p_hwfn->hw_info.p_igu_info;
2654
2655         if (!p_igu_info || !p_sb_cnt_info)
2656                 return;
2657
2658         OSAL_MEMCPY(p_sb_cnt_info, &p_igu_info->usage,
2659                     sizeof(*p_sb_cnt_info));
2660 }
2661
2662 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2663 {
2664         int i;
2665
2666         for_each_hwfn(p_dev, i)
2667                 p_dev->hwfns[i].b_int_requested = false;
2668 }
2669
2670 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2671 {
2672         p_dev->attn_clr_en = clr_enable;
2673 }
2674
2675 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2676                                              struct ecore_ptt *p_ptt,
2677                                              u8 timer_res, u16 sb_id, bool tx)
2678 {
2679         struct cau_sb_entry sb_entry;
2680         enum _ecore_status_t rc;
2681
2682         if (!p_hwfn->hw_init_done) {
2683                 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2684                 return ECORE_INVAL;
2685         }
2686
2687         rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2688                                  sb_id * sizeof(u64),
2689                                  (u64)(osal_uintptr_t)&sb_entry, 2,
2690                                  OSAL_NULL /* default parameters */);
2691         if (rc != ECORE_SUCCESS) {
2692                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2693                 return rc;
2694         }
2695
2696         if (tx)
2697                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2698         else
2699                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2700
2701         rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2702                                  (u64)(osal_uintptr_t)&sb_entry,
2703                                  CAU_REG_SB_VAR_MEMORY + sb_id * sizeof(u64), 2,
2704                                  OSAL_NULL /* default parameters */);
2705         if (rc != ECORE_SUCCESS) {
2706                 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2707                 return rc;
2708         }
2709
2710         return rc;
2711 }
2712
2713 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
2714                                           struct ecore_ptt *p_ptt,
2715                                           struct ecore_sb_info *p_sb,
2716                                           struct ecore_sb_info_dbg *p_info)
2717 {
2718         u16 sbid = p_sb->igu_sb_id;
2719         u32 i;
2720
2721         if (IS_VF(p_hwfn->p_dev))
2722                 return ECORE_INVAL;
2723
2724         if (sbid >= NUM_OF_SBS(p_hwfn->p_dev))
2725                 return ECORE_INVAL;
2726
2727         p_info->igu_prod = ecore_rd(p_hwfn, p_ptt,
2728                                     IGU_REG_PRODUCER_MEMORY + sbid * 4);
2729         p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
2730                                     IGU_REG_CONSUMER_MEM + sbid * 4);
2731
2732         for (i = 0; i < PIS_PER_SB; i++)
2733                 p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
2734                                               CAU_REG_PI_MEMORY +
2735                                               sbid * 4 * PIS_PER_SB +
2736                                               i * 4);
2737
2738         return ECORE_SUCCESS;
2739 }
2740
2741 void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn)
2742 {
2743         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2744         struct ecore_ptt *p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
2745                                                              RESERVED_PTT_DPC);
2746         int i;
2747
2748         /* Do not reorder the following cleanup sequence */
2749         /* Ack all attentions */
2750         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff);
2751
2752         /* Clear driver attention */
2753         ecore_wr(p_hwfn,  p_dpc_ptt,
2754                 ((p_hwfn->rel_pf_id << 3) + MISC_REG_AEU_GENERAL_ATTN_0), 0);
2755
2756         /* Clear per-PF IGU registers to restore them as if the IGU
2757          * was reset for this PF
2758          */
2759         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2760         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2761         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
2762
2763         /* Execute IGU clean up*/
2764         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1);
2765
2766         /* Clear Stats */
2767         ecore_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED, 0);
2768
2769         for (i = 0; i < IGU_REG_PBA_STS_PF_SIZE; i++)
2770                 ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0);
2771 }