drivers/net/qede/base/ecore_int.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include <rte_string_fns.h>
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_spq.h"
  12 #include "ecore_gtt_reg_addr.h"
  13 #include "ecore_init_ops.h"
  14 #include "ecore_rt_defs.h"
  15 #include "ecore_int.h"
  16 #include "reg_addr.h"
  17 #include "ecore_hw.h"
  18 #include "ecore_sriov.h"
  19 #include "ecore_vf.h"
  20 #include "ecore_hw_defs.h"
  21 #include "ecore_hsi_common.h"
  22 #include "ecore_mcp.h"
  23
  24 struct ecore_pi_info {
  25         ecore_int_comp_cb_t comp_cb;
  26         void *cookie;           /* Will be sent to the compl cb function */
  27 };
  28
  29 struct ecore_sb_sp_info {
  30         struct ecore_sb_info sb_info;
  31         /* per protocol index data */
  32         struct ecore_pi_info pi_info_arr[PIS_PER_SB_E4];
  33 };
  34
  35 enum ecore_attention_type {
  36         ECORE_ATTN_TYPE_ATTN,
  37         ECORE_ATTN_TYPE_PARITY,
  38 };
  39
  40 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  41         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  42
  43 struct aeu_invert_reg_bit {
  44         char bit_name[30];
  45
  46 #define ATTENTION_PARITY                (1 << 0)
  47
  48 #define ATTENTION_LENGTH_MASK           (0x00000ff0)
  49 #define ATTENTION_LENGTH_SHIFT          (4)
  50 #define ATTENTION_LENGTH(flags)         (((flags) & ATTENTION_LENGTH_MASK) >> \
  51                                          ATTENTION_LENGTH_SHIFT)
  52 #define ATTENTION_SINGLE                (1 << ATTENTION_LENGTH_SHIFT)
  53 #define ATTENTION_PAR                   (ATTENTION_SINGLE | ATTENTION_PARITY)
  54 #define ATTENTION_PAR_INT               ((2 << ATTENTION_LENGTH_SHIFT) | \
  55                                          ATTENTION_PARITY)
  56
  57 /* Multiple bits start with this offset */
  58 #define ATTENTION_OFFSET_MASK           (0x000ff000)
  59 #define ATTENTION_OFFSET_SHIFT          (12)
  60
  61 #define ATTENTION_BB_MASK               (0x00700000)
  62 #define ATTENTION_BB_SHIFT              (20)
  63 #define ATTENTION_BB(value)             ((value) << ATTENTION_BB_SHIFT)
  64 #define ATTENTION_BB_DIFFERENT          (1 << 23)
  65
  66 #define ATTENTION_CLEAR_ENABLE          (1 << 28)
  67         unsigned int flags;
  68
  69         /* Callback to call if attention will be triggered */
  70         enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
  71
  72         enum block_id block_index;
  73 };
  74
  75 struct aeu_invert_reg {
  76         struct aeu_invert_reg_bit bits[32];
  77 };
  78
  79 #define MAX_ATTN_GRPS           (8)
  80 #define NUM_ATTN_REGS           (9)
  81
  82 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
  83 {
  84         u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
  85
  86         DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", tmp);
  87         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 0xffffffff);
  88
  89         return ECORE_SUCCESS;
  90 }
  91
  92 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK         (0x3c000)
  93 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT        (14)
  94 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK         (0x03fc0)
  95 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT        (6)
  96 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK      (0x00020)
  97 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT     (5)
  98 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK     (0x0001e)
  99 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT    (1)
 100 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK      (0x1)
 101 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT     (0)
 102 #define ECORE_PSWHST_ATTENTION_VF_DISABLED              (0x1)
 103 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS         (0x1)
 104 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK         (0x1)
 105 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT        (0)
 106 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK     (0x1e)
 107 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT    (1)
 108 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK   (0x20)
 109 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT  (5)
 110 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK      (0x3fc0)
 111 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT     (6)
 112 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK      (0x3c000)
 113 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT     (14)
 114 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK    (0x3fc0000)
 115 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT   (18)
 116 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
 117 {
 118         u32 tmp =
 119             ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 120                      PSWHST_REG_VF_DISABLED_ERROR_VALID);
 121
 122         /* Disabled VF access */
 123         if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
 124                 u32 addr, data;
 125
 126                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 127                                 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
 128                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 129                                 PSWHST_REG_VF_DISABLED_ERROR_DATA);
 130                 DP_INFO(p_hwfn->p_dev,
 131                         "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x]"
 132                         " Write [0x%02x] Addr [0x%08x]\n",
 133                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK)
 134                              >> ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
 135                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK)
 136                              >> ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
 137                         (u8)((data &
 138                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
 139                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
 140                         (u8)((data &
 141                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
 142                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
 143                         (u8)((data &
 144                               ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
 145                               ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
 146                         addr);
 147         }
 148
 149         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 150                        PSWHST_REG_INCORRECT_ACCESS_VALID);
 151         if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
 152                 u32 addr, data, length;
 153
 154                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 155                                 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
 156                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 157                                 PSWHST_REG_INCORRECT_ACCESS_DATA);
 158                 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 159                                   PSWHST_REG_INCORRECT_ACCESS_LENGTH);
 160
 161                 DP_INFO(p_hwfn->p_dev,
 162                         "Incorrect access to %08x of length %08x - PF [%02x]"
 163                         " VF [%04x] [valid %02x] client [%02x] write [%02x]"
 164                         " Byte-Enable [%04x] [%08x]\n",
 165                         addr, length,
 166                         (u8)((data &
 167                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
 168                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
 169                         (u8)((data &
 170                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
 171                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
 172                         (u8)((data &
 173                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
 174                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
 175                         (u8)((data &
 176                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
 177                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
 178                         (u8)((data &
 179                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
 180                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
 181                         (u8)((data &
 182                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
 183                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
 184                         data);
 185         }
 186
 187         /* TODO - We know 'some' of these are legal due to virtualization,
 188          * but is it true for all of them?
 189          */
 190         return ECORE_SUCCESS;
 191 }
 192
 193 #define ECORE_GRC_ATTENTION_VALID_BIT           (1 << 0)
 194 #define ECORE_GRC_ATTENTION_ADDRESS_MASK        (0x7fffff << 0)
 195 #define ECORE_GRC_ATTENTION_RDWR_BIT            (1 << 23)
 196 #define ECORE_GRC_ATTENTION_MASTER_MASK         (0xf << 24)
 197 #define ECORE_GRC_ATTENTION_MASTER_SHIFT        (24)
 198 #define ECORE_GRC_ATTENTION_PF_MASK             (0xf)
 199 #define ECORE_GRC_ATTENTION_VF_MASK             (0xff << 4)
 200 #define ECORE_GRC_ATTENTION_VF_SHIFT            (4)
 201 #define ECORE_GRC_ATTENTION_PRIV_MASK           (0x3 << 14)
 202 #define ECORE_GRC_ATTENTION_PRIV_SHIFT          (14)
 203 #define ECORE_GRC_ATTENTION_PRIV_VF             (0)
 204 static const char *grc_timeout_attn_master_to_str(u8 master)
 205 {
 206         switch (master) {
 207         case 1:
 208                 return "PXP";
 209         case 2:
 210                 return "MCP";
 211         case 3:
 212                 return "MSDM";
 213         case 4:
 214                 return "PSDM";
 215         case 5:
 216                 return "YSDM";
 217         case 6:
 218                 return "USDM";
 219         case 7:
 220                 return "TSDM";
 221         case 8:
 222                 return "XSDM";
 223         case 9:
 224                 return "DBU";
 225         case 10:
 226                 return "DMAE";
 227         default:
 228                 return "Unknown";
 229         }
 230 }
 231
 232 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
 233 {
 234         enum _ecore_status_t rc = ECORE_SUCCESS;
 235         u32 tmp, tmp2;
 236
 237         /* We've already cleared the timeout interrupt register, so we learn
 238          * of interrupts via the validity register.
 239          * Any attention which is not for a timeout event is treated as fatal.
 240          */
 241         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 242                        GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
 243         if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT)) {
 244                 rc = ECORE_INVAL;
 245                 goto out;
 246         }
 247
 248         /* Read the GRC timeout information */
 249         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 250                        GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
 251         tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 252                         GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
 253
 254         DP_NOTICE(p_hwfn->p_dev, false,
 255                   "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
 256                   tmp2, tmp,
 257                   (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to"
 258                                                        : "Read from",
 259                   (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
 260                   grc_timeout_attn_master_to_str(
 261                         (tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >>
 262                          ECORE_GRC_ATTENTION_MASTER_SHIFT),
 263                   (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
 264                   (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
 265                   ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
 266                   ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
 267                   (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
 268                   ECORE_GRC_ATTENTION_VF_SHIFT);
 269
 270         /* Clean the validity bit */
 271         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 272                  GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
 273 out:
 274         return rc;
 275 }
 276
 277 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
 278 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
 279 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
 280 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
 281 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
 282 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
 283 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
 284 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
 285 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME      (1 << 22)
 286 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
 287 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
 288 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
 289 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
 290
 291 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
 292                                                    struct ecore_ptt *p_ptt,
 293                                                    bool is_hw_init)
 294 {
 295         u32 tmp;
 296         char str[512] = {0};
 297
 298         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
 299         if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
 300                 u32 addr_lo, addr_hi, details;
 301
 302                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 303                                    PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
 304                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 305                                    PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
 306                 details = ecore_rd(p_hwfn, p_ptt,
 307                                    PGLUE_B_REG_TX_ERR_WR_DETAILS);
 308                 OSAL_SNPRINTF(str, 512,
 309                          "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 310                           addr_hi, addr_lo, details,
 311                           (u8)((details &
 312                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 313                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 314                           (u8)((details &
 315                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 316                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 317                           (u8)((details &
 318                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 319                           tmp,
 320                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 321                                 1 : 0),
 322                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 323                                 1 : 0),
 324                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 325                                 1 : 0));
 326                 if (is_hw_init)
 327                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "%s", str);
 328                 else
 329                         DP_NOTICE(p_hwfn, false, "%s", str);
 330         }
 331
 332         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
 333         if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
 334                 u32 addr_lo, addr_hi, details;
 335
 336                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 337                                    PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
 338                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 339                                    PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
 340                 details = ecore_rd(p_hwfn, p_ptt,
 341                                    PGLUE_B_REG_TX_ERR_RD_DETAILS);
 342
 343                 DP_NOTICE(p_hwfn, false,
 344                           "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 345                           addr_hi, addr_lo, details,
 346                           (u8)((details &
 347                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 348                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 349                           (u8)((details &
 350                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 351                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 352                           (u8)((details &
 353                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 354                           tmp,
 355                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 356                                 1 : 0),
 357                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 358                                 1 : 0),
 359                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 360                                 1 : 0));
 361         }
 362
 363         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
 364         if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
 365                 DP_NOTICE(p_hwfn, false, "ICPL erorr - %08x\n", tmp);
 366
 367         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
 368         if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
 369                 u32 addr_hi, addr_lo;
 370
 371                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 372                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
 373                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 374                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
 375
 376                 DP_NOTICE(p_hwfn, false,
 377                           "ICPL erorr - %08x [Address %08x:%08x]\n",
 378                           tmp, addr_hi, addr_lo);
 379         }
 380
 381         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
 382         if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
 383                 u32 addr_hi, addr_lo, details;
 384
 385                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 386                                    PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
 387                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 388                                    PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
 389                 details = ecore_rd(p_hwfn, p_ptt,
 390                                    PGLUE_B_REG_VF_ILT_ERR_DETAILS);
 391
 392                 DP_NOTICE(p_hwfn, false,
 393                           "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
 394                           details, tmp, addr_hi, addr_lo);
 395         }
 396
 397         /* Clear the indications */
 398         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
 399
 400         return ECORE_SUCCESS;
 401 }
 402
 403 static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
 404 {
 405         return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false);
 406 }
 407
 408 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
 409 {
 410         DP_NOTICE(p_hwfn, false, "FW assertion!\n");
 411
 412         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
 413
 414         return ECORE_INVAL;
 415 }
 416
 417 static enum _ecore_status_t
 418 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
 419 {
 420         DP_INFO(p_hwfn, "General attention 35!\n");
 421
 422         return ECORE_SUCCESS;
 423 }
 424
 425 #define ECORE_DORQ_ATTENTION_REASON_MASK        (0xfffff)
 426 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK        (0xffff)
 427 #define ECORE_DORQ_ATTENTION_OPAQUE_SHIFT       (0x0)
 428 #define ECORE_DORQ_ATTENTION_SIZE_MASK          (0x7f)
 429 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT         (16)
 430
 431 #define ECORE_DB_REC_COUNT                      10
 432 #define ECORE_DB_REC_INTERVAL                   100
 433
 434 static enum _ecore_status_t ecore_db_rec_flush_queue(struct ecore_hwfn *p_hwfn,
 435                                                      struct ecore_ptt *p_ptt)
 436 {
 437         u8 count = ECORE_DB_REC_COUNT;
 438         u32 usage = 1;
 439
 440         /* wait for usage to zero or count to run out. This is necessary since
 441          * EDPM doorbell transactions can take multiple 64b cycles, and as such
 442          * can "split" over the pci. Possibly, the doorbell drop can happen with
 443          * half an EDPM in the queue and other half dropped. Another EDPM
 444          * doorbell to the same address (from doorbell recovery mechanism or
 445          * from the doorbelling entity) could have first half dropped and second
 446          * half interperted as continuation of the first. To prevent such
 447          * malformed doorbells from reaching the device, flush the queue before
 448          * releaseing the overflow sticky indication.
 449          */
 450         while (count-- && usage) {
 451                 usage = ecore_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
 452                 OSAL_UDELAY(ECORE_DB_REC_INTERVAL);
 453         }
 454
 455         /* should have been depleted by now */
 456         if (usage) {
 457                 DP_NOTICE(p_hwfn->p_dev, false,
 458                           "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n",
 459                           ECORE_DB_REC_INTERVAL * ECORE_DB_REC_COUNT, usage);
 460                 return ECORE_TIMEOUT;
 461         }
 462
 463         return ECORE_SUCCESS;
 464 }
 465
 466 /* assumes sticky overflow indication was set for this PF */
 467 static enum _ecore_status_t ecore_db_rec_attn(struct ecore_hwfn *p_hwfn,
 468                                               struct ecore_ptt *p_ptt)
 469 {
 470         enum _ecore_status_t rc;
 471
 472         if (ecore_edpm_enabled(p_hwfn)) {
 473                 rc = ecore_db_rec_flush_queue(p_hwfn, p_ptt);
 474                 if (rc != ECORE_SUCCESS)
 475                         return rc;
 476         }
 477
 478         /* flush any pedning (e)dpm as they may never arrive */
 479         ecore_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1);
 480
 481         /* release overflow sticky indication (stop silently dropping
 482          * everything)
 483          */
 484         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
 485
 486         /* repeat all last doorbells (doorbell drop recovery) */
 487         ecore_db_recovery_execute(p_hwfn, DB_REC_REAL_DEAL);
 488
 489         return ECORE_SUCCESS;
 490 }
 491
 492 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
 493 {
 494         u32 int_sts, first_drop_reason, details, address, overflow,
 495                 all_drops_reason;
 496         struct ecore_ptt *p_ptt = p_hwfn->p_dpc_ptt;
 497         enum _ecore_status_t rc;
 498
 499         int_sts = ecore_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
 500         DP_NOTICE(p_hwfn->p_dev, false, "DORQ attention. int_sts was %x\n",
 501                   int_sts);
 502
 503         /* int_sts may be zero since all PFs were interrupted for doorbell
 504          * overflow but another one already handled it. Can abort here. If
 505          * This PF also requires overflow recovery we will be interrupted again
 506          */
 507         if (!int_sts)
 508                 return ECORE_SUCCESS;
 509
 510         /* check if db_drop or overflow happened */
 511         if (int_sts & (DORQ_REG_INT_STS_DB_DROP |
 512                        DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) {
 513                 /* obtain data about db drop/overflow */
 514                 first_drop_reason = ecore_rd(p_hwfn, p_ptt,
 515                                   DORQ_REG_DB_DROP_REASON) &
 516                                   ECORE_DORQ_ATTENTION_REASON_MASK;
 517                 details = ecore_rd(p_hwfn, p_ptt,
 518                                    DORQ_REG_DB_DROP_DETAILS);
 519                 address = ecore_rd(p_hwfn, p_ptt,
 520                                    DORQ_REG_DB_DROP_DETAILS_ADDRESS);
 521                 overflow = ecore_rd(p_hwfn, p_ptt,
 522                                     DORQ_REG_PF_OVFL_STICKY);
 523                 all_drops_reason = ecore_rd(p_hwfn, p_ptt,
 524                                             DORQ_REG_DB_DROP_DETAILS_REASON);
 525
 526                 /* log info */
 527                 DP_NOTICE(p_hwfn->p_dev, false,
 528                           "Doorbell drop occurred\n"
 529                           "Address\t\t0x%08x\t(second BAR address)\n"
 530                           "FID\t\t0x%04x\t\t(Opaque FID)\n"
 531                           "Size\t\t0x%04x\t\t(in bytes)\n"
 532                           "1st drop reason\t0x%08x\t(details on first drop since last handling)\n"
 533                           "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n"
 534                           "Overflow\t0x%x\t\t(a per PF indication)\n",
 535                           address,
 536                           GET_FIELD(details, ECORE_DORQ_ATTENTION_OPAQUE),
 537                           GET_FIELD(details, ECORE_DORQ_ATTENTION_SIZE) * 4,
 538                           first_drop_reason, all_drops_reason, overflow);
 539
 540                 /* if this PF caused overflow, initiate recovery */
 541                 if (overflow) {
 542                         rc = ecore_db_rec_attn(p_hwfn, p_ptt);
 543                         if (rc != ECORE_SUCCESS)
 544                                 return rc;
 545                 }
 546
 547                 /* clear the doorbell drop details and prepare for next drop */
 548                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0);
 549
 550                 /* mark interrupt as handeld (note: even if drop was due to a
 551                  * different reason than overflow we mark as handled)
 552                  */
 553                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_INT_STS_WR,
 554                          DORQ_REG_INT_STS_DB_DROP |
 555                          DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR);
 556
 557                 /* if there are no indications otherthan drop indications,
 558                  * success
 559                  */
 560                 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP |
 561                                  DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR |
 562                                  DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0)
 563                         return ECORE_SUCCESS;
 564         }
 565
 566         /* some other indication was present - non recoverable */
 567         DP_INFO(p_hwfn, "DORQ fatal attention\n");
 568
 569         return ECORE_INVAL;
 570 }
 571
 572 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
 573 {
 574 #ifndef ASIC_ONLY
 575         if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
 576                 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 577                                    TM_REG_INT_STS_1);
 578
 579                 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
 580                             TM_REG_INT_STS_1_PEND_CONN_SCAN))
 581                         return ECORE_INVAL;
 582
 583                 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
 584                            TM_REG_INT_STS_1_PEND_CONN_SCAN))
 585                         DP_INFO(p_hwfn,
 586                                 "TM attention on emulation - most likely"
 587                                 " results of clock-ratios\n");
 588                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
 589                 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
 590                     TM_REG_INT_MASK_1_PEND_TASK_SCAN;
 591                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
 592
 593                 return ECORE_SUCCESS;
 594         }
 595 #endif
 596
 597         return ECORE_INVAL;
 598 }
 599
 600 /* Instead of major changes to the data-structure, we have a some 'special'
 601  * identifiers for sources that changed meaning between adapters.
 602  */
 603 enum aeu_invert_reg_special_type {
 604         AEU_INVERT_REG_SPECIAL_CNIG_0,
 605         AEU_INVERT_REG_SPECIAL_CNIG_1,
 606         AEU_INVERT_REG_SPECIAL_CNIG_2,
 607         AEU_INVERT_REG_SPECIAL_CNIG_3,
 608         AEU_INVERT_REG_SPECIAL_MAX,
 609 };
 610
 611 static struct aeu_invert_reg_bit
 612 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
 613         {"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 614         {"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 615         {"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 616         {"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 617 };
 618
 619 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
 620 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
 621         {
 622          {                      /* After Invert 1 */
 623           {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 624            MAX_BLOCK_ID},
 625           }
 626          },
 627
 628         {
 629          {                      /* After Invert 2 */
 630           {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 631           {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 632           {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglueb_rbc_attn_cb,
 633            BLOCK_PGLUE_B},
 634           {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 635           {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 636           {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 637           {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 638           {"SW timers #%d",
 639            (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT),
 640            OSAL_NULL, MAX_BLOCK_ID},
 641           {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 642            BLOCK_PGLCS},
 643           }
 644          },
 645
 646         {
 647          {                      /* After Invert 3 */
 648           {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 649            MAX_BLOCK_ID},
 650           }
 651          },
 652
 653         {
 654          {                      /* After Invert 4 */
 655           {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 656            ecore_fw_assertion, MAX_BLOCK_ID},
 657           {"General Attention %d",
 658            (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT),
 659            OSAL_NULL, MAX_BLOCK_ID},
 660           {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 661            ecore_general_attention_35, MAX_BLOCK_ID},
 662           {"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 663                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
 664                          OSAL_NULL, BLOCK_NWS},
 665           {"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 666                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
 667                             OSAL_NULL, BLOCK_NWS},
 668           {"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 669                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
 670                          OSAL_NULL, BLOCK_NWM},
 671           {"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 672                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
 673                             OSAL_NULL, BLOCK_NWM},
 674           {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
 675           {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 676           {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 677           {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 678           {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 679           {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 680           {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 681            MAX_BLOCK_ID},
 682           {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
 683           {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
 684           {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
 685           {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
 686           {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
 687           }
 688          },
 689
 690         {
 691          {                      /* After Invert 5 */
 692           {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
 693           {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
 694           {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
 695           {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
 696           {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
 697           {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
 698           {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
 699           {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
 700           {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
 701           {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
 702           {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
 703           {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
 704           {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
 705           {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
 706           {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
 707           {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM},
 708           }
 709          },
 710
 711         {
 712          {                      /* After Invert 6 */
 713           {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
 714           {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
 715           {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
 716           {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
 717           {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
 718           {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
 719           {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
 720           {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
 721           {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
 722           {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
 723           {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
 724           {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
 725           {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
 726           {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
 727           {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
 728           {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
 729           }
 730          },
 731
 732         {
 733          {                      /* After Invert 7 */
 734           {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
 735           {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
 736           {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
 737           {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
 738           {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 739           {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
 740           {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
 741           {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
 742           {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
 743           {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
 744           {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
 745           {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
 746           {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
 747           {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
 748           {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
 749           {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 750           {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
 751           }
 752          },
 753
 754         {
 755          {                      /* After Invert 8 */
 756           {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
 757           {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
 758           {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
 759           {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
 760           {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
 761           {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
 762           {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
 763           {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
 764           {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
 765           {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
 766           {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 767           {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 768           {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 769           {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 770           {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 771           {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 772           {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
 773           {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 774           {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 775           {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 776           {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 777            MAX_BLOCK_ID},
 778           }
 779          },
 780
 781         {
 782          {                      /* After Invert 9 */
 783           {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 784           {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL,
 785            MAX_BLOCK_ID},
 786           {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 787           {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 788           {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 789            MAX_BLOCK_ID},
 790           }
 791          },
 792
 793 };
 794
 795 static struct aeu_invert_reg_bit *
 796 ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
 797                         struct aeu_invert_reg_bit *p_bit)
 798 {
 799         if (!ECORE_IS_BB(p_hwfn->p_dev))
 800                 return p_bit;
 801
 802         if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
 803                 return p_bit;
 804
 805         return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
 806                                   ATTENTION_BB_SHIFT];
 807 }
 808
 809 static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
 810                                      struct aeu_invert_reg_bit *p_bit)
 811 {
 812         return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
 813                   ATTENTION_PARITY);
 814 }
 815
 816 #define ATTN_STATE_BITS         (0xfff)
 817 #define ATTN_BITS_MASKABLE      (0x3ff)
 818 struct ecore_sb_attn_info {
 819         /* Virtual & Physical address of the SB */
 820         struct atten_status_block *sb_attn;
 821         dma_addr_t sb_phys;
 822
 823         /* Last seen running index */
 824         u16 index;
 825
 826         /* A mask of the AEU bits resulting in a parity error */
 827         u32 parity_mask[NUM_ATTN_REGS];
 828
 829         /* A pointer to the attention description structure */
 830         struct aeu_invert_reg *p_aeu_desc;
 831
 832         /* Previously asserted attentions, which are still unasserted */
 833         u16 known_attn;
 834
 835         /* Cleanup address for the link's general hw attention */
 836         u32 mfw_attn_addr;
 837 };
 838
 839 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
 840                                  struct ecore_sb_attn_info *p_sb_desc)
 841 {
 842         u16 rc = 0, index;
 843
 844         OSAL_MMIOWB(p_hwfn->p_dev);
 845
 846         index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
 847         if (p_sb_desc->index != index) {
 848                 p_sb_desc->index = index;
 849                 rc = ECORE_SB_ATT_IDX;
 850         }
 851
 852         OSAL_MMIOWB(p_hwfn->p_dev);
 853
 854         return rc;
 855 }
 856
 857 /**
 858  * @brief ecore_int_assertion - handles asserted attention bits
 859  *
 860  * @param p_hwfn
 861  * @param asserted_bits newly asserted bits
 862  * @return enum _ecore_status_t
 863  */
 864 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
 865                                                 u16 asserted_bits)
 866 {
 867         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 868         u32 igu_mask;
 869
 870         /* Mask the source of the attention in the IGU */
 871         igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 872                             IGU_REG_ATTENTION_ENABLE);
 873         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 874                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 875         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 876         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 877
 878         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 879                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 880                    sb_attn_sw->known_attn,
 881                    sb_attn_sw->known_attn | asserted_bits);
 882         sb_attn_sw->known_attn |= asserted_bits;
 883
 884         /* Handle MCP events */
 885         if (asserted_bits & 0x100) {
 886                 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 887                 /* Clean the MCP attention */
 888                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 889                          sb_attn_sw->mfw_attn_addr, 0);
 890         }
 891
 892         /* FIXME - this will change once we'll have GOOD gtt definitions */
 893         DIRECT_REG_WR(p_hwfn,
 894                       (u8 OSAL_IOMEM *) p_hwfn->regview +
 895                       GTT_BAR0_MAP_REG_IGU_CMD +
 896                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 897                         IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
 898
 899         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
 900                    asserted_bits);
 901
 902         return ECORE_SUCCESS;
 903 }
 904
 905 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
 906                                  enum block_id id, enum dbg_attn_type type,
 907                                  bool b_clear)
 908 {
 909         /* @DPDK */
 910         DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n", id, type);
 911 }
 912
 913 /**
 914  * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
 915  * cause of the attention
 916  *
 917  * @param p_hwfn
 918  * @param p_aeu - descriptor of an AEU bit which caused the attention
 919  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
 920  *  this bit to this group.
 921  * @param bit_index - index of this bit in the aeu_en_reg
 922  *
 923  * @return enum _ecore_status_t
 924  */
 925 static enum _ecore_status_t
 926 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
 927                               struct aeu_invert_reg_bit *p_aeu,
 928                               u32 aeu_en_reg,
 929                               const char *p_bit_name,
 930                               u32 bitmask)
 931 {
 932         enum _ecore_status_t rc = ECORE_INVAL;
 933         bool b_fatal = false;
 934
 935         DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
 936                 p_bit_name, bitmask);
 937
 938         /* Call callback before clearing the interrupt status */
 939         if (p_aeu->cb) {
 940                 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
 941                         p_bit_name);
 942                 rc = p_aeu->cb(p_hwfn);
 943         }
 944
 945         if (rc != ECORE_SUCCESS)
 946                 b_fatal = true;
 947
 948         /* Print HW block interrupt registers */
 949         if (p_aeu->block_index != MAX_BLOCK_ID) {
 950                 ecore_int_attn_print(p_hwfn, p_aeu->block_index,
 951                                      ATTN_TYPE_INTERRUPT, !b_fatal);
 952 }
 953
 954         /* @DPDK */
 955         /* Reach assertion if attention is fatal */
 956         if (b_fatal || (strcmp(p_bit_name, "PGLUE B RBC") == 0)) {
 957                 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
 958                           p_bit_name);
 959
 960                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
 961         }
 962
 963         /* Prevent this Attention from being asserted in the future */
 964         if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
 965             p_hwfn->p_dev->attn_clr_en) {
 966                 u32 val;
 967                 u32 mask = ~bitmask;
 968                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 969                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
 970                 DP_ERR(p_hwfn, "`%s' - Disabled future attentions\n",
 971                         p_bit_name);
 972         }
 973
 974         return rc;
 975 }
 976
 977 /**
 978  * @brief ecore_int_deassertion_parity - handle a single parity AEU source
 979  *
 980  * @param p_hwfn
 981  * @param p_aeu - descriptor of an AEU bit which caused the parity
 982  * @param aeu_en_reg - address of the AEU enable register
 983  * @param bit_index
 984  */
 985 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
 986                                          struct aeu_invert_reg_bit *p_aeu,
 987                                          u32 aeu_en_reg, u8 bit_index)
 988 {
 989         u32 block_id = p_aeu->block_index, mask, val;
 990
 991         DP_NOTICE(p_hwfn->p_dev, false,
 992                   "%s parity attention is set [address 0x%08x, bit %d]\n",
 993                   p_aeu->bit_name, aeu_en_reg, bit_index);
 994
 995         if (block_id != MAX_BLOCK_ID) {
 996                 ecore_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
 997
 998                 /* In A0, there's a single parity bit for several blocks */
 999                 if (block_id == BLOCK_BTB) {
1000                         ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
1001                                              ATTN_TYPE_PARITY, false);
1002                         ecore_int_attn_print(p_hwfn, BLOCK_MCP,
1003                                              ATTN_TYPE_PARITY, false);
1004                 }
1005         }
1006
1007         /* Prevent this parity error from being re-asserted */
1008         mask = ~(0x1 << bit_index);
1009         val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
1010         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
1011         DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
1012                 p_aeu->bit_name);
1013 }
1014
1015 /**
1016  * @brief - handles deassertion of previously asserted attentions.
1017  *
1018  * @param p_hwfn
1019  * @param deasserted_bits - newly deasserted bits
1020  * @return enum _ecore_status_t
1021  *
1022  */
1023 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
1024                                                   u16 deasserted_bits)
1025 {
1026         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1027         u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
1028         u8 i, j, k, bit_idx;
1029         enum _ecore_status_t rc = ECORE_SUCCESS;
1030
1031         /* Read the attention registers in the AEU */
1032         for (i = 0; i < NUM_ATTN_REGS; i++) {
1033                 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1034                                           MISC_REG_AEU_AFTER_INVERT_1_IGU +
1035                                           i * 0x4);
1036                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1037                            "Deasserted bits [%d]: %08x\n", i, aeu_inv_arr[i]);
1038         }
1039
1040         /* Handle parity attentions first */
1041         for (i = 0; i < NUM_ATTN_REGS; i++) {
1042                 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
1043                 u32 parities;
1044
1045                 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
1046                 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1047                 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
1048
1049                 /* Skip register in which no parity bit is currently set */
1050                 if (!parities)
1051                         continue;
1052
1053                 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1054                         struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
1055
1056                         if (ecore_int_is_parity_flag(p_hwfn, p_bit) &&
1057                             !!(parities & (1 << bit_idx)))
1058                                 ecore_int_deassertion_parity(p_hwfn, p_bit,
1059                                                              aeu_en, bit_idx);
1060
1061                         bit_idx += ATTENTION_LENGTH(p_bit->flags);
1062                 }
1063         }
1064
1065         /* Find non-parity cause for attention and act */
1066         for (k = 0; k < MAX_ATTN_GRPS; k++) {
1067                 struct aeu_invert_reg_bit *p_aeu;
1068
1069                 /* Handle only groups whose attention is currently deasserted */
1070                 if (!(deasserted_bits & (1 << k)))
1071                         continue;
1072
1073                 for (i = 0; i < NUM_ATTN_REGS; i++) {
1074                         u32 bits;
1075
1076                         aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
1077                                  i * sizeof(u32) +
1078                                  k * sizeof(u32) * NUM_ATTN_REGS;
1079                         en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1080                         bits = aeu_inv_arr[i] & en;
1081
1082                         /* Skip if no bit from this group is currently set */
1083                         if (!bits)
1084                                 continue;
1085
1086                         /* Find all set bits from current register which belong
1087                          * to current group, making them responsible for the
1088                          * previous assertion.
1089                          */
1090                         for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1091                                 unsigned long int bitmask;
1092                                 u8 bit, bit_len;
1093
1094                                 /* Need to account bits with changed meaning */
1095                                 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1096
1097                                 bit = bit_idx;
1098                                 bit_len = ATTENTION_LENGTH(p_aeu->flags);
1099                                 if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) {
1100                                         /* Skip Parity */
1101                                         bit++;
1102                                         bit_len--;
1103                                 }
1104
1105                                 /* Find the bits relating to HW-block, then
1106                                  * shift so they'll become LSB.
1107                                  */
1108                                 bitmask = bits & (((1 << bit_len) - 1) << bit);
1109                                 bitmask >>= bit;
1110
1111                                 if (bitmask) {
1112                                         u32 flags = p_aeu->flags;
1113                                         char bit_name[30];
1114                                         u8 num;
1115
1116                                         num = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
1117                                                                 bit_len);
1118
1119                                         /* Some bits represent more than a
1120                                          * a single interrupt. Correctly print
1121                                          * their name.
1122                                          */
1123                                         if (ATTENTION_LENGTH(flags) > 2 ||
1124                                             ((flags & ATTENTION_PAR_INT) &&
1125                                             ATTENTION_LENGTH(flags) > 1))
1126                                                 OSAL_SNPRINTF(bit_name, 30,
1127                                                               p_aeu->bit_name,
1128                                                               num);
1129                                         else
1130                                                 strlcpy(bit_name,
1131                                                         p_aeu->bit_name,
1132                                                         sizeof(bit_name));
1133
1134                                         /* We now need to pass bitmask in its
1135                                          * correct position.
1136                                          */
1137                                         bitmask <<= bit;
1138
1139                                         /* Handle source of the attention */
1140                                         ecore_int_deassertion_aeu_bit(p_hwfn,
1141                                                                       p_aeu,
1142                                                                       aeu_en,
1143                                                                       bit_name,
1144                                                                       bitmask);
1145                                 }
1146
1147                                 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1148                         }
1149                 }
1150         }
1151
1152         /* Clear IGU indication for the deasserted bits */
1153         /* FIXME - this will change once we'll have GOOD gtt definitions */
1154         DIRECT_REG_WR(p_hwfn,
1155                       (u8 OSAL_IOMEM *) p_hwfn->regview +
1156                       GTT_BAR0_MAP_REG_IGU_CMD +
1157                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1158                         IGU_CMD_INT_ACK_BASE) << 3), ~((u32)deasserted_bits));
1159
1160         /* Unmask deasserted attentions in IGU */
1161         aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1162                             IGU_REG_ATTENTION_ENABLE);
1163         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1164         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1165
1166         /* Clear deassertion from inner state */
1167         sb_attn_sw->known_attn &= ~deasserted_bits;
1168
1169         return rc;
1170 }
1171
1172 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
1173 {
1174         struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1175         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1176         u16 index = 0, asserted_bits, deasserted_bits;
1177         u32 attn_bits = 0, attn_acks = 0;
1178         enum _ecore_status_t rc = ECORE_SUCCESS;
1179
1180         /* Read current attention bits/acks - safeguard against attentions
1181          * by guaranting work on a synchronized timeframe
1182          */
1183         do {
1184                 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1185                 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1186                 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1187         } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1188         p_sb_attn->sb_index = index;
1189
1190         /* Attention / Deassertion are meaningful (and in correct state)
1191          * only when they differ and consistent with known state - deassertion
1192          * when previous attention & current ack, and assertion when current
1193          * attention with no previous attention
1194          */
1195         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1196             ~p_sb_attn_sw->known_attn;
1197         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1198             p_sb_attn_sw->known_attn;
1199
1200         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1201                 DP_INFO(p_hwfn,
1202                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1203                         index, attn_bits, attn_acks, asserted_bits,
1204                         deasserted_bits, p_sb_attn_sw->known_attn);
1205         else if (asserted_bits == 0x100)
1206                 DP_INFO(p_hwfn, "MFW indication via attention\n");
1207         else
1208                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1209                            "MFW indication [deassertion]\n");
1210
1211         if (asserted_bits) {
1212                 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1213                 if (rc)
1214                         return rc;
1215         }
1216
1217         if (deasserted_bits)
1218                 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1219
1220         return rc;
1221 }
1222
1223 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1224                               void OSAL_IOMEM *igu_addr, u32 ack_cons)
1225 {
1226         struct igu_prod_cons_update igu_ack = { 0 };
1227
1228         igu_ack.sb_id_and_flags =
1229             ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1230              (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1231              (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1232              (IGU_SEG_ACCESS_ATTN <<
1233               IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1234
1235         DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1236
1237         /* Both segments (interrupts & acks) are written to same place address;
1238          * Need to guarantee all commands will be received (in-order) by HW.
1239          */
1240         OSAL_MMIOWB(p_hwfn->p_dev);
1241         OSAL_BARRIER(p_hwfn->p_dev);
1242 }
1243
1244 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1245 {
1246         struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1247         struct ecore_pi_info *pi_info = OSAL_NULL;
1248         struct ecore_sb_attn_info *sb_attn;
1249         struct ecore_sb_info *sb_info;
1250         int arr_size;
1251         u16 rc = 0;
1252
1253         if (!p_hwfn)
1254                 return;
1255
1256         if (!p_hwfn->p_sp_sb) {
1257                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1258                 return;
1259         }
1260
1261         sb_info = &p_hwfn->p_sp_sb->sb_info;
1262         arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1263         if (!sb_info) {
1264                 DP_ERR(p_hwfn->p_dev,
1265                        "Status block is NULL - cannot ack interrupts\n");
1266                 return;
1267         }
1268
1269         if (!p_hwfn->p_sb_attn) {
1270                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1271                 return;
1272         }
1273         sb_attn = p_hwfn->p_sb_attn;
1274
1275         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1276                    p_hwfn, p_hwfn->my_id);
1277
1278         /* Disable ack for def status block. Required both for msix +
1279          * inta in non-mask mode, in inta does no harm.
1280          */
1281         ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1282
1283         /* Gather Interrupts/Attentions information */
1284         if (!sb_info->sb_virt) {
1285                 DP_ERR(p_hwfn->p_dev,
1286                        "Interrupt Status block is NULL -"
1287                        " cannot check for new interrupts!\n");
1288         } else {
1289                 u32 tmp_index = sb_info->sb_ack;
1290                 rc = ecore_sb_update_sb_idx(sb_info);
1291                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1292                            "Interrupt indices: 0x%08x --> 0x%08x\n",
1293                            tmp_index, sb_info->sb_ack);
1294         }
1295
1296         if (!sb_attn || !sb_attn->sb_attn) {
1297                 DP_ERR(p_hwfn->p_dev,
1298                        "Attentions Status block is NULL -"
1299                        " cannot check for new attentions!\n");
1300         } else {
1301                 u16 tmp_index = sb_attn->index;
1302
1303                 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1304                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1305                            "Attention indices: 0x%08x --> 0x%08x\n",
1306                            tmp_index, sb_attn->index);
1307         }
1308
1309         /* Check if we expect interrupts at this time. if not just ack them */
1310         if (!(rc & ECORE_SB_EVENT_MASK)) {
1311                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1312                 return;
1313         }
1314
1315 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1316
1317         if (!p_hwfn->p_dpc_ptt) {
1318                 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1319                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1320                 return;
1321         }
1322
1323         if (rc & ECORE_SB_ATT_IDX)
1324                 ecore_int_attentions(p_hwfn);
1325
1326         if (rc & ECORE_SB_IDX) {
1327                 int pi;
1328
1329                 /* Since we only looked at the SB index, it's possible more
1330                  * than a single protocol-index on the SB incremented.
1331                  * Iterate over all configured protocol indices and check
1332                  * whether something happened for each.
1333                  */
1334                 for (pi = 0; pi < arr_size; pi++) {
1335                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1336                         if (pi_info->comp_cb != OSAL_NULL)
1337                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1338                 }
1339         }
1340
1341         if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1342                 /* This should be done before the interrupts are enabled,
1343                  * since otherwise a new attention will be generated.
1344                  */
1345                 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1346         }
1347
1348         ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1349 }
1350
1351 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1352 {
1353         struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1354
1355         if (!p_sb)
1356                 return;
1357
1358         if (p_sb->sb_attn) {
1359                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1360                                        p_sb->sb_phys,
1361                                        SB_ATTN_ALIGNED_SIZE(p_hwfn));
1362         }
1363         OSAL_FREE(p_hwfn->p_dev, p_sb);
1364 }
1365
1366 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1367                                     struct ecore_ptt *p_ptt)
1368 {
1369         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1370
1371         OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1372
1373         sb_info->index = 0;
1374         sb_info->known_attn = 0;
1375
1376         /* Configure Attention Status Block in IGU */
1377         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1378                  DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1379         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1380                  DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1381 }
1382
1383 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1384                                    struct ecore_ptt *p_ptt,
1385                                    void *sb_virt_addr, dma_addr_t sb_phy_addr)
1386 {
1387         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1388         int i, j, k;
1389
1390         sb_info->sb_attn = sb_virt_addr;
1391         sb_info->sb_phys = sb_phy_addr;
1392
1393         /* Set the pointer to the AEU descriptors */
1394         sb_info->p_aeu_desc = aeu_descs;
1395
1396         /* Calculate Parity Masks */
1397         OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1398         for (i = 0; i < NUM_ATTN_REGS; i++) {
1399                 /* j is array index, k is bit index */
1400                 for (j = 0, k = 0; k < 32; j++) {
1401                         struct aeu_invert_reg_bit *p_aeu;
1402
1403                         p_aeu = &aeu_descs[i].bits[j];
1404                         if (ecore_int_is_parity_flag(p_hwfn, p_aeu))
1405                                 sb_info->parity_mask[i] |= 1 << k;
1406
1407                         k += ATTENTION_LENGTH(p_aeu->flags);
1408                 }
1409                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1410                            "Attn Mask [Reg %d]: 0x%08x\n",
1411                            i, sb_info->parity_mask[i]);
1412         }
1413
1414         /* Set the address of cleanup for the mcp attention */
1415         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1416             MISC_REG_AEU_GENERAL_ATTN_0;
1417
1418         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1419 }
1420
1421 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1422                                                     struct ecore_ptt *p_ptt)
1423 {
1424         struct ecore_dev *p_dev = p_hwfn->p_dev;
1425         struct ecore_sb_attn_info *p_sb;
1426         dma_addr_t p_phys = 0;
1427         void *p_virt;
1428
1429         /* SB struct */
1430         p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1431         if (!p_sb) {
1432                 DP_NOTICE(p_dev, false, "Failed to allocate `struct ecore_sb_attn_info'\n");
1433                 return ECORE_NOMEM;
1434         }
1435
1436         /* SB ring  */
1437         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1438                                          SB_ATTN_ALIGNED_SIZE(p_hwfn));
1439         if (!p_virt) {
1440                 DP_NOTICE(p_dev, false, "Failed to allocate status block (attentions)\n");
1441                 OSAL_FREE(p_dev, p_sb);
1442                 return ECORE_NOMEM;
1443         }
1444
1445         /* Attention setup */
1446         p_hwfn->p_sb_attn = p_sb;
1447         ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1448
1449         return ECORE_SUCCESS;
1450 }
1451
1452 /* coalescing timeout = timeset << (timer_res + 1) */
1453 #define ECORE_CAU_DEF_RX_USECS 24
1454 #define ECORE_CAU_DEF_TX_USECS 48
1455
1456 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1457                              struct cau_sb_entry *p_sb_entry,
1458                              u8 pf_id, u16 vf_number, u8 vf_valid)
1459 {
1460         struct ecore_dev *p_dev = p_hwfn->p_dev;
1461         u32 cau_state;
1462         u8 timer_res;
1463
1464         OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1465
1466         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1467         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1468         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1469         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1470         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1471
1472         cau_state = CAU_HC_DISABLE_STATE;
1473
1474         if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1475                 cau_state = CAU_HC_ENABLE_STATE;
1476                 if (!p_dev->rx_coalesce_usecs)
1477                         p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1478                 if (!p_dev->tx_coalesce_usecs)
1479                         p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1480         }
1481
1482         /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1483         if (p_dev->rx_coalesce_usecs <= 0x7F)
1484                 timer_res = 0;
1485         else if (p_dev->rx_coalesce_usecs <= 0xFF)
1486                 timer_res = 1;
1487         else
1488                 timer_res = 2;
1489         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1490
1491         if (p_dev->tx_coalesce_usecs <= 0x7F)
1492                 timer_res = 0;
1493         else if (p_dev->tx_coalesce_usecs <= 0xFF)
1494                 timer_res = 1;
1495         else
1496                 timer_res = 2;
1497         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1498
1499         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1500         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1501 }
1502
1503 static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1504                                    struct ecore_ptt *p_ptt,
1505                                    u16 igu_sb_id, u32 pi_index,
1506                                    enum ecore_coalescing_fsm coalescing_fsm,
1507                                    u8 timeset)
1508 {
1509         struct cau_pi_entry pi_entry;
1510         u32 sb_offset, pi_offset;
1511
1512         if (IS_VF(p_hwfn->p_dev))
1513                 return;/* @@@TBD MichalK- VF CAU... */
1514
1515         sb_offset = igu_sb_id * PIS_PER_SB_E4;
1516         OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1517
1518         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1519         if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1520                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1521         else
1522                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1523
1524         pi_offset = sb_offset + pi_index;
1525         if (p_hwfn->hw_init_done) {
1526                 ecore_wr(p_hwfn, p_ptt,
1527                          CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1528                          *((u32 *)&(pi_entry)));
1529         } else {
1530                 STORE_RT_REG(p_hwfn,
1531                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1532                              *((u32 *)&(pi_entry)));
1533         }
1534 }
1535
1536 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1537                            struct ecore_ptt *p_ptt,
1538                            struct ecore_sb_info *p_sb, u32 pi_index,
1539                            enum ecore_coalescing_fsm coalescing_fsm,
1540                            u8 timeset)
1541 {
1542         _ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id,
1543                                pi_index, coalescing_fsm, timeset);
1544 }
1545
1546 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1547                            struct ecore_ptt *p_ptt,
1548                            dma_addr_t sb_phys, u16 igu_sb_id,
1549                            u16 vf_number, u8 vf_valid)
1550 {
1551         struct cau_sb_entry sb_entry;
1552
1553         ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1554                                 vf_number, vf_valid);
1555
1556         if (p_hwfn->hw_init_done) {
1557                 /* Wide-bus, initialize via DMAE */
1558                 u64 phys_addr = (u64)sb_phys;
1559
1560                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1561                                     (u64)(osal_uintptr_t)&phys_addr,
1562                                     CAU_REG_SB_ADDR_MEMORY +
1563                                     igu_sb_id * sizeof(u64), 2, 0);
1564                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1565                                     (u64)(osal_uintptr_t)&sb_entry,
1566                                     CAU_REG_SB_VAR_MEMORY +
1567                                     igu_sb_id * sizeof(u64), 2, 0);
1568         } else {
1569                 /* Initialize Status Block Address */
1570                 STORE_RT_REG_AGG(p_hwfn,
1571                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1572                                  igu_sb_id * 2, sb_phys);
1573
1574                 STORE_RT_REG_AGG(p_hwfn,
1575                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1576                                  igu_sb_id * 2, sb_entry);
1577         }
1578
1579         /* Configure pi coalescing if set */
1580         if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1581                 /* eth will open queues for all tcs, so configure all of them
1582                  * properly, rather than just the active ones
1583                  */
1584                 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1585
1586                 u8 timeset, timer_res;
1587                 u8 i;
1588
1589                 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1590                 if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1591                         timer_res = 0;
1592                 else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1593                         timer_res = 1;
1594                 else
1595                         timer_res = 2;
1596                 timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1597                 _ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1598                                        ECORE_COAL_RX_STATE_MACHINE,
1599                                        timeset);
1600
1601                 if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1602                         timer_res = 0;
1603                 else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1604                         timer_res = 1;
1605                 else
1606                         timer_res = 2;
1607                 timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1608                 for (i = 0; i < num_tc; i++) {
1609                         _ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1610                                                igu_sb_id, TX_PI(i),
1611                                                ECORE_COAL_TX_STATE_MACHINE,
1612                                                timeset);
1613                 }
1614         }
1615 }
1616
1617 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1618                         struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info)
1619 {
1620         /* zero status block and ack counter */
1621         sb_info->sb_ack = 0;
1622         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1623
1624         if (IS_PF(p_hwfn->p_dev))
1625                 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1626                                       sb_info->igu_sb_id, 0, 0);
1627 }
1628
1629 struct ecore_igu_block *
1630 ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf)
1631 {
1632         struct ecore_igu_block *p_block;
1633         u16 igu_id;
1634
1635         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1636              igu_id++) {
1637                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1638
1639                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1640                     !(p_block->status & ECORE_IGU_STATUS_FREE))
1641                         continue;
1642
1643                 if (!!(p_block->status & ECORE_IGU_STATUS_PF) ==
1644                     b_is_pf)
1645                         return p_block;
1646         }
1647
1648         return OSAL_NULL;
1649 }
1650
1651 static u16 ecore_get_pf_igu_sb_id(struct ecore_hwfn *p_hwfn,
1652                                   u16 vector_id)
1653 {
1654         struct ecore_igu_block *p_block;
1655         u16 igu_id;
1656
1657         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1658              igu_id++) {
1659                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1660
1661                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1662                     !p_block->is_pf ||
1663                     p_block->vector_number != vector_id)
1664                         continue;
1665
1666                 return igu_id;
1667         }
1668
1669         return ECORE_SB_INVALID_IDX;
1670 }
1671
1672 u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1673 {
1674         u16 igu_sb_id;
1675
1676         /* Assuming continuous set of IGU SBs dedicated for given PF */
1677         if (sb_id == ECORE_SP_SB_ID)
1678                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1679         else if (IS_PF(p_hwfn->p_dev))
1680                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1681         else
1682                 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1683
1684         if (igu_sb_id == ECORE_SB_INVALID_IDX)
1685                 DP_NOTICE(p_hwfn, true,
1686                           "Slowpath SB vector %04x doesn't exist\n",
1687                           sb_id);
1688         else if (sb_id == ECORE_SP_SB_ID)
1689                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1690                            "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1691         else
1692                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1693                            "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1694
1695         return igu_sb_id;
1696 }
1697
1698 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1699                                        struct ecore_ptt *p_ptt,
1700                                        struct ecore_sb_info *sb_info,
1701                                        void *sb_virt_addr,
1702                                        dma_addr_t sb_phy_addr, u16 sb_id)
1703 {
1704         sb_info->sb_virt = sb_virt_addr;
1705         sb_info->sb_phys = sb_phy_addr;
1706
1707         sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1708
1709         if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX)
1710                 return ECORE_INVAL;
1711
1712         /* Let the igu info reference the client's SB info */
1713         if (sb_id != ECORE_SP_SB_ID) {
1714                 if (IS_PF(p_hwfn->p_dev)) {
1715                         struct ecore_igu_info *p_info;
1716                         struct ecore_igu_block *p_block;
1717
1718                         p_info = p_hwfn->hw_info.p_igu_info;
1719                         p_block = &p_info->entry[sb_info->igu_sb_id];
1720
1721                         p_block->sb_info = sb_info;
1722                         p_block->status &= ~ECORE_IGU_STATUS_FREE;
1723                         p_info->usage.free_cnt--;
1724                 } else {
1725                         ecore_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1726                 }
1727         }
1728 #ifdef ECORE_CONFIG_DIRECT_HWFN
1729         sb_info->p_hwfn = p_hwfn;
1730 #endif
1731         sb_info->p_dev = p_hwfn->p_dev;
1732
1733         /* The igu address will hold the absolute address that needs to be
1734          * written to for a specific status block
1735          */
1736         if (IS_PF(p_hwfn->p_dev)) {
1737                 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1738                     GTT_BAR0_MAP_REG_IGU_CMD + (sb_info->igu_sb_id << 3);
1739
1740         } else {
1741                 sb_info->igu_addr =
1742                     (u8 OSAL_IOMEM *)p_hwfn->regview +
1743                     PXP_VF_BAR0_START_IGU +
1744                     ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1745         }
1746
1747         sb_info->flags |= ECORE_SB_INFO_INIT;
1748
1749         ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1750
1751         return ECORE_SUCCESS;
1752 }
1753
1754 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1755                                           struct ecore_sb_info *sb_info,
1756                                           u16 sb_id)
1757 {
1758         struct ecore_igu_info *p_info;
1759         struct ecore_igu_block *p_block;
1760
1761         if (sb_info == OSAL_NULL)
1762                 return ECORE_SUCCESS;
1763
1764         /* zero status block and ack counter */
1765         sb_info->sb_ack = 0;
1766         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1767
1768         if (IS_VF(p_hwfn->p_dev)) {
1769                 ecore_vf_set_sb_info(p_hwfn, sb_id, OSAL_NULL);
1770                 return ECORE_SUCCESS;
1771         }
1772
1773         p_info = p_hwfn->hw_info.p_igu_info;
1774         p_block = &p_info->entry[sb_info->igu_sb_id];
1775
1776         /* Vector 0 is reserved to Default SB */
1777         if (p_block->vector_number == 0) {
1778                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1779                 return ECORE_INVAL;
1780         }
1781
1782         /* Lose reference to client's SB info, and fix counters */
1783         p_block->sb_info = OSAL_NULL;
1784         p_block->status |= ECORE_IGU_STATUS_FREE;
1785         p_info->usage.free_cnt++;
1786
1787         return ECORE_SUCCESS;
1788 }
1789
1790 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1791 {
1792         struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1793
1794         if (!p_sb)
1795                 return;
1796
1797         if (p_sb->sb_info.sb_virt) {
1798                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1799                                        p_sb->sb_info.sb_virt,
1800                                        p_sb->sb_info.sb_phys,
1801                                        SB_ALIGNED_SIZE(p_hwfn));
1802         }
1803
1804         OSAL_FREE(p_hwfn->p_dev, p_sb);
1805 }
1806
1807 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1808                                                   struct ecore_ptt *p_ptt)
1809 {
1810         struct ecore_sb_sp_info *p_sb;
1811         dma_addr_t p_phys = 0;
1812         void *p_virt;
1813
1814         /* SB struct */
1815         p_sb =
1816             OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1817                        sizeof(*p_sb));
1818         if (!p_sb) {
1819                 DP_NOTICE(p_hwfn, false, "Failed to allocate `struct ecore_sb_info'\n");
1820                 return ECORE_NOMEM;
1821         }
1822
1823         /* SB ring  */
1824         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1825                                          &p_phys, SB_ALIGNED_SIZE(p_hwfn));
1826         if (!p_virt) {
1827                 DP_NOTICE(p_hwfn, false, "Failed to allocate status block\n");
1828                 OSAL_FREE(p_hwfn->p_dev, p_sb);
1829                 return ECORE_NOMEM;
1830         }
1831
1832         /* Status Block setup */
1833         p_hwfn->p_sp_sb = p_sb;
1834         ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1835                           p_virt, p_phys, ECORE_SP_SB_ID);
1836
1837         OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1838
1839         return ECORE_SUCCESS;
1840 }
1841
1842 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1843                                            ecore_int_comp_cb_t comp_cb,
1844                                            void *cookie,
1845                                            u8 *sb_idx, __le16 **p_fw_cons)
1846 {
1847         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1848         enum _ecore_status_t rc = ECORE_NOMEM;
1849         u8 pi;
1850
1851         /* Look for a free index */
1852         for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1853                 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1854                         continue;
1855
1856                 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1857                 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1858                 *sb_idx = pi;
1859                 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1860                 rc = ECORE_SUCCESS;
1861                 break;
1862         }
1863
1864         return rc;
1865 }
1866
1867 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi)
1868 {
1869         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1870
1871         if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1872                 return ECORE_NOMEM;
1873
1874         p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1875         p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1876         return ECORE_SUCCESS;
1877 }
1878
1879 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1880 {
1881         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1882 }
1883
1884 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1885                               struct ecore_ptt *p_ptt,
1886                               enum ecore_int_mode int_mode)
1887 {
1888         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1889
1890 #ifndef ASIC_ONLY
1891         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1892                 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1893                 igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1894         }
1895 #endif
1896
1897         p_hwfn->p_dev->int_mode = int_mode;
1898         switch (p_hwfn->p_dev->int_mode) {
1899         case ECORE_INT_MODE_INTA:
1900                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1901                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1902                 break;
1903
1904         case ECORE_INT_MODE_MSI:
1905                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1906                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1907                 break;
1908
1909         case ECORE_INT_MODE_MSIX:
1910                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1911                 break;
1912         case ECORE_INT_MODE_POLL:
1913                 break;
1914         }
1915
1916         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1917 }
1918
1919 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1920                                       struct ecore_ptt *p_ptt)
1921 {
1922 #ifndef ASIC_ONLY
1923         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1924                 DP_INFO(p_hwfn,
1925                         "FPGA - Don't enable Attentions in IGU and MISC\n");
1926                 return;
1927         }
1928 #endif
1929
1930         /* Configure AEU signal change to produce attentions */
1931         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1932         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1933         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1934         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1935
1936         /* Flush the writes to IGU */
1937         OSAL_MMIOWB(p_hwfn->p_dev);
1938
1939         /* Unmask AEU signals toward IGU */
1940         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1941 }
1942
1943 enum _ecore_status_t
1944 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1945                           enum ecore_int_mode int_mode)
1946 {
1947         enum _ecore_status_t rc = ECORE_SUCCESS;
1948
1949         ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1950
1951         if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1952                 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1953                 if (rc != ECORE_SUCCESS) {
1954                         DP_NOTICE(p_hwfn, true,
1955                                   "Slowpath IRQ request failed\n");
1956                         return ECORE_NORESOURCES;
1957                 }
1958                 p_hwfn->b_int_requested = true;
1959         }
1960
1961         /* Enable interrupt Generation */
1962         ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1963
1964         p_hwfn->b_int_enabled = 1;
1965
1966         return rc;
1967 }
1968
1969 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
1970                                struct ecore_ptt *p_ptt)
1971 {
1972         p_hwfn->b_int_enabled = 0;
1973
1974         if (IS_VF(p_hwfn->p_dev))
1975                 return;
1976
1977         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1978 }
1979
1980 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
1981 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1982                                      struct ecore_ptt *p_ptt,
1983                                      u32 igu_sb_id,
1984                                      bool cleanup_set,
1985                                      u16 opaque_fid)
1986 {
1987         u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1988         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1989         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1990         u8 type = 0;            /* FIXME MichalS type??? */
1991
1992         OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1993                            IGU_REG_CLEANUP_STATUS_0) != 0x200);
1994
1995         /* USE Control Command Register to perform cleanup. There is an
1996          * option to do this using IGU bar, but then it can't be used for VFs.
1997          */
1998
1999         /* Set the data field */
2000         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
2001         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
2002         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
2003
2004         /* Set the control register */
2005         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
2006         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
2007         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
2008
2009         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
2010
2011         OSAL_BARRIER(p_hwfn->p_dev);
2012
2013         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
2014
2015         /* Flush the write to IGU */
2016         OSAL_MMIOWB(p_hwfn->p_dev);
2017
2018         /* calculate where to read the status bit from */
2019         sb_bit = 1 << (igu_sb_id % 32);
2020         sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
2021
2022         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
2023
2024         /* Now wait for the command to complete */
2025         while (--sleep_cnt) {
2026                 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
2027                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
2028                         break;
2029                 OSAL_MSLEEP(5);
2030         }
2031
2032         if (!sleep_cnt)
2033                 DP_NOTICE(p_hwfn, true,
2034                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
2035                           val, igu_sb_id);
2036 }
2037
2038 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
2039                                        struct ecore_ptt *p_ptt,
2040                                        u16 igu_sb_id, u16 opaque, bool b_set)
2041 {
2042         struct ecore_igu_block *p_block;
2043         int pi, i;
2044
2045         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2046         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2047                    "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
2048                    igu_sb_id, p_block->function_id, p_block->is_pf,
2049                    p_block->vector_number);
2050
2051         /* Set */
2052         if (b_set)
2053                 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
2054
2055         /* Clear */
2056         ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
2057
2058         /* Wait for the IGU SB to cleanup */
2059         for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
2060                 u32 val;
2061
2062                 val = ecore_rd(p_hwfn, p_ptt,
2063                                IGU_REG_WRITE_DONE_PENDING +
2064                                ((igu_sb_id / 32) * 4));
2065                 if (val & (1 << (igu_sb_id % 32)))
2066                         OSAL_UDELAY(10);
2067                 else
2068                         break;
2069         }
2070         if (i == IGU_CLEANUP_SLEEP_LENGTH)
2071                 DP_NOTICE(p_hwfn, true,
2072                           "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
2073                           igu_sb_id);
2074
2075         /* Clear the CAU for the SB */
2076         for (pi = 0; pi < 12; pi++)
2077                 ecore_wr(p_hwfn, p_ptt,
2078                          CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
2079 }
2080
2081 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
2082                                 struct ecore_ptt *p_ptt,
2083                                 bool b_set, bool b_slowpath)
2084 {
2085         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2086         struct ecore_igu_block *p_block;
2087         u16 igu_sb_id = 0;
2088         u32 val = 0;
2089
2090         /* @@@TBD MichalK temporary... should be moved to init-tool... */
2091         val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2092         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2093         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2094         ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2095         /* end temporary */
2096
2097         for (igu_sb_id = 0;
2098              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2099              igu_sb_id++) {
2100                 p_block = &p_info->entry[igu_sb_id];
2101
2102                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2103                     !p_block->is_pf ||
2104                     (p_block->status & ECORE_IGU_STATUS_DSB))
2105                         continue;
2106
2107                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2108                                                   p_hwfn->hw_info.opaque_fid,
2109                                                   b_set);
2110         }
2111
2112         if (b_slowpath)
2113                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2114                                                   p_info->igu_dsb_id,
2115                                                   p_hwfn->hw_info.opaque_fid,
2116                                                   b_set);
2117 }
2118
2119 int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn,
2120                             struct ecore_ptt *p_ptt)
2121 {
2122         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2123         struct ecore_igu_block *p_block;
2124         int pf_sbs, vf_sbs;
2125         u16 igu_sb_id;
2126         u32 val, rval;
2127
2128         if (!RESC_NUM(p_hwfn, ECORE_SB)) {
2129                 /* We're using an old MFW - have to prevent any switching
2130                  * of SBs between PF and VFs as later driver wouldn't be
2131                  * able to tell which belongs to which.
2132                  */
2133                 p_info->b_allow_pf_vf_change = false;
2134         } else {
2135                 /* Use the numbers the MFW have provided -
2136                  * don't forget MFW accounts for the default SB as well.
2137                  */
2138                 p_info->b_allow_pf_vf_change = true;
2139
2140                 if (p_info->usage.cnt != RESC_NUM(p_hwfn, ECORE_SB) - 1) {
2141                         DP_INFO(p_hwfn,
2142                                 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2143                                 RESC_NUM(p_hwfn, ECORE_SB) - 1,
2144                                 p_info->usage.cnt);
2145                         p_info->usage.cnt = RESC_NUM(p_hwfn, ECORE_SB) - 1;
2146                 }
2147
2148                 /* TODO - how do we learn about VF SBs from MFW? */
2149                 if (IS_PF_SRIOV(p_hwfn)) {
2150                         u16 vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
2151
2152                         if (vfs != p_info->usage.iov_cnt)
2153                                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2154                                            "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2155                                            p_info->usage.iov_cnt, vfs);
2156
2157                         /* At this point we know how many SBs we have totally
2158                          * in IGU + number of PF SBs. So we can validate that
2159                          * we'd have sufficient for VF.
2160                          */
2161                         if (vfs > p_info->usage.free_cnt +
2162                                   p_info->usage.free_cnt_iov -
2163                                   p_info->usage.cnt) {
2164                                 DP_NOTICE(p_hwfn, true,
2165                                           "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2166                                           p_info->usage.free_cnt +
2167                                           p_info->usage.free_cnt_iov,
2168                                           p_info->usage.cnt, vfs);
2169                                 return ECORE_INVAL;
2170                         }
2171                 }
2172         }
2173
2174         /* Cap the number of VFs SBs by the number of VFs */
2175         if (IS_PF_SRIOV(p_hwfn))
2176                 p_info->usage.iov_cnt = p_hwfn->p_dev->p_iov_info->total_vfs;
2177
2178         /* Mark all SBs as free, now in the right PF/VFs division */
2179         p_info->usage.free_cnt = p_info->usage.cnt;
2180         p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2181         p_info->usage.orig = p_info->usage.cnt;
2182         p_info->usage.iov_orig = p_info->usage.iov_cnt;
2183
2184         /* We now proceed to re-configure the IGU cam to reflect the initial
2185          * configuration. We can start with the Default SB.
2186          */
2187         pf_sbs = p_info->usage.cnt;
2188         vf_sbs = p_info->usage.iov_cnt;
2189
2190         for (igu_sb_id = p_info->igu_dsb_id;
2191              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2192              igu_sb_id++) {
2193                 p_block = &p_info->entry[igu_sb_id];
2194                 val = 0;
2195
2196                 if (!(p_block->status & ECORE_IGU_STATUS_VALID))
2197                         continue;
2198
2199                 if (p_block->status & ECORE_IGU_STATUS_DSB) {
2200                         p_block->function_id = p_hwfn->rel_pf_id;
2201                         p_block->is_pf = 1;
2202                         p_block->vector_number = 0;
2203                         p_block->status = ECORE_IGU_STATUS_VALID |
2204                                           ECORE_IGU_STATUS_PF |
2205                                           ECORE_IGU_STATUS_DSB;
2206                 } else if (pf_sbs) {
2207                         pf_sbs--;
2208                         p_block->function_id = p_hwfn->rel_pf_id;
2209                         p_block->is_pf = 1;
2210                         p_block->vector_number = p_info->usage.cnt - pf_sbs;
2211                         p_block->status = ECORE_IGU_STATUS_VALID |
2212                                           ECORE_IGU_STATUS_PF |
2213                                           ECORE_IGU_STATUS_FREE;
2214                 } else if (vf_sbs) {
2215                         p_block->function_id =
2216                                 p_hwfn->p_dev->p_iov_info->first_vf_in_pf +
2217                                 p_info->usage.iov_cnt - vf_sbs;
2218                         p_block->is_pf = 0;
2219                         p_block->vector_number = 0;
2220                         p_block->status = ECORE_IGU_STATUS_VALID |
2221                                           ECORE_IGU_STATUS_FREE;
2222                         vf_sbs--;
2223                 } else {
2224                         p_block->function_id = 0;
2225                         p_block->is_pf = 0;
2226                         p_block->vector_number = 0;
2227                 }
2228
2229                 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2230                           p_block->function_id);
2231                 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2232                 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2233                           p_block->vector_number);
2234
2235                 /* VF entries would be enabled when VF is initializaed */
2236                 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2237
2238                 rval = ecore_rd(p_hwfn, p_ptt,
2239                                 IGU_REG_MAPPING_MEMORY +
2240                                 sizeof(u32) * igu_sb_id);
2241
2242                 if (rval != val) {
2243                         ecore_wr(p_hwfn, p_ptt,
2244                                  IGU_REG_MAPPING_MEMORY +
2245                                  sizeof(u32) * igu_sb_id,
2246                                  val);
2247
2248                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2249                                    "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2250                                    igu_sb_id, p_block->function_id,
2251                                    p_block->is_pf, p_block->vector_number,
2252                                    rval, val);
2253                 }
2254         }
2255
2256         return 0;
2257 }
2258
2259 int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn,
2260                                     struct ecore_ptt *p_ptt)
2261 {
2262         struct ecore_sb_cnt_info *p_cnt = &p_hwfn->hw_info.p_igu_info->usage;
2263
2264         /* Return all the usage indications to default prior to the reset;
2265          * The reset expects the !orig to reflect the initial status of the
2266          * SBs, and would re-calculate the originals based on those.
2267          */
2268         p_cnt->cnt = p_cnt->orig;
2269         p_cnt->free_cnt = p_cnt->orig;
2270         p_cnt->iov_cnt = p_cnt->iov_orig;
2271         p_cnt->free_cnt_iov = p_cnt->iov_orig;
2272         p_cnt->orig = 0;
2273         p_cnt->iov_orig = 0;
2274
2275         /* TODO - we probably need to re-configure the CAU as well... */
2276         return ecore_int_igu_reset_cam(p_hwfn, p_ptt);
2277 }
2278
2279 static void ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
2280                                          struct ecore_ptt *p_ptt,
2281                                          u16 igu_sb_id)
2282 {
2283         u32 val = ecore_rd(p_hwfn, p_ptt,
2284                            IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2285         struct ecore_igu_block *p_block;
2286
2287         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2288
2289         /* Fill the block information */
2290         p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
2291         p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2292         p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
2293
2294         p_block->igu_sb_id = igu_sb_id;
2295 }
2296
2297 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
2298                                             struct ecore_ptt *p_ptt)
2299 {
2300         struct ecore_igu_info *p_igu_info;
2301         struct ecore_igu_block *p_block;
2302         u32 min_vf = 0, max_vf = 0;
2303         u16 igu_sb_id;
2304
2305         p_hwfn->hw_info.p_igu_info = OSAL_ZALLOC(p_hwfn->p_dev,
2306                                                  GFP_KERNEL,
2307                                                  sizeof(*p_igu_info));
2308         if (!p_hwfn->hw_info.p_igu_info)
2309                 return ECORE_NOMEM;
2310         p_igu_info = p_hwfn->hw_info.p_igu_info;
2311
2312         /* Distinguish between existent and onn-existent default SB */
2313         p_igu_info->igu_dsb_id = ECORE_SB_INVALID_IDX;
2314
2315         /* Find the range of VF ids whose SB belong to this PF */
2316         if (p_hwfn->p_dev->p_iov_info) {
2317                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
2318
2319                 min_vf = p_iov->first_vf_in_pf;
2320                 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2321         }
2322
2323         for (igu_sb_id = 0;
2324              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2325              igu_sb_id++) {
2326                 /* Read current entry; Notice it might not belong to this PF */
2327                 ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2328                 p_block = &p_igu_info->entry[igu_sb_id];
2329
2330                 if ((p_block->is_pf) &&
2331                     (p_block->function_id == p_hwfn->rel_pf_id)) {
2332                         p_block->status = ECORE_IGU_STATUS_PF |
2333                                           ECORE_IGU_STATUS_VALID |
2334                                           ECORE_IGU_STATUS_FREE;
2335
2336                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2337                                 p_igu_info->usage.cnt++;
2338                 } else if (!(p_block->is_pf) &&
2339                            (p_block->function_id >= min_vf) &&
2340                            (p_block->function_id < max_vf)) {
2341                         /* Available for VFs of this PF */
2342                         p_block->status = ECORE_IGU_STATUS_VALID |
2343                                           ECORE_IGU_STATUS_FREE;
2344
2345                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2346                                 p_igu_info->usage.iov_cnt++;
2347                 }
2348
2349                 /* Mark the First entry belonging to the PF or its VFs
2350                  * as the default SB [we'll reset IGU prior to first usage].
2351                  */
2352                 if ((p_block->status & ECORE_IGU_STATUS_VALID) &&
2353                     (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX)) {
2354                         p_igu_info->igu_dsb_id = igu_sb_id;
2355                         p_block->status |= ECORE_IGU_STATUS_DSB;
2356                 }
2357
2358                 /* While this isn't suitable for all clients, limit number
2359                  * of prints by having each PF print only its entries with the
2360                  * exception of PF0 which would print everything.
2361                  */
2362                 if ((p_block->status & ECORE_IGU_STATUS_VALID) ||
2363                     (p_hwfn->abs_pf_id == 0))
2364                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2365                                    "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2366                                    igu_sb_id, p_block->function_id,
2367                                    p_block->is_pf, p_block->vector_number);
2368         }
2369
2370         if (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX) {
2371                 DP_NOTICE(p_hwfn, true,
2372                           "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2373                           p_igu_info->igu_dsb_id);
2374                 return ECORE_INVAL;
2375         }
2376
2377         /* All non default SB are considered free at this point */
2378         p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2379         p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2380
2381         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2382                    "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2383                    p_igu_info->igu_dsb_id, p_igu_info->usage.cnt,
2384                    p_igu_info->usage.iov_cnt);
2385
2386         return ECORE_SUCCESS;
2387 }
2388
2389 enum _ecore_status_t
2390 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2391                           u16 sb_id, bool b_to_vf)
2392 {
2393         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2394         struct ecore_igu_block *p_block = OSAL_NULL;
2395         u16 igu_sb_id = 0, vf_num = 0;
2396         u32 val = 0;
2397
2398         if (IS_VF(p_hwfn->p_dev) || !IS_PF_SRIOV(p_hwfn))
2399                 return ECORE_INVAL;
2400
2401         if (sb_id == ECORE_SP_SB_ID)
2402                 return ECORE_INVAL;
2403
2404         if (!p_info->b_allow_pf_vf_change) {
2405                 DP_INFO(p_hwfn, "Can't relocate SBs as MFW is too old.\n");
2406                 return ECORE_INVAL;
2407         }
2408
2409         /* If we're moving a SB from PF to VF, the client had to specify
2410          * which vector it wants to move.
2411          */
2412         if (b_to_vf) {
2413                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
2414                 if (igu_sb_id == ECORE_SB_INVALID_IDX)
2415                         return ECORE_INVAL;
2416         }
2417
2418         /* If we're moving a SB from VF to PF, need to validate there isn't
2419          * already a line configured for that vector.
2420          */
2421         if (!b_to_vf) {
2422                 if (ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1) !=
2423                     ECORE_SB_INVALID_IDX)
2424                         return ECORE_INVAL;
2425         }
2426
2427         /* We need to validate that the SB can actually be relocated.
2428          * This would also handle the previous case where we've explicitly
2429          * stated which IGU SB needs to move.
2430          */
2431         for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2432              igu_sb_id++) {
2433                 p_block = &p_info->entry[igu_sb_id];
2434
2435                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2436                     !(p_block->status & ECORE_IGU_STATUS_FREE) ||
2437                     (!!(p_block->status & ECORE_IGU_STATUS_PF) != b_to_vf)) {
2438                         if (b_to_vf)
2439                                 return ECORE_INVAL;
2440                         else
2441                                 continue;
2442                 }
2443
2444                 break;
2445         }
2446
2447         if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) {
2448                 DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
2449                            "Failed to find a free SB to move\n");
2450                 return ECORE_INVAL;
2451         }
2452
2453         /* At this point, p_block points to the SB we want to relocate */
2454         if (b_to_vf) {
2455                 p_block->status &= ~ECORE_IGU_STATUS_PF;
2456
2457                 /* It doesn't matter which VF number we choose, since we're
2458                  * going to disable the line; But let's keep it in range.
2459                  */
2460                 vf_num = (u16)p_hwfn->p_dev->p_iov_info->first_vf_in_pf;
2461
2462                 p_block->function_id = (u8)vf_num;
2463                 p_block->is_pf = 0;
2464                 p_block->vector_number = 0;
2465
2466                 p_info->usage.cnt--;
2467                 p_info->usage.free_cnt--;
2468                 p_info->usage.iov_cnt++;
2469                 p_info->usage.free_cnt_iov++;
2470
2471                 /* TODO - if SBs aren't really the limiting factor,
2472                  * then it might not be accurate [in the since that
2473                  * we might not need decrement the feature].
2474                  */
2475                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]--;
2476                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]++;
2477         } else {
2478                 p_block->status |= ECORE_IGU_STATUS_PF;
2479                 p_block->function_id = p_hwfn->rel_pf_id;
2480                 p_block->is_pf = 1;
2481                 p_block->vector_number = sb_id + 1;
2482
2483                 p_info->usage.cnt++;
2484                 p_info->usage.free_cnt++;
2485                 p_info->usage.iov_cnt--;
2486                 p_info->usage.free_cnt_iov--;
2487
2488                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]++;
2489                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]--;
2490         }
2491
2492         /* Update the IGU and CAU with the new configuration */
2493         SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2494                   p_block->function_id);
2495         SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2496         SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2497         SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2498                   p_block->vector_number);
2499
2500         ecore_wr(p_hwfn, p_ptt,
2501                  IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id,
2502                  val);
2503
2504         ecore_int_cau_conf_sb(p_hwfn, p_ptt, 0,
2505                               igu_sb_id, vf_num,
2506                               p_block->is_pf ? 0 : 1);
2507
2508         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2509                    "Relocation: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2510                    igu_sb_id, p_block->function_id,
2511                    p_block->is_pf, p_block->vector_number);
2512
2513         return ECORE_SUCCESS;
2514 }
2515
2516 /**
2517  * @brief Initialize igu runtime registers
2518  *
2519  * @param p_hwfn
2520  */
2521 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2522 {
2523         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2524
2525         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2526 }
2527
2528 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2529                           IGU_CMD_INT_ACK_BASE)
2530 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2531                           IGU_CMD_INT_ACK_BASE)
2532 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2533 {
2534         u32 intr_status_hi = 0, intr_status_lo = 0;
2535         u64 intr_status = 0;
2536
2537         intr_status_lo = REG_RD(p_hwfn,
2538                                 GTT_BAR0_MAP_REG_IGU_CMD +
2539                                 LSB_IGU_CMD_ADDR * 8);
2540         intr_status_hi = REG_RD(p_hwfn,
2541                                 GTT_BAR0_MAP_REG_IGU_CMD +
2542                                 MSB_IGU_CMD_ADDR * 8);
2543         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2544
2545         return intr_status;
2546 }
2547
2548 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2549 {
2550         OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2551         p_hwfn->b_sp_dpc_enabled = true;
2552 }
2553
2554 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2555 {
2556         p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2557         if (!p_hwfn->sp_dpc)
2558                 return ECORE_NOMEM;
2559
2560         return ECORE_SUCCESS;
2561 }
2562
2563 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2564 {
2565         OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2566 }
2567
2568 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2569                                      struct ecore_ptt *p_ptt)
2570 {
2571         enum _ecore_status_t rc = ECORE_SUCCESS;
2572
2573         rc = ecore_int_sp_dpc_alloc(p_hwfn);
2574         if (rc != ECORE_SUCCESS) {
2575                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2576                 return rc;
2577         }
2578
2579         rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2580         if (rc != ECORE_SUCCESS) {
2581                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2582                 return rc;
2583         }
2584
2585         rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2586         if (rc != ECORE_SUCCESS)
2587                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2588
2589         return rc;
2590 }
2591
2592 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2593 {
2594         ecore_int_sp_sb_free(p_hwfn);
2595         ecore_int_sb_attn_free(p_hwfn);
2596         ecore_int_sp_dpc_free(p_hwfn);
2597 }
2598
2599 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2600 {
2601         if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2602                 return;
2603
2604         ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2605         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2606         ecore_int_sp_dpc_setup(p_hwfn);
2607 }
2608
2609 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2610                            struct ecore_sb_cnt_info *p_sb_cnt_info)
2611 {
2612         struct ecore_igu_info *p_igu_info = p_hwfn->hw_info.p_igu_info;
2613
2614         if (!p_igu_info || !p_sb_cnt_info)
2615                 return;
2616
2617         OSAL_MEMCPY(p_sb_cnt_info, &p_igu_info->usage,
2618                     sizeof(*p_sb_cnt_info));
2619 }
2620
2621 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2622 {
2623         int i;
2624
2625         for_each_hwfn(p_dev, i)
2626                 p_dev->hwfns[i].b_int_requested = false;
2627 }
2628
2629 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2630 {
2631         p_dev->attn_clr_en = clr_enable;
2632 }
2633
2634 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2635                                              struct ecore_ptt *p_ptt,
2636                                              u8 timer_res, u16 sb_id, bool tx)
2637 {
2638         struct cau_sb_entry sb_entry;
2639         enum _ecore_status_t rc;
2640
2641         if (!p_hwfn->hw_init_done) {
2642                 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2643                 return ECORE_INVAL;
2644         }
2645
2646         rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2647                                  sb_id * sizeof(u64),
2648                                  (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2649         if (rc != ECORE_SUCCESS) {
2650                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2651                 return rc;
2652         }
2653
2654         if (tx)
2655                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2656         else
2657                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2658
2659         rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2660                                  (u64)(osal_uintptr_t)&sb_entry,
2661                                  CAU_REG_SB_VAR_MEMORY +
2662                                  sb_id * sizeof(u64), 2, 0);
2663         if (rc != ECORE_SUCCESS) {
2664                 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2665                 return rc;
2666         }
2667
2668         return rc;
2669 }
2670
2671 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
2672                                           struct ecore_ptt *p_ptt,
2673                                           struct ecore_sb_info *p_sb,
2674                                           struct ecore_sb_info_dbg *p_info)
2675 {
2676         u16 sbid = p_sb->igu_sb_id;
2677         int i;
2678
2679         if (IS_VF(p_hwfn->p_dev))
2680                 return ECORE_INVAL;
2681
2682         if (sbid > NUM_OF_SBS(p_hwfn->p_dev))
2683                 return ECORE_INVAL;
2684
2685         p_info->igu_prod = ecore_rd(p_hwfn, p_ptt,
2686                                     IGU_REG_PRODUCER_MEMORY + sbid * 4);
2687         p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
2688                                     IGU_REG_CONSUMER_MEM + sbid * 4);
2689
2690         for (i = 0; i < PIS_PER_SB_E4; i++)
2691                 p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
2692                                               CAU_REG_PI_MEMORY +
2693                                               sbid * 4 * PIS_PER_SB_E4 +
2694                                               i * 4);
2695
2696         return ECORE_SUCCESS;
2697 }
2698
2699 void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn)
2700 {
2701         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2702         struct ecore_ptt *p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
2703                                                              RESERVED_PTT_DPC);
2704         int i;
2705
2706         /* Do not reorder the following cleanup sequence */
2707         /* Ack all attentions */
2708         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff);
2709
2710         /* Clear driver attention */
2711         ecore_wr(p_hwfn,  p_dpc_ptt,
2712                 ((p_hwfn->rel_pf_id << 3) + MISC_REG_AEU_GENERAL_ATTN_0), 0);
2713
2714         /* Clear per-PF IGU registers to restore them as if the IGU
2715          * was reset for this PF
2716          */
2717         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2718         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2719         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
2720
2721         /* Execute IGU clean up*/
2722         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1);
2723
2724         /* Clear Stats */
2725         ecore_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED, 0);
2726
2727         for (i = 0; i < IGU_REG_PBA_STS_PF_SIZE; i++)
2728                 ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0);
2729 }