drivers/net/qede/base/ecore_int.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_spq.h"
  12 #include "reg_addr.h"
  13 #include "ecore_gtt_reg_addr.h"
  14 #include "ecore_init_ops.h"
  15 #include "ecore_rt_defs.h"
  16 #include "ecore_int.h"
  17 #include "reg_addr.h"
  18 #include "ecore_hw.h"
  19 #include "ecore_sriov.h"
  20 #include "ecore_vf.h"
  21 #include "ecore_hw_defs.h"
  22 #include "ecore_hsi_common.h"
  23 #include "ecore_mcp.h"
  24 #include "ecore_attn_values.h"
  25
  26 struct ecore_pi_info {
  27         ecore_int_comp_cb_t comp_cb;
  28         void *cookie;           /* Will be sent to the compl cb function */
  29 };
  30
  31 struct ecore_sb_sp_info {
  32         struct ecore_sb_info sb_info;
  33         /* per protocol index data */
  34         struct ecore_pi_info pi_info_arr[PIS_PER_SB];
  35 };
  36
  37 enum ecore_attention_type {
  38         ECORE_ATTN_TYPE_ATTN,
  39         ECORE_ATTN_TYPE_PARITY,
  40 };
  41
  42 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  43         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  44
  45 struct aeu_invert_reg_bit {
  46         char bit_name[30];
  47
  48 #define ATTENTION_PARITY                (1 << 0)
  49
  50 #define ATTENTION_LENGTH_MASK           (0x00000ff0)
  51 #define ATTENTION_LENGTH_SHIFT          (4)
  52 #define ATTENTION_LENGTH(flags)         (((flags) & ATTENTION_LENGTH_MASK) >> \
  53                                          ATTENTION_LENGTH_SHIFT)
  54 #define ATTENTION_SINGLE                (1 << ATTENTION_LENGTH_SHIFT)
  55 #define ATTENTION_PAR                   (ATTENTION_SINGLE | ATTENTION_PARITY)
  56 #define ATTENTION_PAR_INT               ((2 << ATTENTION_LENGTH_SHIFT) | \
  57                                          ATTENTION_PARITY)
  58
  59 /* Multiple bits start with this offset */
  60 #define ATTENTION_OFFSET_MASK           (0x000ff000)
  61 #define ATTENTION_OFFSET_SHIFT          (12)
  62
  63 #define ATTENTION_CLEAR_ENABLE          (1 << 28)
  64 #define ATTENTION_FW_DUMP               (1 << 29)
  65 #define ATTENTION_PANIC_DUMP            (1 << 30)
  66         unsigned int flags;
  67
  68         /* Callback to call if attention will be triggered */
  69         enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
  70
  71         enum block_id block_index;
  72 };
  73
  74 struct aeu_invert_reg {
  75         struct aeu_invert_reg_bit bits[32];
  76 };
  77
  78 #define MAX_ATTN_GRPS           (8)
  79 #define NUM_ATTN_REGS           (9)
  80
  81 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
  82 {
  83         u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
  84
  85         DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", tmp);
  86         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 0xffffffff);
  87
  88         return ECORE_SUCCESS;
  89 }
  90
  91 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK         (0x3c000)
  92 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT        (14)
  93 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK         (0x03fc0)
  94 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT        (6)
  95 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK      (0x00020)
  96 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT     (5)
  97 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK     (0x0001e)
  98 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT    (1)
  99 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK      (0x1)
 100 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT     (0)
 101 #define ECORE_PSWHST_ATTENTION_VF_DISABLED              (0x1)
 102 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS         (0x1)
 103 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK         (0x1)
 104 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT        (0)
 105 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK     (0x1e)
 106 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT    (1)
 107 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK   (0x20)
 108 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT  (5)
 109 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK      (0x3fc0)
 110 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT     (6)
 111 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK      (0x3c000)
 112 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT     (14)
 113 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK    (0x3fc0000)
 114 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT   (18)
 115 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
 116 {
 117         u32 tmp =
 118             ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 119                      PSWHST_REG_VF_DISABLED_ERROR_VALID);
 120
 121         /* Disabled VF access */
 122         if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
 123                 u32 addr, data;
 124
 125                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 126                                 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
 127                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 128                                 PSWHST_REG_VF_DISABLED_ERROR_DATA);
 129                 DP_INFO(p_hwfn->p_dev,
 130                         "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x]"
 131                         " Write [0x%02x] Addr [0x%08x]\n",
 132                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK)
 133                              >> ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
 134                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK)
 135                              >> ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
 136                         (u8)((data &
 137                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
 138                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
 139                         (u8)((data &
 140                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
 141                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
 142                         (u8)((data &
 143                               ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
 144                               ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
 145                         addr);
 146         }
 147
 148         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 149                        PSWHST_REG_INCORRECT_ACCESS_VALID);
 150         if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
 151                 u32 addr, data, length;
 152
 153                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 154                                 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
 155                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 156                                 PSWHST_REG_INCORRECT_ACCESS_DATA);
 157                 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 158                                   PSWHST_REG_INCORRECT_ACCESS_LENGTH);
 159
 160                 DP_INFO(p_hwfn->p_dev,
 161                         "Incorrect access to %08x of length %08x - PF [%02x]"
 162                         " VF [%04x] [valid %02x] client [%02x] write [%02x]"
 163                         " Byte-Enable [%04x] [%08x]\n",
 164                         addr, length,
 165                         (u8)((data &
 166                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
 167                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
 168                         (u8)((data &
 169                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
 170                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
 171                         (u8)((data &
 172                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
 173                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
 174                         (u8)((data &
 175                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
 176                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
 177                         (u8)((data &
 178                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
 179                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
 180                         (u8)((data &
 181                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
 182                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
 183                         data);
 184         }
 185
 186         /* TODO - We know 'some' of these are legal due to virtualization,
 187          * but is it true for all of them?
 188          */
 189         return ECORE_SUCCESS;
 190 }
 191
 192 #define ECORE_GRC_ATTENTION_VALID_BIT           (1 << 0)
 193 #define ECORE_GRC_ATTENTION_ADDRESS_MASK        (0x7fffff << 0)
 194 #define ECORE_GRC_ATTENTION_RDWR_BIT            (1 << 23)
 195 #define ECORE_GRC_ATTENTION_MASTER_MASK         (0xf << 24)
 196 #define ECORE_GRC_ATTENTION_MASTER_SHIFT        (24)
 197 #define ECORE_GRC_ATTENTION_PF_MASK             (0xf)
 198 #define ECORE_GRC_ATTENTION_VF_MASK             (0xff << 4)
 199 #define ECORE_GRC_ATTENTION_VF_SHIFT            (4)
 200 #define ECORE_GRC_ATTENTION_PRIV_MASK           (0x3 << 14)
 201 #define ECORE_GRC_ATTENTION_PRIV_SHIFT          (14)
 202 #define ECORE_GRC_ATTENTION_PRIV_VF             (0)
 203 static const char *grc_timeout_attn_master_to_str(u8 master)
 204 {
 205         switch (master) {
 206         case 1:
 207                 return "PXP";
 208         case 2:
 209                 return "MCP";
 210         case 3:
 211                 return "MSDM";
 212         case 4:
 213                 return "PSDM";
 214         case 5:
 215                 return "YSDM";
 216         case 6:
 217                 return "USDM";
 218         case 7:
 219                 return "TSDM";
 220         case 8:
 221                 return "XSDM";
 222         case 9:
 223                 return "DBU";
 224         case 10:
 225                 return "DMAE";
 226         default:
 227                 return "Unknown";
 228         }
 229 }
 230
 231 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
 232 {
 233         u32 tmp, tmp2;
 234
 235         /* We've already cleared the timeout interrupt register, so we learn
 236          * of interrupts via the validity register
 237          */
 238         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 239                        GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
 240         if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT))
 241                 goto out;
 242
 243         /* Read the GRC timeout information */
 244         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 245                        GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
 246         tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 247                         GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
 248
 249         DP_INFO(p_hwfn->p_dev,
 250                 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s]"
 251                 " [PF: %02x %s %02x]\n",
 252                 tmp2, tmp,
 253                 (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
 254                 (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
 255                 grc_timeout_attn_master_to_str((tmp &
 256                                         ECORE_GRC_ATTENTION_MASTER_MASK) >>
 257                                        ECORE_GRC_ATTENTION_MASTER_SHIFT),
 258                 (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
 259                 (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
 260                   ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
 261                  ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
 262                 (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
 263                 ECORE_GRC_ATTENTION_VF_SHIFT);
 264
 265 out:
 266         /* Regardles of anything else, clean the validity bit */
 267         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 268                  GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
 269         return ECORE_SUCCESS;
 270 }
 271
 272 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
 273 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
 274 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
 275 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
 276 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
 277 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
 278 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
 279 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
 280 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME      (1 << 22)
 281 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
 282 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
 283 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
 284 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
 285 static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
 286 {
 287         u32 tmp;
 288
 289         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 290                        PGLUE_B_REG_TX_ERR_WR_DETAILS2);
 291         if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
 292                 u32 addr_lo, addr_hi, details;
 293
 294                 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 295                                    PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
 296                 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 297                                    PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
 298                 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 299                                    PGLUE_B_REG_TX_ERR_WR_DETAILS);
 300
 301                 DP_INFO(p_hwfn,
 302                         "Illegal write by chip to [%08x:%08x] blocked."
 303                         "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]"
 304                         " Details2 %08x [Was_error %02x BME deassert %02x"
 305                         " FID_enable deassert %02x]\n",
 306                         addr_hi, addr_lo, details,
 307                         (u8)((details &
 308                               ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 309                              ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 310                         (u8)((details &
 311                               ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 312                              ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 313                         (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID)
 314                              ? 1 : 0), tmp,
 315                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1
 316                              : 0),
 317                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 :
 318                              0),
 319                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1
 320                              : 0));
 321         }
 322
 323         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 324                        PGLUE_B_REG_TX_ERR_RD_DETAILS2);
 325         if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
 326                 u32 addr_lo, addr_hi, details;
 327
 328                 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 329                                    PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
 330                 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 331                                    PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
 332                 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 333                                    PGLUE_B_REG_TX_ERR_RD_DETAILS);
 334
 335                 DP_INFO(p_hwfn,
 336                         "Illegal read by chip from [%08x:%08x] blocked."
 337                         " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]"
 338                         " Details2 %08x [Was_error %02x BME deassert %02x"
 339                         " FID_enable deassert %02x]\n",
 340                         addr_hi, addr_lo, details,
 341                         (u8)((details &
 342                               ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 343                              ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 344                         (u8)((details &
 345                               ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 346                              ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 347                         (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID)
 348                              ? 1 : 0), tmp,
 349                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1
 350                              : 0),
 351                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 :
 352                              0),
 353                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1
 354                              : 0));
 355         }
 356
 357         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 358                        PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
 359         if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
 360                 DP_INFO(p_hwfn, "ICPL error - %08x\n", tmp);
 361
 362         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 363                        PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
 364         if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
 365                 u32 addr_hi, addr_lo;
 366
 367                 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 368                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
 369                 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 370                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
 371
 372                 DP_INFO(p_hwfn, "ICPL error - %08x [Address %08x:%08x]\n",
 373                         tmp, addr_hi, addr_lo);
 374         }
 375
 376         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 377                        PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
 378         if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
 379                 u32 addr_hi, addr_lo, details;
 380
 381                 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 382                                    PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
 383                 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 384                                    PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
 385                 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 386                                    PGLUE_B_REG_VF_ILT_ERR_DETAILS);
 387
 388                 DP_INFO(p_hwfn,
 389                         "ILT error - Details %08x Details2 %08x"
 390                         " [Address %08x:%08x]\n",
 391                         details, tmp, addr_hi, addr_lo);
 392         }
 393
 394         /* Clear the indications */
 395         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 396                  PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
 397
 398         return ECORE_SUCCESS;
 399 }
 400
 401 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
 402 {
 403         DP_NOTICE(p_hwfn, false, "FW assertion!\n");
 404
 405         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
 406
 407         return ECORE_INVAL;
 408 }
 409
 410 static enum _ecore_status_t
 411 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
 412 {
 413         DP_INFO(p_hwfn, "General attention 35!\n");
 414
 415         return ECORE_SUCCESS;
 416 }
 417
 418 #define ECORE_DORQ_ATTENTION_REASON_MASK (0xfffff)
 419 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
 420 #define ECORE_DORQ_ATTENTION_SIZE_MASK   (0x7f)
 421 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT  (16)
 422
 423 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
 424 {
 425         u32 reason;
 426
 427         reason = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
 428             ECORE_DORQ_ATTENTION_REASON_MASK;
 429         if (reason) {
 430                 u32 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 431                                        DORQ_REG_DB_DROP_DETAILS);
 432
 433                 DP_INFO(p_hwfn->p_dev,
 434                         "DORQ db_drop: address 0x%08x Opaque FID 0x%04x"
 435                         " Size [bytes] 0x%08x Reason: 0x%08x\n",
 436                         ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 437                                  DORQ_REG_DB_DROP_DETAILS_ADDRESS),
 438                         (u16)(details & ECORE_DORQ_ATTENTION_OPAQUE_MASK),
 439                         ((details & ECORE_DORQ_ATTENTION_SIZE_MASK) >>
 440                          ECORE_DORQ_ATTENTION_SIZE_SHIFT) * 4, reason);
 441         }
 442
 443         return ECORE_INVAL;
 444 }
 445
 446 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
 447 {
 448 #ifndef ASIC_ONLY
 449         if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
 450                 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 451                                    TM_REG_INT_STS_1);
 452
 453                 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
 454                             TM_REG_INT_STS_1_PEND_CONN_SCAN))
 455                         return ECORE_INVAL;
 456
 457                 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
 458                            TM_REG_INT_STS_1_PEND_CONN_SCAN))
 459                         DP_INFO(p_hwfn,
 460                                 "TM attention on emulation - most likely"
 461                                 " results of clock-ratios\n");
 462                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
 463                 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
 464                     TM_REG_INT_MASK_1_PEND_TASK_SCAN;
 465                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
 466
 467                 return ECORE_SUCCESS;
 468         }
 469 #endif
 470
 471         return ECORE_INVAL;
 472 }
 473
 474 /* Notice aeu_invert_reg must be defined in the same order of bits as HW;  */
 475 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
 476         {
 477          {                      /* After Invert 1 */
 478           {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 479            MAX_BLOCK_ID},
 480           }
 481          },
 482
 483         {
 484          {                      /* After Invert 2 */
 485           {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 486           {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 487           {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglub_rbc_attn_cb,
 488            BLOCK_PGLUE_B},
 489           {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 490           {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 491           {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 492           {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 493           {"SW timers #%d",
 494            (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT),
 495            OSAL_NULL, MAX_BLOCK_ID},
 496           {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 497            BLOCK_PGLCS},
 498           }
 499          },
 500
 501         {
 502          {                      /* After Invert 3 */
 503           {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 504            MAX_BLOCK_ID},
 505           }
 506          },
 507
 508         {
 509          {                      /* After Invert 4 */
 510           {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 511            ecore_fw_assertion, MAX_BLOCK_ID},
 512           {"General Attention %d",
 513            (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT),
 514            OSAL_NULL, MAX_BLOCK_ID},
 515           {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 516            ecore_general_attention_35, MAX_BLOCK_ID},
 517           {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 518            BLOCK_CNIG},
 519           {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
 520           {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 521           {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 522           {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 523           {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 524           {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 525           {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 526            MAX_BLOCK_ID},
 527           {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
 528           {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
 529           {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
 530           {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
 531           {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
 532           }
 533          },
 534
 535         {
 536          {                      /* After Invert 5 */
 537           {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
 538           {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
 539           {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
 540           {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
 541           {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
 542           {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
 543           {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
 544           {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
 545           {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
 546           {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
 547           {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
 548           {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
 549           {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
 550           {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
 551           {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
 552           {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM},
 553           }
 554          },
 555
 556         {
 557          {                      /* After Invert 6 */
 558           {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
 559           {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
 560           {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
 561           {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
 562           {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
 563           {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
 564           {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
 565           {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
 566           {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
 567           {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
 568           {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
 569           {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
 570           {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
 571           {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
 572           {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
 573           {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
 574           }
 575          },
 576
 577         {
 578          {                      /* After Invert 7 */
 579           {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
 580           {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
 581           {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
 582           {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
 583           {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 584           {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
 585           {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
 586           {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
 587           {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
 588           {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
 589           {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
 590           {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
 591           {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
 592           {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
 593           {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
 594           {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 595           {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
 596           }
 597          },
 598
 599         {
 600          {                      /* After Invert 8 */
 601           {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
 602           {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
 603           {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
 604           {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
 605           {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
 606           {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
 607           {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
 608           {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
 609           {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
 610           {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
 611           {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 612           {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 613           {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 614           {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 615           {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 616           {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 617           {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
 618           {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 619           {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 620           {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 621           {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 622            MAX_BLOCK_ID},
 623           }
 624          },
 625
 626         {
 627          {                      /* After Invert 9 */
 628           {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 629           {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL,
 630            MAX_BLOCK_ID},
 631           {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 632           {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 633           {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 634            MAX_BLOCK_ID},
 635           }
 636          },
 637
 638 };
 639
 640 #define ATTN_STATE_BITS         (0xfff)
 641 #define ATTN_BITS_MASKABLE      (0x3ff)
 642 struct ecore_sb_attn_info {
 643         /* Virtual & Physical address of the SB */
 644         struct atten_status_block *sb_attn;
 645         dma_addr_t sb_phys;
 646
 647         /* Last seen running index */
 648         u16 index;
 649
 650         /* A mask of the AEU bits resulting in a parity error */
 651         u32 parity_mask[NUM_ATTN_REGS];
 652
 653         /* A pointer to the attention description structure */
 654         struct aeu_invert_reg *p_aeu_desc;
 655
 656         /* Previously asserted attentions, which are still unasserted */
 657         u16 known_attn;
 658
 659         /* Cleanup address for the link's general hw attention */
 660         u32 mfw_attn_addr;
 661 };
 662
 663 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
 664                                  struct ecore_sb_attn_info *p_sb_desc)
 665 {
 666         u16 rc = 0, index;
 667
 668         OSAL_MMIOWB(p_hwfn->p_dev);
 669
 670         index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
 671         if (p_sb_desc->index != index) {
 672                 p_sb_desc->index = index;
 673                 rc = ECORE_SB_ATT_IDX;
 674         }
 675
 676         OSAL_MMIOWB(p_hwfn->p_dev);
 677
 678         return rc;
 679 }
 680
 681 /**
 682  * @brief ecore_int_assertion - handles asserted attention bits
 683  *
 684  * @param p_hwfn
 685  * @param asserted_bits newly asserted bits
 686  * @return enum _ecore_status_t
 687  */
 688 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
 689                                                 u16 asserted_bits)
 690 {
 691         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 692         u32 igu_mask;
 693
 694         /* Mask the source of the attention in the IGU */
 695         igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 696                             IGU_REG_ATTENTION_ENABLE);
 697         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 698                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 699         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 700         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 701
 702         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 703                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 704                    sb_attn_sw->known_attn,
 705                    sb_attn_sw->known_attn | asserted_bits);
 706         sb_attn_sw->known_attn |= asserted_bits;
 707
 708         /* Handle MCP events */
 709         if (asserted_bits & 0x100) {
 710                 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 711                 /* Clean the MCP attention */
 712                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 713                          sb_attn_sw->mfw_attn_addr, 0);
 714         }
 715
 716         /* FIXME - this will change once we'll have GOOD gtt definitions */
 717         DIRECT_REG_WR(p_hwfn,
 718                       (u8 OSAL_IOMEM *) p_hwfn->regview +
 719                       GTT_BAR0_MAP_REG_IGU_CMD +
 720                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 721                         IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
 722
 723         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
 724                    asserted_bits);
 725
 726         return ECORE_SUCCESS;
 727 }
 728
 729 static void ecore_int_deassertion_print_bit(struct ecore_hwfn *p_hwfn,
 730                                             struct attn_hw_reg *p_reg_desc,
 731                                             struct attn_hw_block *p_block,
 732                                             enum ecore_attention_type type,
 733                                             u32 val, u32 mask)
 734 {
 735         int j;
 736 #ifdef ATTN_DESC
 737         const char **description;
 738
 739         if (type == ECORE_ATTN_TYPE_ATTN)
 740                 description = p_block->int_desc;
 741         else
 742                 description = p_block->prty_desc;
 743 #endif
 744
 745         for (j = 0; j < p_reg_desc->num_of_bits; j++) {
 746                 if (val & (1 << j)) {
 747 #ifdef ATTN_DESC
 748                         DP_NOTICE(p_hwfn, false,
 749                                   "%s (%s): %s [reg %d [0x%08x], bit %d]%s\n",
 750                                   p_block->name,
 751                                   type == ECORE_ATTN_TYPE_ATTN ? "Interrupt" :
 752                                   "Parity",
 753                                   description[p_reg_desc->bit_attn_idx[j]],
 754                                   p_reg_desc->reg_idx,
 755                                   p_reg_desc->sts_addr, j,
 756                                   (mask & (1 << j)) ? " [MASKED]" : "");
 757 #else
 758                         DP_NOTICE(p_hwfn->p_dev, false,
 759                                   "%s (%s): [reg %d [0x%08x], bit %d]%s\n",
 760                                   p_block->name,
 761                                   type == ECORE_ATTN_TYPE_ATTN ? "Interrupt" :
 762                                   "Parity",
 763                                   p_reg_desc->reg_idx,
 764                                   p_reg_desc->sts_addr, j,
 765                                   (mask & (1 << j)) ? " [MASKED]" : "");
 766 #endif
 767                 }
 768         }
 769 }
 770
 771 /**
 772  * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
 773  * cause of the attention
 774  *
 775  * @param p_hwfn
 776  * @param p_aeu - descriptor of an AEU bit which caused the attention
 777  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
 778  *  this bit to this group.
 779  * @param bit_index - index of this bit in the aeu_en_reg
 780  *
 781  * @return enum _ecore_status_t
 782  */
 783 static enum _ecore_status_t
 784 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
 785                               struct aeu_invert_reg_bit *p_aeu,
 786                               u32 aeu_en_reg,
 787                               const char *p_bit_name,
 788                               u32 bitmask)
 789 {
 790         enum _ecore_status_t rc = ECORE_INVAL;
 791         u32 val, mask;
 792
 793 #ifndef REMOVE_DBG
 794         u32 interrupts[20];     /* TODO- change into HSI define once supplied */
 795
 796         OSAL_MEMSET(interrupts, 0, sizeof(u32) * 20);   /* FIXME real size) */
 797 #endif
 798
 799         DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
 800                 p_bit_name, bitmask);
 801
 802         /* Call callback before clearing the interrupt status */
 803         if (p_aeu->cb) {
 804                 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
 805                         p_bit_name);
 806                 rc = p_aeu->cb(p_hwfn);
 807         }
 808
 809         /* Print HW block interrupt registers */
 810         if (p_aeu->block_index != MAX_BLOCK_ID)
 811                 DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
 812                           p_aeu->block_index, ATTN_TYPE_INTERRUPT);
 813
 814         /* Reach assertion if attention is fatal */
 815         if (rc != ECORE_SUCCESS) {
 816                 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
 817                           p_bit_name);
 818
 819                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
 820         }
 821
 822         /* Prevent this Attention from being asserted in the future */
 823         if (p_aeu->flags & ATTENTION_CLEAR_ENABLE) {
 824                 u32 val;
 825                 u32 mask = ~bitmask;
 826                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 827                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
 828                 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
 829                         p_bit_name);
 830         }
 831
 832         if (p_aeu->flags & (ATTENTION_FW_DUMP | ATTENTION_PANIC_DUMP)) {
 833                 /* @@@TODO - what to dump? <yuvalmin 04/02/13> */
 834                 DP_ERR(p_hwfn->p_dev, "`%s' - Dumps aren't implemented yet\n",
 835                        p_aeu->bit_name);
 836                 return ECORE_NOTIMPL;
 837         }
 838
 839         return rc;
 840 }
 841
 842 /**
 843  * @brief ecore_int_deassertion_parity - handle a single parity AEU source
 844  *
 845  * @param p_hwfn
 846  * @param p_aeu - descriptor of an AEU bit which caused the
 847  *              parity
 848  * @param bit_index
 849  */
 850 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
 851                                          struct aeu_invert_reg_bit *p_aeu,
 852                                          u8 bit_index)
 853 {
 854         u32 block_id = p_aeu->block_index;
 855
 856         DP_INFO(p_hwfn->p_dev, "%s[%d] parity attention is set\n",
 857                 p_aeu->bit_name, bit_index);
 858
 859         if (block_id != MAX_BLOCK_ID)
 860                 return;
 861
 862         /* In A0, there's a single parity bit for several blocks */
 863         if (block_id == BLOCK_BTB) {
 864                 DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
 865                           BLOCK_OPTE, ATTN_TYPE_PARITY);
 866                 DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
 867                           BLOCK_MCP, ATTN_TYPE_PARITY);
 868         }
 869 }
 870
 871 /**
 872  * @brief - handles deassertion of previously asserted attentions.
 873  *
 874  * @param p_hwfn
 875  * @param deasserted_bits - newly deasserted bits
 876  * @return enum _ecore_status_t
 877  *
 878  */
 879 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
 880                                                   u16 deasserted_bits)
 881 {
 882         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 883         u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask;
 884         bool b_parity = false;
 885         u8 i, j, k, bit_idx;
 886         enum _ecore_status_t rc = ECORE_SUCCESS;
 887
 888         /* Read the attention registers in the AEU */
 889         for (i = 0; i < NUM_ATTN_REGS; i++) {
 890                 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 891                                           MISC_REG_AEU_AFTER_INVERT_1_IGU +
 892                                           i * 0x4);
 893                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 894                            "Deasserted bits [%d]: %08x\n", i, aeu_inv_arr[i]);
 895         }
 896
 897         /* Handle parity attentions first */
 898         for (i = 0; i < NUM_ATTN_REGS; i++) {
 899                 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
 900                 u32 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 901                                   MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
 902                                   i * sizeof(u32));
 903
 904                 u32 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
 905
 906                 /* Skip register in which no parity bit is currently set */
 907                 if (!parities)
 908                         continue;
 909
 910                 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
 911                         struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
 912
 913                         if ((p_bit->flags & ATTENTION_PARITY) &&
 914                             !!(parities & (1 << bit_idx))) {
 915                                 ecore_int_deassertion_parity(p_hwfn, p_bit,
 916                                                              bit_idx);
 917                                 b_parity = true;
 918                         }
 919
 920                         bit_idx += ATTENTION_LENGTH(p_bit->flags);
 921                 }
 922         }
 923
 924         /* Find non-parity cause for attention and act */
 925         for (k = 0; k < MAX_ATTN_GRPS; k++) {
 926                 struct aeu_invert_reg_bit *p_aeu;
 927
 928                 /* Handle only groups whose attention is currently deasserted */
 929                 if (!(deasserted_bits & (1 << k)))
 930                         continue;
 931
 932                 for (i = 0; i < NUM_ATTN_REGS; i++) {
 933                         u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
 934                             i * sizeof(u32) + k * sizeof(u32) * NUM_ATTN_REGS;
 935                         u32 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
 936                         u32 bits = aeu_inv_arr[i] & en;
 937
 938                         /* Skip if no bit from this group is currently set */
 939                         if (!bits)
 940                                 continue;
 941
 942                         /* Find all set bits from current register which belong
 943                          * to current group, making them responsible for the
 944                          * previous assertion.
 945                          */
 946                         for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
 947                                 unsigned long bitmask;
 948                                 u8 bit, bit_len;
 949
 950                                 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
 951
 952                                 /* No need to handle attention-only bits */
 953                                 if (p_aeu->flags == ATTENTION_PAR)
 954                                         continue;
 955
 956                                 bit = bit_idx;
 957                                 bit_len = ATTENTION_LENGTH(p_aeu->flags);
 958                                 if (p_aeu->flags & ATTENTION_PAR_INT) {
 959                                         /* Skip Parity */
 960                                         bit++;
 961                                         bit_len--;
 962                                 }
 963
 964                                 bitmask = bits & (((1 << bit_len) - 1) << bit);
 965                                 if (bitmask) {
 966                                         u32 flags = p_aeu->flags;
 967                                         char bit_name[30];
 968
 969                                         bit = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
 970                                                                 bit_len);
 971
 972                                         /* Some bits represent more than a
 973                                          * a single interrupt. Correctly print
 974                                          * their name.
 975                                          */
 976                                         if (ATTENTION_LENGTH(flags) > 2 ||
 977                                             ((flags & ATTENTION_PAR_INT) &&
 978                                             ATTENTION_LENGTH(flags) > 1))
 979                                                 OSAL_SNPRINTF(bit_name, 30,
 980                                                               p_aeu->bit_name,
 981                                                               bit);
 982                                         else
 983                                                 OSAL_STRNCPY(bit_name,
 984                                                              p_aeu->bit_name,
 985                                                              30);
 986                                         /* Handle source of the attention */
 987                                         ecore_int_deassertion_aeu_bit(p_hwfn,
 988                                                                       p_aeu,
 989                                                                       aeu_en,
 990                                                                       bit_name,
 991                                                                       bitmask);
 992                                 }
 993
 994                                 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
 995                         }
 996                 }
 997         }
 998
 999         /* Clear IGU indication for the deasserted bits */
1000         /* FIXME - this will change once we'll have GOOD gtt definitions */
1001         DIRECT_REG_WR(p_hwfn,
1002                       (u8 OSAL_IOMEM *) p_hwfn->regview +
1003                       GTT_BAR0_MAP_REG_IGU_CMD +
1004                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1005                         IGU_CMD_INT_ACK_BASE) << 3), ~((u32)deasserted_bits));
1006
1007         /* Unmask deasserted attentions in IGU */
1008         aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1009                             IGU_REG_ATTENTION_ENABLE);
1010         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1011         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1012
1013         /* Clear deassertion from inner state */
1014         sb_attn_sw->known_attn &= ~deasserted_bits;
1015
1016         return rc;
1017 }
1018
1019 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
1020 {
1021         struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1022         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1023         u16 index = 0, asserted_bits, deasserted_bits;
1024         enum _ecore_status_t rc = ECORE_SUCCESS;
1025         u32 attn_bits = 0, attn_acks = 0;
1026
1027         /* Read current attention bits/acks - safeguard against attentions
1028          * by guaranting work on a synchronized timeframe
1029          */
1030         do {
1031                 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1032                 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1033                 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1034         } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1035         p_sb_attn->sb_index = index;
1036
1037         /* Attention / Deassertion are meaningful (and in correct state)
1038          * only when they differ and consistent with known state - deassertion
1039          * when previous attention & current ack, and assertion when current
1040          * attention with no previous attention
1041          */
1042         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1043             ~p_sb_attn_sw->known_attn;
1044         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1045             p_sb_attn_sw->known_attn;
1046
1047         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1048                 DP_INFO(p_hwfn,
1049                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1050                         index, attn_bits, attn_acks, asserted_bits,
1051                         deasserted_bits, p_sb_attn_sw->known_attn);
1052         else if (asserted_bits == 0x100)
1053                 DP_INFO(p_hwfn, "MFW indication via attention\n");
1054         else
1055                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1056                            "MFW indication [deassertion]\n");
1057
1058         if (asserted_bits) {
1059                 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1060                 if (rc)
1061                         return rc;
1062         }
1063
1064         if (deasserted_bits)
1065                 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1066
1067         return rc;
1068 }
1069
1070 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1071                               void OSAL_IOMEM *igu_addr, u32 ack_cons)
1072 {
1073         struct igu_prod_cons_update igu_ack = { 0 };
1074
1075         igu_ack.sb_id_and_flags =
1076             ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1077              (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1078              (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1079              (IGU_SEG_ACCESS_ATTN <<
1080               IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1081
1082         DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1083
1084         /* Both segments (interrupts & acks) are written to same place address;
1085          * Need to guarantee all commands will be received (in-order) by HW.
1086          */
1087         OSAL_MMIOWB(p_hwfn->p_dev);
1088         OSAL_BARRIER(p_hwfn->p_dev);
1089 }
1090
1091 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1092 {
1093         struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1094         struct ecore_pi_info *pi_info = OSAL_NULL;
1095         struct ecore_sb_attn_info *sb_attn;
1096         struct ecore_sb_info *sb_info;
1097         static int arr_size;
1098         u16 rc = 0;
1099
1100         if (!p_hwfn) {
1101                 DP_ERR(p_hwfn->p_dev, "DPC called - no hwfn!\n");
1102                 return;
1103         }
1104
1105         if (!p_hwfn->p_sp_sb) {
1106                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1107                 return;
1108         }
1109
1110         sb_info = &p_hwfn->p_sp_sb->sb_info;
1111         arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1112         if (!sb_info) {
1113                 DP_ERR(p_hwfn->p_dev,
1114                        "Status block is NULL - cannot ack interrupts\n");
1115                 return;
1116         }
1117
1118         if (!p_hwfn->p_sb_attn) {
1119                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1120                 return;
1121         }
1122         sb_attn = p_hwfn->p_sb_attn;
1123
1124         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1125                    p_hwfn, p_hwfn->my_id);
1126
1127         /* Disable ack for def status block. Required both for msix +
1128          * inta in non-mask mode, in inta does no harm.
1129          */
1130         ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1131
1132         /* Gather Interrupts/Attentions information */
1133         if (!sb_info->sb_virt) {
1134                 DP_ERR(p_hwfn->p_dev,
1135                        "Interrupt Status block is NULL -"
1136                        " cannot check for new interrupts!\n");
1137         } else {
1138                 u32 tmp_index = sb_info->sb_ack;
1139                 rc = ecore_sb_update_sb_idx(sb_info);
1140                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1141                            "Interrupt indices: 0x%08x --> 0x%08x\n",
1142                            tmp_index, sb_info->sb_ack);
1143         }
1144
1145         if (!sb_attn || !sb_attn->sb_attn) {
1146                 DP_ERR(p_hwfn->p_dev,
1147                        "Attentions Status block is NULL -"
1148                        " cannot check for new attentions!\n");
1149         } else {
1150                 u16 tmp_index = sb_attn->index;
1151
1152                 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1153                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1154                            "Attention indices: 0x%08x --> 0x%08x\n",
1155                            tmp_index, sb_attn->index);
1156         }
1157
1158         /* Check if we expect interrupts at this time. if not just ack them */
1159         if (!(rc & ECORE_SB_EVENT_MASK)) {
1160                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1161                 return;
1162         }
1163
1164 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1165         if (!p_hwfn->p_dpc_ptt) {
1166                 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1167                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1168                 return;
1169         }
1170
1171         if (rc & ECORE_SB_ATT_IDX)
1172                 ecore_int_attentions(p_hwfn);
1173
1174         if (rc & ECORE_SB_IDX) {
1175                 int pi;
1176
1177                 /* Since we only looked at the SB index, it's possible more
1178                  * than a single protocol-index on the SB incremented.
1179                  * Iterate over all configured protocol indices and check
1180                  * whether something happened for each.
1181                  */
1182                 for (pi = 0; pi < arr_size; pi++) {
1183                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1184                         if (pi_info->comp_cb != OSAL_NULL)
1185                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1186                 }
1187         }
1188
1189         if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1190                 /* This should be done before the interrupts are enabled,
1191                  * since otherwise a new attention will be generated.
1192                  */
1193                 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1194         }
1195
1196         ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1197 }
1198
1199 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1200 {
1201         struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1202
1203         if (!p_sb)
1204                 return;
1205
1206         if (p_sb->sb_attn) {
1207                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1208                                        p_sb->sb_phys,
1209                                        SB_ATTN_ALIGNED_SIZE(p_hwfn));
1210         }
1211         OSAL_FREE(p_hwfn->p_dev, p_sb);
1212 }
1213
1214 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1215                                     struct ecore_ptt *p_ptt)
1216 {
1217         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1218
1219         OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1220
1221         sb_info->index = 0;
1222         sb_info->known_attn = 0;
1223
1224         /* Configure Attention Status Block in IGU */
1225         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1226                  DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1227         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1228                  DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1229 }
1230
1231 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1232                                    struct ecore_ptt *p_ptt,
1233                                    void *sb_virt_addr, dma_addr_t sb_phy_addr)
1234 {
1235         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1236         int i, j, k;
1237
1238         sb_info->sb_attn = sb_virt_addr;
1239         sb_info->sb_phys = sb_phy_addr;
1240
1241         /* Set the pointer to the AEU descriptors */
1242         sb_info->p_aeu_desc = aeu_descs;
1243
1244         /* Calculate Parity Masks */
1245         OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1246         for (i = 0; i < NUM_ATTN_REGS; i++) {
1247                 /* j is array index, k is bit index */
1248                 for (j = 0, k = 0; k < 32; j++) {
1249                         unsigned int flags = aeu_descs[i].bits[j].flags;
1250
1251                         if (flags & ATTENTION_PARITY)
1252                                 sb_info->parity_mask[i] |= 1 << k;
1253
1254                         k += ATTENTION_LENGTH(flags);
1255                 }
1256                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1257                            "Attn Mask [Reg %d]: 0x%08x\n",
1258                            i, sb_info->parity_mask[i]);
1259         }
1260
1261         /* Set the address of cleanup for the mcp attention */
1262         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1263             MISC_REG_AEU_GENERAL_ATTN_0;
1264
1265         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1266 }
1267
1268 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1269                                                     struct ecore_ptt *p_ptt)
1270 {
1271         struct ecore_dev *p_dev = p_hwfn->p_dev;
1272         struct ecore_sb_attn_info *p_sb;
1273         dma_addr_t p_phys = 0;
1274         void *p_virt;
1275
1276         /* SB struct */
1277         p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(struct ecore_sb_attn_info));
1278         if (!p_sb) {
1279                 DP_NOTICE(p_dev, true,
1280                           "Failed to allocate `struct ecore_sb_attn_info'");
1281                 return ECORE_NOMEM;
1282         }
1283
1284         /* SB ring  */
1285         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1286                                          SB_ATTN_ALIGNED_SIZE(p_hwfn));
1287         if (!p_virt) {
1288                 DP_NOTICE(p_dev, true,
1289                           "Failed to allocate status block (attentions)");
1290                 OSAL_FREE(p_dev, p_sb);
1291                 return ECORE_NOMEM;
1292         }
1293
1294         /* Attention setup */
1295         p_hwfn->p_sb_attn = p_sb;
1296         ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1297
1298         return ECORE_SUCCESS;
1299 }
1300
1301 /* coalescing timeout = timeset << (timer_res + 1) */
1302 #ifdef RTE_LIBRTE_QEDE_RX_COAL_US
1303 #define ECORE_CAU_DEF_RX_USECS RTE_LIBRTE_QEDE_RX_COAL_US
1304 #else
1305 #define ECORE_CAU_DEF_RX_USECS 24
1306 #endif
1307
1308 #ifdef RTE_LIBRTE_QEDE_TX_COAL_US
1309 #define ECORE_CAU_DEF_TX_USECS RTE_LIBRTE_QEDE_TX_COAL_US
1310 #else
1311 #define ECORE_CAU_DEF_TX_USECS 48
1312 #endif
1313
1314 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1315                              struct cau_sb_entry *p_sb_entry,
1316                              u8 pf_id, u16 vf_number, u8 vf_valid)
1317 {
1318         struct ecore_dev *p_dev = p_hwfn->p_dev;
1319         u32 cau_state;
1320
1321         OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1322
1323         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1324         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1325         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1326         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1327         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1328
1329         /* setting the time resultion to a fixed value ( = 1) */
1330         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0,
1331                   ECORE_CAU_DEF_RX_TIMER_RES);
1332         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1,
1333                   ECORE_CAU_DEF_TX_TIMER_RES);
1334
1335         cau_state = CAU_HC_DISABLE_STATE;
1336
1337         if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1338                 cau_state = CAU_HC_ENABLE_STATE;
1339                 if (!p_dev->rx_coalesce_usecs) {
1340                         p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1341                         DP_INFO(p_dev, "Coalesce params rx-usecs=%u\n",
1342                                 p_dev->rx_coalesce_usecs);
1343                 }
1344                 if (!p_dev->tx_coalesce_usecs) {
1345                         p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1346                         DP_INFO(p_dev, "Coalesce params tx-usecs=%u\n",
1347                                 p_dev->tx_coalesce_usecs);
1348                 }
1349         }
1350
1351         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1352         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1353 }
1354
1355 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1356                            struct ecore_ptt *p_ptt,
1357                            dma_addr_t sb_phys, u16 igu_sb_id,
1358                            u16 vf_number, u8 vf_valid)
1359 {
1360         struct cau_sb_entry sb_entry;
1361
1362         ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1363                                 vf_number, vf_valid);
1364
1365         if (p_hwfn->hw_init_done) {
1366                 /* Wide-bus, initialize via DMAE */
1367                 u64 phys_addr = (u64)sb_phys;
1368
1369                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1370                                     (u64)(osal_uintptr_t)&phys_addr,
1371                                     CAU_REG_SB_ADDR_MEMORY +
1372                                     igu_sb_id * sizeof(u64), 2, 0);
1373                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1374                                     (u64)(osal_uintptr_t)&sb_entry,
1375                                     CAU_REG_SB_VAR_MEMORY +
1376                                     igu_sb_id * sizeof(u64), 2, 0);
1377         } else {
1378                 /* Initialize Status Block Address */
1379                 STORE_RT_REG_AGG(p_hwfn,
1380                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1381                                  igu_sb_id * 2, sb_phys);
1382
1383                 STORE_RT_REG_AGG(p_hwfn,
1384                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1385                                  igu_sb_id * 2, sb_entry);
1386         }
1387
1388         /* Configure pi coalescing if set */
1389         if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1390                 u8 num_tc = 1;  /* @@@TBD aelior ECORE_MULTI_COS */
1391                 u8 timeset = p_hwfn->p_dev->rx_coalesce_usecs >>
1392                     (ECORE_CAU_DEF_RX_TIMER_RES + 1);
1393                 u8 i;
1394
1395                 ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1396                                       ECORE_COAL_RX_STATE_MACHINE, timeset);
1397
1398                 timeset = p_hwfn->p_dev->tx_coalesce_usecs >>
1399                     (ECORE_CAU_DEF_TX_TIMER_RES + 1);
1400
1401                 for (i = 0; i < num_tc; i++) {
1402                         ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1403                                               igu_sb_id, TX_PI(i),
1404                                               ECORE_COAL_TX_STATE_MACHINE,
1405                                               timeset);
1406                 }
1407         }
1408 }
1409
1410 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1411                            struct ecore_ptt *p_ptt,
1412                            u16 igu_sb_id, u32 pi_index,
1413                            enum ecore_coalescing_fsm coalescing_fsm, u8 timeset)
1414 {
1415         struct cau_pi_entry pi_entry;
1416         u32 sb_offset, pi_offset;
1417
1418         if (IS_VF(p_hwfn->p_dev))
1419                 return;         /* @@@TBD MichalK- VF CAU... */
1420
1421         sb_offset = igu_sb_id * PIS_PER_SB;
1422         OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1423
1424         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1425         if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1426                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1427         else
1428                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1429
1430         pi_offset = sb_offset + pi_index;
1431         if (p_hwfn->hw_init_done) {
1432                 ecore_wr(p_hwfn, p_ptt,
1433                          CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1434                          *((u32 *)&(pi_entry)));
1435         } else {
1436                 STORE_RT_REG(p_hwfn,
1437                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1438                              *((u32 *)&(pi_entry)));
1439         }
1440 }
1441
1442 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1443                         struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info)
1444 {
1445         /* zero status block and ack counter */
1446         sb_info->sb_ack = 0;
1447         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1448
1449         if (IS_PF(p_hwfn->p_dev))
1450                 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1451                                       sb_info->igu_sb_id, 0, 0);
1452 }
1453
1454 /**
1455  * @brief ecore_get_igu_sb_id - given a sw sb_id return the
1456  *        igu_sb_id
1457  *
1458  * @param p_hwfn
1459  * @param sb_id
1460  *
1461  * @return u16
1462  */
1463 static u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1464 {
1465         u16 igu_sb_id;
1466
1467         /* Assuming continuous set of IGU SBs dedicated for given PF */
1468         if (sb_id == ECORE_SP_SB_ID)
1469                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1470         else if (IS_PF(p_hwfn->p_dev))
1471                 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;
1472         else
1473                 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1474
1475         if (sb_id == ECORE_SP_SB_ID)
1476                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1477                            "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1478         else
1479                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1480                            "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1481
1482         return igu_sb_id;
1483 }
1484
1485 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1486                                        struct ecore_ptt *p_ptt,
1487                                        struct ecore_sb_info *sb_info,
1488                                        void *sb_virt_addr,
1489                                        dma_addr_t sb_phy_addr, u16 sb_id)
1490 {
1491         sb_info->sb_virt = sb_virt_addr;
1492         sb_info->sb_phys = sb_phy_addr;
1493
1494         sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1495
1496         if (sb_id != ECORE_SP_SB_ID) {
1497                 p_hwfn->sbs_info[sb_id] = sb_info;
1498                 p_hwfn->num_sbs++;
1499         }
1500 #ifdef ECORE_CONFIG_DIRECT_HWFN
1501         sb_info->p_hwfn = p_hwfn;
1502 #endif
1503         sb_info->p_dev = p_hwfn->p_dev;
1504
1505         /* The igu address will hold the absolute address that needs to be
1506          * written to for a specific status block
1507          */
1508         if (IS_PF(p_hwfn->p_dev)) {
1509                 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1510                     GTT_BAR0_MAP_REG_IGU_CMD + (sb_info->igu_sb_id << 3);
1511
1512         } else {
1513                 sb_info->igu_addr =
1514                     (u8 OSAL_IOMEM *)p_hwfn->regview +
1515                     PXP_VF_BAR0_START_IGU +
1516                     ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1517         }
1518
1519         sb_info->flags |= ECORE_SB_INFO_INIT;
1520
1521         ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1522
1523         return ECORE_SUCCESS;
1524 }
1525
1526 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1527                                           struct ecore_sb_info *sb_info,
1528                                           u16 sb_id)
1529 {
1530         if (sb_id == ECORE_SP_SB_ID) {
1531                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1532                 return ECORE_INVAL;
1533         }
1534
1535         /* zero status block and ack counter */
1536         sb_info->sb_ack = 0;
1537         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1538
1539         if (p_hwfn->sbs_info[sb_id] != OSAL_NULL) {
1540                 p_hwfn->sbs_info[sb_id] = OSAL_NULL;
1541                 p_hwfn->num_sbs--;
1542         }
1543
1544         return ECORE_SUCCESS;
1545 }
1546
1547 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1548 {
1549         struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1550
1551         if (!p_sb)
1552                 return;
1553
1554         if (p_sb->sb_info.sb_virt) {
1555                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1556                                        p_sb->sb_info.sb_virt,
1557                                        p_sb->sb_info.sb_phys,
1558                                        SB_ALIGNED_SIZE(p_hwfn));
1559         }
1560
1561         OSAL_FREE(p_hwfn->p_dev, p_sb);
1562 }
1563
1564 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1565                                                   struct ecore_ptt *p_ptt)
1566 {
1567         struct ecore_sb_sp_info *p_sb;
1568         dma_addr_t p_phys = 0;
1569         void *p_virt;
1570
1571         /* SB struct */
1572         p_sb =
1573             OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1574                        sizeof(struct ecore_sb_sp_info));
1575         if (!p_sb) {
1576                 DP_NOTICE(p_hwfn, true,
1577                           "Failed to allocate `struct ecore_sb_info'");
1578                 return ECORE_NOMEM;
1579         }
1580
1581         /* SB ring  */
1582         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1583                                          &p_phys, SB_ALIGNED_SIZE(p_hwfn));
1584         if (!p_virt) {
1585                 DP_NOTICE(p_hwfn, true, "Failed to allocate status block");
1586                 OSAL_FREE(p_hwfn->p_dev, p_sb);
1587                 return ECORE_NOMEM;
1588         }
1589
1590         /* Status Block setup */
1591         p_hwfn->p_sp_sb = p_sb;
1592         ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1593                           p_virt, p_phys, ECORE_SP_SB_ID);
1594
1595         OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1596
1597         return ECORE_SUCCESS;
1598 }
1599
1600 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1601                                            ecore_int_comp_cb_t comp_cb,
1602                                            void *cookie,
1603                                            u8 *sb_idx, __le16 **p_fw_cons)
1604 {
1605         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1606         enum _ecore_status_t rc = ECORE_NOMEM;
1607         u8 pi;
1608
1609         /* Look for a free index */
1610         for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1611                 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1612                         continue;
1613
1614                 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1615                 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1616                 *sb_idx = pi;
1617                 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1618                 rc = ECORE_SUCCESS;
1619                 break;
1620         }
1621
1622         return rc;
1623 }
1624
1625 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi)
1626 {
1627         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1628
1629         if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1630                 return ECORE_NOMEM;
1631
1632         p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1633         p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1634         return ECORE_SUCCESS;
1635 }
1636
1637 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1638 {
1639         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1640 }
1641
1642 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1643                               struct ecore_ptt *p_ptt,
1644                               enum ecore_int_mode int_mode)
1645 {
1646         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
1647
1648 #ifndef ASIC_ONLY
1649         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1650                 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1651         else
1652 #endif
1653                 igu_pf_conf |= IGU_PF_CONF_ATTN_BIT_EN;
1654
1655         p_hwfn->p_dev->int_mode = int_mode;
1656         switch (p_hwfn->p_dev->int_mode) {
1657         case ECORE_INT_MODE_INTA:
1658                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1659                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1660                 break;
1661
1662         case ECORE_INT_MODE_MSI:
1663                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1664                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1665                 break;
1666
1667         case ECORE_INT_MODE_MSIX:
1668                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1669                 break;
1670         case ECORE_INT_MODE_POLL:
1671                 break;
1672         }
1673
1674         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1675 }
1676
1677 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1678                                       struct ecore_ptt *p_ptt)
1679 {
1680 #ifndef ASIC_ONLY
1681         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1682                 DP_INFO(p_hwfn,
1683                         "FPGA - Don't enable Attentions in IGU and MISC\n");
1684                 return;
1685         }
1686 #endif
1687
1688         /* Configure AEU signal change to produce attentions */
1689         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1690         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1691         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1692         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1693
1694         OSAL_MMIOWB(p_hwfn->p_dev);
1695
1696         /* Unmask AEU signals toward IGU */
1697         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1698 }
1699
1700 enum _ecore_status_t
1701 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1702                           enum ecore_int_mode int_mode)
1703 {
1704         enum _ecore_status_t rc = ECORE_SUCCESS;
1705         u32 tmp;
1706
1707         /* @@@tmp - Mask General HW attentions 0-31, Enable 32-36 */
1708         tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
1709         tmp |= 0xf;
1710         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE3_IGU_OUT_0, 0);
1711         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
1712
1713         /* @@@tmp - Starting with MFW 8.2.1.0 we've started hitting AVS stop
1714          * attentions. Since we're waiting for BRCM answer regarding this
1715          * attention, in the meanwhile we simply mask it.
1716          */
1717         tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
1718         tmp &= ~0x800;
1719         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
1720
1721         ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1722
1723         if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1724                 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1725                 if (rc != ECORE_SUCCESS) {
1726                         DP_NOTICE(p_hwfn, true,
1727                                   "Slowpath IRQ request failed\n");
1728                         return ECORE_NORESOURCES;
1729                 }
1730                 p_hwfn->b_int_requested = true;
1731         }
1732
1733         /* Enable interrupt Generation */
1734         ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1735
1736         p_hwfn->b_int_enabled = 1;
1737
1738         return rc;
1739 }
1740
1741 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
1742                                struct ecore_ptt *p_ptt)
1743 {
1744         p_hwfn->b_int_enabled = 0;
1745
1746         if (IS_VF(p_hwfn->p_dev))
1747                 return;
1748
1749         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1750 }
1751
1752 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
1753 void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1754                               struct ecore_ptt *p_ptt,
1755                               u32 sb_id, bool cleanup_set, u16 opaque_fid)
1756 {
1757         u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1758         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
1759         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1760         u8 type = 0;            /* FIXME MichalS type??? */
1761
1762         OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1763                            IGU_REG_CLEANUP_STATUS_0) != 0x200);
1764
1765         /* USE Control Command Register to perform cleanup. There is an
1766          * option to do this using IGU bar, but then it can't be used for VFs.
1767          */
1768
1769         /* Set the data field */
1770         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1771         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
1772         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1773
1774         /* Set the control register */
1775         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1776         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1777         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1778
1779         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1780
1781         OSAL_BARRIER(p_hwfn->p_dev);
1782
1783         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1784
1785         OSAL_MMIOWB(p_hwfn->p_dev);
1786
1787         /* calculate where to read the status bit from */
1788         sb_bit = 1 << (sb_id % 32);
1789         sb_bit_addr = sb_id / 32 * sizeof(u32);
1790
1791         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
1792
1793         /* Now wait for the command to complete */
1794         while (--sleep_cnt) {
1795                 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
1796                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1797                         break;
1798                 OSAL_MSLEEP(5);
1799         }
1800
1801         if (!sleep_cnt)
1802                 DP_NOTICE(p_hwfn, true,
1803                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1804                           val, sb_id);
1805 }
1806
1807 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
1808                                        struct ecore_ptt *p_ptt,
1809                                        u32 sb_id, u16 opaque, bool b_set)
1810 {
1811         int pi;
1812
1813         /* Set */
1814         if (b_set)
1815                 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);
1816
1817         /* Clear */
1818         ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
1819
1820         /* Clear the CAU for the SB */
1821         for (pi = 0; pi < 12; pi++)
1822                 ecore_wr(p_hwfn, p_ptt,
1823                          CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0);
1824 }
1825
1826 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
1827                                 struct ecore_ptt *p_ptt,
1828                                 bool b_set, bool b_slowpath)
1829 {
1830         u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
1831         u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
1832         u32 sb_id = 0, val = 0;
1833
1834         /* @@@TBD MichalK temporary... should be moved to init-tool... */
1835         val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
1836         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
1837         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
1838         ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
1839         /* end temporary */
1840
1841         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1842                    "IGU cleaning SBs [%d,...,%d]\n",
1843                    igu_base_sb, igu_base_sb + igu_sb_cnt - 1);
1844
1845         for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++)
1846                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
1847                                                   p_hwfn->hw_info.opaque_fid,
1848                                                   b_set);
1849
1850         if (!b_slowpath)
1851                 return;
1852
1853         sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1854         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1855                    "IGU cleaning slowpath SB [%d]\n", sb_id);
1856         ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
1857                                           p_hwfn->hw_info.opaque_fid, b_set);
1858 }
1859
1860 static u32 ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
1861                                         struct ecore_ptt *p_ptt, u16 sb_id)
1862 {
1863         u32 val = ecore_rd(p_hwfn, p_ptt,
1864                            IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id);
1865         struct ecore_igu_block *p_block;
1866
1867         p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
1868
1869         /* stop scanning when hit first invalid PF entry */
1870         if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
1871             GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
1872                 goto out;
1873
1874         /* Fill the block information */
1875         p_block->status = ECORE_IGU_STATUS_VALID;
1876         p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
1877         p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
1878         p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
1879
1880         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1881                    "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d"
1882                    " is_pf = %d vector_num = 0x%x\n",
1883                    sb_id, val, p_block->function_id, p_block->is_pf,
1884                    p_block->vector_number);
1885
1886 out:
1887         return val;
1888 }
1889
1890 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
1891                                             struct ecore_ptt *p_ptt)
1892 {
1893         struct ecore_igu_info *p_igu_info;
1894         struct ecore_igu_block *p_block;
1895         u16 sb_id, last_iov_sb_id = 0;
1896         u32 min_vf, max_vf, val;
1897         u16 prev_sb_id = 0xFF;
1898
1899         p_hwfn->hw_info.p_igu_info = OSAL_ALLOC(p_hwfn->p_dev,
1900                                                 GFP_KERNEL,
1901                                                 sizeof(*p_igu_info));
1902         if (!p_hwfn->hw_info.p_igu_info)
1903                 return ECORE_NOMEM;
1904
1905         OSAL_MEMSET(p_hwfn->hw_info.p_igu_info, 0, sizeof(*p_igu_info));
1906
1907         p_igu_info = p_hwfn->hw_info.p_igu_info;
1908
1909         /* Initialize base sb / sb cnt for PFs and VFs */
1910         p_igu_info->igu_base_sb = 0xffff;
1911         p_igu_info->igu_sb_cnt = 0;
1912         p_igu_info->igu_dsb_id = 0xffff;
1913         p_igu_info->igu_base_sb_iov = 0xffff;
1914
1915 #ifdef CONFIG_ECORE_SRIOV
1916         min_vf = p_hwfn->hw_info.first_vf_in_pf;
1917         max_vf = p_hwfn->hw_info.first_vf_in_pf +
1918             p_hwfn->p_dev->sriov_info.total_vfs;
1919 #else
1920         min_vf = 0;
1921         max_vf = 0;
1922 #endif
1923
1924         for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1925              sb_id++) {
1926                 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1927                 val = ecore_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id);
1928                 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
1929                     GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
1930                         break;
1931
1932                 if (p_block->is_pf) {
1933                         if (p_block->function_id == p_hwfn->rel_pf_id) {
1934                                 p_block->status |= ECORE_IGU_STATUS_PF;
1935
1936                                 if (p_block->vector_number == 0) {
1937                                         if (p_igu_info->igu_dsb_id == 0xffff)
1938                                                 p_igu_info->igu_dsb_id = sb_id;
1939                                 } else {
1940                                         if (p_igu_info->igu_base_sb == 0xffff) {
1941                                                 p_igu_info->igu_base_sb = sb_id;
1942                                         } else if (prev_sb_id != sb_id - 1) {
1943                                                 DP_NOTICE(p_hwfn->p_dev, false,
1944                                                           "consecutive igu"
1945                                                           " vectors for HWFN"
1946                                                           " %x broken",
1947                                                           p_hwfn->rel_pf_id);
1948                                                 break;
1949                                         }
1950                                         prev_sb_id = sb_id;
1951                                         /* we don't count the default */
1952                                         (p_igu_info->igu_sb_cnt)++;
1953                                 }
1954                         }
1955                 } else {
1956                         if ((p_block->function_id >= min_vf) &&
1957                             (p_block->function_id < max_vf)) {
1958                                 /* Available for VFs of this PF */
1959                                 if (p_igu_info->igu_base_sb_iov == 0xffff) {
1960                                         p_igu_info->igu_base_sb_iov = sb_id;
1961                                 } else if (last_iov_sb_id != sb_id - 1) {
1962                                         if (!val)
1963                                                 DP_VERBOSE(p_hwfn->p_dev,
1964                                                            ECORE_MSG_INTR,
1965                                                            "First uninited IGU"
1966                                                            " CAM entry at"
1967                                                            " index 0x%04x\n",
1968                                                            sb_id);
1969                                         else
1970                                                 DP_NOTICE(p_hwfn->p_dev, false,
1971                                                           "Consecutive igu"
1972                                                           " vectors for HWFN"
1973                                                           " %x vfs is broken"
1974                                                           " [jumps from %04x"
1975                                                           " to %04x]\n",
1976                                                           p_hwfn->rel_pf_id,
1977                                                           last_iov_sb_id,
1978                                                           sb_id);
1979                                         break;
1980                                 }
1981                                 p_block->status |= ECORE_IGU_STATUS_FREE;
1982                                 p_hwfn->hw_info.p_igu_info->free_blks++;
1983                                 last_iov_sb_id = sb_id;
1984                         }
1985                 }
1986         }
1987         p_igu_info->igu_sb_cnt_iov = p_igu_info->free_blks;
1988
1989         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1990                    "IGU igu_base_sb=0x%x [IOV 0x%x] igu_sb_cnt=%d [IOV 0x%x] "
1991                    "igu_dsb_id=0x%x\n",
1992                    p_igu_info->igu_base_sb, p_igu_info->igu_base_sb_iov,
1993                    p_igu_info->igu_sb_cnt, p_igu_info->igu_sb_cnt_iov,
1994                    p_igu_info->igu_dsb_id);
1995
1996         if (p_igu_info->igu_base_sb == 0xffff ||
1997             p_igu_info->igu_dsb_id == 0xffff || p_igu_info->igu_sb_cnt == 0) {
1998                 DP_NOTICE(p_hwfn, true,
1999                           "IGU CAM returned invalid values igu_base_sb=0x%x "
2000                           "igu_sb_cnt=%d igu_dsb_id=0x%x\n",
2001                           p_igu_info->igu_base_sb, p_igu_info->igu_sb_cnt,
2002                           p_igu_info->igu_dsb_id);
2003                 return ECORE_INVAL;
2004         }
2005
2006         return ECORE_SUCCESS;
2007 }
2008
2009 /**
2010  * @brief Initialize igu runtime registers
2011  *
2012  * @param p_hwfn
2013  */
2014 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2015 {
2016         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2017
2018         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2019 }
2020
2021 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2022                           IGU_CMD_INT_ACK_BASE)
2023 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2024                           IGU_CMD_INT_ACK_BASE)
2025 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2026 {
2027         u32 intr_status_hi = 0, intr_status_lo = 0;
2028         u64 intr_status = 0;
2029
2030         intr_status_lo = REG_RD(p_hwfn,
2031                                 GTT_BAR0_MAP_REG_IGU_CMD +
2032                                 LSB_IGU_CMD_ADDR * 8);
2033         intr_status_hi = REG_RD(p_hwfn,
2034                                 GTT_BAR0_MAP_REG_IGU_CMD +
2035                                 MSB_IGU_CMD_ADDR * 8);
2036         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2037
2038         return intr_status;
2039 }
2040
2041 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2042 {
2043         OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2044         p_hwfn->b_sp_dpc_enabled = true;
2045 }
2046
2047 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2048 {
2049         p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2050         if (!p_hwfn->sp_dpc)
2051                 return ECORE_NOMEM;
2052
2053         return ECORE_SUCCESS;
2054 }
2055
2056 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2057 {
2058         OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2059 }
2060
2061 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2062                                      struct ecore_ptt *p_ptt)
2063 {
2064         enum _ecore_status_t rc = ECORE_SUCCESS;
2065
2066         rc = ecore_int_sp_dpc_alloc(p_hwfn);
2067         if (rc != ECORE_SUCCESS) {
2068                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2069                 return rc;
2070         }
2071
2072         rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2073         if (rc != ECORE_SUCCESS) {
2074                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2075                 return rc;
2076         }
2077
2078         rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2079         if (rc != ECORE_SUCCESS)
2080                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2081
2082         return rc;
2083 }
2084
2085 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2086 {
2087         ecore_int_sp_sb_free(p_hwfn);
2088         ecore_int_sb_attn_free(p_hwfn);
2089         ecore_int_sp_dpc_free(p_hwfn);
2090 }
2091
2092 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2093 {
2094         if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2095                 return;
2096
2097         ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2098         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2099         ecore_int_sp_dpc_setup(p_hwfn);
2100 }
2101
2102 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2103                            struct ecore_sb_cnt_info *p_sb_cnt_info)
2104 {
2105         struct ecore_igu_info *info = p_hwfn->hw_info.p_igu_info;
2106
2107         if (!info || !p_sb_cnt_info)
2108                 return;
2109
2110         p_sb_cnt_info->sb_cnt = info->igu_sb_cnt;
2111         p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov;
2112         p_sb_cnt_info->sb_free_blk = info->free_blks;
2113 }
2114
2115 u16 ecore_int_queue_id_from_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
2116 {
2117         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2118
2119         /* Determine origin of SB id */
2120         if ((sb_id >= p_info->igu_base_sb) &&
2121             (sb_id < p_info->igu_base_sb + p_info->igu_sb_cnt)) {
2122                 return sb_id - p_info->igu_base_sb;
2123         } else if ((sb_id >= p_info->igu_base_sb_iov) &&
2124                    (sb_id < p_info->igu_base_sb_iov + p_info->igu_sb_cnt_iov)) {
2125                 return sb_id - p_info->igu_base_sb_iov + p_info->igu_sb_cnt;
2126         }
2127
2128                 DP_NOTICE(p_hwfn, true, "SB %d not in range for function\n",
2129                           sb_id);
2130                 return 0;
2131         }
2132
2133 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2134 {
2135         int i;
2136
2137         for_each_hwfn(p_dev, i)
2138                 p_dev->hwfns[i].b_int_requested = false;
2139 }