drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23
  24 #define CHIP_MCP_RESP_ITER_US 10
  25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  26
  27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  28 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  29
  30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  31         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  32                  _val)
  33
  34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  35         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  36
  37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  38         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  39                      OFFSETOF(struct public_drv_mb, _field), _val)
  40
  41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  42         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  43                      OFFSETOF(struct public_drv_mb, _field))
  44
  45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  46         DRV_ID_PDA_COMP_VER_SHIFT)
  47
  48 #define MCP_BYTES_PER_MBIT_SHIFT 17
  49
  50 #ifndef ASIC_ONLY
  51 static int loaded;
  52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  53 #endif
  54
  55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  56 {
  57         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  58                 return false;
  59         return true;
  60 }
  61
  62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  63 {
  64         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  65                                         PUBLIC_PORT);
  66         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  67
  68         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  69                                                    MFW_PORT(p_hwfn));
  70         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  71                    "port_addr = 0x%x, port_id 0x%02x\n",
  72                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  73 }
  74
  75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  76 {
  77         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  78         OSAL_BE32 tmp;
  79         u32 i;
  80
  81 #ifndef ASIC_ONLY
  82         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  83                 return;
  84 #endif
  85
  86         if (!p_hwfn->mcp_info->public_base)
  87                 return;
  88
  89         for (i = 0; i < length; i++) {
  90                 tmp = ecore_rd(p_hwfn, p_ptt,
  91                                p_hwfn->mcp_info->mfw_mb_addr +
  92                                (i << 2) + sizeof(u32));
  93
  94                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  95                     OSAL_BE32_TO_CPU(tmp);
  96         }
  97 }
  98
  99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 100 {
 101         if (p_hwfn->mcp_info) {
 102                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 103                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 104                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
 105         }
 106         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 107
 108         return ECORE_SUCCESS;
 109 }
 110
 111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 112                                                    struct ecore_ptt *p_ptt)
 113 {
 114         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 115         u32 drv_mb_offsize, mfw_mb_offsize;
 116         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 117
 118 #ifndef ASIC_ONLY
 119         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 120                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 121                 p_info->public_base = 0;
 122                 return ECORE_INVAL;
 123         }
 124 #endif
 125
 126         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 127         if (!p_info->public_base)
 128                 return ECORE_INVAL;
 129
 130         p_info->public_base |= GRCBASE_MCP;
 131
 132         /* Calculate the driver and MFW mailbox address */
 133         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 134                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 135                                                        PUBLIC_DRV_MB));
 136         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 137         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 138                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 139                    " mcp_pf_id = 0x%x\n",
 140                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 141
 142         /* Set the MFW MB address */
 143         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 144                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 145                                                        PUBLIC_MFW_MB));
 146         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 147         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 148                                                p_info->mfw_mb_addr);
 149
 150         /* Get the current driver mailbox sequence before sending
 151          * the first command
 152          */
 153         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 154             DRV_MSG_SEQ_NUMBER_MASK;
 155
 156         /* Get current FW pulse sequence */
 157         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 158             DRV_PULSE_SEQ_MASK;
 159
 160         p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
 161                                           MISCS_REG_GENERIC_POR_0);
 162
 163         return ECORE_SUCCESS;
 164 }
 165
 166 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 167                                         struct ecore_ptt *p_ptt)
 168 {
 169         struct ecore_mcp_info *p_info;
 170         u32 size;
 171
 172         /* Allocate mcp_info structure */
 173         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 174                                        sizeof(*p_hwfn->mcp_info));
 175         if (!p_hwfn->mcp_info)
 176                 goto err;
 177         p_info = p_hwfn->mcp_info;
 178
 179         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 180                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 181                 /* Do not free mcp_info here, since public_base indicate that
 182                  * the MCP is not initialized
 183                  */
 184                 return ECORE_SUCCESS;
 185         }
 186
 187         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 188         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 189         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 190         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 191                 goto err;
 192
 193         /* Initialize the MFW spinlock */
 194         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
 195         OSAL_SPIN_LOCK_INIT(&p_info->lock);
 196
 197         return ECORE_SUCCESS;
 198
 199 err:
 200         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 201         ecore_mcp_free(p_hwfn);
 202         return ECORE_NOMEM;
 203 }
 204
 205 /* Locks the MFW mailbox of a PF to ensure a single access.
 206  * The lock is achieved in most cases by holding a spinlock, causing other
 207  * threads to wait till a previous access is done.
 208  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 209  * access is achieved by setting a blocking flag, which will fail other
 210  * competing contexts to send their mailboxes.
 211  */
 212 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
 213                                               u32 cmd)
 214 {
 215         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
 216
 217         /* The spinlock shouldn't be acquired when the mailbox command is
 218          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 219          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 220          * (i.e. interrupts are disabled) - can lead to a deadlock.
 221          * It is assumed that for a single PF, no other mailbox commands can be
 222          * sent from another context while sending LOAD_REQ, and that any
 223          * parallel commands to UNLOAD_REQ can be cancelled.
 224          */
 225         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 226                 p_hwfn->mcp_info->block_mb_sending = false;
 227
 228         if (p_hwfn->mcp_info->block_mb_sending) {
 229                 DP_NOTICE(p_hwfn, false,
 230                           "Trying to send a MFW mailbox command [0x%x]"
 231                           " in parallel to [UN]LOAD_REQ. Aborting.\n",
 232                           cmd);
 233                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 234                 return ECORE_BUSY;
 235         }
 236
 237         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 238                 p_hwfn->mcp_info->block_mb_sending = true;
 239                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 240         }
 241
 242         return ECORE_SUCCESS;
 243 }
 244
 245 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
 246 {
 247         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 248                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 249 }
 250
 251 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 252                                      struct ecore_ptt *p_ptt)
 253 {
 254         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 255         u32 delay = CHIP_MCP_RESP_ITER_US;
 256         u32 org_mcp_reset_seq, cnt = 0;
 257         enum _ecore_status_t rc = ECORE_SUCCESS;
 258
 259 #ifndef ASIC_ONLY
 260         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 261                 delay = EMUL_MCP_RESP_ITER_US;
 262 #endif
 263
 264         /* Ensure that only a single thread is accessing the mailbox at a
 265          * certain time.
 266          */
 267         rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 268         if (rc != ECORE_SUCCESS)
 269                 return rc;
 270
 271         /* Set drv command along with the updated sequence */
 272         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 273         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 274
 275         do {
 276                 /* Wait for MFW response */
 277                 OSAL_UDELAY(delay);
 278                 /* Give the FW up to 500 second (50*1000*10usec) */
 279         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 280                                                 MISCS_REG_GENERIC_POR_0)) &&
 281                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 282
 283         if (org_mcp_reset_seq !=
 284             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 285                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 286                            "MCP was reset after %d usec\n", cnt * delay);
 287         } else {
 288                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 289                 rc = ECORE_AGAIN;
 290         }
 291
 292         ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 293
 294         return rc;
 295 }
 296
 297 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
 298                                              struct ecore_ptt *p_ptt,
 299                                              u32 cmd, u32 param,
 300                                              u32 *o_mcp_resp,
 301                                              u32 *o_mcp_param)
 302 {
 303         u32 delay = CHIP_MCP_RESP_ITER_US;
 304         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 305         u32 seq, cnt = 1, actual_mb_seq;
 306         enum _ecore_status_t rc = ECORE_SUCCESS;
 307
 308 #ifndef ASIC_ONLY
 309         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 310                 delay = EMUL_MCP_RESP_ITER_US;
 311         /* There is a built-in delay of 100usec in each MFW response read */
 312         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 313                 max_retries /= 10;
 314 #endif
 315
 316         /* Get actual driver mailbox sequence */
 317         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 318             DRV_MSG_SEQ_NUMBER_MASK;
 319
 320         /* Use MCP history register to check if MCP reset occurred between
 321          * init time and now.
 322          */
 323         if (p_hwfn->mcp_info->mcp_hist !=
 324             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 325                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
 326                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 327                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 328         }
 329         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 330
 331         /* Set drv param */
 332         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 333
 334         /* Set drv command along with the updated sequence */
 335         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 336
 337         do {
 338                 /* Wait for MFW response */
 339                 OSAL_UDELAY(delay);
 340                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 341
 342                 /* Give the FW up to 5 second (500*10ms) */
 343         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 344                  (cnt++ < max_retries));
 345
 346         /* Is this a reply to our command? */
 347         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 348                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 349                 /* Get the MCP param */
 350                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 351         } else {
 352                 /* FW BUG! */
 353                 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
 354                        cmd, param);
 355                 *o_mcp_resp = 0;
 356                 rc = ECORE_AGAIN;
 357                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 358         }
 359         return rc;
 360 }
 361
 362 static enum _ecore_status_t
 363 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 364                         struct ecore_ptt *p_ptt,
 365                         struct ecore_mcp_mb_params *p_mb_params)
 366 {
 367         u32 union_data_addr;
 368         enum _ecore_status_t rc;
 369
 370         /* MCP not initialized */
 371         if (!ecore_mcp_is_init(p_hwfn)) {
 372                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 373                 return ECORE_BUSY;
 374         }
 375
 376         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 377                           OFFSETOF(struct public_drv_mb, union_data);
 378
 379         /* Ensure that only a single thread is accessing the mailbox at a
 380          * certain time.
 381          */
 382         rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 383         if (rc != ECORE_SUCCESS)
 384                 return rc;
 385
 386         if (p_mb_params->p_data_src != OSAL_NULL)
 387                 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr,
 388                                 p_mb_params->p_data_src,
 389                                 sizeof(*p_mb_params->p_data_src));
 390
 391         rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 392                               p_mb_params->param, &p_mb_params->mcp_resp,
 393                               &p_mb_params->mcp_param);
 394
 395         if (p_mb_params->p_data_dst != OSAL_NULL)
 396                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 397                                   union_data_addr,
 398                                   sizeof(*p_mb_params->p_data_dst));
 399
 400         ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 401
 402         return rc;
 403 }
 404
 405 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 406                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 407                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 408 {
 409         struct ecore_mcp_mb_params mb_params;
 410         enum _ecore_status_t rc;
 411
 412 #ifndef ASIC_ONLY
 413         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 414                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 415                         loaded--;
 416                         loaded_port[p_hwfn->port_id]--;
 417                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 418                                    loaded);
 419                 }
 420                 return ECORE_SUCCESS;
 421         }
 422 #endif
 423
 424         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 425         mb_params.cmd = cmd;
 426         mb_params.param = param;
 427         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 428         if (rc != ECORE_SUCCESS)
 429                 return rc;
 430
 431         *o_mcp_resp = mb_params.mcp_resp;
 432         *o_mcp_param = mb_params.mcp_param;
 433
 434         return ECORE_SUCCESS;
 435 }
 436
 437 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 438                                           struct ecore_ptt *p_ptt,
 439                                           u32 cmd,
 440                                           u32 param,
 441                                           u32 *o_mcp_resp,
 442                                           u32 *o_mcp_param,
 443                                           u32 i_txn_size, u32 *i_buf)
 444 {
 445         struct ecore_mcp_mb_params mb_params;
 446         union drv_union_data union_data;
 447         enum _ecore_status_t rc;
 448
 449         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 450         mb_params.cmd = cmd;
 451         mb_params.param = param;
 452         OSAL_MEMCPY((u32 *)&union_data.raw_data, i_buf, i_txn_size);
 453         mb_params.p_data_src = &union_data;
 454         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 455         if (rc != ECORE_SUCCESS)
 456                 return rc;
 457
 458         *o_mcp_resp = mb_params.mcp_resp;
 459         *o_mcp_param = mb_params.mcp_param;
 460
 461         return ECORE_SUCCESS;
 462 }
 463
 464 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 465                                           struct ecore_ptt *p_ptt,
 466                                           u32 cmd,
 467                                           u32 param,
 468                                           u32 *o_mcp_resp,
 469                                           u32 *o_mcp_param,
 470                                           u32 *o_txn_size, u32 *o_buf)
 471 {
 472         struct ecore_mcp_mb_params mb_params;
 473         union drv_union_data union_data;
 474         enum _ecore_status_t rc;
 475
 476         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 477         mb_params.cmd = cmd;
 478         mb_params.param = param;
 479         mb_params.p_data_dst = &union_data;
 480         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 481         if (rc != ECORE_SUCCESS)
 482                 return rc;
 483
 484         *o_mcp_resp = mb_params.mcp_resp;
 485         *o_mcp_param = mb_params.mcp_param;
 486
 487         *o_txn_size = *o_mcp_param;
 488         OSAL_MEMCPY(o_buf, (u32 *)&union_data.raw_data, *o_txn_size);
 489
 490         return ECORE_SUCCESS;
 491 }
 492
 493 #ifndef ASIC_ONLY
 494 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 495                                     u32 *p_load_code)
 496 {
 497         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 498
 499         if (!loaded)
 500                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 501         else if (!loaded_port[p_hwfn->port_id])
 502                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 503         else
 504                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 505
 506         /* On CMT, always tell that it's engine */
 507         if (p_hwfn->p_dev->num_hwfns > 1)
 508                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 509
 510         *p_load_code = load_phase;
 511         loaded++;
 512         loaded_port[p_hwfn->port_id]++;
 513
 514         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 515                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 516                    *p_load_code, loaded, p_hwfn->port_id,
 517                    loaded_port[p_hwfn->port_id]);
 518 }
 519 #endif
 520
 521 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 522                                         struct ecore_ptt *p_ptt,
 523                                         u32 *p_load_code)
 524 {
 525         struct ecore_dev *p_dev = p_hwfn->p_dev;
 526         struct ecore_mcp_mb_params mb_params;
 527         enum _ecore_status_t rc;
 528
 529 #ifndef ASIC_ONLY
 530         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 531                 ecore_mcp_mf_workaround(p_hwfn, p_load_code);
 532                 return ECORE_SUCCESS;
 533         }
 534 #endif
 535
 536         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 537         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 538         mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
 539                           p_dev->drv_type;
 540         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 541
 542         /* if mcp fails to respond we must abort */
 543         if (rc != ECORE_SUCCESS) {
 544                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 545                 return rc;
 546         }
 547
 548         *p_load_code = mb_params.mcp_resp;
 549
 550         /* If MFW refused (e.g. other port is in diagnostic mode) we
 551          * must abort. This can happen in the following cases:
 552          * - Other port is in diagnostic mode
 553          * - Previously loaded function on the engine is not compliant with
 554          *   the requester.
 555          * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
 556          *      -
 557          */
 558         if (!(*p_load_code) ||
 559             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
 560             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
 561             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
 562                 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
 563                 return ECORE_BUSY;
 564         }
 565
 566         return ECORE_SUCCESS;
 567 }
 568
 569 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
 570                                     struct ecore_ptt *p_ptt)
 571 {
 572         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 573                                         PUBLIC_PATH);
 574         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 575         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
 576                                      ECORE_PATH_ID(p_hwfn));
 577         u32 disabled_vfs[VF_MAX_STATIC / 32];
 578         int i;
 579
 580         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 581                    "Reading Disabled VF information from [offset %08x],"
 582                    " path_addr %08x\n",
 583                    mfw_path_offsize, path_addr);
 584
 585         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
 586                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
 587                                            path_addr +
 588                                            OFFSETOF(struct public_path,
 589                                                     mcp_vf_disabled) +
 590                                            sizeof(u32) * i);
 591                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 592                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
 593                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
 594         }
 595
 596         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
 597                 OSAL_VF_FLR_UPDATE(p_hwfn);
 598 }
 599
 600 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
 601                                           struct ecore_ptt *p_ptt,
 602                                           u32 *vfs_to_ack)
 603 {
 604         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 605                                         PUBLIC_FUNC);
 606         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 607         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
 608                                      MCP_PF_ID(p_hwfn));
 609         struct ecore_mcp_mb_params mb_params;
 610         union drv_union_data union_data;
 611         enum _ecore_status_t rc;
 612         int i;
 613
 614         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 615                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 616                            "Acking VFs [%08x,...,%08x] - %08x\n",
 617                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
 618
 619         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 620         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
 621         OSAL_MEMCPY(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
 622         mb_params.p_data_src = &union_data;
 623         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
 624                                      &mb_params);
 625         if (rc != ECORE_SUCCESS) {
 626                 DP_NOTICE(p_hwfn, false,
 627                           "Failed to pass ACK for VF flr to MFW\n");
 628                 return ECORE_TIMEOUT;
 629         }
 630
 631         /* TMP - clear the ACK bits; should be done by MFW */
 632         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 633                 ecore_wr(p_hwfn, p_ptt,
 634                          func_addr +
 635                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
 636                          i * sizeof(u32), 0);
 637
 638         return rc;
 639 }
 640
 641 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
 642                                                 struct ecore_ptt *p_ptt)
 643 {
 644         u32 transceiver_state;
 645
 646         transceiver_state = ecore_rd(p_hwfn, p_ptt,
 647                                      p_hwfn->mcp_info->port_addr +
 648                                      OFFSETOF(struct public_port,
 649                                               transceiver_data));
 650
 651         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
 652                    "Received transceiver state update [0x%08x] from mfw"
 653                    " [Addr 0x%x]\n",
 654                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
 655                                             OFFSETOF(struct public_port,
 656                                                      transceiver_data)));
 657
 658         transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
 659
 660         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
 661                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
 662         else
 663                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
 664 }
 665
 666 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
 667                                          struct ecore_ptt *p_ptt,
 668                                          bool b_reset)
 669 {
 670         struct ecore_mcp_link_state *p_link;
 671         u8 max_bw, min_bw;
 672         u32 status = 0;
 673
 674         p_link = &p_hwfn->mcp_info->link_output;
 675         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
 676         if (!b_reset) {
 677                 status = ecore_rd(p_hwfn, p_ptt,
 678                                   p_hwfn->mcp_info->port_addr +
 679                                   OFFSETOF(struct public_port, link_status));
 680                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
 681                            "Received link update [0x%08x] from mfw"
 682                            " [Addr 0x%x]\n",
 683                            status, (u32)(p_hwfn->mcp_info->port_addr +
 684                                           OFFSETOF(struct public_port,
 685                                                    link_status)));
 686         } else {
 687                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 688                            "Resetting link indications\n");
 689                 return;
 690         }
 691
 692         if (p_hwfn->b_drv_link_init)
 693                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
 694         else
 695                 p_link->link_up = false;
 696
 697         p_link->full_duplex = true;
 698         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
 699         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
 700                 p_link->speed = 100000;
 701                 break;
 702         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
 703                 p_link->speed = 50000;
 704                 break;
 705         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
 706                 p_link->speed = 40000;
 707                 break;
 708         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
 709                 p_link->speed = 25000;
 710                 break;
 711         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
 712                 p_link->speed = 20000;
 713                 break;
 714         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
 715                 p_link->speed = 10000;
 716                 break;
 717         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
 718                 p_link->full_duplex = false;
 719                 /* Fall-through */
 720         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
 721                 p_link->speed = 1000;
 722                 break;
 723         default:
 724                 p_link->speed = 0;
 725         }
 726
 727         /* We never store total line speed as p_link->speed is
 728          * again changes according to bandwidth allocation.
 729          */
 730         if (p_link->link_up && p_link->speed)
 731                 p_link->line_speed = p_link->speed;
 732         else
 733                 p_link->line_speed = 0;
 734
 735         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
 736         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
 737
 738         /* Max bandwidth configuration */
 739         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
 740                                            p_link, max_bw);
 741
 742         /* Mintz bandwidth configuration */
 743         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
 744                                            p_link, min_bw);
 745         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
 746                                               p_link->min_pf_rate);
 747
 748         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
 749         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
 750         p_link->parallel_detection = !!(status &
 751                                          LINK_STATUS_PARALLEL_DETECTION_USED);
 752         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
 753
 754         p_link->partner_adv_speed |=
 755             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
 756             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
 757         p_link->partner_adv_speed |=
 758             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
 759             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
 760         p_link->partner_adv_speed |=
 761             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
 762             ECORE_LINK_PARTNER_SPEED_10G : 0;
 763         p_link->partner_adv_speed |=
 764             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
 765             ECORE_LINK_PARTNER_SPEED_20G : 0;
 766         p_link->partner_adv_speed |=
 767             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
 768             ECORE_LINK_PARTNER_SPEED_25G : 0;
 769         p_link->partner_adv_speed |=
 770             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
 771             ECORE_LINK_PARTNER_SPEED_40G : 0;
 772         p_link->partner_adv_speed |=
 773             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
 774             ECORE_LINK_PARTNER_SPEED_50G : 0;
 775         p_link->partner_adv_speed |=
 776             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
 777             ECORE_LINK_PARTNER_SPEED_100G : 0;
 778
 779         p_link->partner_tx_flow_ctrl_en =
 780             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
 781         p_link->partner_rx_flow_ctrl_en =
 782             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
 783
 784         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
 785         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
 786                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
 787                 break;
 788         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
 789                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
 790                 break;
 791         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
 792                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
 793                 break;
 794         default:
 795                 p_link->partner_adv_pause = 0;
 796         }
 797
 798         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
 799
 800         OSAL_LINK_UPDATE(p_hwfn);
 801 }
 802
 803 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
 804                                         struct ecore_ptt *p_ptt, bool b_up)
 805 {
 806         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
 807         struct ecore_mcp_mb_params mb_params;
 808         union drv_union_data union_data;
 809         struct eth_phy_cfg *p_phy_cfg;
 810         enum _ecore_status_t rc = ECORE_SUCCESS;
 811         u32 cmd;
 812
 813 #ifndef ASIC_ONLY
 814         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 815                 return ECORE_SUCCESS;
 816 #endif
 817
 818         /* Set the shmem configuration according to params */
 819         p_phy_cfg = &union_data.drv_phy_cfg;
 820         OSAL_MEMSET(p_phy_cfg, 0, sizeof(*p_phy_cfg));
 821         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
 822         if (!params->speed.autoneg)
 823                 p_phy_cfg->speed = params->speed.forced_speed;
 824         p_phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
 825         p_phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
 826         p_phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
 827         p_phy_cfg->adv_speed = params->speed.advertised_speeds;
 828         p_phy_cfg->loopback_mode = params->loopback_mode;
 829         p_hwfn->b_drv_link_init = b_up;
 830
 831         if (b_up)
 832                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 833                            "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
 834                            " adv_speed 0x%08x, loopback 0x%08x\n",
 835                            p_phy_cfg->speed, p_phy_cfg->pause,
 836                            p_phy_cfg->adv_speed, p_phy_cfg->loopback_mode);
 837         else
 838                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
 839
 840         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 841         mb_params.cmd = cmd;
 842         mb_params.p_data_src = &union_data;
 843         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 844
 845         /* if mcp fails to respond we must abort */
 846         if (rc != ECORE_SUCCESS) {
 847                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 848                 return rc;
 849         }
 850
 851         /* Reset the link status if needed */
 852         if (!b_up)
 853                 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
 854
 855         return rc;
 856 }
 857
 858 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
 859                                    struct ecore_ptt *p_ptt)
 860 {
 861         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
 862
 863         /* TODO - Add support for VFs */
 864         if (IS_VF(p_hwfn->p_dev))
 865                 return ECORE_INVAL;
 866
 867         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 868                                                  PUBLIC_PATH);
 869         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
 870         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
 871
 872         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
 873                                  path_addr +
 874                                  OFFSETOF(struct public_path, process_kill)) &
 875             PROCESS_KILL_COUNTER_MASK;
 876
 877         return proc_kill_cnt;
 878 }
 879
 880 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
 881                                           struct ecore_ptt *p_ptt)
 882 {
 883         struct ecore_dev *p_dev = p_hwfn->p_dev;
 884         u32 proc_kill_cnt;
 885
 886         /* Prevent possible attentions/interrupts during the recovery handling
 887          * and till its load phase, during which they will be re-enabled.
 888          */
 889         ecore_int_igu_disable_int(p_hwfn, p_ptt);
 890
 891         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
 892
 893         /* The following operations should be done once, and thus in CMT mode
 894          * are carried out by only the first HW function.
 895          */
 896         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
 897                 return;
 898
 899         if (p_dev->recov_in_prog) {
 900                 DP_NOTICE(p_hwfn, false,
 901                           "Ignoring the indication since a recovery"
 902                           " process is already in progress\n");
 903                 return;
 904         }
 905
 906         p_dev->recov_in_prog = true;
 907
 908         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
 909         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
 910
 911         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
 912 }
 913
 914 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
 915                                           struct ecore_ptt *p_ptt,
 916                                           enum MFW_DRV_MSG_TYPE type)
 917 {
 918         enum ecore_mcp_protocol_type stats_type;
 919         union ecore_mcp_protocol_stats stats;
 920         struct ecore_mcp_mb_params mb_params;
 921         union drv_union_data union_data;
 922         u32 hsi_param;
 923
 924         switch (type) {
 925         case MFW_DRV_MSG_GET_LAN_STATS:
 926                 stats_type = ECORE_MCP_LAN_STATS;
 927                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
 928                 break;
 929         default:
 930                 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
 931                 return;
 932         }
 933
 934         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
 935
 936         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 937         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
 938         mb_params.param = hsi_param;
 939         OSAL_MEMCPY(&union_data, &stats, sizeof(stats));
 940         mb_params.p_data_src = &union_data;
 941         ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 942 }
 943
 944 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
 945                                     struct public_func *p_shmem_info)
 946 {
 947         struct ecore_mcp_function_info *p_info;
 948
 949         p_info = &p_hwfn->mcp_info->func_info;
 950
 951         /* TODO - bandwidth min/max should have valid values of 1-100,
 952          * as well as some indication that the feature is disabled.
 953          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
 954          * limit and correct value to min `1' and max `100' if limit isn't in
 955          * range.
 956          */
 957         p_info->bandwidth_min = (p_shmem_info->config &
 958                                  FUNC_MF_CFG_MIN_BW_MASK) >>
 959             FUNC_MF_CFG_MIN_BW_SHIFT;
 960         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
 961                 DP_INFO(p_hwfn,
 962                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
 963                         p_info->bandwidth_min);
 964                 p_info->bandwidth_min = 1;
 965         }
 966
 967         p_info->bandwidth_max = (p_shmem_info->config &
 968                                  FUNC_MF_CFG_MAX_BW_MASK) >>
 969             FUNC_MF_CFG_MAX_BW_SHIFT;
 970         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
 971                 DP_INFO(p_hwfn,
 972                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
 973                         p_info->bandwidth_max);
 974                 p_info->bandwidth_max = 100;
 975         }
 976 }
 977
 978 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
 979                                     struct ecore_ptt *p_ptt,
 980                                     struct public_func *p_data,
 981                                     int pfid)
 982 {
 983         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 984                                         PUBLIC_FUNC);
 985         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 986         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
 987         u32 i, size;
 988
 989         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
 990
 991         size = OSAL_MIN_T(u32, sizeof(*p_data),
 992                           SECTION_SIZE(mfw_path_offsize));
 993         for (i = 0; i < size / sizeof(u32); i++)
 994                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
 995                                               func_addr + (i << 2));
 996
 997         return size;
 998 }
 999
1000 static void
1001 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1002 {
1003         struct ecore_mcp_function_info *p_info;
1004         struct public_func shmem_info;
1005         u32 resp = 0, param = 0;
1006
1007         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1008
1009         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1010
1011         p_info = &p_hwfn->mcp_info->func_info;
1012
1013         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1014
1015         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1016
1017         /* Acknowledge the MFW */
1018         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1019                       &param);
1020 }
1021
1022 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1023                                          struct ecore_ptt *p_ptt)
1024 {
1025         /* A single notification should be sent to upper driver in CMT mode */
1026         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1027                 return;
1028
1029         DP_NOTICE(p_hwfn, false,
1030                   "Fan failure was detected on the network interface card"
1031                   " and it's going to be shut down.\n");
1032
1033         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1034 }
1035
1036 static enum _ecore_status_t
1037 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1038                     u32 mdump_cmd, union drv_union_data *p_data_src,
1039                     union drv_union_data *p_data_dst, u32 *p_mcp_resp)
1040 {
1041         struct ecore_mcp_mb_params mb_params;
1042         enum _ecore_status_t rc;
1043
1044         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1045         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1046         mb_params.param = mdump_cmd;
1047         mb_params.p_data_src = p_data_src;
1048         mb_params.p_data_dst = p_data_dst;
1049         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1050         if (rc != ECORE_SUCCESS)
1051                 return rc;
1052
1053         *p_mcp_resp = mb_params.mcp_resp;
1054         if (*p_mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1055                 DP_NOTICE(p_hwfn, false,
1056                           "MFW claims that the mdump command is illegal [mdump_cmd 0x%x]\n",
1057                           mdump_cmd);
1058                 rc = ECORE_INVAL;
1059         }
1060
1061         return rc;
1062 }
1063
1064 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1065                                                 struct ecore_ptt *p_ptt)
1066 {
1067         u32 mcp_resp;
1068
1069         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_ACK,
1070                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1071 }
1072
1073 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1074                                                 struct ecore_ptt *p_ptt,
1075                                                 u32 epoch)
1076 {
1077         union drv_union_data union_data;
1078         u32 mcp_resp;
1079
1080         OSAL_MEMCPY(&union_data.raw_data, &epoch, sizeof(epoch));
1081
1082         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_SET_VALUES,
1083                                    &union_data, OSAL_NULL, &mcp_resp);
1084 }
1085
1086 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1087                                              struct ecore_ptt *p_ptt)
1088 {
1089         u32 mcp_resp;
1090
1091         p_hwfn->p_dev->mdump_en = true;
1092
1093         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_TRIGGER,
1094                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1095 }
1096
1097 static enum _ecore_status_t
1098 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1099                            struct mdump_config_stc *p_mdump_config)
1100 {
1101         union drv_union_data union_data;
1102         u32 mcp_resp;
1103         enum _ecore_status_t rc;
1104
1105         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_GET_CONFIG,
1106                                  OSAL_NULL, &union_data, &mcp_resp);
1107         if (rc != ECORE_SUCCESS)
1108                 return rc;
1109
1110         /* A zero response implies that the mdump command is not supported */
1111         if (!mcp_resp)
1112                 return ECORE_NOTIMPL;
1113
1114         if (mcp_resp != FW_MSG_CODE_OK) {
1115                 DP_NOTICE(p_hwfn, false,
1116                           "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1117                           mcp_resp);
1118                 rc = ECORE_UNKNOWN_ERROR;
1119         }
1120
1121         OSAL_MEMCPY(p_mdump_config, &union_data.mdump_config,
1122                     sizeof(*p_mdump_config));
1123
1124         return rc;
1125 }
1126
1127 enum _ecore_status_t
1128 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1129                          struct ecore_mdump_info *p_mdump_info)
1130 {
1131         u32 addr, global_offsize, global_addr;
1132         struct mdump_config_stc mdump_config;
1133         enum _ecore_status_t rc;
1134
1135         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1136
1137         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1138                                     PUBLIC_GLOBAL);
1139         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1140         global_addr = SECTION_ADDR(global_offsize, 0);
1141         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1142                                         global_addr +
1143                                         OFFSETOF(struct public_global,
1144                                                  mdump_reason));
1145
1146         if (p_mdump_info->reason) {
1147                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1148                 if (rc != ECORE_SUCCESS)
1149                         return rc;
1150
1151                 p_mdump_info->version = mdump_config.version;
1152                 p_mdump_info->config = mdump_config.config;
1153                 p_mdump_info->epoch = mdump_config.epoc;
1154                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1155                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1156
1157                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1158                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1159                            p_mdump_info->reason, p_mdump_info->version,
1160                            p_mdump_info->config, p_mdump_info->epoch,
1161                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1162         } else {
1163                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1164                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1165         }
1166
1167         return ECORE_SUCCESS;
1168 }
1169
1170 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1171                                                 struct ecore_ptt *p_ptt)
1172 {
1173         u32 mcp_resp;
1174
1175         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_CLEAR_LOGS,
1176                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1177 }
1178
1179 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1180                                             struct ecore_ptt *p_ptt)
1181 {
1182         /* In CMT mode - no need for more than a single acknowledgment to the
1183          * MFW, and no more than a single notification to the upper driver.
1184          */
1185         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1186                 return;
1187
1188         DP_NOTICE(p_hwfn, false,
1189                   "Received a critical error notification from the MFW!\n");
1190
1191         if (p_hwfn->p_dev->mdump_en) {
1192                 DP_NOTICE(p_hwfn, false,
1193                           "Not acknowledging the notification to allow the MFW crash dump\n");
1194                 p_hwfn->p_dev->mdump_en = false;
1195                 return;
1196         }
1197
1198         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1199         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1200 }
1201
1202 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1203                                              struct ecore_ptt *p_ptt)
1204 {
1205         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1206         enum _ecore_status_t rc = ECORE_SUCCESS;
1207         bool found = false;
1208         u16 i;
1209
1210         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1211
1212         /* Read Messages from MFW */
1213         ecore_mcp_read_mb(p_hwfn, p_ptt);
1214
1215         /* Compare current messages to old ones */
1216         for (i = 0; i < info->mfw_mb_length; i++) {
1217                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1218                         continue;
1219
1220                 found = true;
1221
1222                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1223                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1224                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1225
1226                 switch (i) {
1227                 case MFW_DRV_MSG_LINK_CHANGE:
1228                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1229                         break;
1230                 case MFW_DRV_MSG_VF_DISABLED:
1231                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1232                         break;
1233                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1234                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1235                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1236                         break;
1237                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1238                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1239                                                     ECORE_DCBX_REMOTE_MIB);
1240                         break;
1241                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1242                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1243                                                     ECORE_DCBX_OPERATIONAL_MIB);
1244                         break;
1245                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1246                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1247                         break;
1248                 case MFW_DRV_MSG_ERROR_RECOVERY:
1249                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1250                         break;
1251                 case MFW_DRV_MSG_GET_LAN_STATS:
1252                 case MFW_DRV_MSG_GET_FCOE_STATS:
1253                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1254                 case MFW_DRV_MSG_GET_RDMA_STATS:
1255                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1256                         break;
1257                 case MFW_DRV_MSG_BW_UPDATE:
1258                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1259                         break;
1260                 case MFW_DRV_MSG_FAILURE_DETECTED:
1261                         ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1262                         break;
1263                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1264                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1265                         break;
1266                 default:
1267                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1268                         rc = ECORE_INVAL;
1269                 }
1270         }
1271
1272         /* ACK everything */
1273         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1274                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1275
1276                 /* MFW expect answer in BE, so we force write in that format */
1277                 ecore_wr(p_hwfn, p_ptt,
1278                          info->mfw_mb_addr + sizeof(u32) +
1279                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1280                          sizeof(u32) + i * sizeof(u32), val);
1281         }
1282
1283         if (!found) {
1284                 DP_NOTICE(p_hwfn, false,
1285                           "Received an MFW message indication but no"
1286                           " new message!\n");
1287                 rc = ECORE_INVAL;
1288         }
1289
1290         /* Copy the new mfw messages into the shadow */
1291         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1292
1293         return rc;
1294 }
1295
1296 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1297                                            struct ecore_ptt *p_ptt,
1298                                            u32 *p_mfw_ver,
1299                                            u32 *p_running_bundle_id)
1300 {
1301         u32 global_offsize;
1302
1303 #ifndef ASIC_ONLY
1304         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1305                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1306                 return ECORE_SUCCESS;
1307         }
1308 #endif
1309
1310         if (IS_VF(p_hwfn->p_dev)) {
1311                 if (p_hwfn->vf_iov_info) {
1312                         struct pfvf_acquire_resp_tlv *p_resp;
1313
1314                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1315                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1316                         return ECORE_SUCCESS;
1317                 } else {
1318                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1319                                    "VF requested MFW version prior to ACQUIRE\n");
1320                         return ECORE_INVAL;
1321                 }
1322         }
1323
1324         global_offsize = ecore_rd(p_hwfn, p_ptt,
1325                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1326                                                        public_base,
1327                                                        PUBLIC_GLOBAL));
1328         *p_mfw_ver =
1329             ecore_rd(p_hwfn, p_ptt,
1330                      SECTION_ADDR(global_offsize,
1331                                   0) + OFFSETOF(struct public_global, mfw_ver));
1332
1333         if (p_running_bundle_id != OSAL_NULL) {
1334                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1335                                                 SECTION_ADDR(global_offsize,
1336                                                              0) +
1337                                                 OFFSETOF(struct public_global,
1338                                                          running_bundle_id));
1339         }
1340
1341         return ECORE_SUCCESS;
1342 }
1343
1344 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1345                                               u32 *p_media_type)
1346 {
1347         struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1348         struct ecore_ptt *p_ptt;
1349
1350         /* TODO - Add support for VFs */
1351         if (IS_VF(p_dev))
1352                 return ECORE_INVAL;
1353
1354         if (!ecore_mcp_is_init(p_hwfn)) {
1355                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1356                 return ECORE_BUSY;
1357         }
1358
1359         *p_media_type = MEDIA_UNSPECIFIED;
1360
1361         p_ptt = ecore_ptt_acquire(p_hwfn);
1362         if (!p_ptt)
1363                 return ECORE_BUSY;
1364
1365         *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1366                                  OFFSETOF(struct public_port, media_type));
1367
1368         ecore_ptt_release(p_hwfn, p_ptt);
1369
1370         return ECORE_SUCCESS;
1371 }
1372
1373 /* @DPDK */
1374 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1375 static void
1376 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
1377                                  enum ecore_pci_personality *p_proto)
1378 {
1379         *p_proto = ECORE_PCI_ETH;
1380
1381         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1382                    "According to Legacy capabilities, L2 personality is %08x\n",
1383                    (u32)*p_proto);
1384 }
1385
1386 /* @DPDK */
1387 static enum _ecore_status_t
1388 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
1389                               struct ecore_ptt *p_ptt,
1390                               enum ecore_pci_personality *p_proto)
1391 {
1392         u32 resp = 0, param = 0;
1393         enum _ecore_status_t rc;
1394
1395         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1396                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1397                    (u32)*p_proto, resp, param);
1398         return ECORE_SUCCESS;
1399 }
1400
1401 static enum _ecore_status_t
1402 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1403                           struct public_func *p_info,
1404                           struct ecore_ptt *p_ptt,
1405                           enum ecore_pci_personality *p_proto)
1406 {
1407         enum _ecore_status_t rc = ECORE_SUCCESS;
1408
1409         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1410         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1411                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
1412                     ECORE_SUCCESS)
1413                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1414                 break;
1415         default:
1416                 rc = ECORE_INVAL;
1417         }
1418
1419         return rc;
1420 }
1421
1422 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1423                                                     struct ecore_ptt *p_ptt)
1424 {
1425         struct ecore_mcp_function_info *info;
1426         struct public_func shmem_info;
1427
1428         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1429         info = &p_hwfn->mcp_info->func_info;
1430
1431         info->pause_on_host = (shmem_info.config &
1432                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1433
1434         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1435                                       &info->protocol)) {
1436                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1437                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1438                 return ECORE_INVAL;
1439         }
1440
1441         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1442
1443         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1444                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1445                 info->mac[1] = (u8)(shmem_info.mac_upper);
1446                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1447                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1448                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1449                 info->mac[5] = (u8)(shmem_info.mac_lower);
1450         } else {
1451                 /* TODO - are there protocols for which there's no MAC? */
1452                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1453         }
1454
1455         /* TODO - are these calculations true for BE machine? */
1456         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1457                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1458         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1459                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1460
1461         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1462
1463         info->mtu = (u16)shmem_info.mtu_size;
1464
1465         if (info->mtu == 0)
1466                 info->mtu = 1500;
1467
1468         info->mtu = (u16)shmem_info.mtu_size;
1469
1470         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1471                    "Read configuration from shmem: pause_on_host %02x"
1472                     " protocol %02x BW [%02x - %02x]"
1473                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1474                     " node %lx ovlan %04x\n",
1475                    info->pause_on_host, info->protocol,
1476                    info->bandwidth_min, info->bandwidth_max,
1477                    info->mac[0], info->mac[1], info->mac[2],
1478                    info->mac[3], info->mac[4], info->mac[5],
1479                    (unsigned long)info->wwn_port,
1480                    (unsigned long)info->wwn_node, info->ovlan);
1481
1482         return ECORE_SUCCESS;
1483 }
1484
1485 struct ecore_mcp_link_params
1486 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1487 {
1488         if (!p_hwfn || !p_hwfn->mcp_info)
1489                 return OSAL_NULL;
1490         return &p_hwfn->mcp_info->link_input;
1491 }
1492
1493 struct ecore_mcp_link_state
1494 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1495 {
1496         if (!p_hwfn || !p_hwfn->mcp_info)
1497                 return OSAL_NULL;
1498
1499 #ifndef ASIC_ONLY
1500         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1501                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1502                 p_hwfn->mcp_info->link_output.link_up = true;
1503         }
1504 #endif
1505
1506         return &p_hwfn->mcp_info->link_output;
1507 }
1508
1509 struct ecore_mcp_link_capabilities
1510 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1511 {
1512         if (!p_hwfn || !p_hwfn->mcp_info)
1513                 return OSAL_NULL;
1514         return &p_hwfn->mcp_info->link_capabilities;
1515 }
1516
1517 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1518                                      struct ecore_ptt *p_ptt)
1519 {
1520         u32 resp = 0, param = 0;
1521         enum _ecore_status_t rc;
1522
1523         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1524                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1525
1526         /* Wait for the drain to complete before returning */
1527         OSAL_MSLEEP(1020);
1528
1529         return rc;
1530 }
1531
1532 const struct ecore_mcp_function_info
1533 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1534 {
1535         if (!p_hwfn || !p_hwfn->mcp_info)
1536                 return OSAL_NULL;
1537         return &p_hwfn->mcp_info->func_info;
1538 }
1539
1540 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1541                                            struct ecore_ptt *p_ptt,
1542                                            struct ecore_mcp_nvm_params *params)
1543 {
1544         enum _ecore_status_t rc;
1545
1546         switch (params->type) {
1547         case ECORE_MCP_NVM_RD:
1548                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1549                                           params->nvm_common.offset,
1550                                           &params->nvm_common.resp,
1551                                           &params->nvm_common.param,
1552                                           params->nvm_rd.buf_size,
1553                                           params->nvm_rd.buf);
1554                 break;
1555         case ECORE_MCP_CMD:
1556                 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1557                                    params->nvm_common.offset,
1558                                    &params->nvm_common.resp,
1559                                    &params->nvm_common.param);
1560                 break;
1561         case ECORE_MCP_NVM_WR:
1562                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1563                                           params->nvm_common.offset,
1564                                           &params->nvm_common.resp,
1565                                           &params->nvm_common.param,
1566                                           params->nvm_wr.buf_size,
1567                                           params->nvm_wr.buf);
1568                 break;
1569         default:
1570                 rc = ECORE_NOTIMPL;
1571                 break;
1572         }
1573         return rc;
1574 }
1575
1576 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1577                                   struct ecore_ptt *p_ptt, u32 personalities)
1578 {
1579         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1580         struct public_func shmem_info;
1581         int i, count = 0, num_pfs;
1582
1583         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1584
1585         for (i = 0; i < num_pfs; i++) {
1586                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1587                                          MCP_PF_ID_BY_REL(p_hwfn, i));
1588                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1589                         continue;
1590
1591                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1592                                               &protocol) !=
1593                     ECORE_SUCCESS)
1594                         continue;
1595
1596                 if ((1 << ((u32)protocol)) & personalities)
1597                         count++;
1598         }
1599
1600         return count;
1601 }
1602
1603 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1604                                               struct ecore_ptt *p_ptt,
1605                                               u32 *p_flash_size)
1606 {
1607         u32 flash_size;
1608
1609 #ifndef ASIC_ONLY
1610         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1611                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
1612                 return ECORE_INVAL;
1613         }
1614 #endif
1615
1616         if (IS_VF(p_hwfn->p_dev))
1617                 return ECORE_INVAL;
1618
1619         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1620         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1621             MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1622         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1623
1624         *p_flash_size = flash_size;
1625
1626         return ECORE_SUCCESS;
1627 }
1628
1629 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
1630                                                   struct ecore_ptt *p_ptt)
1631 {
1632         struct ecore_dev *p_dev = p_hwfn->p_dev;
1633
1634         if (p_dev->recov_in_prog) {
1635                 DP_NOTICE(p_hwfn, false,
1636                           "Avoid triggering a recovery since such a process"
1637                           " is already in progress\n");
1638                 return ECORE_AGAIN;
1639         }
1640
1641         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
1642         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
1643
1644         return ECORE_SUCCESS;
1645 }
1646
1647 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
1648                                               struct ecore_ptt *p_ptt,
1649                                               u8 vf_id, u8 num)
1650 {
1651         u32 resp = 0, param = 0, rc_param = 0;
1652         enum _ecore_status_t rc;
1653
1654 /* Only Leader can configure MSIX, and need to take CMT into account */
1655
1656         if (!IS_LEAD_HWFN(p_hwfn))
1657                 return ECORE_SUCCESS;
1658         num *= p_hwfn->p_dev->num_hwfns;
1659
1660         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1661             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1662         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1663             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1664
1665         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1666                            &resp, &rc_param);
1667
1668         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1669                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
1670                           vf_id);
1671                 rc = ECORE_INVAL;
1672         } else {
1673                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1674                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1675                             num, vf_id);
1676         }
1677
1678         return rc;
1679 }
1680
1681 enum _ecore_status_t
1682 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1683                            struct ecore_mcp_drv_version *p_ver)
1684 {
1685         struct drv_version_stc *p_drv_version;
1686         struct ecore_mcp_mb_params mb_params;
1687         union drv_union_data union_data;
1688         u32 num_words, i;
1689         void *p_name;
1690         OSAL_BE32 val;
1691         enum _ecore_status_t rc;
1692
1693 #ifndef ASIC_ONLY
1694         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
1695                 return ECORE_SUCCESS;
1696 #endif
1697
1698         p_drv_version = &union_data.drv_version;
1699         p_drv_version->version = p_ver->version;
1700         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
1701         for (i = 0; i < num_words; i++) {
1702                 /* The driver name is expected to be in a big-endian format */
1703                 p_name = &p_ver->name[i * sizeof(u32)];
1704                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
1705                 *(u32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1706         }
1707
1708         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1709         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1710         mb_params.p_data_src = &union_data;
1711         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1712         if (rc != ECORE_SUCCESS)
1713                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1714
1715         return rc;
1716 }
1717
1718 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
1719                                     struct ecore_ptt *p_ptt)
1720 {
1721         enum _ecore_status_t rc;
1722         u32 resp = 0, param = 0;
1723
1724         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1725                            &param);
1726         if (rc != ECORE_SUCCESS)
1727                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1728
1729         return rc;
1730 }
1731
1732 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
1733                                       struct ecore_ptt *p_ptt)
1734 {
1735         u32 value, cpu_mode;
1736
1737         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1738
1739         value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1740         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1741         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1742         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1743
1744         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
1745 }
1746
1747 enum _ecore_status_t
1748 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
1749                                    struct ecore_ptt *p_ptt,
1750                                    enum ecore_ov_client client)
1751 {
1752         enum _ecore_status_t rc;
1753         u32 resp = 0, param = 0;
1754         u32 drv_mb_param;
1755
1756         switch (client) {
1757         case ECORE_OV_CLIENT_DRV:
1758                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1759                 break;
1760         case ECORE_OV_CLIENT_USER:
1761                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1762                 break;
1763         case ECORE_OV_CLIENT_VENDOR_SPEC:
1764                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
1765                 break;
1766         default:
1767                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
1768                 return ECORE_INVAL;
1769         }
1770
1771         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1772                            drv_mb_param, &resp, &param);
1773         if (rc != ECORE_SUCCESS)
1774                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1775
1776         return rc;
1777 }
1778
1779 enum _ecore_status_t
1780 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
1781                                  struct ecore_ptt *p_ptt,
1782                                  enum ecore_ov_driver_state drv_state)
1783 {
1784         enum _ecore_status_t rc;
1785         u32 resp = 0, param = 0;
1786         u32 drv_mb_param;
1787
1788         switch (drv_state) {
1789         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
1790                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1791                 break;
1792         case ECORE_OV_DRIVER_STATE_DISABLED:
1793                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1794                 break;
1795         case ECORE_OV_DRIVER_STATE_ACTIVE:
1796                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1797                 break;
1798         default:
1799                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
1800                 return ECORE_INVAL;
1801         }
1802
1803         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1804                            drv_mb_param, &resp, &param);
1805         if (rc != ECORE_SUCCESS)
1806                 DP_ERR(p_hwfn, "Failed to send driver state\n");
1807
1808         return rc;
1809 }
1810
1811 enum _ecore_status_t
1812 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1813                          struct ecore_fc_npiv_tbl *p_table)
1814 {
1815         return 0;
1816 }
1817
1818 enum _ecore_status_t
1819 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
1820                         struct ecore_ptt *p_ptt, u16 mtu)
1821 {
1822         return 0;
1823 }
1824
1825 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
1826                                        struct ecore_ptt *p_ptt,
1827                                        enum ecore_led_mode mode)
1828 {
1829         u32 resp = 0, param = 0, drv_mb_param;
1830         enum _ecore_status_t rc;
1831
1832         switch (mode) {
1833         case ECORE_LED_MODE_ON:
1834                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1835                 break;
1836         case ECORE_LED_MODE_OFF:
1837                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1838                 break;
1839         case ECORE_LED_MODE_RESTORE:
1840                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1841                 break;
1842         default:
1843                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
1844                 return ECORE_INVAL;
1845         }
1846
1847         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1848                            drv_mb_param, &resp, &param);
1849         if (rc != ECORE_SUCCESS)
1850                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1851
1852         return rc;
1853 }
1854
1855 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
1856                                              struct ecore_ptt *p_ptt,
1857                                              u32 mask_parities)
1858 {
1859         enum _ecore_status_t rc;
1860         u32 resp = 0, param = 0;
1861
1862         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1863                            mask_parities, &resp, &param);
1864
1865         if (rc != ECORE_SUCCESS) {
1866                 DP_ERR(p_hwfn,
1867                        "MCP response failure for mask parities, aborting\n");
1868         } else if (resp != FW_MSG_CODE_OK) {
1869                 DP_ERR(p_hwfn,
1870                        "MCP did not ack mask parity request. Old MFW?\n");
1871                 rc = ECORE_INVAL;
1872         }
1873
1874         return rc;
1875 }
1876
1877 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
1878                                         u8 *p_buf, u32 len)
1879 {
1880         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1881         u32 bytes_left, offset, bytes_to_copy, buf_size;
1882         struct ecore_mcp_nvm_params params;
1883         struct ecore_ptt *p_ptt;
1884         enum _ecore_status_t rc = ECORE_SUCCESS;
1885
1886         p_ptt = ecore_ptt_acquire(p_hwfn);
1887         if (!p_ptt)
1888                 return ECORE_BUSY;
1889
1890         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1891         bytes_left = len;
1892         offset = 0;
1893         params.type = ECORE_MCP_NVM_RD;
1894         params.nvm_rd.buf_size = &buf_size;
1895         params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
1896         while (bytes_left > 0) {
1897                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1898                                            MCP_DRV_NVM_BUF_LEN);
1899                 params.nvm_common.offset = (addr + offset) |
1900                     (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
1901                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1902                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1903                 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
1904                                             FW_MSG_CODE_NVM_OK)) {
1905                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1906                         break;
1907                 }
1908
1909                 /* This can be a lengthy process, and it's possible scheduler
1910                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
1911                  */
1912                 if (bytes_left % 0x1000 <
1913                     (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
1914                         OSAL_MSLEEP(1);
1915
1916                 offset += *params.nvm_rd.buf_size;
1917                 bytes_left -= *params.nvm_rd.buf_size;
1918         }
1919
1920         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1921         ecore_ptt_release(p_hwfn, p_ptt);
1922
1923         return rc;
1924 }
1925
1926 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
1927                                         u32 addr, u8 *p_buf, u32 len)
1928 {
1929         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1930         struct ecore_mcp_nvm_params params;
1931         struct ecore_ptt *p_ptt;
1932         enum _ecore_status_t rc;
1933
1934         p_ptt = ecore_ptt_acquire(p_hwfn);
1935         if (!p_ptt)
1936                 return ECORE_BUSY;
1937
1938         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1939         params.type = ECORE_MCP_NVM_RD;
1940         params.nvm_rd.buf_size = &len;
1941         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
1942             DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
1943         params.nvm_common.offset = addr;
1944         params.nvm_rd.buf = (u32 *)p_buf;
1945         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1946         if (rc != ECORE_SUCCESS)
1947                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1948
1949         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1950         ecore_ptt_release(p_hwfn, p_ptt);
1951
1952         return rc;
1953 }
1954
1955 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
1956 {
1957         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1958         struct ecore_mcp_nvm_params params;
1959         struct ecore_ptt *p_ptt;
1960
1961         p_ptt = ecore_ptt_acquire(p_hwfn);
1962         if (!p_ptt)
1963                 return ECORE_BUSY;
1964
1965         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1966         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
1967         ecore_ptt_release(p_hwfn, p_ptt);
1968
1969         return ECORE_SUCCESS;
1970 }
1971
1972 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
1973 {
1974         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1975         struct ecore_mcp_nvm_params params;
1976         struct ecore_ptt *p_ptt;
1977         enum _ecore_status_t rc;
1978
1979         p_ptt = ecore_ptt_acquire(p_hwfn);
1980         if (!p_ptt)
1981                 return ECORE_BUSY;
1982         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1983         params.type = ECORE_MCP_CMD;
1984         params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
1985         params.nvm_common.offset = addr;
1986         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1987         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1988         ecore_ptt_release(p_hwfn, p_ptt);
1989
1990         return rc;
1991 }
1992
1993 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
1994                                                   u32 addr)
1995 {
1996         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1997         struct ecore_mcp_nvm_params params;
1998         struct ecore_ptt *p_ptt;
1999         enum _ecore_status_t rc;
2000
2001         p_ptt = ecore_ptt_acquire(p_hwfn);
2002         if (!p_ptt)
2003                 return ECORE_BUSY;
2004         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2005         params.type = ECORE_MCP_CMD;
2006         params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
2007         params.nvm_common.offset = addr;
2008         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2009         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2010         ecore_ptt_release(p_hwfn, p_ptt);
2011
2012         return rc;
2013 }
2014
2015 /* rc receives ECORE_INVAL as default parameter because
2016  * it might not enter the while loop if the len is 0
2017  */
2018 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2019                                          u32 addr, u8 *p_buf, u32 len)
2020 {
2021         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2022         enum _ecore_status_t rc = ECORE_INVAL;
2023         struct ecore_mcp_nvm_params params;
2024         struct ecore_ptt *p_ptt;
2025         u32 buf_idx, buf_size;
2026
2027         p_ptt = ecore_ptt_acquire(p_hwfn);
2028         if (!p_ptt)
2029                 return ECORE_BUSY;
2030
2031         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2032         params.type = ECORE_MCP_NVM_WR;
2033         if (cmd == ECORE_PUT_FILE_DATA)
2034                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2035         else
2036                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2037         buf_idx = 0;
2038         while (buf_idx < len) {
2039                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2040                                       MCP_DRV_NVM_BUF_LEN);
2041                 params.nvm_common.offset = ((buf_size <<
2042                                              DRV_MB_PARAM_NVM_LEN_SHIFT)
2043                                             | addr) + buf_idx;
2044                 params.nvm_wr.buf_size = buf_size;
2045                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2046                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2047                 if (rc != ECORE_SUCCESS ||
2048                     ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2049                      (params.nvm_common.resp !=
2050                       FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2051                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2052
2053                 /* This can be a lengthy process, and it's possible scheduler
2054                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2055                  */
2056                 if (buf_idx % 0x1000 >
2057                     (buf_idx + buf_size) % 0x1000)
2058                         OSAL_MSLEEP(1);
2059
2060                 buf_idx += buf_size;
2061         }
2062
2063         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2064         ecore_ptt_release(p_hwfn, p_ptt);
2065
2066         return rc;
2067 }
2068
2069 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2070                                          u32 addr, u8 *p_buf, u32 len)
2071 {
2072         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2073         struct ecore_mcp_nvm_params params;
2074         struct ecore_ptt *p_ptt;
2075         enum _ecore_status_t rc;
2076
2077         p_ptt = ecore_ptt_acquire(p_hwfn);
2078         if (!p_ptt)
2079                 return ECORE_BUSY;
2080
2081         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2082         params.type = ECORE_MCP_NVM_WR;
2083         params.nvm_wr.buf_size = len;
2084         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2085             DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2086         params.nvm_common.offset = addr;
2087         params.nvm_wr.buf = (u32 *)p_buf;
2088         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2089         if (rc != ECORE_SUCCESS)
2090                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2091         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2092         ecore_ptt_release(p_hwfn, p_ptt);
2093
2094         return rc;
2095 }
2096
2097 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2098                                                    u32 addr)
2099 {
2100         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2101         struct ecore_mcp_nvm_params params;
2102         struct ecore_ptt *p_ptt;
2103         enum _ecore_status_t rc;
2104
2105         p_ptt = ecore_ptt_acquire(p_hwfn);
2106         if (!p_ptt)
2107                 return ECORE_BUSY;
2108
2109         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2110         params.type = ECORE_MCP_CMD;
2111         params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2112         params.nvm_common.offset = addr;
2113         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2114         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2115         ecore_ptt_release(p_hwfn, p_ptt);
2116
2117         return rc;
2118 }
2119
2120 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2121                                             struct ecore_ptt *p_ptt,
2122                                             u32 port, u32 addr, u32 offset,
2123                                             u32 len, u8 *p_buf)
2124 {
2125         struct ecore_mcp_nvm_params params;
2126         enum _ecore_status_t rc;
2127         u32 bytes_left, bytes_to_copy, buf_size;
2128
2129         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2130         params.nvm_common.offset =
2131                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2132                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2133         addr = offset;
2134         offset = 0;
2135         bytes_left = len;
2136         params.type = ECORE_MCP_NVM_RD;
2137         params.nvm_rd.buf_size = &buf_size;
2138         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2139         while (bytes_left > 0) {
2140                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2141                                            MAX_I2C_TRANSACTION_SIZE);
2142                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2143                 params.nvm_common.offset &=
2144                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2145                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2146                 params.nvm_common.offset |=
2147                         ((addr + offset) <<
2148                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2149                 params.nvm_common.offset |=
2150                         (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2151                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2152                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2153                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2154                         return ECORE_NODEV;
2155                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2156                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2157                         return ECORE_UNKNOWN_ERROR;
2158
2159                 offset += *params.nvm_rd.buf_size;
2160                 bytes_left -= *params.nvm_rd.buf_size;
2161         }
2162
2163         return ECORE_SUCCESS;
2164 }
2165
2166 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2167                                              struct ecore_ptt *p_ptt,
2168                                              u32 port, u32 addr, u32 offset,
2169                                              u32 len, u8 *p_buf)
2170 {
2171         struct ecore_mcp_nvm_params params;
2172         enum _ecore_status_t rc;
2173         u32 buf_idx, buf_size;
2174
2175         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2176         params.nvm_common.offset =
2177                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2178                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2179         params.type = ECORE_MCP_NVM_WR;
2180         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2181         buf_idx = 0;
2182         while (buf_idx < len) {
2183                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2184                                       MAX_I2C_TRANSACTION_SIZE);
2185                 params.nvm_common.offset &=
2186                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2187                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2188                 params.nvm_common.offset |=
2189                         ((offset + buf_idx) <<
2190                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2191                 params.nvm_common.offset |=
2192                         (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2193                 params.nvm_wr.buf_size = buf_size;
2194                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2195                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2196                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2197                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2198                         return ECORE_NODEV;
2199                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2200                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2201                         return ECORE_UNKNOWN_ERROR;
2202
2203                 buf_idx += buf_size;
2204         }
2205
2206         return ECORE_SUCCESS;
2207 }
2208
2209 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2210                                          struct ecore_ptt *p_ptt,
2211                                          u16 gpio, u32 *gpio_val)
2212 {
2213         enum _ecore_status_t rc = ECORE_SUCCESS;
2214         u32 drv_mb_param = 0, rsp;
2215
2216         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2217
2218         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2219                            drv_mb_param, &rsp, gpio_val);
2220
2221         if (rc != ECORE_SUCCESS)
2222                 return rc;
2223
2224         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2225                 return ECORE_UNKNOWN_ERROR;
2226
2227         return ECORE_SUCCESS;
2228 }
2229
2230 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2231                                           struct ecore_ptt *p_ptt,
2232                                           u16 gpio, u16 gpio_val)
2233 {
2234         enum _ecore_status_t rc = ECORE_SUCCESS;
2235         u32 drv_mb_param = 0, param, rsp;
2236
2237         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2238                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2239
2240         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2241                            drv_mb_param, &rsp, &param);
2242
2243         if (rc != ECORE_SUCCESS)
2244                 return rc;
2245
2246         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2247                 return ECORE_UNKNOWN_ERROR;
2248
2249         return ECORE_SUCCESS;
2250 }
2251
2252 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2253                                          struct ecore_ptt *p_ptt,
2254                                          u16 gpio, u32 *gpio_direction,
2255                                          u32 *gpio_ctrl)
2256 {
2257         u32 drv_mb_param = 0, rsp, val = 0;
2258         enum _ecore_status_t rc = ECORE_SUCCESS;
2259
2260         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2261
2262         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2263                            drv_mb_param, &rsp, &val);
2264         if (rc != ECORE_SUCCESS)
2265                 return rc;
2266
2267         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2268                            DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2269         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2270                       DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2271
2272         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2273                 return ECORE_UNKNOWN_ERROR;
2274
2275         return ECORE_SUCCESS;
2276 }
2277
2278 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2279                                                   struct ecore_ptt *p_ptt)
2280 {
2281         u32 drv_mb_param = 0, rsp, param;
2282         enum _ecore_status_t rc = ECORE_SUCCESS;
2283
2284         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2285                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2286
2287         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2288                            drv_mb_param, &rsp, &param);
2289
2290         if (rc != ECORE_SUCCESS)
2291                 return rc;
2292
2293         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2294             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2295                 rc = ECORE_UNKNOWN_ERROR;
2296
2297         return rc;
2298 }
2299
2300 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2301                                                struct ecore_ptt *p_ptt)
2302 {
2303         u32 drv_mb_param, rsp, param;
2304         enum _ecore_status_t rc = ECORE_SUCCESS;
2305
2306         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2307                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2308
2309         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2310                            drv_mb_param, &rsp, &param);
2311
2312         if (rc != ECORE_SUCCESS)
2313                 return rc;
2314
2315         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2316             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2317                 rc = ECORE_UNKNOWN_ERROR;
2318
2319         return rc;
2320 }
2321
2322 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2323         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2324 {
2325         u32 drv_mb_param = 0, rsp;
2326         enum _ecore_status_t rc = ECORE_SUCCESS;
2327
2328         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2329                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2330
2331         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2332                            drv_mb_param, &rsp, num_images);
2333
2334         if (rc != ECORE_SUCCESS)
2335                 return rc;
2336
2337         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2338                 rc = ECORE_UNKNOWN_ERROR;
2339
2340         return rc;
2341 }
2342
2343 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2344         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2345         struct bist_nvm_image_att *p_image_att, u32 image_index)
2346 {
2347         struct ecore_mcp_nvm_params params;
2348         enum _ecore_status_t rc;
2349         u32 buf_size;
2350
2351         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2352         params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2353                                     DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2354         params.nvm_common.offset |= (image_index <<
2355                                     DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2356
2357         params.type = ECORE_MCP_NVM_RD;
2358         params.nvm_rd.buf_size = &buf_size;
2359         params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2360         params.nvm_rd.buf = (u32 *)p_image_att;
2361
2362         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2363         if (rc != ECORE_SUCCESS)
2364                 return rc;
2365
2366         if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2367             (p_image_att->return_code != 1))
2368                 rc = ECORE_UNKNOWN_ERROR;
2369
2370         return rc;
2371 }
2372
2373 enum _ecore_status_t
2374 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2375                                struct ecore_ptt *p_ptt,
2376                                struct ecore_temperature_info *p_temp_info)
2377 {
2378         struct ecore_temperature_sensor *p_temp_sensor;
2379         struct temperature_status_stc *p_mfw_temp_info;
2380         struct ecore_mcp_mb_params mb_params;
2381         union drv_union_data union_data;
2382         u32 val;
2383         enum _ecore_status_t rc;
2384         u8 i;
2385
2386         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2387         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2388         mb_params.p_data_dst = &union_data;
2389         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2390         if (rc != ECORE_SUCCESS)
2391                 return rc;
2392
2393         p_mfw_temp_info = &union_data.temp_info;
2394
2395         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2396         p_temp_info->num_sensors = OSAL_MIN_T(u32,
2397                                               p_mfw_temp_info->num_of_sensors,
2398                                               ECORE_MAX_NUM_OF_SENSORS);
2399         for (i = 0; i < p_temp_info->num_sensors; i++) {
2400                 val = p_mfw_temp_info->sensor[i];
2401                 p_temp_sensor = &p_temp_info->sensors[i];
2402                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2403                                                  SENSOR_LOCATION_SHIFT;
2404                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2405                                                 THRESHOLD_HIGH_SHIFT;
2406                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2407                                           CRITICAL_TEMPERATURE_SHIFT;
2408                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2409                                               CURRENT_TEMP_SHIFT;
2410         }
2411
2412         return ECORE_SUCCESS;
2413 }
2414
2415 enum _ecore_status_t ecore_mcp_get_mba_versions(
2416         struct ecore_hwfn *p_hwfn,
2417         struct ecore_ptt *p_ptt,
2418         struct ecore_mba_vers *p_mba_vers)
2419 {
2420         struct ecore_mcp_nvm_params params;
2421         enum _ecore_status_t rc;
2422         u32 buf_size;
2423
2424         OSAL_MEM_ZERO(&params, sizeof(params));
2425         params.type = ECORE_MCP_NVM_RD;
2426         params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2427         params.nvm_common.offset = 0;
2428         params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2429         params.nvm_rd.buf_size = &buf_size;
2430         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2431
2432         if (rc != ECORE_SUCCESS)
2433                 return rc;
2434
2435         if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2436             FW_MSG_CODE_NVM_OK)
2437                 rc = ECORE_UNKNOWN_ERROR;
2438
2439         if (buf_size != MCP_DRV_NVM_BUF_LEN)
2440                 rc = ECORE_UNKNOWN_ERROR;
2441
2442         return rc;
2443 }
2444
2445 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2446                                               struct ecore_ptt *p_ptt,
2447                                               u64 *num_events)
2448 {
2449         u32 rsp;
2450
2451         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2452                              0, &rsp, (u32 *)num_events);
2453 }
2454
2455 #define ECORE_RESC_ALLOC_VERSION_MAJOR  1
2456 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
2457 #define ECORE_RESC_ALLOC_VERSION                                \
2458         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
2459           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) |    \
2460          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
2461           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2462
2463 enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
2464                                              struct ecore_ptt *p_ptt,
2465                                              struct resource_info *p_resc_info,
2466                                              u32 *p_mcp_resp, u32 *p_mcp_param)
2467 {
2468         struct ecore_mcp_mb_params mb_params;
2469         union drv_union_data union_data;
2470         enum _ecore_status_t rc;
2471
2472         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2473         mb_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2474         mb_params.param = ECORE_RESC_ALLOC_VERSION;
2475         OSAL_MEMCPY(&union_data.resource, p_resc_info, sizeof(*p_resc_info));
2476         mb_params.p_data_src = &union_data;
2477         mb_params.p_data_dst = &union_data;
2478         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2479         if (rc != ECORE_SUCCESS)
2480                 return rc;
2481
2482         *p_mcp_resp = mb_params.mcp_resp;
2483         *p_mcp_param = mb_params.mcp_param;
2484
2485         OSAL_MEMCPY(p_resc_info, &union_data.resource, sizeof(*p_resc_info));
2486
2487         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2488                    "MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x,"
2489                    " offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n",
2490                    *p_mcp_param, p_resc_info->res_id, p_resc_info->size,
2491                    p_resc_info->offset, p_resc_info->vf_size,
2492                    p_resc_info->vf_offset, p_resc_info->flags);
2493
2494         return ECORE_SUCCESS;
2495 }
2496
2497 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
2498                                                struct ecore_ptt *p_ptt)
2499 {
2500         u32 mcp_resp, mcp_param;
2501
2502         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2503                              &mcp_resp, &mcp_param);
2504 }
2505
2506 enum _ecore_status_t
2507 ecore_mfw_process_tlv_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2508 {
2509         return ECORE_SUCCESS;
2510 }