2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
19 #include "ecore_iov_api.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
22 #include "ecore_dcbx.h"
24 #define CHIP_MCP_RESP_ITER_US 10
25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
28 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
31 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
35 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
38 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
39 OFFSETOF(struct public_drv_mb, _field), _val)
41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
42 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
43 OFFSETOF(struct public_drv_mb, _field))
45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
46 DRV_ID_PDA_COMP_VER_SHIFT)
48 #define MCP_BYTES_PER_MBIT_SHIFT 17
52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
57 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
64 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
66 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
68 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
70 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
71 "port_addr = 0x%x, port_id 0x%02x\n",
72 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
77 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
82 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
86 if (!p_hwfn->mcp_info->public_base)
89 for (i = 0; i < length; i++) {
90 tmp = ecore_rd(p_hwfn, p_ptt,
91 p_hwfn->mcp_info->mfw_mb_addr +
92 (i << 2) + sizeof(u32));
94 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
95 OSAL_BE32_TO_CPU(tmp);
99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
101 if (p_hwfn->mcp_info) {
102 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
103 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
104 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
106 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
108 return ECORE_SUCCESS;
111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
112 struct ecore_ptt *p_ptt)
114 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
115 u32 drv_mb_offsize, mfw_mb_offsize;
116 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
119 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
120 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
121 p_info->public_base = 0;
126 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
127 if (!p_info->public_base)
130 p_info->public_base |= GRCBASE_MCP;
132 /* Calculate the driver and MFW mailbox address */
133 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
134 SECTION_OFFSIZE_ADDR(p_info->public_base,
136 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
137 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
138 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
139 " mcp_pf_id = 0x%x\n",
140 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
142 /* Set the MFW MB address */
143 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
144 SECTION_OFFSIZE_ADDR(p_info->public_base,
146 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
147 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
148 p_info->mfw_mb_addr);
150 /* Get the current driver mailbox sequence before sending
153 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
154 DRV_MSG_SEQ_NUMBER_MASK;
156 /* Get current FW pulse sequence */
157 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
160 p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
161 MISCS_REG_GENERIC_POR_0);
163 return ECORE_SUCCESS;
166 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
167 struct ecore_ptt *p_ptt)
169 struct ecore_mcp_info *p_info;
172 /* Allocate mcp_info structure */
173 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
174 sizeof(*p_hwfn->mcp_info));
175 if (!p_hwfn->mcp_info)
177 p_info = p_hwfn->mcp_info;
179 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
180 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
181 /* Do not free mcp_info here, since public_base indicate that
182 * the MCP is not initialized
184 return ECORE_SUCCESS;
187 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
188 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
189 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
190 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
193 /* Initialize the MFW spinlock */
194 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
195 OSAL_SPIN_LOCK_INIT(&p_info->lock);
197 return ECORE_SUCCESS;
200 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
201 ecore_mcp_free(p_hwfn);
205 /* Locks the MFW mailbox of a PF to ensure a single access.
206 * The lock is achieved in most cases by holding a spinlock, causing other
207 * threads to wait till a previous access is done.
208 * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
209 * access is achieved by setting a blocking flag, which will fail other
210 * competing contexts to send their mailboxes.
212 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
215 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
217 /* The spinlock shouldn't be acquired when the mailbox command is
218 * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
219 * pending [UN]LOAD_REQ command of another PF together with a spinlock
220 * (i.e. interrupts are disabled) - can lead to a deadlock.
221 * It is assumed that for a single PF, no other mailbox commands can be
222 * sent from another context while sending LOAD_REQ, and that any
223 * parallel commands to UNLOAD_REQ can be cancelled.
225 if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
226 p_hwfn->mcp_info->block_mb_sending = false;
228 /* There's at least a single command that is sent by ecore during the
229 * load sequence [expectation of MFW].
231 if ((p_hwfn->mcp_info->block_mb_sending) &&
232 (cmd != DRV_MSG_CODE_FEATURE_SUPPORT)) {
233 DP_NOTICE(p_hwfn, false,
234 "Trying to send a MFW mailbox command [0x%x]"
235 " in parallel to [UN]LOAD_REQ. Aborting.\n",
237 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
241 if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
242 p_hwfn->mcp_info->block_mb_sending = true;
243 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
246 return ECORE_SUCCESS;
249 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
251 if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
252 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
255 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
256 struct ecore_ptt *p_ptt)
258 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
259 u32 delay = CHIP_MCP_RESP_ITER_US;
260 u32 org_mcp_reset_seq, cnt = 0;
261 enum _ecore_status_t rc = ECORE_SUCCESS;
264 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
265 delay = EMUL_MCP_RESP_ITER_US;
268 /* Ensure that only a single thread is accessing the mailbox at a
271 rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
272 if (rc != ECORE_SUCCESS)
275 /* Set drv command along with the updated sequence */
276 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
277 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
280 /* Wait for MFW response */
282 /* Give the FW up to 500 second (50*1000*10usec) */
283 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
284 MISCS_REG_GENERIC_POR_0)) &&
285 (cnt++ < ECORE_MCP_RESET_RETRIES));
287 if (org_mcp_reset_seq !=
288 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
289 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
290 "MCP was reset after %d usec\n", cnt * delay);
292 DP_ERR(p_hwfn, "Failed to reset MCP\n");
296 ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
301 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
302 struct ecore_ptt *p_ptt,
307 u32 delay = CHIP_MCP_RESP_ITER_US;
308 u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
309 u32 seq, cnt = 1, actual_mb_seq;
310 enum _ecore_status_t rc = ECORE_SUCCESS;
313 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
314 delay = EMUL_MCP_RESP_ITER_US;
315 /* There is a built-in delay of 100usec in each MFW response read */
316 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
320 /* Get actual driver mailbox sequence */
321 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
322 DRV_MSG_SEQ_NUMBER_MASK;
324 /* Use MCP history register to check if MCP reset occurred between
327 if (p_hwfn->mcp_info->mcp_hist !=
328 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
329 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
330 ecore_load_mcp_offsets(p_hwfn, p_ptt);
331 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
333 seq = ++p_hwfn->mcp_info->drv_mb_seq;
336 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
338 /* Set drv command along with the updated sequence */
339 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
342 /* Wait for MFW response */
344 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
346 /* Give the FW up to 5 second (500*10ms) */
347 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
348 (cnt++ < max_retries));
350 /* Is this a reply to our command? */
351 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
352 *o_mcp_resp &= FW_MSG_CODE_MASK;
353 /* Get the MCP param */
354 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
357 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
361 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
366 static enum _ecore_status_t
367 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
368 struct ecore_ptt *p_ptt,
369 struct ecore_mcp_mb_params *p_mb_params)
371 union drv_union_data union_data;
373 enum _ecore_status_t rc;
375 /* MCP not initialized */
376 if (!ecore_mcp_is_init(p_hwfn)) {
377 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
381 if (p_mb_params->data_src_size > sizeof(union_data) ||
382 p_mb_params->data_dst_size > sizeof(union_data)) {
384 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
385 p_mb_params->data_src_size, p_mb_params->data_dst_size,
390 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
391 OFFSETOF(struct public_drv_mb, union_data);
393 /* Ensure that only a single thread is accessing the mailbox at a
396 rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
397 if (rc != ECORE_SUCCESS)
400 OSAL_MEM_ZERO(&union_data, sizeof(union_data));
401 if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
402 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
403 p_mb_params->data_src_size);
404 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
407 rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
408 p_mb_params->param, &p_mb_params->mcp_resp,
409 &p_mb_params->mcp_param);
411 if (p_mb_params->p_data_dst != OSAL_NULL &&
412 p_mb_params->data_dst_size)
413 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
414 union_data_addr, p_mb_params->data_dst_size);
416 ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
421 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
422 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
423 u32 *o_mcp_resp, u32 *o_mcp_param)
425 struct ecore_mcp_mb_params mb_params;
426 enum _ecore_status_t rc;
429 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
430 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
432 loaded_port[p_hwfn->port_id]--;
433 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
436 return ECORE_SUCCESS;
440 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
442 mb_params.param = param;
443 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
444 if (rc != ECORE_SUCCESS)
447 *o_mcp_resp = mb_params.mcp_resp;
448 *o_mcp_param = mb_params.mcp_param;
450 return ECORE_SUCCESS;
453 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
454 struct ecore_ptt *p_ptt,
459 u32 i_txn_size, u32 *i_buf)
461 struct ecore_mcp_mb_params mb_params;
462 enum _ecore_status_t rc;
464 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
466 mb_params.param = param;
467 mb_params.p_data_src = i_buf;
468 mb_params.data_src_size = (u8)i_txn_size;
469 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
470 if (rc != ECORE_SUCCESS)
473 *o_mcp_resp = mb_params.mcp_resp;
474 *o_mcp_param = mb_params.mcp_param;
476 return ECORE_SUCCESS;
479 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
480 struct ecore_ptt *p_ptt,
485 u32 *o_txn_size, u32 *o_buf)
487 struct ecore_mcp_mb_params mb_params;
488 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
489 enum _ecore_status_t rc;
491 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
493 mb_params.param = param;
494 mb_params.p_data_dst = raw_data;
496 /* Use the maximal value since the actual one is part of the response */
497 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
499 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
500 if (rc != ECORE_SUCCESS)
503 *o_mcp_resp = mb_params.mcp_resp;
504 *o_mcp_param = mb_params.mcp_param;
506 *o_txn_size = *o_mcp_param;
508 OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
510 return ECORE_SUCCESS;
514 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
517 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
520 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
521 else if (!loaded_port[p_hwfn->port_id])
522 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
524 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
526 /* On CMT, always tell that it's engine */
527 if (p_hwfn->p_dev->num_hwfns > 1)
528 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
530 *p_load_code = load_phase;
532 loaded_port[p_hwfn->port_id]++;
534 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
535 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
536 *p_load_code, loaded, p_hwfn->port_id,
537 loaded_port[p_hwfn->port_id]);
542 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
543 enum ecore_override_force_load override_force_load)
545 bool can_force_load = false;
547 switch (override_force_load) {
548 case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
549 can_force_load = true;
551 case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
552 can_force_load = false;
555 can_force_load = (drv_role == DRV_ROLE_OS &&
556 exist_drv_role == DRV_ROLE_PREBOOT) ||
557 (drv_role == DRV_ROLE_KDUMP &&
558 exist_drv_role == DRV_ROLE_OS);
562 return can_force_load;
565 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
566 struct ecore_ptt *p_ptt)
568 u32 resp = 0, param = 0;
569 enum _ecore_status_t rc;
571 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
573 if (rc != ECORE_SUCCESS)
574 DP_NOTICE(p_hwfn, false,
575 "Failed to send cancel load request, rc = %d\n", rc);
580 #define CONFIG_ECORE_L2_BITMAP_IDX (0x1 << 0)
581 #define CONFIG_ECORE_SRIOV_BITMAP_IDX (0x1 << 1)
582 #define CONFIG_ECORE_ROCE_BITMAP_IDX (0x1 << 2)
583 #define CONFIG_ECORE_IWARP_BITMAP_IDX (0x1 << 3)
584 #define CONFIG_ECORE_FCOE_BITMAP_IDX (0x1 << 4)
585 #define CONFIG_ECORE_ISCSI_BITMAP_IDX (0x1 << 5)
586 #define CONFIG_ECORE_LL2_BITMAP_IDX (0x1 << 6)
588 static u32 ecore_get_config_bitmap(void)
590 u32 config_bitmap = 0x0;
592 #ifdef CONFIG_ECORE_L2
593 config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
595 #ifdef CONFIG_ECORE_SRIOV
596 config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
598 #ifdef CONFIG_ECORE_ROCE
599 config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
601 #ifdef CONFIG_ECORE_IWARP
602 config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
604 #ifdef CONFIG_ECORE_FCOE
605 config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
607 #ifdef CONFIG_ECORE_ISCSI
608 config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
610 #ifdef CONFIG_ECORE_LL2
611 config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
614 return config_bitmap;
617 struct ecore_load_req_in_params {
619 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT 0
620 #define ECORE_LOAD_REQ_HSI_VER_1 1
627 bool avoid_eng_reset;
630 struct ecore_load_req_out_params {
640 static enum _ecore_status_t
641 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
642 struct ecore_load_req_in_params *p_in_params,
643 struct ecore_load_req_out_params *p_out_params)
645 struct ecore_mcp_mb_params mb_params;
646 struct load_req_stc load_req;
647 struct load_rsp_stc load_rsp;
649 enum _ecore_status_t rc;
651 OSAL_MEM_ZERO(&load_req, sizeof(load_req));
652 load_req.drv_ver_0 = p_in_params->drv_ver_0;
653 load_req.drv_ver_1 = p_in_params->drv_ver_1;
654 load_req.fw_ver = p_in_params->fw_ver;
655 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE,
656 p_in_params->drv_role);
657 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
658 p_in_params->timeout_val);
659 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
660 p_in_params->force_cmd);
661 ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
662 p_in_params->avoid_eng_reset);
664 hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
665 DRV_ID_MCP_HSI_VER_CURRENT :
666 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
668 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
669 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
670 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
671 mb_params.p_data_src = &load_req;
672 mb_params.data_src_size = sizeof(load_req);
673 mb_params.p_data_dst = &load_rsp;
674 mb_params.data_dst_size = sizeof(load_rsp);
676 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
677 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
679 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
680 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
681 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
682 ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
684 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
685 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
686 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
687 load_req.drv_ver_0, load_req.drv_ver_1,
688 load_req.fw_ver, load_req.misc0,
689 ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
690 ECORE_MFW_GET_FIELD(load_req.misc0,
692 ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
693 ECORE_MFW_GET_FIELD(load_req.misc0,
696 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
697 if (rc != ECORE_SUCCESS) {
698 DP_NOTICE(p_hwfn, false,
699 "Failed to send load request, rc = %d\n", rc);
703 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
704 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
705 p_out_params->load_code = mb_params.mcp_resp;
707 if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
708 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
709 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
710 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
711 load_rsp.drv_ver_0, load_rsp.drv_ver_1,
712 load_rsp.fw_ver, load_rsp.misc0,
713 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
714 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
715 ECORE_MFW_GET_FIELD(load_rsp.misc0,
718 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
719 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
720 p_out_params->exist_fw_ver = load_rsp.fw_ver;
721 p_out_params->exist_drv_role =
722 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
723 p_out_params->mfw_hsi_ver =
724 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
725 p_out_params->drv_exists =
726 ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
727 LOAD_RSP_FLAGS0_DRV_EXISTS;
730 return ECORE_SUCCESS;
733 static void ecore_get_mfw_drv_role(struct ecore_hwfn *p_hwfn,
734 enum ecore_drv_role drv_role,
738 case ECORE_DRV_ROLE_OS:
739 *p_mfw_drv_role = DRV_ROLE_OS;
741 case ECORE_DRV_ROLE_KDUMP:
742 *p_mfw_drv_role = DRV_ROLE_KDUMP;
747 enum ecore_load_req_force {
748 ECORE_LOAD_REQ_FORCE_NONE,
749 ECORE_LOAD_REQ_FORCE_PF,
750 ECORE_LOAD_REQ_FORCE_ALL,
753 static void ecore_get_mfw_force_cmd(struct ecore_hwfn *p_hwfn,
754 enum ecore_load_req_force force_cmd,
758 case ECORE_LOAD_REQ_FORCE_NONE:
759 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
761 case ECORE_LOAD_REQ_FORCE_PF:
762 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
764 case ECORE_LOAD_REQ_FORCE_ALL:
765 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
770 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
771 struct ecore_ptt *p_ptt,
772 struct ecore_load_req_params *p_params)
774 struct ecore_load_req_out_params out_params;
775 struct ecore_load_req_in_params in_params;
776 u8 mfw_drv_role = 0, mfw_force_cmd;
777 enum _ecore_status_t rc;
780 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
781 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
782 return ECORE_SUCCESS;
786 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
787 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
788 in_params.drv_ver_0 = ECORE_VERSION;
789 in_params.drv_ver_1 = ecore_get_config_bitmap();
790 in_params.fw_ver = STORM_FW_VERSION;
791 ecore_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
792 in_params.drv_role = mfw_drv_role;
793 in_params.timeout_val = p_params->timeout_val;
794 ecore_get_mfw_force_cmd(p_hwfn, ECORE_LOAD_REQ_FORCE_NONE,
796 in_params.force_cmd = mfw_force_cmd;
797 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
799 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
800 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
801 if (rc != ECORE_SUCCESS)
804 /* First handle cases where another load request should/might be sent:
805 * - MFW expects the old interface [HSI version = 1]
806 * - MFW responds that a force load request is required
808 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
810 "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
812 /* The previous load request set the mailbox blocking */
813 p_hwfn->mcp_info->block_mb_sending = false;
815 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
816 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
817 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
819 if (rc != ECORE_SUCCESS)
821 } else if (out_params.load_code ==
822 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
823 /* The previous load request set the mailbox blocking */
824 p_hwfn->mcp_info->block_mb_sending = false;
826 if (ecore_mcp_can_force_load(in_params.drv_role,
827 out_params.exist_drv_role,
828 p_params->override_force_load)) {
830 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
831 in_params.drv_role, in_params.fw_ver,
832 in_params.drv_ver_0, in_params.drv_ver_1,
833 out_params.exist_drv_role,
834 out_params.exist_fw_ver,
835 out_params.exist_drv_ver_0,
836 out_params.exist_drv_ver_1);
838 ecore_get_mfw_force_cmd(p_hwfn,
839 ECORE_LOAD_REQ_FORCE_ALL,
842 in_params.force_cmd = mfw_force_cmd;
843 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
844 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
846 if (rc != ECORE_SUCCESS)
849 DP_NOTICE(p_hwfn, false,
850 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
851 in_params.drv_role, in_params.fw_ver,
852 in_params.drv_ver_0, in_params.drv_ver_1,
853 out_params.exist_drv_role,
854 out_params.exist_fw_ver,
855 out_params.exist_drv_ver_0,
856 out_params.exist_drv_ver_1);
858 ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
863 /* Now handle the other types of responses.
864 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
865 * expected here after the additional revised load requests were sent.
867 switch (out_params.load_code) {
868 case FW_MSG_CODE_DRV_LOAD_ENGINE:
869 case FW_MSG_CODE_DRV_LOAD_PORT:
870 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
871 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
872 out_params.drv_exists) {
873 /* The role and fw/driver version match, but the PF is
874 * already loaded and has not been unloaded gracefully.
875 * This is unexpected since a quasi-FLR request was
876 * previously sent as part of ecore_hw_prepare().
878 DP_NOTICE(p_hwfn, false,
879 "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
884 DP_NOTICE(p_hwfn, false,
885 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
886 out_params.load_code);
890 p_params->load_code = out_params.load_code;
892 return ECORE_SUCCESS;
895 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
896 struct ecore_ptt *p_ptt)
898 u32 resp = 0, param = 0;
899 enum _ecore_status_t rc;
901 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
903 if (rc != ECORE_SUCCESS) {
904 DP_NOTICE(p_hwfn, false,
905 "Failed to send a LOAD_DONE command, rc = %d\n", rc);
909 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
911 /* Check if there is a DID mismatch between nvm-cfg/efuse */
912 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
913 DP_NOTICE(p_hwfn, false,
914 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
916 return ECORE_SUCCESS;
919 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
920 struct ecore_ptt *p_ptt)
922 u32 wol_param, mcp_resp, mcp_param;
925 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
927 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
928 &mcp_resp, &mcp_param);
931 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
932 struct ecore_ptt *p_ptt)
934 struct ecore_mcp_mb_params mb_params;
935 struct mcp_mac wol_mac;
937 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
938 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
940 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
943 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
944 struct ecore_ptt *p_ptt)
946 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
948 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
949 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
950 ECORE_PATH_ID(p_hwfn));
951 u32 disabled_vfs[VF_MAX_STATIC / 32];
954 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
955 "Reading Disabled VF information from [offset %08x],"
957 mfw_path_offsize, path_addr);
959 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
960 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
962 OFFSETOF(struct public_path,
965 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
966 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
967 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
970 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
971 OSAL_VF_FLR_UPDATE(p_hwfn);
974 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
975 struct ecore_ptt *p_ptt,
978 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
980 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
981 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
983 struct ecore_mcp_mb_params mb_params;
984 enum _ecore_status_t rc;
987 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
988 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
989 "Acking VFs [%08x,...,%08x] - %08x\n",
990 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
992 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
993 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
994 mb_params.p_data_src = vfs_to_ack;
995 mb_params.data_src_size = VF_MAX_STATIC / 8;
996 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
998 if (rc != ECORE_SUCCESS) {
999 DP_NOTICE(p_hwfn, false,
1000 "Failed to pass ACK for VF flr to MFW\n");
1001 return ECORE_TIMEOUT;
1004 /* TMP - clear the ACK bits; should be done by MFW */
1005 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1006 ecore_wr(p_hwfn, p_ptt,
1008 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1009 i * sizeof(u32), 0);
1014 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1015 struct ecore_ptt *p_ptt)
1017 u32 transceiver_state;
1019 transceiver_state = ecore_rd(p_hwfn, p_ptt,
1020 p_hwfn->mcp_info->port_addr +
1021 OFFSETOF(struct public_port,
1024 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1025 "Received transceiver state update [0x%08x] from mfw"
1027 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1028 OFFSETOF(struct public_port,
1029 transceiver_data)));
1031 transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
1033 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1034 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1036 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1039 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1040 struct ecore_ptt *p_ptt,
1043 struct ecore_mcp_link_state *p_link;
1047 p_link = &p_hwfn->mcp_info->link_output;
1048 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1050 status = ecore_rd(p_hwfn, p_ptt,
1051 p_hwfn->mcp_info->port_addr +
1052 OFFSETOF(struct public_port, link_status));
1053 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1054 "Received link update [0x%08x] from mfw"
1056 status, (u32)(p_hwfn->mcp_info->port_addr +
1057 OFFSETOF(struct public_port,
1060 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1061 "Resetting link indications\n");
1065 if (p_hwfn->b_drv_link_init)
1066 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1068 p_link->link_up = false;
1070 p_link->full_duplex = true;
1071 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1072 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1073 p_link->speed = 100000;
1075 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1076 p_link->speed = 50000;
1078 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1079 p_link->speed = 40000;
1081 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1082 p_link->speed = 25000;
1084 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1085 p_link->speed = 20000;
1087 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1088 p_link->speed = 10000;
1090 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1091 p_link->full_duplex = false;
1093 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1094 p_link->speed = 1000;
1100 /* We never store total line speed as p_link->speed is
1101 * again changes according to bandwidth allocation.
1103 if (p_link->link_up && p_link->speed)
1104 p_link->line_speed = p_link->speed;
1106 p_link->line_speed = 0;
1108 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1109 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1111 /* Max bandwidth configuration */
1112 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1115 /* Mintz bandwidth configuration */
1116 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1118 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1119 p_link->min_pf_rate);
1121 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1122 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1123 p_link->parallel_detection = !!(status &
1124 LINK_STATUS_PARALLEL_DETECTION_USED);
1125 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1127 p_link->partner_adv_speed |=
1128 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1129 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1130 p_link->partner_adv_speed |=
1131 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1132 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1133 p_link->partner_adv_speed |=
1134 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1135 ECORE_LINK_PARTNER_SPEED_10G : 0;
1136 p_link->partner_adv_speed |=
1137 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1138 ECORE_LINK_PARTNER_SPEED_20G : 0;
1139 p_link->partner_adv_speed |=
1140 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1141 ECORE_LINK_PARTNER_SPEED_25G : 0;
1142 p_link->partner_adv_speed |=
1143 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1144 ECORE_LINK_PARTNER_SPEED_40G : 0;
1145 p_link->partner_adv_speed |=
1146 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1147 ECORE_LINK_PARTNER_SPEED_50G : 0;
1148 p_link->partner_adv_speed |=
1149 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1150 ECORE_LINK_PARTNER_SPEED_100G : 0;
1152 p_link->partner_tx_flow_ctrl_en =
1153 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1154 p_link->partner_rx_flow_ctrl_en =
1155 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1157 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1158 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1159 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1161 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1162 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1164 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1165 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1168 p_link->partner_adv_pause = 0;
1171 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1173 OSAL_LINK_UPDATE(p_hwfn);
1176 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1177 struct ecore_ptt *p_ptt, bool b_up)
1179 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1180 struct ecore_mcp_mb_params mb_params;
1181 struct eth_phy_cfg phy_cfg;
1182 enum _ecore_status_t rc = ECORE_SUCCESS;
1186 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1187 return ECORE_SUCCESS;
1190 /* Set the shmem configuration according to params */
1191 OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1192 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1193 if (!params->speed.autoneg)
1194 phy_cfg.speed = params->speed.forced_speed;
1195 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1196 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1197 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1198 phy_cfg.adv_speed = params->speed.advertised_speeds;
1199 phy_cfg.loopback_mode = params->loopback_mode;
1200 p_hwfn->b_drv_link_init = b_up;
1203 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1204 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1205 phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1206 phy_cfg.loopback_mode);
1208 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1210 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1211 mb_params.cmd = cmd;
1212 mb_params.p_data_src = &phy_cfg;
1213 mb_params.data_src_size = sizeof(phy_cfg);
1214 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1216 /* if mcp fails to respond we must abort */
1217 if (rc != ECORE_SUCCESS) {
1218 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1222 /* Reset the link status if needed */
1224 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
1229 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1230 struct ecore_ptt *p_ptt)
1232 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1234 /* TODO - Add support for VFs */
1235 if (IS_VF(p_hwfn->p_dev))
1238 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1240 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1241 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1243 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1245 OFFSETOF(struct public_path, process_kill)) &
1246 PROCESS_KILL_COUNTER_MASK;
1248 return proc_kill_cnt;
1251 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1252 struct ecore_ptt *p_ptt)
1254 struct ecore_dev *p_dev = p_hwfn->p_dev;
1257 /* Prevent possible attentions/interrupts during the recovery handling
1258 * and till its load phase, during which they will be re-enabled.
1260 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1262 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1264 /* The following operations should be done once, and thus in CMT mode
1265 * are carried out by only the first HW function.
1267 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1270 if (p_dev->recov_in_prog) {
1271 DP_NOTICE(p_hwfn, false,
1272 "Ignoring the indication since a recovery"
1273 " process is already in progress\n");
1277 p_dev->recov_in_prog = true;
1279 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1280 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1282 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1285 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1286 struct ecore_ptt *p_ptt,
1287 enum MFW_DRV_MSG_TYPE type)
1289 enum ecore_mcp_protocol_type stats_type;
1290 union ecore_mcp_protocol_stats stats;
1291 struct ecore_mcp_mb_params mb_params;
1293 enum _ecore_status_t rc;
1296 case MFW_DRV_MSG_GET_LAN_STATS:
1297 stats_type = ECORE_MCP_LAN_STATS;
1298 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1301 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1305 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1307 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1308 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1309 mb_params.param = hsi_param;
1310 mb_params.p_data_src = &stats;
1311 mb_params.data_src_size = sizeof(stats);
1312 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1313 if (rc != ECORE_SUCCESS)
1314 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1317 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1318 struct public_func *p_shmem_info)
1320 struct ecore_mcp_function_info *p_info;
1322 p_info = &p_hwfn->mcp_info->func_info;
1324 /* TODO - bandwidth min/max should have valid values of 1-100,
1325 * as well as some indication that the feature is disabled.
1326 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1327 * limit and correct value to min `1' and max `100' if limit isn't in
1330 p_info->bandwidth_min = (p_shmem_info->config &
1331 FUNC_MF_CFG_MIN_BW_MASK) >>
1332 FUNC_MF_CFG_MIN_BW_SHIFT;
1333 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1335 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1336 p_info->bandwidth_min);
1337 p_info->bandwidth_min = 1;
1340 p_info->bandwidth_max = (p_shmem_info->config &
1341 FUNC_MF_CFG_MAX_BW_MASK) >>
1342 FUNC_MF_CFG_MAX_BW_SHIFT;
1343 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1345 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1346 p_info->bandwidth_max);
1347 p_info->bandwidth_max = 100;
1351 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1352 struct ecore_ptt *p_ptt,
1353 struct public_func *p_data,
1356 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1358 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1359 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1362 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1364 size = OSAL_MIN_T(u32, sizeof(*p_data),
1365 SECTION_SIZE(mfw_path_offsize));
1366 for (i = 0; i < size / sizeof(u32); i++)
1367 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1368 func_addr + (i << 2));
1374 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1376 struct ecore_mcp_function_info *p_info;
1377 struct public_func shmem_info;
1378 u32 resp = 0, param = 0;
1380 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1382 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1384 p_info = &p_hwfn->mcp_info->func_info;
1386 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1388 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1390 /* Acknowledge the MFW */
1391 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1395 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1396 struct ecore_ptt *p_ptt)
1398 /* A single notification should be sent to upper driver in CMT mode */
1399 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1402 DP_NOTICE(p_hwfn, false,
1403 "Fan failure was detected on the network interface card"
1404 " and it's going to be shut down.\n");
1406 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1409 struct ecore_mdump_cmd_params {
1418 static enum _ecore_status_t
1419 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1420 struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1422 struct ecore_mcp_mb_params mb_params;
1423 enum _ecore_status_t rc;
1425 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1426 mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1427 mb_params.param = p_mdump_cmd_params->cmd;
1428 mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1429 mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1430 mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1431 mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1432 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1433 if (rc != ECORE_SUCCESS)
1436 p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1437 if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1438 DP_NOTICE(p_hwfn, false,
1439 "MFW claims that the mdump command is illegal [mdump_cmd 0x%x]\n",
1440 p_mdump_cmd_params->cmd);
1447 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1448 struct ecore_ptt *p_ptt)
1450 struct ecore_mdump_cmd_params mdump_cmd_params;
1452 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1453 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1455 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1458 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1459 struct ecore_ptt *p_ptt,
1462 struct ecore_mdump_cmd_params mdump_cmd_params;
1464 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1465 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1466 mdump_cmd_params.p_data_src = &epoch;
1467 mdump_cmd_params.data_src_size = sizeof(epoch);
1469 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1472 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1473 struct ecore_ptt *p_ptt)
1475 struct ecore_mdump_cmd_params mdump_cmd_params;
1477 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1478 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1480 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1483 static enum _ecore_status_t
1484 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1485 struct mdump_config_stc *p_mdump_config)
1487 struct ecore_mdump_cmd_params mdump_cmd_params;
1488 enum _ecore_status_t rc;
1490 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1491 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1492 mdump_cmd_params.p_data_dst = p_mdump_config;
1493 mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1495 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1496 if (rc != ECORE_SUCCESS)
1499 if (mdump_cmd_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1501 "The mdump command is not supported by the MFW\n");
1502 return ECORE_NOTIMPL;
1505 if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1506 DP_NOTICE(p_hwfn, false,
1507 "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1508 mdump_cmd_params.mcp_resp);
1509 rc = ECORE_UNKNOWN_ERROR;
1515 enum _ecore_status_t
1516 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1517 struct ecore_mdump_info *p_mdump_info)
1519 u32 addr, global_offsize, global_addr;
1520 struct mdump_config_stc mdump_config;
1521 enum _ecore_status_t rc;
1523 OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1525 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1527 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1528 global_addr = SECTION_ADDR(global_offsize, 0);
1529 p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1531 OFFSETOF(struct public_global,
1534 if (p_mdump_info->reason) {
1535 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1536 if (rc != ECORE_SUCCESS)
1539 p_mdump_info->version = mdump_config.version;
1540 p_mdump_info->config = mdump_config.config;
1541 p_mdump_info->epoch = mdump_config.epoc;
1542 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1543 p_mdump_info->valid_logs = mdump_config.valid_logs;
1545 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1546 "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1547 p_mdump_info->reason, p_mdump_info->version,
1548 p_mdump_info->config, p_mdump_info->epoch,
1549 p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1551 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1552 "MFW mdump info: reason %d\n", p_mdump_info->reason);
1555 return ECORE_SUCCESS;
1558 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1559 struct ecore_ptt *p_ptt)
1561 struct ecore_mdump_cmd_params mdump_cmd_params;
1563 OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1564 mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1566 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1569 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1570 struct ecore_ptt *p_ptt)
1572 /* In CMT mode - no need for more than a single acknowledgment to the
1573 * MFW, and no more than a single notification to the upper driver.
1575 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1578 DP_NOTICE(p_hwfn, false,
1579 "Received a critical error notification from the MFW!\n");
1581 if (p_hwfn->p_dev->allow_mdump) {
1582 DP_NOTICE(p_hwfn, false,
1583 "Not acknowledging the notification to allow the MFW crash dump\n");
1587 ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1588 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1591 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1592 struct ecore_ptt *p_ptt)
1594 struct ecore_mcp_info *info = p_hwfn->mcp_info;
1595 enum _ecore_status_t rc = ECORE_SUCCESS;
1599 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1601 /* Read Messages from MFW */
1602 ecore_mcp_read_mb(p_hwfn, p_ptt);
1604 /* Compare current messages to old ones */
1605 for (i = 0; i < info->mfw_mb_length; i++) {
1606 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1611 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1612 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1613 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1616 case MFW_DRV_MSG_LINK_CHANGE:
1617 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1619 case MFW_DRV_MSG_VF_DISABLED:
1620 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1622 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1623 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1624 ECORE_DCBX_REMOTE_LLDP_MIB);
1626 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1627 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1628 ECORE_DCBX_REMOTE_MIB);
1630 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1631 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1632 ECORE_DCBX_OPERATIONAL_MIB);
1634 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1635 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1637 case MFW_DRV_MSG_ERROR_RECOVERY:
1638 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1640 case MFW_DRV_MSG_GET_LAN_STATS:
1641 case MFW_DRV_MSG_GET_FCOE_STATS:
1642 case MFW_DRV_MSG_GET_ISCSI_STATS:
1643 case MFW_DRV_MSG_GET_RDMA_STATS:
1644 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1646 case MFW_DRV_MSG_BW_UPDATE:
1647 ecore_mcp_update_bw(p_hwfn, p_ptt);
1649 case MFW_DRV_MSG_FAILURE_DETECTED:
1650 ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1652 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1653 ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1656 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1661 /* ACK everything */
1662 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1663 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1665 /* MFW expect answer in BE, so we force write in that format */
1666 ecore_wr(p_hwfn, p_ptt,
1667 info->mfw_mb_addr + sizeof(u32) +
1668 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1669 sizeof(u32) + i * sizeof(u32), val);
1673 DP_NOTICE(p_hwfn, false,
1674 "Received an MFW message indication but no"
1679 /* Copy the new mfw messages into the shadow */
1680 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1685 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1686 struct ecore_ptt *p_ptt,
1688 u32 *p_running_bundle_id)
1693 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1694 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1695 return ECORE_SUCCESS;
1699 if (IS_VF(p_hwfn->p_dev)) {
1700 if (p_hwfn->vf_iov_info) {
1701 struct pfvf_acquire_resp_tlv *p_resp;
1703 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1704 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1705 return ECORE_SUCCESS;
1707 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1708 "VF requested MFW version prior to ACQUIRE\n");
1713 global_offsize = ecore_rd(p_hwfn, p_ptt,
1714 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1718 ecore_rd(p_hwfn, p_ptt,
1719 SECTION_ADDR(global_offsize,
1720 0) + OFFSETOF(struct public_global, mfw_ver));
1722 if (p_running_bundle_id != OSAL_NULL) {
1723 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1724 SECTION_ADDR(global_offsize,
1726 OFFSETOF(struct public_global,
1727 running_bundle_id));
1730 return ECORE_SUCCESS;
1733 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1736 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1737 struct ecore_ptt *p_ptt;
1739 /* TODO - Add support for VFs */
1743 if (!ecore_mcp_is_init(p_hwfn)) {
1744 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1748 *p_media_type = MEDIA_UNSPECIFIED;
1750 p_ptt = ecore_ptt_acquire(p_hwfn);
1754 *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1755 OFFSETOF(struct public_port, media_type));
1757 ecore_ptt_release(p_hwfn, p_ptt);
1759 return ECORE_SUCCESS;
1763 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1765 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
1766 enum ecore_pci_personality *p_proto)
1768 *p_proto = ECORE_PCI_ETH;
1770 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1771 "According to Legacy capabilities, L2 personality is %08x\n",
1776 static enum _ecore_status_t
1777 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
1778 struct ecore_ptt *p_ptt,
1779 enum ecore_pci_personality *p_proto)
1781 u32 resp = 0, param = 0;
1782 enum _ecore_status_t rc;
1784 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1785 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1786 (u32)*p_proto, resp, param);
1787 return ECORE_SUCCESS;
1790 static enum _ecore_status_t
1791 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1792 struct public_func *p_info,
1793 struct ecore_ptt *p_ptt,
1794 enum ecore_pci_personality *p_proto)
1796 enum _ecore_status_t rc = ECORE_SUCCESS;
1798 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1799 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1800 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
1802 ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1811 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1812 struct ecore_ptt *p_ptt)
1814 struct ecore_mcp_function_info *info;
1815 struct public_func shmem_info;
1817 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1818 info = &p_hwfn->mcp_info->func_info;
1820 info->pause_on_host = (shmem_info.config &
1821 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1823 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1825 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1826 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1830 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1832 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1833 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1834 info->mac[1] = (u8)(shmem_info.mac_upper);
1835 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1836 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1837 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1838 info->mac[5] = (u8)(shmem_info.mac_lower);
1840 /* TODO - are there protocols for which there's no MAC? */
1841 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1844 /* TODO - are these calculations true for BE machine? */
1845 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1846 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1847 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1848 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1850 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1852 info->mtu = (u16)shmem_info.mtu_size;
1857 info->mtu = (u16)shmem_info.mtu_size;
1859 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1860 "Read configuration from shmem: pause_on_host %02x"
1861 " protocol %02x BW [%02x - %02x]"
1862 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1863 " node %lx ovlan %04x\n",
1864 info->pause_on_host, info->protocol,
1865 info->bandwidth_min, info->bandwidth_max,
1866 info->mac[0], info->mac[1], info->mac[2],
1867 info->mac[3], info->mac[4], info->mac[5],
1868 (unsigned long)info->wwn_port,
1869 (unsigned long)info->wwn_node, info->ovlan);
1871 return ECORE_SUCCESS;
1874 struct ecore_mcp_link_params
1875 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1877 if (!p_hwfn || !p_hwfn->mcp_info)
1879 return &p_hwfn->mcp_info->link_input;
1882 struct ecore_mcp_link_state
1883 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1885 if (!p_hwfn || !p_hwfn->mcp_info)
1889 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1890 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1891 p_hwfn->mcp_info->link_output.link_up = true;
1895 return &p_hwfn->mcp_info->link_output;
1898 struct ecore_mcp_link_capabilities
1899 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1901 if (!p_hwfn || !p_hwfn->mcp_info)
1903 return &p_hwfn->mcp_info->link_capabilities;
1906 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1907 struct ecore_ptt *p_ptt)
1909 u32 resp = 0, param = 0;
1910 enum _ecore_status_t rc;
1912 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1913 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
1915 /* Wait for the drain to complete before returning */
1921 const struct ecore_mcp_function_info
1922 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1924 if (!p_hwfn || !p_hwfn->mcp_info)
1926 return &p_hwfn->mcp_info->func_info;
1929 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1930 struct ecore_ptt *p_ptt,
1931 struct ecore_mcp_nvm_params *params)
1933 enum _ecore_status_t rc;
1935 switch (params->type) {
1936 case ECORE_MCP_NVM_RD:
1937 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1938 params->nvm_common.offset,
1939 ¶ms->nvm_common.resp,
1940 ¶ms->nvm_common.param,
1941 params->nvm_rd.buf_size,
1942 params->nvm_rd.buf);
1945 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1946 params->nvm_common.offset,
1947 ¶ms->nvm_common.resp,
1948 ¶ms->nvm_common.param);
1950 case ECORE_MCP_NVM_WR:
1951 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1952 params->nvm_common.offset,
1953 ¶ms->nvm_common.resp,
1954 ¶ms->nvm_common.param,
1955 params->nvm_wr.buf_size,
1956 params->nvm_wr.buf);
1965 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1966 struct ecore_ptt *p_ptt, u32 personalities)
1968 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1969 struct public_func shmem_info;
1970 int i, count = 0, num_pfs;
1972 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1974 for (i = 0; i < num_pfs; i++) {
1975 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1976 MCP_PF_ID_BY_REL(p_hwfn, i));
1977 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1980 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1985 if ((1 << ((u32)protocol)) & personalities)
1992 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1993 struct ecore_ptt *p_ptt,
1999 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2000 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2005 if (IS_VF(p_hwfn->p_dev))
2008 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2009 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2010 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2011 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2013 *p_flash_size = flash_size;
2015 return ECORE_SUCCESS;
2018 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2019 struct ecore_ptt *p_ptt)
2021 struct ecore_dev *p_dev = p_hwfn->p_dev;
2023 if (p_dev->recov_in_prog) {
2024 DP_NOTICE(p_hwfn, false,
2025 "Avoid triggering a recovery since such a process"
2026 " is already in progress\n");
2030 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2031 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2033 return ECORE_SUCCESS;
2036 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2037 struct ecore_ptt *p_ptt,
2040 u32 resp = 0, param = 0, rc_param = 0;
2041 enum _ecore_status_t rc;
2043 /* Only Leader can configure MSIX, and need to take CMT into account */
2045 if (!IS_LEAD_HWFN(p_hwfn))
2046 return ECORE_SUCCESS;
2047 num *= p_hwfn->p_dev->num_hwfns;
2049 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2050 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2051 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2052 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2054 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2057 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2058 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2062 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2063 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2070 enum _ecore_status_t
2071 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2072 struct ecore_mcp_drv_version *p_ver)
2074 struct ecore_mcp_mb_params mb_params;
2075 struct drv_version_stc drv_version;
2079 enum _ecore_status_t rc;
2082 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2083 return ECORE_SUCCESS;
2086 OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2087 drv_version.version = p_ver->version;
2088 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2089 for (i = 0; i < num_words; i++) {
2090 /* The driver name is expected to be in a big-endian format */
2091 p_name = &p_ver->name[i * sizeof(u32)];
2092 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2093 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2096 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2097 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2098 mb_params.p_data_src = &drv_version;
2099 mb_params.data_src_size = sizeof(drv_version);
2100 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2101 if (rc != ECORE_SUCCESS)
2102 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2107 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2108 struct ecore_ptt *p_ptt)
2110 enum _ecore_status_t rc;
2111 u32 resp = 0, param = 0;
2113 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2115 if (rc != ECORE_SUCCESS)
2116 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2121 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2122 struct ecore_ptt *p_ptt)
2124 u32 value, cpu_mode;
2126 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2128 value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2129 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2130 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2131 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2133 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
2136 enum _ecore_status_t
2137 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2138 struct ecore_ptt *p_ptt,
2139 enum ecore_ov_client client)
2141 enum _ecore_status_t rc;
2142 u32 resp = 0, param = 0;
2146 case ECORE_OV_CLIENT_DRV:
2147 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2149 case ECORE_OV_CLIENT_USER:
2150 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2152 case ECORE_OV_CLIENT_VENDOR_SPEC:
2153 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2156 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2160 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2161 drv_mb_param, &resp, ¶m);
2162 if (rc != ECORE_SUCCESS)
2163 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2168 enum _ecore_status_t
2169 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2170 struct ecore_ptt *p_ptt,
2171 enum ecore_ov_driver_state drv_state)
2173 enum _ecore_status_t rc;
2174 u32 resp = 0, param = 0;
2177 switch (drv_state) {
2178 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2179 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2181 case ECORE_OV_DRIVER_STATE_DISABLED:
2182 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2184 case ECORE_OV_DRIVER_STATE_ACTIVE:
2185 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2188 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2192 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2193 drv_mb_param, &resp, ¶m);
2194 if (rc != ECORE_SUCCESS)
2195 DP_ERR(p_hwfn, "Failed to send driver state\n");
2200 enum _ecore_status_t
2201 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2202 struct ecore_fc_npiv_tbl *p_table)
2207 enum _ecore_status_t
2208 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2209 struct ecore_ptt *p_ptt, u16 mtu)
2214 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2215 struct ecore_ptt *p_ptt,
2216 enum ecore_led_mode mode)
2218 u32 resp = 0, param = 0, drv_mb_param;
2219 enum _ecore_status_t rc;
2222 case ECORE_LED_MODE_ON:
2223 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2225 case ECORE_LED_MODE_OFF:
2226 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2228 case ECORE_LED_MODE_RESTORE:
2229 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2232 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2236 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2237 drv_mb_param, &resp, ¶m);
2238 if (rc != ECORE_SUCCESS)
2239 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2244 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2245 struct ecore_ptt *p_ptt,
2248 enum _ecore_status_t rc;
2249 u32 resp = 0, param = 0;
2251 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2252 mask_parities, &resp, ¶m);
2254 if (rc != ECORE_SUCCESS) {
2256 "MCP response failure for mask parities, aborting\n");
2257 } else if (resp != FW_MSG_CODE_OK) {
2259 "MCP did not ack mask parity request. Old MFW?\n");
2266 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2269 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2270 u32 bytes_left, offset, bytes_to_copy, buf_size;
2271 struct ecore_mcp_nvm_params params;
2272 struct ecore_ptt *p_ptt;
2273 enum _ecore_status_t rc = ECORE_SUCCESS;
2275 p_ptt = ecore_ptt_acquire(p_hwfn);
2279 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2282 params.type = ECORE_MCP_NVM_RD;
2283 params.nvm_rd.buf_size = &buf_size;
2284 params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
2285 while (bytes_left > 0) {
2286 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2287 MCP_DRV_NVM_BUF_LEN);
2288 params.nvm_common.offset = (addr + offset) |
2289 (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
2290 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2291 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2292 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
2293 FW_MSG_CODE_NVM_OK)) {
2294 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2298 /* This can be a lengthy process, and it's possible scheduler
2299 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2301 if (bytes_left % 0x1000 <
2302 (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
2305 offset += *params.nvm_rd.buf_size;
2306 bytes_left -= *params.nvm_rd.buf_size;
2309 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2310 ecore_ptt_release(p_hwfn, p_ptt);
2315 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2316 u32 addr, u8 *p_buf, u32 len)
2318 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2319 struct ecore_mcp_nvm_params params;
2320 struct ecore_ptt *p_ptt;
2321 enum _ecore_status_t rc;
2323 p_ptt = ecore_ptt_acquire(p_hwfn);
2327 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2328 params.type = ECORE_MCP_NVM_RD;
2329 params.nvm_rd.buf_size = &len;
2330 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
2331 DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
2332 params.nvm_common.offset = addr;
2333 params.nvm_rd.buf = (u32 *)p_buf;
2334 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2335 if (rc != ECORE_SUCCESS)
2336 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2338 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2339 ecore_ptt_release(p_hwfn, p_ptt);
2344 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2346 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2347 struct ecore_mcp_nvm_params params;
2348 struct ecore_ptt *p_ptt;
2350 p_ptt = ecore_ptt_acquire(p_hwfn);
2354 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2355 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2356 ecore_ptt_release(p_hwfn, p_ptt);
2358 return ECORE_SUCCESS;
2361 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2363 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2364 struct ecore_mcp_nvm_params params;
2365 struct ecore_ptt *p_ptt;
2366 enum _ecore_status_t rc;
2368 p_ptt = ecore_ptt_acquire(p_hwfn);
2371 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2372 params.type = ECORE_MCP_CMD;
2373 params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
2374 params.nvm_common.offset = addr;
2375 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2376 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2377 ecore_ptt_release(p_hwfn, p_ptt);
2382 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2385 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2386 struct ecore_mcp_nvm_params params;
2387 struct ecore_ptt *p_ptt;
2388 enum _ecore_status_t rc;
2390 p_ptt = ecore_ptt_acquire(p_hwfn);
2393 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2394 params.type = ECORE_MCP_CMD;
2395 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
2396 params.nvm_common.offset = addr;
2397 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2398 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2399 ecore_ptt_release(p_hwfn, p_ptt);
2404 /* rc receives ECORE_INVAL as default parameter because
2405 * it might not enter the while loop if the len is 0
2407 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2408 u32 addr, u8 *p_buf, u32 len)
2410 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2411 enum _ecore_status_t rc = ECORE_INVAL;
2412 struct ecore_mcp_nvm_params params;
2413 struct ecore_ptt *p_ptt;
2414 u32 buf_idx, buf_size;
2416 p_ptt = ecore_ptt_acquire(p_hwfn);
2420 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2421 params.type = ECORE_MCP_NVM_WR;
2422 if (cmd == ECORE_PUT_FILE_DATA)
2423 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2425 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2427 while (buf_idx < len) {
2428 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2429 MCP_DRV_NVM_BUF_LEN);
2430 params.nvm_common.offset = ((buf_size <<
2431 DRV_MB_PARAM_NVM_LEN_SHIFT)
2433 params.nvm_wr.buf_size = buf_size;
2434 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2435 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2436 if (rc != ECORE_SUCCESS ||
2437 ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2438 (params.nvm_common.resp !=
2439 FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2440 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2442 /* This can be a lengthy process, and it's possible scheduler
2443 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2445 if (buf_idx % 0x1000 >
2446 (buf_idx + buf_size) % 0x1000)
2449 buf_idx += buf_size;
2452 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2453 ecore_ptt_release(p_hwfn, p_ptt);
2458 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2459 u32 addr, u8 *p_buf, u32 len)
2461 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2462 struct ecore_mcp_nvm_params params;
2463 struct ecore_ptt *p_ptt;
2464 enum _ecore_status_t rc;
2466 p_ptt = ecore_ptt_acquire(p_hwfn);
2470 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2471 params.type = ECORE_MCP_NVM_WR;
2472 params.nvm_wr.buf_size = len;
2473 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2474 DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2475 params.nvm_common.offset = addr;
2476 params.nvm_wr.buf = (u32 *)p_buf;
2477 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2478 if (rc != ECORE_SUCCESS)
2479 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2480 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2481 ecore_ptt_release(p_hwfn, p_ptt);
2486 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2489 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2490 struct ecore_mcp_nvm_params params;
2491 struct ecore_ptt *p_ptt;
2492 enum _ecore_status_t rc;
2494 p_ptt = ecore_ptt_acquire(p_hwfn);
2498 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2499 params.type = ECORE_MCP_CMD;
2500 params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2501 params.nvm_common.offset = addr;
2502 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2503 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2504 ecore_ptt_release(p_hwfn, p_ptt);
2509 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2510 struct ecore_ptt *p_ptt,
2511 u32 port, u32 addr, u32 offset,
2514 struct ecore_mcp_nvm_params params;
2515 enum _ecore_status_t rc;
2516 u32 bytes_left, bytes_to_copy, buf_size;
2518 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2519 params.nvm_common.offset =
2520 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2521 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2525 params.type = ECORE_MCP_NVM_RD;
2526 params.nvm_rd.buf_size = &buf_size;
2527 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2528 while (bytes_left > 0) {
2529 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2530 MAX_I2C_TRANSACTION_SIZE);
2531 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2532 params.nvm_common.offset &=
2533 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2534 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2535 params.nvm_common.offset |=
2537 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2538 params.nvm_common.offset |=
2539 (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2540 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2541 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2542 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2544 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2545 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2546 return ECORE_UNKNOWN_ERROR;
2548 offset += *params.nvm_rd.buf_size;
2549 bytes_left -= *params.nvm_rd.buf_size;
2552 return ECORE_SUCCESS;
2555 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2556 struct ecore_ptt *p_ptt,
2557 u32 port, u32 addr, u32 offset,
2560 struct ecore_mcp_nvm_params params;
2561 enum _ecore_status_t rc;
2562 u32 buf_idx, buf_size;
2564 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2565 params.nvm_common.offset =
2566 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2567 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2568 params.type = ECORE_MCP_NVM_WR;
2569 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2571 while (buf_idx < len) {
2572 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2573 MAX_I2C_TRANSACTION_SIZE);
2574 params.nvm_common.offset &=
2575 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2576 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2577 params.nvm_common.offset |=
2578 ((offset + buf_idx) <<
2579 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2580 params.nvm_common.offset |=
2581 (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2582 params.nvm_wr.buf_size = buf_size;
2583 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2584 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2585 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2586 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2588 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2589 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2590 return ECORE_UNKNOWN_ERROR;
2592 buf_idx += buf_size;
2595 return ECORE_SUCCESS;
2598 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2599 struct ecore_ptt *p_ptt,
2600 u16 gpio, u32 *gpio_val)
2602 enum _ecore_status_t rc = ECORE_SUCCESS;
2603 u32 drv_mb_param = 0, rsp;
2605 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2607 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2608 drv_mb_param, &rsp, gpio_val);
2610 if (rc != ECORE_SUCCESS)
2613 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2614 return ECORE_UNKNOWN_ERROR;
2616 return ECORE_SUCCESS;
2619 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2620 struct ecore_ptt *p_ptt,
2621 u16 gpio, u16 gpio_val)
2623 enum _ecore_status_t rc = ECORE_SUCCESS;
2624 u32 drv_mb_param = 0, param, rsp;
2626 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2627 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2629 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2630 drv_mb_param, &rsp, ¶m);
2632 if (rc != ECORE_SUCCESS)
2635 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2636 return ECORE_UNKNOWN_ERROR;
2638 return ECORE_SUCCESS;
2641 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2642 struct ecore_ptt *p_ptt,
2643 u16 gpio, u32 *gpio_direction,
2646 u32 drv_mb_param = 0, rsp, val = 0;
2647 enum _ecore_status_t rc = ECORE_SUCCESS;
2649 drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2651 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2652 drv_mb_param, &rsp, &val);
2653 if (rc != ECORE_SUCCESS)
2656 *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2657 DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2658 *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2659 DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2661 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2662 return ECORE_UNKNOWN_ERROR;
2664 return ECORE_SUCCESS;
2667 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2668 struct ecore_ptt *p_ptt)
2670 u32 drv_mb_param = 0, rsp, param;
2671 enum _ecore_status_t rc = ECORE_SUCCESS;
2673 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2674 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2676 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2677 drv_mb_param, &rsp, ¶m);
2679 if (rc != ECORE_SUCCESS)
2682 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2683 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2684 rc = ECORE_UNKNOWN_ERROR;
2689 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2690 struct ecore_ptt *p_ptt)
2692 u32 drv_mb_param, rsp, param;
2693 enum _ecore_status_t rc = ECORE_SUCCESS;
2695 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2696 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2698 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2699 drv_mb_param, &rsp, ¶m);
2701 if (rc != ECORE_SUCCESS)
2704 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2705 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2706 rc = ECORE_UNKNOWN_ERROR;
2711 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2712 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2714 u32 drv_mb_param = 0, rsp;
2715 enum _ecore_status_t rc = ECORE_SUCCESS;
2717 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2718 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2720 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2721 drv_mb_param, &rsp, num_images);
2723 if (rc != ECORE_SUCCESS)
2726 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2727 rc = ECORE_UNKNOWN_ERROR;
2732 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2733 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2734 struct bist_nvm_image_att *p_image_att, u32 image_index)
2736 struct ecore_mcp_nvm_params params;
2737 enum _ecore_status_t rc;
2740 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2741 params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2742 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2743 params.nvm_common.offset |= (image_index <<
2744 DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2746 params.type = ECORE_MCP_NVM_RD;
2747 params.nvm_rd.buf_size = &buf_size;
2748 params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2749 params.nvm_rd.buf = (u32 *)p_image_att;
2751 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2752 if (rc != ECORE_SUCCESS)
2755 if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2756 (p_image_att->return_code != 1))
2757 rc = ECORE_UNKNOWN_ERROR;
2762 enum _ecore_status_t
2763 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2764 struct ecore_ptt *p_ptt,
2765 struct ecore_temperature_info *p_temp_info)
2767 struct ecore_temperature_sensor *p_temp_sensor;
2768 struct temperature_status_stc mfw_temp_info;
2769 struct ecore_mcp_mb_params mb_params;
2771 enum _ecore_status_t rc;
2774 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2775 mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2776 mb_params.p_data_dst = &mfw_temp_info;
2777 mb_params.data_dst_size = sizeof(mfw_temp_info);
2778 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2779 if (rc != ECORE_SUCCESS)
2782 OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2783 p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
2784 ECORE_MAX_NUM_OF_SENSORS);
2785 for (i = 0; i < p_temp_info->num_sensors; i++) {
2786 val = mfw_temp_info.sensor[i];
2787 p_temp_sensor = &p_temp_info->sensors[i];
2788 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2789 SENSOR_LOCATION_SHIFT;
2790 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2791 THRESHOLD_HIGH_SHIFT;
2792 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2793 CRITICAL_TEMPERATURE_SHIFT;
2794 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2798 return ECORE_SUCCESS;
2801 enum _ecore_status_t ecore_mcp_get_mba_versions(
2802 struct ecore_hwfn *p_hwfn,
2803 struct ecore_ptt *p_ptt,
2804 struct ecore_mba_vers *p_mba_vers)
2806 struct ecore_mcp_nvm_params params;
2807 enum _ecore_status_t rc;
2810 OSAL_MEM_ZERO(¶ms, sizeof(params));
2811 params.type = ECORE_MCP_NVM_RD;
2812 params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2813 params.nvm_common.offset = 0;
2814 params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2815 params.nvm_rd.buf_size = &buf_size;
2816 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2818 if (rc != ECORE_SUCCESS)
2821 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2823 rc = ECORE_UNKNOWN_ERROR;
2825 if (buf_size != MCP_DRV_NVM_BUF_LEN)
2826 rc = ECORE_UNKNOWN_ERROR;
2831 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2832 struct ecore_ptt *p_ptt,
2837 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2838 0, &rsp, (u32 *)num_events);
2841 static enum resource_id_enum
2842 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
2844 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2848 mfw_res_id = RESOURCE_NUM_SB_E;
2850 case ECORE_L2_QUEUE:
2851 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2854 mfw_res_id = RESOURCE_NUM_VPORT_E;
2857 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2860 mfw_res_id = RESOURCE_NUM_PQ_E;
2863 mfw_res_id = RESOURCE_NUM_RL_E;
2867 /* Each VFC resource can accommodate both a MAC and a VLAN */
2868 mfw_res_id = RESOURCE_VFC_FILTER_E;
2871 mfw_res_id = RESOURCE_ILT_E;
2873 case ECORE_LL2_QUEUE:
2874 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2876 case ECORE_RDMA_CNQ_RAM:
2877 case ECORE_CMDQS_CQS:
2878 /* CNQ/CMDQS are the same resource */
2879 mfw_res_id = RESOURCE_CQS_E;
2881 case ECORE_RDMA_STATS_QUEUE:
2882 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2885 mfw_res_id = RESOURCE_BDQ_E;
2894 #define ECORE_RESC_ALLOC_VERSION_MAJOR 2
2895 #define ECORE_RESC_ALLOC_VERSION_MINOR 0
2896 #define ECORE_RESC_ALLOC_VERSION \
2897 ((ECORE_RESC_ALLOC_VERSION_MAJOR << \
2898 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2899 (ECORE_RESC_ALLOC_VERSION_MINOR << \
2900 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2902 struct ecore_resc_alloc_in_params {
2904 enum ecore_resources res_id;
2908 struct ecore_resc_alloc_out_params {
2918 #define ECORE_RECOVERY_PROLOG_SLEEP_MS 100
2920 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
2922 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2923 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2924 enum _ecore_status_t rc;
2926 /* Allow ongoing PCIe transactions to complete */
2927 OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
2929 /* Clear the PF's internal FID_enable in the PXP */
2930 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
2931 if (rc != ECORE_SUCCESS)
2932 DP_NOTICE(p_hwfn, false,
2933 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2939 static enum _ecore_status_t
2940 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
2941 struct ecore_ptt *p_ptt,
2942 struct ecore_resc_alloc_in_params *p_in_params,
2943 struct ecore_resc_alloc_out_params *p_out_params)
2945 struct ecore_mcp_mb_params mb_params;
2946 struct resource_info mfw_resc_info;
2947 enum _ecore_status_t rc;
2949 OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
2951 mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
2952 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
2954 "Failed to match resource %d [%s] with the MFW resources\n",
2955 p_in_params->res_id,
2956 ecore_hw_get_resc_name(p_in_params->res_id));
2960 switch (p_in_params->cmd) {
2961 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
2962 mfw_resc_info.size = p_in_params->resc_max_val;
2964 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
2967 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
2972 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2973 mb_params.cmd = p_in_params->cmd;
2974 mb_params.param = ECORE_RESC_ALLOC_VERSION;
2975 mb_params.p_data_src = &mfw_resc_info;
2976 mb_params.data_src_size = sizeof(mfw_resc_info);
2977 mb_params.p_data_dst = mb_params.p_data_src;
2978 mb_params.data_dst_size = mb_params.data_src_size;
2980 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2981 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
2982 p_in_params->cmd, p_in_params->res_id,
2983 ecore_hw_get_resc_name(p_in_params->res_id),
2984 ECORE_MFW_GET_FIELD(mb_params.param,
2985 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2986 ECORE_MFW_GET_FIELD(mb_params.param,
2987 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2988 p_in_params->resc_max_val);
2990 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2991 if (rc != ECORE_SUCCESS)
2994 p_out_params->mcp_resp = mb_params.mcp_resp;
2995 p_out_params->mcp_param = mb_params.mcp_param;
2996 p_out_params->resc_num = mfw_resc_info.size;
2997 p_out_params->resc_start = mfw_resc_info.offset;
2998 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
2999 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3000 p_out_params->flags = mfw_resc_info.flags;
3002 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3003 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3004 ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3005 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3006 ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3007 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3008 p_out_params->resc_num, p_out_params->resc_start,
3009 p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3010 p_out_params->flags);
3012 return ECORE_SUCCESS;
3015 enum _ecore_status_t
3016 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3017 enum ecore_resources res_id, u32 resc_max_val,
3020 struct ecore_resc_alloc_out_params out_params;
3021 struct ecore_resc_alloc_in_params in_params;
3022 enum _ecore_status_t rc;
3024 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3025 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3026 in_params.res_id = res_id;
3027 in_params.resc_max_val = resc_max_val;
3028 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3029 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3031 if (rc != ECORE_SUCCESS)
3034 *p_mcp_resp = out_params.mcp_resp;
3036 return ECORE_SUCCESS;
3039 enum _ecore_status_t
3040 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3041 enum ecore_resources res_id, u32 *p_mcp_resp,
3042 u32 *p_resc_num, u32 *p_resc_start)
3044 struct ecore_resc_alloc_out_params out_params;
3045 struct ecore_resc_alloc_in_params in_params;
3046 enum _ecore_status_t rc;
3048 OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3049 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3050 in_params.res_id = res_id;
3051 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3052 rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3054 if (rc != ECORE_SUCCESS)
3057 *p_mcp_resp = out_params.mcp_resp;
3059 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3060 *p_resc_num = out_params.resc_num;
3061 *p_resc_start = out_params.resc_start;
3064 return ECORE_SUCCESS;
3067 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3068 struct ecore_ptt *p_ptt)
3070 u32 mcp_resp, mcp_param;
3072 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3073 &mcp_resp, &mcp_param);
3076 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3077 struct ecore_ptt *p_ptt,
3078 u32 param, u32 *p_mcp_resp,
3081 enum _ecore_status_t rc;
3083 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3084 p_mcp_resp, p_mcp_param);
3085 if (rc != ECORE_SUCCESS)
3088 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3090 "The resource command is unsupported by the MFW\n");
3091 return ECORE_NOTIMPL;
3094 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3095 u8 opcode = ECORE_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3097 DP_NOTICE(p_hwfn, false,
3098 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3106 enum _ecore_status_t
3107 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3108 struct ecore_resc_lock_params *p_params)
3110 u32 param = 0, mcp_resp, mcp_param;
3112 enum _ecore_status_t rc;
3114 switch (p_params->timeout) {
3115 case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3116 opcode = RESOURCE_OPCODE_REQ;
3117 p_params->timeout = 0;
3119 case ECORE_MCP_RESC_LOCK_TO_NONE:
3120 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3121 p_params->timeout = 0;
3124 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3128 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3129 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3130 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3132 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3133 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3134 param, p_params->timeout, opcode, p_params->resource);
3136 /* Attempt to acquire the resource */
3137 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3139 if (rc != ECORE_SUCCESS)
3142 /* Analyze the response */
3143 p_params->owner = ECORE_MFW_GET_FIELD(mcp_param,
3144 RESOURCE_CMD_RSP_OWNER);
3145 opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3147 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3148 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3149 mcp_param, opcode, p_params->owner);
3152 case RESOURCE_OPCODE_GNT:
3153 p_params->b_granted = true;
3155 case RESOURCE_OPCODE_BUSY:
3156 p_params->b_granted = false;
3159 DP_NOTICE(p_hwfn, false,
3160 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3165 return ECORE_SUCCESS;
3168 enum _ecore_status_t
3169 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3170 struct ecore_resc_lock_params *p_params)
3173 enum _ecore_status_t rc;
3176 /* No need for an interval before the first iteration */
3178 if (p_params->sleep_b4_retry) {
3179 u16 retry_interval_in_ms =
3180 DIV_ROUND_UP(p_params->retry_interval,
3183 OSAL_MSLEEP(retry_interval_in_ms);
3185 OSAL_UDELAY(p_params->retry_interval);
3189 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3190 if (rc != ECORE_SUCCESS)
3193 if (p_params->b_granted)
3195 } while (retry_cnt++ < p_params->retry_num);
3197 return ECORE_SUCCESS;
3200 enum _ecore_status_t
3201 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3202 struct ecore_resc_unlock_params *p_params)
3204 u32 param = 0, mcp_resp, mcp_param;
3206 enum _ecore_status_t rc;
3208 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3209 : RESOURCE_OPCODE_RELEASE;
3210 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3211 ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3213 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3214 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3215 param, opcode, p_params->resource);
3217 /* Attempt to release the resource */
3218 rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3220 if (rc != ECORE_SUCCESS)
3223 /* Analyze the response */
3224 opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3226 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3227 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3231 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3233 "Resource unlock request for an already released resource [%d]\n",
3234 p_params->resource);
3236 case RESOURCE_OPCODE_RELEASED:
3237 p_params->b_released = true;
3239 case RESOURCE_OPCODE_WRONG_OWNER:
3240 p_params->b_released = false;
3243 DP_NOTICE(p_hwfn, false,
3244 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3249 return ECORE_SUCCESS;
3252 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3254 return !!(p_hwfn->mcp_info->capabilities &
3255 FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3258 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3259 struct ecore_ptt *p_ptt)
3262 enum _ecore_status_t rc;
3264 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3265 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3266 if (rc == ECORE_SUCCESS)
3267 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3268 "MFW supported features: %08x\n",
3269 p_hwfn->mcp_info->capabilities);
3274 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3275 struct ecore_ptt *p_ptt)
3277 u32 mcp_resp, mcp_param, features;
3279 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ;
3281 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3282 features, &mcp_resp, &mcp_param);