drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23
  24 #define CHIP_MCP_RESP_ITER_US 10
  25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  26
  27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  28 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  29
  30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  31         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  32                  _val)
  33
  34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  35         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  36
  37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  38         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  39                      OFFSETOF(struct public_drv_mb, _field), _val)
  40
  41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  42         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  43                      OFFSETOF(struct public_drv_mb, _field))
  44
  45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  46         DRV_ID_PDA_COMP_VER_SHIFT)
  47
  48 #define MCP_BYTES_PER_MBIT_SHIFT 17
  49
  50 #ifndef ASIC_ONLY
  51 static int loaded;
  52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  53 #endif
  54
  55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  56 {
  57         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  58                 return false;
  59         return true;
  60 }
  61
  62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  63 {
  64         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  65                                         PUBLIC_PORT);
  66         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  67
  68         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  69                                                    MFW_PORT(p_hwfn));
  70         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  71                    "port_addr = 0x%x, port_id 0x%02x\n",
  72                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  73 }
  74
  75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  76 {
  77         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  78         OSAL_BE32 tmp;
  79         u32 i;
  80
  81 #ifndef ASIC_ONLY
  82         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  83                 return;
  84 #endif
  85
  86         if (!p_hwfn->mcp_info->public_base)
  87                 return;
  88
  89         for (i = 0; i < length; i++) {
  90                 tmp = ecore_rd(p_hwfn, p_ptt,
  91                                p_hwfn->mcp_info->mfw_mb_addr +
  92                                (i << 2) + sizeof(u32));
  93
  94                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  95                     OSAL_BE32_TO_CPU(tmp);
  96         }
  97 }
  98
  99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 100 {
 101         if (p_hwfn->mcp_info) {
 102                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 103                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 104                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
 105         }
 106         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 107
 108         return ECORE_SUCCESS;
 109 }
 110
 111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 112                                                    struct ecore_ptt *p_ptt)
 113 {
 114         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 115         u32 drv_mb_offsize, mfw_mb_offsize;
 116         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 117
 118 #ifndef ASIC_ONLY
 119         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 120                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 121                 p_info->public_base = 0;
 122                 return ECORE_INVAL;
 123         }
 124 #endif
 125
 126         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 127         if (!p_info->public_base)
 128                 return ECORE_INVAL;
 129
 130         p_info->public_base |= GRCBASE_MCP;
 131
 132         /* Calculate the driver and MFW mailbox address */
 133         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 134                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 135                                                        PUBLIC_DRV_MB));
 136         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 137         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 138                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 139                    " mcp_pf_id = 0x%x\n",
 140                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 141
 142         /* Set the MFW MB address */
 143         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 144                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 145                                                        PUBLIC_MFW_MB));
 146         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 147         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 148                                                p_info->mfw_mb_addr);
 149
 150         /* Get the current driver mailbox sequence before sending
 151          * the first command
 152          */
 153         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 154             DRV_MSG_SEQ_NUMBER_MASK;
 155
 156         /* Get current FW pulse sequence */
 157         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 158             DRV_PULSE_SEQ_MASK;
 159
 160         p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
 161                                           MISCS_REG_GENERIC_POR_0);
 162
 163         return ECORE_SUCCESS;
 164 }
 165
 166 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 167                                         struct ecore_ptt *p_ptt)
 168 {
 169         struct ecore_mcp_info *p_info;
 170         u32 size;
 171
 172         /* Allocate mcp_info structure */
 173         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 174                                        sizeof(*p_hwfn->mcp_info));
 175         if (!p_hwfn->mcp_info)
 176                 goto err;
 177         p_info = p_hwfn->mcp_info;
 178
 179         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 180                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 181                 /* Do not free mcp_info here, since public_base indicate that
 182                  * the MCP is not initialized
 183                  */
 184                 return ECORE_SUCCESS;
 185         }
 186
 187         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 188         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 189         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 190         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 191                 goto err;
 192
 193         /* Initialize the MFW spinlock */
 194         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
 195         OSAL_SPIN_LOCK_INIT(&p_info->lock);
 196
 197         return ECORE_SUCCESS;
 198
 199 err:
 200         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 201         ecore_mcp_free(p_hwfn);
 202         return ECORE_NOMEM;
 203 }
 204
 205 /* Locks the MFW mailbox of a PF to ensure a single access.
 206  * The lock is achieved in most cases by holding a spinlock, causing other
 207  * threads to wait till a previous access is done.
 208  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 209  * access is achieved by setting a blocking flag, which will fail other
 210  * competing contexts to send their mailboxes.
 211  */
 212 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
 213                                               u32 cmd)
 214 {
 215         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
 216
 217         /* The spinlock shouldn't be acquired when the mailbox command is
 218          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 219          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 220          * (i.e. interrupts are disabled) - can lead to a deadlock.
 221          * It is assumed that for a single PF, no other mailbox commands can be
 222          * sent from another context while sending LOAD_REQ, and that any
 223          * parallel commands to UNLOAD_REQ can be cancelled.
 224          */
 225         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 226                 p_hwfn->mcp_info->block_mb_sending = false;
 227
 228         if (p_hwfn->mcp_info->block_mb_sending) {
 229                 DP_NOTICE(p_hwfn, false,
 230                           "Trying to send a MFW mailbox command [0x%x]"
 231                           " in parallel to [UN]LOAD_REQ. Aborting.\n",
 232                           cmd);
 233                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 234                 return ECORE_BUSY;
 235         }
 236
 237         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 238                 p_hwfn->mcp_info->block_mb_sending = true;
 239                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 240         }
 241
 242         return ECORE_SUCCESS;
 243 }
 244
 245 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
 246 {
 247         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 248                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 249 }
 250
 251 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 252                                      struct ecore_ptt *p_ptt)
 253 {
 254         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 255         u32 delay = CHIP_MCP_RESP_ITER_US;
 256         u32 org_mcp_reset_seq, cnt = 0;
 257         enum _ecore_status_t rc = ECORE_SUCCESS;
 258
 259 #ifndef ASIC_ONLY
 260         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 261                 delay = EMUL_MCP_RESP_ITER_US;
 262 #endif
 263
 264         /* Ensure that only a single thread is accessing the mailbox at a
 265          * certain time.
 266          */
 267         rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 268         if (rc != ECORE_SUCCESS)
 269                 return rc;
 270
 271         /* Set drv command along with the updated sequence */
 272         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 273         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 274
 275         do {
 276                 /* Wait for MFW response */
 277                 OSAL_UDELAY(delay);
 278                 /* Give the FW up to 500 second (50*1000*10usec) */
 279         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 280                                                 MISCS_REG_GENERIC_POR_0)) &&
 281                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 282
 283         if (org_mcp_reset_seq !=
 284             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 285                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 286                            "MCP was reset after %d usec\n", cnt * delay);
 287         } else {
 288                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 289                 rc = ECORE_AGAIN;
 290         }
 291
 292         ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 293
 294         return rc;
 295 }
 296
 297 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
 298                                              struct ecore_ptt *p_ptt,
 299                                              u32 cmd, u32 param,
 300                                              u32 *o_mcp_resp,
 301                                              u32 *o_mcp_param)
 302 {
 303         u32 delay = CHIP_MCP_RESP_ITER_US;
 304         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 305         u32 seq, cnt = 1, actual_mb_seq;
 306         enum _ecore_status_t rc = ECORE_SUCCESS;
 307
 308 #ifndef ASIC_ONLY
 309         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 310                 delay = EMUL_MCP_RESP_ITER_US;
 311         /* There is a built-in delay of 100usec in each MFW response read */
 312         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 313                 max_retries /= 10;
 314 #endif
 315
 316         /* Get actual driver mailbox sequence */
 317         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 318             DRV_MSG_SEQ_NUMBER_MASK;
 319
 320         /* Use MCP history register to check if MCP reset occurred between
 321          * init time and now.
 322          */
 323         if (p_hwfn->mcp_info->mcp_hist !=
 324             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 325                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
 326                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 327                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 328         }
 329         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 330
 331         /* Set drv param */
 332         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 333
 334         /* Set drv command along with the updated sequence */
 335         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 336
 337         do {
 338                 /* Wait for MFW response */
 339                 OSAL_UDELAY(delay);
 340                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 341
 342                 /* Give the FW up to 5 second (500*10ms) */
 343         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 344                  (cnt++ < max_retries));
 345
 346         /* Is this a reply to our command? */
 347         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 348                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 349                 /* Get the MCP param */
 350                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 351         } else {
 352                 /* FW BUG! */
 353                 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
 354                        cmd, param);
 355                 *o_mcp_resp = 0;
 356                 rc = ECORE_AGAIN;
 357                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 358         }
 359         return rc;
 360 }
 361
 362 static enum _ecore_status_t
 363 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 364                         struct ecore_ptt *p_ptt,
 365                         struct ecore_mcp_mb_params *p_mb_params)
 366 {
 367         u32 union_data_addr;
 368         enum _ecore_status_t rc;
 369
 370         /* MCP not initialized */
 371         if (!ecore_mcp_is_init(p_hwfn)) {
 372                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 373                 return ECORE_BUSY;
 374         }
 375
 376         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 377                           OFFSETOF(struct public_drv_mb, union_data);
 378
 379         /* Ensure that only a single thread is accessing the mailbox at a
 380          * certain time.
 381          */
 382         rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 383         if (rc != ECORE_SUCCESS)
 384                 return rc;
 385
 386         if (p_mb_params->p_data_src != OSAL_NULL)
 387                 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr,
 388                                 p_mb_params->p_data_src,
 389                                 sizeof(*p_mb_params->p_data_src));
 390
 391         rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 392                               p_mb_params->param, &p_mb_params->mcp_resp,
 393                               &p_mb_params->mcp_param);
 394
 395         if (p_mb_params->p_data_dst != OSAL_NULL)
 396                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 397                                   union_data_addr,
 398                                   sizeof(*p_mb_params->p_data_dst));
 399
 400         ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 401
 402         return rc;
 403 }
 404
 405 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 406                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 407                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 408 {
 409         struct ecore_mcp_mb_params mb_params;
 410         enum _ecore_status_t rc;
 411
 412 #ifndef ASIC_ONLY
 413         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 414                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 415                         loaded--;
 416                         loaded_port[p_hwfn->port_id]--;
 417                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 418                                    loaded);
 419                 }
 420                 return ECORE_SUCCESS;
 421         }
 422 #endif
 423
 424         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 425         mb_params.cmd = cmd;
 426         mb_params.param = param;
 427         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 428         if (rc != ECORE_SUCCESS)
 429                 return rc;
 430
 431         *o_mcp_resp = mb_params.mcp_resp;
 432         *o_mcp_param = mb_params.mcp_param;
 433
 434         return ECORE_SUCCESS;
 435 }
 436
 437 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 438                                           struct ecore_ptt *p_ptt,
 439                                           u32 cmd,
 440                                           u32 param,
 441                                           u32 *o_mcp_resp,
 442                                           u32 *o_mcp_param,
 443                                           u32 i_txn_size, u32 *i_buf)
 444 {
 445         struct ecore_mcp_mb_params mb_params;
 446         union drv_union_data union_data;
 447         enum _ecore_status_t rc;
 448
 449         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 450         mb_params.cmd = cmd;
 451         mb_params.param = param;
 452         OSAL_MEMCPY((u32 *)&union_data.raw_data, i_buf, i_txn_size);
 453         mb_params.p_data_src = &union_data;
 454         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 455         if (rc != ECORE_SUCCESS)
 456                 return rc;
 457
 458         *o_mcp_resp = mb_params.mcp_resp;
 459         *o_mcp_param = mb_params.mcp_param;
 460
 461         return ECORE_SUCCESS;
 462 }
 463
 464 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 465                                           struct ecore_ptt *p_ptt,
 466                                           u32 cmd,
 467                                           u32 param,
 468                                           u32 *o_mcp_resp,
 469                                           u32 *o_mcp_param,
 470                                           u32 *o_txn_size, u32 *o_buf)
 471 {
 472         struct ecore_mcp_mb_params mb_params;
 473         union drv_union_data union_data;
 474         enum _ecore_status_t rc;
 475
 476         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 477         mb_params.cmd = cmd;
 478         mb_params.param = param;
 479         mb_params.p_data_dst = &union_data;
 480         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 481         if (rc != ECORE_SUCCESS)
 482                 return rc;
 483
 484         *o_mcp_resp = mb_params.mcp_resp;
 485         *o_mcp_param = mb_params.mcp_param;
 486
 487         *o_txn_size = *o_mcp_param;
 488         OSAL_MEMCPY(o_buf, (u32 *)&union_data.raw_data, *o_txn_size);
 489
 490         return ECORE_SUCCESS;
 491 }
 492
 493 #ifndef ASIC_ONLY
 494 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 495                                     u32 *p_load_code)
 496 {
 497         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 498
 499         if (!loaded)
 500                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 501         else if (!loaded_port[p_hwfn->port_id])
 502                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 503         else
 504                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 505
 506         /* On CMT, always tell that it's engine */
 507         if (p_hwfn->p_dev->num_hwfns > 1)
 508                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 509
 510         *p_load_code = load_phase;
 511         loaded++;
 512         loaded_port[p_hwfn->port_id]++;
 513
 514         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 515                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 516                    *p_load_code, loaded, p_hwfn->port_id,
 517                    loaded_port[p_hwfn->port_id]);
 518 }
 519 #endif
 520
 521 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 522                                         struct ecore_ptt *p_ptt,
 523                                         u32 *p_load_code)
 524 {
 525         struct ecore_dev *p_dev = p_hwfn->p_dev;
 526         struct ecore_mcp_mb_params mb_params;
 527         union drv_union_data union_data;
 528         enum _ecore_status_t rc;
 529
 530 #ifndef ASIC_ONLY
 531         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 532                 ecore_mcp_mf_workaround(p_hwfn, p_load_code);
 533                 return ECORE_SUCCESS;
 534         }
 535 #endif
 536
 537         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 538         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 539         mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
 540                           p_dev->drv_type;
 541         OSAL_MEMCPY(&union_data.ver_str, p_dev->ver_str, MCP_DRV_VER_STR_SIZE);
 542         mb_params.p_data_src = &union_data;
 543         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 544
 545         /* if mcp fails to respond we must abort */
 546         if (rc != ECORE_SUCCESS) {
 547                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 548                 return rc;
 549         }
 550
 551         *p_load_code = mb_params.mcp_resp;
 552
 553         /* If MFW refused (e.g. other port is in diagnostic mode) we
 554          * must abort. This can happen in the following cases:
 555          * - Other port is in diagnostic mode
 556          * - Previously loaded function on the engine is not compliant with
 557          *   the requester.
 558          * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
 559          *      -
 560          */
 561         if (!(*p_load_code) ||
 562             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
 563             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
 564             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
 565                 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
 566                 return ECORE_BUSY;
 567         }
 568
 569         return ECORE_SUCCESS;
 570 }
 571
 572 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
 573                                     struct ecore_ptt *p_ptt)
 574 {
 575         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 576                                         PUBLIC_PATH);
 577         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 578         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
 579                                      ECORE_PATH_ID(p_hwfn));
 580         u32 disabled_vfs[VF_MAX_STATIC / 32];
 581         int i;
 582
 583         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 584                    "Reading Disabled VF information from [offset %08x],"
 585                    " path_addr %08x\n",
 586                    mfw_path_offsize, path_addr);
 587
 588         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
 589                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
 590                                            path_addr +
 591                                            OFFSETOF(struct public_path,
 592                                                     mcp_vf_disabled) +
 593                                            sizeof(u32) * i);
 594                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 595                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
 596                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
 597         }
 598
 599         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
 600                 OSAL_VF_FLR_UPDATE(p_hwfn);
 601 }
 602
 603 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
 604                                           struct ecore_ptt *p_ptt,
 605                                           u32 *vfs_to_ack)
 606 {
 607         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 608                                         PUBLIC_FUNC);
 609         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 610         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
 611                                      MCP_PF_ID(p_hwfn));
 612         struct ecore_mcp_mb_params mb_params;
 613         union drv_union_data union_data;
 614         enum _ecore_status_t rc;
 615         int i;
 616
 617         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 618                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 619                            "Acking VFs [%08x,...,%08x] - %08x\n",
 620                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
 621
 622         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 623         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
 624         OSAL_MEMCPY(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
 625         mb_params.p_data_src = &union_data;
 626         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
 627                                      &mb_params);
 628         if (rc != ECORE_SUCCESS) {
 629                 DP_NOTICE(p_hwfn, false,
 630                           "Failed to pass ACK for VF flr to MFW\n");
 631                 return ECORE_TIMEOUT;
 632         }
 633
 634         /* TMP - clear the ACK bits; should be done by MFW */
 635         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 636                 ecore_wr(p_hwfn, p_ptt,
 637                          func_addr +
 638                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
 639                          i * sizeof(u32), 0);
 640
 641         return rc;
 642 }
 643
 644 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
 645                                                 struct ecore_ptt *p_ptt)
 646 {
 647         u32 transceiver_state;
 648
 649         transceiver_state = ecore_rd(p_hwfn, p_ptt,
 650                                      p_hwfn->mcp_info->port_addr +
 651                                      OFFSETOF(struct public_port,
 652                                               transceiver_data));
 653
 654         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
 655                    "Received transceiver state update [0x%08x] from mfw"
 656                    " [Addr 0x%x]\n",
 657                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
 658                                             OFFSETOF(struct public_port,
 659                                                      transceiver_data)));
 660
 661         transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
 662
 663         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
 664                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
 665         else
 666                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
 667 }
 668
 669 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
 670                                          struct ecore_ptt *p_ptt,
 671                                          bool b_reset)
 672 {
 673         struct ecore_mcp_link_state *p_link;
 674         u8 max_bw, min_bw;
 675         u32 status = 0;
 676
 677         p_link = &p_hwfn->mcp_info->link_output;
 678         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
 679         if (!b_reset) {
 680                 status = ecore_rd(p_hwfn, p_ptt,
 681                                   p_hwfn->mcp_info->port_addr +
 682                                   OFFSETOF(struct public_port, link_status));
 683                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
 684                            "Received link update [0x%08x] from mfw"
 685                            " [Addr 0x%x]\n",
 686                            status, (u32)(p_hwfn->mcp_info->port_addr +
 687                                           OFFSETOF(struct public_port,
 688                                                    link_status)));
 689         } else {
 690                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 691                            "Resetting link indications\n");
 692                 return;
 693         }
 694
 695         if (p_hwfn->b_drv_link_init)
 696                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
 697         else
 698                 p_link->link_up = false;
 699
 700         p_link->full_duplex = true;
 701         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
 702         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
 703                 p_link->speed = 100000;
 704                 break;
 705         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
 706                 p_link->speed = 50000;
 707                 break;
 708         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
 709                 p_link->speed = 40000;
 710                 break;
 711         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
 712                 p_link->speed = 25000;
 713                 break;
 714         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
 715                 p_link->speed = 20000;
 716                 break;
 717         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
 718                 p_link->speed = 10000;
 719                 break;
 720         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
 721                 p_link->full_duplex = false;
 722                 /* Fall-through */
 723         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
 724                 p_link->speed = 1000;
 725                 break;
 726         default:
 727                 p_link->speed = 0;
 728         }
 729
 730         /* We never store total line speed as p_link->speed is
 731          * again changes according to bandwidth allocation.
 732          */
 733         if (p_link->link_up && p_link->speed)
 734                 p_link->line_speed = p_link->speed;
 735         else
 736                 p_link->line_speed = 0;
 737
 738         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
 739         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
 740
 741         /* Max bandwidth configuration */
 742         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
 743                                            p_link, max_bw);
 744
 745         /* Mintz bandwidth configuration */
 746         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
 747                                            p_link, min_bw);
 748         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
 749                                               p_link->min_pf_rate);
 750
 751         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
 752         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
 753         p_link->parallel_detection = !!(status &
 754                                          LINK_STATUS_PARALLEL_DETECTION_USED);
 755         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
 756
 757         p_link->partner_adv_speed |=
 758             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
 759             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
 760         p_link->partner_adv_speed |=
 761             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
 762             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
 763         p_link->partner_adv_speed |=
 764             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
 765             ECORE_LINK_PARTNER_SPEED_10G : 0;
 766         p_link->partner_adv_speed |=
 767             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
 768             ECORE_LINK_PARTNER_SPEED_20G : 0;
 769         p_link->partner_adv_speed |=
 770             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
 771             ECORE_LINK_PARTNER_SPEED_25G : 0;
 772         p_link->partner_adv_speed |=
 773             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
 774             ECORE_LINK_PARTNER_SPEED_40G : 0;
 775         p_link->partner_adv_speed |=
 776             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
 777             ECORE_LINK_PARTNER_SPEED_50G : 0;
 778         p_link->partner_adv_speed |=
 779             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
 780             ECORE_LINK_PARTNER_SPEED_100G : 0;
 781
 782         p_link->partner_tx_flow_ctrl_en =
 783             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
 784         p_link->partner_rx_flow_ctrl_en =
 785             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
 786
 787         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
 788         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
 789                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
 790                 break;
 791         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
 792                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
 793                 break;
 794         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
 795                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
 796                 break;
 797         default:
 798                 p_link->partner_adv_pause = 0;
 799         }
 800
 801         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
 802
 803         OSAL_LINK_UPDATE(p_hwfn);
 804 }
 805
 806 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
 807                                         struct ecore_ptt *p_ptt, bool b_up)
 808 {
 809         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
 810         struct ecore_mcp_mb_params mb_params;
 811         union drv_union_data union_data;
 812         struct eth_phy_cfg *p_phy_cfg;
 813         enum _ecore_status_t rc = ECORE_SUCCESS;
 814         u32 cmd;
 815
 816 #ifndef ASIC_ONLY
 817         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 818                 return ECORE_SUCCESS;
 819 #endif
 820
 821         /* Set the shmem configuration according to params */
 822         p_phy_cfg = &union_data.drv_phy_cfg;
 823         OSAL_MEMSET(p_phy_cfg, 0, sizeof(*p_phy_cfg));
 824         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
 825         if (!params->speed.autoneg)
 826                 p_phy_cfg->speed = params->speed.forced_speed;
 827         p_phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
 828         p_phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
 829         p_phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
 830         p_phy_cfg->adv_speed = params->speed.advertised_speeds;
 831         p_phy_cfg->loopback_mode = params->loopback_mode;
 832         p_hwfn->b_drv_link_init = b_up;
 833
 834         if (b_up)
 835                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
 836                            "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
 837                            " adv_speed 0x%08x, loopback 0x%08x\n",
 838                            p_phy_cfg->speed, p_phy_cfg->pause,
 839                            p_phy_cfg->adv_speed, p_phy_cfg->loopback_mode);
 840         else
 841                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
 842
 843         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 844         mb_params.cmd = cmd;
 845         mb_params.p_data_src = &union_data;
 846         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 847
 848         /* if mcp fails to respond we must abort */
 849         if (rc != ECORE_SUCCESS) {
 850                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 851                 return rc;
 852         }
 853
 854         /* Reset the link status if needed */
 855         if (!b_up)
 856                 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
 857
 858         return rc;
 859 }
 860
 861 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
 862                                    struct ecore_ptt *p_ptt)
 863 {
 864         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
 865
 866         /* TODO - Add support for VFs */
 867         if (IS_VF(p_hwfn->p_dev))
 868                 return ECORE_INVAL;
 869
 870         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 871                                                  PUBLIC_PATH);
 872         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
 873         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
 874
 875         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
 876                                  path_addr +
 877                                  OFFSETOF(struct public_path, process_kill)) &
 878             PROCESS_KILL_COUNTER_MASK;
 879
 880         return proc_kill_cnt;
 881 }
 882
 883 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
 884                                           struct ecore_ptt *p_ptt)
 885 {
 886         struct ecore_dev *p_dev = p_hwfn->p_dev;
 887         u32 proc_kill_cnt;
 888
 889         /* Prevent possible attentions/interrupts during the recovery handling
 890          * and till its load phase, during which they will be re-enabled.
 891          */
 892         ecore_int_igu_disable_int(p_hwfn, p_ptt);
 893
 894         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
 895
 896         /* The following operations should be done once, and thus in CMT mode
 897          * are carried out by only the first HW function.
 898          */
 899         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
 900                 return;
 901
 902         if (p_dev->recov_in_prog) {
 903                 DP_NOTICE(p_hwfn, false,
 904                           "Ignoring the indication since a recovery"
 905                           " process is already in progress\n");
 906                 return;
 907         }
 908
 909         p_dev->recov_in_prog = true;
 910
 911         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
 912         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
 913
 914         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
 915 }
 916
 917 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
 918                                           struct ecore_ptt *p_ptt,
 919                                           enum MFW_DRV_MSG_TYPE type)
 920 {
 921         enum ecore_mcp_protocol_type stats_type;
 922         union ecore_mcp_protocol_stats stats;
 923         struct ecore_mcp_mb_params mb_params;
 924         union drv_union_data union_data;
 925         u32 hsi_param;
 926
 927         switch (type) {
 928         case MFW_DRV_MSG_GET_LAN_STATS:
 929                 stats_type = ECORE_MCP_LAN_STATS;
 930                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
 931                 break;
 932         default:
 933                 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
 934                 return;
 935         }
 936
 937         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
 938
 939         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 940         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
 941         mb_params.param = hsi_param;
 942         OSAL_MEMCPY(&union_data, &stats, sizeof(stats));
 943         mb_params.p_data_src = &union_data;
 944         ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 945 }
 946
 947 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
 948                                     struct public_func *p_shmem_info)
 949 {
 950         struct ecore_mcp_function_info *p_info;
 951
 952         p_info = &p_hwfn->mcp_info->func_info;
 953
 954         /* TODO - bandwidth min/max should have valid values of 1-100,
 955          * as well as some indication that the feature is disabled.
 956          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
 957          * limit and correct value to min `1' and max `100' if limit isn't in
 958          * range.
 959          */
 960         p_info->bandwidth_min = (p_shmem_info->config &
 961                                  FUNC_MF_CFG_MIN_BW_MASK) >>
 962             FUNC_MF_CFG_MIN_BW_SHIFT;
 963         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
 964                 DP_INFO(p_hwfn,
 965                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
 966                         p_info->bandwidth_min);
 967                 p_info->bandwidth_min = 1;
 968         }
 969
 970         p_info->bandwidth_max = (p_shmem_info->config &
 971                                  FUNC_MF_CFG_MAX_BW_MASK) >>
 972             FUNC_MF_CFG_MAX_BW_SHIFT;
 973         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
 974                 DP_INFO(p_hwfn,
 975                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
 976                         p_info->bandwidth_max);
 977                 p_info->bandwidth_max = 100;
 978         }
 979 }
 980
 981 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
 982                                     struct ecore_ptt *p_ptt,
 983                                     struct public_func *p_data,
 984                                     int pfid)
 985 {
 986         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 987                                         PUBLIC_FUNC);
 988         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 989         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
 990         u32 i, size;
 991
 992         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
 993
 994         size = OSAL_MIN_T(u32, sizeof(*p_data),
 995                           SECTION_SIZE(mfw_path_offsize));
 996         for (i = 0; i < size / sizeof(u32); i++)
 997                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
 998                                               func_addr + (i << 2));
 999
1000         return size;
1001 }
1002
1003 static void
1004 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1005 {
1006         struct ecore_mcp_function_info *p_info;
1007         struct public_func shmem_info;
1008         u32 resp = 0, param = 0;
1009
1010         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1011
1012         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1013
1014         p_info = &p_hwfn->mcp_info->func_info;
1015
1016         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1017
1018         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1019
1020         /* Acknowledge the MFW */
1021         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1022                       &param);
1023 }
1024
1025 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1026                                          struct ecore_ptt *p_ptt)
1027 {
1028         /* A single notification should be sent to upper driver in CMT mode */
1029         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1030                 return;
1031
1032         DP_NOTICE(p_hwfn, false,
1033                   "Fan failure was detected on the network interface card"
1034                   " and it's going to be shut down.\n");
1035
1036         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1037 }
1038
1039 static enum _ecore_status_t
1040 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1041                     u32 mdump_cmd, union drv_union_data *p_data_src,
1042                     union drv_union_data *p_data_dst, u32 *p_mcp_resp)
1043 {
1044         struct ecore_mcp_mb_params mb_params;
1045         enum _ecore_status_t rc;
1046
1047         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1048         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1049         mb_params.param = mdump_cmd;
1050         mb_params.p_data_src = p_data_src;
1051         mb_params.p_data_dst = p_data_dst;
1052         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1053         if (rc != ECORE_SUCCESS)
1054                 return rc;
1055
1056         *p_mcp_resp = mb_params.mcp_resp;
1057         if (*p_mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1058                 DP_NOTICE(p_hwfn, false,
1059                           "MFW claims that the mdump command is illegal [mdump_cmd 0x%x]\n",
1060                           mdump_cmd);
1061                 rc = ECORE_INVAL;
1062         }
1063
1064         return rc;
1065 }
1066
1067 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1068                                                 struct ecore_ptt *p_ptt)
1069 {
1070         u32 mcp_resp;
1071
1072         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_ACK,
1073                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1074 }
1075
1076 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1077                                                 struct ecore_ptt *p_ptt,
1078                                                 u32 epoch)
1079 {
1080         union drv_union_data union_data;
1081         u32 mcp_resp;
1082
1083         OSAL_MEMCPY(&union_data.raw_data, &epoch, sizeof(epoch));
1084
1085         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_SET_VALUES,
1086                                    &union_data, OSAL_NULL, &mcp_resp);
1087 }
1088
1089 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1090                                              struct ecore_ptt *p_ptt)
1091 {
1092         u32 mcp_resp;
1093
1094         p_hwfn->p_dev->mdump_en = true;
1095
1096         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_TRIGGER,
1097                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1098 }
1099
1100 static enum _ecore_status_t
1101 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1102                            struct mdump_config_stc *p_mdump_config)
1103 {
1104         union drv_union_data union_data;
1105         u32 mcp_resp;
1106         enum _ecore_status_t rc;
1107
1108         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_GET_CONFIG,
1109                                  OSAL_NULL, &union_data, &mcp_resp);
1110         if (rc != ECORE_SUCCESS)
1111                 return rc;
1112
1113         /* A zero response implies that the mdump command is not supported */
1114         if (!mcp_resp)
1115                 return ECORE_NOTIMPL;
1116
1117         if (mcp_resp != FW_MSG_CODE_OK) {
1118                 DP_NOTICE(p_hwfn, false,
1119                           "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1120                           mcp_resp);
1121                 rc = ECORE_UNKNOWN_ERROR;
1122         }
1123
1124         OSAL_MEMCPY(p_mdump_config, &union_data.mdump_config,
1125                     sizeof(*p_mdump_config));
1126
1127         return rc;
1128 }
1129
1130 enum _ecore_status_t
1131 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1132                          struct ecore_mdump_info *p_mdump_info)
1133 {
1134         u32 addr, global_offsize, global_addr;
1135         struct mdump_config_stc mdump_config;
1136         enum _ecore_status_t rc;
1137
1138         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1139
1140         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1141                                     PUBLIC_GLOBAL);
1142         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1143         global_addr = SECTION_ADDR(global_offsize, 0);
1144         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1145                                         global_addr +
1146                                         OFFSETOF(struct public_global,
1147                                                  mdump_reason));
1148
1149         if (p_mdump_info->reason) {
1150                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1151                 if (rc != ECORE_SUCCESS)
1152                         return rc;
1153
1154                 p_mdump_info->version = mdump_config.version;
1155                 p_mdump_info->config = mdump_config.config;
1156                 p_mdump_info->epoch = mdump_config.epoc;
1157                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1158                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1159
1160                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1161                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1162                            p_mdump_info->reason, p_mdump_info->version,
1163                            p_mdump_info->config, p_mdump_info->epoch,
1164                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1165         } else {
1166                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1167                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1168         }
1169
1170         return ECORE_SUCCESS;
1171 }
1172
1173 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1174                                                 struct ecore_ptt *p_ptt)
1175 {
1176         u32 mcp_resp;
1177
1178         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_CLEAR_LOGS,
1179                                    OSAL_NULL, OSAL_NULL, &mcp_resp);
1180 }
1181
1182 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1183                                             struct ecore_ptt *p_ptt)
1184 {
1185         /* In CMT mode - no need for more than a single acknowledgment to the
1186          * MFW, and no more than a single notification to the upper driver.
1187          */
1188         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1189                 return;
1190
1191         DP_NOTICE(p_hwfn, false,
1192                   "Received a critical error notification from the MFW!\n");
1193
1194         if (p_hwfn->p_dev->mdump_en) {
1195                 DP_NOTICE(p_hwfn, false,
1196                           "Not acknowledging the notification to allow the MFW crash dump\n");
1197                 p_hwfn->p_dev->mdump_en = false;
1198                 return;
1199         }
1200
1201         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1202         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1203 }
1204
1205 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1206                                              struct ecore_ptt *p_ptt)
1207 {
1208         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1209         enum _ecore_status_t rc = ECORE_SUCCESS;
1210         bool found = false;
1211         u16 i;
1212
1213         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1214
1215         /* Read Messages from MFW */
1216         ecore_mcp_read_mb(p_hwfn, p_ptt);
1217
1218         /* Compare current messages to old ones */
1219         for (i = 0; i < info->mfw_mb_length; i++) {
1220                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1221                         continue;
1222
1223                 found = true;
1224
1225                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1226                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1227                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1228
1229                 switch (i) {
1230                 case MFW_DRV_MSG_LINK_CHANGE:
1231                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1232                         break;
1233                 case MFW_DRV_MSG_VF_DISABLED:
1234                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1235                         break;
1236                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1237                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1238                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1239                         break;
1240                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1241                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1242                                                     ECORE_DCBX_REMOTE_MIB);
1243                         break;
1244                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1245                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1246                                                     ECORE_DCBX_OPERATIONAL_MIB);
1247                         break;
1248                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1249                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1250                         break;
1251                 case MFW_DRV_MSG_ERROR_RECOVERY:
1252                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1253                         break;
1254                 case MFW_DRV_MSG_GET_LAN_STATS:
1255                 case MFW_DRV_MSG_GET_FCOE_STATS:
1256                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1257                 case MFW_DRV_MSG_GET_RDMA_STATS:
1258                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1259                         break;
1260                 case MFW_DRV_MSG_BW_UPDATE:
1261                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1262                         break;
1263                 case MFW_DRV_MSG_FAILURE_DETECTED:
1264                         ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1265                         break;
1266                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1267                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1268                         break;
1269                 default:
1270                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1271                         rc = ECORE_INVAL;
1272                 }
1273         }
1274
1275         /* ACK everything */
1276         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1277                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1278
1279                 /* MFW expect answer in BE, so we force write in that format */
1280                 ecore_wr(p_hwfn, p_ptt,
1281                          info->mfw_mb_addr + sizeof(u32) +
1282                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1283                          sizeof(u32) + i * sizeof(u32), val);
1284         }
1285
1286         if (!found) {
1287                 DP_NOTICE(p_hwfn, false,
1288                           "Received an MFW message indication but no"
1289                           " new message!\n");
1290                 rc = ECORE_INVAL;
1291         }
1292
1293         /* Copy the new mfw messages into the shadow */
1294         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1295
1296         return rc;
1297 }
1298
1299 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1300                                            struct ecore_ptt *p_ptt,
1301                                            u32 *p_mfw_ver,
1302                                            u32 *p_running_bundle_id)
1303 {
1304         u32 global_offsize;
1305
1306 #ifndef ASIC_ONLY
1307         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1308                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1309                 return ECORE_SUCCESS;
1310         }
1311 #endif
1312
1313         if (IS_VF(p_hwfn->p_dev)) {
1314                 if (p_hwfn->vf_iov_info) {
1315                         struct pfvf_acquire_resp_tlv *p_resp;
1316
1317                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1318                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1319                         return ECORE_SUCCESS;
1320                 } else {
1321                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1322                                    "VF requested MFW version prior to ACQUIRE\n");
1323                         return ECORE_INVAL;
1324                 }
1325         }
1326
1327         global_offsize = ecore_rd(p_hwfn, p_ptt,
1328                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1329                                                        public_base,
1330                                                        PUBLIC_GLOBAL));
1331         *p_mfw_ver =
1332             ecore_rd(p_hwfn, p_ptt,
1333                      SECTION_ADDR(global_offsize,
1334                                   0) + OFFSETOF(struct public_global, mfw_ver));
1335
1336         if (p_running_bundle_id != OSAL_NULL) {
1337                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1338                                                 SECTION_ADDR(global_offsize,
1339                                                              0) +
1340                                                 OFFSETOF(struct public_global,
1341                                                          running_bundle_id));
1342         }
1343
1344         return ECORE_SUCCESS;
1345 }
1346
1347 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1348                                               u32 *p_media_type)
1349 {
1350         struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1351         struct ecore_ptt *p_ptt;
1352
1353         /* TODO - Add support for VFs */
1354         if (IS_VF(p_dev))
1355                 return ECORE_INVAL;
1356
1357         if (!ecore_mcp_is_init(p_hwfn)) {
1358                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1359                 return ECORE_BUSY;
1360         }
1361
1362         *p_media_type = MEDIA_UNSPECIFIED;
1363
1364         p_ptt = ecore_ptt_acquire(p_hwfn);
1365         if (!p_ptt)
1366                 return ECORE_BUSY;
1367
1368         *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1369                                  OFFSETOF(struct public_port, media_type));
1370
1371         ecore_ptt_release(p_hwfn, p_ptt);
1372
1373         return ECORE_SUCCESS;
1374 }
1375
1376 static enum _ecore_status_t
1377 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1378                           struct public_func *p_info,
1379                           enum ecore_pci_personality *p_proto)
1380 {
1381         enum _ecore_status_t rc = ECORE_SUCCESS;
1382
1383         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1384         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1385                 *p_proto = ECORE_PCI_ETH;
1386                 break;
1387         default:
1388                 rc = ECORE_INVAL;
1389         }
1390
1391         return rc;
1392 }
1393
1394 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1395                                                     struct ecore_ptt *p_ptt)
1396 {
1397         struct ecore_mcp_function_info *info;
1398         struct public_func shmem_info;
1399
1400         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1401         info = &p_hwfn->mcp_info->func_info;
1402
1403         info->pause_on_host = (shmem_info.config &
1404                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1405
1406         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) {
1407                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1408                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1409                 return ECORE_INVAL;
1410         }
1411
1412         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1413
1414         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1415                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1416                 info->mac[1] = (u8)(shmem_info.mac_upper);
1417                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1418                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1419                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1420                 info->mac[5] = (u8)(shmem_info.mac_lower);
1421         } else {
1422                 /* TODO - are there protocols for which there's no MAC? */
1423                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1424         }
1425
1426         /* TODO - are these calculations true for BE machine? */
1427         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1428                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1429         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1430                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1431
1432         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1433
1434         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1435                    "Read configuration from shmem: pause_on_host %02x"
1436                     " protocol %02x BW [%02x - %02x]"
1437                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1438                     " node %lx ovlan %04x\n",
1439                    info->pause_on_host, info->protocol,
1440                    info->bandwidth_min, info->bandwidth_max,
1441                    info->mac[0], info->mac[1], info->mac[2],
1442                    info->mac[3], info->mac[4], info->mac[5],
1443                    (unsigned long)info->wwn_port,
1444                    (unsigned long)info->wwn_node, info->ovlan);
1445
1446         return ECORE_SUCCESS;
1447 }
1448
1449 struct ecore_mcp_link_params
1450 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1451 {
1452         if (!p_hwfn || !p_hwfn->mcp_info)
1453                 return OSAL_NULL;
1454         return &p_hwfn->mcp_info->link_input;
1455 }
1456
1457 struct ecore_mcp_link_state
1458 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1459 {
1460         if (!p_hwfn || !p_hwfn->mcp_info)
1461                 return OSAL_NULL;
1462
1463 #ifndef ASIC_ONLY
1464         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1465                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1466                 p_hwfn->mcp_info->link_output.link_up = true;
1467         }
1468 #endif
1469
1470         return &p_hwfn->mcp_info->link_output;
1471 }
1472
1473 struct ecore_mcp_link_capabilities
1474 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1475 {
1476         if (!p_hwfn || !p_hwfn->mcp_info)
1477                 return OSAL_NULL;
1478         return &p_hwfn->mcp_info->link_capabilities;
1479 }
1480
1481 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1482                                      struct ecore_ptt *p_ptt)
1483 {
1484         u32 resp = 0, param = 0;
1485         enum _ecore_status_t rc;
1486
1487         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1488                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1489
1490         /* Wait for the drain to complete before returning */
1491         OSAL_MSLEEP(1020);
1492
1493         return rc;
1494 }
1495
1496 const struct ecore_mcp_function_info
1497 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1498 {
1499         if (!p_hwfn || !p_hwfn->mcp_info)
1500                 return OSAL_NULL;
1501         return &p_hwfn->mcp_info->func_info;
1502 }
1503
1504 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1505                                            struct ecore_ptt *p_ptt,
1506                                            struct ecore_mcp_nvm_params *params)
1507 {
1508         enum _ecore_status_t rc;
1509
1510         switch (params->type) {
1511         case ECORE_MCP_NVM_RD:
1512                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1513                                           params->nvm_common.offset,
1514                                           &params->nvm_common.resp,
1515                                           &params->nvm_common.param,
1516                                           params->nvm_rd.buf_size,
1517                                           params->nvm_rd.buf);
1518                 break;
1519         case ECORE_MCP_CMD:
1520                 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1521                                    params->nvm_common.offset,
1522                                    &params->nvm_common.resp,
1523                                    &params->nvm_common.param);
1524                 break;
1525         case ECORE_MCP_NVM_WR:
1526                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1527                                           params->nvm_common.offset,
1528                                           &params->nvm_common.resp,
1529                                           &params->nvm_common.param,
1530                                           params->nvm_wr.buf_size,
1531                                           params->nvm_wr.buf);
1532                 break;
1533         default:
1534                 rc = ECORE_NOTIMPL;
1535                 break;
1536         }
1537         return rc;
1538 }
1539
1540 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1541                                   struct ecore_ptt *p_ptt, u32 personalities)
1542 {
1543         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1544         struct public_func shmem_info;
1545         int i, count = 0, num_pfs;
1546
1547         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1548
1549         for (i = 0; i < num_pfs; i++) {
1550                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1551                                          MCP_PF_ID_BY_REL(p_hwfn, i));
1552                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1553                         continue;
1554
1555                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info,
1556                                               &protocol) != ECORE_SUCCESS)
1557                         continue;
1558
1559                 if ((1 << ((u32)protocol)) & personalities)
1560                         count++;
1561         }
1562
1563         return count;
1564 }
1565
1566 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1567                                               struct ecore_ptt *p_ptt,
1568                                               u32 *p_flash_size)
1569 {
1570         u32 flash_size;
1571
1572 #ifndef ASIC_ONLY
1573         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1574                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
1575                 return ECORE_INVAL;
1576         }
1577 #endif
1578
1579         if (IS_VF(p_hwfn->p_dev))
1580                 return ECORE_INVAL;
1581
1582         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1583         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1584             MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1585         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1586
1587         *p_flash_size = flash_size;
1588
1589         return ECORE_SUCCESS;
1590 }
1591
1592 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
1593                                                   struct ecore_ptt *p_ptt)
1594 {
1595         struct ecore_dev *p_dev = p_hwfn->p_dev;
1596
1597         if (p_dev->recov_in_prog) {
1598                 DP_NOTICE(p_hwfn, false,
1599                           "Avoid triggering a recovery since such a process"
1600                           " is already in progress\n");
1601                 return ECORE_AGAIN;
1602         }
1603
1604         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
1605         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
1606
1607         return ECORE_SUCCESS;
1608 }
1609
1610 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
1611                                               struct ecore_ptt *p_ptt,
1612                                               u8 vf_id, u8 num)
1613 {
1614         u32 resp = 0, param = 0, rc_param = 0;
1615         enum _ecore_status_t rc;
1616
1617 /* Only Leader can configure MSIX, and need to take CMT into account */
1618
1619         if (!IS_LEAD_HWFN(p_hwfn))
1620                 return ECORE_SUCCESS;
1621         num *= p_hwfn->p_dev->num_hwfns;
1622
1623         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1624             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1625         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1626             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1627
1628         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1629                            &resp, &rc_param);
1630
1631         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1632                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
1633                           vf_id);
1634                 rc = ECORE_INVAL;
1635         } else {
1636                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1637                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1638                             num, vf_id);
1639         }
1640
1641         return rc;
1642 }
1643
1644 enum _ecore_status_t
1645 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1646                            struct ecore_mcp_drv_version *p_ver)
1647 {
1648         struct drv_version_stc *p_drv_version;
1649         struct ecore_mcp_mb_params mb_params;
1650         union drv_union_data union_data;
1651         u32 num_words, i;
1652         void *p_name;
1653         OSAL_BE32 val;
1654         enum _ecore_status_t rc;
1655
1656 #ifndef ASIC_ONLY
1657         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
1658                 return ECORE_SUCCESS;
1659 #endif
1660
1661         p_drv_version = &union_data.drv_version;
1662         p_drv_version->version = p_ver->version;
1663         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
1664         for (i = 0; i < num_words; i++) {
1665                 p_name = &p_ver->name[i * sizeof(u32)];
1666                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
1667                 *(u32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1668         }
1669
1670         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1671         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1672         mb_params.p_data_src = &union_data;
1673         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1674         if (rc != ECORE_SUCCESS)
1675                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1676
1677         return rc;
1678 }
1679
1680 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
1681                                     struct ecore_ptt *p_ptt)
1682 {
1683         enum _ecore_status_t rc;
1684         u32 resp = 0, param = 0;
1685
1686         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1687                            &param);
1688         if (rc != ECORE_SUCCESS)
1689                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1690
1691         return rc;
1692 }
1693
1694 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
1695                                       struct ecore_ptt *p_ptt)
1696 {
1697         u32 value, cpu_mode;
1698
1699         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1700
1701         value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1702         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1703         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1704         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1705
1706         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
1707 }
1708
1709 enum _ecore_status_t
1710 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
1711                                    struct ecore_ptt *p_ptt,
1712                                    enum ecore_ov_config_method config,
1713                                    enum ecore_ov_client client)
1714 {
1715         enum _ecore_status_t rc;
1716         u32 resp = 0, param = 0;
1717         u32 drv_mb_param;
1718
1719         switch (config) {
1720         case ECORE_OV_CLIENT_DRV:
1721                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1722                 break;
1723         case ECORE_OV_CLIENT_USER:
1724                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1725                 break;
1726         case ECORE_OV_CLIENT_VENDOR_SPEC:
1727                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
1728                 break;
1729         default:
1730                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", config);
1731                 return ECORE_INVAL;
1732         }
1733
1734         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1735                            drv_mb_param, &resp, &param);
1736         if (rc != ECORE_SUCCESS)
1737                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1738
1739         return rc;
1740 }
1741
1742 enum _ecore_status_t
1743 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
1744                                  struct ecore_ptt *p_ptt,
1745                                  enum ecore_ov_driver_state drv_state)
1746 {
1747         enum _ecore_status_t rc;
1748         u32 resp = 0, param = 0;
1749         u32 drv_mb_param;
1750
1751         switch (drv_state) {
1752         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
1753                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1754                 break;
1755         case ECORE_OV_DRIVER_STATE_DISABLED:
1756                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1757                 break;
1758         case ECORE_OV_DRIVER_STATE_ACTIVE:
1759                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1760                 break;
1761         default:
1762                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
1763                 return ECORE_INVAL;
1764         }
1765
1766         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1767                            drv_mb_param, &resp, &param);
1768         if (rc != ECORE_SUCCESS)
1769                 DP_ERR(p_hwfn, "Failed to send driver state\n");
1770
1771         return rc;
1772 }
1773
1774 enum _ecore_status_t
1775 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1776                          struct ecore_fc_npiv_tbl *p_table)
1777 {
1778         return 0;
1779 }
1780
1781 enum _ecore_status_t
1782 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
1783                         struct ecore_ptt *p_ptt, u16 mtu)
1784 {
1785         return 0;
1786 }
1787
1788 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
1789                                        struct ecore_ptt *p_ptt,
1790                                        enum ecore_led_mode mode)
1791 {
1792         u32 resp = 0, param = 0, drv_mb_param;
1793         enum _ecore_status_t rc;
1794
1795         switch (mode) {
1796         case ECORE_LED_MODE_ON:
1797                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1798                 break;
1799         case ECORE_LED_MODE_OFF:
1800                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1801                 break;
1802         case ECORE_LED_MODE_RESTORE:
1803                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1804                 break;
1805         default:
1806                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
1807                 return ECORE_INVAL;
1808         }
1809
1810         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1811                            drv_mb_param, &resp, &param);
1812         if (rc != ECORE_SUCCESS)
1813                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1814
1815         return rc;
1816 }
1817
1818 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
1819                                              struct ecore_ptt *p_ptt,
1820                                              u32 mask_parities)
1821 {
1822         enum _ecore_status_t rc;
1823         u32 resp = 0, param = 0;
1824
1825         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1826                            mask_parities, &resp, &param);
1827
1828         if (rc != ECORE_SUCCESS) {
1829                 DP_ERR(p_hwfn,
1830                        "MCP response failure for mask parities, aborting\n");
1831         } else if (resp != FW_MSG_CODE_OK) {
1832                 DP_ERR(p_hwfn,
1833                        "MCP did not ack mask parity request. Old MFW?\n");
1834                 rc = ECORE_INVAL;
1835         }
1836
1837         return rc;
1838 }
1839
1840 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
1841                                         u8 *p_buf, u32 len)
1842 {
1843         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1844         u32 bytes_left, offset, bytes_to_copy, buf_size;
1845         struct ecore_mcp_nvm_params params;
1846         struct ecore_ptt *p_ptt;
1847         enum _ecore_status_t rc = ECORE_SUCCESS;
1848
1849         p_ptt = ecore_ptt_acquire(p_hwfn);
1850         if (!p_ptt)
1851                 return ECORE_BUSY;
1852
1853         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1854         bytes_left = len;
1855         offset = 0;
1856         params.type = ECORE_MCP_NVM_RD;
1857         params.nvm_rd.buf_size = &buf_size;
1858         params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
1859         while (bytes_left > 0) {
1860                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1861                                            MCP_DRV_NVM_BUF_LEN);
1862                 params.nvm_common.offset = (addr + offset) |
1863                     (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
1864                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1865                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1866                 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
1867                                             FW_MSG_CODE_NVM_OK)) {
1868                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1869                         break;
1870                 }
1871
1872                 /* This can be a lengthy process, and it's possible scheduler
1873                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
1874                  */
1875                 if (bytes_left % 0x1000 <
1876                     (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
1877                         OSAL_MSLEEP(1);
1878
1879                 offset += *params.nvm_rd.buf_size;
1880                 bytes_left -= *params.nvm_rd.buf_size;
1881         }
1882
1883         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1884         ecore_ptt_release(p_hwfn, p_ptt);
1885
1886         return rc;
1887 }
1888
1889 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
1890                                         u32 addr, u8 *p_buf, u32 len)
1891 {
1892         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1893         struct ecore_mcp_nvm_params params;
1894         struct ecore_ptt *p_ptt;
1895         enum _ecore_status_t rc;
1896
1897         p_ptt = ecore_ptt_acquire(p_hwfn);
1898         if (!p_ptt)
1899                 return ECORE_BUSY;
1900
1901         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1902         params.type = ECORE_MCP_NVM_RD;
1903         params.nvm_rd.buf_size = &len;
1904         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
1905             DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
1906         params.nvm_common.offset = addr;
1907         params.nvm_rd.buf = (u32 *)p_buf;
1908         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1909         if (rc != ECORE_SUCCESS)
1910                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1911
1912         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1913         ecore_ptt_release(p_hwfn, p_ptt);
1914
1915         return rc;
1916 }
1917
1918 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
1919 {
1920         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1921         struct ecore_mcp_nvm_params params;
1922         struct ecore_ptt *p_ptt;
1923
1924         p_ptt = ecore_ptt_acquire(p_hwfn);
1925         if (!p_ptt)
1926                 return ECORE_BUSY;
1927
1928         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1929         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
1930         ecore_ptt_release(p_hwfn, p_ptt);
1931
1932         return ECORE_SUCCESS;
1933 }
1934
1935 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
1936 {
1937         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1938         struct ecore_mcp_nvm_params params;
1939         struct ecore_ptt *p_ptt;
1940         enum _ecore_status_t rc;
1941
1942         p_ptt = ecore_ptt_acquire(p_hwfn);
1943         if (!p_ptt)
1944                 return ECORE_BUSY;
1945         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1946         params.type = ECORE_MCP_CMD;
1947         params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
1948         params.nvm_common.offset = addr;
1949         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1950         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1951         ecore_ptt_release(p_hwfn, p_ptt);
1952
1953         return rc;
1954 }
1955
1956 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
1957                                                   u32 addr)
1958 {
1959         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1960         struct ecore_mcp_nvm_params params;
1961         struct ecore_ptt *p_ptt;
1962         enum _ecore_status_t rc;
1963
1964         p_ptt = ecore_ptt_acquire(p_hwfn);
1965         if (!p_ptt)
1966                 return ECORE_BUSY;
1967         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1968         params.type = ECORE_MCP_CMD;
1969         params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
1970         params.nvm_common.offset = addr;
1971         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
1972         p_dev->mcp_nvm_resp = params.nvm_common.resp;
1973         ecore_ptt_release(p_hwfn, p_ptt);
1974
1975         return rc;
1976 }
1977
1978 /* rc receives ECORE_INVAL as default parameter because
1979  * it might not enter the while loop if the len is 0
1980  */
1981 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
1982                                          u32 addr, u8 *p_buf, u32 len)
1983 {
1984         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1985         enum _ecore_status_t rc = ECORE_INVAL;
1986         struct ecore_mcp_nvm_params params;
1987         struct ecore_ptt *p_ptt;
1988         u32 buf_idx, buf_size;
1989
1990         p_ptt = ecore_ptt_acquire(p_hwfn);
1991         if (!p_ptt)
1992                 return ECORE_BUSY;
1993
1994         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
1995         params.type = ECORE_MCP_NVM_WR;
1996         if (cmd == ECORE_PUT_FILE_DATA)
1997                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
1998         else
1999                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2000         buf_idx = 0;
2001         while (buf_idx < len) {
2002                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2003                                       MCP_DRV_NVM_BUF_LEN);
2004                 params.nvm_common.offset = ((buf_size <<
2005                                              DRV_MB_PARAM_NVM_LEN_SHIFT)
2006                                             | addr) + buf_idx;
2007                 params.nvm_wr.buf_size = buf_size;
2008                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2009                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2010                 if (rc != ECORE_SUCCESS ||
2011                     ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2012                      (params.nvm_common.resp !=
2013                       FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2014                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2015
2016                 /* This can be a lengthy process, and it's possible scheduler
2017                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2018                  */
2019                 if (buf_idx % 0x1000 >
2020                     (buf_idx + buf_size) % 0x1000)
2021                         OSAL_MSLEEP(1);
2022
2023                 buf_idx += buf_size;
2024         }
2025
2026         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2027         ecore_ptt_release(p_hwfn, p_ptt);
2028
2029         return rc;
2030 }
2031
2032 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2033                                          u32 addr, u8 *p_buf, u32 len)
2034 {
2035         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2036         struct ecore_mcp_nvm_params params;
2037         struct ecore_ptt *p_ptt;
2038         enum _ecore_status_t rc;
2039
2040         p_ptt = ecore_ptt_acquire(p_hwfn);
2041         if (!p_ptt)
2042                 return ECORE_BUSY;
2043
2044         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2045         params.type = ECORE_MCP_NVM_WR;
2046         params.nvm_wr.buf_size = len;
2047         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2048             DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2049         params.nvm_common.offset = addr;
2050         params.nvm_wr.buf = (u32 *)p_buf;
2051         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2052         if (rc != ECORE_SUCCESS)
2053                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2054         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2055         ecore_ptt_release(p_hwfn, p_ptt);
2056
2057         return rc;
2058 }
2059
2060 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2061                                                    u32 addr)
2062 {
2063         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2064         struct ecore_mcp_nvm_params params;
2065         struct ecore_ptt *p_ptt;
2066         enum _ecore_status_t rc;
2067
2068         p_ptt = ecore_ptt_acquire(p_hwfn);
2069         if (!p_ptt)
2070                 return ECORE_BUSY;
2071
2072         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2073         params.type = ECORE_MCP_CMD;
2074         params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2075         params.nvm_common.offset = addr;
2076         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2077         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2078         ecore_ptt_release(p_hwfn, p_ptt);
2079
2080         return rc;
2081 }
2082
2083 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2084                                             struct ecore_ptt *p_ptt,
2085                                             u32 port, u32 addr, u32 offset,
2086                                             u32 len, u8 *p_buf)
2087 {
2088         struct ecore_mcp_nvm_params params;
2089         enum _ecore_status_t rc;
2090         u32 bytes_left, bytes_to_copy, buf_size;
2091
2092         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2093         params.nvm_common.offset =
2094                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2095                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2096         addr = offset;
2097         offset = 0;
2098         bytes_left = len;
2099         params.type = ECORE_MCP_NVM_RD;
2100         params.nvm_rd.buf_size = &buf_size;
2101         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2102         while (bytes_left > 0) {
2103                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2104                                            MAX_I2C_TRANSACTION_SIZE);
2105                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2106                 params.nvm_common.offset &=
2107                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2108                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2109                 params.nvm_common.offset |=
2110                         ((addr + offset) <<
2111                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2112                 params.nvm_common.offset |=
2113                         (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2114                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2115                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2116                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2117                         return ECORE_NODEV;
2118                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2119                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2120                         return ECORE_UNKNOWN_ERROR;
2121
2122                 offset += *params.nvm_rd.buf_size;
2123                 bytes_left -= *params.nvm_rd.buf_size;
2124         }
2125
2126         return ECORE_SUCCESS;
2127 }
2128
2129 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2130                                              struct ecore_ptt *p_ptt,
2131                                              u32 port, u32 addr, u32 offset,
2132                                              u32 len, u8 *p_buf)
2133 {
2134         struct ecore_mcp_nvm_params params;
2135         enum _ecore_status_t rc;
2136         u32 buf_idx, buf_size;
2137
2138         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2139         params.nvm_common.offset =
2140                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2141                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2142         params.type = ECORE_MCP_NVM_WR;
2143         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2144         buf_idx = 0;
2145         while (buf_idx < len) {
2146                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2147                                       MAX_I2C_TRANSACTION_SIZE);
2148                 params.nvm_common.offset &=
2149                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2150                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2151                 params.nvm_common.offset |=
2152                         ((offset + buf_idx) <<
2153                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2154                 params.nvm_common.offset |=
2155                         (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2156                 params.nvm_wr.buf_size = buf_size;
2157                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2158                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2159                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2160                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2161                         return ECORE_NODEV;
2162                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2163                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2164                         return ECORE_UNKNOWN_ERROR;
2165
2166                 buf_idx += buf_size;
2167         }
2168
2169         return ECORE_SUCCESS;
2170 }
2171
2172 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2173                                          struct ecore_ptt *p_ptt,
2174                                          u16 gpio, u32 *gpio_val)
2175 {
2176         enum _ecore_status_t rc = ECORE_SUCCESS;
2177         u32 drv_mb_param = 0, rsp;
2178
2179         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2180
2181         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2182                            drv_mb_param, &rsp, gpio_val);
2183
2184         if (rc != ECORE_SUCCESS)
2185                 return rc;
2186
2187         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2188                 return ECORE_UNKNOWN_ERROR;
2189
2190         return ECORE_SUCCESS;
2191 }
2192
2193 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2194                                           struct ecore_ptt *p_ptt,
2195                                           u16 gpio, u16 gpio_val)
2196 {
2197         enum _ecore_status_t rc = ECORE_SUCCESS;
2198         u32 drv_mb_param = 0, param, rsp;
2199
2200         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2201                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2202
2203         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2204                            drv_mb_param, &rsp, &param);
2205
2206         if (rc != ECORE_SUCCESS)
2207                 return rc;
2208
2209         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2210                 return ECORE_UNKNOWN_ERROR;
2211
2212         return ECORE_SUCCESS;
2213 }
2214
2215 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2216                                          struct ecore_ptt *p_ptt,
2217                                          u16 gpio, u32 *gpio_direction,
2218                                          u32 *gpio_ctrl)
2219 {
2220         u32 drv_mb_param = 0, rsp, val = 0;
2221         enum _ecore_status_t rc = ECORE_SUCCESS;
2222
2223         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2224
2225         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2226                            drv_mb_param, &rsp, &val);
2227         if (rc != ECORE_SUCCESS)
2228                 return rc;
2229
2230         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2231                            DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2232         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2233                       DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2234
2235         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2236                 return ECORE_UNKNOWN_ERROR;
2237
2238         return ECORE_SUCCESS;
2239 }
2240
2241 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2242                                                   struct ecore_ptt *p_ptt)
2243 {
2244         u32 drv_mb_param = 0, rsp, param;
2245         enum _ecore_status_t rc = ECORE_SUCCESS;
2246
2247         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2248                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2249
2250         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2251                            drv_mb_param, &rsp, &param);
2252
2253         if (rc != ECORE_SUCCESS)
2254                 return rc;
2255
2256         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2257             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2258                 rc = ECORE_UNKNOWN_ERROR;
2259
2260         return rc;
2261 }
2262
2263 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2264                                                struct ecore_ptt *p_ptt)
2265 {
2266         u32 drv_mb_param, rsp, param;
2267         enum _ecore_status_t rc = ECORE_SUCCESS;
2268
2269         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2270                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2271
2272         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2273                            drv_mb_param, &rsp, &param);
2274
2275         if (rc != ECORE_SUCCESS)
2276                 return rc;
2277
2278         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2279             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2280                 rc = ECORE_UNKNOWN_ERROR;
2281
2282         return rc;
2283 }
2284
2285 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2286         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2287 {
2288         u32 drv_mb_param = 0, rsp;
2289         enum _ecore_status_t rc = ECORE_SUCCESS;
2290
2291         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2292                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2293
2294         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2295                            drv_mb_param, &rsp, num_images);
2296
2297         if (rc != ECORE_SUCCESS)
2298                 return rc;
2299
2300         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2301                 rc = ECORE_UNKNOWN_ERROR;
2302
2303         return rc;
2304 }
2305
2306 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2307         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2308         struct bist_nvm_image_att *p_image_att, u32 image_index)
2309 {
2310         struct ecore_mcp_nvm_params params;
2311         enum _ecore_status_t rc;
2312         u32 buf_size;
2313
2314         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2315         params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2316                                     DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2317         params.nvm_common.offset |= (image_index <<
2318                                     DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2319
2320         params.type = ECORE_MCP_NVM_RD;
2321         params.nvm_rd.buf_size = &buf_size;
2322         params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2323         params.nvm_rd.buf = (u32 *)p_image_att;
2324
2325         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2326         if (rc != ECORE_SUCCESS)
2327                 return rc;
2328
2329         if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2330             (p_image_att->return_code != 1))
2331                 rc = ECORE_UNKNOWN_ERROR;
2332
2333         return rc;
2334 }
2335
2336 enum _ecore_status_t
2337 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2338                                struct ecore_ptt *p_ptt,
2339                                struct ecore_temperature_info *p_temp_info)
2340 {
2341         struct ecore_temperature_sensor *p_temp_sensor;
2342         struct temperature_status_stc *p_mfw_temp_info;
2343         struct ecore_mcp_mb_params mb_params;
2344         union drv_union_data union_data;
2345         u32 val;
2346         enum _ecore_status_t rc;
2347         u8 i;
2348
2349         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2350         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2351         mb_params.p_data_dst = &union_data;
2352         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2353         if (rc != ECORE_SUCCESS)
2354                 return rc;
2355
2356         p_mfw_temp_info = &union_data.temp_info;
2357
2358         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2359         p_temp_info->num_sensors = OSAL_MIN_T(u32,
2360                                               p_mfw_temp_info->num_of_sensors,
2361                                               ECORE_MAX_NUM_OF_SENSORS);
2362         for (i = 0; i < p_temp_info->num_sensors; i++) {
2363                 val = p_mfw_temp_info->sensor[i];
2364                 p_temp_sensor = &p_temp_info->sensors[i];
2365                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2366                                                  SENSOR_LOCATION_SHIFT;
2367                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2368                                                 THRESHOLD_HIGH_SHIFT;
2369                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2370                                           CRITICAL_TEMPERATURE_SHIFT;
2371                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2372                                               CURRENT_TEMP_SHIFT;
2373         }
2374
2375         return ECORE_SUCCESS;
2376 }
2377
2378 enum _ecore_status_t ecore_mcp_get_mba_versions(
2379         struct ecore_hwfn *p_hwfn,
2380         struct ecore_ptt *p_ptt,
2381         struct ecore_mba_vers *p_mba_vers)
2382 {
2383         struct ecore_mcp_nvm_params params;
2384         enum _ecore_status_t rc;
2385         u32 buf_size;
2386
2387         OSAL_MEM_ZERO(&params, sizeof(params));
2388         params.type = ECORE_MCP_NVM_RD;
2389         params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2390         params.nvm_common.offset = 0;
2391         params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2392         params.nvm_rd.buf_size = &buf_size;
2393         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2394
2395         if (rc != ECORE_SUCCESS)
2396                 return rc;
2397
2398         if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2399             FW_MSG_CODE_NVM_OK)
2400                 rc = ECORE_UNKNOWN_ERROR;
2401
2402         if (buf_size != MCP_DRV_NVM_BUF_LEN)
2403                 rc = ECORE_UNKNOWN_ERROR;
2404
2405         return rc;
2406 }
2407
2408 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2409                                               struct ecore_ptt *p_ptt,
2410                                               u64 *num_events)
2411 {
2412         u32 rsp;
2413
2414         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2415                              0, &rsp, (u32 *)num_events);
2416 }
2417
2418 #define ECORE_RESC_ALLOC_VERSION_MAJOR  1
2419 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
2420 #define ECORE_RESC_ALLOC_VERSION                                \
2421         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
2422           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) |    \
2423          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
2424           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2425
2426 enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
2427                                              struct ecore_ptt *p_ptt,
2428                                              struct resource_info *p_resc_info,
2429                                              u32 *p_mcp_resp, u32 *p_mcp_param)
2430 {
2431         struct ecore_mcp_mb_params mb_params;
2432         union drv_union_data union_data;
2433         enum _ecore_status_t rc;
2434
2435         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2436         mb_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2437         mb_params.param = ECORE_RESC_ALLOC_VERSION;
2438         OSAL_MEMCPY(&union_data.resource, p_resc_info, sizeof(*p_resc_info));
2439         mb_params.p_data_src = &union_data;
2440         mb_params.p_data_dst = &union_data;
2441         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2442         if (rc != ECORE_SUCCESS)
2443                 return rc;
2444
2445         *p_mcp_resp = mb_params.mcp_resp;
2446         *p_mcp_param = mb_params.mcp_param;
2447
2448         OSAL_MEMCPY(p_resc_info, &union_data.resource, sizeof(*p_resc_info));
2449
2450         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2451                    "MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x,"
2452                    " offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n",
2453                    *p_mcp_param, p_resc_info->res_id, p_resc_info->size,
2454                    p_resc_info->offset, p_resc_info->vf_size,
2455                    p_resc_info->vf_offset, p_resc_info->flags);
2456
2457         return ECORE_SUCCESS;
2458 }
2459
2460 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
2461                                                struct ecore_ptt *p_ptt)
2462 {
2463         u32 mcp_resp, mcp_param;
2464
2465         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2466                              &mcp_resp, &mcp_param);
2467 }