2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #define __ETH_COMMON__
11 /********************/
12 /* ETH FW CONSTANTS */
13 /********************/
14 #define ETH_CACHE_LINE_SIZE 64
15 #define ETH_RX_CQE_GAP 32
16 #define ETH_MAX_RAMROD_PER_CON 8
17 #define ETH_TX_BD_PAGE_SIZE_BYTES 4096
18 #define ETH_RX_BD_PAGE_SIZE_BYTES 4096
19 #define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
20 #define ETH_RX_NUM_NEXT_PAGE_BDS 2
22 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
23 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
24 #define ETH_TX_MAX_LSO_HDR_NBD 4
25 #define ETH_TX_MIN_BDS_PER_LSO_PKT 3
26 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
27 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
28 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
29 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
30 #define ETH_TX_MAX_LSO_HDR_BYTES 510
31 #define ETH_TX_LSO_WINDOW_BDS_NUM 18
32 #define ETH_TX_LSO_WINDOW_MIN_LEN 9700
33 #define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFFFF
35 #define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
37 #define ETH_RX_MAX_BUFF_PER_PKT 5
39 /* num of MAC/VLAN filters */
40 #define ETH_NUM_MAC_FILTERS 512
41 #define ETH_NUM_VLAN_FILTERS 512
43 /* approx. multicast constants */
44 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
45 #define ETH_MULTICAST_MAC_BINS 256
46 #define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
48 /* ethernet vport update constants */
49 #define ETH_FILTER_RULES_COUNT 10
50 #define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
51 #define ETH_RSS_KEY_SIZE_REGS 10
52 #define ETH_RSS_ENGINE_NUM_K2 207
53 #define ETH_RSS_ENGINE_NUM_BB 127
56 #define ETH_TPA_MAX_AGGS_NUM 64
57 #define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
58 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
59 #define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
62 * Destination port mode
65 DEST_PORT_PHY /* Send to physical port. */,
66 DEST_PORT_LOOPBACK /* Send to loopback port. */,
67 DEST_PORT_PHY_LOOPBACK /* Send to physical and loopback port. */,
68 DEST_PORT_DROP /* Drop the packet in PBF. */,
73 * Ethernet address type
83 struct eth_tx_1st_bd_flags {
85 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
86 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
87 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
88 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
89 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
90 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
91 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
92 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
93 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
94 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
95 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
96 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
97 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
98 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
99 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
100 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
104 * The parsing information data for the first tx bd of a given packet.
106 struct eth_tx_data_1st_bd {
107 __le16 vlan /* VLAN to insert to packet (if needed). */;
108 /* Number of BDs in packet. Should be at least 2 in non-LSO
109 * packet and at least 3 in LSO (or Tunnel with IPv6+ext) packet.
112 struct eth_tx_1st_bd_flags bd_flags;
114 #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_MASK 0x1
115 #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT 0
116 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
117 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
118 #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_MASK 0x3FFF
119 #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_SHIFT 2
123 * The parsing information data for the second tx bd of a given packet.
125 struct eth_tx_data_2nd_bd {
128 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
129 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
130 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
131 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
132 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
133 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
134 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
135 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
136 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
137 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
138 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
139 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
140 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
141 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
142 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
143 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
144 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
145 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
146 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
147 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
149 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
150 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
151 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
152 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
156 * Firmware data for L2-EDPM packet.
158 struct eth_edpm_fw_data {
159 struct eth_tx_data_1st_bd data_1st_bd
160 /* Parsing information data from the 1st BD. */;
161 struct eth_tx_data_2nd_bd data_2nd_bd
162 /* Parsing information data from the 2nd BD. */;
169 struct eth_fast_path_cqe_fw_debug {
170 u8 reserved0 /* FW reserved. */;
171 u8 reserved1 /* FW reserved. */;
172 __le16 reserved2 /* FW reserved. */;
175 struct tunnel_parsing_flags {
177 #define TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
178 #define TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
179 #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
180 #define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
181 #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
182 #define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
183 #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
184 #define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
185 #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
186 #define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
187 #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
188 #define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
192 * Regular ETH Rx FP CQE.
194 struct eth_fast_path_rx_reg_cqe {
195 u8 type /* CQE type */;
197 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
198 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
199 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
200 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
201 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
202 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
203 __le16 pkt_len /* Total packet length (from the parser) */;
204 struct parsing_and_err_flags pars_flags
205 /* Parsing and error flags from the parser */;
206 __le16 vlan_tag /* 802.1q VLAN tag */;
207 __le32 rss_hash /* RSS hash result */;
208 __le16 len_on_first_bd /* Number of bytes placed on first BD */;
209 u8 placement_offset /* Offset of placement from BD start */;
210 struct tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */
212 u8 bd_num /* Number of BDs, used for packet */;
214 struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
217 #define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1
218 #define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0
219 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1
220 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1
221 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F
222 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2
226 * TPA-continue ETH Rx FP CQE.
228 struct eth_fast_path_rx_tpa_cont_cqe {
229 u8 type /* CQE type */;
230 u8 tpa_agg_index /* TPA aggregation index */;
231 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]
232 /* List of the segment sizes */;
234 u8 reserved1 /* FW reserved. */;
235 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE] /* FW reserved. */;
239 * TPA-end ETH Rx FP CQE .
241 struct eth_fast_path_rx_tpa_end_cqe {
242 u8 type /* CQE type */;
243 u8 tpa_agg_index /* TPA aggregation index */;
244 __le16 total_packet_len /* Total aggregated packet length */;
245 u8 num_of_bds /* Total number of BDs comprising the packet */;
246 u8 end_reason /* Aggregation end reason. Use enum eth_tpa_end_reason */
248 __le16 num_of_coalesced_segs /* Number of coalesced TCP segments */;
249 __le32 ts_delta /* TCP timestamp delta */;
250 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE]
251 /* List of the segment sizes */;
253 u8 reserved2 /* FW reserved. */;
254 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE] /* FW reserved. */;
258 * TPA-start ETH Rx FP CQE.
260 struct eth_fast_path_rx_tpa_start_cqe {
261 u8 type /* CQE type */;
263 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
264 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
265 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
266 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
267 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
268 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
269 __le16 seg_len /* Segment length (packetLen from the parser) */;
270 struct parsing_and_err_flags pars_flags
271 /* Parsing and error flags from the parser */;
272 __le16 vlan_tag /* 802.1q VLAN tag */;
273 __le32 rss_hash /* RSS hash result */;
274 __le16 len_on_first_bd /* Number of bytes placed on first BD */;
275 u8 placement_offset /* Offset of placement from BD start */;
276 struct tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */
278 u8 tpa_agg_index /* TPA aggregation index */;
279 u8 header_len /* Packet L2+L3+L4 header length */;
280 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE]
281 /* Additional BDs length list. */;
282 struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
286 * The L4 pseudo checksum mode for Ethernet
288 enum eth_l4_pseudo_checksum_mode {
289 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH
290 /* Pseudo Header checksum on packet is calculated
291 * with the correct packet length field.
294 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH
295 /* Pseudo Hdr checksum on packet is calc with zero len field. */
297 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
301 struct regpair addr /* single continues buffer */;
305 * regular ETH Rx SP CQE
307 struct eth_slow_path_rx_cqe {
308 u8 type /* CQE type */;
315 #define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1
316 #define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0
317 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1
318 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
319 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F
320 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2
324 * union for all ETH Rx CQE types
327 struct eth_fast_path_rx_reg_cqe fast_path_regular /* Regular FP CQE */;
328 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start
330 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont
331 /* TPA-continue CQE */;
332 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end /* TPA-end CQE */
334 struct eth_slow_path_rx_cqe slow_path /* SP CQE */;
340 enum eth_rx_cqe_type {
341 ETH_RX_CQE_TYPE_UNUSED,
342 ETH_RX_CQE_TYPE_REGULAR /* Regular FP ETH Rx CQE */,
343 ETH_RX_CQE_TYPE_SLOW_PATH /* Slow path ETH Rx CQE */,
344 ETH_RX_CQE_TYPE_TPA_START /* TPA start ETH Rx CQE */,
345 ETH_RX_CQE_TYPE_TPA_CONT /* TPA Continue ETH Rx CQE */,
346 ETH_RX_CQE_TYPE_TPA_END /* TPA end ETH Rx CQE */,
351 * Wrapp for PD RX CQE used in order to cover full cache line when writing CQE
353 struct eth_rx_pmd_cqe {
354 union eth_rx_cqe cqe /* CQE data itself */;
355 u8 reserved[ETH_RX_CQE_GAP];
359 * Aggregation end reason.
361 enum eth_tpa_end_reason {
363 ETH_AGG_END_SP_UPDATE /* SP configuration update */,
365 /* Maximum aggregation length or maximum buffer number used. */,
367 /* TCP PSH flag or TCP payload length below continue threshold. */,
368 ETH_AGG_END_TIMEOUT /* Timeout expiration. */,
369 ETH_AGG_END_NOT_CONSISTENT,
370 ETH_AGG_END_OUT_OF_ORDER,
371 ETH_AGG_END_NON_TPA_SEG,
372 MAX_ETH_TPA_END_REASON
379 ETH_TUNN_GENEVE /* GENEVE Tunnel. */,
380 ETH_TUNN_TTAG /* T-Tag Tunnel. */,
381 ETH_TUNN_GRE /* GRE Tunnel. */,
382 ETH_TUNN_VXLAN /* VXLAN Tunnel. */,
387 * The first tx bd of a given packet
389 struct eth_tx_1st_bd {
390 struct regpair addr /* Single continuous buffer */;
391 __le16 nbytes /* Number of bytes in this BD. */;
392 struct eth_tx_data_1st_bd data /* Parsing information data. */;
396 * The second tx bd of a given packet
398 struct eth_tx_2nd_bd {
399 struct regpair addr /* Single continuous buffer */;
400 __le16 nbytes /* Number of bytes in this BD. */;
401 struct eth_tx_data_2nd_bd data /* Parsing information data. */;
405 * The parsing information data for the third tx bd of a given packet.
407 struct eth_tx_data_3rd_bd {
408 __le16 lso_mss /* For LSO packet - the MSS in bytes. */;
410 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
411 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
412 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
413 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
414 #define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
415 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
416 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
417 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
418 u8 tunn_l4_hdr_start_offset_w;
423 * The third tx bd of a given packet
425 struct eth_tx_3rd_bd {
426 struct regpair addr /* Single continuous buffer */;
427 __le16 nbytes /* Number of bytes in this BD. */;
428 struct eth_tx_data_3rd_bd data /* Parsing information data. */;
432 * Complementary information for the regular tx bd of a given packet.
434 struct eth_tx_data_bd {
437 #define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
438 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
439 #define ETH_TX_DATA_BD_START_BD_MASK 0x1
440 #define ETH_TX_DATA_BD_START_BD_SHIFT 8
441 #define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
442 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
447 * The common regular TX BD ring element
450 struct regpair addr /* Single continuous buffer */;
451 __le16 nbytes /* Number of bytes in this BD. */;
452 struct eth_tx_data_bd data /* Complementary information. */;
455 union eth_tx_bd_types {
456 struct eth_tx_1st_bd first_bd /* The first tx bd of a given packet */;
457 struct eth_tx_2nd_bd second_bd /* The second tx bd of a given packet */
459 struct eth_tx_3rd_bd third_bd /* The third tx bd of a given packet */;
460 struct eth_tx_bd reg_bd /* The common non-special bd */;
466 struct mstorm_eth_queue_zone {
467 struct eth_rx_prod_data rx_producers;
474 struct ystorm_eth_queue_zone {
475 struct coalescing_timeset int_coalescing_timeset
476 /* Tx interrupt coalescing TimeSet */;
485 #define ETH_DB_DATA_DEST_MASK 0x3
486 #define ETH_DB_DATA_DEST_SHIFT 0
487 #define ETH_DB_DATA_AGG_CMD_MASK 0x3
488 #define ETH_DB_DATA_AGG_CMD_SHIFT 2
489 #define ETH_DB_DATA_BYPASS_EN_MASK 0x1
490 #define ETH_DB_DATA_BYPASS_EN_SHIFT 4
491 #define ETH_DB_DATA_RESERVED_MASK 0x1
492 #define ETH_DB_DATA_RESERVED_SHIFT 5
493 #define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
494 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
499 #endif /* __ETH_COMMON__ */