drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 /* Globals */
  14 int qede_logtype_init;
  15 int qede_logtype_driver;
  16
  17 static const struct qed_eth_ops *qed_ops;
  18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  20
  21 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  22
  23 struct rte_qede_xstats_name_off {
  24         char name[RTE_ETH_XSTATS_NAME_SIZE];
  25         uint64_t offset;
  26 };
  27
  28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  29         {"rx_unicast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  31         {"rx_multicast_bytes",
  32                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  33         {"rx_broadcast_bytes",
  34                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  35         {"rx_unicast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  37         {"rx_multicast_packets",
  38                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  39         {"rx_broadcast_packets",
  40                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  41
  42         {"tx_unicast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  44         {"tx_multicast_bytes",
  45                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  46         {"tx_broadcast_bytes",
  47                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  48         {"tx_unicast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  50         {"tx_multicast_packets",
  51                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  52         {"tx_broadcast_packets",
  53                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  54
  55         {"rx_64_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  57         {"rx_65_to_127_byte_packets",
  58                 offsetof(struct ecore_eth_stats_common,
  59                          rx_65_to_127_byte_packets)},
  60         {"rx_128_to_255_byte_packets",
  61                 offsetof(struct ecore_eth_stats_common,
  62                          rx_128_to_255_byte_packets)},
  63         {"rx_256_to_511_byte_packets",
  64                 offsetof(struct ecore_eth_stats_common,
  65                          rx_256_to_511_byte_packets)},
  66         {"rx_512_to_1023_byte_packets",
  67                 offsetof(struct ecore_eth_stats_common,
  68                          rx_512_to_1023_byte_packets)},
  69         {"rx_1024_to_1518_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          rx_1024_to_1518_byte_packets)},
  72         {"tx_64_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  74         {"tx_65_to_127_byte_packets",
  75                 offsetof(struct ecore_eth_stats_common,
  76                          tx_65_to_127_byte_packets)},
  77         {"tx_128_to_255_byte_packets",
  78                 offsetof(struct ecore_eth_stats_common,
  79                          tx_128_to_255_byte_packets)},
  80         {"tx_256_to_511_byte_packets",
  81                 offsetof(struct ecore_eth_stats_common,
  82                          tx_256_to_511_byte_packets)},
  83         {"tx_512_to_1023_byte_packets",
  84                 offsetof(struct ecore_eth_stats_common,
  85                          tx_512_to_1023_byte_packets)},
  86         {"tx_1024_to_1518_byte_packets",
  87                 offsetof(struct ecore_eth_stats_common,
  88                          tx_1024_to_1518_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  96         {"tx_pause_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  98         {"rx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 100         {"tx_priority_flow_control_frames",
 101                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 102
 103         {"rx_crc_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 105         {"rx_align_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 107         {"rx_carrier_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 109         {"rx_oversize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 111         {"rx_jabber_errors",
 112                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 113         {"rx_undersize_packet_errors",
 114                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 115         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 116         {"rx_host_buffer_not_available",
 117                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 118         /* Number of packets discarded because they are bigger than MTU */
 119         {"rx_packet_too_big_discards",
 120                 offsetof(struct ecore_eth_stats_common,
 121                          packet_too_big_discard)},
 122         {"rx_ttl_zero_discards",
 123                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 124         {"rx_multi_function_tag_filter_discards",
 125                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 126         {"rx_mac_filter_discards",
 127                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 128         {"rx_gft_filter_drop",
 129                 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
 130         {"rx_hw_buffer_truncates",
 131                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 132         {"rx_hw_buffer_discards",
 133                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 134         {"tx_error_drop_packets",
 135                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 136
 137         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 138         {"rx_mac_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 140         {"rx_mac_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 142         {"rx_mac_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 144         {"rx_mac_frames_ok",
 145                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 146         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 147         {"tx_mac_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 149         {"tx_mac_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 151         {"tx_mac_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 153
 154         {"lro_coalesced_packets",
 155                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 156         {"lro_coalesced_events",
 157                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 158         {"lro_aborts_num",
 159                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 160         {"lro_not_coalesced_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          tpa_not_coalesced_pkts)},
 163         {"lro_coalesced_bytes",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          tpa_coalesced_bytes)},
 166 };
 167
 168 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 169         {"rx_1519_to_1522_byte_packets",
 170                 offsetof(struct ecore_eth_stats, bb) +
 171                 offsetof(struct ecore_eth_stats_bb,
 172                          rx_1519_to_1522_byte_packets)},
 173         {"rx_1519_to_2047_byte_packets",
 174                 offsetof(struct ecore_eth_stats, bb) +
 175                 offsetof(struct ecore_eth_stats_bb,
 176                          rx_1519_to_2047_byte_packets)},
 177         {"rx_2048_to_4095_byte_packets",
 178                 offsetof(struct ecore_eth_stats, bb) +
 179                 offsetof(struct ecore_eth_stats_bb,
 180                          rx_2048_to_4095_byte_packets)},
 181         {"rx_4096_to_9216_byte_packets",
 182                 offsetof(struct ecore_eth_stats, bb) +
 183                 offsetof(struct ecore_eth_stats_bb,
 184                          rx_4096_to_9216_byte_packets)},
 185         {"rx_9217_to_16383_byte_packets",
 186                 offsetof(struct ecore_eth_stats, bb) +
 187                 offsetof(struct ecore_eth_stats_bb,
 188                          rx_9217_to_16383_byte_packets)},
 189
 190         {"tx_1519_to_2047_byte_packets",
 191                 offsetof(struct ecore_eth_stats, bb) +
 192                 offsetof(struct ecore_eth_stats_bb,
 193                          tx_1519_to_2047_byte_packets)},
 194         {"tx_2048_to_4095_byte_packets",
 195                 offsetof(struct ecore_eth_stats, bb) +
 196                 offsetof(struct ecore_eth_stats_bb,
 197                          tx_2048_to_4095_byte_packets)},
 198         {"tx_4096_to_9216_byte_packets",
 199                 offsetof(struct ecore_eth_stats, bb) +
 200                 offsetof(struct ecore_eth_stats_bb,
 201                          tx_4096_to_9216_byte_packets)},
 202         {"tx_9217_to_16383_byte_packets",
 203                 offsetof(struct ecore_eth_stats, bb) +
 204                 offsetof(struct ecore_eth_stats_bb,
 205                          tx_9217_to_16383_byte_packets)},
 206
 207         {"tx_lpi_entry_count",
 208                 offsetof(struct ecore_eth_stats, bb) +
 209                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 210         {"tx_total_collisions",
 211                 offsetof(struct ecore_eth_stats, bb) +
 212                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 213 };
 214
 215 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 216         {"rx_1519_to_max_byte_packets",
 217                 offsetof(struct ecore_eth_stats, ah) +
 218                 offsetof(struct ecore_eth_stats_ah,
 219                          rx_1519_to_max_byte_packets)},
 220         {"tx_1519_to_max_byte_packets",
 221                 offsetof(struct ecore_eth_stats, ah) +
 222                 offsetof(struct ecore_eth_stats_ah,
 223                          tx_1519_to_max_byte_packets)},
 224 };
 225
 226 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 227         {"rx_q_segments",
 228                 offsetof(struct qede_rx_queue, rx_segs)},
 229         {"rx_q_hw_errors",
 230                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 231         {"rx_q_allocation_errors",
 232                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 233 };
 234
 235 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 236 {
 237         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 238 }
 239
 240 static void
 241 qede_interrupt_handler_intx(void *param)
 242 {
 243         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 244         struct qede_dev *qdev = eth_dev->data->dev_private;
 245         struct ecore_dev *edev = &qdev->edev;
 246         u64 status;
 247
 248         /* Check if our device actually raised an interrupt */
 249         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 250         if (status & 0x1) {
 251                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 252
 253                 if (rte_intr_ack(eth_dev->intr_handle))
 254                         DP_ERR(edev, "rte_intr_ack failed\n");
 255         }
 256 }
 257
 258 static void
 259 qede_interrupt_handler(void *param)
 260 {
 261         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 262         struct qede_dev *qdev = eth_dev->data->dev_private;
 263         struct ecore_dev *edev = &qdev->edev;
 264
 265         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 266         if (rte_intr_ack(eth_dev->intr_handle))
 267                 DP_ERR(edev, "rte_intr_ack failed\n");
 268 }
 269
 270 static void
 271 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 272 {
 273         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 274         qdev->ops = qed_ops;
 275 }
 276
 277 static void qede_print_adapter_info(struct qede_dev *qdev)
 278 {
 279         struct ecore_dev *edev = &qdev->edev;
 280         struct qed_dev_info *info = &qdev->dev_info.common;
 281         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 282
 283         DP_INFO(edev, "**************************************************\n");
 284         DP_INFO(edev, " DPDK version\t\t\t: %s\n", rte_version());
 285         DP_INFO(edev, " Chip details\t\t\t: %s %c%d\n",
 286                   ECORE_IS_BB(edev) ? "BB" : "AH",
 287                   'A' + edev->chip_rev,
 288                   (int)edev->chip_metal);
 289         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 290                  QEDE_PMD_DRV_VERSION);
 291         DP_INFO(edev, " Driver version\t\t\t: %s\n", ver_str);
 292
 293         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 294                  QEDE_PMD_BASE_VERSION);
 295         DP_INFO(edev, " Base version\t\t\t: %s\n", ver_str);
 296
 297         if (!IS_VF(edev))
 298                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 299                          QEDE_PMD_FW_VERSION);
 300         else
 301                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 302                          info->fw_major, info->fw_minor,
 303                          info->fw_rev, info->fw_eng);
 304         DP_INFO(edev, " Firmware version\t\t\t: %s\n", ver_str);
 305
 306         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 307                  "%d.%d.%d.%d",
 308                  (info->mfw_rev & QED_MFW_VERSION_3_MASK) >>
 309                  QED_MFW_VERSION_3_OFFSET,
 310                  (info->mfw_rev & QED_MFW_VERSION_2_MASK) >>
 311                  QED_MFW_VERSION_2_OFFSET,
 312                  (info->mfw_rev & QED_MFW_VERSION_1_MASK) >>
 313                  QED_MFW_VERSION_1_OFFSET,
 314                  (info->mfw_rev & QED_MFW_VERSION_0_MASK) >>
 315                  QED_MFW_VERSION_0_OFFSET);
 316         DP_INFO(edev, " Management Firmware version\t: %s\n", ver_str);
 317         DP_INFO(edev, " Firmware file\t\t\t: %s\n", qede_fw_file);
 318         DP_INFO(edev, "**************************************************\n");
 319 }
 320
 321 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 322 {
 323         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 324         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 325         unsigned int i = 0, j = 0, qid;
 326         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 327         struct qede_tx_queue *txq;
 328
 329         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 330
 331         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 332                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 333         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 334                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 335
 336         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 337                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 338                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 339                             sizeof(uint64_t));
 340                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 341                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 342                             sizeof(uint64_t));
 343                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 344                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 345                             sizeof(uint64_t));
 346
 347                 if (xstats)
 348                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 349                                 OSAL_MEMSET((((char *)
 350                                               (qdev->fp_array[qid].rxq)) +
 351                                              qede_rxq_xstats_strings[j].offset),
 352                                             0,
 353                                             sizeof(uint64_t));
 354
 355                 i++;
 356                 if (i == rxq_stat_cntrs)
 357                         break;
 358         }
 359
 360         i = 0;
 361
 362         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 363                 txq = qdev->fp_array[qid].txq;
 364
 365                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 366                                 (((uint64_t)(uintptr_t)(txq)) +
 367                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 368                             sizeof(uint64_t));
 369
 370                 i++;
 371                 if (i == txq_stat_cntrs)
 372                         break;
 373         }
 374 }
 375
 376 static int
 377 qede_stop_vport(struct ecore_dev *edev)
 378 {
 379         struct ecore_hwfn *p_hwfn;
 380         uint8_t vport_id;
 381         int rc;
 382         int i;
 383
 384         vport_id = 0;
 385         for_each_hwfn(edev, i) {
 386                 p_hwfn = &edev->hwfns[i];
 387                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 388                                          vport_id);
 389                 if (rc != ECORE_SUCCESS) {
 390                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 391                         return rc;
 392                 }
 393         }
 394
 395         DP_INFO(edev, "vport stopped\n");
 396
 397         return 0;
 398 }
 399
 400 static int
 401 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 402 {
 403         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 404         struct ecore_sp_vport_start_params params;
 405         struct ecore_hwfn *p_hwfn;
 406         int rc;
 407         int i;
 408
 409         if (qdev->vport_started)
 410                 qede_stop_vport(edev);
 411
 412         memset(&params, 0, sizeof(params));
 413         params.vport_id = 0;
 414         params.mtu = mtu;
 415         /* @DPDK - Disable FW placement */
 416         params.zero_placement_offset = 1;
 417         for_each_hwfn(edev, i) {
 418                 p_hwfn = &edev->hwfns[i];
 419                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 420                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 421                 rc = ecore_sp_vport_start(p_hwfn, &params);
 422                 if (rc != ECORE_SUCCESS) {
 423                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 424                         return rc;
 425                 }
 426         }
 427         ecore_reset_vport_stats(edev);
 428         qdev->vport_started = true;
 429         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 430
 431         return 0;
 432 }
 433
 434 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 435 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 436
 437 /* Activate or deactivate vport via vport-update */
 438 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 439 {
 440         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 441         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 442         struct ecore_sp_vport_update_params params;
 443         struct ecore_hwfn *p_hwfn;
 444         uint8_t i;
 445         int rc = -1;
 446
 447         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 448         params.vport_id = 0;
 449         params.update_vport_active_rx_flg = 1;
 450         params.update_vport_active_tx_flg = 1;
 451         params.vport_active_rx_flg = flg;
 452         params.vport_active_tx_flg = flg;
 453         if (~qdev->enable_tx_switching & flg) {
 454                 params.update_tx_switching_flg = 1;
 455                 params.tx_switching_flg = !flg;
 456         }
 457         for_each_hwfn(edev, i) {
 458                 p_hwfn = &edev->hwfns[i];
 459                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 460                 rc = ecore_sp_vport_update(p_hwfn, &params,
 461                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 462                 if (rc != ECORE_SUCCESS) {
 463                         DP_ERR(edev, "Failed to update vport\n");
 464                         break;
 465                 }
 466         }
 467         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 468
 469         return rc;
 470 }
 471
 472 static void
 473 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 474                            uint16_t mtu, bool enable)
 475 {
 476         /* Enable LRO in split mode */
 477         sge_tpa_params->tpa_ipv4_en_flg = enable;
 478         sge_tpa_params->tpa_ipv6_en_flg = enable;
 479         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 480         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 481         /* set if tpa enable changes */
 482         sge_tpa_params->update_tpa_en_flg = 1;
 483         /* set if tpa parameters should be handled */
 484         sge_tpa_params->update_tpa_param_flg = enable;
 485
 486         sge_tpa_params->max_buffers_per_cqe = 20;
 487         /* Enable TPA in split mode. In this mode each TPA segment
 488          * starts on the new BD, so there is one BD per segment.
 489          */
 490         sge_tpa_params->tpa_pkt_split_flg = 1;
 491         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 492         sge_tpa_params->tpa_gro_consistent_flg = 0;
 493         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 494         sge_tpa_params->tpa_max_size = 0x7FFF;
 495         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 496         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 497 }
 498
 499 /* Enable/disable LRO via vport-update */
 500 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 501 {
 502         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 503         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 504         struct ecore_sp_vport_update_params params;
 505         struct ecore_sge_tpa_params tpa_params;
 506         struct ecore_hwfn *p_hwfn;
 507         int rc;
 508         int i;
 509
 510         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 511         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 512         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 513         params.vport_id = 0;
 514         params.sge_tpa_params = &tpa_params;
 515         for_each_hwfn(edev, i) {
 516                 p_hwfn = &edev->hwfns[i];
 517                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 518                 rc = ecore_sp_vport_update(p_hwfn, &params,
 519                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 520                 if (rc != ECORE_SUCCESS) {
 521                         DP_ERR(edev, "Failed to update LRO\n");
 522                         return -1;
 523                 }
 524         }
 525         qdev->enable_lro = flg;
 526         eth_dev->data->lro = flg;
 527
 528         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 529
 530         return 0;
 531 }
 532
 533 static int
 534 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 535                              enum qed_filter_rx_mode_type type)
 536 {
 537         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 538         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 539         struct ecore_filter_accept_flags flags;
 540
 541         memset(&flags, 0, sizeof(flags));
 542
 543         flags.update_rx_mode_config = 1;
 544         flags.update_tx_mode_config = 1;
 545         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 546                 ECORE_ACCEPT_MCAST_MATCHED |
 547                 ECORE_ACCEPT_BCAST;
 548
 549         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 550                 ECORE_ACCEPT_MCAST_MATCHED |
 551                 ECORE_ACCEPT_BCAST;
 552
 553         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 554                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 555                 if (IS_VF(edev)) {
 556                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 557                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 558                 }
 559         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 560                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 561         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 562                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 563                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 564                         ECORE_ACCEPT_MCAST_UNMATCHED;
 565         }
 566
 567         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 568                         ECORE_SPQ_MODE_CB, NULL);
 569 }
 570
 571 int
 572 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 573                   bool add)
 574 {
 575         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 576         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 577         struct qede_ucast_entry *tmp = NULL;
 578         struct qede_ucast_entry *u;
 579         struct rte_ether_addr *mac_addr;
 580
 581         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 582         if (add) {
 583                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 584                         if ((memcmp(mac_addr, &tmp->mac,
 585                                     RTE_ETHER_ADDR_LEN) == 0) &&
 586                              ucast->vni == tmp->vni &&
 587                              ucast->vlan == tmp->vlan) {
 588                                 DP_INFO(edev, "Unicast MAC is already added"
 589                                         " with vlan = %u, vni = %u\n",
 590                                         ucast->vlan,  ucast->vni);
 591                                         return 0;
 592                         }
 593                 }
 594                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 595                                RTE_CACHE_LINE_SIZE);
 596                 if (!u) {
 597                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 598                         return -ENOMEM;
 599                 }
 600                 rte_ether_addr_copy(mac_addr, &u->mac);
 601                 u->vlan = ucast->vlan;
 602                 u->vni = ucast->vni;
 603                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 604                 qdev->num_uc_addr++;
 605         } else {
 606                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 607                         if ((memcmp(mac_addr, &tmp->mac,
 608                                     RTE_ETHER_ADDR_LEN) == 0) &&
 609                             ucast->vlan == tmp->vlan      &&
 610                             ucast->vni == tmp->vni)
 611                         break;
 612                 }
 613                 if (tmp == NULL) {
 614                         DP_INFO(edev, "Unicast MAC is not found\n");
 615                         return -EINVAL;
 616                 }
 617                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 618                 qdev->num_uc_addr--;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static int
 625 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 626                 struct rte_ether_addr *mc_addrs,
 627                 uint32_t mc_addrs_num)
 628 {
 629         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 630         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 631         struct ecore_filter_mcast mcast;
 632         struct qede_mcast_entry *m = NULL;
 633         uint8_t i;
 634         int rc;
 635
 636         for (i = 0; i < mc_addrs_num; i++) {
 637                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 638                                RTE_CACHE_LINE_SIZE);
 639                 if (!m) {
 640                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 641                         return -ENOMEM;
 642                 }
 643                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 644                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 645         }
 646         memset(&mcast, 0, sizeof(mcast));
 647         mcast.num_mc_addrs = mc_addrs_num;
 648         mcast.opcode = ECORE_FILTER_ADD;
 649         for (i = 0; i < mc_addrs_num; i++)
 650                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 651                                                         &mcast.mac[i]);
 652         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 653         if (rc != ECORE_SUCCESS) {
 654                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 655                 return -1;
 656         }
 657
 658         return 0;
 659 }
 660
 661 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 662 {
 663         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 664         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 665         struct qede_mcast_entry *tmp = NULL;
 666         struct ecore_filter_mcast mcast;
 667         int j;
 668         int rc;
 669
 670         memset(&mcast, 0, sizeof(mcast));
 671         mcast.num_mc_addrs = qdev->num_mc_addr;
 672         mcast.opcode = ECORE_FILTER_REMOVE;
 673         j = 0;
 674         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 675                 rte_ether_addr_copy(&tmp->mac,
 676                                 (struct rte_ether_addr *)&mcast.mac[j]);
 677                 j++;
 678         }
 679         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 680         if (rc != ECORE_SUCCESS) {
 681                 DP_ERR(edev, "Failed to delete multicast filter\n");
 682                 return -1;
 683         }
 684         /* Init the list */
 685         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 686                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 687                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 688         }
 689         SLIST_INIT(&qdev->mc_list_head);
 690
 691         return 0;
 692 }
 693
 694 enum _ecore_status_t
 695 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 696                  bool add)
 697 {
 698         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 699         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 700         enum _ecore_status_t rc = ECORE_INVAL;
 701
 702         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 703                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 704                               " Please enable promisc mode\n");
 705                         return ECORE_INVAL;
 706         }
 707
 708         rc = qede_ucast_filter(eth_dev, ucast, add);
 709         if (rc == 0)
 710                 rc = ecore_filter_ucast_cmd(edev, ucast,
 711                                             ECORE_SPQ_MODE_CB, NULL);
 712         /* Indicate error only for add filter operation.
 713          * Delete filter operations are not severe.
 714          */
 715         if ((rc != ECORE_SUCCESS) && add)
 716                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 717                        rc, add);
 718
 719         return rc;
 720 }
 721
 722 static int
 723 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 724                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 725 {
 726         struct ecore_filter_ucast ucast;
 727         int re;
 728
 729         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 730                 return -EINVAL;
 731
 732         qede_set_ucast_cmn_params(&ucast);
 733         ucast.opcode = ECORE_FILTER_ADD;
 734         ucast.type = ECORE_FILTER_MAC;
 735         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 736         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 737         return re;
 738 }
 739
 740 static void
 741 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 742 {
 743         struct qede_dev *qdev = eth_dev->data->dev_private;
 744         struct ecore_dev *edev = &qdev->edev;
 745         struct ecore_filter_ucast ucast;
 746
 747         PMD_INIT_FUNC_TRACE(edev);
 748
 749         if (index >= qdev->dev_info.num_mac_filters) {
 750                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 751                        index, qdev->dev_info.num_mac_filters);
 752                 return;
 753         }
 754
 755         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 756                 return;
 757
 758         qede_set_ucast_cmn_params(&ucast);
 759         ucast.opcode = ECORE_FILTER_REMOVE;
 760         ucast.type = ECORE_FILTER_MAC;
 761
 762         /* Use the index maintained by rte */
 763         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 764                         (struct rte_ether_addr *)&ucast.mac);
 765
 766         qede_mac_int_ops(eth_dev, &ucast, false);
 767 }
 768
 769 static int
 770 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 771 {
 772         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 773         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 774
 775         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 776                                                mac_addr->addr_bytes)) {
 777                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 778                 return -EPERM;
 779         }
 780
 781         qede_mac_addr_remove(eth_dev, 0);
 782
 783         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 784 }
 785
 786 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 787 {
 788         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 789         struct ecore_sp_vport_update_params params;
 790         struct ecore_hwfn *p_hwfn;
 791         uint8_t i;
 792         int rc;
 793
 794         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 795         params.vport_id = 0;
 796         params.update_accept_any_vlan_flg = 1;
 797         params.accept_any_vlan = flg;
 798         for_each_hwfn(edev, i) {
 799                 p_hwfn = &edev->hwfns[i];
 800                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 801                 rc = ecore_sp_vport_update(p_hwfn, &params,
 802                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 803                 if (rc != ECORE_SUCCESS) {
 804                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 805                         return;
 806                 }
 807         }
 808
 809         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 810 }
 811
 812 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 813 {
 814         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 815         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 816         struct ecore_sp_vport_update_params params;
 817         struct ecore_hwfn *p_hwfn;
 818         uint8_t i;
 819         int rc;
 820
 821         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 822         params.vport_id = 0;
 823         params.update_inner_vlan_removal_flg = 1;
 824         params.inner_vlan_removal_flg = flg;
 825         for_each_hwfn(edev, i) {
 826                 p_hwfn = &edev->hwfns[i];
 827                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 828                 rc = ecore_sp_vport_update(p_hwfn, &params,
 829                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 830                 if (rc != ECORE_SUCCESS) {
 831                         DP_ERR(edev, "Failed to update vport\n");
 832                         return -1;
 833                 }
 834         }
 835
 836         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 837         return 0;
 838 }
 839
 840 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 841                                 uint16_t vlan_id, int on)
 842 {
 843         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 844         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 845         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 846         struct qede_vlan_entry *tmp = NULL;
 847         struct qede_vlan_entry *vlan;
 848         struct ecore_filter_ucast ucast;
 849         int rc;
 850
 851         if (on) {
 852                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 853                         DP_ERR(edev, "Reached max VLAN filter limit"
 854                                       " enabling accept_any_vlan\n");
 855                         qede_config_accept_any_vlan(qdev, true);
 856                         return 0;
 857                 }
 858
 859                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 860                         if (tmp->vid == vlan_id) {
 861                                 DP_INFO(edev, "VLAN %u already configured\n",
 862                                         vlan_id);
 863                                 return 0;
 864                         }
 865                 }
 866
 867                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 868                                   RTE_CACHE_LINE_SIZE);
 869
 870                 if (!vlan) {
 871                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 872                         return -ENOMEM;
 873                 }
 874
 875                 qede_set_ucast_cmn_params(&ucast);
 876                 ucast.opcode = ECORE_FILTER_ADD;
 877                 ucast.type = ECORE_FILTER_VLAN;
 878                 ucast.vlan = vlan_id;
 879                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 880                                             NULL);
 881                 if (rc != 0) {
 882                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 883                                rc);
 884                         rte_free(vlan);
 885                 } else {
 886                         vlan->vid = vlan_id;
 887                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 888                         qdev->configured_vlans++;
 889                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 890                                 vlan_id, qdev->configured_vlans);
 891                 }
 892         } else {
 893                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 894                         if (tmp->vid == vlan_id)
 895                                 break;
 896                 }
 897
 898                 if (!tmp) {
 899                         if (qdev->configured_vlans == 0) {
 900                                 DP_INFO(edev,
 901                                         "No VLAN filters configured yet\n");
 902                                 return 0;
 903                         }
 904
 905                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 906                         return -EINVAL;
 907                 }
 908
 909                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 910
 911                 qede_set_ucast_cmn_params(&ucast);
 912                 ucast.opcode = ECORE_FILTER_REMOVE;
 913                 ucast.type = ECORE_FILTER_VLAN;
 914                 ucast.vlan = vlan_id;
 915                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 916                                             NULL);
 917                 if (rc != 0) {
 918                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 919                                vlan_id, rc);
 920                 } else {
 921                         qdev->configured_vlans--;
 922                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 923                                 vlan_id, qdev->configured_vlans);
 924                 }
 925         }
 926
 927         return rc;
 928 }
 929
 930 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 931 {
 932         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 933         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 934         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 935
 936         if (mask & ETH_VLAN_STRIP_MASK) {
 937                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 938                         (void)qede_vlan_stripping(eth_dev, 1);
 939                 else
 940                         (void)qede_vlan_stripping(eth_dev, 0);
 941         }
 942
 943         if (mask & ETH_VLAN_FILTER_MASK) {
 944                 /* VLAN filtering kicks in when a VLAN is added */
 945                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 946                         qede_vlan_filter_set(eth_dev, 0, 1);
 947                 } else {
 948                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 949                                 DP_ERR(edev,
 950                                   " Please remove existing VLAN filters"
 951                                   " before disabling VLAN filtering\n");
 952                                 /* Signal app that VLAN filtering is still
 953                                  * enabled
 954                                  */
 955                                 eth_dev->data->dev_conf.rxmode.offloads |=
 956                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
 957                         } else {
 958                                 qede_vlan_filter_set(eth_dev, 0, 0);
 959                         }
 960                 }
 961         }
 962
 963         if (mask & ETH_VLAN_EXTEND_MASK)
 964                 DP_ERR(edev, "Extend VLAN not supported\n");
 965
 966         qdev->vlan_offload_mask = mask;
 967
 968         DP_INFO(edev, "VLAN offload mask %d\n", mask);
 969
 970         return 0;
 971 }
 972
 973 static void qede_prandom_bytes(uint32_t *buff)
 974 {
 975         uint8_t i;
 976
 977         srand((unsigned int)time(NULL));
 978         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 979                 buff[i] = rand();
 980 }
 981
 982 int qede_config_rss(struct rte_eth_dev *eth_dev)
 983 {
 984         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 985         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 986         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 987         struct rte_eth_rss_reta_entry64 reta_conf[2];
 988         struct rte_eth_rss_conf rss_conf;
 989         uint32_t i, id, pos, q;
 990
 991         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 992         if (!rss_conf.rss_key) {
 993                 DP_INFO(edev, "Applying driver default key\n");
 994                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 995                 qede_prandom_bytes(&def_rss_key[0]);
 996                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 997         }
 998
 999         /* Configure RSS hash */
1000         if (qede_rss_hash_update(eth_dev, &rss_conf))
1001                 return -EINVAL;
1002
1003         /* Configure default RETA */
1004         memset(reta_conf, 0, sizeof(reta_conf));
1005         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1006                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1007
1008         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1009                 id = i / RTE_RETA_GROUP_SIZE;
1010                 pos = i % RTE_RETA_GROUP_SIZE;
1011                 q = i % QEDE_RSS_COUNT(eth_dev);
1012                 reta_conf[id].reta[pos] = q;
1013         }
1014         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1015                                  ECORE_RSS_IND_TABLE_SIZE))
1016                 return -EINVAL;
1017
1018         return 0;
1019 }
1020
1021 static void qede_fastpath_start(struct ecore_dev *edev)
1022 {
1023         struct ecore_hwfn *p_hwfn;
1024         int i;
1025
1026         for_each_hwfn(edev, i) {
1027                 p_hwfn = &edev->hwfns[i];
1028                 ecore_hw_start_fastpath(p_hwfn);
1029         }
1030 }
1031
1032 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1033 {
1034         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1035         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1036         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1037
1038         PMD_INIT_FUNC_TRACE(edev);
1039
1040         /* Update MTU only if it has changed */
1041         if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1042                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1043                         goto err;
1044                 qdev->mtu = qdev->new_mtu;
1045                 qdev->new_mtu = 0;
1046         }
1047
1048         /* Configure TPA parameters */
1049         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1050                 if (qede_enable_tpa(eth_dev, true))
1051                         return -EINVAL;
1052                 /* Enable scatter mode for LRO */
1053                 if (!eth_dev->data->scattered_rx)
1054                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1055         }
1056
1057         /* Start queues */
1058         if (qede_start_queues(eth_dev))
1059                 goto err;
1060
1061         if (IS_PF(edev))
1062                 qede_reset_queue_stats(qdev, true);
1063
1064         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1065          * enabling RSS. Hence RSS configuration is deferred upto this point.
1066          * Also, we would like to retain similar behavior in PF case, so we
1067          * don't do PF/VF specific check here.
1068          */
1069         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1070                 if (qede_config_rss(eth_dev))
1071                         goto err;
1072
1073         /* Enable vport*/
1074         if (qede_activate_vport(eth_dev, true))
1075                 goto err;
1076
1077         /* Update link status */
1078         qede_link_update(eth_dev, 0);
1079
1080         /* Start/resume traffic */
1081         qede_fastpath_start(edev);
1082
1083         DP_INFO(edev, "Device started\n");
1084
1085         return 0;
1086 err:
1087         DP_ERR(edev, "Device start fails\n");
1088         return -1; /* common error code is < 0 */
1089 }
1090
1091 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1092 {
1093         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1094         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1095
1096         PMD_INIT_FUNC_TRACE(edev);
1097
1098         /* Disable vport */
1099         if (qede_activate_vport(eth_dev, false))
1100                 return;
1101
1102         if (qdev->enable_lro)
1103                 qede_enable_tpa(eth_dev, false);
1104
1105         /* Stop queues */
1106         qede_stop_queues(eth_dev);
1107
1108         /* Disable traffic */
1109         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1110
1111         DP_INFO(edev, "Device is stopped\n");
1112 }
1113
1114 static const char * const valid_args[] = {
1115         QEDE_NPAR_TX_SWITCHING,
1116         QEDE_VF_TX_SWITCHING,
1117         NULL,
1118 };
1119
1120 static int qede_args_check(const char *key, const char *val, void *opaque)
1121 {
1122         unsigned long tmp;
1123         int ret = 0;
1124         struct rte_eth_dev *eth_dev = opaque;
1125         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1126         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1127
1128         errno = 0;
1129         tmp = strtoul(val, NULL, 0);
1130         if (errno) {
1131                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1132                 return errno;
1133         }
1134
1135         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1136             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1137                 qdev->enable_tx_switching = !!tmp;
1138                 DP_INFO(edev, "Disabling %s tx-switching\n",
1139                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1140                         "VF" : "NPAR");
1141         }
1142
1143         return ret;
1144 }
1145
1146 static int qede_args(struct rte_eth_dev *eth_dev)
1147 {
1148         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1149         struct rte_kvargs *kvlist;
1150         struct rte_devargs *devargs;
1151         int ret;
1152         int i;
1153
1154         devargs = pci_dev->device.devargs;
1155         if (!devargs)
1156                 return 0; /* return success */
1157
1158         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1159         if (kvlist == NULL)
1160                 return -EINVAL;
1161
1162          /* Process parameters. */
1163         for (i = 0; (valid_args[i] != NULL); ++i) {
1164                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1165                         ret = rte_kvargs_process(kvlist, valid_args[i],
1166                                                  qede_args_check, eth_dev);
1167                         if (ret != ECORE_SUCCESS) {
1168                                 rte_kvargs_free(kvlist);
1169                                 return ret;
1170                         }
1171                 }
1172         }
1173         rte_kvargs_free(kvlist);
1174
1175         return 0;
1176 }
1177
1178 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1179 {
1180         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1181         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1182         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1183         int ret;
1184
1185         PMD_INIT_FUNC_TRACE(edev);
1186
1187         /* We need to have min 1 RX queue.There is no min check in
1188          * rte_eth_dev_configure(), so we are checking it here.
1189          */
1190         if (eth_dev->data->nb_rx_queues == 0) {
1191                 DP_ERR(edev, "Minimum one RX queue is required\n");
1192                 return -EINVAL;
1193         }
1194
1195         /* Enable Tx switching by default */
1196         qdev->enable_tx_switching = 1;
1197
1198         /* Parse devargs and fix up rxmode */
1199         if (qede_args(eth_dev))
1200                 DP_NOTICE(edev, false,
1201                           "Invalid devargs supplied, requested change will not take effect\n");
1202
1203         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1204               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1205                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1206                 return -ENOTSUP;
1207         }
1208         /* Flow director mode check */
1209         if (qede_check_fdir_support(eth_dev))
1210                 return -ENOTSUP;
1211
1212         qede_dealloc_fp_resc(eth_dev);
1213         qdev->num_tx_queues = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1214         qdev->num_rx_queues = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1215
1216         if (qede_alloc_fp_resc(qdev))
1217                 return -ENOMEM;
1218
1219         /* If jumbo enabled adjust MTU */
1220         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1221                 eth_dev->data->mtu =
1222                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1223                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1224
1225         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1226                 eth_dev->data->scattered_rx = 1;
1227
1228         if (qede_start_vport(qdev, eth_dev->data->mtu))
1229                 return -1;
1230
1231         qdev->mtu = eth_dev->data->mtu;
1232
1233         /* Enable VLAN offloads by default */
1234         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1235                                              ETH_VLAN_FILTER_MASK);
1236         if (ret)
1237                 return ret;
1238
1239         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1240                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1241
1242         if (ECORE_IS_CMT(edev))
1243                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1244                         qdev->num_rx_queues, qdev->num_tx_queues);
1245
1246
1247         return 0;
1248 }
1249
1250 /* Info about HW descriptor ring limitations */
1251 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1252         .nb_max = 0x8000, /* 32K */
1253         .nb_min = 128,
1254         .nb_align = 128 /* lowest common multiple */
1255 };
1256
1257 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1258         .nb_max = 0x8000, /* 32K */
1259         .nb_min = 256,
1260         .nb_align = 256,
1261         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1262         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1263 };
1264
1265 static int
1266 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1267                   struct rte_eth_dev_info *dev_info)
1268 {
1269         struct qede_dev *qdev = eth_dev->data->dev_private;
1270         struct ecore_dev *edev = &qdev->edev;
1271         struct qed_link_output link;
1272         uint32_t speed_cap = 0;
1273
1274         PMD_INIT_FUNC_TRACE(edev);
1275
1276         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1277         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1278         dev_info->rx_desc_lim = qede_rx_desc_lim;
1279         dev_info->tx_desc_lim = qede_tx_desc_lim;
1280
1281         if (IS_PF(edev))
1282                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1283                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1284         else
1285                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1286                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1287         /* Since CMT mode internally doubles the number of queues */
1288         if (ECORE_IS_CMT(edev))
1289                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1290
1291         dev_info->max_tx_queues = dev_info->max_rx_queues;
1292
1293         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1294         dev_info->max_vfs = 0;
1295         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1296         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1297         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1298         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1299                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1300                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1301                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1302                                      DEV_RX_OFFLOAD_TCP_LRO     |
1303                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1304                                      DEV_RX_OFFLOAD_SCATTER     |
1305                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1306                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1307                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1308         dev_info->rx_queue_offload_capa = 0;
1309
1310         /* TX offloads are on a per-packet basis, so it is applicable
1311          * to both at port and queue levels.
1312          */
1313         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1314                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1315                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1316                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1317                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1318                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1319                                      DEV_TX_OFFLOAD_TCP_TSO     |
1320                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1321                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1322         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1323
1324         dev_info->default_txconf = (struct rte_eth_txconf) {
1325                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1326         };
1327
1328         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1329                 /* Packets are always dropped if no descriptors are available */
1330                 .rx_drop_en = 1,
1331                 .offloads = 0,
1332         };
1333
1334         memset(&link, 0, sizeof(struct qed_link_output));
1335         qdev->ops->common->get_link(edev, &link);
1336         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1337                 speed_cap |= ETH_LINK_SPEED_1G;
1338         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1339                 speed_cap |= ETH_LINK_SPEED_10G;
1340         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1341                 speed_cap |= ETH_LINK_SPEED_25G;
1342         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1343                 speed_cap |= ETH_LINK_SPEED_40G;
1344         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1345                 speed_cap |= ETH_LINK_SPEED_50G;
1346         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1347                 speed_cap |= ETH_LINK_SPEED_100G;
1348         dev_info->speed_capa = speed_cap;
1349
1350         return 0;
1351 }
1352
1353 /* return 0 means link status changed, -1 means not changed */
1354 int
1355 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1356 {
1357         struct qede_dev *qdev = eth_dev->data->dev_private;
1358         struct ecore_dev *edev = &qdev->edev;
1359         struct qed_link_output q_link;
1360         struct rte_eth_link link;
1361         uint16_t link_duplex;
1362
1363         memset(&q_link, 0, sizeof(q_link));
1364         memset(&link, 0, sizeof(link));
1365
1366         qdev->ops->common->get_link(edev, &q_link);
1367
1368         /* Link Speed */
1369         link.link_speed = q_link.speed;
1370
1371         /* Link Mode */
1372         switch (q_link.duplex) {
1373         case QEDE_DUPLEX_HALF:
1374                 link_duplex = ETH_LINK_HALF_DUPLEX;
1375                 break;
1376         case QEDE_DUPLEX_FULL:
1377                 link_duplex = ETH_LINK_FULL_DUPLEX;
1378                 break;
1379         case QEDE_DUPLEX_UNKNOWN:
1380         default:
1381                 link_duplex = -1;
1382         }
1383         link.link_duplex = link_duplex;
1384
1385         /* Link Status */
1386         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1387
1388         /* AN */
1389         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1390                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1391
1392         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1393                 link.link_speed, link.link_duplex,
1394                 link.link_autoneg, link.link_status);
1395
1396         return rte_eth_linkstatus_set(eth_dev, &link);
1397 }
1398
1399 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1400 {
1401         struct qede_dev *qdev = eth_dev->data->dev_private;
1402         struct ecore_dev *edev = &qdev->edev;
1403         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1404         enum _ecore_status_t ecore_status;
1405
1406         PMD_INIT_FUNC_TRACE(edev);
1407
1408         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1409                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1410
1411         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1412
1413         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1414 }
1415
1416 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1417 {
1418         struct qede_dev *qdev = eth_dev->data->dev_private;
1419         struct ecore_dev *edev = &qdev->edev;
1420         enum _ecore_status_t ecore_status;
1421
1422         PMD_INIT_FUNC_TRACE(edev);
1423
1424         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1425                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1426                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1427         else
1428                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1429                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1430
1431         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1432 }
1433
1434 static void qede_poll_sp_sb_cb(void *param)
1435 {
1436         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1437         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1438         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1439         int rc;
1440
1441         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1442         qede_interrupt_action(&edev->hwfns[1]);
1443
1444         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1445                                qede_poll_sp_sb_cb,
1446                                (void *)eth_dev);
1447         if (rc != 0) {
1448                 DP_ERR(edev, "Unable to start periodic"
1449                              " timer rc %d\n", rc);
1450         }
1451 }
1452
1453 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1454 {
1455         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1456         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1457         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1458
1459         PMD_INIT_FUNC_TRACE(edev);
1460
1461         /* dev_stop() shall cleanup fp resources in hw but without releasing
1462          * dma memories and sw structures so that dev_start() can be called
1463          * by the app without reconfiguration. However, in dev_close() we
1464          * can release all the resources and device can be brought up newly
1465          */
1466         if (eth_dev->data->dev_started)
1467                 qede_dev_stop(eth_dev);
1468
1469         qede_stop_vport(edev);
1470         qdev->vport_started = false;
1471         qede_fdir_dealloc_resc(eth_dev);
1472         qede_dealloc_fp_resc(eth_dev);
1473
1474         eth_dev->data->nb_rx_queues = 0;
1475         eth_dev->data->nb_tx_queues = 0;
1476
1477         /* Bring the link down */
1478         qede_dev_set_link_state(eth_dev, false);
1479         qdev->ops->common->slowpath_stop(edev);
1480         qdev->ops->common->remove(edev);
1481         rte_intr_disable(&pci_dev->intr_handle);
1482
1483         switch (pci_dev->intr_handle.type) {
1484         case RTE_INTR_HANDLE_UIO_INTX:
1485         case RTE_INTR_HANDLE_VFIO_LEGACY:
1486                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1487                                              qede_interrupt_handler_intx,
1488                                              (void *)eth_dev);
1489                 break;
1490         default:
1491                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1492                                            qede_interrupt_handler,
1493                                            (void *)eth_dev);
1494         }
1495
1496         if (ECORE_IS_CMT(edev))
1497                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1498 }
1499
1500 static int
1501 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1502 {
1503         struct qede_dev *qdev = eth_dev->data->dev_private;
1504         struct ecore_dev *edev = &qdev->edev;
1505         struct ecore_eth_stats stats;
1506         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1507         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1508         struct qede_tx_queue *txq;
1509
1510         ecore_get_vport_stats(edev, &stats);
1511
1512         /* RX Stats */
1513         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1514             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1515
1516         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1517             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1518
1519         eth_stats->ierrors = stats.common.rx_crc_errors +
1520             stats.common.rx_align_errors +
1521             stats.common.rx_carrier_errors +
1522             stats.common.rx_oversize_packets +
1523             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1524
1525         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1526
1527         eth_stats->imissed = stats.common.mftag_filter_discards +
1528             stats.common.mac_filter_discards +
1529             stats.common.no_buff_discards +
1530             stats.common.brb_truncates + stats.common.brb_discards;
1531
1532         /* TX stats */
1533         eth_stats->opackets = stats.common.tx_ucast_pkts +
1534             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1535
1536         eth_stats->obytes = stats.common.tx_ucast_bytes +
1537             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1538
1539         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1540
1541         /* Queue stats */
1542         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1543                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1544         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1545                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1546         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1547             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1548                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1549                        "Not all the queue stats will be displayed. Set"
1550                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1551                        " appropriately and retry.\n");
1552
1553         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1554                 eth_stats->q_ipackets[i] = 0;
1555                 eth_stats->q_errors[i] = 0;
1556
1557                 for_each_hwfn(edev, hw_fn) {
1558                         idx = qid * edev->num_hwfns + hw_fn;
1559
1560                         eth_stats->q_ipackets[i] +=
1561                                 *(uint64_t *)
1562                                         (((char *)(qdev->fp_array[idx].rxq)) +
1563                                          offsetof(struct qede_rx_queue,
1564                                          rcv_pkts));
1565                         eth_stats->q_errors[i] +=
1566                                 *(uint64_t *)
1567                                         (((char *)(qdev->fp_array[idx].rxq)) +
1568                                          offsetof(struct qede_rx_queue,
1569                                          rx_hw_errors)) +
1570                                 *(uint64_t *)
1571                                         (((char *)(qdev->fp_array[idx].rxq)) +
1572                                          offsetof(struct qede_rx_queue,
1573                                          rx_alloc_errors));
1574                 }
1575
1576                 i++;
1577                 if (i == rxq_stat_cntrs)
1578                         break;
1579         }
1580
1581         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1582                 eth_stats->q_opackets[j] = 0;
1583
1584                 for_each_hwfn(edev, hw_fn) {
1585                         idx = qid * edev->num_hwfns + hw_fn;
1586
1587                         txq = qdev->fp_array[idx].txq;
1588                         eth_stats->q_opackets[j] +=
1589                                 *((uint64_t *)(uintptr_t)
1590                                         (((uint64_t)(uintptr_t)(txq)) +
1591                                          offsetof(struct qede_tx_queue,
1592                                                   xmit_pkts)));
1593                 }
1594
1595                 j++;
1596                 if (j == txq_stat_cntrs)
1597                         break;
1598         }
1599
1600         return 0;
1601 }
1602
1603 static unsigned
1604 qede_get_xstats_count(struct qede_dev *qdev) {
1605         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1606
1607         if (ECORE_IS_BB(&qdev->edev))
1608                 return RTE_DIM(qede_xstats_strings) +
1609                        RTE_DIM(qede_bb_xstats_strings) +
1610                        (RTE_DIM(qede_rxq_xstats_strings) *
1611                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1612         else
1613                 return RTE_DIM(qede_xstats_strings) +
1614                        RTE_DIM(qede_ah_xstats_strings) +
1615                        (RTE_DIM(qede_rxq_xstats_strings) *
1616                         QEDE_RSS_COUNT(dev));
1617 }
1618
1619 static int
1620 qede_get_xstats_names(struct rte_eth_dev *dev,
1621                       struct rte_eth_xstat_name *xstats_names,
1622                       __rte_unused unsigned int limit)
1623 {
1624         struct qede_dev *qdev = dev->data->dev_private;
1625         struct ecore_dev *edev = &qdev->edev;
1626         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1627         unsigned int i, qid, hw_fn, stat_idx = 0;
1628
1629         if (xstats_names == NULL)
1630                 return stat_cnt;
1631
1632         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1633                 strlcpy(xstats_names[stat_idx].name,
1634                         qede_xstats_strings[i].name,
1635                         sizeof(xstats_names[stat_idx].name));
1636                 stat_idx++;
1637         }
1638
1639         if (ECORE_IS_BB(edev)) {
1640                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1641                         strlcpy(xstats_names[stat_idx].name,
1642                                 qede_bb_xstats_strings[i].name,
1643                                 sizeof(xstats_names[stat_idx].name));
1644                         stat_idx++;
1645                 }
1646         } else {
1647                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1648                         strlcpy(xstats_names[stat_idx].name,
1649                                 qede_ah_xstats_strings[i].name,
1650                                 sizeof(xstats_names[stat_idx].name));
1651                         stat_idx++;
1652                 }
1653         }
1654
1655         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1656                 for_each_hwfn(edev, hw_fn) {
1657                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1658                                 snprintf(xstats_names[stat_idx].name,
1659                                          RTE_ETH_XSTATS_NAME_SIZE,
1660                                          "%.4s%d.%d%s",
1661                                          qede_rxq_xstats_strings[i].name,
1662                                          hw_fn, qid,
1663                                          qede_rxq_xstats_strings[i].name + 4);
1664                                 stat_idx++;
1665                         }
1666                 }
1667         }
1668
1669         return stat_cnt;
1670 }
1671
1672 static int
1673 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1674                 unsigned int n)
1675 {
1676         struct qede_dev *qdev = dev->data->dev_private;
1677         struct ecore_dev *edev = &qdev->edev;
1678         struct ecore_eth_stats stats;
1679         const unsigned int num = qede_get_xstats_count(qdev);
1680         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1681
1682         if (n < num)
1683                 return num;
1684
1685         ecore_get_vport_stats(edev, &stats);
1686
1687         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1688                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1689                                              qede_xstats_strings[i].offset);
1690                 xstats[stat_idx].id = stat_idx;
1691                 stat_idx++;
1692         }
1693
1694         if (ECORE_IS_BB(edev)) {
1695                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1696                         xstats[stat_idx].value =
1697                                         *(uint64_t *)(((char *)&stats) +
1698                                         qede_bb_xstats_strings[i].offset);
1699                         xstats[stat_idx].id = stat_idx;
1700                         stat_idx++;
1701                 }
1702         } else {
1703                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1704                         xstats[stat_idx].value =
1705                                         *(uint64_t *)(((char *)&stats) +
1706                                         qede_ah_xstats_strings[i].offset);
1707                         xstats[stat_idx].id = stat_idx;
1708                         stat_idx++;
1709                 }
1710         }
1711
1712         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1713                 for_each_hwfn(edev, hw_fn) {
1714                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1715                                 fpidx = qid * edev->num_hwfns + hw_fn;
1716                                 xstats[stat_idx].value = *(uint64_t *)
1717                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1718                                          qede_rxq_xstats_strings[i].offset);
1719                                 xstats[stat_idx].id = stat_idx;
1720                                 stat_idx++;
1721                         }
1722
1723                 }
1724         }
1725
1726         return stat_idx;
1727 }
1728
1729 static int
1730 qede_reset_xstats(struct rte_eth_dev *dev)
1731 {
1732         struct qede_dev *qdev = dev->data->dev_private;
1733         struct ecore_dev *edev = &qdev->edev;
1734
1735         ecore_reset_vport_stats(edev);
1736         qede_reset_queue_stats(qdev, true);
1737
1738         return 0;
1739 }
1740
1741 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1742 {
1743         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1744         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1745         struct qed_link_params link_params;
1746         int rc;
1747
1748         DP_INFO(edev, "setting link state %d\n", link_up);
1749         memset(&link_params, 0, sizeof(link_params));
1750         link_params.link_up = link_up;
1751         rc = qdev->ops->common->set_link(edev, &link_params);
1752         if (rc != ECORE_SUCCESS)
1753                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1754
1755         return rc;
1756 }
1757
1758 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1759 {
1760         return qede_dev_set_link_state(eth_dev, true);
1761 }
1762
1763 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1764 {
1765         return qede_dev_set_link_state(eth_dev, false);
1766 }
1767
1768 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1769 {
1770         struct qede_dev *qdev = eth_dev->data->dev_private;
1771         struct ecore_dev *edev = &qdev->edev;
1772
1773         ecore_reset_vport_stats(edev);
1774         qede_reset_queue_stats(qdev, false);
1775
1776         return 0;
1777 }
1778
1779 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1780 {
1781         enum qed_filter_rx_mode_type type =
1782             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1783         enum _ecore_status_t ecore_status;
1784
1785         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1786                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1787
1788         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1789
1790         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1791 }
1792
1793 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1794 {
1795         enum _ecore_status_t ecore_status;
1796
1797         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1798                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1799                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1800         else
1801                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1802                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1803
1804         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1805 }
1806
1807 static int
1808 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1809                 struct rte_ether_addr *mc_addrs,
1810                 uint32_t mc_addrs_num)
1811 {
1812         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1813         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1814         uint8_t i;
1815
1816         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1817                 DP_ERR(edev, "Reached max multicast filters limit,"
1818                              "Please enable multicast promisc mode\n");
1819                 return -ENOSPC;
1820         }
1821
1822         for (i = 0; i < mc_addrs_num; i++) {
1823                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1824                         DP_ERR(edev, "Not a valid multicast MAC\n");
1825                         return -EINVAL;
1826                 }
1827         }
1828
1829         /* Flush all existing entries */
1830         if (qede_del_mcast_filters(eth_dev))
1831                 return -1;
1832
1833         /* Set new mcast list */
1834         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1835 }
1836
1837 /* Update MTU via vport-update without doing port restart.
1838  * The vport must be deactivated before calling this API.
1839  */
1840 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1841 {
1842         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1843         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1844         struct ecore_hwfn *p_hwfn;
1845         int rc;
1846         int i;
1847
1848         if (IS_PF(edev)) {
1849                 struct ecore_sp_vport_update_params params;
1850
1851                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1852                 params.vport_id = 0;
1853                 params.mtu = mtu;
1854                 params.vport_id = 0;
1855                 for_each_hwfn(edev, i) {
1856                         p_hwfn = &edev->hwfns[i];
1857                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1858                         rc = ecore_sp_vport_update(p_hwfn, &params,
1859                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1860                         if (rc != ECORE_SUCCESS)
1861                                 goto err;
1862                 }
1863         } else {
1864                 for_each_hwfn(edev, i) {
1865                         p_hwfn = &edev->hwfns[i];
1866                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1867                         if (rc == ECORE_INVAL) {
1868                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1869                                 /* Recreate vport */
1870                                 rc = qede_start_vport(qdev, mtu);
1871                                 if (rc != ECORE_SUCCESS)
1872                                         goto err;
1873
1874                                 /* Restore config lost due to vport stop */
1875                                 if (eth_dev->data->promiscuous)
1876                                         qede_promiscuous_enable(eth_dev);
1877                                 else
1878                                         qede_promiscuous_disable(eth_dev);
1879
1880                                 if (eth_dev->data->all_multicast)
1881                                         qede_allmulticast_enable(eth_dev);
1882                                 else
1883                                         qede_allmulticast_disable(eth_dev);
1884
1885                                 qede_vlan_offload_set(eth_dev,
1886                                                       qdev->vlan_offload_mask);
1887                         } else if (rc != ECORE_SUCCESS) {
1888                                 goto err;
1889                         }
1890                 }
1891         }
1892         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1893
1894         return 0;
1895
1896 err:
1897         DP_ERR(edev, "Failed to update MTU\n");
1898         return -1;
1899 }
1900
1901 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1902                               struct rte_eth_fc_conf *fc_conf)
1903 {
1904         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1905         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1906         struct qed_link_output current_link;
1907         struct qed_link_params params;
1908
1909         memset(&current_link, 0, sizeof(current_link));
1910         qdev->ops->common->get_link(edev, &current_link);
1911
1912         memset(&params, 0, sizeof(params));
1913         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1914         if (fc_conf->autoneg) {
1915                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1916                         DP_ERR(edev, "Autoneg not supported\n");
1917                         return -EINVAL;
1918                 }
1919                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1920         }
1921
1922         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1923         if (fc_conf->mode == RTE_FC_FULL)
1924                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1925                                         QED_LINK_PAUSE_RX_ENABLE);
1926         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1927                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1928         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1929                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1930
1931         params.link_up = true;
1932         (void)qdev->ops->common->set_link(edev, &params);
1933
1934         return 0;
1935 }
1936
1937 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1938                               struct rte_eth_fc_conf *fc_conf)
1939 {
1940         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1941         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1942         struct qed_link_output current_link;
1943
1944         memset(&current_link, 0, sizeof(current_link));
1945         qdev->ops->common->get_link(edev, &current_link);
1946
1947         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1948                 fc_conf->autoneg = true;
1949
1950         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1951                                          QED_LINK_PAUSE_TX_ENABLE))
1952                 fc_conf->mode = RTE_FC_FULL;
1953         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1954                 fc_conf->mode = RTE_FC_RX_PAUSE;
1955         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1956                 fc_conf->mode = RTE_FC_TX_PAUSE;
1957         else
1958                 fc_conf->mode = RTE_FC_NONE;
1959
1960         return 0;
1961 }
1962
1963 static const uint32_t *
1964 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1965 {
1966         static const uint32_t ptypes[] = {
1967                 RTE_PTYPE_L2_ETHER,
1968                 RTE_PTYPE_L2_ETHER_VLAN,
1969                 RTE_PTYPE_L3_IPV4,
1970                 RTE_PTYPE_L3_IPV6,
1971                 RTE_PTYPE_L4_TCP,
1972                 RTE_PTYPE_L4_UDP,
1973                 RTE_PTYPE_TUNNEL_VXLAN,
1974                 RTE_PTYPE_L4_FRAG,
1975                 RTE_PTYPE_TUNNEL_GENEVE,
1976                 RTE_PTYPE_TUNNEL_GRE,
1977                 /* Inner */
1978                 RTE_PTYPE_INNER_L2_ETHER,
1979                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1980                 RTE_PTYPE_INNER_L3_IPV4,
1981                 RTE_PTYPE_INNER_L3_IPV6,
1982                 RTE_PTYPE_INNER_L4_TCP,
1983                 RTE_PTYPE_INNER_L4_UDP,
1984                 RTE_PTYPE_INNER_L4_FRAG,
1985                 RTE_PTYPE_UNKNOWN
1986         };
1987
1988         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
1989             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
1990                 return ptypes;
1991
1992         return NULL;
1993 }
1994
1995 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1996 {
1997         *rss_caps = 0;
1998         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1999         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2000         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2001         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2002         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2003         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2004         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2005         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2006 }
2007
2008 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2009                          struct rte_eth_rss_conf *rss_conf)
2010 {
2011         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2012         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2013         struct ecore_sp_vport_update_params vport_update_params;
2014         struct ecore_rss_params rss_params;
2015         struct ecore_hwfn *p_hwfn;
2016         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2017         uint64_t hf = rss_conf->rss_hf;
2018         uint8_t len = rss_conf->rss_key_len;
2019         uint8_t idx, i, j, fpidx;
2020         int rc;
2021
2022         memset(&vport_update_params, 0, sizeof(vport_update_params));
2023         memset(&rss_params, 0, sizeof(rss_params));
2024
2025         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2026                 (unsigned long)hf, len, key);
2027
2028         if (hf != 0) {
2029                 /* Enabling RSS */
2030                 DP_INFO(edev, "Enabling rss\n");
2031
2032                 /* RSS caps */
2033                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2034                 rss_params.update_rss_capabilities = 1;
2035
2036                 /* RSS hash key */
2037                 if (key) {
2038                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2039                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2040                                 return -EINVAL;
2041                         }
2042                         DP_INFO(edev, "Applying user supplied hash key\n");
2043                         rss_params.update_rss_key = 1;
2044                         memcpy(&rss_params.rss_key, key, len);
2045                 }
2046                 rss_params.rss_enable = 1;
2047         }
2048
2049         rss_params.update_rss_config = 1;
2050         /* tbl_size has to be set with capabilities */
2051         rss_params.rss_table_size_log = 7;
2052         vport_update_params.vport_id = 0;
2053
2054         for_each_hwfn(edev, i) {
2055                 /* pass the L2 handles instead of qids */
2056                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2057                         idx = j % QEDE_RSS_COUNT(eth_dev);
2058                         fpidx = idx * edev->num_hwfns + i;
2059                         rss_params.rss_ind_table[j] =
2060                                 qdev->fp_array[fpidx].rxq->handle;
2061                 }
2062
2063                 vport_update_params.rss_params = &rss_params;
2064
2065                 p_hwfn = &edev->hwfns[i];
2066                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2067                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2068                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2069                 if (rc) {
2070                         DP_ERR(edev, "vport-update for RSS failed\n");
2071                         return rc;
2072                 }
2073         }
2074         qdev->rss_enable = rss_params.rss_enable;
2075
2076         /* Update local structure for hash query */
2077         qdev->rss_conf.rss_hf = hf;
2078         qdev->rss_conf.rss_key_len = len;
2079         if (qdev->rss_enable) {
2080                 if  (qdev->rss_conf.rss_key == NULL) {
2081                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2082                         if (qdev->rss_conf.rss_key == NULL) {
2083                                 DP_ERR(edev, "No memory to store RSS key\n");
2084                                 return -ENOMEM;
2085                         }
2086                 }
2087                 if (key && len) {
2088                         DP_INFO(edev, "Storing RSS key\n");
2089                         memcpy(qdev->rss_conf.rss_key, key, len);
2090                 }
2091         } else if (!qdev->rss_enable && len == 0) {
2092                 if (qdev->rss_conf.rss_key) {
2093                         free(qdev->rss_conf.rss_key);
2094                         qdev->rss_conf.rss_key = NULL;
2095                         DP_INFO(edev, "Free RSS key\n");
2096                 }
2097         }
2098
2099         return 0;
2100 }
2101
2102 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2103                            struct rte_eth_rss_conf *rss_conf)
2104 {
2105         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2106
2107         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2108         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2109
2110         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2111                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2112                        rss_conf->rss_key_len);
2113         return 0;
2114 }
2115
2116 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2117                          struct rte_eth_rss_reta_entry64 *reta_conf,
2118                          uint16_t reta_size)
2119 {
2120         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2121         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2122         struct ecore_sp_vport_update_params vport_update_params;
2123         struct ecore_rss_params *params;
2124         uint16_t i, j, idx, fid, shift;
2125         struct ecore_hwfn *p_hwfn;
2126         uint8_t entry;
2127         int rc = 0;
2128
2129         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2130                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2131                        reta_size);
2132                 return -EINVAL;
2133         }
2134
2135         memset(&vport_update_params, 0, sizeof(vport_update_params));
2136         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2137         if (params == NULL) {
2138                 DP_ERR(edev, "failed to allocate memory\n");
2139                 return -ENOMEM;
2140         }
2141
2142         params->update_rss_ind_table = 1;
2143         params->rss_table_size_log = 7;
2144         params->update_rss_config = 1;
2145
2146         vport_update_params.vport_id = 0;
2147         /* Use the current value of rss_enable */
2148         params->rss_enable = qdev->rss_enable;
2149         vport_update_params.rss_params = params;
2150
2151         for_each_hwfn(edev, i) {
2152                 for (j = 0; j < reta_size; j++) {
2153                         idx = j / RTE_RETA_GROUP_SIZE;
2154                         shift = j % RTE_RETA_GROUP_SIZE;
2155                         if (reta_conf[idx].mask & (1ULL << shift)) {
2156                                 entry = reta_conf[idx].reta[shift];
2157                                 fid = entry * edev->num_hwfns + i;
2158                                 /* Pass rxq handles to ecore */
2159                                 params->rss_ind_table[j] =
2160                                                 qdev->fp_array[fid].rxq->handle;
2161                                 /* Update the local copy for RETA query cmd */
2162                                 qdev->rss_ind_table[j] = entry;
2163                         }
2164                 }
2165
2166                 p_hwfn = &edev->hwfns[i];
2167                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2168                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2169                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2170                 if (rc) {
2171                         DP_ERR(edev, "vport-update for RSS failed\n");
2172                         goto out;
2173                 }
2174         }
2175
2176 out:
2177         rte_free(params);
2178         return rc;
2179 }
2180
2181 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2182                                struct rte_eth_rss_reta_entry64 *reta_conf,
2183                                uint16_t reta_size)
2184 {
2185         struct qede_dev *qdev = eth_dev->data->dev_private;
2186         struct ecore_dev *edev = &qdev->edev;
2187         uint16_t i, idx, shift;
2188         uint8_t entry;
2189
2190         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2191                 DP_ERR(edev, "reta_size %d is not supported\n",
2192                        reta_size);
2193                 return -EINVAL;
2194         }
2195
2196         for (i = 0; i < reta_size; i++) {
2197                 idx = i / RTE_RETA_GROUP_SIZE;
2198                 shift = i % RTE_RETA_GROUP_SIZE;
2199                 if (reta_conf[idx].mask & (1ULL << shift)) {
2200                         entry = qdev->rss_ind_table[i];
2201                         reta_conf[idx].reta[shift] = entry;
2202                 }
2203         }
2204
2205         return 0;
2206 }
2207
2208
2209
2210 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2211 {
2212         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2213         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2214         struct rte_eth_dev_info dev_info = {0};
2215         struct qede_fastpath *fp;
2216         uint32_t max_rx_pkt_len;
2217         uint32_t frame_size;
2218         uint16_t bufsz;
2219         bool restart = false;
2220         int i, rc;
2221
2222         PMD_INIT_FUNC_TRACE(edev);
2223         rc = qede_dev_info_get(dev, &dev_info);
2224         if (rc != 0) {
2225                 DP_ERR(edev, "Error during getting ethernet device info\n");
2226                 return rc;
2227         }
2228         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2229         frame_size = max_rx_pkt_len;
2230         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2231                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2232                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2233                        QEDE_ETH_OVERHEAD);
2234                 return -EINVAL;
2235         }
2236         if (!dev->data->scattered_rx &&
2237             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2238                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2239                         dev->data->min_rx_buf_size);
2240                 return -EINVAL;
2241         }
2242         /* Temporarily replace I/O functions with dummy ones. It cannot
2243          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2244          */
2245         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2246         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2247         if (dev->data->dev_started) {
2248                 dev->data->dev_started = 0;
2249                 qede_dev_stop(dev);
2250                 restart = true;
2251         }
2252         rte_delay_ms(1000);
2253         qdev->new_mtu = mtu;
2254
2255         /* Fix up RX buf size for all queues of the port */
2256         for (i = 0; i < qdev->num_rx_queues; i++) {
2257                 fp = &qdev->fp_array[i];
2258                 if (fp->rxq != NULL) {
2259                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2260                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2261                         /* cache align the mbuf size to simplfy rx_buf_size
2262                          * calculation
2263                          */
2264                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2265                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2266                         if (rc < 0)
2267                                 return rc;
2268
2269                         fp->rxq->rx_buf_size = rc;
2270                 }
2271         }
2272         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2273                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2274         else
2275                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2276
2277         if (!dev->data->dev_started && restart) {
2278                 qede_dev_start(dev);
2279                 dev->data->dev_started = 1;
2280         }
2281
2282         /* update max frame size */
2283         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2284         /* Reassign back */
2285         if (ECORE_IS_CMT(edev)) {
2286                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
2287                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2288         } else {
2289                 dev->rx_pkt_burst = qede_recv_pkts;
2290                 dev->tx_pkt_burst = qede_xmit_pkts;
2291         }
2292         return 0;
2293 }
2294
2295 static int
2296 qede_dev_reset(struct rte_eth_dev *dev)
2297 {
2298         int ret;
2299
2300         ret = qede_eth_dev_uninit(dev);
2301         if (ret)
2302                 return ret;
2303
2304         return qede_eth_dev_init(dev);
2305 }
2306
2307 static const struct eth_dev_ops qede_eth_dev_ops = {
2308         .dev_configure = qede_dev_configure,
2309         .dev_infos_get = qede_dev_info_get,
2310         .rx_queue_setup = qede_rx_queue_setup,
2311         .rx_queue_release = qede_rx_queue_release,
2312         .rx_descriptor_status = qede_rx_descriptor_status,
2313         .tx_queue_setup = qede_tx_queue_setup,
2314         .tx_queue_release = qede_tx_queue_release,
2315         .dev_start = qede_dev_start,
2316         .dev_reset = qede_dev_reset,
2317         .dev_set_link_up = qede_dev_set_link_up,
2318         .dev_set_link_down = qede_dev_set_link_down,
2319         .link_update = qede_link_update,
2320         .promiscuous_enable = qede_promiscuous_enable,
2321         .promiscuous_disable = qede_promiscuous_disable,
2322         .allmulticast_enable = qede_allmulticast_enable,
2323         .allmulticast_disable = qede_allmulticast_disable,
2324         .set_mc_addr_list = qede_set_mc_addr_list,
2325         .dev_stop = qede_dev_stop,
2326         .dev_close = qede_dev_close,
2327         .stats_get = qede_get_stats,
2328         .stats_reset = qede_reset_stats,
2329         .xstats_get = qede_get_xstats,
2330         .xstats_reset = qede_reset_xstats,
2331         .xstats_get_names = qede_get_xstats_names,
2332         .mac_addr_add = qede_mac_addr_add,
2333         .mac_addr_remove = qede_mac_addr_remove,
2334         .mac_addr_set = qede_mac_addr_set,
2335         .vlan_offload_set = qede_vlan_offload_set,
2336         .vlan_filter_set = qede_vlan_filter_set,
2337         .flow_ctrl_set = qede_flow_ctrl_set,
2338         .flow_ctrl_get = qede_flow_ctrl_get,
2339         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2340         .rss_hash_update = qede_rss_hash_update,
2341         .rss_hash_conf_get = qede_rss_hash_conf_get,
2342         .reta_update  = qede_rss_reta_update,
2343         .reta_query  = qede_rss_reta_query,
2344         .mtu_set = qede_set_mtu,
2345         .filter_ctrl = qede_dev_filter_ctrl,
2346         .udp_tunnel_port_add = qede_udp_dst_port_add,
2347         .udp_tunnel_port_del = qede_udp_dst_port_del,
2348 };
2349
2350 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2351         .dev_configure = qede_dev_configure,
2352         .dev_infos_get = qede_dev_info_get,
2353         .rx_queue_setup = qede_rx_queue_setup,
2354         .rx_queue_release = qede_rx_queue_release,
2355         .rx_descriptor_status = qede_rx_descriptor_status,
2356         .tx_queue_setup = qede_tx_queue_setup,
2357         .tx_queue_release = qede_tx_queue_release,
2358         .dev_start = qede_dev_start,
2359         .dev_reset = qede_dev_reset,
2360         .dev_set_link_up = qede_dev_set_link_up,
2361         .dev_set_link_down = qede_dev_set_link_down,
2362         .link_update = qede_link_update,
2363         .promiscuous_enable = qede_promiscuous_enable,
2364         .promiscuous_disable = qede_promiscuous_disable,
2365         .allmulticast_enable = qede_allmulticast_enable,
2366         .allmulticast_disable = qede_allmulticast_disable,
2367         .set_mc_addr_list = qede_set_mc_addr_list,
2368         .dev_stop = qede_dev_stop,
2369         .dev_close = qede_dev_close,
2370         .stats_get = qede_get_stats,
2371         .stats_reset = qede_reset_stats,
2372         .xstats_get = qede_get_xstats,
2373         .xstats_reset = qede_reset_xstats,
2374         .xstats_get_names = qede_get_xstats_names,
2375         .vlan_offload_set = qede_vlan_offload_set,
2376         .vlan_filter_set = qede_vlan_filter_set,
2377         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2378         .rss_hash_update = qede_rss_hash_update,
2379         .rss_hash_conf_get = qede_rss_hash_conf_get,
2380         .reta_update  = qede_rss_reta_update,
2381         .reta_query  = qede_rss_reta_query,
2382         .mtu_set = qede_set_mtu,
2383         .udp_tunnel_port_add = qede_udp_dst_port_add,
2384         .udp_tunnel_port_del = qede_udp_dst_port_del,
2385         .mac_addr_add = qede_mac_addr_add,
2386         .mac_addr_remove = qede_mac_addr_remove,
2387         .mac_addr_set = qede_mac_addr_set,
2388 };
2389
2390 static void qede_update_pf_params(struct ecore_dev *edev)
2391 {
2392         struct ecore_pf_params pf_params;
2393
2394         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2395         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2396         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2397         qed_ops->common->update_pf_params(edev, &pf_params);
2398 }
2399
2400 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2401 {
2402         struct rte_pci_device *pci_dev;
2403         struct rte_pci_addr pci_addr;
2404         struct qede_dev *adapter;
2405         struct ecore_dev *edev;
2406         struct qed_dev_eth_info dev_info;
2407         struct qed_slowpath_params params;
2408         static bool do_once = true;
2409         uint8_t bulletin_change;
2410         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2411         uint8_t is_mac_forced;
2412         bool is_mac_exist;
2413         /* Fix up ecore debug level */
2414         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2415         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2416         uint32_t int_mode;
2417         int rc;
2418
2419         /* Extract key data structures */
2420         adapter = eth_dev->data->dev_private;
2421         adapter->ethdev = eth_dev;
2422         edev = &adapter->edev;
2423         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2424         pci_addr = pci_dev->addr;
2425
2426         PMD_INIT_FUNC_TRACE(edev);
2427
2428         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2429                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2430                  eth_dev->data->port_id);
2431
2432         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2433                 DP_ERR(edev, "Skipping device init from secondary process\n");
2434                 return 0;
2435         }
2436
2437         rte_eth_copy_pci_info(eth_dev, pci_dev);
2438
2439         /* @DPDK */
2440         edev->vendor_id = pci_dev->id.vendor_id;
2441         edev->device_id = pci_dev->id.device_id;
2442
2443         qed_ops = qed_get_eth_ops();
2444         if (!qed_ops) {
2445                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2446                 rc = -EINVAL;
2447                 goto err;
2448         }
2449
2450         DP_INFO(edev, "Starting qede probe\n");
2451         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2452                                     dp_level, is_vf);
2453         if (rc != 0) {
2454                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2455                 rc = -ENODEV;
2456                 goto err;
2457         }
2458         qede_update_pf_params(edev);
2459
2460         switch (pci_dev->intr_handle.type) {
2461         case RTE_INTR_HANDLE_UIO_INTX:
2462         case RTE_INTR_HANDLE_VFIO_LEGACY:
2463                 int_mode = ECORE_INT_MODE_INTA;
2464                 rte_intr_callback_register(&pci_dev->intr_handle,
2465                                            qede_interrupt_handler_intx,
2466                                            (void *)eth_dev);
2467                 break;
2468         default:
2469                 int_mode = ECORE_INT_MODE_MSIX;
2470                 rte_intr_callback_register(&pci_dev->intr_handle,
2471                                            qede_interrupt_handler,
2472                                            (void *)eth_dev);
2473         }
2474
2475         if (rte_intr_enable(&pci_dev->intr_handle)) {
2476                 DP_ERR(edev, "rte_intr_enable() failed\n");
2477                 rc = -ENODEV;
2478                 goto err;
2479         }
2480
2481         /* Start the Slowpath-process */
2482         memset(&params, 0, sizeof(struct qed_slowpath_params));
2483
2484         params.int_mode = int_mode;
2485         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2486         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2487         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2488         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2489         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2490                 QEDE_PMD_DRV_VER_STR_SIZE);
2491
2492         if (ECORE_IS_CMT(edev)) {
2493                 eth_dev->rx_pkt_burst = qede_recv_pkts_cmt;
2494                 eth_dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2495         } else {
2496                 eth_dev->rx_pkt_burst = qede_recv_pkts;
2497                 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2498         }
2499
2500         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2501
2502         /* For CMT mode device do periodic polling for slowpath events.
2503          * This is required since uio device uses only one MSI-x
2504          * interrupt vector but we need one for each engine.
2505          */
2506         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2507                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2508                                        qede_poll_sp_sb_cb,
2509                                        (void *)eth_dev);
2510                 if (rc != 0) {
2511                         DP_ERR(edev, "Unable to start periodic"
2512                                      " timer rc %d\n", rc);
2513                         rc = -EINVAL;
2514                         goto err;
2515                 }
2516         }
2517
2518         rc = qed_ops->common->slowpath_start(edev, &params);
2519         if (rc) {
2520                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2521                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2522                                      (void *)eth_dev);
2523                 rc = -ENODEV;
2524                 goto err;
2525         }
2526
2527         rc = qed_ops->fill_dev_info(edev, &dev_info);
2528         if (rc) {
2529                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2530                 qed_ops->common->slowpath_stop(edev);
2531                 qed_ops->common->remove(edev);
2532                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2533                                      (void *)eth_dev);
2534                 rc = -ENODEV;
2535                 goto err;
2536         }
2537
2538         qede_alloc_etherdev(adapter, &dev_info);
2539
2540         if (do_once) {
2541                 qede_print_adapter_info(adapter);
2542                 do_once = false;
2543         }
2544
2545         adapter->ops->common->set_name(edev, edev->name);
2546
2547         if (!is_vf)
2548                 adapter->dev_info.num_mac_filters =
2549                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2550                                             ECORE_MAC);
2551         else
2552                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2553                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2554
2555         /* Allocate memory for storing MAC addr */
2556         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2557                                         (RTE_ETHER_ADDR_LEN *
2558                                         adapter->dev_info.num_mac_filters),
2559                                         RTE_CACHE_LINE_SIZE);
2560
2561         if (eth_dev->data->mac_addrs == NULL) {
2562                 DP_ERR(edev, "Failed to allocate MAC address\n");
2563                 qed_ops->common->slowpath_stop(edev);
2564                 qed_ops->common->remove(edev);
2565                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2566                                      (void *)eth_dev);
2567                 return -ENOMEM;
2568         }
2569
2570         if (!is_vf) {
2571                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2572                                 hw_info.hw_mac_addr,
2573                                 &eth_dev->data->mac_addrs[0]);
2574                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2575                                 &adapter->primary_mac);
2576         } else {
2577                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2578                                        &bulletin_change);
2579                 if (bulletin_change) {
2580                         is_mac_exist =
2581                             ecore_vf_bulletin_get_forced_mac(
2582                                                 ECORE_LEADING_HWFN(edev),
2583                                                 vf_mac,
2584                                                 &is_mac_forced);
2585                         if (is_mac_exist) {
2586                                 DP_INFO(edev, "VF macaddr received from PF\n");
2587                                 rte_ether_addr_copy(
2588                                         (struct rte_ether_addr *)&vf_mac,
2589                                         &eth_dev->data->mac_addrs[0]);
2590                                 rte_ether_addr_copy(
2591                                         &eth_dev->data->mac_addrs[0],
2592                                         &adapter->primary_mac);
2593                         } else {
2594                                 DP_ERR(edev, "No VF macaddr assigned\n");
2595                         }
2596                 }
2597         }
2598
2599         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2600
2601         /* Bring-up the link */
2602         qede_dev_set_link_state(eth_dev, true);
2603
2604         adapter->num_tx_queues = 0;
2605         adapter->num_rx_queues = 0;
2606         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2607         SLIST_INIT(&adapter->vlan_list_head);
2608         SLIST_INIT(&adapter->uc_list_head);
2609         SLIST_INIT(&adapter->mc_list_head);
2610         adapter->mtu = RTE_ETHER_MTU;
2611         adapter->vport_started = false;
2612
2613         /* VF tunnel offloads is enabled by default in PF driver */
2614         adapter->vxlan.num_filters = 0;
2615         adapter->geneve.num_filters = 0;
2616         adapter->ipgre.num_filters = 0;
2617         if (is_vf) {
2618                 adapter->vxlan.enable = true;
2619                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2620                                              ETH_TUNNEL_FILTER_IVLAN;
2621                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2622                 adapter->geneve.enable = true;
2623                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2624                                               ETH_TUNNEL_FILTER_IVLAN;
2625                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2626                 adapter->ipgre.enable = true;
2627                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2628                                              ETH_TUNNEL_FILTER_IVLAN;
2629         } else {
2630                 adapter->vxlan.enable = false;
2631                 adapter->geneve.enable = false;
2632                 adapter->ipgre.enable = false;
2633         }
2634
2635         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2636                 adapter->primary_mac.addr_bytes[0],
2637                 adapter->primary_mac.addr_bytes[1],
2638                 adapter->primary_mac.addr_bytes[2],
2639                 adapter->primary_mac.addr_bytes[3],
2640                 adapter->primary_mac.addr_bytes[4],
2641                 adapter->primary_mac.addr_bytes[5]);
2642
2643         DP_INFO(edev, "Device initialized\n");
2644
2645         return 0;
2646
2647 err:
2648         if (do_once) {
2649                 qede_print_adapter_info(adapter);
2650                 do_once = false;
2651         }
2652         return rc;
2653 }
2654
2655 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2656 {
2657         return qede_common_dev_init(eth_dev, 1);
2658 }
2659
2660 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2661 {
2662         return qede_common_dev_init(eth_dev, 0);
2663 }
2664
2665 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2666 {
2667         struct qede_dev *qdev = eth_dev->data->dev_private;
2668         struct ecore_dev *edev = &qdev->edev;
2669
2670         PMD_INIT_FUNC_TRACE(edev);
2671
2672         /* only uninitialize in the primary process */
2673         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2674                 return 0;
2675
2676         /* safe to close dev here */
2677         qede_dev_close(eth_dev);
2678
2679         eth_dev->dev_ops = NULL;
2680         eth_dev->rx_pkt_burst = NULL;
2681         eth_dev->tx_pkt_burst = NULL;
2682
2683         return 0;
2684 }
2685
2686 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2687 {
2688         return qede_dev_common_uninit(eth_dev);
2689 }
2690
2691 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2692 {
2693         return qede_dev_common_uninit(eth_dev);
2694 }
2695
2696 static const struct rte_pci_id pci_id_qedevf_map[] = {
2697 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2698         {
2699                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2700         },
2701         {
2702                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2703         },
2704         {
2705                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2706         },
2707         {.vendor_id = 0,}
2708 };
2709
2710 static const struct rte_pci_id pci_id_qede_map[] = {
2711 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2712         {
2713                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2714         },
2715         {
2716                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2717         },
2718         {
2719                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2720         },
2721         {
2722                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2723         },
2724         {
2725                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2726         },
2727         {
2728                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2729         },
2730         {
2731                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2732         },
2733         {
2734                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2735         },
2736         {
2737                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2738         },
2739         {
2740                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2741         },
2742         {.vendor_id = 0,}
2743 };
2744
2745 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2746         struct rte_pci_device *pci_dev)
2747 {
2748         return rte_eth_dev_pci_generic_probe(pci_dev,
2749                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2750 }
2751
2752 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2753 {
2754         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2755 }
2756
2757 static struct rte_pci_driver rte_qedevf_pmd = {
2758         .id_table = pci_id_qedevf_map,
2759         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2760         .probe = qedevf_eth_dev_pci_probe,
2761         .remove = qedevf_eth_dev_pci_remove,
2762 };
2763
2764 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2765         struct rte_pci_device *pci_dev)
2766 {
2767         return rte_eth_dev_pci_generic_probe(pci_dev,
2768                 sizeof(struct qede_dev), qede_eth_dev_init);
2769 }
2770
2771 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2772 {
2773         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2774 }
2775
2776 static struct rte_pci_driver rte_qede_pmd = {
2777         .id_table = pci_id_qede_map,
2778         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2779         .probe = qede_eth_dev_pci_probe,
2780         .remove = qede_eth_dev_pci_remove,
2781 };
2782
2783 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2784 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2785 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2786 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2787 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2788 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2789
2790 RTE_INIT(qede_init_log)
2791 {
2792         qede_logtype_init = rte_log_register("pmd.net.qede.init");
2793         if (qede_logtype_init >= 0)
2794                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2795         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2796         if (qede_logtype_driver >= 0)
2797                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
2798 }