drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 /* Globals */
  14 int qede_logtype_init;
  15 int qede_logtype_driver;
  16
  17 static const struct qed_eth_ops *qed_ops;
  18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  20
  21 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  22
  23 struct rte_qede_xstats_name_off {
  24         char name[RTE_ETH_XSTATS_NAME_SIZE];
  25         uint64_t offset;
  26 };
  27
  28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  29         {"rx_unicast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  31         {"rx_multicast_bytes",
  32                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  33         {"rx_broadcast_bytes",
  34                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  35         {"rx_unicast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  37         {"rx_multicast_packets",
  38                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  39         {"rx_broadcast_packets",
  40                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  41
  42         {"tx_unicast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  44         {"tx_multicast_bytes",
  45                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  46         {"tx_broadcast_bytes",
  47                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  48         {"tx_unicast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  50         {"tx_multicast_packets",
  51                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  52         {"tx_broadcast_packets",
  53                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  54
  55         {"rx_64_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  57         {"rx_65_to_127_byte_packets",
  58                 offsetof(struct ecore_eth_stats_common,
  59                          rx_65_to_127_byte_packets)},
  60         {"rx_128_to_255_byte_packets",
  61                 offsetof(struct ecore_eth_stats_common,
  62                          rx_128_to_255_byte_packets)},
  63         {"rx_256_to_511_byte_packets",
  64                 offsetof(struct ecore_eth_stats_common,
  65                          rx_256_to_511_byte_packets)},
  66         {"rx_512_to_1023_byte_packets",
  67                 offsetof(struct ecore_eth_stats_common,
  68                          rx_512_to_1023_byte_packets)},
  69         {"rx_1024_to_1518_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          rx_1024_to_1518_byte_packets)},
  72         {"tx_64_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  74         {"tx_65_to_127_byte_packets",
  75                 offsetof(struct ecore_eth_stats_common,
  76                          tx_65_to_127_byte_packets)},
  77         {"tx_128_to_255_byte_packets",
  78                 offsetof(struct ecore_eth_stats_common,
  79                          tx_128_to_255_byte_packets)},
  80         {"tx_256_to_511_byte_packets",
  81                 offsetof(struct ecore_eth_stats_common,
  82                          tx_256_to_511_byte_packets)},
  83         {"tx_512_to_1023_byte_packets",
  84                 offsetof(struct ecore_eth_stats_common,
  85                          tx_512_to_1023_byte_packets)},
  86         {"tx_1024_to_1518_byte_packets",
  87                 offsetof(struct ecore_eth_stats_common,
  88                          tx_1024_to_1518_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  96         {"tx_pause_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  98         {"rx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 100         {"tx_priority_flow_control_frames",
 101                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 102
 103         {"rx_crc_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 105         {"rx_align_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 107         {"rx_carrier_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 109         {"rx_oversize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 111         {"rx_jabber_errors",
 112                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 113         {"rx_undersize_packet_errors",
 114                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 115         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 116         {"rx_host_buffer_not_available",
 117                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 118         /* Number of packets discarded because they are bigger than MTU */
 119         {"rx_packet_too_big_discards",
 120                 offsetof(struct ecore_eth_stats_common,
 121                          packet_too_big_discard)},
 122         {"rx_ttl_zero_discards",
 123                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 124         {"rx_multi_function_tag_filter_discards",
 125                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 126         {"rx_mac_filter_discards",
 127                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 128         {"rx_gft_filter_drop",
 129                 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
 130         {"rx_hw_buffer_truncates",
 131                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 132         {"rx_hw_buffer_discards",
 133                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 134         {"tx_error_drop_packets",
 135                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 136
 137         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 138         {"rx_mac_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 140         {"rx_mac_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 142         {"rx_mac_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 144         {"rx_mac_frames_ok",
 145                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 146         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 147         {"tx_mac_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 149         {"tx_mac_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 151         {"tx_mac_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 153
 154         {"lro_coalesced_packets",
 155                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 156         {"lro_coalesced_events",
 157                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 158         {"lro_aborts_num",
 159                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 160         {"lro_not_coalesced_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          tpa_not_coalesced_pkts)},
 163         {"lro_coalesced_bytes",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          tpa_coalesced_bytes)},
 166 };
 167
 168 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 169         {"rx_1519_to_1522_byte_packets",
 170                 offsetof(struct ecore_eth_stats, bb) +
 171                 offsetof(struct ecore_eth_stats_bb,
 172                          rx_1519_to_1522_byte_packets)},
 173         {"rx_1519_to_2047_byte_packets",
 174                 offsetof(struct ecore_eth_stats, bb) +
 175                 offsetof(struct ecore_eth_stats_bb,
 176                          rx_1519_to_2047_byte_packets)},
 177         {"rx_2048_to_4095_byte_packets",
 178                 offsetof(struct ecore_eth_stats, bb) +
 179                 offsetof(struct ecore_eth_stats_bb,
 180                          rx_2048_to_4095_byte_packets)},
 181         {"rx_4096_to_9216_byte_packets",
 182                 offsetof(struct ecore_eth_stats, bb) +
 183                 offsetof(struct ecore_eth_stats_bb,
 184                          rx_4096_to_9216_byte_packets)},
 185         {"rx_9217_to_16383_byte_packets",
 186                 offsetof(struct ecore_eth_stats, bb) +
 187                 offsetof(struct ecore_eth_stats_bb,
 188                          rx_9217_to_16383_byte_packets)},
 189
 190         {"tx_1519_to_2047_byte_packets",
 191                 offsetof(struct ecore_eth_stats, bb) +
 192                 offsetof(struct ecore_eth_stats_bb,
 193                          tx_1519_to_2047_byte_packets)},
 194         {"tx_2048_to_4095_byte_packets",
 195                 offsetof(struct ecore_eth_stats, bb) +
 196                 offsetof(struct ecore_eth_stats_bb,
 197                          tx_2048_to_4095_byte_packets)},
 198         {"tx_4096_to_9216_byte_packets",
 199                 offsetof(struct ecore_eth_stats, bb) +
 200                 offsetof(struct ecore_eth_stats_bb,
 201                          tx_4096_to_9216_byte_packets)},
 202         {"tx_9217_to_16383_byte_packets",
 203                 offsetof(struct ecore_eth_stats, bb) +
 204                 offsetof(struct ecore_eth_stats_bb,
 205                          tx_9217_to_16383_byte_packets)},
 206
 207         {"tx_lpi_entry_count",
 208                 offsetof(struct ecore_eth_stats, bb) +
 209                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 210         {"tx_total_collisions",
 211                 offsetof(struct ecore_eth_stats, bb) +
 212                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 213 };
 214
 215 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 216         {"rx_1519_to_max_byte_packets",
 217                 offsetof(struct ecore_eth_stats, ah) +
 218                 offsetof(struct ecore_eth_stats_ah,
 219                          rx_1519_to_max_byte_packets)},
 220         {"tx_1519_to_max_byte_packets",
 221                 offsetof(struct ecore_eth_stats, ah) +
 222                 offsetof(struct ecore_eth_stats_ah,
 223                          tx_1519_to_max_byte_packets)},
 224 };
 225
 226 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 227         {"rx_q_segments",
 228                 offsetof(struct qede_rx_queue, rx_segs)},
 229         {"rx_q_hw_errors",
 230                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 231         {"rx_q_allocation_errors",
 232                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 233 };
 234
 235 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 236 {
 237         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 238 }
 239
 240 static void
 241 qede_interrupt_handler_intx(void *param)
 242 {
 243         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 244         struct qede_dev *qdev = eth_dev->data->dev_private;
 245         struct ecore_dev *edev = &qdev->edev;
 246         u64 status;
 247
 248         /* Check if our device actually raised an interrupt */
 249         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 250         if (status & 0x1) {
 251                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 252
 253                 if (rte_intr_ack(eth_dev->intr_handle))
 254                         DP_ERR(edev, "rte_intr_ack failed\n");
 255         }
 256 }
 257
 258 static void
 259 qede_interrupt_handler(void *param)
 260 {
 261         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 262         struct qede_dev *qdev = eth_dev->data->dev_private;
 263         struct ecore_dev *edev = &qdev->edev;
 264
 265         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 266         if (rte_intr_ack(eth_dev->intr_handle))
 267                 DP_ERR(edev, "rte_intr_ack failed\n");
 268 }
 269
 270 static void
 271 qede_assign_rxtx_handlers(struct rte_eth_dev *dev)
 272 {
 273         uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
 274         struct qede_dev *qdev = dev->data->dev_private;
 275         struct ecore_dev *edev = &qdev->edev;
 276         bool use_tx_offload = false;
 277
 278         if (ECORE_IS_CMT(edev)) {
 279                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
 280                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
 281                 return;
 282         }
 283
 284         if (dev->data->lro || dev->data->scattered_rx) {
 285                 DP_INFO(edev, "Assigning qede_recv_pkts\n");
 286                 dev->rx_pkt_burst = qede_recv_pkts;
 287         } else {
 288                 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n");
 289                 dev->rx_pkt_burst = qede_recv_pkts_regular;
 290         }
 291
 292         use_tx_offload = !!(tx_offloads &
 293                             (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */
 294                              DEV_TX_OFFLOAD_TCP_TSO | /* tso */
 295                              DEV_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */
 296
 297         if (use_tx_offload) {
 298                 DP_INFO(edev, "Assigning qede_xmit_pkts\n");
 299                 dev->tx_pkt_burst = qede_xmit_pkts;
 300         } else {
 301                 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n");
 302                 dev->tx_pkt_burst = qede_xmit_pkts_regular;
 303         }
 304 }
 305
 306 static void
 307 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 308 {
 309         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 310         qdev->ops = qed_ops;
 311 }
 312
 313 static void qede_print_adapter_info(struct qede_dev *qdev)
 314 {
 315         struct ecore_dev *edev = &qdev->edev;
 316         struct qed_dev_info *info = &qdev->dev_info.common;
 317         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 318
 319         DP_INFO(edev, "**************************************************\n");
 320         DP_INFO(edev, " DPDK version\t\t\t: %s\n", rte_version());
 321         DP_INFO(edev, " Chip details\t\t\t: %s %c%d\n",
 322                   ECORE_IS_BB(edev) ? "BB" : "AH",
 323                   'A' + edev->chip_rev,
 324                   (int)edev->chip_metal);
 325         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 326                  QEDE_PMD_DRV_VERSION);
 327         DP_INFO(edev, " Driver version\t\t\t: %s\n", ver_str);
 328
 329         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 330                  QEDE_PMD_BASE_VERSION);
 331         DP_INFO(edev, " Base version\t\t\t: %s\n", ver_str);
 332
 333         if (!IS_VF(edev))
 334                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 335                          QEDE_PMD_FW_VERSION);
 336         else
 337                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 338                          info->fw_major, info->fw_minor,
 339                          info->fw_rev, info->fw_eng);
 340         DP_INFO(edev, " Firmware version\t\t\t: %s\n", ver_str);
 341
 342         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 343                  "%d.%d.%d.%d",
 344                  (info->mfw_rev & QED_MFW_VERSION_3_MASK) >>
 345                  QED_MFW_VERSION_3_OFFSET,
 346                  (info->mfw_rev & QED_MFW_VERSION_2_MASK) >>
 347                  QED_MFW_VERSION_2_OFFSET,
 348                  (info->mfw_rev & QED_MFW_VERSION_1_MASK) >>
 349                  QED_MFW_VERSION_1_OFFSET,
 350                  (info->mfw_rev & QED_MFW_VERSION_0_MASK) >>
 351                  QED_MFW_VERSION_0_OFFSET);
 352         DP_INFO(edev, " Management Firmware version\t: %s\n", ver_str);
 353         DP_INFO(edev, " Firmware file\t\t\t: %s\n", qede_fw_file);
 354         DP_INFO(edev, "**************************************************\n");
 355 }
 356
 357 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 358 {
 359         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 360         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 361         unsigned int i = 0, j = 0, qid;
 362         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 363         struct qede_tx_queue *txq;
 364
 365         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 366
 367         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 368                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 369         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 370                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 371
 372         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 373                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 374                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 375                             sizeof(uint64_t));
 376                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 377                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 378                             sizeof(uint64_t));
 379                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 380                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 381                             sizeof(uint64_t));
 382
 383                 if (xstats)
 384                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 385                                 OSAL_MEMSET((((char *)
 386                                               (qdev->fp_array[qid].rxq)) +
 387                                              qede_rxq_xstats_strings[j].offset),
 388                                             0,
 389                                             sizeof(uint64_t));
 390
 391                 i++;
 392                 if (i == rxq_stat_cntrs)
 393                         break;
 394         }
 395
 396         i = 0;
 397
 398         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 399                 txq = qdev->fp_array[qid].txq;
 400
 401                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 402                                 (((uint64_t)(uintptr_t)(txq)) +
 403                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 404                             sizeof(uint64_t));
 405
 406                 i++;
 407                 if (i == txq_stat_cntrs)
 408                         break;
 409         }
 410 }
 411
 412 static int
 413 qede_stop_vport(struct ecore_dev *edev)
 414 {
 415         struct ecore_hwfn *p_hwfn;
 416         uint8_t vport_id;
 417         int rc;
 418         int i;
 419
 420         vport_id = 0;
 421         for_each_hwfn(edev, i) {
 422                 p_hwfn = &edev->hwfns[i];
 423                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 424                                          vport_id);
 425                 if (rc != ECORE_SUCCESS) {
 426                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 427                         return rc;
 428                 }
 429         }
 430
 431         DP_INFO(edev, "vport stopped\n");
 432
 433         return 0;
 434 }
 435
 436 static int
 437 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 438 {
 439         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 440         struct ecore_sp_vport_start_params params;
 441         struct ecore_hwfn *p_hwfn;
 442         int rc;
 443         int i;
 444
 445         if (qdev->vport_started)
 446                 qede_stop_vport(edev);
 447
 448         memset(&params, 0, sizeof(params));
 449         params.vport_id = 0;
 450         params.mtu = mtu;
 451         /* @DPDK - Disable FW placement */
 452         params.zero_placement_offset = 1;
 453         for_each_hwfn(edev, i) {
 454                 p_hwfn = &edev->hwfns[i];
 455                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 456                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 457                 rc = ecore_sp_vport_start(p_hwfn, &params);
 458                 if (rc != ECORE_SUCCESS) {
 459                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 460                         return rc;
 461                 }
 462         }
 463         ecore_reset_vport_stats(edev);
 464         qdev->vport_started = true;
 465         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 466
 467         return 0;
 468 }
 469
 470 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 471 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 472
 473 /* Activate or deactivate vport via vport-update */
 474 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 475 {
 476         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 477         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 478         struct ecore_sp_vport_update_params params;
 479         struct ecore_hwfn *p_hwfn;
 480         uint8_t i;
 481         int rc = -1;
 482
 483         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 484         params.vport_id = 0;
 485         params.update_vport_active_rx_flg = 1;
 486         params.update_vport_active_tx_flg = 1;
 487         params.vport_active_rx_flg = flg;
 488         params.vport_active_tx_flg = flg;
 489         if ((qdev->enable_tx_switching == false) && (flg == true)) {
 490                 params.update_tx_switching_flg = 1;
 491                 params.tx_switching_flg = !flg;
 492         }
 493         for_each_hwfn(edev, i) {
 494                 p_hwfn = &edev->hwfns[i];
 495                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 496                 rc = ecore_sp_vport_update(p_hwfn, &params,
 497                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 498                 if (rc != ECORE_SUCCESS) {
 499                         DP_ERR(edev, "Failed to update vport\n");
 500                         break;
 501                 }
 502         }
 503         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 504
 505         return rc;
 506 }
 507
 508 static void
 509 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 510                            uint16_t mtu, bool enable)
 511 {
 512         /* Enable LRO in split mode */
 513         sge_tpa_params->tpa_ipv4_en_flg = enable;
 514         sge_tpa_params->tpa_ipv6_en_flg = enable;
 515         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 516         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 517         /* set if tpa enable changes */
 518         sge_tpa_params->update_tpa_en_flg = 1;
 519         /* set if tpa parameters should be handled */
 520         sge_tpa_params->update_tpa_param_flg = enable;
 521
 522         sge_tpa_params->max_buffers_per_cqe = 20;
 523         /* Enable TPA in split mode. In this mode each TPA segment
 524          * starts on the new BD, so there is one BD per segment.
 525          */
 526         sge_tpa_params->tpa_pkt_split_flg = 1;
 527         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 528         sge_tpa_params->tpa_gro_consistent_flg = 0;
 529         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 530         sge_tpa_params->tpa_max_size = 0x7FFF;
 531         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 532         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 533 }
 534
 535 /* Enable/disable LRO via vport-update */
 536 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 537 {
 538         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 539         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 540         struct ecore_sp_vport_update_params params;
 541         struct ecore_sge_tpa_params tpa_params;
 542         struct ecore_hwfn *p_hwfn;
 543         int rc;
 544         int i;
 545
 546         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 547         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 548         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 549         params.vport_id = 0;
 550         params.sge_tpa_params = &tpa_params;
 551         for_each_hwfn(edev, i) {
 552                 p_hwfn = &edev->hwfns[i];
 553                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 554                 rc = ecore_sp_vport_update(p_hwfn, &params,
 555                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 556                 if (rc != ECORE_SUCCESS) {
 557                         DP_ERR(edev, "Failed to update LRO\n");
 558                         return -1;
 559                 }
 560         }
 561         qdev->enable_lro = flg;
 562         eth_dev->data->lro = flg;
 563
 564         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 565
 566         return 0;
 567 }
 568
 569 static int
 570 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 571                              enum qed_filter_rx_mode_type type)
 572 {
 573         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 574         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 575         struct ecore_filter_accept_flags flags;
 576
 577         memset(&flags, 0, sizeof(flags));
 578
 579         flags.update_rx_mode_config = 1;
 580         flags.update_tx_mode_config = 1;
 581         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 582                 ECORE_ACCEPT_MCAST_MATCHED |
 583                 ECORE_ACCEPT_BCAST;
 584
 585         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 586                 ECORE_ACCEPT_MCAST_MATCHED |
 587                 ECORE_ACCEPT_BCAST;
 588
 589         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 590                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 591                 if (IS_VF(edev)) {
 592                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 593                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 594                 }
 595         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 596                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 597         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 598                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 599                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 600                         ECORE_ACCEPT_MCAST_UNMATCHED;
 601         }
 602
 603         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 604                         ECORE_SPQ_MODE_CB, NULL);
 605 }
 606
 607 int
 608 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 609                   bool add)
 610 {
 611         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 612         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 613         struct qede_ucast_entry *tmp = NULL;
 614         struct qede_ucast_entry *u;
 615         struct rte_ether_addr *mac_addr;
 616
 617         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 618         if (add) {
 619                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 620                         if ((memcmp(mac_addr, &tmp->mac,
 621                                     RTE_ETHER_ADDR_LEN) == 0) &&
 622                              ucast->vni == tmp->vni &&
 623                              ucast->vlan == tmp->vlan) {
 624                                 DP_INFO(edev, "Unicast MAC is already added"
 625                                         " with vlan = %u, vni = %u\n",
 626                                         ucast->vlan,  ucast->vni);
 627                                         return 0;
 628                         }
 629                 }
 630                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 631                                RTE_CACHE_LINE_SIZE);
 632                 if (!u) {
 633                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 634                         return -ENOMEM;
 635                 }
 636                 rte_ether_addr_copy(mac_addr, &u->mac);
 637                 u->vlan = ucast->vlan;
 638                 u->vni = ucast->vni;
 639                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 640                 qdev->num_uc_addr++;
 641         } else {
 642                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 643                         if ((memcmp(mac_addr, &tmp->mac,
 644                                     RTE_ETHER_ADDR_LEN) == 0) &&
 645                             ucast->vlan == tmp->vlan      &&
 646                             ucast->vni == tmp->vni)
 647                         break;
 648                 }
 649                 if (tmp == NULL) {
 650                         DP_INFO(edev, "Unicast MAC is not found\n");
 651                         return -EINVAL;
 652                 }
 653                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 654                 qdev->num_uc_addr--;
 655         }
 656
 657         return 0;
 658 }
 659
 660 static int
 661 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 662                 struct rte_ether_addr *mc_addrs,
 663                 uint32_t mc_addrs_num)
 664 {
 665         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 666         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 667         struct ecore_filter_mcast mcast;
 668         struct qede_mcast_entry *m = NULL;
 669         uint8_t i;
 670         int rc;
 671
 672         for (i = 0; i < mc_addrs_num; i++) {
 673                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 674                                RTE_CACHE_LINE_SIZE);
 675                 if (!m) {
 676                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 677                         return -ENOMEM;
 678                 }
 679                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 680                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 681         }
 682         memset(&mcast, 0, sizeof(mcast));
 683         mcast.num_mc_addrs = mc_addrs_num;
 684         mcast.opcode = ECORE_FILTER_ADD;
 685         for (i = 0; i < mc_addrs_num; i++)
 686                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 687                                                         &mcast.mac[i]);
 688         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 689         if (rc != ECORE_SUCCESS) {
 690                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 691                 return -1;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 698 {
 699         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 700         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 701         struct qede_mcast_entry *tmp = NULL;
 702         struct ecore_filter_mcast mcast;
 703         int j;
 704         int rc;
 705
 706         memset(&mcast, 0, sizeof(mcast));
 707         mcast.num_mc_addrs = qdev->num_mc_addr;
 708         mcast.opcode = ECORE_FILTER_REMOVE;
 709         j = 0;
 710         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 711                 rte_ether_addr_copy(&tmp->mac,
 712                                 (struct rte_ether_addr *)&mcast.mac[j]);
 713                 j++;
 714         }
 715         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 716         if (rc != ECORE_SUCCESS) {
 717                 DP_ERR(edev, "Failed to delete multicast filter\n");
 718                 return -1;
 719         }
 720         /* Init the list */
 721         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 722                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 723                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 724         }
 725         SLIST_INIT(&qdev->mc_list_head);
 726
 727         return 0;
 728 }
 729
 730 enum _ecore_status_t
 731 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 732                  bool add)
 733 {
 734         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 735         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 736         enum _ecore_status_t rc = ECORE_INVAL;
 737
 738         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 739                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 740                               " Please enable promisc mode\n");
 741                         return ECORE_INVAL;
 742         }
 743
 744         rc = qede_ucast_filter(eth_dev, ucast, add);
 745         if (rc == 0)
 746                 rc = ecore_filter_ucast_cmd(edev, ucast,
 747                                             ECORE_SPQ_MODE_CB, NULL);
 748         /* Indicate error only for add filter operation.
 749          * Delete filter operations are not severe.
 750          */
 751         if ((rc != ECORE_SUCCESS) && add)
 752                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 753                        rc, add);
 754
 755         return rc;
 756 }
 757
 758 static int
 759 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 760                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 761 {
 762         struct ecore_filter_ucast ucast;
 763         int re;
 764
 765         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 766                 return -EINVAL;
 767
 768         qede_set_ucast_cmn_params(&ucast);
 769         ucast.opcode = ECORE_FILTER_ADD;
 770         ucast.type = ECORE_FILTER_MAC;
 771         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 772         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 773         return re;
 774 }
 775
 776 static void
 777 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 778 {
 779         struct qede_dev *qdev = eth_dev->data->dev_private;
 780         struct ecore_dev *edev = &qdev->edev;
 781         struct ecore_filter_ucast ucast;
 782
 783         PMD_INIT_FUNC_TRACE(edev);
 784
 785         if (index >= qdev->dev_info.num_mac_filters) {
 786                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 787                        index, qdev->dev_info.num_mac_filters);
 788                 return;
 789         }
 790
 791         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 792                 return;
 793
 794         qede_set_ucast_cmn_params(&ucast);
 795         ucast.opcode = ECORE_FILTER_REMOVE;
 796         ucast.type = ECORE_FILTER_MAC;
 797
 798         /* Use the index maintained by rte */
 799         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 800                         (struct rte_ether_addr *)&ucast.mac);
 801
 802         qede_mac_int_ops(eth_dev, &ucast, false);
 803 }
 804
 805 static int
 806 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 807 {
 808         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 809         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 810
 811         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 812                                                mac_addr->addr_bytes)) {
 813                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 814                 return -EPERM;
 815         }
 816
 817         qede_mac_addr_remove(eth_dev, 0);
 818
 819         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 820 }
 821
 822 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 823 {
 824         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 825         struct ecore_sp_vport_update_params params;
 826         struct ecore_hwfn *p_hwfn;
 827         uint8_t i;
 828         int rc;
 829
 830         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 831         params.vport_id = 0;
 832         params.update_accept_any_vlan_flg = 1;
 833         params.accept_any_vlan = flg;
 834         for_each_hwfn(edev, i) {
 835                 p_hwfn = &edev->hwfns[i];
 836                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 837                 rc = ecore_sp_vport_update(p_hwfn, &params,
 838                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 839                 if (rc != ECORE_SUCCESS) {
 840                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 841                         return;
 842                 }
 843         }
 844
 845         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 846 }
 847
 848 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 849 {
 850         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 851         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 852         struct ecore_sp_vport_update_params params;
 853         struct ecore_hwfn *p_hwfn;
 854         uint8_t i;
 855         int rc;
 856
 857         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 858         params.vport_id = 0;
 859         params.update_inner_vlan_removal_flg = 1;
 860         params.inner_vlan_removal_flg = flg;
 861         for_each_hwfn(edev, i) {
 862                 p_hwfn = &edev->hwfns[i];
 863                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 864                 rc = ecore_sp_vport_update(p_hwfn, &params,
 865                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 866                 if (rc != ECORE_SUCCESS) {
 867                         DP_ERR(edev, "Failed to update vport\n");
 868                         return -1;
 869                 }
 870         }
 871
 872         qdev->vlan_strip_flg = flg;
 873
 874         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 875         return 0;
 876 }
 877
 878 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 879                                 uint16_t vlan_id, int on)
 880 {
 881         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 882         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 883         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 884         struct qede_vlan_entry *tmp = NULL;
 885         struct qede_vlan_entry *vlan;
 886         struct ecore_filter_ucast ucast;
 887         int rc;
 888
 889         if (on) {
 890                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 891                         DP_ERR(edev, "Reached max VLAN filter limit"
 892                                       " enabling accept_any_vlan\n");
 893                         qede_config_accept_any_vlan(qdev, true);
 894                         return 0;
 895                 }
 896
 897                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 898                         if (tmp->vid == vlan_id) {
 899                                 DP_INFO(edev, "VLAN %u already configured\n",
 900                                         vlan_id);
 901                                 return 0;
 902                         }
 903                 }
 904
 905                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 906                                   RTE_CACHE_LINE_SIZE);
 907
 908                 if (!vlan) {
 909                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 910                         return -ENOMEM;
 911                 }
 912
 913                 qede_set_ucast_cmn_params(&ucast);
 914                 ucast.opcode = ECORE_FILTER_ADD;
 915                 ucast.type = ECORE_FILTER_VLAN;
 916                 ucast.vlan = vlan_id;
 917                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 918                                             NULL);
 919                 if (rc != 0) {
 920                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 921                                rc);
 922                         rte_free(vlan);
 923                 } else {
 924                         vlan->vid = vlan_id;
 925                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 926                         qdev->configured_vlans++;
 927                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 928                                 vlan_id, qdev->configured_vlans);
 929                 }
 930         } else {
 931                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 932                         if (tmp->vid == vlan_id)
 933                                 break;
 934                 }
 935
 936                 if (!tmp) {
 937                         if (qdev->configured_vlans == 0) {
 938                                 DP_INFO(edev,
 939                                         "No VLAN filters configured yet\n");
 940                                 return 0;
 941                         }
 942
 943                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 944                         return -EINVAL;
 945                 }
 946
 947                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 948
 949                 qede_set_ucast_cmn_params(&ucast);
 950                 ucast.opcode = ECORE_FILTER_REMOVE;
 951                 ucast.type = ECORE_FILTER_VLAN;
 952                 ucast.vlan = vlan_id;
 953                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 954                                             NULL);
 955                 if (rc != 0) {
 956                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 957                                vlan_id, rc);
 958                 } else {
 959                         qdev->configured_vlans--;
 960                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 961                                 vlan_id, qdev->configured_vlans);
 962                 }
 963         }
 964
 965         return rc;
 966 }
 967
 968 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 969 {
 970         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 971         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 972         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 973
 974         if (mask & ETH_VLAN_STRIP_MASK) {
 975                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 976                         (void)qede_vlan_stripping(eth_dev, 1);
 977                 else
 978                         (void)qede_vlan_stripping(eth_dev, 0);
 979         }
 980
 981         if (mask & ETH_VLAN_FILTER_MASK) {
 982                 /* VLAN filtering kicks in when a VLAN is added */
 983                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 984                         qede_vlan_filter_set(eth_dev, 0, 1);
 985                 } else {
 986                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 987                                 DP_ERR(edev,
 988                                   " Please remove existing VLAN filters"
 989                                   " before disabling VLAN filtering\n");
 990                                 /* Signal app that VLAN filtering is still
 991                                  * enabled
 992                                  */
 993                                 eth_dev->data->dev_conf.rxmode.offloads |=
 994                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
 995                         } else {
 996                                 qede_vlan_filter_set(eth_dev, 0, 0);
 997                         }
 998                 }
 999         }
1000
1001         if (mask & ETH_VLAN_EXTEND_MASK)
1002                 DP_ERR(edev, "Extend VLAN not supported\n");
1003
1004         qdev->vlan_offload_mask = mask;
1005
1006         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1007
1008         return 0;
1009 }
1010
1011 static void qede_prandom_bytes(uint32_t *buff)
1012 {
1013         uint8_t i;
1014
1015         srand((unsigned int)time(NULL));
1016         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1017                 buff[i] = rand();
1018 }
1019
1020 int qede_config_rss(struct rte_eth_dev *eth_dev)
1021 {
1022         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1023         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1024         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1025         struct rte_eth_rss_reta_entry64 reta_conf[2];
1026         struct rte_eth_rss_conf rss_conf;
1027         uint32_t i, id, pos, q;
1028
1029         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1030         if (!rss_conf.rss_key) {
1031                 DP_INFO(edev, "Applying driver default key\n");
1032                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1033                 qede_prandom_bytes(&def_rss_key[0]);
1034                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1035         }
1036
1037         /* Configure RSS hash */
1038         if (qede_rss_hash_update(eth_dev, &rss_conf))
1039                 return -EINVAL;
1040
1041         /* Configure default RETA */
1042         memset(reta_conf, 0, sizeof(reta_conf));
1043         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1044                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1045
1046         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1047                 id = i / RTE_RETA_GROUP_SIZE;
1048                 pos = i % RTE_RETA_GROUP_SIZE;
1049                 q = i % QEDE_RSS_COUNT(eth_dev);
1050                 reta_conf[id].reta[pos] = q;
1051         }
1052         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1053                                  ECORE_RSS_IND_TABLE_SIZE))
1054                 return -EINVAL;
1055
1056         return 0;
1057 }
1058
1059 static void qede_fastpath_start(struct ecore_dev *edev)
1060 {
1061         struct ecore_hwfn *p_hwfn;
1062         int i;
1063
1064         for_each_hwfn(edev, i) {
1065                 p_hwfn = &edev->hwfns[i];
1066                 ecore_hw_start_fastpath(p_hwfn);
1067         }
1068 }
1069
1070 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1071 {
1072         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1073         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1074         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1075
1076         PMD_INIT_FUNC_TRACE(edev);
1077
1078         /* Update MTU only if it has changed */
1079         if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1080                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1081                         goto err;
1082                 qdev->mtu = qdev->new_mtu;
1083                 qdev->new_mtu = 0;
1084         }
1085
1086         /* Configure TPA parameters */
1087         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1088                 if (qede_enable_tpa(eth_dev, true))
1089                         return -EINVAL;
1090                 /* Enable scatter mode for LRO */
1091                 if (!eth_dev->data->scattered_rx)
1092                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1093         }
1094
1095         /* Start queues */
1096         if (qede_start_queues(eth_dev))
1097                 goto err;
1098
1099         if (IS_PF(edev))
1100                 qede_reset_queue_stats(qdev, true);
1101
1102         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1103          * enabling RSS. Hence RSS configuration is deferred upto this point.
1104          * Also, we would like to retain similar behavior in PF case, so we
1105          * don't do PF/VF specific check here.
1106          */
1107         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1108                 if (qede_config_rss(eth_dev))
1109                         goto err;
1110
1111         /* Enable vport*/
1112         if (qede_activate_vport(eth_dev, true))
1113                 goto err;
1114
1115         /* Update link status */
1116         qede_link_update(eth_dev, 0);
1117
1118         /* Start/resume traffic */
1119         qede_fastpath_start(edev);
1120
1121         qede_assign_rxtx_handlers(eth_dev);
1122         DP_INFO(edev, "Device started\n");
1123
1124         return 0;
1125 err:
1126         DP_ERR(edev, "Device start fails\n");
1127         return -1; /* common error code is < 0 */
1128 }
1129
1130 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1131 {
1132         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1133         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1134
1135         PMD_INIT_FUNC_TRACE(edev);
1136
1137         /* Disable vport */
1138         if (qede_activate_vport(eth_dev, false))
1139                 return;
1140
1141         if (qdev->enable_lro)
1142                 qede_enable_tpa(eth_dev, false);
1143
1144         /* Stop queues */
1145         qede_stop_queues(eth_dev);
1146
1147         /* Disable traffic */
1148         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1149
1150         DP_INFO(edev, "Device is stopped\n");
1151 }
1152
1153 static const char * const valid_args[] = {
1154         QEDE_NPAR_TX_SWITCHING,
1155         QEDE_VF_TX_SWITCHING,
1156         NULL,
1157 };
1158
1159 static int qede_args_check(const char *key, const char *val, void *opaque)
1160 {
1161         unsigned long tmp;
1162         int ret = 0;
1163         struct rte_eth_dev *eth_dev = opaque;
1164         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1165         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1166
1167         errno = 0;
1168         tmp = strtoul(val, NULL, 0);
1169         if (errno) {
1170                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1171                 return errno;
1172         }
1173
1174         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1175             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1176                 qdev->enable_tx_switching = !!tmp;
1177                 DP_INFO(edev, "Disabling %s tx-switching\n",
1178                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1179                         "VF" : "NPAR");
1180         }
1181
1182         return ret;
1183 }
1184
1185 static int qede_args(struct rte_eth_dev *eth_dev)
1186 {
1187         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1188         struct rte_kvargs *kvlist;
1189         struct rte_devargs *devargs;
1190         int ret;
1191         int i;
1192
1193         devargs = pci_dev->device.devargs;
1194         if (!devargs)
1195                 return 0; /* return success */
1196
1197         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1198         if (kvlist == NULL)
1199                 return -EINVAL;
1200
1201          /* Process parameters. */
1202         for (i = 0; (valid_args[i] != NULL); ++i) {
1203                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1204                         ret = rte_kvargs_process(kvlist, valid_args[i],
1205                                                  qede_args_check, eth_dev);
1206                         if (ret != ECORE_SUCCESS) {
1207                                 rte_kvargs_free(kvlist);
1208                                 return ret;
1209                         }
1210                 }
1211         }
1212         rte_kvargs_free(kvlist);
1213
1214         return 0;
1215 }
1216
1217 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1218 {
1219         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1220         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1221         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1222         int ret;
1223
1224         PMD_INIT_FUNC_TRACE(edev);
1225
1226         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
1227                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1228
1229         /* We need to have min 1 RX queue.There is no min check in
1230          * rte_eth_dev_configure(), so we are checking it here.
1231          */
1232         if (eth_dev->data->nb_rx_queues == 0) {
1233                 DP_ERR(edev, "Minimum one RX queue is required\n");
1234                 return -EINVAL;
1235         }
1236
1237         /* Enable Tx switching by default */
1238         qdev->enable_tx_switching = 1;
1239
1240         /* Parse devargs and fix up rxmode */
1241         if (qede_args(eth_dev))
1242                 DP_NOTICE(edev, false,
1243                           "Invalid devargs supplied, requested change will not take effect\n");
1244
1245         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1246               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1247                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1248                 return -ENOTSUP;
1249         }
1250         /* Flow director mode check */
1251         if (qede_check_fdir_support(eth_dev))
1252                 return -ENOTSUP;
1253
1254         qede_dealloc_fp_resc(eth_dev);
1255         qdev->num_tx_queues = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1256         qdev->num_rx_queues = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1257
1258         if (qede_alloc_fp_resc(qdev))
1259                 return -ENOMEM;
1260
1261         /* If jumbo enabled adjust MTU */
1262         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1263                 eth_dev->data->mtu =
1264                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1265                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1266
1267         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1268                 eth_dev->data->scattered_rx = 1;
1269
1270         if (qede_start_vport(qdev, eth_dev->data->mtu))
1271                 return -1;
1272
1273         qdev->mtu = eth_dev->data->mtu;
1274
1275         /* Enable VLAN offloads by default */
1276         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1277                                              ETH_VLAN_FILTER_MASK);
1278         if (ret)
1279                 return ret;
1280
1281         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1282                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1283
1284         if (ECORE_IS_CMT(edev))
1285                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1286                         qdev->num_rx_queues, qdev->num_tx_queues);
1287
1288
1289         return 0;
1290 }
1291
1292 /* Info about HW descriptor ring limitations */
1293 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1294         .nb_max = 0x8000, /* 32K */
1295         .nb_min = 128,
1296         .nb_align = 128 /* lowest common multiple */
1297 };
1298
1299 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1300         .nb_max = 0x8000, /* 32K */
1301         .nb_min = 256,
1302         .nb_align = 256,
1303         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1304         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1305 };
1306
1307 static int
1308 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1309                   struct rte_eth_dev_info *dev_info)
1310 {
1311         struct qede_dev *qdev = eth_dev->data->dev_private;
1312         struct ecore_dev *edev = &qdev->edev;
1313         struct qed_link_output link;
1314         uint32_t speed_cap = 0;
1315
1316         PMD_INIT_FUNC_TRACE(edev);
1317
1318         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1319         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1320         dev_info->rx_desc_lim = qede_rx_desc_lim;
1321         dev_info->tx_desc_lim = qede_tx_desc_lim;
1322
1323         if (IS_PF(edev))
1324                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1325                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1326         else
1327                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1328                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1329         /* Since CMT mode internally doubles the number of queues */
1330         if (ECORE_IS_CMT(edev))
1331                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1332
1333         dev_info->max_tx_queues = dev_info->max_rx_queues;
1334
1335         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1336         dev_info->max_vfs = 0;
1337         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1338         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1339         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1340         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1341                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1342                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1343                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1344                                      DEV_RX_OFFLOAD_TCP_LRO     |
1345                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1346                                      DEV_RX_OFFLOAD_SCATTER     |
1347                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1348                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1349                                      DEV_RX_OFFLOAD_VLAN_STRIP  |
1350                                      DEV_RX_OFFLOAD_RSS_HASH);
1351         dev_info->rx_queue_offload_capa = 0;
1352
1353         /* TX offloads are on a per-packet basis, so it is applicable
1354          * to both at port and queue levels.
1355          */
1356         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1357                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1358                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1359                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1360                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1361                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1362                                      DEV_TX_OFFLOAD_TCP_TSO     |
1363                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1364                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1365         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1366
1367         dev_info->default_txconf = (struct rte_eth_txconf) {
1368                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1369         };
1370
1371         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1372                 /* Packets are always dropped if no descriptors are available */
1373                 .rx_drop_en = 1,
1374                 .offloads = 0,
1375         };
1376
1377         memset(&link, 0, sizeof(struct qed_link_output));
1378         qdev->ops->common->get_link(edev, &link);
1379         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1380                 speed_cap |= ETH_LINK_SPEED_1G;
1381         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1382                 speed_cap |= ETH_LINK_SPEED_10G;
1383         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1384                 speed_cap |= ETH_LINK_SPEED_25G;
1385         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1386                 speed_cap |= ETH_LINK_SPEED_40G;
1387         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1388                 speed_cap |= ETH_LINK_SPEED_50G;
1389         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1390                 speed_cap |= ETH_LINK_SPEED_100G;
1391         dev_info->speed_capa = speed_cap;
1392
1393         return 0;
1394 }
1395
1396 /* return 0 means link status changed, -1 means not changed */
1397 int
1398 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1399 {
1400         struct qede_dev *qdev = eth_dev->data->dev_private;
1401         struct ecore_dev *edev = &qdev->edev;
1402         struct qed_link_output q_link;
1403         struct rte_eth_link link;
1404         uint16_t link_duplex;
1405
1406         memset(&q_link, 0, sizeof(q_link));
1407         memset(&link, 0, sizeof(link));
1408
1409         qdev->ops->common->get_link(edev, &q_link);
1410
1411         /* Link Speed */
1412         link.link_speed = q_link.speed;
1413
1414         /* Link Mode */
1415         switch (q_link.duplex) {
1416         case QEDE_DUPLEX_HALF:
1417                 link_duplex = ETH_LINK_HALF_DUPLEX;
1418                 break;
1419         case QEDE_DUPLEX_FULL:
1420                 link_duplex = ETH_LINK_FULL_DUPLEX;
1421                 break;
1422         case QEDE_DUPLEX_UNKNOWN:
1423         default:
1424                 link_duplex = -1;
1425         }
1426         link.link_duplex = link_duplex;
1427
1428         /* Link Status */
1429         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1430
1431         /* AN */
1432         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1433                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1434
1435         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1436                 link.link_speed, link.link_duplex,
1437                 link.link_autoneg, link.link_status);
1438
1439         return rte_eth_linkstatus_set(eth_dev, &link);
1440 }
1441
1442 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1443 {
1444         struct qede_dev *qdev = eth_dev->data->dev_private;
1445         struct ecore_dev *edev = &qdev->edev;
1446         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1447         enum _ecore_status_t ecore_status;
1448
1449         PMD_INIT_FUNC_TRACE(edev);
1450
1451         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1452                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1453
1454         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1455
1456         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1457 }
1458
1459 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1460 {
1461         struct qede_dev *qdev = eth_dev->data->dev_private;
1462         struct ecore_dev *edev = &qdev->edev;
1463         enum _ecore_status_t ecore_status;
1464
1465         PMD_INIT_FUNC_TRACE(edev);
1466
1467         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1468                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1469                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1470         else
1471                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1472                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1473
1474         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1475 }
1476
1477 static void qede_poll_sp_sb_cb(void *param)
1478 {
1479         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1480         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1481         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1482         int rc;
1483
1484         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1485         qede_interrupt_action(&edev->hwfns[1]);
1486
1487         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1488                                qede_poll_sp_sb_cb,
1489                                (void *)eth_dev);
1490         if (rc != 0) {
1491                 DP_ERR(edev, "Unable to start periodic"
1492                              " timer rc %d\n", rc);
1493         }
1494 }
1495
1496 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1497 {
1498         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1499         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1500         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1501
1502         PMD_INIT_FUNC_TRACE(edev);
1503
1504         /* dev_stop() shall cleanup fp resources in hw but without releasing
1505          * dma memories and sw structures so that dev_start() can be called
1506          * by the app without reconfiguration. However, in dev_close() we
1507          * can release all the resources and device can be brought up newly
1508          */
1509         if (eth_dev->data->dev_started)
1510                 qede_dev_stop(eth_dev);
1511
1512         qede_stop_vport(edev);
1513         qdev->vport_started = false;
1514         qede_fdir_dealloc_resc(eth_dev);
1515         qede_dealloc_fp_resc(eth_dev);
1516
1517         eth_dev->data->nb_rx_queues = 0;
1518         eth_dev->data->nb_tx_queues = 0;
1519
1520         /* Bring the link down */
1521         qede_dev_set_link_state(eth_dev, false);
1522         qdev->ops->common->slowpath_stop(edev);
1523         qdev->ops->common->remove(edev);
1524         rte_intr_disable(&pci_dev->intr_handle);
1525
1526         switch (pci_dev->intr_handle.type) {
1527         case RTE_INTR_HANDLE_UIO_INTX:
1528         case RTE_INTR_HANDLE_VFIO_LEGACY:
1529                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1530                                              qede_interrupt_handler_intx,
1531                                              (void *)eth_dev);
1532                 break;
1533         default:
1534                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1535                                            qede_interrupt_handler,
1536                                            (void *)eth_dev);
1537         }
1538
1539         if (ECORE_IS_CMT(edev))
1540                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1541 }
1542
1543 static int
1544 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1545 {
1546         struct qede_dev *qdev = eth_dev->data->dev_private;
1547         struct ecore_dev *edev = &qdev->edev;
1548         struct ecore_eth_stats stats;
1549         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1550         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1551         struct qede_tx_queue *txq;
1552
1553         ecore_get_vport_stats(edev, &stats);
1554
1555         /* RX Stats */
1556         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1557             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1558
1559         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1560             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1561
1562         eth_stats->ierrors = stats.common.rx_crc_errors +
1563             stats.common.rx_align_errors +
1564             stats.common.rx_carrier_errors +
1565             stats.common.rx_oversize_packets +
1566             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1567
1568         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1569
1570         eth_stats->imissed = stats.common.mftag_filter_discards +
1571             stats.common.mac_filter_discards +
1572             stats.common.no_buff_discards +
1573             stats.common.brb_truncates + stats.common.brb_discards;
1574
1575         /* TX stats */
1576         eth_stats->opackets = stats.common.tx_ucast_pkts +
1577             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1578
1579         eth_stats->obytes = stats.common.tx_ucast_bytes +
1580             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1581
1582         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1583
1584         /* Queue stats */
1585         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1586                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1587         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1588                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1589         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1590             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1591                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1592                        "Not all the queue stats will be displayed. Set"
1593                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1594                        " appropriately and retry.\n");
1595
1596         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1597                 eth_stats->q_ipackets[i] = 0;
1598                 eth_stats->q_errors[i] = 0;
1599
1600                 for_each_hwfn(edev, hw_fn) {
1601                         idx = qid * edev->num_hwfns + hw_fn;
1602
1603                         eth_stats->q_ipackets[i] +=
1604                                 *(uint64_t *)
1605                                         (((char *)(qdev->fp_array[idx].rxq)) +
1606                                          offsetof(struct qede_rx_queue,
1607                                          rcv_pkts));
1608                         eth_stats->q_errors[i] +=
1609                                 *(uint64_t *)
1610                                         (((char *)(qdev->fp_array[idx].rxq)) +
1611                                          offsetof(struct qede_rx_queue,
1612                                          rx_hw_errors)) +
1613                                 *(uint64_t *)
1614                                         (((char *)(qdev->fp_array[idx].rxq)) +
1615                                          offsetof(struct qede_rx_queue,
1616                                          rx_alloc_errors));
1617                 }
1618
1619                 i++;
1620                 if (i == rxq_stat_cntrs)
1621                         break;
1622         }
1623
1624         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1625                 eth_stats->q_opackets[j] = 0;
1626
1627                 for_each_hwfn(edev, hw_fn) {
1628                         idx = qid * edev->num_hwfns + hw_fn;
1629
1630                         txq = qdev->fp_array[idx].txq;
1631                         eth_stats->q_opackets[j] +=
1632                                 *((uint64_t *)(uintptr_t)
1633                                         (((uint64_t)(uintptr_t)(txq)) +
1634                                          offsetof(struct qede_tx_queue,
1635                                                   xmit_pkts)));
1636                 }
1637
1638                 j++;
1639                 if (j == txq_stat_cntrs)
1640                         break;
1641         }
1642
1643         return 0;
1644 }
1645
1646 static unsigned
1647 qede_get_xstats_count(struct qede_dev *qdev) {
1648         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1649
1650         if (ECORE_IS_BB(&qdev->edev))
1651                 return RTE_DIM(qede_xstats_strings) +
1652                        RTE_DIM(qede_bb_xstats_strings) +
1653                        (RTE_DIM(qede_rxq_xstats_strings) *
1654                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1655         else
1656                 return RTE_DIM(qede_xstats_strings) +
1657                        RTE_DIM(qede_ah_xstats_strings) +
1658                        (RTE_DIM(qede_rxq_xstats_strings) *
1659                         QEDE_RSS_COUNT(dev));
1660 }
1661
1662 static int
1663 qede_get_xstats_names(struct rte_eth_dev *dev,
1664                       struct rte_eth_xstat_name *xstats_names,
1665                       __rte_unused unsigned int limit)
1666 {
1667         struct qede_dev *qdev = dev->data->dev_private;
1668         struct ecore_dev *edev = &qdev->edev;
1669         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1670         unsigned int i, qid, hw_fn, stat_idx = 0;
1671
1672         if (xstats_names == NULL)
1673                 return stat_cnt;
1674
1675         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1676                 strlcpy(xstats_names[stat_idx].name,
1677                         qede_xstats_strings[i].name,
1678                         sizeof(xstats_names[stat_idx].name));
1679                 stat_idx++;
1680         }
1681
1682         if (ECORE_IS_BB(edev)) {
1683                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1684                         strlcpy(xstats_names[stat_idx].name,
1685                                 qede_bb_xstats_strings[i].name,
1686                                 sizeof(xstats_names[stat_idx].name));
1687                         stat_idx++;
1688                 }
1689         } else {
1690                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1691                         strlcpy(xstats_names[stat_idx].name,
1692                                 qede_ah_xstats_strings[i].name,
1693                                 sizeof(xstats_names[stat_idx].name));
1694                         stat_idx++;
1695                 }
1696         }
1697
1698         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1699                 for_each_hwfn(edev, hw_fn) {
1700                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1701                                 snprintf(xstats_names[stat_idx].name,
1702                                          RTE_ETH_XSTATS_NAME_SIZE,
1703                                          "%.4s%d.%d%s",
1704                                          qede_rxq_xstats_strings[i].name,
1705                                          hw_fn, qid,
1706                                          qede_rxq_xstats_strings[i].name + 4);
1707                                 stat_idx++;
1708                         }
1709                 }
1710         }
1711
1712         return stat_cnt;
1713 }
1714
1715 static int
1716 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1717                 unsigned int n)
1718 {
1719         struct qede_dev *qdev = dev->data->dev_private;
1720         struct ecore_dev *edev = &qdev->edev;
1721         struct ecore_eth_stats stats;
1722         const unsigned int num = qede_get_xstats_count(qdev);
1723         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1724
1725         if (n < num)
1726                 return num;
1727
1728         ecore_get_vport_stats(edev, &stats);
1729
1730         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1731                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1732                                              qede_xstats_strings[i].offset);
1733                 xstats[stat_idx].id = stat_idx;
1734                 stat_idx++;
1735         }
1736
1737         if (ECORE_IS_BB(edev)) {
1738                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1739                         xstats[stat_idx].value =
1740                                         *(uint64_t *)(((char *)&stats) +
1741                                         qede_bb_xstats_strings[i].offset);
1742                         xstats[stat_idx].id = stat_idx;
1743                         stat_idx++;
1744                 }
1745         } else {
1746                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1747                         xstats[stat_idx].value =
1748                                         *(uint64_t *)(((char *)&stats) +
1749                                         qede_ah_xstats_strings[i].offset);
1750                         xstats[stat_idx].id = stat_idx;
1751                         stat_idx++;
1752                 }
1753         }
1754
1755         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1756                 for_each_hwfn(edev, hw_fn) {
1757                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1758                                 fpidx = qid * edev->num_hwfns + hw_fn;
1759                                 xstats[stat_idx].value = *(uint64_t *)
1760                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1761                                          qede_rxq_xstats_strings[i].offset);
1762                                 xstats[stat_idx].id = stat_idx;
1763                                 stat_idx++;
1764                         }
1765
1766                 }
1767         }
1768
1769         return stat_idx;
1770 }
1771
1772 static int
1773 qede_reset_xstats(struct rte_eth_dev *dev)
1774 {
1775         struct qede_dev *qdev = dev->data->dev_private;
1776         struct ecore_dev *edev = &qdev->edev;
1777
1778         ecore_reset_vport_stats(edev);
1779         qede_reset_queue_stats(qdev, true);
1780
1781         return 0;
1782 }
1783
1784 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1785 {
1786         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1787         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1788         struct qed_link_params link_params;
1789         int rc;
1790
1791         DP_INFO(edev, "setting link state %d\n", link_up);
1792         memset(&link_params, 0, sizeof(link_params));
1793         link_params.link_up = link_up;
1794         rc = qdev->ops->common->set_link(edev, &link_params);
1795         if (rc != ECORE_SUCCESS)
1796                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1797
1798         return rc;
1799 }
1800
1801 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1802 {
1803         return qede_dev_set_link_state(eth_dev, true);
1804 }
1805
1806 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1807 {
1808         return qede_dev_set_link_state(eth_dev, false);
1809 }
1810
1811 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1812 {
1813         struct qede_dev *qdev = eth_dev->data->dev_private;
1814         struct ecore_dev *edev = &qdev->edev;
1815
1816         ecore_reset_vport_stats(edev);
1817         qede_reset_queue_stats(qdev, false);
1818
1819         return 0;
1820 }
1821
1822 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1823 {
1824         enum qed_filter_rx_mode_type type =
1825             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1826         enum _ecore_status_t ecore_status;
1827
1828         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1829                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1830
1831         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1832
1833         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1834 }
1835
1836 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1837 {
1838         enum _ecore_status_t ecore_status;
1839
1840         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1841                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1842                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1843         else
1844                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1845                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1846
1847         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1848 }
1849
1850 static int
1851 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1852                 struct rte_ether_addr *mc_addrs,
1853                 uint32_t mc_addrs_num)
1854 {
1855         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1856         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1857         uint8_t i;
1858
1859         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1860                 DP_ERR(edev, "Reached max multicast filters limit,"
1861                              "Please enable multicast promisc mode\n");
1862                 return -ENOSPC;
1863         }
1864
1865         for (i = 0; i < mc_addrs_num; i++) {
1866                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1867                         DP_ERR(edev, "Not a valid multicast MAC\n");
1868                         return -EINVAL;
1869                 }
1870         }
1871
1872         /* Flush all existing entries */
1873         if (qede_del_mcast_filters(eth_dev))
1874                 return -1;
1875
1876         /* Set new mcast list */
1877         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1878 }
1879
1880 /* Update MTU via vport-update without doing port restart.
1881  * The vport must be deactivated before calling this API.
1882  */
1883 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1884 {
1885         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1886         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1887         struct ecore_hwfn *p_hwfn;
1888         int rc;
1889         int i;
1890
1891         if (IS_PF(edev)) {
1892                 struct ecore_sp_vport_update_params params;
1893
1894                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1895                 params.vport_id = 0;
1896                 params.mtu = mtu;
1897                 params.vport_id = 0;
1898                 for_each_hwfn(edev, i) {
1899                         p_hwfn = &edev->hwfns[i];
1900                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1901                         rc = ecore_sp_vport_update(p_hwfn, &params,
1902                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1903                         if (rc != ECORE_SUCCESS)
1904                                 goto err;
1905                 }
1906         } else {
1907                 for_each_hwfn(edev, i) {
1908                         p_hwfn = &edev->hwfns[i];
1909                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1910                         if (rc == ECORE_INVAL) {
1911                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1912                                 /* Recreate vport */
1913                                 rc = qede_start_vport(qdev, mtu);
1914                                 if (rc != ECORE_SUCCESS)
1915                                         goto err;
1916
1917                                 /* Restore config lost due to vport stop */
1918                                 if (eth_dev->data->promiscuous)
1919                                         qede_promiscuous_enable(eth_dev);
1920                                 else
1921                                         qede_promiscuous_disable(eth_dev);
1922
1923                                 if (eth_dev->data->all_multicast)
1924                                         qede_allmulticast_enable(eth_dev);
1925                                 else
1926                                         qede_allmulticast_disable(eth_dev);
1927
1928                                 qede_vlan_offload_set(eth_dev,
1929                                                       qdev->vlan_offload_mask);
1930                         } else if (rc != ECORE_SUCCESS) {
1931                                 goto err;
1932                         }
1933                 }
1934         }
1935         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1936
1937         return 0;
1938
1939 err:
1940         DP_ERR(edev, "Failed to update MTU\n");
1941         return -1;
1942 }
1943
1944 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1945                               struct rte_eth_fc_conf *fc_conf)
1946 {
1947         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1948         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1949         struct qed_link_output current_link;
1950         struct qed_link_params params;
1951
1952         memset(&current_link, 0, sizeof(current_link));
1953         qdev->ops->common->get_link(edev, &current_link);
1954
1955         memset(&params, 0, sizeof(params));
1956         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1957         if (fc_conf->autoneg) {
1958                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1959                         DP_ERR(edev, "Autoneg not supported\n");
1960                         return -EINVAL;
1961                 }
1962                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1963         }
1964
1965         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1966         if (fc_conf->mode == RTE_FC_FULL)
1967                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1968                                         QED_LINK_PAUSE_RX_ENABLE);
1969         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1970                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1971         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1972                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1973
1974         params.link_up = true;
1975         (void)qdev->ops->common->set_link(edev, &params);
1976
1977         return 0;
1978 }
1979
1980 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1981                               struct rte_eth_fc_conf *fc_conf)
1982 {
1983         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1984         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1985         struct qed_link_output current_link;
1986
1987         memset(&current_link, 0, sizeof(current_link));
1988         qdev->ops->common->get_link(edev, &current_link);
1989
1990         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1991                 fc_conf->autoneg = true;
1992
1993         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1994                                          QED_LINK_PAUSE_TX_ENABLE))
1995                 fc_conf->mode = RTE_FC_FULL;
1996         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1997                 fc_conf->mode = RTE_FC_RX_PAUSE;
1998         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1999                 fc_conf->mode = RTE_FC_TX_PAUSE;
2000         else
2001                 fc_conf->mode = RTE_FC_NONE;
2002
2003         return 0;
2004 }
2005
2006 static const uint32_t *
2007 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2008 {
2009         static const uint32_t ptypes[] = {
2010                 RTE_PTYPE_L2_ETHER,
2011                 RTE_PTYPE_L2_ETHER_VLAN,
2012                 RTE_PTYPE_L3_IPV4,
2013                 RTE_PTYPE_L3_IPV6,
2014                 RTE_PTYPE_L4_TCP,
2015                 RTE_PTYPE_L4_UDP,
2016                 RTE_PTYPE_TUNNEL_VXLAN,
2017                 RTE_PTYPE_L4_FRAG,
2018                 RTE_PTYPE_TUNNEL_GENEVE,
2019                 RTE_PTYPE_TUNNEL_GRE,
2020                 /* Inner */
2021                 RTE_PTYPE_INNER_L2_ETHER,
2022                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2023                 RTE_PTYPE_INNER_L3_IPV4,
2024                 RTE_PTYPE_INNER_L3_IPV6,
2025                 RTE_PTYPE_INNER_L4_TCP,
2026                 RTE_PTYPE_INNER_L4_UDP,
2027                 RTE_PTYPE_INNER_L4_FRAG,
2028                 RTE_PTYPE_UNKNOWN
2029         };
2030
2031         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
2032             eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||
2033             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
2034                 return ptypes;
2035
2036         return NULL;
2037 }
2038
2039 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2040 {
2041         *rss_caps = 0;
2042         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2043         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2044         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2045         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2046         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2047         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2048         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2049         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2050 }
2051
2052 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2053                          struct rte_eth_rss_conf *rss_conf)
2054 {
2055         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2056         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2057         struct ecore_sp_vport_update_params vport_update_params;
2058         struct ecore_rss_params rss_params;
2059         struct ecore_hwfn *p_hwfn;
2060         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2061         uint64_t hf = rss_conf->rss_hf;
2062         uint8_t len = rss_conf->rss_key_len;
2063         uint8_t idx, i, j, fpidx;
2064         int rc;
2065
2066         memset(&vport_update_params, 0, sizeof(vport_update_params));
2067         memset(&rss_params, 0, sizeof(rss_params));
2068
2069         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2070                 (unsigned long)hf, len, key);
2071
2072         if (hf != 0) {
2073                 /* Enabling RSS */
2074                 DP_INFO(edev, "Enabling rss\n");
2075
2076                 /* RSS caps */
2077                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2078                 rss_params.update_rss_capabilities = 1;
2079
2080                 /* RSS hash key */
2081                 if (key) {
2082                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2083                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2084                                 return -EINVAL;
2085                         }
2086                         DP_INFO(edev, "Applying user supplied hash key\n");
2087                         rss_params.update_rss_key = 1;
2088                         memcpy(&rss_params.rss_key, key, len);
2089                 }
2090                 rss_params.rss_enable = 1;
2091         }
2092
2093         rss_params.update_rss_config = 1;
2094         /* tbl_size has to be set with capabilities */
2095         rss_params.rss_table_size_log = 7;
2096         vport_update_params.vport_id = 0;
2097
2098         for_each_hwfn(edev, i) {
2099                 /* pass the L2 handles instead of qids */
2100                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2101                         idx = j % QEDE_RSS_COUNT(eth_dev);
2102                         fpidx = idx * edev->num_hwfns + i;
2103                         rss_params.rss_ind_table[j] =
2104                                 qdev->fp_array[fpidx].rxq->handle;
2105                 }
2106
2107                 vport_update_params.rss_params = &rss_params;
2108
2109                 p_hwfn = &edev->hwfns[i];
2110                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2111                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2112                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2113                 if (rc) {
2114                         DP_ERR(edev, "vport-update for RSS failed\n");
2115                         return rc;
2116                 }
2117         }
2118         qdev->rss_enable = rss_params.rss_enable;
2119
2120         /* Update local structure for hash query */
2121         qdev->rss_conf.rss_hf = hf;
2122         qdev->rss_conf.rss_key_len = len;
2123         if (qdev->rss_enable) {
2124                 if  (qdev->rss_conf.rss_key == NULL) {
2125                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2126                         if (qdev->rss_conf.rss_key == NULL) {
2127                                 DP_ERR(edev, "No memory to store RSS key\n");
2128                                 return -ENOMEM;
2129                         }
2130                 }
2131                 if (key && len) {
2132                         DP_INFO(edev, "Storing RSS key\n");
2133                         memcpy(qdev->rss_conf.rss_key, key, len);
2134                 }
2135         } else if (!qdev->rss_enable && len == 0) {
2136                 if (qdev->rss_conf.rss_key) {
2137                         free(qdev->rss_conf.rss_key);
2138                         qdev->rss_conf.rss_key = NULL;
2139                         DP_INFO(edev, "Free RSS key\n");
2140                 }
2141         }
2142
2143         return 0;
2144 }
2145
2146 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2147                            struct rte_eth_rss_conf *rss_conf)
2148 {
2149         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2150
2151         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2152         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2153
2154         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2155                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2156                        rss_conf->rss_key_len);
2157         return 0;
2158 }
2159
2160 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2161                          struct rte_eth_rss_reta_entry64 *reta_conf,
2162                          uint16_t reta_size)
2163 {
2164         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2165         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2166         struct ecore_sp_vport_update_params vport_update_params;
2167         struct ecore_rss_params *params;
2168         uint16_t i, j, idx, fid, shift;
2169         struct ecore_hwfn *p_hwfn;
2170         uint8_t entry;
2171         int rc = 0;
2172
2173         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2174                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2175                        reta_size);
2176                 return -EINVAL;
2177         }
2178
2179         memset(&vport_update_params, 0, sizeof(vport_update_params));
2180         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2181         if (params == NULL) {
2182                 DP_ERR(edev, "failed to allocate memory\n");
2183                 return -ENOMEM;
2184         }
2185
2186         params->update_rss_ind_table = 1;
2187         params->rss_table_size_log = 7;
2188         params->update_rss_config = 1;
2189
2190         vport_update_params.vport_id = 0;
2191         /* Use the current value of rss_enable */
2192         params->rss_enable = qdev->rss_enable;
2193         vport_update_params.rss_params = params;
2194
2195         for_each_hwfn(edev, i) {
2196                 for (j = 0; j < reta_size; j++) {
2197                         idx = j / RTE_RETA_GROUP_SIZE;
2198                         shift = j % RTE_RETA_GROUP_SIZE;
2199                         if (reta_conf[idx].mask & (1ULL << shift)) {
2200                                 entry = reta_conf[idx].reta[shift];
2201                                 fid = entry * edev->num_hwfns + i;
2202                                 /* Pass rxq handles to ecore */
2203                                 params->rss_ind_table[j] =
2204                                                 qdev->fp_array[fid].rxq->handle;
2205                                 /* Update the local copy for RETA query cmd */
2206                                 qdev->rss_ind_table[j] = entry;
2207                         }
2208                 }
2209
2210                 p_hwfn = &edev->hwfns[i];
2211                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2212                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2213                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2214                 if (rc) {
2215                         DP_ERR(edev, "vport-update for RSS failed\n");
2216                         goto out;
2217                 }
2218         }
2219
2220 out:
2221         rte_free(params);
2222         return rc;
2223 }
2224
2225 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2226                                struct rte_eth_rss_reta_entry64 *reta_conf,
2227                                uint16_t reta_size)
2228 {
2229         struct qede_dev *qdev = eth_dev->data->dev_private;
2230         struct ecore_dev *edev = &qdev->edev;
2231         uint16_t i, idx, shift;
2232         uint8_t entry;
2233
2234         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2235                 DP_ERR(edev, "reta_size %d is not supported\n",
2236                        reta_size);
2237                 return -EINVAL;
2238         }
2239
2240         for (i = 0; i < reta_size; i++) {
2241                 idx = i / RTE_RETA_GROUP_SIZE;
2242                 shift = i % RTE_RETA_GROUP_SIZE;
2243                 if (reta_conf[idx].mask & (1ULL << shift)) {
2244                         entry = qdev->rss_ind_table[i];
2245                         reta_conf[idx].reta[shift] = entry;
2246                 }
2247         }
2248
2249         return 0;
2250 }
2251
2252
2253
2254 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2255 {
2256         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2257         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2258         struct rte_eth_dev_info dev_info = {0};
2259         struct qede_fastpath *fp;
2260         uint32_t max_rx_pkt_len;
2261         uint32_t frame_size;
2262         uint16_t bufsz;
2263         bool restart = false;
2264         int i, rc;
2265
2266         PMD_INIT_FUNC_TRACE(edev);
2267         rc = qede_dev_info_get(dev, &dev_info);
2268         if (rc != 0) {
2269                 DP_ERR(edev, "Error during getting ethernet device info\n");
2270                 return rc;
2271         }
2272         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2273         frame_size = max_rx_pkt_len;
2274         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2275                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2276                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2277                        QEDE_ETH_OVERHEAD);
2278                 return -EINVAL;
2279         }
2280         if (!dev->data->scattered_rx &&
2281             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2282                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2283                         dev->data->min_rx_buf_size);
2284                 return -EINVAL;
2285         }
2286         /* Temporarily replace I/O functions with dummy ones. It cannot
2287          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2288          */
2289         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2290         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2291         if (dev->data->dev_started) {
2292                 dev->data->dev_started = 0;
2293                 qede_dev_stop(dev);
2294                 restart = true;
2295         }
2296         rte_delay_ms(1000);
2297         qdev->new_mtu = mtu;
2298
2299         /* Fix up RX buf size for all queues of the port */
2300         for (i = 0; i < qdev->num_rx_queues; i++) {
2301                 fp = &qdev->fp_array[i];
2302                 if (fp->rxq != NULL) {
2303                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2304                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2305                         /* cache align the mbuf size to simplfy rx_buf_size
2306                          * calculation
2307                          */
2308                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2309                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2310                         if (rc < 0)
2311                                 return rc;
2312
2313                         fp->rxq->rx_buf_size = rc;
2314                 }
2315         }
2316         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2317                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2318         else
2319                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2320
2321         if (!dev->data->dev_started && restart) {
2322                 qede_dev_start(dev);
2323                 dev->data->dev_started = 1;
2324         }
2325
2326         /* update max frame size */
2327         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2328
2329         /* Reassign back */
2330         qede_assign_rxtx_handlers(dev);
2331         if (ECORE_IS_CMT(edev)) {
2332                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
2333                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2334         } else {
2335                 dev->rx_pkt_burst = qede_recv_pkts;
2336                 dev->tx_pkt_burst = qede_xmit_pkts;
2337         }
2338         return 0;
2339 }
2340
2341 static int
2342 qede_dev_reset(struct rte_eth_dev *dev)
2343 {
2344         int ret;
2345
2346         ret = qede_eth_dev_uninit(dev);
2347         if (ret)
2348                 return ret;
2349
2350         return qede_eth_dev_init(dev);
2351 }
2352
2353 static const struct eth_dev_ops qede_eth_dev_ops = {
2354         .dev_configure = qede_dev_configure,
2355         .dev_infos_get = qede_dev_info_get,
2356         .rx_queue_setup = qede_rx_queue_setup,
2357         .rx_queue_release = qede_rx_queue_release,
2358         .rx_descriptor_status = qede_rx_descriptor_status,
2359         .tx_queue_setup = qede_tx_queue_setup,
2360         .tx_queue_release = qede_tx_queue_release,
2361         .dev_start = qede_dev_start,
2362         .dev_reset = qede_dev_reset,
2363         .dev_set_link_up = qede_dev_set_link_up,
2364         .dev_set_link_down = qede_dev_set_link_down,
2365         .link_update = qede_link_update,
2366         .promiscuous_enable = qede_promiscuous_enable,
2367         .promiscuous_disable = qede_promiscuous_disable,
2368         .allmulticast_enable = qede_allmulticast_enable,
2369         .allmulticast_disable = qede_allmulticast_disable,
2370         .set_mc_addr_list = qede_set_mc_addr_list,
2371         .dev_stop = qede_dev_stop,
2372         .dev_close = qede_dev_close,
2373         .stats_get = qede_get_stats,
2374         .stats_reset = qede_reset_stats,
2375         .xstats_get = qede_get_xstats,
2376         .xstats_reset = qede_reset_xstats,
2377         .xstats_get_names = qede_get_xstats_names,
2378         .mac_addr_add = qede_mac_addr_add,
2379         .mac_addr_remove = qede_mac_addr_remove,
2380         .mac_addr_set = qede_mac_addr_set,
2381         .vlan_offload_set = qede_vlan_offload_set,
2382         .vlan_filter_set = qede_vlan_filter_set,
2383         .flow_ctrl_set = qede_flow_ctrl_set,
2384         .flow_ctrl_get = qede_flow_ctrl_get,
2385         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2386         .rss_hash_update = qede_rss_hash_update,
2387         .rss_hash_conf_get = qede_rss_hash_conf_get,
2388         .reta_update  = qede_rss_reta_update,
2389         .reta_query  = qede_rss_reta_query,
2390         .mtu_set = qede_set_mtu,
2391         .filter_ctrl = qede_dev_filter_ctrl,
2392         .udp_tunnel_port_add = qede_udp_dst_port_add,
2393         .udp_tunnel_port_del = qede_udp_dst_port_del,
2394 };
2395
2396 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2397         .dev_configure = qede_dev_configure,
2398         .dev_infos_get = qede_dev_info_get,
2399         .rx_queue_setup = qede_rx_queue_setup,
2400         .rx_queue_release = qede_rx_queue_release,
2401         .rx_descriptor_status = qede_rx_descriptor_status,
2402         .tx_queue_setup = qede_tx_queue_setup,
2403         .tx_queue_release = qede_tx_queue_release,
2404         .dev_start = qede_dev_start,
2405         .dev_reset = qede_dev_reset,
2406         .dev_set_link_up = qede_dev_set_link_up,
2407         .dev_set_link_down = qede_dev_set_link_down,
2408         .link_update = qede_link_update,
2409         .promiscuous_enable = qede_promiscuous_enable,
2410         .promiscuous_disable = qede_promiscuous_disable,
2411         .allmulticast_enable = qede_allmulticast_enable,
2412         .allmulticast_disable = qede_allmulticast_disable,
2413         .set_mc_addr_list = qede_set_mc_addr_list,
2414         .dev_stop = qede_dev_stop,
2415         .dev_close = qede_dev_close,
2416         .stats_get = qede_get_stats,
2417         .stats_reset = qede_reset_stats,
2418         .xstats_get = qede_get_xstats,
2419         .xstats_reset = qede_reset_xstats,
2420         .xstats_get_names = qede_get_xstats_names,
2421         .vlan_offload_set = qede_vlan_offload_set,
2422         .vlan_filter_set = qede_vlan_filter_set,
2423         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2424         .rss_hash_update = qede_rss_hash_update,
2425         .rss_hash_conf_get = qede_rss_hash_conf_get,
2426         .reta_update  = qede_rss_reta_update,
2427         .reta_query  = qede_rss_reta_query,
2428         .mtu_set = qede_set_mtu,
2429         .udp_tunnel_port_add = qede_udp_dst_port_add,
2430         .udp_tunnel_port_del = qede_udp_dst_port_del,
2431         .mac_addr_add = qede_mac_addr_add,
2432         .mac_addr_remove = qede_mac_addr_remove,
2433         .mac_addr_set = qede_mac_addr_set,
2434 };
2435
2436 static void qede_update_pf_params(struct ecore_dev *edev)
2437 {
2438         struct ecore_pf_params pf_params;
2439
2440         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2441         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2442         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2443         qed_ops->common->update_pf_params(edev, &pf_params);
2444 }
2445
2446 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2447 {
2448         struct rte_pci_device *pci_dev;
2449         struct rte_pci_addr pci_addr;
2450         struct qede_dev *adapter;
2451         struct ecore_dev *edev;
2452         struct qed_dev_eth_info dev_info;
2453         struct qed_slowpath_params params;
2454         static bool do_once = true;
2455         uint8_t bulletin_change;
2456         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2457         uint8_t is_mac_forced;
2458         bool is_mac_exist;
2459         /* Fix up ecore debug level */
2460         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2461         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2462         uint32_t int_mode;
2463         int rc;
2464
2465         /* Extract key data structures */
2466         adapter = eth_dev->data->dev_private;
2467         adapter->ethdev = eth_dev;
2468         edev = &adapter->edev;
2469         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2470         pci_addr = pci_dev->addr;
2471
2472         PMD_INIT_FUNC_TRACE(edev);
2473
2474         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2475                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2476                  eth_dev->data->port_id);
2477
2478         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2479                 DP_ERR(edev, "Skipping device init from secondary process\n");
2480                 return 0;
2481         }
2482
2483         rte_eth_copy_pci_info(eth_dev, pci_dev);
2484
2485         /* @DPDK */
2486         edev->vendor_id = pci_dev->id.vendor_id;
2487         edev->device_id = pci_dev->id.device_id;
2488
2489         qed_ops = qed_get_eth_ops();
2490         if (!qed_ops) {
2491                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2492                 rc = -EINVAL;
2493                 goto err;
2494         }
2495
2496         DP_INFO(edev, "Starting qede probe\n");
2497         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2498                                     dp_level, is_vf);
2499         if (rc != 0) {
2500                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2501                 rc = -ENODEV;
2502                 goto err;
2503         }
2504         qede_update_pf_params(edev);
2505
2506         switch (pci_dev->intr_handle.type) {
2507         case RTE_INTR_HANDLE_UIO_INTX:
2508         case RTE_INTR_HANDLE_VFIO_LEGACY:
2509                 int_mode = ECORE_INT_MODE_INTA;
2510                 rte_intr_callback_register(&pci_dev->intr_handle,
2511                                            qede_interrupt_handler_intx,
2512                                            (void *)eth_dev);
2513                 break;
2514         default:
2515                 int_mode = ECORE_INT_MODE_MSIX;
2516                 rte_intr_callback_register(&pci_dev->intr_handle,
2517                                            qede_interrupt_handler,
2518                                            (void *)eth_dev);
2519         }
2520
2521         if (rte_intr_enable(&pci_dev->intr_handle)) {
2522                 DP_ERR(edev, "rte_intr_enable() failed\n");
2523                 rc = -ENODEV;
2524                 goto err;
2525         }
2526
2527         /* Start the Slowpath-process */
2528         memset(&params, 0, sizeof(struct qed_slowpath_params));
2529
2530         params.int_mode = int_mode;
2531         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2532         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2533         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2534         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2535         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2536                 QEDE_PMD_DRV_VER_STR_SIZE);
2537
2538         qede_assign_rxtx_handlers(eth_dev);
2539         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2540
2541         /* For CMT mode device do periodic polling for slowpath events.
2542          * This is required since uio device uses only one MSI-x
2543          * interrupt vector but we need one for each engine.
2544          */
2545         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2546                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2547                                        qede_poll_sp_sb_cb,
2548                                        (void *)eth_dev);
2549                 if (rc != 0) {
2550                         DP_ERR(edev, "Unable to start periodic"
2551                                      " timer rc %d\n", rc);
2552                         rc = -EINVAL;
2553                         goto err;
2554                 }
2555         }
2556
2557         rc = qed_ops->common->slowpath_start(edev, &params);
2558         if (rc) {
2559                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2560                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2561                                      (void *)eth_dev);
2562                 rc = -ENODEV;
2563                 goto err;
2564         }
2565
2566         rc = qed_ops->fill_dev_info(edev, &dev_info);
2567         if (rc) {
2568                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2569                 qed_ops->common->slowpath_stop(edev);
2570                 qed_ops->common->remove(edev);
2571                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2572                                      (void *)eth_dev);
2573                 rc = -ENODEV;
2574                 goto err;
2575         }
2576
2577         qede_alloc_etherdev(adapter, &dev_info);
2578
2579         if (do_once) {
2580                 qede_print_adapter_info(adapter);
2581                 do_once = false;
2582         }
2583
2584         adapter->ops->common->set_name(edev, edev->name);
2585
2586         if (!is_vf)
2587                 adapter->dev_info.num_mac_filters =
2588                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2589                                             ECORE_MAC);
2590         else
2591                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2592                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2593
2594         /* Allocate memory for storing MAC addr */
2595         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2596                                         (RTE_ETHER_ADDR_LEN *
2597                                         adapter->dev_info.num_mac_filters),
2598                                         RTE_CACHE_LINE_SIZE);
2599
2600         if (eth_dev->data->mac_addrs == NULL) {
2601                 DP_ERR(edev, "Failed to allocate MAC address\n");
2602                 qed_ops->common->slowpath_stop(edev);
2603                 qed_ops->common->remove(edev);
2604                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2605                                      (void *)eth_dev);
2606                 return -ENOMEM;
2607         }
2608
2609         if (!is_vf) {
2610                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2611                                 hw_info.hw_mac_addr,
2612                                 &eth_dev->data->mac_addrs[0]);
2613                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2614                                 &adapter->primary_mac);
2615         } else {
2616                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2617                                        &bulletin_change);
2618                 if (bulletin_change) {
2619                         is_mac_exist =
2620                             ecore_vf_bulletin_get_forced_mac(
2621                                                 ECORE_LEADING_HWFN(edev),
2622                                                 vf_mac,
2623                                                 &is_mac_forced);
2624                         if (is_mac_exist) {
2625                                 DP_INFO(edev, "VF macaddr received from PF\n");
2626                                 rte_ether_addr_copy(
2627                                         (struct rte_ether_addr *)&vf_mac,
2628                                         &eth_dev->data->mac_addrs[0]);
2629                                 rte_ether_addr_copy(
2630                                         &eth_dev->data->mac_addrs[0],
2631                                         &adapter->primary_mac);
2632                         } else {
2633                                 DP_ERR(edev, "No VF macaddr assigned\n");
2634                         }
2635                 }
2636         }
2637
2638         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2639
2640         /* Bring-up the link */
2641         qede_dev_set_link_state(eth_dev, true);
2642
2643         adapter->num_tx_queues = 0;
2644         adapter->num_rx_queues = 0;
2645         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2646         SLIST_INIT(&adapter->vlan_list_head);
2647         SLIST_INIT(&adapter->uc_list_head);
2648         SLIST_INIT(&adapter->mc_list_head);
2649         adapter->mtu = RTE_ETHER_MTU;
2650         adapter->vport_started = false;
2651
2652         /* VF tunnel offloads is enabled by default in PF driver */
2653         adapter->vxlan.num_filters = 0;
2654         adapter->geneve.num_filters = 0;
2655         adapter->ipgre.num_filters = 0;
2656         if (is_vf) {
2657                 adapter->vxlan.enable = true;
2658                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2659                                              ETH_TUNNEL_FILTER_IVLAN;
2660                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2661                 adapter->geneve.enable = true;
2662                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2663                                               ETH_TUNNEL_FILTER_IVLAN;
2664                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2665                 adapter->ipgre.enable = true;
2666                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2667                                              ETH_TUNNEL_FILTER_IVLAN;
2668         } else {
2669                 adapter->vxlan.enable = false;
2670                 adapter->geneve.enable = false;
2671                 adapter->ipgre.enable = false;
2672         }
2673
2674         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2675                 adapter->primary_mac.addr_bytes[0],
2676                 adapter->primary_mac.addr_bytes[1],
2677                 adapter->primary_mac.addr_bytes[2],
2678                 adapter->primary_mac.addr_bytes[3],
2679                 adapter->primary_mac.addr_bytes[4],
2680                 adapter->primary_mac.addr_bytes[5]);
2681
2682         DP_INFO(edev, "Device initialized\n");
2683
2684         return 0;
2685
2686 err:
2687         if (do_once) {
2688                 qede_print_adapter_info(adapter);
2689                 do_once = false;
2690         }
2691         return rc;
2692 }
2693
2694 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2695 {
2696         return qede_common_dev_init(eth_dev, 1);
2697 }
2698
2699 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2700 {
2701         return qede_common_dev_init(eth_dev, 0);
2702 }
2703
2704 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2705 {
2706         struct qede_dev *qdev = eth_dev->data->dev_private;
2707         struct ecore_dev *edev = &qdev->edev;
2708
2709         PMD_INIT_FUNC_TRACE(edev);
2710
2711         /* only uninitialize in the primary process */
2712         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2713                 return 0;
2714
2715         /* safe to close dev here */
2716         qede_dev_close(eth_dev);
2717
2718         eth_dev->dev_ops = NULL;
2719         eth_dev->rx_pkt_burst = NULL;
2720         eth_dev->tx_pkt_burst = NULL;
2721
2722         return 0;
2723 }
2724
2725 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2726 {
2727         return qede_dev_common_uninit(eth_dev);
2728 }
2729
2730 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2731 {
2732         return qede_dev_common_uninit(eth_dev);
2733 }
2734
2735 static const struct rte_pci_id pci_id_qedevf_map[] = {
2736 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2737         {
2738                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2739         },
2740         {
2741                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2742         },
2743         {
2744                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2745         },
2746         {.vendor_id = 0,}
2747 };
2748
2749 static const struct rte_pci_id pci_id_qede_map[] = {
2750 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2751         {
2752                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2753         },
2754         {
2755                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2756         },
2757         {
2758                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2759         },
2760         {
2761                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2762         },
2763         {
2764                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2765         },
2766         {
2767                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2768         },
2769         {
2770                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2771         },
2772         {
2773                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2774         },
2775         {
2776                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2777         },
2778         {
2779                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2780         },
2781         {.vendor_id = 0,}
2782 };
2783
2784 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2785         struct rte_pci_device *pci_dev)
2786 {
2787         return rte_eth_dev_pci_generic_probe(pci_dev,
2788                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2789 }
2790
2791 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2792 {
2793         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2794 }
2795
2796 static struct rte_pci_driver rte_qedevf_pmd = {
2797         .id_table = pci_id_qedevf_map,
2798         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2799         .probe = qedevf_eth_dev_pci_probe,
2800         .remove = qedevf_eth_dev_pci_remove,
2801 };
2802
2803 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2804         struct rte_pci_device *pci_dev)
2805 {
2806         return rte_eth_dev_pci_generic_probe(pci_dev,
2807                 sizeof(struct qede_dev), qede_eth_dev_init);
2808 }
2809
2810 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2811 {
2812         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2813 }
2814
2815 static struct rte_pci_driver rte_qede_pmd = {
2816         .id_table = pci_id_qede_map,
2817         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2818         .probe = qede_eth_dev_pci_probe,
2819         .remove = qede_eth_dev_pci_remove,
2820 };
2821
2822 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2823 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2824 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2825 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2826 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2827 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2828
2829 RTE_INIT(qede_init_log)
2830 {
2831         qede_logtype_init = rte_log_register("pmd.net.qede.init");
2832         if (qede_logtype_init >= 0)
2833                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2834         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2835         if (qede_logtype_driver >= 0)
2836                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
2837 }