drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 /* Globals */
  14 int qede_logtype_init;
  15 int qede_logtype_driver;
  16
  17 static const struct qed_eth_ops *qed_ops;
  18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  20
  21 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  22
  23 struct rte_qede_xstats_name_off {
  24         char name[RTE_ETH_XSTATS_NAME_SIZE];
  25         uint64_t offset;
  26 };
  27
  28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  29         {"rx_unicast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  31         {"rx_multicast_bytes",
  32                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  33         {"rx_broadcast_bytes",
  34                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  35         {"rx_unicast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  37         {"rx_multicast_packets",
  38                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  39         {"rx_broadcast_packets",
  40                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  41
  42         {"tx_unicast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  44         {"tx_multicast_bytes",
  45                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  46         {"tx_broadcast_bytes",
  47                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  48         {"tx_unicast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  50         {"tx_multicast_packets",
  51                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  52         {"tx_broadcast_packets",
  53                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  54
  55         {"rx_64_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  57         {"rx_65_to_127_byte_packets",
  58                 offsetof(struct ecore_eth_stats_common,
  59                          rx_65_to_127_byte_packets)},
  60         {"rx_128_to_255_byte_packets",
  61                 offsetof(struct ecore_eth_stats_common,
  62                          rx_128_to_255_byte_packets)},
  63         {"rx_256_to_511_byte_packets",
  64                 offsetof(struct ecore_eth_stats_common,
  65                          rx_256_to_511_byte_packets)},
  66         {"rx_512_to_1023_byte_packets",
  67                 offsetof(struct ecore_eth_stats_common,
  68                          rx_512_to_1023_byte_packets)},
  69         {"rx_1024_to_1518_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          rx_1024_to_1518_byte_packets)},
  72         {"tx_64_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  74         {"tx_65_to_127_byte_packets",
  75                 offsetof(struct ecore_eth_stats_common,
  76                          tx_65_to_127_byte_packets)},
  77         {"tx_128_to_255_byte_packets",
  78                 offsetof(struct ecore_eth_stats_common,
  79                          tx_128_to_255_byte_packets)},
  80         {"tx_256_to_511_byte_packets",
  81                 offsetof(struct ecore_eth_stats_common,
  82                          tx_256_to_511_byte_packets)},
  83         {"tx_512_to_1023_byte_packets",
  84                 offsetof(struct ecore_eth_stats_common,
  85                          tx_512_to_1023_byte_packets)},
  86         {"tx_1024_to_1518_byte_packets",
  87                 offsetof(struct ecore_eth_stats_common,
  88                          tx_1024_to_1518_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  96         {"tx_pause_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  98         {"rx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 100         {"tx_priority_flow_control_frames",
 101                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 102
 103         {"rx_crc_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 105         {"rx_align_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 107         {"rx_carrier_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 109         {"rx_oversize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 111         {"rx_jabber_errors",
 112                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 113         {"rx_undersize_packet_errors",
 114                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 115         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 116         {"rx_host_buffer_not_available",
 117                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 118         /* Number of packets discarded because they are bigger than MTU */
 119         {"rx_packet_too_big_discards",
 120                 offsetof(struct ecore_eth_stats_common,
 121                          packet_too_big_discard)},
 122         {"rx_ttl_zero_discards",
 123                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 124         {"rx_multi_function_tag_filter_discards",
 125                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 126         {"rx_mac_filter_discards",
 127                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 128         {"rx_gft_filter_drop",
 129                 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
 130         {"rx_hw_buffer_truncates",
 131                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 132         {"rx_hw_buffer_discards",
 133                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 134         {"tx_error_drop_packets",
 135                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 136
 137         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 138         {"rx_mac_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 140         {"rx_mac_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 142         {"rx_mac_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 144         {"rx_mac_frames_ok",
 145                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 146         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 147         {"tx_mac_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 149         {"tx_mac_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 151         {"tx_mac_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 153
 154         {"lro_coalesced_packets",
 155                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 156         {"lro_coalesced_events",
 157                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 158         {"lro_aborts_num",
 159                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 160         {"lro_not_coalesced_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          tpa_not_coalesced_pkts)},
 163         {"lro_coalesced_bytes",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          tpa_coalesced_bytes)},
 166 };
 167
 168 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 169         {"rx_1519_to_1522_byte_packets",
 170                 offsetof(struct ecore_eth_stats, bb) +
 171                 offsetof(struct ecore_eth_stats_bb,
 172                          rx_1519_to_1522_byte_packets)},
 173         {"rx_1519_to_2047_byte_packets",
 174                 offsetof(struct ecore_eth_stats, bb) +
 175                 offsetof(struct ecore_eth_stats_bb,
 176                          rx_1519_to_2047_byte_packets)},
 177         {"rx_2048_to_4095_byte_packets",
 178                 offsetof(struct ecore_eth_stats, bb) +
 179                 offsetof(struct ecore_eth_stats_bb,
 180                          rx_2048_to_4095_byte_packets)},
 181         {"rx_4096_to_9216_byte_packets",
 182                 offsetof(struct ecore_eth_stats, bb) +
 183                 offsetof(struct ecore_eth_stats_bb,
 184                          rx_4096_to_9216_byte_packets)},
 185         {"rx_9217_to_16383_byte_packets",
 186                 offsetof(struct ecore_eth_stats, bb) +
 187                 offsetof(struct ecore_eth_stats_bb,
 188                          rx_9217_to_16383_byte_packets)},
 189
 190         {"tx_1519_to_2047_byte_packets",
 191                 offsetof(struct ecore_eth_stats, bb) +
 192                 offsetof(struct ecore_eth_stats_bb,
 193                          tx_1519_to_2047_byte_packets)},
 194         {"tx_2048_to_4095_byte_packets",
 195                 offsetof(struct ecore_eth_stats, bb) +
 196                 offsetof(struct ecore_eth_stats_bb,
 197                          tx_2048_to_4095_byte_packets)},
 198         {"tx_4096_to_9216_byte_packets",
 199                 offsetof(struct ecore_eth_stats, bb) +
 200                 offsetof(struct ecore_eth_stats_bb,
 201                          tx_4096_to_9216_byte_packets)},
 202         {"tx_9217_to_16383_byte_packets",
 203                 offsetof(struct ecore_eth_stats, bb) +
 204                 offsetof(struct ecore_eth_stats_bb,
 205                          tx_9217_to_16383_byte_packets)},
 206
 207         {"tx_lpi_entry_count",
 208                 offsetof(struct ecore_eth_stats, bb) +
 209                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 210         {"tx_total_collisions",
 211                 offsetof(struct ecore_eth_stats, bb) +
 212                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 213 };
 214
 215 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 216         {"rx_1519_to_max_byte_packets",
 217                 offsetof(struct ecore_eth_stats, ah) +
 218                 offsetof(struct ecore_eth_stats_ah,
 219                          rx_1519_to_max_byte_packets)},
 220         {"tx_1519_to_max_byte_packets",
 221                 offsetof(struct ecore_eth_stats, ah) +
 222                 offsetof(struct ecore_eth_stats_ah,
 223                          tx_1519_to_max_byte_packets)},
 224 };
 225
 226 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 227         {"rx_q_segments",
 228                 offsetof(struct qede_rx_queue, rx_segs)},
 229         {"rx_q_hw_errors",
 230                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 231         {"rx_q_allocation_errors",
 232                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 233 };
 234
 235 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 236 {
 237         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 238 }
 239
 240 static void
 241 qede_interrupt_handler_intx(void *param)
 242 {
 243         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 244         struct qede_dev *qdev = eth_dev->data->dev_private;
 245         struct ecore_dev *edev = &qdev->edev;
 246         u64 status;
 247
 248         /* Check if our device actually raised an interrupt */
 249         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 250         if (status & 0x1) {
 251                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 252
 253                 if (rte_intr_ack(eth_dev->intr_handle))
 254                         DP_ERR(edev, "rte_intr_ack failed\n");
 255         }
 256 }
 257
 258 static void
 259 qede_interrupt_handler(void *param)
 260 {
 261         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 262         struct qede_dev *qdev = eth_dev->data->dev_private;
 263         struct ecore_dev *edev = &qdev->edev;
 264
 265         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 266         if (rte_intr_ack(eth_dev->intr_handle))
 267                 DP_ERR(edev, "rte_intr_ack failed\n");
 268 }
 269
 270 static void
 271 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 272 {
 273         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 274         qdev->ops = qed_ops;
 275 }
 276
 277 static void qede_print_adapter_info(struct qede_dev *qdev)
 278 {
 279         struct ecore_dev *edev = &qdev->edev;
 280         struct qed_dev_info *info = &qdev->dev_info.common;
 281         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 282         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 283
 284         DP_INFO(edev, "*********************************\n");
 285         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 286         DP_INFO(edev, " Chip details : %s %c%d\n",
 287                   ECORE_IS_BB(edev) ? "BB" : "AH",
 288                   'A' + edev->chip_rev,
 289                   (int)edev->chip_metal);
 290         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 291                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 292         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 293                  ver_str, QEDE_PMD_VERSION);
 294         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 295         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 296
 297         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 298                  "%d.%d.%d.%d",
 299                 (info->mfw_rev >> 24) & 0xff,
 300                 (info->mfw_rev >> 16) & 0xff,
 301                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 302         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 303         DP_INFO(edev, " Firmware file : %s\n", qede_fw_file);
 304         DP_INFO(edev, "*********************************\n");
 305 }
 306
 307 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 308 {
 309         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 310         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 311         unsigned int i = 0, j = 0, qid;
 312         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 313         struct qede_tx_queue *txq;
 314
 315         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 316
 317         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 318                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 319         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 320                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 321
 322         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 323                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 324                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 325                             sizeof(uint64_t));
 326                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 327                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 328                             sizeof(uint64_t));
 329                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 330                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 331                             sizeof(uint64_t));
 332
 333                 if (xstats)
 334                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 335                                 OSAL_MEMSET((((char *)
 336                                               (qdev->fp_array[qid].rxq)) +
 337                                              qede_rxq_xstats_strings[j].offset),
 338                                             0,
 339                                             sizeof(uint64_t));
 340
 341                 i++;
 342                 if (i == rxq_stat_cntrs)
 343                         break;
 344         }
 345
 346         i = 0;
 347
 348         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 349                 txq = qdev->fp_array[qid].txq;
 350
 351                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 352                                 (((uint64_t)(uintptr_t)(txq)) +
 353                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 354                             sizeof(uint64_t));
 355
 356                 i++;
 357                 if (i == txq_stat_cntrs)
 358                         break;
 359         }
 360 }
 361
 362 static int
 363 qede_stop_vport(struct ecore_dev *edev)
 364 {
 365         struct ecore_hwfn *p_hwfn;
 366         uint8_t vport_id;
 367         int rc;
 368         int i;
 369
 370         vport_id = 0;
 371         for_each_hwfn(edev, i) {
 372                 p_hwfn = &edev->hwfns[i];
 373                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 374                                          vport_id);
 375                 if (rc != ECORE_SUCCESS) {
 376                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 377                         return rc;
 378                 }
 379         }
 380
 381         DP_INFO(edev, "vport stopped\n");
 382
 383         return 0;
 384 }
 385
 386 static int
 387 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 388 {
 389         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 390         struct ecore_sp_vport_start_params params;
 391         struct ecore_hwfn *p_hwfn;
 392         int rc;
 393         int i;
 394
 395         if (qdev->vport_started)
 396                 qede_stop_vport(edev);
 397
 398         memset(&params, 0, sizeof(params));
 399         params.vport_id = 0;
 400         params.mtu = mtu;
 401         /* @DPDK - Disable FW placement */
 402         params.zero_placement_offset = 1;
 403         for_each_hwfn(edev, i) {
 404                 p_hwfn = &edev->hwfns[i];
 405                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 406                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 407                 rc = ecore_sp_vport_start(p_hwfn, &params);
 408                 if (rc != ECORE_SUCCESS) {
 409                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 410                         return rc;
 411                 }
 412         }
 413         ecore_reset_vport_stats(edev);
 414         qdev->vport_started = true;
 415         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 416
 417         return 0;
 418 }
 419
 420 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 421 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 422
 423 /* Activate or deactivate vport via vport-update */
 424 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 425 {
 426         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 427         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 428         struct ecore_sp_vport_update_params params;
 429         struct ecore_hwfn *p_hwfn;
 430         uint8_t i;
 431         int rc = -1;
 432
 433         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 434         params.vport_id = 0;
 435         params.update_vport_active_rx_flg = 1;
 436         params.update_vport_active_tx_flg = 1;
 437         params.vport_active_rx_flg = flg;
 438         params.vport_active_tx_flg = flg;
 439         if (~qdev->enable_tx_switching & flg) {
 440                 params.update_tx_switching_flg = 1;
 441                 params.tx_switching_flg = !flg;
 442         }
 443         for_each_hwfn(edev, i) {
 444                 p_hwfn = &edev->hwfns[i];
 445                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 446                 rc = ecore_sp_vport_update(p_hwfn, &params,
 447                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 448                 if (rc != ECORE_SUCCESS) {
 449                         DP_ERR(edev, "Failed to update vport\n");
 450                         break;
 451                 }
 452         }
 453         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 454
 455         return rc;
 456 }
 457
 458 static void
 459 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 460                            uint16_t mtu, bool enable)
 461 {
 462         /* Enable LRO in split mode */
 463         sge_tpa_params->tpa_ipv4_en_flg = enable;
 464         sge_tpa_params->tpa_ipv6_en_flg = enable;
 465         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 466         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 467         /* set if tpa enable changes */
 468         sge_tpa_params->update_tpa_en_flg = 1;
 469         /* set if tpa parameters should be handled */
 470         sge_tpa_params->update_tpa_param_flg = enable;
 471
 472         sge_tpa_params->max_buffers_per_cqe = 20;
 473         /* Enable TPA in split mode. In this mode each TPA segment
 474          * starts on the new BD, so there is one BD per segment.
 475          */
 476         sge_tpa_params->tpa_pkt_split_flg = 1;
 477         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 478         sge_tpa_params->tpa_gro_consistent_flg = 0;
 479         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 480         sge_tpa_params->tpa_max_size = 0x7FFF;
 481         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 482         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 483 }
 484
 485 /* Enable/disable LRO via vport-update */
 486 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 487 {
 488         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 489         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 490         struct ecore_sp_vport_update_params params;
 491         struct ecore_sge_tpa_params tpa_params;
 492         struct ecore_hwfn *p_hwfn;
 493         int rc;
 494         int i;
 495
 496         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 497         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 498         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 499         params.vport_id = 0;
 500         params.sge_tpa_params = &tpa_params;
 501         for_each_hwfn(edev, i) {
 502                 p_hwfn = &edev->hwfns[i];
 503                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 504                 rc = ecore_sp_vport_update(p_hwfn, &params,
 505                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 506                 if (rc != ECORE_SUCCESS) {
 507                         DP_ERR(edev, "Failed to update LRO\n");
 508                         return -1;
 509                 }
 510         }
 511         qdev->enable_lro = flg;
 512         eth_dev->data->lro = flg;
 513
 514         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 515
 516         return 0;
 517 }
 518
 519 static int
 520 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 521                              enum qed_filter_rx_mode_type type)
 522 {
 523         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 524         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 525         struct ecore_filter_accept_flags flags;
 526
 527         memset(&flags, 0, sizeof(flags));
 528
 529         flags.update_rx_mode_config = 1;
 530         flags.update_tx_mode_config = 1;
 531         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 532                 ECORE_ACCEPT_MCAST_MATCHED |
 533                 ECORE_ACCEPT_BCAST;
 534
 535         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 536                 ECORE_ACCEPT_MCAST_MATCHED |
 537                 ECORE_ACCEPT_BCAST;
 538
 539         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 540                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 541                 if (IS_VF(edev)) {
 542                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 543                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 544                 }
 545         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 546                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 547         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 548                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 549                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 550                         ECORE_ACCEPT_MCAST_UNMATCHED;
 551         }
 552
 553         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 554                         ECORE_SPQ_MODE_CB, NULL);
 555 }
 556
 557 int
 558 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 559                   bool add)
 560 {
 561         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 562         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 563         struct qede_ucast_entry *tmp = NULL;
 564         struct qede_ucast_entry *u;
 565         struct rte_ether_addr *mac_addr;
 566
 567         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 568         if (add) {
 569                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 570                         if ((memcmp(mac_addr, &tmp->mac,
 571                                     RTE_ETHER_ADDR_LEN) == 0) &&
 572                              ucast->vni == tmp->vni &&
 573                              ucast->vlan == tmp->vlan) {
 574                                 DP_INFO(edev, "Unicast MAC is already added"
 575                                         " with vlan = %u, vni = %u\n",
 576                                         ucast->vlan,  ucast->vni);
 577                                         return 0;
 578                         }
 579                 }
 580                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 581                                RTE_CACHE_LINE_SIZE);
 582                 if (!u) {
 583                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 584                         return -ENOMEM;
 585                 }
 586                 rte_ether_addr_copy(mac_addr, &u->mac);
 587                 u->vlan = ucast->vlan;
 588                 u->vni = ucast->vni;
 589                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 590                 qdev->num_uc_addr++;
 591         } else {
 592                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 593                         if ((memcmp(mac_addr, &tmp->mac,
 594                                     RTE_ETHER_ADDR_LEN) == 0) &&
 595                             ucast->vlan == tmp->vlan      &&
 596                             ucast->vni == tmp->vni)
 597                         break;
 598                 }
 599                 if (tmp == NULL) {
 600                         DP_INFO(edev, "Unicast MAC is not found\n");
 601                         return -EINVAL;
 602                 }
 603                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 604                 qdev->num_uc_addr--;
 605         }
 606
 607         return 0;
 608 }
 609
 610 static int
 611 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 612                 struct rte_ether_addr *mc_addrs,
 613                 uint32_t mc_addrs_num)
 614 {
 615         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 616         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 617         struct ecore_filter_mcast mcast;
 618         struct qede_mcast_entry *m = NULL;
 619         uint8_t i;
 620         int rc;
 621
 622         for (i = 0; i < mc_addrs_num; i++) {
 623                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 624                                RTE_CACHE_LINE_SIZE);
 625                 if (!m) {
 626                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 627                         return -ENOMEM;
 628                 }
 629                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 630                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 631         }
 632         memset(&mcast, 0, sizeof(mcast));
 633         mcast.num_mc_addrs = mc_addrs_num;
 634         mcast.opcode = ECORE_FILTER_ADD;
 635         for (i = 0; i < mc_addrs_num; i++)
 636                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 637                                                         &mcast.mac[i]);
 638         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 639         if (rc != ECORE_SUCCESS) {
 640                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 641                 return -1;
 642         }
 643
 644         return 0;
 645 }
 646
 647 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 648 {
 649         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 650         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 651         struct qede_mcast_entry *tmp = NULL;
 652         struct ecore_filter_mcast mcast;
 653         int j;
 654         int rc;
 655
 656         memset(&mcast, 0, sizeof(mcast));
 657         mcast.num_mc_addrs = qdev->num_mc_addr;
 658         mcast.opcode = ECORE_FILTER_REMOVE;
 659         j = 0;
 660         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 661                 rte_ether_addr_copy(&tmp->mac,
 662                                 (struct rte_ether_addr *)&mcast.mac[j]);
 663                 j++;
 664         }
 665         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 666         if (rc != ECORE_SUCCESS) {
 667                 DP_ERR(edev, "Failed to delete multicast filter\n");
 668                 return -1;
 669         }
 670         /* Init the list */
 671         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 672                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 673                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 674         }
 675         SLIST_INIT(&qdev->mc_list_head);
 676
 677         return 0;
 678 }
 679
 680 enum _ecore_status_t
 681 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 682                  bool add)
 683 {
 684         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 685         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 686         enum _ecore_status_t rc = ECORE_INVAL;
 687
 688         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 689                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 690                               " Please enable promisc mode\n");
 691                         return ECORE_INVAL;
 692         }
 693
 694         rc = qede_ucast_filter(eth_dev, ucast, add);
 695         if (rc == 0)
 696                 rc = ecore_filter_ucast_cmd(edev, ucast,
 697                                             ECORE_SPQ_MODE_CB, NULL);
 698         /* Indicate error only for add filter operation.
 699          * Delete filter operations are not severe.
 700          */
 701         if ((rc != ECORE_SUCCESS) && add)
 702                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 703                        rc, add);
 704
 705         return rc;
 706 }
 707
 708 static int
 709 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 710                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 711 {
 712         struct ecore_filter_ucast ucast;
 713         int re;
 714
 715         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 716                 return -EINVAL;
 717
 718         qede_set_ucast_cmn_params(&ucast);
 719         ucast.opcode = ECORE_FILTER_ADD;
 720         ucast.type = ECORE_FILTER_MAC;
 721         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 722         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 723         return re;
 724 }
 725
 726 static void
 727 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 728 {
 729         struct qede_dev *qdev = eth_dev->data->dev_private;
 730         struct ecore_dev *edev = &qdev->edev;
 731         struct ecore_filter_ucast ucast;
 732
 733         PMD_INIT_FUNC_TRACE(edev);
 734
 735         if (index >= qdev->dev_info.num_mac_filters) {
 736                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 737                        index, qdev->dev_info.num_mac_filters);
 738                 return;
 739         }
 740
 741         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 742                 return;
 743
 744         qede_set_ucast_cmn_params(&ucast);
 745         ucast.opcode = ECORE_FILTER_REMOVE;
 746         ucast.type = ECORE_FILTER_MAC;
 747
 748         /* Use the index maintained by rte */
 749         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 750                         (struct rte_ether_addr *)&ucast.mac);
 751
 752         qede_mac_int_ops(eth_dev, &ucast, false);
 753 }
 754
 755 static int
 756 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 757 {
 758         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 759         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 760
 761         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 762                                                mac_addr->addr_bytes)) {
 763                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 764                 return -EPERM;
 765         }
 766
 767         qede_mac_addr_remove(eth_dev, 0);
 768
 769         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 770 }
 771
 772 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 773 {
 774         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 775         struct ecore_sp_vport_update_params params;
 776         struct ecore_hwfn *p_hwfn;
 777         uint8_t i;
 778         int rc;
 779
 780         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 781         params.vport_id = 0;
 782         params.update_accept_any_vlan_flg = 1;
 783         params.accept_any_vlan = flg;
 784         for_each_hwfn(edev, i) {
 785                 p_hwfn = &edev->hwfns[i];
 786                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 787                 rc = ecore_sp_vport_update(p_hwfn, &params,
 788                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 789                 if (rc != ECORE_SUCCESS) {
 790                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 791                         return;
 792                 }
 793         }
 794
 795         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 796 }
 797
 798 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 799 {
 800         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 801         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 802         struct ecore_sp_vport_update_params params;
 803         struct ecore_hwfn *p_hwfn;
 804         uint8_t i;
 805         int rc;
 806
 807         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 808         params.vport_id = 0;
 809         params.update_inner_vlan_removal_flg = 1;
 810         params.inner_vlan_removal_flg = flg;
 811         for_each_hwfn(edev, i) {
 812                 p_hwfn = &edev->hwfns[i];
 813                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 814                 rc = ecore_sp_vport_update(p_hwfn, &params,
 815                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 816                 if (rc != ECORE_SUCCESS) {
 817                         DP_ERR(edev, "Failed to update vport\n");
 818                         return -1;
 819                 }
 820         }
 821
 822         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 823         return 0;
 824 }
 825
 826 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 827                                 uint16_t vlan_id, int on)
 828 {
 829         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 830         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 831         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 832         struct qede_vlan_entry *tmp = NULL;
 833         struct qede_vlan_entry *vlan;
 834         struct ecore_filter_ucast ucast;
 835         int rc;
 836
 837         if (on) {
 838                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 839                         DP_ERR(edev, "Reached max VLAN filter limit"
 840                                       " enabling accept_any_vlan\n");
 841                         qede_config_accept_any_vlan(qdev, true);
 842                         return 0;
 843                 }
 844
 845                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 846                         if (tmp->vid == vlan_id) {
 847                                 DP_INFO(edev, "VLAN %u already configured\n",
 848                                         vlan_id);
 849                                 return 0;
 850                         }
 851                 }
 852
 853                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 854                                   RTE_CACHE_LINE_SIZE);
 855
 856                 if (!vlan) {
 857                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 858                         return -ENOMEM;
 859                 }
 860
 861                 qede_set_ucast_cmn_params(&ucast);
 862                 ucast.opcode = ECORE_FILTER_ADD;
 863                 ucast.type = ECORE_FILTER_VLAN;
 864                 ucast.vlan = vlan_id;
 865                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 866                                             NULL);
 867                 if (rc != 0) {
 868                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 869                                rc);
 870                         rte_free(vlan);
 871                 } else {
 872                         vlan->vid = vlan_id;
 873                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 874                         qdev->configured_vlans++;
 875                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 876                                 vlan_id, qdev->configured_vlans);
 877                 }
 878         } else {
 879                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 880                         if (tmp->vid == vlan_id)
 881                                 break;
 882                 }
 883
 884                 if (!tmp) {
 885                         if (qdev->configured_vlans == 0) {
 886                                 DP_INFO(edev,
 887                                         "No VLAN filters configured yet\n");
 888                                 return 0;
 889                         }
 890
 891                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 892                         return -EINVAL;
 893                 }
 894
 895                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 896
 897                 qede_set_ucast_cmn_params(&ucast);
 898                 ucast.opcode = ECORE_FILTER_REMOVE;
 899                 ucast.type = ECORE_FILTER_VLAN;
 900                 ucast.vlan = vlan_id;
 901                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 902                                             NULL);
 903                 if (rc != 0) {
 904                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 905                                vlan_id, rc);
 906                 } else {
 907                         qdev->configured_vlans--;
 908                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 909                                 vlan_id, qdev->configured_vlans);
 910                 }
 911         }
 912
 913         return rc;
 914 }
 915
 916 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 917 {
 918         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 919         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 920         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 921
 922         if (mask & ETH_VLAN_STRIP_MASK) {
 923                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 924                         (void)qede_vlan_stripping(eth_dev, 1);
 925                 else
 926                         (void)qede_vlan_stripping(eth_dev, 0);
 927         }
 928
 929         if (mask & ETH_VLAN_FILTER_MASK) {
 930                 /* VLAN filtering kicks in when a VLAN is added */
 931                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 932                         qede_vlan_filter_set(eth_dev, 0, 1);
 933                 } else {
 934                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 935                                 DP_ERR(edev,
 936                                   " Please remove existing VLAN filters"
 937                                   " before disabling VLAN filtering\n");
 938                                 /* Signal app that VLAN filtering is still
 939                                  * enabled
 940                                  */
 941                                 eth_dev->data->dev_conf.rxmode.offloads |=
 942                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
 943                         } else {
 944                                 qede_vlan_filter_set(eth_dev, 0, 0);
 945                         }
 946                 }
 947         }
 948
 949         if (mask & ETH_VLAN_EXTEND_MASK)
 950                 DP_ERR(edev, "Extend VLAN not supported\n");
 951
 952         qdev->vlan_offload_mask = mask;
 953
 954         DP_INFO(edev, "VLAN offload mask %d\n", mask);
 955
 956         return 0;
 957 }
 958
 959 static void qede_prandom_bytes(uint32_t *buff)
 960 {
 961         uint8_t i;
 962
 963         srand((unsigned int)time(NULL));
 964         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 965                 buff[i] = rand();
 966 }
 967
 968 int qede_config_rss(struct rte_eth_dev *eth_dev)
 969 {
 970         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 971         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 972         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 973         struct rte_eth_rss_reta_entry64 reta_conf[2];
 974         struct rte_eth_rss_conf rss_conf;
 975         uint32_t i, id, pos, q;
 976
 977         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 978         if (!rss_conf.rss_key) {
 979                 DP_INFO(edev, "Applying driver default key\n");
 980                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 981                 qede_prandom_bytes(&def_rss_key[0]);
 982                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 983         }
 984
 985         /* Configure RSS hash */
 986         if (qede_rss_hash_update(eth_dev, &rss_conf))
 987                 return -EINVAL;
 988
 989         /* Configure default RETA */
 990         memset(reta_conf, 0, sizeof(reta_conf));
 991         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 992                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
 993
 994         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 995                 id = i / RTE_RETA_GROUP_SIZE;
 996                 pos = i % RTE_RETA_GROUP_SIZE;
 997                 q = i % QEDE_RSS_COUNT(eth_dev);
 998                 reta_conf[id].reta[pos] = q;
 999         }
1000         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1001                                  ECORE_RSS_IND_TABLE_SIZE))
1002                 return -EINVAL;
1003
1004         return 0;
1005 }
1006
1007 static void qede_fastpath_start(struct ecore_dev *edev)
1008 {
1009         struct ecore_hwfn *p_hwfn;
1010         int i;
1011
1012         for_each_hwfn(edev, i) {
1013                 p_hwfn = &edev->hwfns[i];
1014                 ecore_hw_start_fastpath(p_hwfn);
1015         }
1016 }
1017
1018 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1019 {
1020         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1021         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1022         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1023
1024         PMD_INIT_FUNC_TRACE(edev);
1025
1026         /* Update MTU only if it has changed */
1027         if (eth_dev->data->mtu != qdev->mtu) {
1028                 if (qede_update_mtu(eth_dev, qdev->mtu))
1029                         goto err;
1030         }
1031
1032         /* Configure TPA parameters */
1033         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1034                 if (qede_enable_tpa(eth_dev, true))
1035                         return -EINVAL;
1036                 /* Enable scatter mode for LRO */
1037                 if (!eth_dev->data->scattered_rx)
1038                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1039         }
1040
1041         /* Start queues */
1042         if (qede_start_queues(eth_dev))
1043                 goto err;
1044
1045         if (IS_PF(edev))
1046                 qede_reset_queue_stats(qdev, true);
1047
1048         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1049          * enabling RSS. Hence RSS configuration is deferred upto this point.
1050          * Also, we would like to retain similar behavior in PF case, so we
1051          * don't do PF/VF specific check here.
1052          */
1053         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1054                 if (qede_config_rss(eth_dev))
1055                         goto err;
1056
1057         /* Enable vport*/
1058         if (qede_activate_vport(eth_dev, true))
1059                 goto err;
1060
1061         /* Update link status */
1062         qede_link_update(eth_dev, 0);
1063
1064         /* Start/resume traffic */
1065         qede_fastpath_start(edev);
1066
1067         DP_INFO(edev, "Device started\n");
1068
1069         return 0;
1070 err:
1071         DP_ERR(edev, "Device start fails\n");
1072         return -1; /* common error code is < 0 */
1073 }
1074
1075 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1076 {
1077         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1078         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1079
1080         PMD_INIT_FUNC_TRACE(edev);
1081
1082         /* Disable vport */
1083         if (qede_activate_vport(eth_dev, false))
1084                 return;
1085
1086         if (qdev->enable_lro)
1087                 qede_enable_tpa(eth_dev, false);
1088
1089         /* Stop queues */
1090         qede_stop_queues(eth_dev);
1091
1092         /* Disable traffic */
1093         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1094
1095         DP_INFO(edev, "Device is stopped\n");
1096 }
1097
1098 static const char * const valid_args[] = {
1099         QEDE_NPAR_TX_SWITCHING,
1100         QEDE_VF_TX_SWITCHING,
1101         NULL,
1102 };
1103
1104 static int qede_args_check(const char *key, const char *val, void *opaque)
1105 {
1106         unsigned long tmp;
1107         int ret = 0;
1108         struct rte_eth_dev *eth_dev = opaque;
1109         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1110         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1111
1112         errno = 0;
1113         tmp = strtoul(val, NULL, 0);
1114         if (errno) {
1115                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1116                 return errno;
1117         }
1118
1119         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1120             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1121                 qdev->enable_tx_switching = !!tmp;
1122                 DP_INFO(edev, "Disabling %s tx-switching\n",
1123                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1124                         "VF" : "NPAR");
1125         }
1126
1127         return ret;
1128 }
1129
1130 static int qede_args(struct rte_eth_dev *eth_dev)
1131 {
1132         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1133         struct rte_kvargs *kvlist;
1134         struct rte_devargs *devargs;
1135         int ret;
1136         int i;
1137
1138         devargs = pci_dev->device.devargs;
1139         if (!devargs)
1140                 return 0; /* return success */
1141
1142         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1143         if (kvlist == NULL)
1144                 return -EINVAL;
1145
1146          /* Process parameters. */
1147         for (i = 0; (valid_args[i] != NULL); ++i) {
1148                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1149                         ret = rte_kvargs_process(kvlist, valid_args[i],
1150                                                  qede_args_check, eth_dev);
1151                         if (ret != ECORE_SUCCESS) {
1152                                 rte_kvargs_free(kvlist);
1153                                 return ret;
1154                         }
1155                 }
1156         }
1157         rte_kvargs_free(kvlist);
1158
1159         return 0;
1160 }
1161
1162 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1163 {
1164         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1165         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1166         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1167         int ret;
1168
1169         PMD_INIT_FUNC_TRACE(edev);
1170
1171         /* We need to have min 1 RX queue.There is no min check in
1172          * rte_eth_dev_configure(), so we are checking it here.
1173          */
1174         if (eth_dev->data->nb_rx_queues == 0) {
1175                 DP_ERR(edev, "Minimum one RX queue is required\n");
1176                 return -EINVAL;
1177         }
1178
1179         /* Enable Tx switching by default */
1180         qdev->enable_tx_switching = 1;
1181
1182         /* Parse devargs and fix up rxmode */
1183         if (qede_args(eth_dev))
1184                 DP_NOTICE(edev, false,
1185                           "Invalid devargs supplied, requested change will not take effect\n");
1186
1187         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1188               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1189                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1190                 return -ENOTSUP;
1191         }
1192         /* Flow director mode check */
1193         if (qede_check_fdir_support(eth_dev))
1194                 return -ENOTSUP;
1195
1196         qede_dealloc_fp_resc(eth_dev);
1197         qdev->num_tx_queues = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1198         qdev->num_rx_queues = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1199
1200         if (qede_alloc_fp_resc(qdev))
1201                 return -ENOMEM;
1202
1203         /* If jumbo enabled adjust MTU */
1204         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1205                 eth_dev->data->mtu =
1206                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1207                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1208
1209         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1210                 eth_dev->data->scattered_rx = 1;
1211
1212         if (qede_start_vport(qdev, eth_dev->data->mtu))
1213                 return -1;
1214
1215         qdev->mtu = eth_dev->data->mtu;
1216
1217         /* Enable VLAN offloads by default */
1218         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1219                                              ETH_VLAN_FILTER_MASK);
1220         if (ret)
1221                 return ret;
1222
1223         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1224                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1225
1226         if (ECORE_IS_CMT(edev))
1227                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1228                         qdev->num_rx_queues, qdev->num_tx_queues);
1229
1230
1231         return 0;
1232 }
1233
1234 /* Info about HW descriptor ring limitations */
1235 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1236         .nb_max = 0x8000, /* 32K */
1237         .nb_min = 128,
1238         .nb_align = 128 /* lowest common multiple */
1239 };
1240
1241 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1242         .nb_max = 0x8000, /* 32K */
1243         .nb_min = 256,
1244         .nb_align = 256,
1245         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1246         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1247 };
1248
1249 static void
1250 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1251                   struct rte_eth_dev_info *dev_info)
1252 {
1253         struct qede_dev *qdev = eth_dev->data->dev_private;
1254         struct ecore_dev *edev = &qdev->edev;
1255         struct qed_link_output link;
1256         uint32_t speed_cap = 0;
1257
1258         PMD_INIT_FUNC_TRACE(edev);
1259
1260         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1261         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1262         dev_info->rx_desc_lim = qede_rx_desc_lim;
1263         dev_info->tx_desc_lim = qede_tx_desc_lim;
1264
1265         if (IS_PF(edev))
1266                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1267                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1268         else
1269                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1270                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1271         /* Since CMT mode internally doubles the number of queues */
1272         if (ECORE_IS_CMT(edev))
1273                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1274
1275         dev_info->max_tx_queues = dev_info->max_rx_queues;
1276
1277         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1278         dev_info->max_vfs = 0;
1279         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1280         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1281         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1282         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1283                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1284                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1285                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1286                                      DEV_RX_OFFLOAD_TCP_LRO     |
1287                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1288                                      DEV_RX_OFFLOAD_SCATTER     |
1289                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1290                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1291                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1292         dev_info->rx_queue_offload_capa = 0;
1293
1294         /* TX offloads are on a per-packet basis, so it is applicable
1295          * to both at port and queue levels.
1296          */
1297         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1298                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1299                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1300                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1301                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1302                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1303                                      DEV_TX_OFFLOAD_TCP_TSO     |
1304                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1305                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1306         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1307
1308         dev_info->default_txconf = (struct rte_eth_txconf) {
1309                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1310         };
1311
1312         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1313                 /* Packets are always dropped if no descriptors are available */
1314                 .rx_drop_en = 1,
1315                 .offloads = 0,
1316         };
1317
1318         memset(&link, 0, sizeof(struct qed_link_output));
1319         qdev->ops->common->get_link(edev, &link);
1320         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1321                 speed_cap |= ETH_LINK_SPEED_1G;
1322         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1323                 speed_cap |= ETH_LINK_SPEED_10G;
1324         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1325                 speed_cap |= ETH_LINK_SPEED_25G;
1326         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1327                 speed_cap |= ETH_LINK_SPEED_40G;
1328         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1329                 speed_cap |= ETH_LINK_SPEED_50G;
1330         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1331                 speed_cap |= ETH_LINK_SPEED_100G;
1332         dev_info->speed_capa = speed_cap;
1333 }
1334
1335 /* return 0 means link status changed, -1 means not changed */
1336 int
1337 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1338 {
1339         struct qede_dev *qdev = eth_dev->data->dev_private;
1340         struct ecore_dev *edev = &qdev->edev;
1341         struct qed_link_output q_link;
1342         struct rte_eth_link link;
1343         uint16_t link_duplex;
1344
1345         memset(&q_link, 0, sizeof(q_link));
1346         memset(&link, 0, sizeof(link));
1347
1348         qdev->ops->common->get_link(edev, &q_link);
1349
1350         /* Link Speed */
1351         link.link_speed = q_link.speed;
1352
1353         /* Link Mode */
1354         switch (q_link.duplex) {
1355         case QEDE_DUPLEX_HALF:
1356                 link_duplex = ETH_LINK_HALF_DUPLEX;
1357                 break;
1358         case QEDE_DUPLEX_FULL:
1359                 link_duplex = ETH_LINK_FULL_DUPLEX;
1360                 break;
1361         case QEDE_DUPLEX_UNKNOWN:
1362         default:
1363                 link_duplex = -1;
1364         }
1365         link.link_duplex = link_duplex;
1366
1367         /* Link Status */
1368         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1369
1370         /* AN */
1371         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1372                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1373
1374         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1375                 link.link_speed, link.link_duplex,
1376                 link.link_autoneg, link.link_status);
1377
1378         return rte_eth_linkstatus_set(eth_dev, &link);
1379 }
1380
1381 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1382 {
1383         struct qede_dev *qdev = eth_dev->data->dev_private;
1384         struct ecore_dev *edev = &qdev->edev;
1385         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1386
1387         PMD_INIT_FUNC_TRACE(edev);
1388
1389         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1390                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1391
1392         qed_configure_filter_rx_mode(eth_dev, type);
1393 }
1394
1395 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1396 {
1397         struct qede_dev *qdev = eth_dev->data->dev_private;
1398         struct ecore_dev *edev = &qdev->edev;
1399
1400         PMD_INIT_FUNC_TRACE(edev);
1401
1402         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1403                 qed_configure_filter_rx_mode(eth_dev,
1404                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1405         else
1406                 qed_configure_filter_rx_mode(eth_dev,
1407                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1408 }
1409
1410 static void qede_poll_sp_sb_cb(void *param)
1411 {
1412         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1413         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1414         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1415         int rc;
1416
1417         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1418         qede_interrupt_action(&edev->hwfns[1]);
1419
1420         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1421                                qede_poll_sp_sb_cb,
1422                                (void *)eth_dev);
1423         if (rc != 0) {
1424                 DP_ERR(edev, "Unable to start periodic"
1425                              " timer rc %d\n", rc);
1426         }
1427 }
1428
1429 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1430 {
1431         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1432         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1433         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1434
1435         PMD_INIT_FUNC_TRACE(edev);
1436
1437         /* dev_stop() shall cleanup fp resources in hw but without releasing
1438          * dma memories and sw structures so that dev_start() can be called
1439          * by the app without reconfiguration. However, in dev_close() we
1440          * can release all the resources and device can be brought up newly
1441          */
1442         if (eth_dev->data->dev_started)
1443                 qede_dev_stop(eth_dev);
1444
1445         qede_stop_vport(edev);
1446         qdev->vport_started = false;
1447         qede_fdir_dealloc_resc(eth_dev);
1448         qede_dealloc_fp_resc(eth_dev);
1449
1450         eth_dev->data->nb_rx_queues = 0;
1451         eth_dev->data->nb_tx_queues = 0;
1452
1453         /* Bring the link down */
1454         qede_dev_set_link_state(eth_dev, false);
1455         qdev->ops->common->slowpath_stop(edev);
1456         qdev->ops->common->remove(edev);
1457         rte_intr_disable(&pci_dev->intr_handle);
1458
1459         switch (pci_dev->intr_handle.type) {
1460         case RTE_INTR_HANDLE_UIO_INTX:
1461         case RTE_INTR_HANDLE_VFIO_LEGACY:
1462                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1463                                              qede_interrupt_handler_intx,
1464                                              (void *)eth_dev);
1465                 break;
1466         default:
1467                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1468                                            qede_interrupt_handler,
1469                                            (void *)eth_dev);
1470         }
1471
1472         if (ECORE_IS_CMT(edev))
1473                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1474 }
1475
1476 static int
1477 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1478 {
1479         struct qede_dev *qdev = eth_dev->data->dev_private;
1480         struct ecore_dev *edev = &qdev->edev;
1481         struct ecore_eth_stats stats;
1482         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1483         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1484         struct qede_tx_queue *txq;
1485
1486         ecore_get_vport_stats(edev, &stats);
1487
1488         /* RX Stats */
1489         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1490             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1491
1492         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1493             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1494
1495         eth_stats->ierrors = stats.common.rx_crc_errors +
1496             stats.common.rx_align_errors +
1497             stats.common.rx_carrier_errors +
1498             stats.common.rx_oversize_packets +
1499             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1500
1501         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1502
1503         eth_stats->imissed = stats.common.mftag_filter_discards +
1504             stats.common.mac_filter_discards +
1505             stats.common.no_buff_discards +
1506             stats.common.brb_truncates + stats.common.brb_discards;
1507
1508         /* TX stats */
1509         eth_stats->opackets = stats.common.tx_ucast_pkts +
1510             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1511
1512         eth_stats->obytes = stats.common.tx_ucast_bytes +
1513             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1514
1515         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1516
1517         /* Queue stats */
1518         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1519                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1520         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1521                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1522         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1523             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1524                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1525                        "Not all the queue stats will be displayed. Set"
1526                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1527                        " appropriately and retry.\n");
1528
1529         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1530                 eth_stats->q_ipackets[i] = 0;
1531                 eth_stats->q_errors[i] = 0;
1532
1533                 for_each_hwfn(edev, hw_fn) {
1534                         idx = qid * edev->num_hwfns + hw_fn;
1535
1536                         eth_stats->q_ipackets[i] +=
1537                                 *(uint64_t *)
1538                                         (((char *)(qdev->fp_array[idx].rxq)) +
1539                                          offsetof(struct qede_rx_queue,
1540                                          rcv_pkts));
1541                         eth_stats->q_errors[i] +=
1542                                 *(uint64_t *)
1543                                         (((char *)(qdev->fp_array[idx].rxq)) +
1544                                          offsetof(struct qede_rx_queue,
1545                                          rx_hw_errors)) +
1546                                 *(uint64_t *)
1547                                         (((char *)(qdev->fp_array[idx].rxq)) +
1548                                          offsetof(struct qede_rx_queue,
1549                                          rx_alloc_errors));
1550                 }
1551
1552                 i++;
1553                 if (i == rxq_stat_cntrs)
1554                         break;
1555         }
1556
1557         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1558                 eth_stats->q_opackets[j] = 0;
1559
1560                 for_each_hwfn(edev, hw_fn) {
1561                         idx = qid * edev->num_hwfns + hw_fn;
1562
1563                         txq = qdev->fp_array[idx].txq;
1564                         eth_stats->q_opackets[j] +=
1565                                 *((uint64_t *)(uintptr_t)
1566                                         (((uint64_t)(uintptr_t)(txq)) +
1567                                          offsetof(struct qede_tx_queue,
1568                                                   xmit_pkts)));
1569                 }
1570
1571                 j++;
1572                 if (j == txq_stat_cntrs)
1573                         break;
1574         }
1575
1576         return 0;
1577 }
1578
1579 static unsigned
1580 qede_get_xstats_count(struct qede_dev *qdev) {
1581         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1582
1583         if (ECORE_IS_BB(&qdev->edev))
1584                 return RTE_DIM(qede_xstats_strings) +
1585                        RTE_DIM(qede_bb_xstats_strings) +
1586                        (RTE_DIM(qede_rxq_xstats_strings) *
1587                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1588         else
1589                 return RTE_DIM(qede_xstats_strings) +
1590                        RTE_DIM(qede_ah_xstats_strings) +
1591                        (RTE_DIM(qede_rxq_xstats_strings) *
1592                         QEDE_RSS_COUNT(dev));
1593 }
1594
1595 static int
1596 qede_get_xstats_names(struct rte_eth_dev *dev,
1597                       struct rte_eth_xstat_name *xstats_names,
1598                       __rte_unused unsigned int limit)
1599 {
1600         struct qede_dev *qdev = dev->data->dev_private;
1601         struct ecore_dev *edev = &qdev->edev;
1602         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1603         unsigned int i, qid, hw_fn, stat_idx = 0;
1604
1605         if (xstats_names == NULL)
1606                 return stat_cnt;
1607
1608         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1609                 strlcpy(xstats_names[stat_idx].name,
1610                         qede_xstats_strings[i].name,
1611                         sizeof(xstats_names[stat_idx].name));
1612                 stat_idx++;
1613         }
1614
1615         if (ECORE_IS_BB(edev)) {
1616                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1617                         strlcpy(xstats_names[stat_idx].name,
1618                                 qede_bb_xstats_strings[i].name,
1619                                 sizeof(xstats_names[stat_idx].name));
1620                         stat_idx++;
1621                 }
1622         } else {
1623                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1624                         strlcpy(xstats_names[stat_idx].name,
1625                                 qede_ah_xstats_strings[i].name,
1626                                 sizeof(xstats_names[stat_idx].name));
1627                         stat_idx++;
1628                 }
1629         }
1630
1631         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1632                 for_each_hwfn(edev, hw_fn) {
1633                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1634                                 snprintf(xstats_names[stat_idx].name,
1635                                          RTE_ETH_XSTATS_NAME_SIZE,
1636                                          "%.4s%d.%d%s",
1637                                          qede_rxq_xstats_strings[i].name,
1638                                          hw_fn, qid,
1639                                          qede_rxq_xstats_strings[i].name + 4);
1640                                 stat_idx++;
1641                         }
1642                 }
1643         }
1644
1645         return stat_cnt;
1646 }
1647
1648 static int
1649 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1650                 unsigned int n)
1651 {
1652         struct qede_dev *qdev = dev->data->dev_private;
1653         struct ecore_dev *edev = &qdev->edev;
1654         struct ecore_eth_stats stats;
1655         const unsigned int num = qede_get_xstats_count(qdev);
1656         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1657
1658         if (n < num)
1659                 return num;
1660
1661         ecore_get_vport_stats(edev, &stats);
1662
1663         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1664                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1665                                              qede_xstats_strings[i].offset);
1666                 xstats[stat_idx].id = stat_idx;
1667                 stat_idx++;
1668         }
1669
1670         if (ECORE_IS_BB(edev)) {
1671                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1672                         xstats[stat_idx].value =
1673                                         *(uint64_t *)(((char *)&stats) +
1674                                         qede_bb_xstats_strings[i].offset);
1675                         xstats[stat_idx].id = stat_idx;
1676                         stat_idx++;
1677                 }
1678         } else {
1679                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1680                         xstats[stat_idx].value =
1681                                         *(uint64_t *)(((char *)&stats) +
1682                                         qede_ah_xstats_strings[i].offset);
1683                         xstats[stat_idx].id = stat_idx;
1684                         stat_idx++;
1685                 }
1686         }
1687
1688         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1689                 for_each_hwfn(edev, hw_fn) {
1690                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1691                                 fpidx = qid * edev->num_hwfns + hw_fn;
1692                                 xstats[stat_idx].value = *(uint64_t *)
1693                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1694                                          qede_rxq_xstats_strings[i].offset);
1695                                 xstats[stat_idx].id = stat_idx;
1696                                 stat_idx++;
1697                         }
1698
1699                 }
1700         }
1701
1702         return stat_idx;
1703 }
1704
1705 static void
1706 qede_reset_xstats(struct rte_eth_dev *dev)
1707 {
1708         struct qede_dev *qdev = dev->data->dev_private;
1709         struct ecore_dev *edev = &qdev->edev;
1710
1711         ecore_reset_vport_stats(edev);
1712         qede_reset_queue_stats(qdev, true);
1713 }
1714
1715 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1716 {
1717         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1718         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1719         struct qed_link_params link_params;
1720         int rc;
1721
1722         DP_INFO(edev, "setting link state %d\n", link_up);
1723         memset(&link_params, 0, sizeof(link_params));
1724         link_params.link_up = link_up;
1725         rc = qdev->ops->common->set_link(edev, &link_params);
1726         if (rc != ECORE_SUCCESS)
1727                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1728
1729         return rc;
1730 }
1731
1732 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1733 {
1734         return qede_dev_set_link_state(eth_dev, true);
1735 }
1736
1737 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1738 {
1739         return qede_dev_set_link_state(eth_dev, false);
1740 }
1741
1742 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1743 {
1744         struct qede_dev *qdev = eth_dev->data->dev_private;
1745         struct ecore_dev *edev = &qdev->edev;
1746
1747         ecore_reset_vport_stats(edev);
1748         qede_reset_queue_stats(qdev, false);
1749 }
1750
1751 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1752 {
1753         enum qed_filter_rx_mode_type type =
1754             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1755
1756         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1757                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1758
1759         qed_configure_filter_rx_mode(eth_dev, type);
1760 }
1761
1762 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1763 {
1764         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1765                 qed_configure_filter_rx_mode(eth_dev,
1766                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1767         else
1768                 qed_configure_filter_rx_mode(eth_dev,
1769                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1770 }
1771
1772 static int
1773 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1774                 struct rte_ether_addr *mc_addrs,
1775                 uint32_t mc_addrs_num)
1776 {
1777         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1778         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1779         uint8_t i;
1780
1781         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1782                 DP_ERR(edev, "Reached max multicast filters limit,"
1783                              "Please enable multicast promisc mode\n");
1784                 return -ENOSPC;
1785         }
1786
1787         for (i = 0; i < mc_addrs_num; i++) {
1788                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1789                         DP_ERR(edev, "Not a valid multicast MAC\n");
1790                         return -EINVAL;
1791                 }
1792         }
1793
1794         /* Flush all existing entries */
1795         if (qede_del_mcast_filters(eth_dev))
1796                 return -1;
1797
1798         /* Set new mcast list */
1799         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1800 }
1801
1802 /* Update MTU via vport-update without doing port restart.
1803  * The vport must be deactivated before calling this API.
1804  */
1805 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1806 {
1807         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1808         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1809         struct ecore_hwfn *p_hwfn;
1810         int rc;
1811         int i;
1812
1813         if (IS_PF(edev)) {
1814                 struct ecore_sp_vport_update_params params;
1815
1816                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1817                 params.vport_id = 0;
1818                 params.mtu = mtu;
1819                 params.vport_id = 0;
1820                 for_each_hwfn(edev, i) {
1821                         p_hwfn = &edev->hwfns[i];
1822                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1823                         rc = ecore_sp_vport_update(p_hwfn, &params,
1824                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1825                         if (rc != ECORE_SUCCESS)
1826                                 goto err;
1827                 }
1828         } else {
1829                 for_each_hwfn(edev, i) {
1830                         p_hwfn = &edev->hwfns[i];
1831                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1832                         if (rc == ECORE_INVAL) {
1833                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1834                                 /* Recreate vport */
1835                                 rc = qede_start_vport(qdev, mtu);
1836                                 if (rc != ECORE_SUCCESS)
1837                                         goto err;
1838
1839                                 /* Restore config lost due to vport stop */
1840                                 if (eth_dev->data->promiscuous)
1841                                         qede_promiscuous_enable(eth_dev);
1842                                 else
1843                                         qede_promiscuous_disable(eth_dev);
1844
1845                                 if (eth_dev->data->all_multicast)
1846                                         qede_allmulticast_enable(eth_dev);
1847                                 else
1848                                         qede_allmulticast_disable(eth_dev);
1849
1850                                 qede_vlan_offload_set(eth_dev,
1851                                                       qdev->vlan_offload_mask);
1852                         } else if (rc != ECORE_SUCCESS) {
1853                                 goto err;
1854                         }
1855                 }
1856         }
1857         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1858
1859         return 0;
1860
1861 err:
1862         DP_ERR(edev, "Failed to update MTU\n");
1863         return -1;
1864 }
1865
1866 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1867                               struct rte_eth_fc_conf *fc_conf)
1868 {
1869         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1870         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1871         struct qed_link_output current_link;
1872         struct qed_link_params params;
1873
1874         memset(&current_link, 0, sizeof(current_link));
1875         qdev->ops->common->get_link(edev, &current_link);
1876
1877         memset(&params, 0, sizeof(params));
1878         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1879         if (fc_conf->autoneg) {
1880                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1881                         DP_ERR(edev, "Autoneg not supported\n");
1882                         return -EINVAL;
1883                 }
1884                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1885         }
1886
1887         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1888         if (fc_conf->mode == RTE_FC_FULL)
1889                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1890                                         QED_LINK_PAUSE_RX_ENABLE);
1891         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1892                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1893         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1894                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1895
1896         params.link_up = true;
1897         (void)qdev->ops->common->set_link(edev, &params);
1898
1899         return 0;
1900 }
1901
1902 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1903                               struct rte_eth_fc_conf *fc_conf)
1904 {
1905         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1906         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1907         struct qed_link_output current_link;
1908
1909         memset(&current_link, 0, sizeof(current_link));
1910         qdev->ops->common->get_link(edev, &current_link);
1911
1912         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1913                 fc_conf->autoneg = true;
1914
1915         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1916                                          QED_LINK_PAUSE_TX_ENABLE))
1917                 fc_conf->mode = RTE_FC_FULL;
1918         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1919                 fc_conf->mode = RTE_FC_RX_PAUSE;
1920         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1921                 fc_conf->mode = RTE_FC_TX_PAUSE;
1922         else
1923                 fc_conf->mode = RTE_FC_NONE;
1924
1925         return 0;
1926 }
1927
1928 static const uint32_t *
1929 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1930 {
1931         static const uint32_t ptypes[] = {
1932                 RTE_PTYPE_L2_ETHER,
1933                 RTE_PTYPE_L2_ETHER_VLAN,
1934                 RTE_PTYPE_L3_IPV4,
1935                 RTE_PTYPE_L3_IPV6,
1936                 RTE_PTYPE_L4_TCP,
1937                 RTE_PTYPE_L4_UDP,
1938                 RTE_PTYPE_TUNNEL_VXLAN,
1939                 RTE_PTYPE_L4_FRAG,
1940                 RTE_PTYPE_TUNNEL_GENEVE,
1941                 RTE_PTYPE_TUNNEL_GRE,
1942                 /* Inner */
1943                 RTE_PTYPE_INNER_L2_ETHER,
1944                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1945                 RTE_PTYPE_INNER_L3_IPV4,
1946                 RTE_PTYPE_INNER_L3_IPV6,
1947                 RTE_PTYPE_INNER_L4_TCP,
1948                 RTE_PTYPE_INNER_L4_UDP,
1949                 RTE_PTYPE_INNER_L4_FRAG,
1950                 RTE_PTYPE_UNKNOWN
1951         };
1952
1953         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
1954             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
1955                 return ptypes;
1956
1957         return NULL;
1958 }
1959
1960 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1961 {
1962         *rss_caps = 0;
1963         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1964         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1965         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1966         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1967         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1968         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1969         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1970         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1971 }
1972
1973 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1974                          struct rte_eth_rss_conf *rss_conf)
1975 {
1976         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1977         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1978         struct ecore_sp_vport_update_params vport_update_params;
1979         struct ecore_rss_params rss_params;
1980         struct ecore_hwfn *p_hwfn;
1981         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1982         uint64_t hf = rss_conf->rss_hf;
1983         uint8_t len = rss_conf->rss_key_len;
1984         uint8_t idx, i, j, fpidx;
1985         int rc;
1986
1987         memset(&vport_update_params, 0, sizeof(vport_update_params));
1988         memset(&rss_params, 0, sizeof(rss_params));
1989
1990         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1991                 (unsigned long)hf, len, key);
1992
1993         if (hf != 0) {
1994                 /* Enabling RSS */
1995                 DP_INFO(edev, "Enabling rss\n");
1996
1997                 /* RSS caps */
1998                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1999                 rss_params.update_rss_capabilities = 1;
2000
2001                 /* RSS hash key */
2002                 if (key) {
2003                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2004                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2005                                 return -EINVAL;
2006                         }
2007                         DP_INFO(edev, "Applying user supplied hash key\n");
2008                         rss_params.update_rss_key = 1;
2009                         memcpy(&rss_params.rss_key, key, len);
2010                 }
2011                 rss_params.rss_enable = 1;
2012         }
2013
2014         rss_params.update_rss_config = 1;
2015         /* tbl_size has to be set with capabilities */
2016         rss_params.rss_table_size_log = 7;
2017         vport_update_params.vport_id = 0;
2018
2019         for_each_hwfn(edev, i) {
2020                 /* pass the L2 handles instead of qids */
2021                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2022                         idx = j % QEDE_RSS_COUNT(eth_dev);
2023                         fpidx = idx * edev->num_hwfns + i;
2024                         rss_params.rss_ind_table[j] =
2025                                 qdev->fp_array[fpidx].rxq->handle;
2026                 }
2027
2028                 vport_update_params.rss_params = &rss_params;
2029
2030                 p_hwfn = &edev->hwfns[i];
2031                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2032                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2033                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2034                 if (rc) {
2035                         DP_ERR(edev, "vport-update for RSS failed\n");
2036                         return rc;
2037                 }
2038         }
2039         qdev->rss_enable = rss_params.rss_enable;
2040
2041         /* Update local structure for hash query */
2042         qdev->rss_conf.rss_hf = hf;
2043         qdev->rss_conf.rss_key_len = len;
2044         if (qdev->rss_enable) {
2045                 if  (qdev->rss_conf.rss_key == NULL) {
2046                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2047                         if (qdev->rss_conf.rss_key == NULL) {
2048                                 DP_ERR(edev, "No memory to store RSS key\n");
2049                                 return -ENOMEM;
2050                         }
2051                 }
2052                 if (key && len) {
2053                         DP_INFO(edev, "Storing RSS key\n");
2054                         memcpy(qdev->rss_conf.rss_key, key, len);
2055                 }
2056         } else if (!qdev->rss_enable && len == 0) {
2057                 if (qdev->rss_conf.rss_key) {
2058                         free(qdev->rss_conf.rss_key);
2059                         qdev->rss_conf.rss_key = NULL;
2060                         DP_INFO(edev, "Free RSS key\n");
2061                 }
2062         }
2063
2064         return 0;
2065 }
2066
2067 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2068                            struct rte_eth_rss_conf *rss_conf)
2069 {
2070         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2071
2072         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2073         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2074
2075         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2076                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2077                        rss_conf->rss_key_len);
2078         return 0;
2079 }
2080
2081 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2082                          struct rte_eth_rss_reta_entry64 *reta_conf,
2083                          uint16_t reta_size)
2084 {
2085         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2086         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2087         struct ecore_sp_vport_update_params vport_update_params;
2088         struct ecore_rss_params *params;
2089         uint16_t i, j, idx, fid, shift;
2090         struct ecore_hwfn *p_hwfn;
2091         uint8_t entry;
2092         int rc = 0;
2093
2094         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2095                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2096                        reta_size);
2097                 return -EINVAL;
2098         }
2099
2100         memset(&vport_update_params, 0, sizeof(vport_update_params));
2101         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2102         if (params == NULL) {
2103                 DP_ERR(edev, "failed to allocate memory\n");
2104                 return -ENOMEM;
2105         }
2106
2107         params->update_rss_ind_table = 1;
2108         params->rss_table_size_log = 7;
2109         params->update_rss_config = 1;
2110
2111         vport_update_params.vport_id = 0;
2112         /* Use the current value of rss_enable */
2113         params->rss_enable = qdev->rss_enable;
2114         vport_update_params.rss_params = params;
2115
2116         for_each_hwfn(edev, i) {
2117                 for (j = 0; j < reta_size; j++) {
2118                         idx = j / RTE_RETA_GROUP_SIZE;
2119                         shift = j % RTE_RETA_GROUP_SIZE;
2120                         if (reta_conf[idx].mask & (1ULL << shift)) {
2121                                 entry = reta_conf[idx].reta[shift];
2122                                 fid = entry * edev->num_hwfns + i;
2123                                 /* Pass rxq handles to ecore */
2124                                 params->rss_ind_table[j] =
2125                                                 qdev->fp_array[fid].rxq->handle;
2126                                 /* Update the local copy for RETA query cmd */
2127                                 qdev->rss_ind_table[j] = entry;
2128                         }
2129                 }
2130
2131                 p_hwfn = &edev->hwfns[i];
2132                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2133                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2134                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2135                 if (rc) {
2136                         DP_ERR(edev, "vport-update for RSS failed\n");
2137                         goto out;
2138                 }
2139         }
2140
2141 out:
2142         rte_free(params);
2143         return rc;
2144 }
2145
2146 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2147                                struct rte_eth_rss_reta_entry64 *reta_conf,
2148                                uint16_t reta_size)
2149 {
2150         struct qede_dev *qdev = eth_dev->data->dev_private;
2151         struct ecore_dev *edev = &qdev->edev;
2152         uint16_t i, idx, shift;
2153         uint8_t entry;
2154
2155         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2156                 DP_ERR(edev, "reta_size %d is not supported\n",
2157                        reta_size);
2158                 return -EINVAL;
2159         }
2160
2161         for (i = 0; i < reta_size; i++) {
2162                 idx = i / RTE_RETA_GROUP_SIZE;
2163                 shift = i % RTE_RETA_GROUP_SIZE;
2164                 if (reta_conf[idx].mask & (1ULL << shift)) {
2165                         entry = qdev->rss_ind_table[i];
2166                         reta_conf[idx].reta[shift] = entry;
2167                 }
2168         }
2169
2170         return 0;
2171 }
2172
2173
2174
2175 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2176 {
2177         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2178         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2179         struct rte_eth_dev_info dev_info = {0};
2180         struct qede_fastpath *fp;
2181         uint32_t max_rx_pkt_len;
2182         uint32_t frame_size;
2183         uint16_t bufsz;
2184         bool restart = false;
2185         int i, rc;
2186
2187         PMD_INIT_FUNC_TRACE(edev);
2188         qede_dev_info_get(dev, &dev_info);
2189         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2190         frame_size = max_rx_pkt_len;
2191         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2192                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2193                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2194                        QEDE_ETH_OVERHEAD);
2195                 return -EINVAL;
2196         }
2197         if (!dev->data->scattered_rx &&
2198             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2199                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2200                         dev->data->min_rx_buf_size);
2201                 return -EINVAL;
2202         }
2203         /* Temporarily replace I/O functions with dummy ones. It cannot
2204          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2205          */
2206         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2207         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2208         if (dev->data->dev_started) {
2209                 dev->data->dev_started = 0;
2210                 qede_dev_stop(dev);
2211                 restart = true;
2212         }
2213         rte_delay_ms(1000);
2214         qdev->mtu = mtu;
2215
2216         /* Fix up RX buf size for all queues of the port */
2217         for (i = 0; i < qdev->num_rx_queues; i++) {
2218                 fp = &qdev->fp_array[i];
2219                 if (fp->rxq != NULL) {
2220                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2221                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2222                         /* cache align the mbuf size to simplfy rx_buf_size
2223                          * calculation
2224                          */
2225                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2226                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2227                         if (rc < 0)
2228                                 return rc;
2229
2230                         fp->rxq->rx_buf_size = rc;
2231                 }
2232         }
2233         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2234                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2235         else
2236                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2237
2238         if (!dev->data->dev_started && restart) {
2239                 qede_dev_start(dev);
2240                 dev->data->dev_started = 1;
2241         }
2242
2243         /* update max frame size */
2244         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2245         /* Reassign back */
2246         if (ECORE_IS_CMT(edev)) {
2247                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
2248                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2249         } else {
2250                 dev->rx_pkt_burst = qede_recv_pkts;
2251                 dev->tx_pkt_burst = qede_xmit_pkts;
2252         }
2253         return 0;
2254 }
2255
2256 static int
2257 qede_dev_reset(struct rte_eth_dev *dev)
2258 {
2259         int ret;
2260
2261         ret = qede_eth_dev_uninit(dev);
2262         if (ret)
2263                 return ret;
2264
2265         return qede_eth_dev_init(dev);
2266 }
2267
2268 static const struct eth_dev_ops qede_eth_dev_ops = {
2269         .dev_configure = qede_dev_configure,
2270         .dev_infos_get = qede_dev_info_get,
2271         .rx_queue_setup = qede_rx_queue_setup,
2272         .rx_queue_release = qede_rx_queue_release,
2273         .rx_descriptor_status = qede_rx_descriptor_status,
2274         .tx_queue_setup = qede_tx_queue_setup,
2275         .tx_queue_release = qede_tx_queue_release,
2276         .dev_start = qede_dev_start,
2277         .dev_reset = qede_dev_reset,
2278         .dev_set_link_up = qede_dev_set_link_up,
2279         .dev_set_link_down = qede_dev_set_link_down,
2280         .link_update = qede_link_update,
2281         .promiscuous_enable = qede_promiscuous_enable,
2282         .promiscuous_disable = qede_promiscuous_disable,
2283         .allmulticast_enable = qede_allmulticast_enable,
2284         .allmulticast_disable = qede_allmulticast_disable,
2285         .set_mc_addr_list = qede_set_mc_addr_list,
2286         .dev_stop = qede_dev_stop,
2287         .dev_close = qede_dev_close,
2288         .stats_get = qede_get_stats,
2289         .stats_reset = qede_reset_stats,
2290         .xstats_get = qede_get_xstats,
2291         .xstats_reset = qede_reset_xstats,
2292         .xstats_get_names = qede_get_xstats_names,
2293         .mac_addr_add = qede_mac_addr_add,
2294         .mac_addr_remove = qede_mac_addr_remove,
2295         .mac_addr_set = qede_mac_addr_set,
2296         .vlan_offload_set = qede_vlan_offload_set,
2297         .vlan_filter_set = qede_vlan_filter_set,
2298         .flow_ctrl_set = qede_flow_ctrl_set,
2299         .flow_ctrl_get = qede_flow_ctrl_get,
2300         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2301         .rss_hash_update = qede_rss_hash_update,
2302         .rss_hash_conf_get = qede_rss_hash_conf_get,
2303         .reta_update  = qede_rss_reta_update,
2304         .reta_query  = qede_rss_reta_query,
2305         .mtu_set = qede_set_mtu,
2306         .filter_ctrl = qede_dev_filter_ctrl,
2307         .udp_tunnel_port_add = qede_udp_dst_port_add,
2308         .udp_tunnel_port_del = qede_udp_dst_port_del,
2309 };
2310
2311 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2312         .dev_configure = qede_dev_configure,
2313         .dev_infos_get = qede_dev_info_get,
2314         .rx_queue_setup = qede_rx_queue_setup,
2315         .rx_queue_release = qede_rx_queue_release,
2316         .rx_descriptor_status = qede_rx_descriptor_status,
2317         .tx_queue_setup = qede_tx_queue_setup,
2318         .tx_queue_release = qede_tx_queue_release,
2319         .dev_start = qede_dev_start,
2320         .dev_reset = qede_dev_reset,
2321         .dev_set_link_up = qede_dev_set_link_up,
2322         .dev_set_link_down = qede_dev_set_link_down,
2323         .link_update = qede_link_update,
2324         .promiscuous_enable = qede_promiscuous_enable,
2325         .promiscuous_disable = qede_promiscuous_disable,
2326         .allmulticast_enable = qede_allmulticast_enable,
2327         .allmulticast_disable = qede_allmulticast_disable,
2328         .set_mc_addr_list = qede_set_mc_addr_list,
2329         .dev_stop = qede_dev_stop,
2330         .dev_close = qede_dev_close,
2331         .stats_get = qede_get_stats,
2332         .stats_reset = qede_reset_stats,
2333         .xstats_get = qede_get_xstats,
2334         .xstats_reset = qede_reset_xstats,
2335         .xstats_get_names = qede_get_xstats_names,
2336         .vlan_offload_set = qede_vlan_offload_set,
2337         .vlan_filter_set = qede_vlan_filter_set,
2338         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2339         .rss_hash_update = qede_rss_hash_update,
2340         .rss_hash_conf_get = qede_rss_hash_conf_get,
2341         .reta_update  = qede_rss_reta_update,
2342         .reta_query  = qede_rss_reta_query,
2343         .mtu_set = qede_set_mtu,
2344         .udp_tunnel_port_add = qede_udp_dst_port_add,
2345         .udp_tunnel_port_del = qede_udp_dst_port_del,
2346         .mac_addr_add = qede_mac_addr_add,
2347         .mac_addr_remove = qede_mac_addr_remove,
2348         .mac_addr_set = qede_mac_addr_set,
2349 };
2350
2351 static void qede_update_pf_params(struct ecore_dev *edev)
2352 {
2353         struct ecore_pf_params pf_params;
2354
2355         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2356         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2357         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2358         qed_ops->common->update_pf_params(edev, &pf_params);
2359 }
2360
2361 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2362 {
2363         struct rte_pci_device *pci_dev;
2364         struct rte_pci_addr pci_addr;
2365         struct qede_dev *adapter;
2366         struct ecore_dev *edev;
2367         struct qed_dev_eth_info dev_info;
2368         struct qed_slowpath_params params;
2369         static bool do_once = true;
2370         uint8_t bulletin_change;
2371         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2372         uint8_t is_mac_forced;
2373         bool is_mac_exist;
2374         /* Fix up ecore debug level */
2375         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2376         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2377         uint32_t int_mode;
2378         int rc;
2379
2380         /* Extract key data structures */
2381         adapter = eth_dev->data->dev_private;
2382         adapter->ethdev = eth_dev;
2383         edev = &adapter->edev;
2384         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2385         pci_addr = pci_dev->addr;
2386
2387         PMD_INIT_FUNC_TRACE(edev);
2388
2389         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2390                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2391                  eth_dev->data->port_id);
2392
2393         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2394                 DP_ERR(edev, "Skipping device init from secondary process\n");
2395                 return 0;
2396         }
2397
2398         rte_eth_copy_pci_info(eth_dev, pci_dev);
2399
2400         /* @DPDK */
2401         edev->vendor_id = pci_dev->id.vendor_id;
2402         edev->device_id = pci_dev->id.device_id;
2403
2404         qed_ops = qed_get_eth_ops();
2405         if (!qed_ops) {
2406                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2407                 return -EINVAL;
2408         }
2409
2410         DP_INFO(edev, "Starting qede probe\n");
2411         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2412                                     dp_level, is_vf);
2413         if (rc != 0) {
2414                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2415                 return -ENODEV;
2416         }
2417         qede_update_pf_params(edev);
2418
2419         switch (pci_dev->intr_handle.type) {
2420         case RTE_INTR_HANDLE_UIO_INTX:
2421         case RTE_INTR_HANDLE_VFIO_LEGACY:
2422                 int_mode = ECORE_INT_MODE_INTA;
2423                 rte_intr_callback_register(&pci_dev->intr_handle,
2424                                            qede_interrupt_handler_intx,
2425                                            (void *)eth_dev);
2426                 break;
2427         default:
2428                 int_mode = ECORE_INT_MODE_MSIX;
2429                 rte_intr_callback_register(&pci_dev->intr_handle,
2430                                            qede_interrupt_handler,
2431                                            (void *)eth_dev);
2432         }
2433
2434         if (rte_intr_enable(&pci_dev->intr_handle)) {
2435                 DP_ERR(edev, "rte_intr_enable() failed\n");
2436                 return -ENODEV;
2437         }
2438
2439         /* Start the Slowpath-process */
2440         memset(&params, 0, sizeof(struct qed_slowpath_params));
2441
2442         params.int_mode = int_mode;
2443         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2444         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2445         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2446         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2447         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2448                 QEDE_PMD_DRV_VER_STR_SIZE);
2449
2450         if (ECORE_IS_CMT(edev)) {
2451                 eth_dev->rx_pkt_burst = qede_recv_pkts_cmt;
2452                 eth_dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2453         } else {
2454                 eth_dev->rx_pkt_burst = qede_recv_pkts;
2455                 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2456         }
2457
2458         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2459
2460         /* For CMT mode device do periodic polling for slowpath events.
2461          * This is required since uio device uses only one MSI-x
2462          * interrupt vector but we need one for each engine.
2463          */
2464         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2465                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2466                                        qede_poll_sp_sb_cb,
2467                                        (void *)eth_dev);
2468                 if (rc != 0) {
2469                         DP_ERR(edev, "Unable to start periodic"
2470                                      " timer rc %d\n", rc);
2471                         return -EINVAL;
2472                 }
2473         }
2474
2475         rc = qed_ops->common->slowpath_start(edev, &params);
2476         if (rc) {
2477                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2478                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2479                                      (void *)eth_dev);
2480                 return -ENODEV;
2481         }
2482
2483         rc = qed_ops->fill_dev_info(edev, &dev_info);
2484         if (rc) {
2485                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2486                 qed_ops->common->slowpath_stop(edev);
2487                 qed_ops->common->remove(edev);
2488                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2489                                      (void *)eth_dev);
2490                 return -ENODEV;
2491         }
2492
2493         qede_alloc_etherdev(adapter, &dev_info);
2494
2495         adapter->ops->common->set_name(edev, edev->name);
2496
2497         if (!is_vf)
2498                 adapter->dev_info.num_mac_filters =
2499                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2500                                             ECORE_MAC);
2501         else
2502                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2503                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2504
2505         /* Allocate memory for storing MAC addr */
2506         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2507                                         (RTE_ETHER_ADDR_LEN *
2508                                         adapter->dev_info.num_mac_filters),
2509                                         RTE_CACHE_LINE_SIZE);
2510
2511         if (eth_dev->data->mac_addrs == NULL) {
2512                 DP_ERR(edev, "Failed to allocate MAC address\n");
2513                 qed_ops->common->slowpath_stop(edev);
2514                 qed_ops->common->remove(edev);
2515                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2516                                      (void *)eth_dev);
2517                 return -ENOMEM;
2518         }
2519
2520         if (!is_vf) {
2521                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2522                                 hw_info.hw_mac_addr,
2523                                 &eth_dev->data->mac_addrs[0]);
2524                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2525                                 &adapter->primary_mac);
2526         } else {
2527                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2528                                        &bulletin_change);
2529                 if (bulletin_change) {
2530                         is_mac_exist =
2531                             ecore_vf_bulletin_get_forced_mac(
2532                                                 ECORE_LEADING_HWFN(edev),
2533                                                 vf_mac,
2534                                                 &is_mac_forced);
2535                         if (is_mac_exist) {
2536                                 DP_INFO(edev, "VF macaddr received from PF\n");
2537                                 rte_ether_addr_copy(
2538                                         (struct rte_ether_addr *)&vf_mac,
2539                                         &eth_dev->data->mac_addrs[0]);
2540                                 rte_ether_addr_copy(
2541                                         &eth_dev->data->mac_addrs[0],
2542                                         &adapter->primary_mac);
2543                         } else {
2544                                 DP_ERR(edev, "No VF macaddr assigned\n");
2545                         }
2546                 }
2547         }
2548
2549         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2550
2551         if (do_once) {
2552                 qede_print_adapter_info(adapter);
2553                 do_once = false;
2554         }
2555
2556         /* Bring-up the link */
2557         qede_dev_set_link_state(eth_dev, true);
2558
2559         adapter->num_tx_queues = 0;
2560         adapter->num_rx_queues = 0;
2561         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2562         SLIST_INIT(&adapter->vlan_list_head);
2563         SLIST_INIT(&adapter->uc_list_head);
2564         SLIST_INIT(&adapter->mc_list_head);
2565         adapter->mtu = RTE_ETHER_MTU;
2566         adapter->vport_started = false;
2567
2568         /* VF tunnel offloads is enabled by default in PF driver */
2569         adapter->vxlan.num_filters = 0;
2570         adapter->geneve.num_filters = 0;
2571         adapter->ipgre.num_filters = 0;
2572         if (is_vf) {
2573                 adapter->vxlan.enable = true;
2574                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2575                                              ETH_TUNNEL_FILTER_IVLAN;
2576                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2577                 adapter->geneve.enable = true;
2578                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2579                                               ETH_TUNNEL_FILTER_IVLAN;
2580                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2581                 adapter->ipgre.enable = true;
2582                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2583                                              ETH_TUNNEL_FILTER_IVLAN;
2584         } else {
2585                 adapter->vxlan.enable = false;
2586                 adapter->geneve.enable = false;
2587                 adapter->ipgre.enable = false;
2588         }
2589
2590         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2591                 adapter->primary_mac.addr_bytes[0],
2592                 adapter->primary_mac.addr_bytes[1],
2593                 adapter->primary_mac.addr_bytes[2],
2594                 adapter->primary_mac.addr_bytes[3],
2595                 adapter->primary_mac.addr_bytes[4],
2596                 adapter->primary_mac.addr_bytes[5]);
2597
2598         DP_INFO(edev, "Device initialized\n");
2599
2600         return 0;
2601 }
2602
2603 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2604 {
2605         return qede_common_dev_init(eth_dev, 1);
2606 }
2607
2608 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2609 {
2610         return qede_common_dev_init(eth_dev, 0);
2611 }
2612
2613 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2614 {
2615         struct qede_dev *qdev = eth_dev->data->dev_private;
2616         struct ecore_dev *edev = &qdev->edev;
2617
2618         PMD_INIT_FUNC_TRACE(edev);
2619
2620         /* only uninitialize in the primary process */
2621         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2622                 return 0;
2623
2624         /* safe to close dev here */
2625         qede_dev_close(eth_dev);
2626
2627         eth_dev->dev_ops = NULL;
2628         eth_dev->rx_pkt_burst = NULL;
2629         eth_dev->tx_pkt_burst = NULL;
2630
2631         return 0;
2632 }
2633
2634 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2635 {
2636         return qede_dev_common_uninit(eth_dev);
2637 }
2638
2639 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2640 {
2641         return qede_dev_common_uninit(eth_dev);
2642 }
2643
2644 static const struct rte_pci_id pci_id_qedevf_map[] = {
2645 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2646         {
2647                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2648         },
2649         {
2650                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2651         },
2652         {
2653                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2654         },
2655         {.vendor_id = 0,}
2656 };
2657
2658 static const struct rte_pci_id pci_id_qede_map[] = {
2659 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2660         {
2661                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2662         },
2663         {
2664                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2665         },
2666         {
2667                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2668         },
2669         {
2670                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2671         },
2672         {
2673                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2674         },
2675         {
2676                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2677         },
2678         {
2679                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2680         },
2681         {
2682                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2683         },
2684         {
2685                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2686         },
2687         {
2688                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2689         },
2690         {.vendor_id = 0,}
2691 };
2692
2693 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2694         struct rte_pci_device *pci_dev)
2695 {
2696         return rte_eth_dev_pci_generic_probe(pci_dev,
2697                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2698 }
2699
2700 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2701 {
2702         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2703 }
2704
2705 static struct rte_pci_driver rte_qedevf_pmd = {
2706         .id_table = pci_id_qedevf_map,
2707         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2708         .probe = qedevf_eth_dev_pci_probe,
2709         .remove = qedevf_eth_dev_pci_remove,
2710 };
2711
2712 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2713         struct rte_pci_device *pci_dev)
2714 {
2715         return rte_eth_dev_pci_generic_probe(pci_dev,
2716                 sizeof(struct qede_dev), qede_eth_dev_init);
2717 }
2718
2719 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2720 {
2721         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2722 }
2723
2724 static struct rte_pci_driver rte_qede_pmd = {
2725         .id_table = pci_id_qede_map,
2726         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2727         .probe = qede_eth_dev_pci_probe,
2728         .remove = qede_eth_dev_pci_remove,
2729 };
2730
2731 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2732 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2733 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2734 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2735 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2736 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2737
2738 RTE_INIT(qede_init_log)
2739 {
2740         qede_logtype_init = rte_log_register("pmd.net.qede.init");
2741         if (qede_logtype_init >= 0)
2742                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2743         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2744         if (qede_logtype_driver >= 0)
2745                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
2746 }