drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 /* Globals */
  14 int qede_logtype_init;
  15 int qede_logtype_driver;
  16
  17 static const struct qed_eth_ops *qed_ops;
  18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  20
  21 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  22
  23 struct rte_qede_xstats_name_off {
  24         char name[RTE_ETH_XSTATS_NAME_SIZE];
  25         uint64_t offset;
  26 };
  27
  28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  29         {"rx_unicast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  31         {"rx_multicast_bytes",
  32                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  33         {"rx_broadcast_bytes",
  34                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  35         {"rx_unicast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  37         {"rx_multicast_packets",
  38                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  39         {"rx_broadcast_packets",
  40                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  41
  42         {"tx_unicast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  44         {"tx_multicast_bytes",
  45                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  46         {"tx_broadcast_bytes",
  47                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  48         {"tx_unicast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  50         {"tx_multicast_packets",
  51                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  52         {"tx_broadcast_packets",
  53                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  54
  55         {"rx_64_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  57         {"rx_65_to_127_byte_packets",
  58                 offsetof(struct ecore_eth_stats_common,
  59                          rx_65_to_127_byte_packets)},
  60         {"rx_128_to_255_byte_packets",
  61                 offsetof(struct ecore_eth_stats_common,
  62                          rx_128_to_255_byte_packets)},
  63         {"rx_256_to_511_byte_packets",
  64                 offsetof(struct ecore_eth_stats_common,
  65                          rx_256_to_511_byte_packets)},
  66         {"rx_512_to_1023_byte_packets",
  67                 offsetof(struct ecore_eth_stats_common,
  68                          rx_512_to_1023_byte_packets)},
  69         {"rx_1024_to_1518_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          rx_1024_to_1518_byte_packets)},
  72         {"tx_64_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  74         {"tx_65_to_127_byte_packets",
  75                 offsetof(struct ecore_eth_stats_common,
  76                          tx_65_to_127_byte_packets)},
  77         {"tx_128_to_255_byte_packets",
  78                 offsetof(struct ecore_eth_stats_common,
  79                          tx_128_to_255_byte_packets)},
  80         {"tx_256_to_511_byte_packets",
  81                 offsetof(struct ecore_eth_stats_common,
  82                          tx_256_to_511_byte_packets)},
  83         {"tx_512_to_1023_byte_packets",
  84                 offsetof(struct ecore_eth_stats_common,
  85                          tx_512_to_1023_byte_packets)},
  86         {"tx_1024_to_1518_byte_packets",
  87                 offsetof(struct ecore_eth_stats_common,
  88                          tx_1024_to_1518_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  96         {"tx_pause_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  98         {"rx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 100         {"tx_priority_flow_control_frames",
 101                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 102
 103         {"rx_crc_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 105         {"rx_align_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 107         {"rx_carrier_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 109         {"rx_oversize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 111         {"rx_jabber_errors",
 112                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 113         {"rx_undersize_packet_errors",
 114                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 115         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 116         {"rx_host_buffer_not_available",
 117                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 118         /* Number of packets discarded because they are bigger than MTU */
 119         {"rx_packet_too_big_discards",
 120                 offsetof(struct ecore_eth_stats_common,
 121                          packet_too_big_discard)},
 122         {"rx_ttl_zero_discards",
 123                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 124         {"rx_multi_function_tag_filter_discards",
 125                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 126         {"rx_mac_filter_discards",
 127                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 128         {"rx_gft_filter_drop",
 129                 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
 130         {"rx_hw_buffer_truncates",
 131                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 132         {"rx_hw_buffer_discards",
 133                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 134         {"tx_error_drop_packets",
 135                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 136
 137         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 138         {"rx_mac_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 140         {"rx_mac_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 142         {"rx_mac_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 144         {"rx_mac_frames_ok",
 145                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 146         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 147         {"tx_mac_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 149         {"tx_mac_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 151         {"tx_mac_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 153
 154         {"lro_coalesced_packets",
 155                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 156         {"lro_coalesced_events",
 157                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 158         {"lro_aborts_num",
 159                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 160         {"lro_not_coalesced_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          tpa_not_coalesced_pkts)},
 163         {"lro_coalesced_bytes",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          tpa_coalesced_bytes)},
 166 };
 167
 168 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 169         {"rx_1519_to_1522_byte_packets",
 170                 offsetof(struct ecore_eth_stats, bb) +
 171                 offsetof(struct ecore_eth_stats_bb,
 172                          rx_1519_to_1522_byte_packets)},
 173         {"rx_1519_to_2047_byte_packets",
 174                 offsetof(struct ecore_eth_stats, bb) +
 175                 offsetof(struct ecore_eth_stats_bb,
 176                          rx_1519_to_2047_byte_packets)},
 177         {"rx_2048_to_4095_byte_packets",
 178                 offsetof(struct ecore_eth_stats, bb) +
 179                 offsetof(struct ecore_eth_stats_bb,
 180                          rx_2048_to_4095_byte_packets)},
 181         {"rx_4096_to_9216_byte_packets",
 182                 offsetof(struct ecore_eth_stats, bb) +
 183                 offsetof(struct ecore_eth_stats_bb,
 184                          rx_4096_to_9216_byte_packets)},
 185         {"rx_9217_to_16383_byte_packets",
 186                 offsetof(struct ecore_eth_stats, bb) +
 187                 offsetof(struct ecore_eth_stats_bb,
 188                          rx_9217_to_16383_byte_packets)},
 189
 190         {"tx_1519_to_2047_byte_packets",
 191                 offsetof(struct ecore_eth_stats, bb) +
 192                 offsetof(struct ecore_eth_stats_bb,
 193                          tx_1519_to_2047_byte_packets)},
 194         {"tx_2048_to_4095_byte_packets",
 195                 offsetof(struct ecore_eth_stats, bb) +
 196                 offsetof(struct ecore_eth_stats_bb,
 197                          tx_2048_to_4095_byte_packets)},
 198         {"tx_4096_to_9216_byte_packets",
 199                 offsetof(struct ecore_eth_stats, bb) +
 200                 offsetof(struct ecore_eth_stats_bb,
 201                          tx_4096_to_9216_byte_packets)},
 202         {"tx_9217_to_16383_byte_packets",
 203                 offsetof(struct ecore_eth_stats, bb) +
 204                 offsetof(struct ecore_eth_stats_bb,
 205                          tx_9217_to_16383_byte_packets)},
 206
 207         {"tx_lpi_entry_count",
 208                 offsetof(struct ecore_eth_stats, bb) +
 209                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 210         {"tx_total_collisions",
 211                 offsetof(struct ecore_eth_stats, bb) +
 212                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 213 };
 214
 215 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 216         {"rx_1519_to_max_byte_packets",
 217                 offsetof(struct ecore_eth_stats, ah) +
 218                 offsetof(struct ecore_eth_stats_ah,
 219                          rx_1519_to_max_byte_packets)},
 220         {"tx_1519_to_max_byte_packets",
 221                 offsetof(struct ecore_eth_stats, ah) +
 222                 offsetof(struct ecore_eth_stats_ah,
 223                          tx_1519_to_max_byte_packets)},
 224 };
 225
 226 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 227         {"rx_q_segments",
 228                 offsetof(struct qede_rx_queue, rx_segs)},
 229         {"rx_q_hw_errors",
 230                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 231         {"rx_q_allocation_errors",
 232                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 233 };
 234
 235 /* Get FW version string based on fw_size */
 236 static int
 237 qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
 238 {
 239         struct qede_dev *qdev = dev->data->dev_private;
 240         struct ecore_dev *edev = &qdev->edev;
 241         struct qed_dev_info *info = &qdev->dev_info.common;
 242         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 243         size_t size;
 244
 245         if (fw_ver == NULL)
 246                 return 0;
 247
 248         if (IS_PF(edev))
 249                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 250                          QEDE_PMD_FW_VERSION);
 251         else
 252                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 253                          info->fw_major, info->fw_minor,
 254                          info->fw_rev, info->fw_eng);
 255         size = strlen(ver_str);
 256         if (size + 1 <= fw_size) /* Add 1 byte for "\0" */
 257                 strlcpy(fw_ver, ver_str, fw_size);
 258         else
 259                 return (size + 1);
 260
 261         snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
 262                  " MFW: %d.%d.%d.%d",
 263                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_3),
 264                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_2),
 265                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_1),
 266                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_0));
 267         size = strlen(ver_str);
 268         if (size + 1 <= fw_size)
 269                 strlcpy(fw_ver, ver_str, fw_size);
 270
 271         if (fw_size <= 32)
 272                 goto out;
 273
 274         snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
 275                  " MBI: %d.%d.%d",
 276                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_2),
 277                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_1),
 278                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_0));
 279         size = strlen(ver_str);
 280         if (size + 1 <= fw_size)
 281                 strlcpy(fw_ver, ver_str, fw_size);
 282
 283 out:
 284         return 0;
 285 }
 286
 287 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 288 {
 289         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 290 }
 291
 292 static void
 293 qede_interrupt_handler_intx(void *param)
 294 {
 295         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 296         struct qede_dev *qdev = eth_dev->data->dev_private;
 297         struct ecore_dev *edev = &qdev->edev;
 298         u64 status;
 299
 300         /* Check if our device actually raised an interrupt */
 301         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 302         if (status & 0x1) {
 303                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 304
 305                 if (rte_intr_ack(eth_dev->intr_handle))
 306                         DP_ERR(edev, "rte_intr_ack failed\n");
 307         }
 308 }
 309
 310 static void
 311 qede_interrupt_handler(void *param)
 312 {
 313         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 314         struct qede_dev *qdev = eth_dev->data->dev_private;
 315         struct ecore_dev *edev = &qdev->edev;
 316
 317         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 318         if (rte_intr_ack(eth_dev->intr_handle))
 319                 DP_ERR(edev, "rte_intr_ack failed\n");
 320 }
 321
 322 static void
 323 qede_assign_rxtx_handlers(struct rte_eth_dev *dev, bool is_dummy)
 324 {
 325         uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
 326         struct qede_dev *qdev = dev->data->dev_private;
 327         struct ecore_dev *edev = &qdev->edev;
 328         bool use_tx_offload = false;
 329
 330         if (is_dummy) {
 331                 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
 332                 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
 333                 return;
 334         }
 335
 336         if (ECORE_IS_CMT(edev)) {
 337                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
 338                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
 339                 return;
 340         }
 341
 342         if (dev->data->lro || dev->data->scattered_rx) {
 343                 DP_INFO(edev, "Assigning qede_recv_pkts\n");
 344                 dev->rx_pkt_burst = qede_recv_pkts;
 345         } else {
 346                 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n");
 347                 dev->rx_pkt_burst = qede_recv_pkts_regular;
 348         }
 349
 350         use_tx_offload = !!(tx_offloads &
 351                             (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */
 352                              DEV_TX_OFFLOAD_TCP_TSO | /* tso */
 353                              DEV_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */
 354
 355         if (use_tx_offload) {
 356                 DP_INFO(edev, "Assigning qede_xmit_pkts\n");
 357                 dev->tx_pkt_burst = qede_xmit_pkts;
 358         } else {
 359                 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n");
 360                 dev->tx_pkt_burst = qede_xmit_pkts_regular;
 361         }
 362 }
 363
 364 static void
 365 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 366 {
 367         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 368         qdev->ops = qed_ops;
 369 }
 370
 371 static void qede_print_adapter_info(struct rte_eth_dev *dev)
 372 {
 373         struct qede_dev *qdev = dev->data->dev_private;
 374         struct ecore_dev *edev = &qdev->edev;
 375         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 376
 377         DP_INFO(edev, "**************************************************\n");
 378         DP_INFO(edev, " %-20s: %s\n", "DPDK version", rte_version());
 379         DP_INFO(edev, " %-20s: %s %c%d\n", "Chip details",
 380                   ECORE_IS_BB(edev) ? "BB" : "AH",
 381                   'A' + edev->chip_rev,
 382                   (int)edev->chip_metal);
 383         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 384                  QEDE_PMD_DRV_VERSION);
 385         DP_INFO(edev, " %-20s: %s\n", "Driver version", ver_str);
 386         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 387                  QEDE_PMD_BASE_VERSION);
 388         DP_INFO(edev, " %-20s: %s\n", "Base version", ver_str);
 389         qede_fw_version_get(dev, ver_str, sizeof(ver_str));
 390         DP_INFO(edev, " %-20s: %s\n", "Firmware version", ver_str);
 391         DP_INFO(edev, " %-20s: %s\n", "Firmware file", qede_fw_file);
 392         DP_INFO(edev, "**************************************************\n");
 393 }
 394
 395 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 396 {
 397         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 398         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 399         unsigned int i = 0, j = 0, qid;
 400         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 401         struct qede_tx_queue *txq;
 402
 403         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 404
 405         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 406                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 407         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 408                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 409
 410         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 411                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 412                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 413                             sizeof(uint64_t));
 414                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 415                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 416                             sizeof(uint64_t));
 417                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 418                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 419                             sizeof(uint64_t));
 420
 421                 if (xstats)
 422                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 423                                 OSAL_MEMSET((((char *)
 424                                               (qdev->fp_array[qid].rxq)) +
 425                                              qede_rxq_xstats_strings[j].offset),
 426                                             0,
 427                                             sizeof(uint64_t));
 428
 429                 i++;
 430                 if (i == rxq_stat_cntrs)
 431                         break;
 432         }
 433
 434         i = 0;
 435
 436         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 437                 txq = qdev->fp_array[qid].txq;
 438
 439                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 440                                 (((uint64_t)(uintptr_t)(txq)) +
 441                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 442                             sizeof(uint64_t));
 443
 444                 i++;
 445                 if (i == txq_stat_cntrs)
 446                         break;
 447         }
 448 }
 449
 450 static int
 451 qede_stop_vport(struct ecore_dev *edev)
 452 {
 453         struct ecore_hwfn *p_hwfn;
 454         uint8_t vport_id;
 455         int rc;
 456         int i;
 457
 458         vport_id = 0;
 459         for_each_hwfn(edev, i) {
 460                 p_hwfn = &edev->hwfns[i];
 461                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 462                                          vport_id);
 463                 if (rc != ECORE_SUCCESS) {
 464                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 465                         return rc;
 466                 }
 467         }
 468
 469         DP_INFO(edev, "vport stopped\n");
 470
 471         return 0;
 472 }
 473
 474 static int
 475 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 476 {
 477         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 478         struct ecore_sp_vport_start_params params;
 479         struct ecore_hwfn *p_hwfn;
 480         int rc;
 481         int i;
 482
 483         if (qdev->vport_started)
 484                 qede_stop_vport(edev);
 485
 486         memset(&params, 0, sizeof(params));
 487         params.vport_id = 0;
 488         params.mtu = mtu;
 489         /* @DPDK - Disable FW placement */
 490         params.zero_placement_offset = 1;
 491         for_each_hwfn(edev, i) {
 492                 p_hwfn = &edev->hwfns[i];
 493                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 494                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 495                 rc = ecore_sp_vport_start(p_hwfn, &params);
 496                 if (rc != ECORE_SUCCESS) {
 497                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 498                         return rc;
 499                 }
 500         }
 501         ecore_reset_vport_stats(edev);
 502         qdev->vport_started = true;
 503         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 504
 505         return 0;
 506 }
 507
 508 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 509 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 510
 511 /* Activate or deactivate vport via vport-update */
 512 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 513 {
 514         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 515         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 516         struct ecore_sp_vport_update_params params;
 517         struct ecore_hwfn *p_hwfn;
 518         uint8_t i;
 519         int rc = -1;
 520
 521         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 522         params.vport_id = 0;
 523         params.update_vport_active_rx_flg = 1;
 524         params.update_vport_active_tx_flg = 1;
 525         params.vport_active_rx_flg = flg;
 526         params.vport_active_tx_flg = flg;
 527         if ((qdev->enable_tx_switching == false) && (flg == true)) {
 528                 params.update_tx_switching_flg = 1;
 529                 params.tx_switching_flg = !flg;
 530         }
 531         for_each_hwfn(edev, i) {
 532                 p_hwfn = &edev->hwfns[i];
 533                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 534                 rc = ecore_sp_vport_update(p_hwfn, &params,
 535                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 536                 if (rc != ECORE_SUCCESS) {
 537                         DP_ERR(edev, "Failed to update vport\n");
 538                         break;
 539                 }
 540         }
 541         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 542
 543         return rc;
 544 }
 545
 546 static void
 547 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 548                            uint16_t mtu, bool enable)
 549 {
 550         /* Enable LRO in split mode */
 551         sge_tpa_params->tpa_ipv4_en_flg = enable;
 552         sge_tpa_params->tpa_ipv6_en_flg = enable;
 553         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 554         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 555         /* set if tpa enable changes */
 556         sge_tpa_params->update_tpa_en_flg = 1;
 557         /* set if tpa parameters should be handled */
 558         sge_tpa_params->update_tpa_param_flg = enable;
 559
 560         sge_tpa_params->max_buffers_per_cqe = 20;
 561         /* Enable TPA in split mode. In this mode each TPA segment
 562          * starts on the new BD, so there is one BD per segment.
 563          */
 564         sge_tpa_params->tpa_pkt_split_flg = 1;
 565         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 566         sge_tpa_params->tpa_gro_consistent_flg = 0;
 567         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 568         sge_tpa_params->tpa_max_size = 0x7FFF;
 569         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 570         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 571 }
 572
 573 /* Enable/disable LRO via vport-update */
 574 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 575 {
 576         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 577         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 578         struct ecore_sp_vport_update_params params;
 579         struct ecore_sge_tpa_params tpa_params;
 580         struct ecore_hwfn *p_hwfn;
 581         int rc;
 582         int i;
 583
 584         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 585         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 586         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 587         params.vport_id = 0;
 588         params.sge_tpa_params = &tpa_params;
 589         for_each_hwfn(edev, i) {
 590                 p_hwfn = &edev->hwfns[i];
 591                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 592                 rc = ecore_sp_vport_update(p_hwfn, &params,
 593                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 594                 if (rc != ECORE_SUCCESS) {
 595                         DP_ERR(edev, "Failed to update LRO\n");
 596                         return -1;
 597                 }
 598         }
 599         qdev->enable_lro = flg;
 600         eth_dev->data->lro = flg;
 601
 602         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 603
 604         return 0;
 605 }
 606
 607 static int
 608 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 609                              enum qed_filter_rx_mode_type type)
 610 {
 611         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 612         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 613         struct ecore_filter_accept_flags flags;
 614
 615         memset(&flags, 0, sizeof(flags));
 616
 617         flags.update_rx_mode_config = 1;
 618         flags.update_tx_mode_config = 1;
 619         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 620                 ECORE_ACCEPT_MCAST_MATCHED |
 621                 ECORE_ACCEPT_BCAST;
 622
 623         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 624                 ECORE_ACCEPT_MCAST_MATCHED |
 625                 ECORE_ACCEPT_BCAST;
 626
 627         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 628                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 629                 if (IS_VF(edev)) {
 630                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 631                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 632                 }
 633         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 634                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 635         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 636                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 637                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 638                         ECORE_ACCEPT_MCAST_UNMATCHED;
 639         }
 640
 641         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 642                         ECORE_SPQ_MODE_CB, NULL);
 643 }
 644
 645 int
 646 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 647                   bool add)
 648 {
 649         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 650         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 651         struct qede_ucast_entry *tmp = NULL;
 652         struct qede_ucast_entry *u;
 653         struct rte_ether_addr *mac_addr;
 654
 655         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 656         if (add) {
 657                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 658                         if ((memcmp(mac_addr, &tmp->mac,
 659                                     RTE_ETHER_ADDR_LEN) == 0) &&
 660                              ucast->vni == tmp->vni &&
 661                              ucast->vlan == tmp->vlan) {
 662                                 DP_INFO(edev, "Unicast MAC is already added"
 663                                         " with vlan = %u, vni = %u\n",
 664                                         ucast->vlan,  ucast->vni);
 665                                         return 0;
 666                         }
 667                 }
 668                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 669                                RTE_CACHE_LINE_SIZE);
 670                 if (!u) {
 671                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 672                         return -ENOMEM;
 673                 }
 674                 rte_ether_addr_copy(mac_addr, &u->mac);
 675                 u->vlan = ucast->vlan;
 676                 u->vni = ucast->vni;
 677                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 678                 qdev->num_uc_addr++;
 679         } else {
 680                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 681                         if ((memcmp(mac_addr, &tmp->mac,
 682                                     RTE_ETHER_ADDR_LEN) == 0) &&
 683                             ucast->vlan == tmp->vlan      &&
 684                             ucast->vni == tmp->vni)
 685                         break;
 686                 }
 687                 if (tmp == NULL) {
 688                         DP_INFO(edev, "Unicast MAC is not found\n");
 689                         return -EINVAL;
 690                 }
 691                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 692                 qdev->num_uc_addr--;
 693         }
 694
 695         return 0;
 696 }
 697
 698 static int
 699 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 700                 struct rte_ether_addr *mc_addrs,
 701                 uint32_t mc_addrs_num)
 702 {
 703         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 704         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 705         struct ecore_filter_mcast mcast;
 706         struct qede_mcast_entry *m = NULL;
 707         uint8_t i;
 708         int rc;
 709
 710         for (i = 0; i < mc_addrs_num; i++) {
 711                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 712                                RTE_CACHE_LINE_SIZE);
 713                 if (!m) {
 714                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 715                         return -ENOMEM;
 716                 }
 717                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 718                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 719         }
 720         memset(&mcast, 0, sizeof(mcast));
 721         mcast.num_mc_addrs = mc_addrs_num;
 722         mcast.opcode = ECORE_FILTER_ADD;
 723         for (i = 0; i < mc_addrs_num; i++)
 724                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 725                                                         &mcast.mac[i]);
 726         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 727         if (rc != ECORE_SUCCESS) {
 728                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 729                 return -1;
 730         }
 731
 732         return 0;
 733 }
 734
 735 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 736 {
 737         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 738         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 739         struct qede_mcast_entry *tmp = NULL;
 740         struct ecore_filter_mcast mcast;
 741         int j;
 742         int rc;
 743
 744         memset(&mcast, 0, sizeof(mcast));
 745         mcast.num_mc_addrs = qdev->num_mc_addr;
 746         mcast.opcode = ECORE_FILTER_REMOVE;
 747         j = 0;
 748         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 749                 rte_ether_addr_copy(&tmp->mac,
 750                                 (struct rte_ether_addr *)&mcast.mac[j]);
 751                 j++;
 752         }
 753         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 754         if (rc != ECORE_SUCCESS) {
 755                 DP_ERR(edev, "Failed to delete multicast filter\n");
 756                 return -1;
 757         }
 758         /* Init the list */
 759         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 760                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 761                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 762         }
 763         SLIST_INIT(&qdev->mc_list_head);
 764
 765         return 0;
 766 }
 767
 768 enum _ecore_status_t
 769 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 770                  bool add)
 771 {
 772         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 773         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 774         enum _ecore_status_t rc = ECORE_INVAL;
 775
 776         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 777                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 778                               " Please enable promisc mode\n");
 779                         return ECORE_INVAL;
 780         }
 781
 782         rc = qede_ucast_filter(eth_dev, ucast, add);
 783         if (rc == 0)
 784                 rc = ecore_filter_ucast_cmd(edev, ucast,
 785                                             ECORE_SPQ_MODE_CB, NULL);
 786         /* Indicate error only for add filter operation.
 787          * Delete filter operations are not severe.
 788          */
 789         if ((rc != ECORE_SUCCESS) && add)
 790                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 791                        rc, add);
 792
 793         return rc;
 794 }
 795
 796 static int
 797 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 798                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 799 {
 800         struct ecore_filter_ucast ucast;
 801         int re;
 802
 803         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 804                 return -EINVAL;
 805
 806         qede_set_ucast_cmn_params(&ucast);
 807         ucast.opcode = ECORE_FILTER_ADD;
 808         ucast.type = ECORE_FILTER_MAC;
 809         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 810         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 811         return re;
 812 }
 813
 814 static void
 815 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 816 {
 817         struct qede_dev *qdev = eth_dev->data->dev_private;
 818         struct ecore_dev *edev = &qdev->edev;
 819         struct ecore_filter_ucast ucast;
 820
 821         PMD_INIT_FUNC_TRACE(edev);
 822
 823         if (index >= qdev->dev_info.num_mac_filters) {
 824                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 825                        index, qdev->dev_info.num_mac_filters);
 826                 return;
 827         }
 828
 829         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 830                 return;
 831
 832         qede_set_ucast_cmn_params(&ucast);
 833         ucast.opcode = ECORE_FILTER_REMOVE;
 834         ucast.type = ECORE_FILTER_MAC;
 835
 836         /* Use the index maintained by rte */
 837         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 838                         (struct rte_ether_addr *)&ucast.mac);
 839
 840         qede_mac_int_ops(eth_dev, &ucast, false);
 841 }
 842
 843 static int
 844 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 845 {
 846         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 847         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 848
 849         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 850                                                mac_addr->addr_bytes)) {
 851                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 852                 return -EPERM;
 853         }
 854
 855         qede_mac_addr_remove(eth_dev, 0);
 856
 857         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 858 }
 859
 860 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 861 {
 862         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 863         struct ecore_sp_vport_update_params params;
 864         struct ecore_hwfn *p_hwfn;
 865         uint8_t i;
 866         int rc;
 867
 868         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 869         params.vport_id = 0;
 870         params.update_accept_any_vlan_flg = 1;
 871         params.accept_any_vlan = flg;
 872         for_each_hwfn(edev, i) {
 873                 p_hwfn = &edev->hwfns[i];
 874                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 875                 rc = ecore_sp_vport_update(p_hwfn, &params,
 876                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 877                 if (rc != ECORE_SUCCESS) {
 878                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 879                         return;
 880                 }
 881         }
 882
 883         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 884 }
 885
 886 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 887 {
 888         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 889         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 890         struct ecore_sp_vport_update_params params;
 891         struct ecore_hwfn *p_hwfn;
 892         uint8_t i;
 893         int rc;
 894
 895         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 896         params.vport_id = 0;
 897         params.update_inner_vlan_removal_flg = 1;
 898         params.inner_vlan_removal_flg = flg;
 899         for_each_hwfn(edev, i) {
 900                 p_hwfn = &edev->hwfns[i];
 901                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 902                 rc = ecore_sp_vport_update(p_hwfn, &params,
 903                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 904                 if (rc != ECORE_SUCCESS) {
 905                         DP_ERR(edev, "Failed to update vport\n");
 906                         return -1;
 907                 }
 908         }
 909
 910         qdev->vlan_strip_flg = flg;
 911
 912         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 913         return 0;
 914 }
 915
 916 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 917                                 uint16_t vlan_id, int on)
 918 {
 919         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 920         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 921         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 922         struct qede_vlan_entry *tmp = NULL;
 923         struct qede_vlan_entry *vlan;
 924         struct ecore_filter_ucast ucast;
 925         int rc;
 926
 927         if (on) {
 928                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 929                         DP_ERR(edev, "Reached max VLAN filter limit"
 930                                       " enabling accept_any_vlan\n");
 931                         qede_config_accept_any_vlan(qdev, true);
 932                         return 0;
 933                 }
 934
 935                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 936                         if (tmp->vid == vlan_id) {
 937                                 DP_INFO(edev, "VLAN %u already configured\n",
 938                                         vlan_id);
 939                                 return 0;
 940                         }
 941                 }
 942
 943                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 944                                   RTE_CACHE_LINE_SIZE);
 945
 946                 if (!vlan) {
 947                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 948                         return -ENOMEM;
 949                 }
 950
 951                 qede_set_ucast_cmn_params(&ucast);
 952                 ucast.opcode = ECORE_FILTER_ADD;
 953                 ucast.type = ECORE_FILTER_VLAN;
 954                 ucast.vlan = vlan_id;
 955                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 956                                             NULL);
 957                 if (rc != 0) {
 958                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 959                                rc);
 960                         rte_free(vlan);
 961                 } else {
 962                         vlan->vid = vlan_id;
 963                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 964                         qdev->configured_vlans++;
 965                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 966                                 vlan_id, qdev->configured_vlans);
 967                 }
 968         } else {
 969                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 970                         if (tmp->vid == vlan_id)
 971                                 break;
 972                 }
 973
 974                 if (!tmp) {
 975                         if (qdev->configured_vlans == 0) {
 976                                 DP_INFO(edev,
 977                                         "No VLAN filters configured yet\n");
 978                                 return 0;
 979                         }
 980
 981                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 982                         return -EINVAL;
 983                 }
 984
 985                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 986
 987                 qede_set_ucast_cmn_params(&ucast);
 988                 ucast.opcode = ECORE_FILTER_REMOVE;
 989                 ucast.type = ECORE_FILTER_VLAN;
 990                 ucast.vlan = vlan_id;
 991                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 992                                             NULL);
 993                 if (rc != 0) {
 994                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 995                                vlan_id, rc);
 996                 } else {
 997                         qdev->configured_vlans--;
 998                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 999                                 vlan_id, qdev->configured_vlans);
1000                 }
1001         }
1002
1003         return rc;
1004 }
1005
1006 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1007 {
1008         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1009         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1010         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1011
1012         if (mask & ETH_VLAN_STRIP_MASK) {
1013                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1014                         (void)qede_vlan_stripping(eth_dev, 1);
1015                 else
1016                         (void)qede_vlan_stripping(eth_dev, 0);
1017         }
1018
1019         if (mask & ETH_VLAN_FILTER_MASK) {
1020                 /* VLAN filtering kicks in when a VLAN is added */
1021                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1022                         qede_vlan_filter_set(eth_dev, 0, 1);
1023                 } else {
1024                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1025                                 DP_ERR(edev,
1026                                   " Please remove existing VLAN filters"
1027                                   " before disabling VLAN filtering\n");
1028                                 /* Signal app that VLAN filtering is still
1029                                  * enabled
1030                                  */
1031                                 eth_dev->data->dev_conf.rxmode.offloads |=
1032                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1033                         } else {
1034                                 qede_vlan_filter_set(eth_dev, 0, 0);
1035                         }
1036                 }
1037         }
1038
1039         if (mask & ETH_VLAN_EXTEND_MASK)
1040                 DP_ERR(edev, "Extend VLAN not supported\n");
1041
1042         qdev->vlan_offload_mask = mask;
1043
1044         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1045
1046         return 0;
1047 }
1048
1049 static void qede_prandom_bytes(uint32_t *buff)
1050 {
1051         uint8_t i;
1052
1053         srand((unsigned int)time(NULL));
1054         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1055                 buff[i] = rand();
1056 }
1057
1058 int qede_config_rss(struct rte_eth_dev *eth_dev)
1059 {
1060         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1061         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1062         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1063         struct rte_eth_rss_reta_entry64 reta_conf[2];
1064         struct rte_eth_rss_conf rss_conf;
1065         uint32_t i, id, pos, q;
1066
1067         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1068         if (!rss_conf.rss_key) {
1069                 DP_INFO(edev, "Applying driver default key\n");
1070                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1071                 qede_prandom_bytes(&def_rss_key[0]);
1072                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1073         }
1074
1075         /* Configure RSS hash */
1076         if (qede_rss_hash_update(eth_dev, &rss_conf))
1077                 return -EINVAL;
1078
1079         /* Configure default RETA */
1080         memset(reta_conf, 0, sizeof(reta_conf));
1081         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1082                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1083
1084         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1085                 id = i / RTE_RETA_GROUP_SIZE;
1086                 pos = i % RTE_RETA_GROUP_SIZE;
1087                 q = i % QEDE_RSS_COUNT(eth_dev);
1088                 reta_conf[id].reta[pos] = q;
1089         }
1090         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1091                                  ECORE_RSS_IND_TABLE_SIZE))
1092                 return -EINVAL;
1093
1094         return 0;
1095 }
1096
1097 static void qede_fastpath_start(struct ecore_dev *edev)
1098 {
1099         struct ecore_hwfn *p_hwfn;
1100         int i;
1101
1102         for_each_hwfn(edev, i) {
1103                 p_hwfn = &edev->hwfns[i];
1104                 ecore_hw_start_fastpath(p_hwfn);
1105         }
1106 }
1107
1108 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1109 {
1110         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1111         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1112         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1113
1114         PMD_INIT_FUNC_TRACE(edev);
1115
1116         /* Update MTU only if it has changed */
1117         if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1118                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1119                         goto err;
1120                 qdev->mtu = qdev->new_mtu;
1121                 qdev->new_mtu = 0;
1122         }
1123
1124         /* Configure TPA parameters */
1125         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1126                 if (qede_enable_tpa(eth_dev, true))
1127                         return -EINVAL;
1128                 /* Enable scatter mode for LRO */
1129                 if (!eth_dev->data->scattered_rx)
1130                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1131         }
1132
1133         /* Start queues */
1134         if (qede_start_queues(eth_dev))
1135                 goto err;
1136
1137         if (IS_PF(edev))
1138                 qede_reset_queue_stats(qdev, true);
1139
1140         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1141          * enabling RSS. Hence RSS configuration is deferred up to this point.
1142          * Also, we would like to retain similar behavior in PF case, so we
1143          * don't do PF/VF specific check here.
1144          */
1145         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1146                 if (qede_config_rss(eth_dev))
1147                         goto err;
1148
1149         /* Enable vport*/
1150         if (qede_activate_vport(eth_dev, true))
1151                 goto err;
1152
1153         /* Bring-up the link */
1154         qede_dev_set_link_state(eth_dev, true);
1155
1156         /* Update link status */
1157         qede_link_update(eth_dev, 0);
1158
1159         /* Start/resume traffic */
1160         qede_fastpath_start(edev);
1161
1162         /* Assign I/O handlers */
1163         qede_assign_rxtx_handlers(eth_dev, false);
1164
1165         DP_INFO(edev, "Device started\n");
1166
1167         return 0;
1168 err:
1169         DP_ERR(edev, "Device start fails\n");
1170         return -1; /* common error code is < 0 */
1171 }
1172
1173 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1174 {
1175         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1176         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1177
1178         PMD_INIT_FUNC_TRACE(edev);
1179
1180         /* Bring the link down */
1181         qede_dev_set_link_state(eth_dev, false);
1182
1183         /* Update link status */
1184         qede_link_update(eth_dev, 0);
1185
1186         /* Replace I/O functions with dummy ones. It cannot
1187          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1188          */
1189         qede_assign_rxtx_handlers(eth_dev, true);
1190
1191         /* Disable vport */
1192         if (qede_activate_vport(eth_dev, false))
1193                 return;
1194
1195         if (qdev->enable_lro)
1196                 qede_enable_tpa(eth_dev, false);
1197
1198         /* Stop queues */
1199         qede_stop_queues(eth_dev);
1200
1201         /* Disable traffic */
1202         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1203
1204         DP_INFO(edev, "Device is stopped\n");
1205 }
1206
1207 static const char * const valid_args[] = {
1208         QEDE_NPAR_TX_SWITCHING,
1209         QEDE_VF_TX_SWITCHING,
1210         NULL,
1211 };
1212
1213 static int qede_args_check(const char *key, const char *val, void *opaque)
1214 {
1215         unsigned long tmp;
1216         int ret = 0;
1217         struct rte_eth_dev *eth_dev = opaque;
1218         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1219         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1220
1221         errno = 0;
1222         tmp = strtoul(val, NULL, 0);
1223         if (errno) {
1224                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1225                 return errno;
1226         }
1227
1228         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1229             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1230                 qdev->enable_tx_switching = !!tmp;
1231                 DP_INFO(edev, "Disabling %s tx-switching\n",
1232                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1233                         "VF" : "NPAR");
1234         }
1235
1236         return ret;
1237 }
1238
1239 static int qede_args(struct rte_eth_dev *eth_dev)
1240 {
1241         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1242         struct rte_kvargs *kvlist;
1243         struct rte_devargs *devargs;
1244         int ret;
1245         int i;
1246
1247         devargs = pci_dev->device.devargs;
1248         if (!devargs)
1249                 return 0; /* return success */
1250
1251         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1252         if (kvlist == NULL)
1253                 return -EINVAL;
1254
1255          /* Process parameters. */
1256         for (i = 0; (valid_args[i] != NULL); ++i) {
1257                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1258                         ret = rte_kvargs_process(kvlist, valid_args[i],
1259                                                  qede_args_check, eth_dev);
1260                         if (ret != ECORE_SUCCESS) {
1261                                 rte_kvargs_free(kvlist);
1262                                 return ret;
1263                         }
1264                 }
1265         }
1266         rte_kvargs_free(kvlist);
1267
1268         return 0;
1269 }
1270
1271 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1272 {
1273         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1274         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1275         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1276         uint8_t num_rxqs;
1277         uint8_t num_txqs;
1278         int ret;
1279
1280         PMD_INIT_FUNC_TRACE(edev);
1281
1282         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
1283                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1284
1285         /* We need to have min 1 RX queue.There is no min check in
1286          * rte_eth_dev_configure(), so we are checking it here.
1287          */
1288         if (eth_dev->data->nb_rx_queues == 0) {
1289                 DP_ERR(edev, "Minimum one RX queue is required\n");
1290                 return -EINVAL;
1291         }
1292
1293         /* Enable Tx switching by default */
1294         qdev->enable_tx_switching = 1;
1295
1296         /* Parse devargs and fix up rxmode */
1297         if (qede_args(eth_dev))
1298                 DP_NOTICE(edev, false,
1299                           "Invalid devargs supplied, requested change will not take effect\n");
1300
1301         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1302               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1303                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1304                 return -ENOTSUP;
1305         }
1306         /* Flow director mode check */
1307         if (qede_check_fdir_support(eth_dev))
1308                 return -ENOTSUP;
1309
1310         /* Allocate/reallocate fastpath resources only for new queue config */
1311         num_txqs = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1312         num_rxqs = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1313         if (qdev->num_tx_queues != num_txqs ||
1314             qdev->num_rx_queues != num_rxqs) {
1315                 qede_dealloc_fp_resc(eth_dev);
1316                 qdev->num_tx_queues = num_txqs;
1317                 qdev->num_rx_queues = num_rxqs;
1318                 if (qede_alloc_fp_resc(qdev))
1319                         return -ENOMEM;
1320         }
1321
1322         /* If jumbo enabled adjust MTU */
1323         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1324                 eth_dev->data->mtu =
1325                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1326                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1327
1328         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1329                 eth_dev->data->scattered_rx = 1;
1330
1331         if (qede_start_vport(qdev, eth_dev->data->mtu))
1332                 return -1;
1333
1334         qdev->mtu = eth_dev->data->mtu;
1335
1336         /* Enable VLAN offloads by default */
1337         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1338                                              ETH_VLAN_FILTER_MASK);
1339         if (ret)
1340                 return ret;
1341
1342         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1343                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1344
1345         if (ECORE_IS_CMT(edev))
1346                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1347                         qdev->num_rx_queues, qdev->num_tx_queues);
1348
1349
1350         return 0;
1351 }
1352
1353 /* Info about HW descriptor ring limitations */
1354 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1355         .nb_max = 0x8000, /* 32K */
1356         .nb_min = 128,
1357         .nb_align = 128 /* lowest common multiple */
1358 };
1359
1360 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1361         .nb_max = 0x8000, /* 32K */
1362         .nb_min = 256,
1363         .nb_align = 256,
1364         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1365         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1366 };
1367
1368 static int
1369 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1370                   struct rte_eth_dev_info *dev_info)
1371 {
1372         struct qede_dev *qdev = eth_dev->data->dev_private;
1373         struct ecore_dev *edev = &qdev->edev;
1374         struct qed_link_output link;
1375         uint32_t speed_cap = 0;
1376
1377         PMD_INIT_FUNC_TRACE(edev);
1378
1379         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1380         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1381         dev_info->rx_desc_lim = qede_rx_desc_lim;
1382         dev_info->tx_desc_lim = qede_tx_desc_lim;
1383
1384         if (IS_PF(edev))
1385                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1386                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1387         else
1388                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1389                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1390         /* Since CMT mode internally doubles the number of queues */
1391         if (ECORE_IS_CMT(edev))
1392                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1393
1394         dev_info->max_tx_queues = dev_info->max_rx_queues;
1395
1396         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1397         dev_info->max_vfs = 0;
1398         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1399         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1400         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1401         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1402                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1403                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1404                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1405                                      DEV_RX_OFFLOAD_TCP_LRO     |
1406                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1407                                      DEV_RX_OFFLOAD_SCATTER     |
1408                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1409                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1410                                      DEV_RX_OFFLOAD_VLAN_STRIP  |
1411                                      DEV_RX_OFFLOAD_RSS_HASH);
1412         dev_info->rx_queue_offload_capa = 0;
1413
1414         /* TX offloads are on a per-packet basis, so it is applicable
1415          * to both at port and queue levels.
1416          */
1417         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1418                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1419                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1420                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1421                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1422                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1423                                      DEV_TX_OFFLOAD_TCP_TSO     |
1424                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1425                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1426         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1427
1428         dev_info->default_txconf = (struct rte_eth_txconf) {
1429                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1430         };
1431
1432         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1433                 /* Packets are always dropped if no descriptors are available */
1434                 .rx_drop_en = 1,
1435                 .offloads = 0,
1436         };
1437
1438         memset(&link, 0, sizeof(struct qed_link_output));
1439         qdev->ops->common->get_link(edev, &link);
1440         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1441                 speed_cap |= ETH_LINK_SPEED_1G;
1442         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1443                 speed_cap |= ETH_LINK_SPEED_10G;
1444         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1445                 speed_cap |= ETH_LINK_SPEED_25G;
1446         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1447                 speed_cap |= ETH_LINK_SPEED_40G;
1448         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1449                 speed_cap |= ETH_LINK_SPEED_50G;
1450         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1451                 speed_cap |= ETH_LINK_SPEED_100G;
1452         dev_info->speed_capa = speed_cap;
1453
1454         return 0;
1455 }
1456
1457 /* return 0 means link status changed, -1 means not changed */
1458 int
1459 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1460 {
1461         struct qede_dev *qdev = eth_dev->data->dev_private;
1462         struct ecore_dev *edev = &qdev->edev;
1463         struct qed_link_output q_link;
1464         struct rte_eth_link link;
1465         uint16_t link_duplex;
1466
1467         memset(&q_link, 0, sizeof(q_link));
1468         memset(&link, 0, sizeof(link));
1469
1470         qdev->ops->common->get_link(edev, &q_link);
1471
1472         /* Link Speed */
1473         link.link_speed = q_link.speed;
1474
1475         /* Link Mode */
1476         switch (q_link.duplex) {
1477         case QEDE_DUPLEX_HALF:
1478                 link_duplex = ETH_LINK_HALF_DUPLEX;
1479                 break;
1480         case QEDE_DUPLEX_FULL:
1481                 link_duplex = ETH_LINK_FULL_DUPLEX;
1482                 break;
1483         case QEDE_DUPLEX_UNKNOWN:
1484         default:
1485                 link_duplex = -1;
1486         }
1487         link.link_duplex = link_duplex;
1488
1489         /* Link Status */
1490         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1491
1492         /* AN */
1493         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1494                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1495
1496         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1497                 link.link_speed, link.link_duplex,
1498                 link.link_autoneg, link.link_status);
1499
1500         return rte_eth_linkstatus_set(eth_dev, &link);
1501 }
1502
1503 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1504 {
1505         struct qede_dev *qdev = eth_dev->data->dev_private;
1506         struct ecore_dev *edev = &qdev->edev;
1507         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1508         enum _ecore_status_t ecore_status;
1509
1510         PMD_INIT_FUNC_TRACE(edev);
1511
1512         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1513                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1514
1515         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1516
1517         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1518 }
1519
1520 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1521 {
1522         struct qede_dev *qdev = eth_dev->data->dev_private;
1523         struct ecore_dev *edev = &qdev->edev;
1524         enum _ecore_status_t ecore_status;
1525
1526         PMD_INIT_FUNC_TRACE(edev);
1527
1528         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1529                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1530                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1531         else
1532                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1533                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1534
1535         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1536 }
1537
1538 static void qede_poll_sp_sb_cb(void *param)
1539 {
1540         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1541         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1542         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1543         int rc;
1544
1545         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1546         qede_interrupt_action(&edev->hwfns[1]);
1547
1548         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1549                                qede_poll_sp_sb_cb,
1550                                (void *)eth_dev);
1551         if (rc != 0) {
1552                 DP_ERR(edev, "Unable to start periodic"
1553                              " timer rc %d\n", rc);
1554         }
1555 }
1556
1557 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1558 {
1559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1560         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1561         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1562
1563         PMD_INIT_FUNC_TRACE(edev);
1564
1565         /* dev_stop() shall cleanup fp resources in hw but without releasing
1566          * dma memories and sw structures so that dev_start() can be called
1567          * by the app without reconfiguration. However, in dev_close() we
1568          * can release all the resources and device can be brought up newly
1569          */
1570         if (eth_dev->data->dev_started)
1571                 qede_dev_stop(eth_dev);
1572
1573         if (qdev->vport_started)
1574                 qede_stop_vport(edev);
1575         qdev->vport_started = false;
1576         qede_fdir_dealloc_resc(eth_dev);
1577         qede_dealloc_fp_resc(eth_dev);
1578
1579         eth_dev->data->nb_rx_queues = 0;
1580         eth_dev->data->nb_tx_queues = 0;
1581
1582         qdev->ops->common->slowpath_stop(edev);
1583         qdev->ops->common->remove(edev);
1584         rte_intr_disable(&pci_dev->intr_handle);
1585
1586         switch (pci_dev->intr_handle.type) {
1587         case RTE_INTR_HANDLE_UIO_INTX:
1588         case RTE_INTR_HANDLE_VFIO_LEGACY:
1589                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1590                                              qede_interrupt_handler_intx,
1591                                              (void *)eth_dev);
1592                 break;
1593         default:
1594                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1595                                            qede_interrupt_handler,
1596                                            (void *)eth_dev);
1597         }
1598
1599         if (ECORE_IS_CMT(edev))
1600                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1601 }
1602
1603 static int
1604 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1605 {
1606         struct qede_dev *qdev = eth_dev->data->dev_private;
1607         struct ecore_dev *edev = &qdev->edev;
1608         struct ecore_eth_stats stats;
1609         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1610         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1611         struct qede_tx_queue *txq;
1612
1613         ecore_get_vport_stats(edev, &stats);
1614
1615         /* RX Stats */
1616         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1617             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1618
1619         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1620             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1621
1622         eth_stats->ierrors = stats.common.rx_crc_errors +
1623             stats.common.rx_align_errors +
1624             stats.common.rx_carrier_errors +
1625             stats.common.rx_oversize_packets +
1626             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1627
1628         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1629
1630         eth_stats->imissed = stats.common.mftag_filter_discards +
1631             stats.common.mac_filter_discards +
1632             stats.common.no_buff_discards +
1633             stats.common.brb_truncates + stats.common.brb_discards;
1634
1635         /* TX stats */
1636         eth_stats->opackets = stats.common.tx_ucast_pkts +
1637             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1638
1639         eth_stats->obytes = stats.common.tx_ucast_bytes +
1640             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1641
1642         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1643
1644         /* Queue stats */
1645         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1646                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1647         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1648                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1649         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1650             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1651                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1652                        "Not all the queue stats will be displayed. Set"
1653                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1654                        " appropriately and retry.\n");
1655
1656         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1657                 eth_stats->q_ipackets[i] = 0;
1658                 eth_stats->q_errors[i] = 0;
1659
1660                 for_each_hwfn(edev, hw_fn) {
1661                         idx = qid * edev->num_hwfns + hw_fn;
1662
1663                         eth_stats->q_ipackets[i] +=
1664                                 *(uint64_t *)
1665                                         (((char *)(qdev->fp_array[idx].rxq)) +
1666                                          offsetof(struct qede_rx_queue,
1667                                          rcv_pkts));
1668                         eth_stats->q_errors[i] +=
1669                                 *(uint64_t *)
1670                                         (((char *)(qdev->fp_array[idx].rxq)) +
1671                                          offsetof(struct qede_rx_queue,
1672                                          rx_hw_errors)) +
1673                                 *(uint64_t *)
1674                                         (((char *)(qdev->fp_array[idx].rxq)) +
1675                                          offsetof(struct qede_rx_queue,
1676                                          rx_alloc_errors));
1677                 }
1678
1679                 i++;
1680                 if (i == rxq_stat_cntrs)
1681                         break;
1682         }
1683
1684         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1685                 eth_stats->q_opackets[j] = 0;
1686
1687                 for_each_hwfn(edev, hw_fn) {
1688                         idx = qid * edev->num_hwfns + hw_fn;
1689
1690                         txq = qdev->fp_array[idx].txq;
1691                         eth_stats->q_opackets[j] +=
1692                                 *((uint64_t *)(uintptr_t)
1693                                         (((uint64_t)(uintptr_t)(txq)) +
1694                                          offsetof(struct qede_tx_queue,
1695                                                   xmit_pkts)));
1696                 }
1697
1698                 j++;
1699                 if (j == txq_stat_cntrs)
1700                         break;
1701         }
1702
1703         return 0;
1704 }
1705
1706 static unsigned
1707 qede_get_xstats_count(struct qede_dev *qdev) {
1708         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1709
1710         if (ECORE_IS_BB(&qdev->edev))
1711                 return RTE_DIM(qede_xstats_strings) +
1712                        RTE_DIM(qede_bb_xstats_strings) +
1713                        (RTE_DIM(qede_rxq_xstats_strings) *
1714                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1715         else
1716                 return RTE_DIM(qede_xstats_strings) +
1717                        RTE_DIM(qede_ah_xstats_strings) +
1718                        (RTE_DIM(qede_rxq_xstats_strings) *
1719                         QEDE_RSS_COUNT(dev));
1720 }
1721
1722 static int
1723 qede_get_xstats_names(struct rte_eth_dev *dev,
1724                       struct rte_eth_xstat_name *xstats_names,
1725                       __rte_unused unsigned int limit)
1726 {
1727         struct qede_dev *qdev = dev->data->dev_private;
1728         struct ecore_dev *edev = &qdev->edev;
1729         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1730         unsigned int i, qid, hw_fn, stat_idx = 0;
1731
1732         if (xstats_names == NULL)
1733                 return stat_cnt;
1734
1735         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1736                 strlcpy(xstats_names[stat_idx].name,
1737                         qede_xstats_strings[i].name,
1738                         sizeof(xstats_names[stat_idx].name));
1739                 stat_idx++;
1740         }
1741
1742         if (ECORE_IS_BB(edev)) {
1743                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1744                         strlcpy(xstats_names[stat_idx].name,
1745                                 qede_bb_xstats_strings[i].name,
1746                                 sizeof(xstats_names[stat_idx].name));
1747                         stat_idx++;
1748                 }
1749         } else {
1750                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1751                         strlcpy(xstats_names[stat_idx].name,
1752                                 qede_ah_xstats_strings[i].name,
1753                                 sizeof(xstats_names[stat_idx].name));
1754                         stat_idx++;
1755                 }
1756         }
1757
1758         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1759                 for_each_hwfn(edev, hw_fn) {
1760                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1761                                 snprintf(xstats_names[stat_idx].name,
1762                                          RTE_ETH_XSTATS_NAME_SIZE,
1763                                          "%.4s%d.%d%s",
1764                                          qede_rxq_xstats_strings[i].name,
1765                                          hw_fn, qid,
1766                                          qede_rxq_xstats_strings[i].name + 4);
1767                                 stat_idx++;
1768                         }
1769                 }
1770         }
1771
1772         return stat_cnt;
1773 }
1774
1775 static int
1776 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1777                 unsigned int n)
1778 {
1779         struct qede_dev *qdev = dev->data->dev_private;
1780         struct ecore_dev *edev = &qdev->edev;
1781         struct ecore_eth_stats stats;
1782         const unsigned int num = qede_get_xstats_count(qdev);
1783         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1784
1785         if (n < num)
1786                 return num;
1787
1788         ecore_get_vport_stats(edev, &stats);
1789
1790         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1791                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1792                                              qede_xstats_strings[i].offset);
1793                 xstats[stat_idx].id = stat_idx;
1794                 stat_idx++;
1795         }
1796
1797         if (ECORE_IS_BB(edev)) {
1798                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1799                         xstats[stat_idx].value =
1800                                         *(uint64_t *)(((char *)&stats) +
1801                                         qede_bb_xstats_strings[i].offset);
1802                         xstats[stat_idx].id = stat_idx;
1803                         stat_idx++;
1804                 }
1805         } else {
1806                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1807                         xstats[stat_idx].value =
1808                                         *(uint64_t *)(((char *)&stats) +
1809                                         qede_ah_xstats_strings[i].offset);
1810                         xstats[stat_idx].id = stat_idx;
1811                         stat_idx++;
1812                 }
1813         }
1814
1815         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1816                 for_each_hwfn(edev, hw_fn) {
1817                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1818                                 fpidx = qid * edev->num_hwfns + hw_fn;
1819                                 xstats[stat_idx].value = *(uint64_t *)
1820                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1821                                          qede_rxq_xstats_strings[i].offset);
1822                                 xstats[stat_idx].id = stat_idx;
1823                                 stat_idx++;
1824                         }
1825
1826                 }
1827         }
1828
1829         return stat_idx;
1830 }
1831
1832 static int
1833 qede_reset_xstats(struct rte_eth_dev *dev)
1834 {
1835         struct qede_dev *qdev = dev->data->dev_private;
1836         struct ecore_dev *edev = &qdev->edev;
1837
1838         ecore_reset_vport_stats(edev);
1839         qede_reset_queue_stats(qdev, true);
1840
1841         return 0;
1842 }
1843
1844 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1845 {
1846         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1847         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1848         struct qed_link_params link_params;
1849         int rc;
1850
1851         DP_INFO(edev, "setting link state %d\n", link_up);
1852         memset(&link_params, 0, sizeof(link_params));
1853         link_params.link_up = link_up;
1854         rc = qdev->ops->common->set_link(edev, &link_params);
1855         if (rc != ECORE_SUCCESS)
1856                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1857
1858         return rc;
1859 }
1860
1861 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1862 {
1863         return qede_dev_set_link_state(eth_dev, true);
1864 }
1865
1866 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1867 {
1868         return qede_dev_set_link_state(eth_dev, false);
1869 }
1870
1871 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1872 {
1873         struct qede_dev *qdev = eth_dev->data->dev_private;
1874         struct ecore_dev *edev = &qdev->edev;
1875
1876         ecore_reset_vport_stats(edev);
1877         qede_reset_queue_stats(qdev, false);
1878
1879         return 0;
1880 }
1881
1882 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1883 {
1884         enum qed_filter_rx_mode_type type =
1885             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1886         enum _ecore_status_t ecore_status;
1887
1888         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1889                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1890
1891         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1892
1893         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1894 }
1895
1896 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1897 {
1898         enum _ecore_status_t ecore_status;
1899
1900         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1901                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1902                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1903         else
1904                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1905                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1906
1907         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1908 }
1909
1910 static int
1911 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1912                 struct rte_ether_addr *mc_addrs,
1913                 uint32_t mc_addrs_num)
1914 {
1915         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1916         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1917         uint8_t i;
1918
1919         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1920                 DP_ERR(edev, "Reached max multicast filters limit,"
1921                              "Please enable multicast promisc mode\n");
1922                 return -ENOSPC;
1923         }
1924
1925         for (i = 0; i < mc_addrs_num; i++) {
1926                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1927                         DP_ERR(edev, "Not a valid multicast MAC\n");
1928                         return -EINVAL;
1929                 }
1930         }
1931
1932         /* Flush all existing entries */
1933         if (qede_del_mcast_filters(eth_dev))
1934                 return -1;
1935
1936         /* Set new mcast list */
1937         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1938 }
1939
1940 /* Update MTU via vport-update without doing port restart.
1941  * The vport must be deactivated before calling this API.
1942  */
1943 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1944 {
1945         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1946         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1947         struct ecore_hwfn *p_hwfn;
1948         int rc;
1949         int i;
1950
1951         if (IS_PF(edev)) {
1952                 struct ecore_sp_vport_update_params params;
1953
1954                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1955                 params.vport_id = 0;
1956                 params.mtu = mtu;
1957                 params.vport_id = 0;
1958                 for_each_hwfn(edev, i) {
1959                         p_hwfn = &edev->hwfns[i];
1960                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1961                         rc = ecore_sp_vport_update(p_hwfn, &params,
1962                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1963                         if (rc != ECORE_SUCCESS)
1964                                 goto err;
1965                 }
1966         } else {
1967                 for_each_hwfn(edev, i) {
1968                         p_hwfn = &edev->hwfns[i];
1969                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1970                         if (rc == ECORE_INVAL) {
1971                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1972                                 /* Recreate vport */
1973                                 rc = qede_start_vport(qdev, mtu);
1974                                 if (rc != ECORE_SUCCESS)
1975                                         goto err;
1976
1977                                 /* Restore config lost due to vport stop */
1978                                 if (eth_dev->data->promiscuous)
1979                                         qede_promiscuous_enable(eth_dev);
1980                                 else
1981                                         qede_promiscuous_disable(eth_dev);
1982
1983                                 if (eth_dev->data->all_multicast)
1984                                         qede_allmulticast_enable(eth_dev);
1985                                 else
1986                                         qede_allmulticast_disable(eth_dev);
1987
1988                                 qede_vlan_offload_set(eth_dev,
1989                                                       qdev->vlan_offload_mask);
1990                         } else if (rc != ECORE_SUCCESS) {
1991                                 goto err;
1992                         }
1993                 }
1994         }
1995         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1996
1997         return 0;
1998
1999 err:
2000         DP_ERR(edev, "Failed to update MTU\n");
2001         return -1;
2002 }
2003
2004 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2005                               struct rte_eth_fc_conf *fc_conf)
2006 {
2007         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2008         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2009         struct qed_link_output current_link;
2010         struct qed_link_params params;
2011
2012         memset(&current_link, 0, sizeof(current_link));
2013         qdev->ops->common->get_link(edev, &current_link);
2014
2015         memset(&params, 0, sizeof(params));
2016         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2017         if (fc_conf->autoneg) {
2018                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2019                         DP_ERR(edev, "Autoneg not supported\n");
2020                         return -EINVAL;
2021                 }
2022                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2023         }
2024
2025         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2026         if (fc_conf->mode == RTE_FC_FULL)
2027                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2028                                         QED_LINK_PAUSE_RX_ENABLE);
2029         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2030                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2031         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2032                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2033
2034         params.link_up = true;
2035         (void)qdev->ops->common->set_link(edev, &params);
2036
2037         return 0;
2038 }
2039
2040 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2041                               struct rte_eth_fc_conf *fc_conf)
2042 {
2043         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2044         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2045         struct qed_link_output current_link;
2046
2047         memset(&current_link, 0, sizeof(current_link));
2048         qdev->ops->common->get_link(edev, &current_link);
2049
2050         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2051                 fc_conf->autoneg = true;
2052
2053         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2054                                          QED_LINK_PAUSE_TX_ENABLE))
2055                 fc_conf->mode = RTE_FC_FULL;
2056         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2057                 fc_conf->mode = RTE_FC_RX_PAUSE;
2058         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2059                 fc_conf->mode = RTE_FC_TX_PAUSE;
2060         else
2061                 fc_conf->mode = RTE_FC_NONE;
2062
2063         return 0;
2064 }
2065
2066 static const uint32_t *
2067 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2068 {
2069         static const uint32_t ptypes[] = {
2070                 RTE_PTYPE_L2_ETHER,
2071                 RTE_PTYPE_L2_ETHER_VLAN,
2072                 RTE_PTYPE_L3_IPV4,
2073                 RTE_PTYPE_L3_IPV6,
2074                 RTE_PTYPE_L4_TCP,
2075                 RTE_PTYPE_L4_UDP,
2076                 RTE_PTYPE_TUNNEL_VXLAN,
2077                 RTE_PTYPE_L4_FRAG,
2078                 RTE_PTYPE_TUNNEL_GENEVE,
2079                 RTE_PTYPE_TUNNEL_GRE,
2080                 /* Inner */
2081                 RTE_PTYPE_INNER_L2_ETHER,
2082                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2083                 RTE_PTYPE_INNER_L3_IPV4,
2084                 RTE_PTYPE_INNER_L3_IPV6,
2085                 RTE_PTYPE_INNER_L4_TCP,
2086                 RTE_PTYPE_INNER_L4_UDP,
2087                 RTE_PTYPE_INNER_L4_FRAG,
2088                 RTE_PTYPE_UNKNOWN
2089         };
2090
2091         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
2092             eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||
2093             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
2094                 return ptypes;
2095
2096         return NULL;
2097 }
2098
2099 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2100 {
2101         *rss_caps = 0;
2102         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2103         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2104         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2105         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2106         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2107         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2108         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2109         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2110 }
2111
2112 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2113                          struct rte_eth_rss_conf *rss_conf)
2114 {
2115         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2116         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2117         struct ecore_sp_vport_update_params vport_update_params;
2118         struct ecore_rss_params rss_params;
2119         struct ecore_hwfn *p_hwfn;
2120         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2121         uint64_t hf = rss_conf->rss_hf;
2122         uint8_t len = rss_conf->rss_key_len;
2123         uint8_t idx, i, j, fpidx;
2124         int rc;
2125
2126         memset(&vport_update_params, 0, sizeof(vport_update_params));
2127         memset(&rss_params, 0, sizeof(rss_params));
2128
2129         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2130                 (unsigned long)hf, len, key);
2131
2132         if (hf != 0) {
2133                 /* Enabling RSS */
2134                 DP_INFO(edev, "Enabling rss\n");
2135
2136                 /* RSS caps */
2137                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2138                 rss_params.update_rss_capabilities = 1;
2139
2140                 /* RSS hash key */
2141                 if (key) {
2142                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2143                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2144                                 return -EINVAL;
2145                         }
2146                         DP_INFO(edev, "Applying user supplied hash key\n");
2147                         rss_params.update_rss_key = 1;
2148                         memcpy(&rss_params.rss_key, key, len);
2149                 }
2150                 rss_params.rss_enable = 1;
2151         }
2152
2153         rss_params.update_rss_config = 1;
2154         /* tbl_size has to be set with capabilities */
2155         rss_params.rss_table_size_log = 7;
2156         vport_update_params.vport_id = 0;
2157
2158         for_each_hwfn(edev, i) {
2159                 /* pass the L2 handles instead of qids */
2160                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2161                         idx = j % QEDE_RSS_COUNT(eth_dev);
2162                         fpidx = idx * edev->num_hwfns + i;
2163                         rss_params.rss_ind_table[j] =
2164                                 qdev->fp_array[fpidx].rxq->handle;
2165                 }
2166
2167                 vport_update_params.rss_params = &rss_params;
2168
2169                 p_hwfn = &edev->hwfns[i];
2170                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2171                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2172                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2173                 if (rc) {
2174                         DP_ERR(edev, "vport-update for RSS failed\n");
2175                         return rc;
2176                 }
2177         }
2178         qdev->rss_enable = rss_params.rss_enable;
2179
2180         /* Update local structure for hash query */
2181         qdev->rss_conf.rss_hf = hf;
2182         qdev->rss_conf.rss_key_len = len;
2183         if (qdev->rss_enable) {
2184                 if  (qdev->rss_conf.rss_key == NULL) {
2185                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2186                         if (qdev->rss_conf.rss_key == NULL) {
2187                                 DP_ERR(edev, "No memory to store RSS key\n");
2188                                 return -ENOMEM;
2189                         }
2190                 }
2191                 if (key && len) {
2192                         DP_INFO(edev, "Storing RSS key\n");
2193                         memcpy(qdev->rss_conf.rss_key, key, len);
2194                 }
2195         } else if (!qdev->rss_enable && len == 0) {
2196                 if (qdev->rss_conf.rss_key) {
2197                         free(qdev->rss_conf.rss_key);
2198                         qdev->rss_conf.rss_key = NULL;
2199                         DP_INFO(edev, "Free RSS key\n");
2200                 }
2201         }
2202
2203         return 0;
2204 }
2205
2206 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2207                            struct rte_eth_rss_conf *rss_conf)
2208 {
2209         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2210
2211         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2212         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2213
2214         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2215                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2216                        rss_conf->rss_key_len);
2217         return 0;
2218 }
2219
2220 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2221                          struct rte_eth_rss_reta_entry64 *reta_conf,
2222                          uint16_t reta_size)
2223 {
2224         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2225         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2226         struct ecore_sp_vport_update_params vport_update_params;
2227         struct ecore_rss_params *params;
2228         uint16_t i, j, idx, fid, shift;
2229         struct ecore_hwfn *p_hwfn;
2230         uint8_t entry;
2231         int rc = 0;
2232
2233         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2234                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2235                        reta_size);
2236                 return -EINVAL;
2237         }
2238
2239         memset(&vport_update_params, 0, sizeof(vport_update_params));
2240         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2241         if (params == NULL) {
2242                 DP_ERR(edev, "failed to allocate memory\n");
2243                 return -ENOMEM;
2244         }
2245
2246         params->update_rss_ind_table = 1;
2247         params->rss_table_size_log = 7;
2248         params->update_rss_config = 1;
2249
2250         vport_update_params.vport_id = 0;
2251         /* Use the current value of rss_enable */
2252         params->rss_enable = qdev->rss_enable;
2253         vport_update_params.rss_params = params;
2254
2255         for_each_hwfn(edev, i) {
2256                 for (j = 0; j < reta_size; j++) {
2257                         idx = j / RTE_RETA_GROUP_SIZE;
2258                         shift = j % RTE_RETA_GROUP_SIZE;
2259                         if (reta_conf[idx].mask & (1ULL << shift)) {
2260                                 entry = reta_conf[idx].reta[shift];
2261                                 fid = entry * edev->num_hwfns + i;
2262                                 /* Pass rxq handles to ecore */
2263                                 params->rss_ind_table[j] =
2264                                                 qdev->fp_array[fid].rxq->handle;
2265                                 /* Update the local copy for RETA query cmd */
2266                                 qdev->rss_ind_table[j] = entry;
2267                         }
2268                 }
2269
2270                 p_hwfn = &edev->hwfns[i];
2271                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2272                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2273                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2274                 if (rc) {
2275                         DP_ERR(edev, "vport-update for RSS failed\n");
2276                         goto out;
2277                 }
2278         }
2279
2280 out:
2281         rte_free(params);
2282         return rc;
2283 }
2284
2285 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2286                                struct rte_eth_rss_reta_entry64 *reta_conf,
2287                                uint16_t reta_size)
2288 {
2289         struct qede_dev *qdev = eth_dev->data->dev_private;
2290         struct ecore_dev *edev = &qdev->edev;
2291         uint16_t i, idx, shift;
2292         uint8_t entry;
2293
2294         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2295                 DP_ERR(edev, "reta_size %d is not supported\n",
2296                        reta_size);
2297                 return -EINVAL;
2298         }
2299
2300         for (i = 0; i < reta_size; i++) {
2301                 idx = i / RTE_RETA_GROUP_SIZE;
2302                 shift = i % RTE_RETA_GROUP_SIZE;
2303                 if (reta_conf[idx].mask & (1ULL << shift)) {
2304                         entry = qdev->rss_ind_table[i];
2305                         reta_conf[idx].reta[shift] = entry;
2306                 }
2307         }
2308
2309         return 0;
2310 }
2311
2312
2313
2314 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2315 {
2316         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2317         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2318         struct rte_eth_dev_info dev_info = {0};
2319         struct qede_fastpath *fp;
2320         uint32_t max_rx_pkt_len;
2321         uint32_t frame_size;
2322         uint16_t bufsz;
2323         bool restart = false;
2324         int i, rc;
2325
2326         PMD_INIT_FUNC_TRACE(edev);
2327         rc = qede_dev_info_get(dev, &dev_info);
2328         if (rc != 0) {
2329                 DP_ERR(edev, "Error during getting ethernet device info\n");
2330                 return rc;
2331         }
2332         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2333         frame_size = max_rx_pkt_len;
2334         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2335                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2336                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2337                        QEDE_ETH_OVERHEAD);
2338                 return -EINVAL;
2339         }
2340         if (!dev->data->scattered_rx &&
2341             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2342                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2343                         dev->data->min_rx_buf_size);
2344                 return -EINVAL;
2345         }
2346         if (dev->data->dev_started) {
2347                 dev->data->dev_started = 0;
2348                 qede_dev_stop(dev);
2349                 restart = true;
2350         }
2351         rte_delay_ms(1000);
2352         qdev->new_mtu = mtu;
2353
2354         /* Fix up RX buf size for all queues of the port */
2355         for (i = 0; i < qdev->num_rx_queues; i++) {
2356                 fp = &qdev->fp_array[i];
2357                 if (fp->rxq != NULL) {
2358                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2359                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2360                         /* cache align the mbuf size to simplfy rx_buf_size
2361                          * calculation
2362                          */
2363                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2364                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2365                         if (rc < 0)
2366                                 return rc;
2367
2368                         fp->rxq->rx_buf_size = rc;
2369                 }
2370         }
2371         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2372                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2373         else
2374                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2375
2376         if (!dev->data->dev_started && restart) {
2377                 qede_dev_start(dev);
2378                 dev->data->dev_started = 1;
2379         }
2380
2381         /* update max frame size */
2382         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2383
2384         return 0;
2385 }
2386
2387 static int
2388 qede_dev_reset(struct rte_eth_dev *dev)
2389 {
2390         int ret;
2391
2392         ret = qede_eth_dev_uninit(dev);
2393         if (ret)
2394                 return ret;
2395
2396         return qede_eth_dev_init(dev);
2397 }
2398
2399 static const struct eth_dev_ops qede_eth_dev_ops = {
2400         .dev_configure = qede_dev_configure,
2401         .dev_infos_get = qede_dev_info_get,
2402         .rx_queue_setup = qede_rx_queue_setup,
2403         .rx_queue_release = qede_rx_queue_release,
2404         .rx_descriptor_status = qede_rx_descriptor_status,
2405         .tx_queue_setup = qede_tx_queue_setup,
2406         .tx_queue_release = qede_tx_queue_release,
2407         .dev_start = qede_dev_start,
2408         .dev_reset = qede_dev_reset,
2409         .dev_set_link_up = qede_dev_set_link_up,
2410         .dev_set_link_down = qede_dev_set_link_down,
2411         .link_update = qede_link_update,
2412         .promiscuous_enable = qede_promiscuous_enable,
2413         .promiscuous_disable = qede_promiscuous_disable,
2414         .allmulticast_enable = qede_allmulticast_enable,
2415         .allmulticast_disable = qede_allmulticast_disable,
2416         .set_mc_addr_list = qede_set_mc_addr_list,
2417         .dev_stop = qede_dev_stop,
2418         .dev_close = qede_dev_close,
2419         .stats_get = qede_get_stats,
2420         .stats_reset = qede_reset_stats,
2421         .xstats_get = qede_get_xstats,
2422         .xstats_reset = qede_reset_xstats,
2423         .xstats_get_names = qede_get_xstats_names,
2424         .mac_addr_add = qede_mac_addr_add,
2425         .mac_addr_remove = qede_mac_addr_remove,
2426         .mac_addr_set = qede_mac_addr_set,
2427         .vlan_offload_set = qede_vlan_offload_set,
2428         .vlan_filter_set = qede_vlan_filter_set,
2429         .flow_ctrl_set = qede_flow_ctrl_set,
2430         .flow_ctrl_get = qede_flow_ctrl_get,
2431         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2432         .rss_hash_update = qede_rss_hash_update,
2433         .rss_hash_conf_get = qede_rss_hash_conf_get,
2434         .reta_update  = qede_rss_reta_update,
2435         .reta_query  = qede_rss_reta_query,
2436         .mtu_set = qede_set_mtu,
2437         .filter_ctrl = qede_dev_filter_ctrl,
2438         .udp_tunnel_port_add = qede_udp_dst_port_add,
2439         .udp_tunnel_port_del = qede_udp_dst_port_del,
2440         .fw_version_get = qede_fw_version_get,
2441 };
2442
2443 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2444         .dev_configure = qede_dev_configure,
2445         .dev_infos_get = qede_dev_info_get,
2446         .rx_queue_setup = qede_rx_queue_setup,
2447         .rx_queue_release = qede_rx_queue_release,
2448         .rx_descriptor_status = qede_rx_descriptor_status,
2449         .tx_queue_setup = qede_tx_queue_setup,
2450         .tx_queue_release = qede_tx_queue_release,
2451         .dev_start = qede_dev_start,
2452         .dev_reset = qede_dev_reset,
2453         .dev_set_link_up = qede_dev_set_link_up,
2454         .dev_set_link_down = qede_dev_set_link_down,
2455         .link_update = qede_link_update,
2456         .promiscuous_enable = qede_promiscuous_enable,
2457         .promiscuous_disable = qede_promiscuous_disable,
2458         .allmulticast_enable = qede_allmulticast_enable,
2459         .allmulticast_disable = qede_allmulticast_disable,
2460         .set_mc_addr_list = qede_set_mc_addr_list,
2461         .dev_stop = qede_dev_stop,
2462         .dev_close = qede_dev_close,
2463         .stats_get = qede_get_stats,
2464         .stats_reset = qede_reset_stats,
2465         .xstats_get = qede_get_xstats,
2466         .xstats_reset = qede_reset_xstats,
2467         .xstats_get_names = qede_get_xstats_names,
2468         .vlan_offload_set = qede_vlan_offload_set,
2469         .vlan_filter_set = qede_vlan_filter_set,
2470         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2471         .rss_hash_update = qede_rss_hash_update,
2472         .rss_hash_conf_get = qede_rss_hash_conf_get,
2473         .reta_update  = qede_rss_reta_update,
2474         .reta_query  = qede_rss_reta_query,
2475         .mtu_set = qede_set_mtu,
2476         .udp_tunnel_port_add = qede_udp_dst_port_add,
2477         .udp_tunnel_port_del = qede_udp_dst_port_del,
2478         .mac_addr_add = qede_mac_addr_add,
2479         .mac_addr_remove = qede_mac_addr_remove,
2480         .mac_addr_set = qede_mac_addr_set,
2481         .fw_version_get = qede_fw_version_get,
2482 };
2483
2484 static void qede_update_pf_params(struct ecore_dev *edev)
2485 {
2486         struct ecore_pf_params pf_params;
2487
2488         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2489         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2490         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2491         qed_ops->common->update_pf_params(edev, &pf_params);
2492 }
2493
2494 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2495 {
2496         struct rte_pci_device *pci_dev;
2497         struct rte_pci_addr pci_addr;
2498         struct qede_dev *adapter;
2499         struct ecore_dev *edev;
2500         struct qed_dev_eth_info dev_info;
2501         struct qed_slowpath_params params;
2502         static bool do_once = true;
2503         uint8_t bulletin_change;
2504         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2505         uint8_t is_mac_forced;
2506         bool is_mac_exist;
2507         /* Fix up ecore debug level */
2508         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2509         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2510         uint32_t int_mode;
2511         int rc;
2512
2513         /* Extract key data structures */
2514         adapter = eth_dev->data->dev_private;
2515         adapter->ethdev = eth_dev;
2516         edev = &adapter->edev;
2517         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2518         pci_addr = pci_dev->addr;
2519
2520         PMD_INIT_FUNC_TRACE(edev);
2521
2522         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2523                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2524                  eth_dev->data->port_id);
2525
2526         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2527                 DP_ERR(edev, "Skipping device init from secondary process\n");
2528                 return 0;
2529         }
2530
2531         rte_eth_copy_pci_info(eth_dev, pci_dev);
2532
2533         /* @DPDK */
2534         edev->vendor_id = pci_dev->id.vendor_id;
2535         edev->device_id = pci_dev->id.device_id;
2536
2537         qed_ops = qed_get_eth_ops();
2538         if (!qed_ops) {
2539                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2540                 rc = -EINVAL;
2541                 goto err;
2542         }
2543
2544         DP_INFO(edev, "Starting qede probe\n");
2545         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2546                                     dp_level, is_vf);
2547         if (rc != 0) {
2548                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2549                 rc = -ENODEV;
2550                 goto err;
2551         }
2552         qede_update_pf_params(edev);
2553
2554         switch (pci_dev->intr_handle.type) {
2555         case RTE_INTR_HANDLE_UIO_INTX:
2556         case RTE_INTR_HANDLE_VFIO_LEGACY:
2557                 int_mode = ECORE_INT_MODE_INTA;
2558                 rte_intr_callback_register(&pci_dev->intr_handle,
2559                                            qede_interrupt_handler_intx,
2560                                            (void *)eth_dev);
2561                 break;
2562         default:
2563                 int_mode = ECORE_INT_MODE_MSIX;
2564                 rte_intr_callback_register(&pci_dev->intr_handle,
2565                                            qede_interrupt_handler,
2566                                            (void *)eth_dev);
2567         }
2568
2569         if (rte_intr_enable(&pci_dev->intr_handle)) {
2570                 DP_ERR(edev, "rte_intr_enable() failed\n");
2571                 rc = -ENODEV;
2572                 goto err;
2573         }
2574
2575         /* Start the Slowpath-process */
2576         memset(&params, 0, sizeof(struct qed_slowpath_params));
2577
2578         params.int_mode = int_mode;
2579         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2580         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2581         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2582         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2583         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2584                 QEDE_PMD_DRV_VER_STR_SIZE);
2585
2586         qede_assign_rxtx_handlers(eth_dev, true);
2587         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2588
2589         /* For CMT mode device do periodic polling for slowpath events.
2590          * This is required since uio device uses only one MSI-x
2591          * interrupt vector but we need one for each engine.
2592          */
2593         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2594                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2595                                        qede_poll_sp_sb_cb,
2596                                        (void *)eth_dev);
2597                 if (rc != 0) {
2598                         DP_ERR(edev, "Unable to start periodic"
2599                                      " timer rc %d\n", rc);
2600                         rc = -EINVAL;
2601                         goto err;
2602                 }
2603         }
2604
2605         rc = qed_ops->common->slowpath_start(edev, &params);
2606         if (rc) {
2607                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2608                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2609                                      (void *)eth_dev);
2610                 rc = -ENODEV;
2611                 goto err;
2612         }
2613
2614         rc = qed_ops->fill_dev_info(edev, &dev_info);
2615         if (rc) {
2616                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2617                 qed_ops->common->slowpath_stop(edev);
2618                 qed_ops->common->remove(edev);
2619                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2620                                      (void *)eth_dev);
2621                 rc = -ENODEV;
2622                 goto err;
2623         }
2624
2625         qede_alloc_etherdev(adapter, &dev_info);
2626
2627         if (do_once) {
2628                 qede_print_adapter_info(eth_dev);
2629                 do_once = false;
2630         }
2631
2632         adapter->ops->common->set_name(edev, edev->name);
2633
2634         if (!is_vf)
2635                 adapter->dev_info.num_mac_filters =
2636                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2637                                             ECORE_MAC);
2638         else
2639                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2640                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2641
2642         /* Allocate memory for storing MAC addr */
2643         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2644                                         (RTE_ETHER_ADDR_LEN *
2645                                         adapter->dev_info.num_mac_filters),
2646                                         RTE_CACHE_LINE_SIZE);
2647
2648         if (eth_dev->data->mac_addrs == NULL) {
2649                 DP_ERR(edev, "Failed to allocate MAC address\n");
2650                 qed_ops->common->slowpath_stop(edev);
2651                 qed_ops->common->remove(edev);
2652                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2653                                      (void *)eth_dev);
2654                 return -ENOMEM;
2655         }
2656
2657         if (!is_vf) {
2658                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2659                                 hw_info.hw_mac_addr,
2660                                 &eth_dev->data->mac_addrs[0]);
2661                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2662                                 &adapter->primary_mac);
2663         } else {
2664                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2665                                        &bulletin_change);
2666                 if (bulletin_change) {
2667                         is_mac_exist =
2668                             ecore_vf_bulletin_get_forced_mac(
2669                                                 ECORE_LEADING_HWFN(edev),
2670                                                 vf_mac,
2671                                                 &is_mac_forced);
2672                         if (is_mac_exist) {
2673                                 DP_INFO(edev, "VF macaddr received from PF\n");
2674                                 rte_ether_addr_copy(
2675                                         (struct rte_ether_addr *)&vf_mac,
2676                                         &eth_dev->data->mac_addrs[0]);
2677                                 rte_ether_addr_copy(
2678                                         &eth_dev->data->mac_addrs[0],
2679                                         &adapter->primary_mac);
2680                         } else {
2681                                 DP_ERR(edev, "No VF macaddr assigned\n");
2682                         }
2683                 }
2684         }
2685
2686         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2687
2688         adapter->num_tx_queues = 0;
2689         adapter->num_rx_queues = 0;
2690         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2691         SLIST_INIT(&adapter->vlan_list_head);
2692         SLIST_INIT(&adapter->uc_list_head);
2693         SLIST_INIT(&adapter->mc_list_head);
2694         adapter->mtu = RTE_ETHER_MTU;
2695         adapter->vport_started = false;
2696
2697         /* VF tunnel offloads is enabled by default in PF driver */
2698         adapter->vxlan.num_filters = 0;
2699         adapter->geneve.num_filters = 0;
2700         adapter->ipgre.num_filters = 0;
2701         if (is_vf) {
2702                 adapter->vxlan.enable = true;
2703                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2704                                              ETH_TUNNEL_FILTER_IVLAN;
2705                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2706                 adapter->geneve.enable = true;
2707                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2708                                               ETH_TUNNEL_FILTER_IVLAN;
2709                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2710                 adapter->ipgre.enable = true;
2711                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2712                                              ETH_TUNNEL_FILTER_IVLAN;
2713         } else {
2714                 adapter->vxlan.enable = false;
2715                 adapter->geneve.enable = false;
2716                 adapter->ipgre.enable = false;
2717         }
2718
2719         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2720                 adapter->primary_mac.addr_bytes[0],
2721                 adapter->primary_mac.addr_bytes[1],
2722                 adapter->primary_mac.addr_bytes[2],
2723                 adapter->primary_mac.addr_bytes[3],
2724                 adapter->primary_mac.addr_bytes[4],
2725                 adapter->primary_mac.addr_bytes[5]);
2726
2727         DP_INFO(edev, "Device initialized\n");
2728
2729         return 0;
2730
2731 err:
2732         if (do_once) {
2733                 qede_print_adapter_info(eth_dev);
2734                 do_once = false;
2735         }
2736         return rc;
2737 }
2738
2739 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2740 {
2741         return qede_common_dev_init(eth_dev, 1);
2742 }
2743
2744 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2745 {
2746         return qede_common_dev_init(eth_dev, 0);
2747 }
2748
2749 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2750 {
2751         struct qede_dev *qdev = eth_dev->data->dev_private;
2752         struct ecore_dev *edev = &qdev->edev;
2753
2754         PMD_INIT_FUNC_TRACE(edev);
2755
2756         /* only uninitialize in the primary process */
2757         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2758                 return 0;
2759
2760         /* safe to close dev here */
2761         qede_dev_close(eth_dev);
2762
2763         eth_dev->dev_ops = NULL;
2764         eth_dev->rx_pkt_burst = NULL;
2765         eth_dev->tx_pkt_burst = NULL;
2766
2767         return 0;
2768 }
2769
2770 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2771 {
2772         return qede_dev_common_uninit(eth_dev);
2773 }
2774
2775 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2776 {
2777         return qede_dev_common_uninit(eth_dev);
2778 }
2779
2780 static const struct rte_pci_id pci_id_qedevf_map[] = {
2781 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2782         {
2783                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2784         },
2785         {
2786                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2787         },
2788         {
2789                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2790         },
2791         {.vendor_id = 0,}
2792 };
2793
2794 static const struct rte_pci_id pci_id_qede_map[] = {
2795 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2796         {
2797                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2798         },
2799         {
2800                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2801         },
2802         {
2803                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2804         },
2805         {
2806                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2807         },
2808         {
2809                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2810         },
2811         {
2812                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2813         },
2814         {
2815                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2816         },
2817         {
2818                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2819         },
2820         {
2821                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2822         },
2823         {
2824                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2825         },
2826         {.vendor_id = 0,}
2827 };
2828
2829 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2830         struct rte_pci_device *pci_dev)
2831 {
2832         return rte_eth_dev_pci_generic_probe(pci_dev,
2833                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2834 }
2835
2836 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2837 {
2838         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2839 }
2840
2841 static struct rte_pci_driver rte_qedevf_pmd = {
2842         .id_table = pci_id_qedevf_map,
2843         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2844         .probe = qedevf_eth_dev_pci_probe,
2845         .remove = qedevf_eth_dev_pci_remove,
2846 };
2847
2848 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2849         struct rte_pci_device *pci_dev)
2850 {
2851         return rte_eth_dev_pci_generic_probe(pci_dev,
2852                 sizeof(struct qede_dev), qede_eth_dev_init);
2853 }
2854
2855 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2856 {
2857         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2858 }
2859
2860 static struct rte_pci_driver rte_qede_pmd = {
2861         .id_table = pci_id_qede_map,
2862         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2863         .probe = qede_eth_dev_pci_probe,
2864         .remove = qede_eth_dev_pci_remove,
2865 };
2866
2867 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2868 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2869 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2870 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2871 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2872 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2873
2874 RTE_INIT(qede_init_log)
2875 {
2876         qede_logtype_init = rte_log_register("pmd.net.qede.init");
2877         if (qede_logtype_init >= 0)
2878                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2879         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2880         if (qede_logtype_driver >= 0)
2881                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
2882 }