drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12 #include <rte_kvargs.h>
  13
  14 /* Globals */
  15 int qede_logtype_init;
  16 int qede_logtype_driver;
  17
  18 static const struct qed_eth_ops *qed_ops;
  19 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  20
  21 /* VXLAN tunnel classification mapping */
  22 const struct _qede_udp_tunn_types {
  23         uint16_t rte_filter_type;
  24         enum ecore_filter_ucast_type qede_type;
  25         enum ecore_tunn_clss qede_tunn_clss;
  26         const char *string;
  27 } qede_tunn_types[] = {
  28         {
  29                 ETH_TUNNEL_FILTER_OMAC,
  30                 ECORE_FILTER_MAC,
  31                 ECORE_TUNN_CLSS_MAC_VLAN,
  32                 "outer-mac"
  33         },
  34         {
  35                 ETH_TUNNEL_FILTER_TENID,
  36                 ECORE_FILTER_VNI,
  37                 ECORE_TUNN_CLSS_MAC_VNI,
  38                 "vni"
  39         },
  40         {
  41                 ETH_TUNNEL_FILTER_IMAC,
  42                 ECORE_FILTER_INNER_MAC,
  43                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  44                 "inner-mac"
  45         },
  46         {
  47                 ETH_TUNNEL_FILTER_IVLAN,
  48                 ECORE_FILTER_INNER_VLAN,
  49                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  50                 "inner-vlan"
  51         },
  52         {
  53                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  54                 ECORE_FILTER_MAC_VNI_PAIR,
  55                 ECORE_TUNN_CLSS_MAC_VNI,
  56                 "outer-mac and vni"
  57         },
  58         {
  59                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  60                 ECORE_FILTER_UNUSED,
  61                 MAX_ECORE_TUNN_CLSS,
  62                 "outer-mac and inner-mac"
  63         },
  64         {
  65                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  66                 ECORE_FILTER_UNUSED,
  67                 MAX_ECORE_TUNN_CLSS,
  68                 "outer-mac and inner-vlan"
  69         },
  70         {
  71                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  72                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  73                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  74                 "vni and inner-mac",
  75         },
  76         {
  77                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  78                 ECORE_FILTER_UNUSED,
  79                 MAX_ECORE_TUNN_CLSS,
  80                 "vni and inner-vlan",
  81         },
  82         {
  83                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  84                 ECORE_FILTER_INNER_PAIR,
  85                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  86                 "inner-mac and inner-vlan",
  87         },
  88         {
  89                 ETH_TUNNEL_FILTER_OIP,
  90                 ECORE_FILTER_UNUSED,
  91                 MAX_ECORE_TUNN_CLSS,
  92                 "outer-IP"
  93         },
  94         {
  95                 ETH_TUNNEL_FILTER_IIP,
  96                 ECORE_FILTER_UNUSED,
  97                 MAX_ECORE_TUNN_CLSS,
  98                 "inner-IP"
  99         },
 100         {
 101                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
 102                 ECORE_FILTER_UNUSED,
 103                 MAX_ECORE_TUNN_CLSS,
 104                 "IMAC_IVLAN"
 105         },
 106         {
 107                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 108                 ECORE_FILTER_UNUSED,
 109                 MAX_ECORE_TUNN_CLSS,
 110                 "IMAC_IVLAN_TENID"
 111         },
 112         {
 113                 RTE_TUNNEL_FILTER_IMAC_TENID,
 114                 ECORE_FILTER_UNUSED,
 115                 MAX_ECORE_TUNN_CLSS,
 116                 "IMAC_TENID"
 117         },
 118         {
 119                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 120                 ECORE_FILTER_UNUSED,
 121                 MAX_ECORE_TUNN_CLSS,
 122                 "OMAC_TENID_IMAC"
 123         },
 124 };
 125
 126 struct rte_qede_xstats_name_off {
 127         char name[RTE_ETH_XSTATS_NAME_SIZE];
 128         uint64_t offset;
 129 };
 130
 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 132         {"rx_unicast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 134         {"rx_multicast_bytes",
 135                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 136         {"rx_broadcast_bytes",
 137                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 138         {"rx_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 140         {"rx_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 142         {"rx_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 144
 145         {"tx_unicast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 147         {"tx_multicast_bytes",
 148                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 149         {"tx_broadcast_bytes",
 150                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 151         {"tx_unicast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 153         {"tx_multicast_packets",
 154                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 155         {"tx_broadcast_packets",
 156                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 157
 158         {"rx_64_byte_packets",
 159                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 160         {"rx_65_to_127_byte_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          rx_65_to_127_byte_packets)},
 163         {"rx_128_to_255_byte_packets",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          rx_128_to_255_byte_packets)},
 166         {"rx_256_to_511_byte_packets",
 167                 offsetof(struct ecore_eth_stats_common,
 168                          rx_256_to_511_byte_packets)},
 169         {"rx_512_to_1023_byte_packets",
 170                 offsetof(struct ecore_eth_stats_common,
 171                          rx_512_to_1023_byte_packets)},
 172         {"rx_1024_to_1518_byte_packets",
 173                 offsetof(struct ecore_eth_stats_common,
 174                          rx_1024_to_1518_byte_packets)},
 175         {"tx_64_byte_packets",
 176                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 177         {"tx_65_to_127_byte_packets",
 178                 offsetof(struct ecore_eth_stats_common,
 179                          tx_65_to_127_byte_packets)},
 180         {"tx_128_to_255_byte_packets",
 181                 offsetof(struct ecore_eth_stats_common,
 182                          tx_128_to_255_byte_packets)},
 183         {"tx_256_to_511_byte_packets",
 184                 offsetof(struct ecore_eth_stats_common,
 185                          tx_256_to_511_byte_packets)},
 186         {"tx_512_to_1023_byte_packets",
 187                 offsetof(struct ecore_eth_stats_common,
 188                          tx_512_to_1023_byte_packets)},
 189         {"tx_1024_to_1518_byte_packets",
 190                 offsetof(struct ecore_eth_stats_common,
 191                          tx_1024_to_1518_byte_packets)},
 192
 193         {"rx_mac_crtl_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 195         {"tx_mac_control_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 197         {"rx_pause_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 199         {"tx_pause_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 205
 206         {"rx_crc_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 208         {"rx_align_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 210         {"rx_carrier_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 212         {"rx_oversize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 214         {"rx_jabber_errors",
 215                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 216         {"rx_undersize_packet_errors",
 217                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 218         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 219         {"rx_host_buffer_not_available",
 220                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 221         /* Number of packets discarded because they are bigger than MTU */
 222         {"rx_packet_too_big_discards",
 223                 offsetof(struct ecore_eth_stats_common,
 224                          packet_too_big_discard)},
 225         {"rx_ttl_zero_discards",
 226                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 227         {"rx_multi_function_tag_filter_discards",
 228                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 229         {"rx_mac_filter_discards",
 230                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 231         {"rx_hw_buffer_truncates",
 232                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 233         {"rx_hw_buffer_discards",
 234                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats_common,
 263                          tpa_not_coalesced_pkts)},
 264         {"lro_coalesced_bytes",
 265                 offsetof(struct ecore_eth_stats_common,
 266                          tpa_coalesced_bytes)},
 267 };
 268
 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 270         {"rx_1519_to_1522_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_1522_byte_packets)},
 274         {"rx_1519_to_2047_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_1519_to_2047_byte_packets)},
 278         {"rx_2048_to_4095_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_2048_to_4095_byte_packets)},
 282         {"rx_4096_to_9216_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_4096_to_9216_byte_packets)},
 286         {"rx_9217_to_16383_byte_packets",
 287                 offsetof(struct ecore_eth_stats, bb) +
 288                 offsetof(struct ecore_eth_stats_bb,
 289                          rx_9217_to_16383_byte_packets)},
 290
 291         {"tx_1519_to_2047_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_1519_to_2047_byte_packets)},
 295         {"tx_2048_to_4095_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_2048_to_4095_byte_packets)},
 299         {"tx_4096_to_9216_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_4096_to_9216_byte_packets)},
 303         {"tx_9217_to_16383_byte_packets",
 304                 offsetof(struct ecore_eth_stats, bb) +
 305                 offsetof(struct ecore_eth_stats_bb,
 306                          tx_9217_to_16383_byte_packets)},
 307
 308         {"tx_lpi_entry_count",
 309                 offsetof(struct ecore_eth_stats, bb) +
 310                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 311         {"tx_total_collisions",
 312                 offsetof(struct ecore_eth_stats, bb) +
 313                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 314 };
 315
 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 317         {"rx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          rx_1519_to_max_byte_packets)},
 321         {"tx_1519_to_max_byte_packets",
 322                 offsetof(struct ecore_eth_stats, ah) +
 323                 offsetof(struct ecore_eth_stats_ah,
 324                          tx_1519_to_max_byte_packets)},
 325 };
 326
 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 328         {"rx_q_segments",
 329                 offsetof(struct qede_rx_queue, rx_segs)},
 330         {"rx_q_hw_errors",
 331                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 332         {"rx_q_allocation_errors",
 333                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 334 };
 335
 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 337 {
 338         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 339 }
 340
 341 static void
 342 qede_interrupt_handler(void *param)
 343 {
 344         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 345         struct qede_dev *qdev = eth_dev->data->dev_private;
 346         struct ecore_dev *edev = &qdev->edev;
 347
 348         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 349         if (rte_intr_enable(eth_dev->intr_handle))
 350                 DP_ERR(edev, "rte_intr_enable failed\n");
 351 }
 352
 353 static void
 354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 355 {
 356         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 357         qdev->ops = qed_ops;
 358 }
 359
 360 static void qede_print_adapter_info(struct qede_dev *qdev)
 361 {
 362         struct ecore_dev *edev = &qdev->edev;
 363         struct qed_dev_info *info = &qdev->dev_info.common;
 364         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 365         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 366
 367         DP_INFO(edev, "*********************************\n");
 368         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 369         DP_INFO(edev, " Chip details : %s %c%d\n",
 370                   ECORE_IS_BB(edev) ? "BB" : "AH",
 371                   'A' + edev->chip_rev,
 372                   (int)edev->chip_metal);
 373         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 374                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 375         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 376                  ver_str, QEDE_PMD_VERSION);
 377         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 378         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 379
 380         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 381                  "%d.%d.%d.%d",
 382                 (info->mfw_rev >> 24) & 0xff,
 383                 (info->mfw_rev >> 16) & 0xff,
 384                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 385         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 386         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 387         DP_INFO(edev, "*********************************\n");
 388 }
 389
 390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 391 {
 392         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 393         unsigned int i = 0, j = 0, qid;
 394         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 395         struct qede_tx_queue *txq;
 396
 397         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 398
 399         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 400                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 401         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 402                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 403
 404         for_each_rss(qid) {
 405                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 406                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 407                             sizeof(uint64_t));
 408                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 409                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 410                             sizeof(uint64_t));
 411                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 412                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 413                             sizeof(uint64_t));
 414
 415                 if (xstats)
 416                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 417                                 OSAL_MEMSET((((char *)
 418                                               (qdev->fp_array[qid].rxq)) +
 419                                              qede_rxq_xstats_strings[j].offset),
 420                                             0,
 421                                             sizeof(uint64_t));
 422
 423                 i++;
 424                 if (i == rxq_stat_cntrs)
 425                         break;
 426         }
 427
 428         i = 0;
 429
 430         for_each_tss(qid) {
 431                 txq = qdev->fp_array[qid].txq;
 432
 433                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 434                                 (((uint64_t)(uintptr_t)(txq)) +
 435                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 436                             sizeof(uint64_t));
 437
 438                 i++;
 439                 if (i == txq_stat_cntrs)
 440                         break;
 441         }
 442 }
 443
 444 static int
 445 qede_stop_vport(struct ecore_dev *edev)
 446 {
 447         struct ecore_hwfn *p_hwfn;
 448         uint8_t vport_id;
 449         int rc;
 450         int i;
 451
 452         vport_id = 0;
 453         for_each_hwfn(edev, i) {
 454                 p_hwfn = &edev->hwfns[i];
 455                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 456                                          vport_id);
 457                 if (rc != ECORE_SUCCESS) {
 458                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 459                         return rc;
 460                 }
 461         }
 462
 463         DP_INFO(edev, "vport stopped\n");
 464
 465         return 0;
 466 }
 467
 468 static int
 469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 470 {
 471         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 472         struct ecore_sp_vport_start_params params;
 473         struct ecore_hwfn *p_hwfn;
 474         int rc;
 475         int i;
 476
 477         if (qdev->vport_started)
 478                 qede_stop_vport(edev);
 479
 480         memset(&params, 0, sizeof(params));
 481         params.vport_id = 0;
 482         params.mtu = mtu;
 483         /* @DPDK - Disable FW placement */
 484         params.zero_placement_offset = 1;
 485         for_each_hwfn(edev, i) {
 486                 p_hwfn = &edev->hwfns[i];
 487                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 488                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 489                 rc = ecore_sp_vport_start(p_hwfn, &params);
 490                 if (rc != ECORE_SUCCESS) {
 491                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 492                         return rc;
 493                 }
 494         }
 495         ecore_reset_vport_stats(edev);
 496         qdev->vport_started = true;
 497         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 498
 499         return 0;
 500 }
 501
 502 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 503 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 504
 505 /* Activate or deactivate vport via vport-update */
 506 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 507 {
 508         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 509         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 510         struct ecore_sp_vport_update_params params;
 511         struct ecore_hwfn *p_hwfn;
 512         uint8_t i;
 513         int rc = -1;
 514
 515         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 516         params.vport_id = 0;
 517         params.update_vport_active_rx_flg = 1;
 518         params.update_vport_active_tx_flg = 1;
 519         params.vport_active_rx_flg = flg;
 520         params.vport_active_tx_flg = flg;
 521         if (!qdev->enable_tx_switching) {
 522                 if ((QEDE_NPAR_TX_SWITCHING != NULL) ||
 523                     ((QEDE_VF_TX_SWITCHING != NULL) && IS_VF(edev))) {
 524                         params.update_tx_switching_flg = 1;
 525                         params.tx_switching_flg = !flg;
 526                         DP_INFO(edev, "%s tx-switching is disabled\n",
 527                                 QEDE_NPAR_TX_SWITCHING ? "NPAR" : "VF");
 528                 }
 529         }
 530         for_each_hwfn(edev, i) {
 531                 p_hwfn = &edev->hwfns[i];
 532                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 533                 rc = ecore_sp_vport_update(p_hwfn, &params,
 534                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 535                 if (rc != ECORE_SUCCESS) {
 536                         DP_ERR(edev, "Failed to update vport\n");
 537                         break;
 538                 }
 539         }
 540         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 541
 542         return rc;
 543 }
 544
 545 static void
 546 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 547                            uint16_t mtu, bool enable)
 548 {
 549         /* Enable LRO in split mode */
 550         sge_tpa_params->tpa_ipv4_en_flg = enable;
 551         sge_tpa_params->tpa_ipv6_en_flg = enable;
 552         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 553         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 554         /* set if tpa enable changes */
 555         sge_tpa_params->update_tpa_en_flg = 1;
 556         /* set if tpa parameters should be handled */
 557         sge_tpa_params->update_tpa_param_flg = enable;
 558
 559         sge_tpa_params->max_buffers_per_cqe = 20;
 560         /* Enable TPA in split mode. In this mode each TPA segment
 561          * starts on the new BD, so there is one BD per segment.
 562          */
 563         sge_tpa_params->tpa_pkt_split_flg = 1;
 564         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 565         sge_tpa_params->tpa_gro_consistent_flg = 0;
 566         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 567         sge_tpa_params->tpa_max_size = 0x7FFF;
 568         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 569         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 570 }
 571
 572 /* Enable/disable LRO via vport-update */
 573 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 574 {
 575         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 576         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 577         struct ecore_sp_vport_update_params params;
 578         struct ecore_sge_tpa_params tpa_params;
 579         struct ecore_hwfn *p_hwfn;
 580         int rc;
 581         int i;
 582
 583         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 584         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 585         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 586         params.vport_id = 0;
 587         params.sge_tpa_params = &tpa_params;
 588         for_each_hwfn(edev, i) {
 589                 p_hwfn = &edev->hwfns[i];
 590                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 591                 rc = ecore_sp_vport_update(p_hwfn, &params,
 592                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 593                 if (rc != ECORE_SUCCESS) {
 594                         DP_ERR(edev, "Failed to update LRO\n");
 595                         return -1;
 596                 }
 597         }
 598         qdev->enable_lro = flg;
 599         eth_dev->data->lro = flg;
 600
 601         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 602
 603         return 0;
 604 }
 605
 606 /* Update MTU via vport-update without doing port restart.
 607  * The vport must be deactivated before calling this API.
 608  */
 609 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 610 {
 611         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 612         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 613         struct ecore_sp_vport_update_params params;
 614         struct ecore_hwfn *p_hwfn;
 615         int rc;
 616         int i;
 617
 618         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 619         params.vport_id = 0;
 620         params.mtu = mtu;
 621         params.vport_id = 0;
 622         for_each_hwfn(edev, i) {
 623                 p_hwfn = &edev->hwfns[i];
 624                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 625                 rc = ecore_sp_vport_update(p_hwfn, &params,
 626                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 627                 if (rc != ECORE_SUCCESS) {
 628                         DP_ERR(edev, "Failed to update MTU\n");
 629                         return -1;
 630                 }
 631         }
 632         DP_INFO(edev, "MTU updated to %u\n", mtu);
 633
 634         return 0;
 635 }
 636
 637 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 638 {
 639         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 640         ucast->is_rx_filter = true;
 641         ucast->is_tx_filter = true;
 642         /* ucast->assert_on_error = true; - For debug */
 643 }
 644
 645 static int
 646 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 647                              enum qed_filter_rx_mode_type type)
 648 {
 649         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 650         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 651         struct ecore_filter_accept_flags flags;
 652
 653         memset(&flags, 0, sizeof(flags));
 654
 655         flags.update_rx_mode_config = 1;
 656         flags.update_tx_mode_config = 1;
 657         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 658                 ECORE_ACCEPT_MCAST_MATCHED |
 659                 ECORE_ACCEPT_BCAST;
 660
 661         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 662                 ECORE_ACCEPT_MCAST_MATCHED |
 663                 ECORE_ACCEPT_BCAST;
 664
 665         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 666                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 667                 if (IS_VF(edev)) {
 668                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 669                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 670                 }
 671         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 672                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 673         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 674                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 675                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 676                         ECORE_ACCEPT_MCAST_UNMATCHED;
 677         }
 678
 679         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 680                         ECORE_SPQ_MODE_CB, NULL);
 681 }
 682
 683 static int
 684 qede_tunnel_update(struct qede_dev *qdev,
 685                    struct ecore_tunnel_info *tunn_info)
 686 {
 687         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 688         enum _ecore_status_t rc = ECORE_INVAL;
 689         struct ecore_hwfn *p_hwfn;
 690         struct ecore_ptt *p_ptt;
 691         int i;
 692
 693         for_each_hwfn(edev, i) {
 694                 p_hwfn = &edev->hwfns[i];
 695                 if (IS_PF(edev)) {
 696                         p_ptt = ecore_ptt_acquire(p_hwfn);
 697                         if (!p_ptt) {
 698                                 DP_ERR(p_hwfn, "Can't acquire PTT\n");
 699                                 return -EAGAIN;
 700                         }
 701                 } else {
 702                         p_ptt = NULL;
 703                 }
 704
 705                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 706                                 tunn_info, ECORE_SPQ_MODE_CB, NULL);
 707                 if (IS_PF(edev))
 708                         ecore_ptt_release(p_hwfn, p_ptt);
 709
 710                 if (rc != ECORE_SUCCESS)
 711                         break;
 712         }
 713
 714         return rc;
 715 }
 716
 717 static int
 718 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 719                   bool enable)
 720 {
 721         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 722         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 723         enum _ecore_status_t rc = ECORE_INVAL;
 724         struct ecore_tunnel_info tunn;
 725
 726         if (qdev->vxlan.enable == enable)
 727                 return ECORE_SUCCESS;
 728
 729         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 730         tunn.vxlan.b_update_mode = true;
 731         tunn.vxlan.b_mode_enabled = enable;
 732         tunn.b_update_rx_cls = true;
 733         tunn.b_update_tx_cls = true;
 734         tunn.vxlan.tun_cls = clss;
 735
 736         tunn.vxlan_port.b_update_port = true;
 737         tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
 738
 739         rc = qede_tunnel_update(qdev, &tunn);
 740         if (rc == ECORE_SUCCESS) {
 741                 qdev->vxlan.enable = enable;
 742                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 743                 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
 744                         enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
 745         } else {
 746                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 747                        tunn.vxlan.tun_cls);
 748         }
 749
 750         return rc;
 751 }
 752
 753 static int
 754 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 755                   bool enable)
 756 {
 757         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 758         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 759         enum _ecore_status_t rc = ECORE_INVAL;
 760         struct ecore_tunnel_info tunn;
 761
 762         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 763         tunn.l2_geneve.b_update_mode = true;
 764         tunn.l2_geneve.b_mode_enabled = enable;
 765         tunn.ip_geneve.b_update_mode = true;
 766         tunn.ip_geneve.b_mode_enabled = enable;
 767         tunn.l2_geneve.tun_cls = clss;
 768         tunn.ip_geneve.tun_cls = clss;
 769         tunn.b_update_rx_cls = true;
 770         tunn.b_update_tx_cls = true;
 771
 772         tunn.geneve_port.b_update_port = true;
 773         tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
 774
 775         rc = qede_tunnel_update(qdev, &tunn);
 776         if (rc == ECORE_SUCCESS) {
 777                 qdev->geneve.enable = enable;
 778                 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
 779                 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
 780                         enable ? "enabled" : "disabled", qdev->geneve.udp_port);
 781         } else {
 782                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 783                        clss);
 784         }
 785
 786         return rc;
 787 }
 788
 789 static int
 790 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 791                   bool enable)
 792 {
 793         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 794         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 795         enum _ecore_status_t rc = ECORE_INVAL;
 796         struct ecore_tunnel_info tunn;
 797
 798         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 799         tunn.ip_gre.b_update_mode = true;
 800         tunn.ip_gre.b_mode_enabled = enable;
 801         tunn.ip_gre.tun_cls = clss;
 802         tunn.ip_gre.tun_cls = clss;
 803         tunn.b_update_rx_cls = true;
 804         tunn.b_update_tx_cls = true;
 805
 806         rc = qede_tunnel_update(qdev, &tunn);
 807         if (rc == ECORE_SUCCESS) {
 808                 qdev->ipgre.enable = enable;
 809                 DP_INFO(edev, "IPGRE is %s\n",
 810                         enable ? "enabled" : "disabled");
 811         } else {
 812                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 813                        clss);
 814         }
 815
 816         return rc;
 817 }
 818
 819 static int
 820 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 821                  enum rte_eth_tunnel_type tunn_type, bool enable)
 822 {
 823         int rc = -EINVAL;
 824
 825         switch (tunn_type) {
 826         case RTE_TUNNEL_TYPE_VXLAN:
 827                 rc = qede_vxlan_enable(eth_dev, clss, enable);
 828                 break;
 829         case RTE_TUNNEL_TYPE_GENEVE:
 830                 rc = qede_geneve_enable(eth_dev, clss, enable);
 831                 break;
 832         case RTE_TUNNEL_TYPE_IP_IN_GRE:
 833                 rc = qede_ipgre_enable(eth_dev, clss, enable);
 834                 break;
 835         default:
 836                 rc = -EINVAL;
 837                 break;
 838         }
 839
 840         return rc;
 841 }
 842
 843 static int
 844 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 845                   bool add)
 846 {
 847         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 848         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 849         struct qede_ucast_entry *tmp = NULL;
 850         struct qede_ucast_entry *u;
 851         struct ether_addr *mac_addr;
 852
 853         mac_addr  = (struct ether_addr *)ucast->mac;
 854         if (add) {
 855                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 856                         if ((memcmp(mac_addr, &tmp->mac,
 857                                     ETHER_ADDR_LEN) == 0) &&
 858                              ucast->vni == tmp->vni &&
 859                              ucast->vlan == tmp->vlan) {
 860                                 DP_INFO(edev, "Unicast MAC is already added"
 861                                         " with vlan = %u, vni = %u\n",
 862                                         ucast->vlan,  ucast->vni);
 863                                         return 0;
 864                         }
 865                 }
 866                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 867                                RTE_CACHE_LINE_SIZE);
 868                 if (!u) {
 869                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 870                         return -ENOMEM;
 871                 }
 872                 ether_addr_copy(mac_addr, &u->mac);
 873                 u->vlan = ucast->vlan;
 874                 u->vni = ucast->vni;
 875                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 876                 qdev->num_uc_addr++;
 877         } else {
 878                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 879                         if ((memcmp(mac_addr, &tmp->mac,
 880                                     ETHER_ADDR_LEN) == 0) &&
 881                             ucast->vlan == tmp->vlan      &&
 882                             ucast->vni == tmp->vni)
 883                         break;
 884                 }
 885                 if (tmp == NULL) {
 886                         DP_INFO(edev, "Unicast MAC is not found\n");
 887                         return -EINVAL;
 888                 }
 889                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 890                 qdev->num_uc_addr--;
 891         }
 892
 893         return 0;
 894 }
 895
 896 static int
 897 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
 898                        uint32_t mc_addrs_num)
 899 {
 900         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 901         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 902         struct ecore_filter_mcast mcast;
 903         struct qede_mcast_entry *m = NULL;
 904         uint8_t i;
 905         int rc;
 906
 907         for (i = 0; i < mc_addrs_num; i++) {
 908                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 909                                RTE_CACHE_LINE_SIZE);
 910                 if (!m) {
 911                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 912                         return -ENOMEM;
 913                 }
 914                 ether_addr_copy(&mc_addrs[i], &m->mac);
 915                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 916         }
 917         memset(&mcast, 0, sizeof(mcast));
 918         mcast.num_mc_addrs = mc_addrs_num;
 919         mcast.opcode = ECORE_FILTER_ADD;
 920         for (i = 0; i < mc_addrs_num; i++)
 921                 ether_addr_copy(&mc_addrs[i], (struct ether_addr *)
 922                                                         &mcast.mac[i]);
 923         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 924         if (rc != ECORE_SUCCESS) {
 925                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 926                 return -1;
 927         }
 928
 929         return 0;
 930 }
 931
 932 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 933 {
 934         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 935         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 936         struct qede_mcast_entry *tmp = NULL;
 937         struct ecore_filter_mcast mcast;
 938         int j;
 939         int rc;
 940
 941         memset(&mcast, 0, sizeof(mcast));
 942         mcast.num_mc_addrs = qdev->num_mc_addr;
 943         mcast.opcode = ECORE_FILTER_REMOVE;
 944         j = 0;
 945         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 946                 ether_addr_copy(&tmp->mac, (struct ether_addr *)&mcast.mac[j]);
 947                 j++;
 948         }
 949         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 950         if (rc != ECORE_SUCCESS) {
 951                 DP_ERR(edev, "Failed to delete multicast filter\n");
 952                 return -1;
 953         }
 954         /* Init the list */
 955         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 956                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 957                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 958         }
 959         SLIST_INIT(&qdev->mc_list_head);
 960
 961         return 0;
 962 }
 963
 964 static enum _ecore_status_t
 965 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 966                  bool add)
 967 {
 968         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 969         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 970         enum _ecore_status_t rc = ECORE_INVAL;
 971
 972         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 973                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 974                               " Please enable promisc mode\n");
 975                         return ECORE_INVAL;
 976         }
 977
 978         rc = qede_ucast_filter(eth_dev, ucast, add);
 979         if (rc == 0)
 980                 rc = ecore_filter_ucast_cmd(edev, ucast,
 981                                             ECORE_SPQ_MODE_CB, NULL);
 982         if (rc != ECORE_SUCCESS)
 983                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 984                        rc, add);
 985
 986         return rc;
 987 }
 988
 989 static int
 990 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 991                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 992 {
 993         struct ecore_filter_ucast ucast;
 994         int re;
 995
 996         qede_set_ucast_cmn_params(&ucast);
 997         ucast.type = ECORE_FILTER_MAC;
 998         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 999         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
1000         return re;
1001 }
1002
1003 static void
1004 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
1005 {
1006         struct qede_dev *qdev = eth_dev->data->dev_private;
1007         struct ecore_dev *edev = &qdev->edev;
1008         struct ecore_filter_ucast ucast;
1009
1010         PMD_INIT_FUNC_TRACE(edev);
1011
1012         if (index >= qdev->dev_info.num_mac_filters) {
1013                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
1014                        index, qdev->dev_info.num_mac_filters);
1015                 return;
1016         }
1017
1018         qede_set_ucast_cmn_params(&ucast);
1019         ucast.opcode = ECORE_FILTER_REMOVE;
1020         ucast.type = ECORE_FILTER_MAC;
1021
1022         /* Use the index maintained by rte */
1023         ether_addr_copy(&eth_dev->data->mac_addrs[index],
1024                         (struct ether_addr *)&ucast.mac);
1025
1026         qede_mac_int_ops(eth_dev, &ucast, false);
1027 }
1028
1029 static int
1030 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1031 {
1032         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1033         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1034
1035         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1036                                                mac_addr->addr_bytes)) {
1037                 DP_ERR(edev, "Setting MAC address is not allowed\n");
1038                 return -EPERM;
1039         }
1040
1041         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1042         return 0;
1043 }
1044
1045 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1046 {
1047         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1048         struct ecore_sp_vport_update_params params;
1049         struct ecore_hwfn *p_hwfn;
1050         uint8_t i;
1051         int rc;
1052
1053         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1054         params.vport_id = 0;
1055         params.update_accept_any_vlan_flg = 1;
1056         params.accept_any_vlan = flg;
1057         for_each_hwfn(edev, i) {
1058                 p_hwfn = &edev->hwfns[i];
1059                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1060                 rc = ecore_sp_vport_update(p_hwfn, &params,
1061                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1062                 if (rc != ECORE_SUCCESS) {
1063                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1064                         return;
1065                 }
1066         }
1067
1068         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1069 }
1070
1071 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1072 {
1073         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1074         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1075         struct ecore_sp_vport_update_params params;
1076         struct ecore_hwfn *p_hwfn;
1077         uint8_t i;
1078         int rc;
1079
1080         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1081         params.vport_id = 0;
1082         params.update_inner_vlan_removal_flg = 1;
1083         params.inner_vlan_removal_flg = flg;
1084         for_each_hwfn(edev, i) {
1085                 p_hwfn = &edev->hwfns[i];
1086                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1087                 rc = ecore_sp_vport_update(p_hwfn, &params,
1088                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1089                 if (rc != ECORE_SUCCESS) {
1090                         DP_ERR(edev, "Failed to update vport\n");
1091                         return -1;
1092                 }
1093         }
1094
1095         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1096         return 0;
1097 }
1098
1099 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1100                                 uint16_t vlan_id, int on)
1101 {
1102         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1103         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1104         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1105         struct qede_vlan_entry *tmp = NULL;
1106         struct qede_vlan_entry *vlan;
1107         struct ecore_filter_ucast ucast;
1108         int rc;
1109
1110         if (on) {
1111                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1112                         DP_ERR(edev, "Reached max VLAN filter limit"
1113                                       " enabling accept_any_vlan\n");
1114                         qede_config_accept_any_vlan(qdev, true);
1115                         return 0;
1116                 }
1117
1118                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1119                         if (tmp->vid == vlan_id) {
1120                                 DP_INFO(edev, "VLAN %u already configured\n",
1121                                         vlan_id);
1122                                 return 0;
1123                         }
1124                 }
1125
1126                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1127                                   RTE_CACHE_LINE_SIZE);
1128
1129                 if (!vlan) {
1130                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1131                         return -ENOMEM;
1132                 }
1133
1134                 qede_set_ucast_cmn_params(&ucast);
1135                 ucast.opcode = ECORE_FILTER_ADD;
1136                 ucast.type = ECORE_FILTER_VLAN;
1137                 ucast.vlan = vlan_id;
1138                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1139                                             NULL);
1140                 if (rc != 0) {
1141                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1142                                rc);
1143                         rte_free(vlan);
1144                 } else {
1145                         vlan->vid = vlan_id;
1146                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1147                         qdev->configured_vlans++;
1148                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1149                                 vlan_id, qdev->configured_vlans);
1150                 }
1151         } else {
1152                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1153                         if (tmp->vid == vlan_id)
1154                                 break;
1155                 }
1156
1157                 if (!tmp) {
1158                         if (qdev->configured_vlans == 0) {
1159                                 DP_INFO(edev,
1160                                         "No VLAN filters configured yet\n");
1161                                 return 0;
1162                         }
1163
1164                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1165                         return -EINVAL;
1166                 }
1167
1168                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1169
1170                 qede_set_ucast_cmn_params(&ucast);
1171                 ucast.opcode = ECORE_FILTER_REMOVE;
1172                 ucast.type = ECORE_FILTER_VLAN;
1173                 ucast.vlan = vlan_id;
1174                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1175                                             NULL);
1176                 if (rc != 0) {
1177                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1178                                vlan_id, rc);
1179                 } else {
1180                         qdev->configured_vlans--;
1181                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1182                                 vlan_id, qdev->configured_vlans);
1183                 }
1184         }
1185
1186         return rc;
1187 }
1188
1189 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1190 {
1191         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1192         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1193         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1194
1195         if (mask & ETH_VLAN_STRIP_MASK) {
1196                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1197                         (void)qede_vlan_stripping(eth_dev, 1);
1198                 else
1199                         (void)qede_vlan_stripping(eth_dev, 0);
1200         }
1201
1202         if (mask & ETH_VLAN_FILTER_MASK) {
1203                 /* VLAN filtering kicks in when a VLAN is added */
1204                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1205                         qede_vlan_filter_set(eth_dev, 0, 1);
1206                 } else {
1207                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1208                                 DP_ERR(edev,
1209                                   " Please remove existing VLAN filters"
1210                                   " before disabling VLAN filtering\n");
1211                                 /* Signal app that VLAN filtering is still
1212                                  * enabled
1213                                  */
1214                                 eth_dev->data->dev_conf.rxmode.offloads |=
1215                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1216                         } else {
1217                                 qede_vlan_filter_set(eth_dev, 0, 0);
1218                         }
1219                 }
1220         }
1221
1222         if (mask & ETH_VLAN_EXTEND_MASK)
1223                 DP_ERR(edev, "Extend VLAN not supported\n");
1224
1225         qdev->vlan_offload_mask = mask;
1226
1227         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1228
1229         return 0;
1230 }
1231
1232 static void qede_prandom_bytes(uint32_t *buff)
1233 {
1234         uint8_t i;
1235
1236         srand((unsigned int)time(NULL));
1237         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1238                 buff[i] = rand();
1239 }
1240
1241 int qede_config_rss(struct rte_eth_dev *eth_dev)
1242 {
1243         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1244         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1245         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1246         struct rte_eth_rss_reta_entry64 reta_conf[2];
1247         struct rte_eth_rss_conf rss_conf;
1248         uint32_t i, id, pos, q;
1249
1250         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1251         if (!rss_conf.rss_key) {
1252                 DP_INFO(edev, "Applying driver default key\n");
1253                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1254                 qede_prandom_bytes(&def_rss_key[0]);
1255                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1256         }
1257
1258         /* Configure RSS hash */
1259         if (qede_rss_hash_update(eth_dev, &rss_conf))
1260                 return -EINVAL;
1261
1262         /* Configure default RETA */
1263         memset(reta_conf, 0, sizeof(reta_conf));
1264         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1265                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1266
1267         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1268                 id = i / RTE_RETA_GROUP_SIZE;
1269                 pos = i % RTE_RETA_GROUP_SIZE;
1270                 q = i % QEDE_RSS_COUNT(qdev);
1271                 reta_conf[id].reta[pos] = q;
1272         }
1273         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1274                                  ECORE_RSS_IND_TABLE_SIZE))
1275                 return -EINVAL;
1276
1277         return 0;
1278 }
1279
1280 static void qede_fastpath_start(struct ecore_dev *edev)
1281 {
1282         struct ecore_hwfn *p_hwfn;
1283         int i;
1284
1285         for_each_hwfn(edev, i) {
1286                 p_hwfn = &edev->hwfns[i];
1287                 ecore_hw_start_fastpath(p_hwfn);
1288         }
1289 }
1290
1291 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1292 {
1293         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1294         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1295         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1296
1297         PMD_INIT_FUNC_TRACE(edev);
1298
1299         /* Configure TPA parameters */
1300         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1301                 if (qede_enable_tpa(eth_dev, true))
1302                         return -EINVAL;
1303                 /* Enable scatter mode for LRO */
1304                 if (!eth_dev->data->scattered_rx)
1305                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1306         }
1307
1308         /* Start queues */
1309         if (qede_start_queues(eth_dev))
1310                 goto err;
1311
1312         if (IS_PF(edev))
1313                 qede_reset_queue_stats(qdev, true);
1314
1315         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1316          * enabling RSS. Hence RSS configuration is deferred upto this point.
1317          * Also, we would like to retain similar behavior in PF case, so we
1318          * don't do PF/VF specific check here.
1319          */
1320         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1321                 if (qede_config_rss(eth_dev))
1322                         goto err;
1323
1324         /* Enable vport*/
1325         if (qede_activate_vport(eth_dev, true))
1326                 goto err;
1327
1328         /* Update link status */
1329         qede_link_update(eth_dev, 0);
1330
1331         /* Start/resume traffic */
1332         qede_fastpath_start(edev);
1333
1334         DP_INFO(edev, "Device started\n");
1335
1336         return 0;
1337 err:
1338         DP_ERR(edev, "Device start fails\n");
1339         return -1; /* common error code is < 0 */
1340 }
1341
1342 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1343 {
1344         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1345         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1346
1347         PMD_INIT_FUNC_TRACE(edev);
1348
1349         /* Disable vport */
1350         if (qede_activate_vport(eth_dev, false))
1351                 return;
1352
1353         if (qdev->enable_lro)
1354                 qede_enable_tpa(eth_dev, false);
1355
1356         /* Stop queues */
1357         qede_stop_queues(eth_dev);
1358
1359         /* Disable traffic */
1360         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1361
1362         if (IS_PF(edev))
1363                 qede_mac_addr_remove(eth_dev, 0);
1364
1365         DP_INFO(edev, "Device is stopped\n");
1366 }
1367
1368 const char *valid_args[] = {
1369         QEDE_NPAR_TX_SWITCHING,
1370         QEDE_VF_TX_SWITCHING,
1371         NULL,
1372 };
1373
1374 static int qede_args_check(const char *key, const char *val, void *opaque)
1375 {
1376         unsigned long tmp;
1377         int ret = 0;
1378         struct rte_eth_dev *eth_dev = opaque;
1379         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1380         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1381
1382         errno = 0;
1383         tmp = strtoul(val, NULL, 0);
1384         if (errno) {
1385                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1386                 return errno;
1387         }
1388
1389         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1390             (strcmp(QEDE_VF_TX_SWITCHING, key) == 0))
1391                 qdev->enable_tx_switching = !!tmp;
1392
1393         return ret;
1394 }
1395
1396 static int qede_args(struct rte_eth_dev *eth_dev)
1397 {
1398         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1399         struct rte_kvargs *kvlist;
1400         struct rte_devargs *devargs;
1401         int ret;
1402         int i;
1403
1404         devargs = pci_dev->device.devargs;
1405         if (!devargs)
1406                 return 0; /* return success */
1407
1408         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1409         if (kvlist == NULL)
1410                 return -EINVAL;
1411
1412          /* Process parameters. */
1413         for (i = 0; (valid_args[i] != NULL); ++i) {
1414                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1415                         ret = rte_kvargs_process(kvlist, valid_args[i],
1416                                                  qede_args_check, eth_dev);
1417                         if (ret != ECORE_SUCCESS) {
1418                                 rte_kvargs_free(kvlist);
1419                                 return ret;
1420                         }
1421                 }
1422         }
1423         rte_kvargs_free(kvlist);
1424
1425         return 0;
1426 }
1427
1428 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1429 {
1430         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1431         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1432         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1433         int ret;
1434
1435         PMD_INIT_FUNC_TRACE(edev);
1436
1437         /* Check requirements for 100G mode */
1438         if (ECORE_IS_CMT(edev)) {
1439                 if (eth_dev->data->nb_rx_queues < 2 ||
1440                     eth_dev->data->nb_tx_queues < 2) {
1441                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1442                         return -EINVAL;
1443                 }
1444
1445                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1446                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
1447                         DP_ERR(edev,
1448                                "100G mode needs even no. of RX/TX queues\n");
1449                         return -EINVAL;
1450                 }
1451         }
1452
1453         /* We need to have min 1 RX queue.There is no min check in
1454          * rte_eth_dev_configure(), so we are checking it here.
1455          */
1456         if (eth_dev->data->nb_rx_queues == 0) {
1457                 DP_ERR(edev, "Minimum one RX queue is required\n");
1458                 return -EINVAL;
1459         }
1460
1461         /* Enable Tx switching by default */
1462         qdev->enable_tx_switching = 1;
1463
1464         /* Parse devargs and fix up rxmode */
1465         if (qede_args(eth_dev))
1466                 return -ENOTSUP;
1467
1468         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1469               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1470                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1471                 return -ENOTSUP;
1472         }
1473         /* Flow director mode check */
1474         if (qede_check_fdir_support(eth_dev))
1475                 return -ENOTSUP;
1476
1477         qede_dealloc_fp_resc(eth_dev);
1478         qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1479         qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1480         if (qede_alloc_fp_resc(qdev))
1481                 return -ENOMEM;
1482
1483         /* If jumbo enabled adjust MTU */
1484         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1485                 eth_dev->data->mtu =
1486                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1487                         ETHER_HDR_LEN - ETHER_CRC_LEN;
1488
1489         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1490                 eth_dev->data->scattered_rx = 1;
1491
1492         if (qede_start_vport(qdev, eth_dev->data->mtu))
1493                 return -1;
1494
1495         qdev->mtu = eth_dev->data->mtu;
1496
1497         /* Enable VLAN offloads by default */
1498         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1499                                              ETH_VLAN_FILTER_MASK |
1500                                              ETH_VLAN_EXTEND_MASK);
1501         if (ret)
1502                 return ret;
1503
1504         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1505                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1506
1507         return 0;
1508 }
1509
1510 /* Info about HW descriptor ring limitations */
1511 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1512         .nb_max = 0x8000, /* 32K */
1513         .nb_min = 128,
1514         .nb_align = 128 /* lowest common multiple */
1515 };
1516
1517 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1518         .nb_max = 0x8000, /* 32K */
1519         .nb_min = 256,
1520         .nb_align = 256,
1521         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1522         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1523 };
1524
1525 static void
1526 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1527                   struct rte_eth_dev_info *dev_info)
1528 {
1529         struct qede_dev *qdev = eth_dev->data->dev_private;
1530         struct ecore_dev *edev = &qdev->edev;
1531         struct qed_link_output link;
1532         uint32_t speed_cap = 0;
1533
1534         PMD_INIT_FUNC_TRACE(edev);
1535
1536         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1537         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1538         dev_info->rx_desc_lim = qede_rx_desc_lim;
1539         dev_info->tx_desc_lim = qede_tx_desc_lim;
1540
1541         if (IS_PF(edev))
1542                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1543                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1544         else
1545                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1546                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1547         dev_info->max_tx_queues = dev_info->max_rx_queues;
1548
1549         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1550         dev_info->max_vfs = 0;
1551         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1552         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1553         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1554         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1555                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1556                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1557                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1558                                      DEV_RX_OFFLOAD_TCP_LRO     |
1559                                      DEV_RX_OFFLOAD_CRC_STRIP   |
1560                                      DEV_RX_OFFLOAD_SCATTER     |
1561                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1562                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1563                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1564         dev_info->rx_queue_offload_capa = 0;
1565
1566         /* TX offloads are on a per-packet basis, so it is applicable
1567          * to both at port and queue levels.
1568          */
1569         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1570                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1571                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1572                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1573                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1574                                      DEV_TX_OFFLOAD_QINQ_INSERT |
1575                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1576                                      DEV_TX_OFFLOAD_TCP_TSO     |
1577                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1578                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1579         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1580
1581         dev_info->default_txconf = (struct rte_eth_txconf) {
1582                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1583         };
1584
1585         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1586                 /* Packets are always dropped if no descriptors are available */
1587                 .rx_drop_en = 1,
1588                 /* The below RX offloads are always enabled */
1589                 .offloads = (DEV_RX_OFFLOAD_CRC_STRIP  |
1590                              DEV_RX_OFFLOAD_IPV4_CKSUM |
1591                              DEV_RX_OFFLOAD_TCP_CKSUM  |
1592                              DEV_RX_OFFLOAD_UDP_CKSUM),
1593         };
1594
1595         memset(&link, 0, sizeof(struct qed_link_output));
1596         qdev->ops->common->get_link(edev, &link);
1597         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1598                 speed_cap |= ETH_LINK_SPEED_1G;
1599         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1600                 speed_cap |= ETH_LINK_SPEED_10G;
1601         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1602                 speed_cap |= ETH_LINK_SPEED_25G;
1603         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1604                 speed_cap |= ETH_LINK_SPEED_40G;
1605         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1606                 speed_cap |= ETH_LINK_SPEED_50G;
1607         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1608                 speed_cap |= ETH_LINK_SPEED_100G;
1609         dev_info->speed_capa = speed_cap;
1610 }
1611
1612 /* return 0 means link status changed, -1 means not changed */
1613 int
1614 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1615 {
1616         struct qede_dev *qdev = eth_dev->data->dev_private;
1617         struct ecore_dev *edev = &qdev->edev;
1618         uint16_t link_duplex;
1619         struct qed_link_output link;
1620         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1621
1622         memset(&link, 0, sizeof(struct qed_link_output));
1623         qdev->ops->common->get_link(edev, &link);
1624
1625         /* Link Speed */
1626         curr->link_speed = link.speed;
1627
1628         /* Link Mode */
1629         switch (link.duplex) {
1630         case QEDE_DUPLEX_HALF:
1631                 link_duplex = ETH_LINK_HALF_DUPLEX;
1632                 break;
1633         case QEDE_DUPLEX_FULL:
1634                 link_duplex = ETH_LINK_FULL_DUPLEX;
1635                 break;
1636         case QEDE_DUPLEX_UNKNOWN:
1637         default:
1638                 link_duplex = -1;
1639         }
1640         curr->link_duplex = link_duplex;
1641
1642         /* Link Status */
1643         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1644
1645         /* AN */
1646         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1647                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1648
1649         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1650                 curr->link_speed, curr->link_duplex,
1651                 curr->link_autoneg, curr->link_status);
1652
1653         /* return 0 means link status changed, -1 means not changed */
1654         return ((curr->link_status == link.link_up) ? -1 : 0);
1655 }
1656
1657 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1658 {
1659 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1660         struct qede_dev *qdev = eth_dev->data->dev_private;
1661         struct ecore_dev *edev = &qdev->edev;
1662
1663         PMD_INIT_FUNC_TRACE(edev);
1664 #endif
1665
1666         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1667
1668         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1669                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1670
1671         qed_configure_filter_rx_mode(eth_dev, type);
1672 }
1673
1674 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1675 {
1676 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1677         struct qede_dev *qdev = eth_dev->data->dev_private;
1678         struct ecore_dev *edev = &qdev->edev;
1679
1680         PMD_INIT_FUNC_TRACE(edev);
1681 #endif
1682
1683         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1684                 qed_configure_filter_rx_mode(eth_dev,
1685                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1686         else
1687                 qed_configure_filter_rx_mode(eth_dev,
1688                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1689 }
1690
1691 static void qede_poll_sp_sb_cb(void *param)
1692 {
1693         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1694         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1695         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1696         int rc;
1697
1698         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1699         qede_interrupt_action(&edev->hwfns[1]);
1700
1701         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1702                                qede_poll_sp_sb_cb,
1703                                (void *)eth_dev);
1704         if (rc != 0) {
1705                 DP_ERR(edev, "Unable to start periodic"
1706                              " timer rc %d\n", rc);
1707                 assert(false && "Unable to start periodic timer");
1708         }
1709 }
1710
1711 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1712 {
1713         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1714         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1715         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1716
1717         PMD_INIT_FUNC_TRACE(edev);
1718
1719         /* dev_stop() shall cleanup fp resources in hw but without releasing
1720          * dma memories and sw structures so that dev_start() can be called
1721          * by the app without reconfiguration. However, in dev_close() we
1722          * can release all the resources and device can be brought up newly
1723          */
1724         if (eth_dev->data->dev_started)
1725                 qede_dev_stop(eth_dev);
1726
1727         qede_stop_vport(edev);
1728         qdev->vport_started = false;
1729         qede_fdir_dealloc_resc(eth_dev);
1730         qede_dealloc_fp_resc(eth_dev);
1731
1732         eth_dev->data->nb_rx_queues = 0;
1733         eth_dev->data->nb_tx_queues = 0;
1734
1735         /* Bring the link down */
1736         qede_dev_set_link_state(eth_dev, false);
1737         qdev->ops->common->slowpath_stop(edev);
1738         qdev->ops->common->remove(edev);
1739         rte_intr_disable(&pci_dev->intr_handle);
1740         rte_intr_callback_unregister(&pci_dev->intr_handle,
1741                                      qede_interrupt_handler, (void *)eth_dev);
1742         if (ECORE_IS_CMT(edev))
1743                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1744 }
1745
1746 static int
1747 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1748 {
1749         struct qede_dev *qdev = eth_dev->data->dev_private;
1750         struct ecore_dev *edev = &qdev->edev;
1751         struct ecore_eth_stats stats;
1752         unsigned int i = 0, j = 0, qid;
1753         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1754         struct qede_tx_queue *txq;
1755
1756         ecore_get_vport_stats(edev, &stats);
1757
1758         /* RX Stats */
1759         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1760             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1761
1762         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1763             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1764
1765         eth_stats->ierrors = stats.common.rx_crc_errors +
1766             stats.common.rx_align_errors +
1767             stats.common.rx_carrier_errors +
1768             stats.common.rx_oversize_packets +
1769             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1770
1771         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1772
1773         eth_stats->imissed = stats.common.mftag_filter_discards +
1774             stats.common.mac_filter_discards +
1775             stats.common.no_buff_discards +
1776             stats.common.brb_truncates + stats.common.brb_discards;
1777
1778         /* TX stats */
1779         eth_stats->opackets = stats.common.tx_ucast_pkts +
1780             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1781
1782         eth_stats->obytes = stats.common.tx_ucast_bytes +
1783             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1784
1785         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1786
1787         /* Queue stats */
1788         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1789                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1790         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1791                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1792         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1793             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1794                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1795                        "Not all the queue stats will be displayed. Set"
1796                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1797                        " appropriately and retry.\n");
1798
1799         for_each_rss(qid) {
1800                 eth_stats->q_ipackets[i] =
1801                         *(uint64_t *)(
1802                                 ((char *)(qdev->fp_array[qid].rxq)) +
1803                                 offsetof(struct qede_rx_queue,
1804                                 rcv_pkts));
1805                 eth_stats->q_errors[i] =
1806                         *(uint64_t *)(
1807                                 ((char *)(qdev->fp_array[qid].rxq)) +
1808                                 offsetof(struct qede_rx_queue,
1809                                 rx_hw_errors)) +
1810                         *(uint64_t *)(
1811                                 ((char *)(qdev->fp_array[qid].rxq)) +
1812                                 offsetof(struct qede_rx_queue,
1813                                 rx_alloc_errors));
1814                 i++;
1815                 if (i == rxq_stat_cntrs)
1816                         break;
1817         }
1818
1819         for_each_tss(qid) {
1820                 txq = qdev->fp_array[qid].txq;
1821                 eth_stats->q_opackets[j] =
1822                         *((uint64_t *)(uintptr_t)
1823                                 (((uint64_t)(uintptr_t)(txq)) +
1824                                  offsetof(struct qede_tx_queue,
1825                                           xmit_pkts)));
1826                 j++;
1827                 if (j == txq_stat_cntrs)
1828                         break;
1829         }
1830
1831         return 0;
1832 }
1833
1834 static unsigned
1835 qede_get_xstats_count(struct qede_dev *qdev) {
1836         if (ECORE_IS_BB(&qdev->edev))
1837                 return RTE_DIM(qede_xstats_strings) +
1838                        RTE_DIM(qede_bb_xstats_strings) +
1839                        (RTE_DIM(qede_rxq_xstats_strings) *
1840                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1841                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1842         else
1843                 return RTE_DIM(qede_xstats_strings) +
1844                        RTE_DIM(qede_ah_xstats_strings) +
1845                        (RTE_DIM(qede_rxq_xstats_strings) *
1846                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1847                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1848 }
1849
1850 static int
1851 qede_get_xstats_names(struct rte_eth_dev *dev,
1852                       struct rte_eth_xstat_name *xstats_names,
1853                       __rte_unused unsigned int limit)
1854 {
1855         struct qede_dev *qdev = dev->data->dev_private;
1856         struct ecore_dev *edev = &qdev->edev;
1857         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1858         unsigned int i, qid, stat_idx = 0;
1859         unsigned int rxq_stat_cntrs;
1860
1861         if (xstats_names != NULL) {
1862                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1863                         snprintf(xstats_names[stat_idx].name,
1864                                 sizeof(xstats_names[stat_idx].name),
1865                                 "%s",
1866                                 qede_xstats_strings[i].name);
1867                         stat_idx++;
1868                 }
1869
1870                 if (ECORE_IS_BB(edev)) {
1871                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1872                                 snprintf(xstats_names[stat_idx].name,
1873                                         sizeof(xstats_names[stat_idx].name),
1874                                         "%s",
1875                                         qede_bb_xstats_strings[i].name);
1876                                 stat_idx++;
1877                         }
1878                 } else {
1879                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1880                                 snprintf(xstats_names[stat_idx].name,
1881                                         sizeof(xstats_names[stat_idx].name),
1882                                         "%s",
1883                                         qede_ah_xstats_strings[i].name);
1884                                 stat_idx++;
1885                         }
1886                 }
1887
1888                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1889                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1890                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1891                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1892                                 snprintf(xstats_names[stat_idx].name,
1893                                         sizeof(xstats_names[stat_idx].name),
1894                                         "%.4s%d%s",
1895                                         qede_rxq_xstats_strings[i].name, qid,
1896                                         qede_rxq_xstats_strings[i].name + 4);
1897                                 stat_idx++;
1898                         }
1899                 }
1900         }
1901
1902         return stat_cnt;
1903 }
1904
1905 static int
1906 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1907                 unsigned int n)
1908 {
1909         struct qede_dev *qdev = dev->data->dev_private;
1910         struct ecore_dev *edev = &qdev->edev;
1911         struct ecore_eth_stats stats;
1912         const unsigned int num = qede_get_xstats_count(qdev);
1913         unsigned int i, qid, stat_idx = 0;
1914         unsigned int rxq_stat_cntrs;
1915
1916         if (n < num)
1917                 return num;
1918
1919         ecore_get_vport_stats(edev, &stats);
1920
1921         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1922                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1923                                              qede_xstats_strings[i].offset);
1924                 xstats[stat_idx].id = stat_idx;
1925                 stat_idx++;
1926         }
1927
1928         if (ECORE_IS_BB(edev)) {
1929                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1930                         xstats[stat_idx].value =
1931                                         *(uint64_t *)(((char *)&stats) +
1932                                         qede_bb_xstats_strings[i].offset);
1933                         xstats[stat_idx].id = stat_idx;
1934                         stat_idx++;
1935                 }
1936         } else {
1937                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1938                         xstats[stat_idx].value =
1939                                         *(uint64_t *)(((char *)&stats) +
1940                                         qede_ah_xstats_strings[i].offset);
1941                         xstats[stat_idx].id = stat_idx;
1942                         stat_idx++;
1943                 }
1944         }
1945
1946         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1947                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1948         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1949                 for_each_rss(qid) {
1950                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1951                                 xstats[stat_idx].value = *(uint64_t *)(
1952                                         ((char *)(qdev->fp_array[qid].rxq)) +
1953                                          qede_rxq_xstats_strings[i].offset);
1954                                 xstats[stat_idx].id = stat_idx;
1955                                 stat_idx++;
1956                         }
1957                 }
1958         }
1959
1960         return stat_idx;
1961 }
1962
1963 static void
1964 qede_reset_xstats(struct rte_eth_dev *dev)
1965 {
1966         struct qede_dev *qdev = dev->data->dev_private;
1967         struct ecore_dev *edev = &qdev->edev;
1968
1969         ecore_reset_vport_stats(edev);
1970         qede_reset_queue_stats(qdev, true);
1971 }
1972
1973 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1974 {
1975         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1976         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1977         struct qed_link_params link_params;
1978         int rc;
1979
1980         DP_INFO(edev, "setting link state %d\n", link_up);
1981         memset(&link_params, 0, sizeof(link_params));
1982         link_params.link_up = link_up;
1983         rc = qdev->ops->common->set_link(edev, &link_params);
1984         if (rc != ECORE_SUCCESS)
1985                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1986
1987         return rc;
1988 }
1989
1990 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1991 {
1992         return qede_dev_set_link_state(eth_dev, true);
1993 }
1994
1995 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1996 {
1997         return qede_dev_set_link_state(eth_dev, false);
1998 }
1999
2000 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
2001 {
2002         struct qede_dev *qdev = eth_dev->data->dev_private;
2003         struct ecore_dev *edev = &qdev->edev;
2004
2005         ecore_reset_vport_stats(edev);
2006         qede_reset_queue_stats(qdev, false);
2007 }
2008
2009 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
2010 {
2011         enum qed_filter_rx_mode_type type =
2012             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
2013
2014         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2015                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
2016
2017         qed_configure_filter_rx_mode(eth_dev, type);
2018 }
2019
2020 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
2021 {
2022         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2023                 qed_configure_filter_rx_mode(eth_dev,
2024                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
2025         else
2026                 qed_configure_filter_rx_mode(eth_dev,
2027                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
2028 }
2029
2030 static int
2031 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
2032                       uint32_t mc_addrs_num)
2033 {
2034         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2035         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2036         uint8_t i;
2037
2038         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
2039                 DP_ERR(edev, "Reached max multicast filters limit,"
2040                              "Please enable multicast promisc mode\n");
2041                 return -ENOSPC;
2042         }
2043
2044         for (i = 0; i < mc_addrs_num; i++) {
2045                 if (!is_multicast_ether_addr(&mc_addrs[i])) {
2046                         DP_ERR(edev, "Not a valid multicast MAC\n");
2047                         return -EINVAL;
2048                 }
2049         }
2050
2051         /* Flush all existing entries */
2052         if (qede_del_mcast_filters(eth_dev))
2053                 return -1;
2054
2055         /* Set new mcast list */
2056         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
2057 }
2058
2059 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2060                               struct rte_eth_fc_conf *fc_conf)
2061 {
2062         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2063         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2064         struct qed_link_output current_link;
2065         struct qed_link_params params;
2066
2067         memset(&current_link, 0, sizeof(current_link));
2068         qdev->ops->common->get_link(edev, &current_link);
2069
2070         memset(&params, 0, sizeof(params));
2071         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2072         if (fc_conf->autoneg) {
2073                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2074                         DP_ERR(edev, "Autoneg not supported\n");
2075                         return -EINVAL;
2076                 }
2077                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2078         }
2079
2080         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2081         if (fc_conf->mode == RTE_FC_FULL)
2082                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2083                                         QED_LINK_PAUSE_RX_ENABLE);
2084         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2085                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2086         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2087                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2088
2089         params.link_up = true;
2090         (void)qdev->ops->common->set_link(edev, &params);
2091
2092         return 0;
2093 }
2094
2095 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2096                               struct rte_eth_fc_conf *fc_conf)
2097 {
2098         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2099         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2100         struct qed_link_output current_link;
2101
2102         memset(&current_link, 0, sizeof(current_link));
2103         qdev->ops->common->get_link(edev, &current_link);
2104
2105         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2106                 fc_conf->autoneg = true;
2107
2108         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2109                                          QED_LINK_PAUSE_TX_ENABLE))
2110                 fc_conf->mode = RTE_FC_FULL;
2111         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2112                 fc_conf->mode = RTE_FC_RX_PAUSE;
2113         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2114                 fc_conf->mode = RTE_FC_TX_PAUSE;
2115         else
2116                 fc_conf->mode = RTE_FC_NONE;
2117
2118         return 0;
2119 }
2120
2121 static const uint32_t *
2122 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2123 {
2124         static const uint32_t ptypes[] = {
2125                 RTE_PTYPE_L2_ETHER,
2126                 RTE_PTYPE_L2_ETHER_VLAN,
2127                 RTE_PTYPE_L3_IPV4,
2128                 RTE_PTYPE_L3_IPV6,
2129                 RTE_PTYPE_L4_TCP,
2130                 RTE_PTYPE_L4_UDP,
2131                 RTE_PTYPE_TUNNEL_VXLAN,
2132                 RTE_PTYPE_L4_FRAG,
2133                 RTE_PTYPE_TUNNEL_GENEVE,
2134                 RTE_PTYPE_TUNNEL_GRE,
2135                 /* Inner */
2136                 RTE_PTYPE_INNER_L2_ETHER,
2137                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2138                 RTE_PTYPE_INNER_L3_IPV4,
2139                 RTE_PTYPE_INNER_L3_IPV6,
2140                 RTE_PTYPE_INNER_L4_TCP,
2141                 RTE_PTYPE_INNER_L4_UDP,
2142                 RTE_PTYPE_INNER_L4_FRAG,
2143                 RTE_PTYPE_UNKNOWN
2144         };
2145
2146         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2147                 return ptypes;
2148
2149         return NULL;
2150 }
2151
2152 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2153 {
2154         *rss_caps = 0;
2155         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2156         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2157         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2158         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2159         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2160         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2161         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2162         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2163 }
2164
2165 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2166                          struct rte_eth_rss_conf *rss_conf)
2167 {
2168         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2169         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2170         struct ecore_sp_vport_update_params vport_update_params;
2171         struct ecore_rss_params rss_params;
2172         struct ecore_hwfn *p_hwfn;
2173         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2174         uint64_t hf = rss_conf->rss_hf;
2175         uint8_t len = rss_conf->rss_key_len;
2176         uint8_t idx;
2177         uint8_t i;
2178         int rc;
2179
2180         memset(&vport_update_params, 0, sizeof(vport_update_params));
2181         memset(&rss_params, 0, sizeof(rss_params));
2182
2183         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2184                 (unsigned long)hf, len, key);
2185
2186         if (hf != 0) {
2187                 /* Enabling RSS */
2188                 DP_INFO(edev, "Enabling rss\n");
2189
2190                 /* RSS caps */
2191                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2192                 rss_params.update_rss_capabilities = 1;
2193
2194                 /* RSS hash key */
2195                 if (key) {
2196                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2197                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2198                                 return -EINVAL;
2199                         }
2200                         DP_INFO(edev, "Applying user supplied hash key\n");
2201                         rss_params.update_rss_key = 1;
2202                         memcpy(&rss_params.rss_key, key, len);
2203                 }
2204                 rss_params.rss_enable = 1;
2205         }
2206
2207         rss_params.update_rss_config = 1;
2208         /* tbl_size has to be set with capabilities */
2209         rss_params.rss_table_size_log = 7;
2210         vport_update_params.vport_id = 0;
2211         /* pass the L2 handles instead of qids */
2212         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2213                 idx = qdev->rss_ind_table[i];
2214                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2215         }
2216         vport_update_params.rss_params = &rss_params;
2217
2218         for_each_hwfn(edev, i) {
2219                 p_hwfn = &edev->hwfns[i];
2220                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2221                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2222                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2223                 if (rc) {
2224                         DP_ERR(edev, "vport-update for RSS failed\n");
2225                         return rc;
2226                 }
2227         }
2228         qdev->rss_enable = rss_params.rss_enable;
2229
2230         /* Update local structure for hash query */
2231         qdev->rss_conf.rss_hf = hf;
2232         qdev->rss_conf.rss_key_len = len;
2233         if (qdev->rss_enable) {
2234                 if  (qdev->rss_conf.rss_key == NULL) {
2235                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2236                         if (qdev->rss_conf.rss_key == NULL) {
2237                                 DP_ERR(edev, "No memory to store RSS key\n");
2238                                 return -ENOMEM;
2239                         }
2240                 }
2241                 if (key && len) {
2242                         DP_INFO(edev, "Storing RSS key\n");
2243                         memcpy(qdev->rss_conf.rss_key, key, len);
2244                 }
2245         } else if (!qdev->rss_enable && len == 0) {
2246                 if (qdev->rss_conf.rss_key) {
2247                         free(qdev->rss_conf.rss_key);
2248                         qdev->rss_conf.rss_key = NULL;
2249                         DP_INFO(edev, "Free RSS key\n");
2250                 }
2251         }
2252
2253         return 0;
2254 }
2255
2256 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2257                            struct rte_eth_rss_conf *rss_conf)
2258 {
2259         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2260
2261         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2262         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2263
2264         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2265                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2266                        rss_conf->rss_key_len);
2267         return 0;
2268 }
2269
2270 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2271                                     struct ecore_rss_params *rss)
2272 {
2273         int i, fn;
2274         bool rss_mode = 1; /* enable */
2275         struct ecore_queue_cid *cid;
2276         struct ecore_rss_params *t_rss;
2277
2278         /* In regular scenario, we'd simply need to take input handlers.
2279          * But in CMT, we'd have to split the handlers according to the
2280          * engine they were configured on. We'd then have to understand
2281          * whether RSS is really required, since 2-queues on CMT doesn't
2282          * require RSS.
2283          */
2284
2285         /* CMT should be round-robin */
2286         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2287                 cid = rss->rss_ind_table[i];
2288
2289                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2290                         t_rss = &rss[0];
2291                 else
2292                         t_rss = &rss[1];
2293
2294                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2295         }
2296
2297         t_rss = &rss[1];
2298         t_rss->update_rss_ind_table = 1;
2299         t_rss->rss_table_size_log = 7;
2300         t_rss->update_rss_config = 1;
2301
2302         /* Make sure RSS is actually required */
2303         for_each_hwfn(edev, fn) {
2304                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2305                      i++) {
2306                         if (rss[fn].rss_ind_table[i] !=
2307                             rss[fn].rss_ind_table[0])
2308                                 break;
2309                 }
2310
2311                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2312                         DP_INFO(edev,
2313                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2314                         rss_mode = 0;
2315                         goto out;
2316                 }
2317         }
2318
2319 out:
2320         t_rss->rss_enable = rss_mode;
2321
2322         return rss_mode;
2323 }
2324
2325 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2326                          struct rte_eth_rss_reta_entry64 *reta_conf,
2327                          uint16_t reta_size)
2328 {
2329         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2330         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2331         struct ecore_sp_vport_update_params vport_update_params;
2332         struct ecore_rss_params *params;
2333         struct ecore_hwfn *p_hwfn;
2334         uint16_t i, idx, shift;
2335         uint8_t entry;
2336         int rc = 0;
2337
2338         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2339                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2340                        reta_size);
2341                 return -EINVAL;
2342         }
2343
2344         memset(&vport_update_params, 0, sizeof(vport_update_params));
2345         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2346                              RTE_CACHE_LINE_SIZE);
2347         if (params == NULL) {
2348                 DP_ERR(edev, "failed to allocate memory\n");
2349                 return -ENOMEM;
2350         }
2351
2352         for (i = 0; i < reta_size; i++) {
2353                 idx = i / RTE_RETA_GROUP_SIZE;
2354                 shift = i % RTE_RETA_GROUP_SIZE;
2355                 if (reta_conf[idx].mask & (1ULL << shift)) {
2356                         entry = reta_conf[idx].reta[shift];
2357                         /* Pass rxq handles to ecore */
2358                         params->rss_ind_table[i] =
2359                                         qdev->fp_array[entry].rxq->handle;
2360                         /* Update the local copy for RETA query command */
2361                         qdev->rss_ind_table[i] = entry;
2362                 }
2363         }
2364
2365         params->update_rss_ind_table = 1;
2366         params->rss_table_size_log = 7;
2367         params->update_rss_config = 1;
2368
2369         /* Fix up RETA for CMT mode device */
2370         if (ECORE_IS_CMT(edev))
2371                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2372                                                             params);
2373         vport_update_params.vport_id = 0;
2374         /* Use the current value of rss_enable */
2375         params->rss_enable = qdev->rss_enable;
2376         vport_update_params.rss_params = params;
2377
2378         for_each_hwfn(edev, i) {
2379                 p_hwfn = &edev->hwfns[i];
2380                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2381                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2382                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2383                 if (rc) {
2384                         DP_ERR(edev, "vport-update for RSS failed\n");
2385                         goto out;
2386                 }
2387         }
2388
2389 out:
2390         rte_free(params);
2391         return rc;
2392 }
2393
2394 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2395                                struct rte_eth_rss_reta_entry64 *reta_conf,
2396                                uint16_t reta_size)
2397 {
2398         struct qede_dev *qdev = eth_dev->data->dev_private;
2399         struct ecore_dev *edev = &qdev->edev;
2400         uint16_t i, idx, shift;
2401         uint8_t entry;
2402
2403         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2404                 DP_ERR(edev, "reta_size %d is not supported\n",
2405                        reta_size);
2406                 return -EINVAL;
2407         }
2408
2409         for (i = 0; i < reta_size; i++) {
2410                 idx = i / RTE_RETA_GROUP_SIZE;
2411                 shift = i % RTE_RETA_GROUP_SIZE;
2412                 if (reta_conf[idx].mask & (1ULL << shift)) {
2413                         entry = qdev->rss_ind_table[i];
2414                         reta_conf[idx].reta[shift] = entry;
2415                 }
2416         }
2417
2418         return 0;
2419 }
2420
2421
2422
2423 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2424 {
2425         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2426         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2427         struct rte_eth_dev_info dev_info = {0};
2428         struct qede_fastpath *fp;
2429         uint32_t max_rx_pkt_len;
2430         uint32_t frame_size;
2431         uint16_t rx_buf_size;
2432         uint16_t bufsz;
2433         bool restart = false;
2434         int i;
2435
2436         PMD_INIT_FUNC_TRACE(edev);
2437         qede_dev_info_get(dev, &dev_info);
2438         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2439         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2440         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2441                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2442                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2443                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2444                 return -EINVAL;
2445         }
2446         if (!dev->data->scattered_rx &&
2447             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2448                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2449                         dev->data->min_rx_buf_size);
2450                 return -EINVAL;
2451         }
2452         /* Temporarily replace I/O functions with dummy ones. It cannot
2453          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2454          */
2455         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2456         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2457         if (dev->data->dev_started) {
2458                 dev->data->dev_started = 0;
2459                 qede_dev_stop(dev);
2460                 restart = true;
2461         } else {
2462                 if (IS_PF(edev))
2463                         qede_mac_addr_remove(dev, 0);
2464         }
2465         rte_delay_ms(1000);
2466         qede_start_vport(qdev, mtu); /* Recreate vport */
2467         qdev->mtu = mtu;
2468
2469         /* Fix up RX buf size for all queues of the port */
2470         for_each_rss(i) {
2471                 fp = &qdev->fp_array[i];
2472                 if (fp->rxq != NULL) {
2473                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2474                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2475                         if (dev->data->scattered_rx)
2476                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2477                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2478                         else
2479                                 rx_buf_size = frame_size;
2480                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2481                         fp->rxq->rx_buf_size = rx_buf_size;
2482                         DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2483                 }
2484         }
2485         if (max_rx_pkt_len > ETHER_MAX_LEN)
2486                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2487         else
2488                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2489
2490         /* Restore config lost due to vport stop */
2491         if (IS_PF(edev))
2492                 qede_mac_addr_set(dev, &qdev->primary_mac);
2493
2494         if (dev->data->promiscuous)
2495                 qede_promiscuous_enable(dev);
2496         else
2497                 qede_promiscuous_disable(dev);
2498
2499         if (dev->data->all_multicast)
2500                 qede_allmulticast_enable(dev);
2501         else
2502                 qede_allmulticast_disable(dev);
2503
2504         qede_vlan_offload_set(dev, qdev->vlan_offload_mask);
2505
2506         if (!dev->data->dev_started && restart) {
2507                 qede_dev_start(dev);
2508                 dev->data->dev_started = 1;
2509         }
2510
2511         /* update max frame size */
2512         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2513         /* Reassign back */
2514         dev->rx_pkt_burst = qede_recv_pkts;
2515         dev->tx_pkt_burst = qede_xmit_pkts;
2516
2517         return 0;
2518 }
2519
2520 static int
2521 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2522                       struct rte_eth_udp_tunnel *tunnel_udp)
2523 {
2524         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2525         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2526         struct ecore_tunnel_info tunn; /* @DPDK */
2527         uint16_t udp_port;
2528         int rc;
2529
2530         PMD_INIT_FUNC_TRACE(edev);
2531
2532         memset(&tunn, 0, sizeof(tunn));
2533
2534         switch (tunnel_udp->prot_type) {
2535         case RTE_TUNNEL_TYPE_VXLAN:
2536                 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2537                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2538                                 tunnel_udp->udp_port);
2539                         return ECORE_INVAL;
2540                 }
2541                 udp_port = 0;
2542
2543                 tunn.vxlan_port.b_update_port = true;
2544                 tunn.vxlan_port.port = udp_port;
2545
2546                 rc = qede_tunnel_update(qdev, &tunn);
2547                 if (rc != ECORE_SUCCESS) {
2548                         DP_ERR(edev, "Unable to config UDP port %u\n",
2549                                tunn.vxlan_port.port);
2550                         return rc;
2551                 }
2552
2553                 qdev->vxlan.udp_port = udp_port;
2554                 /* If the request is to delete UDP port and if the number of
2555                  * VXLAN filters have reached 0 then VxLAN offload can be be
2556                  * disabled.
2557                  */
2558                 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2559                         return qede_vxlan_enable(eth_dev,
2560                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2561
2562                 break;
2563         case RTE_TUNNEL_TYPE_GENEVE:
2564                 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2565                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2566                                 tunnel_udp->udp_port);
2567                         return ECORE_INVAL;
2568                 }
2569
2570                 udp_port = 0;
2571
2572                 tunn.geneve_port.b_update_port = true;
2573                 tunn.geneve_port.port = udp_port;
2574
2575                 rc = qede_tunnel_update(qdev, &tunn);
2576                 if (rc != ECORE_SUCCESS) {
2577                         DP_ERR(edev, "Unable to config UDP port %u\n",
2578                                tunn.vxlan_port.port);
2579                         return rc;
2580                 }
2581
2582                 qdev->vxlan.udp_port = udp_port;
2583                 /* If the request is to delete UDP port and if the number of
2584                  * GENEVE filters have reached 0 then GENEVE offload can be be
2585                  * disabled.
2586                  */
2587                 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2588                         return qede_geneve_enable(eth_dev,
2589                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2590
2591                 break;
2592
2593         default:
2594                 return ECORE_INVAL;
2595         }
2596
2597         return 0;
2598
2599 }
2600 static int
2601 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2602                       struct rte_eth_udp_tunnel *tunnel_udp)
2603 {
2604         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2605         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2606         struct ecore_tunnel_info tunn; /* @DPDK */
2607         uint16_t udp_port;
2608         int rc;
2609
2610         PMD_INIT_FUNC_TRACE(edev);
2611
2612         memset(&tunn, 0, sizeof(tunn));
2613
2614         switch (tunnel_udp->prot_type) {
2615         case RTE_TUNNEL_TYPE_VXLAN:
2616                 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2617                         DP_INFO(edev,
2618                                 "UDP port %u for VXLAN was already configured\n",
2619                                 tunnel_udp->udp_port);
2620                         return ECORE_SUCCESS;
2621                 }
2622
2623                 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2624                  * it was not enabled while adding VXLAN filter before UDP port
2625                  * update.
2626                  */
2627                 if (!qdev->vxlan.enable) {
2628                         rc = qede_vxlan_enable(eth_dev,
2629                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2630                         if (rc != ECORE_SUCCESS) {
2631                                 DP_ERR(edev, "Failed to enable VXLAN "
2632                                         "prior to updating UDP port\n");
2633                                 return rc;
2634                         }
2635                 }
2636                 udp_port = tunnel_udp->udp_port;
2637
2638                 tunn.vxlan_port.b_update_port = true;
2639                 tunn.vxlan_port.port = udp_port;
2640
2641                 rc = qede_tunnel_update(qdev, &tunn);
2642                 if (rc != ECORE_SUCCESS) {
2643                         DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2644                                udp_port);
2645                         return rc;
2646                 }
2647
2648                 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2649
2650                 qdev->vxlan.udp_port = udp_port;
2651                 break;
2652         case RTE_TUNNEL_TYPE_GENEVE:
2653                 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2654                         DP_INFO(edev,
2655                                 "UDP port %u for GENEVE was already configured\n",
2656                                 tunnel_udp->udp_port);
2657                         return ECORE_SUCCESS;
2658                 }
2659
2660                 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2661                  * it was not enabled while adding GENEVE filter before UDP port
2662                  * update.
2663                  */
2664                 if (!qdev->geneve.enable) {
2665                         rc = qede_geneve_enable(eth_dev,
2666                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2667                         if (rc != ECORE_SUCCESS) {
2668                                 DP_ERR(edev, "Failed to enable GENEVE "
2669                                         "prior to updating UDP port\n");
2670                                 return rc;
2671                         }
2672                 }
2673                 udp_port = tunnel_udp->udp_port;
2674
2675                 tunn.geneve_port.b_update_port = true;
2676                 tunn.geneve_port.port = udp_port;
2677
2678                 rc = qede_tunnel_update(qdev, &tunn);
2679                 if (rc != ECORE_SUCCESS) {
2680                         DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2681                                udp_port);
2682                         return rc;
2683                 }
2684
2685                 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2686
2687                 qdev->geneve.udp_port = udp_port;
2688                 break;
2689         default:
2690                 return ECORE_INVAL;
2691         }
2692
2693         return 0;
2694 }
2695
2696 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2697                                        uint32_t *clss, char *str)
2698 {
2699         uint16_t j;
2700         *clss = MAX_ECORE_TUNN_CLSS;
2701
2702         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2703                 if (filter == qede_tunn_types[j].rte_filter_type) {
2704                         *type = qede_tunn_types[j].qede_type;
2705                         *clss = qede_tunn_types[j].qede_tunn_clss;
2706                         strcpy(str, qede_tunn_types[j].string);
2707                         return;
2708                 }
2709         }
2710 }
2711
2712 static int
2713 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2714                               const struct rte_eth_tunnel_filter_conf *conf,
2715                               uint32_t type)
2716 {
2717         /* Init commmon ucast params first */
2718         qede_set_ucast_cmn_params(ucast);
2719
2720         /* Copy out the required fields based on classification type */
2721         ucast->type = type;
2722
2723         switch (type) {
2724         case ECORE_FILTER_VNI:
2725                 ucast->vni = conf->tenant_id;
2726         break;
2727         case ECORE_FILTER_INNER_VLAN:
2728                 ucast->vlan = conf->inner_vlan;
2729         break;
2730         case ECORE_FILTER_MAC:
2731                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2732                        ETHER_ADDR_LEN);
2733         break;
2734         case ECORE_FILTER_INNER_MAC:
2735                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2736                        ETHER_ADDR_LEN);
2737         break;
2738         case ECORE_FILTER_MAC_VNI_PAIR:
2739                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2740                         ETHER_ADDR_LEN);
2741                 ucast->vni = conf->tenant_id;
2742         break;
2743         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2744                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2745                         ETHER_ADDR_LEN);
2746                 ucast->vni = conf->tenant_id;
2747         break;
2748         case ECORE_FILTER_INNER_PAIR:
2749                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2750                         ETHER_ADDR_LEN);
2751                 ucast->vlan = conf->inner_vlan;
2752         break;
2753         default:
2754                 return -EINVAL;
2755         }
2756
2757         return ECORE_SUCCESS;
2758 }
2759
2760 static int
2761 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2762                          const struct rte_eth_tunnel_filter_conf *conf,
2763                          __attribute__((unused)) enum rte_filter_op filter_op,
2764                          enum ecore_tunn_clss *clss,
2765                          bool add)
2766 {
2767         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2768         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2769         struct ecore_filter_ucast ucast = {0};
2770         enum ecore_filter_ucast_type type;
2771         uint16_t filter_type = 0;
2772         char str[80];
2773         int rc;
2774
2775         filter_type = conf->filter_type;
2776         /* Determine if the given filter classification is supported */
2777         qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2778         if (*clss == MAX_ECORE_TUNN_CLSS) {
2779                 DP_ERR(edev, "Unsupported filter type\n");
2780                 return -EINVAL;
2781         }
2782         /* Init tunnel ucast params */
2783         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2784         if (rc != ECORE_SUCCESS) {
2785                 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2786                 conf->filter_type);
2787                 return rc;
2788         }
2789         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2790                 str, filter_op, ucast.type);
2791
2792         ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2793
2794         /* Skip MAC/VLAN if filter is based on VNI */
2795         if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2796                 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2797                 if ((rc == 0) && add) {
2798                         /* Enable accept anyvlan */
2799                         qede_config_accept_any_vlan(qdev, true);
2800                 }
2801         } else {
2802                 rc = qede_ucast_filter(eth_dev, &ucast, add);
2803                 if (rc == 0)
2804                         rc = ecore_filter_ucast_cmd(edev, &ucast,
2805                                             ECORE_SPQ_MODE_CB, NULL);
2806         }
2807
2808         return rc;
2809 }
2810
2811 static int
2812 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2813                         enum rte_filter_op filter_op,
2814                         const struct rte_eth_tunnel_filter_conf *conf)
2815 {
2816         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2817         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2818         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2819         bool add;
2820         int rc;
2821
2822         PMD_INIT_FUNC_TRACE(edev);
2823
2824         switch (filter_op) {
2825         case RTE_ETH_FILTER_ADD:
2826                 add = true;
2827                 break;
2828         case RTE_ETH_FILTER_DELETE:
2829                 add = false;
2830                 break;
2831         default:
2832                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2833                 return -EINVAL;
2834         }
2835
2836         if (IS_VF(edev))
2837                 return qede_tunn_enable(eth_dev,
2838                                         ECORE_TUNN_CLSS_MAC_VLAN,
2839                                         conf->tunnel_type, add);
2840
2841         rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2842         if (rc != ECORE_SUCCESS)
2843                 return rc;
2844
2845         if (add) {
2846                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2847                         qdev->vxlan.num_filters++;
2848                         qdev->vxlan.filter_type = conf->filter_type;
2849                 } else { /* GENEVE */
2850                         qdev->geneve.num_filters++;
2851                         qdev->geneve.filter_type = conf->filter_type;
2852                 }
2853
2854                 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2855                     !qdev->ipgre.enable)
2856                         return qede_tunn_enable(eth_dev, clss,
2857                                                 conf->tunnel_type,
2858                                                 true);
2859         } else {
2860                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2861                         qdev->vxlan.num_filters--;
2862                 else /*GENEVE*/
2863                         qdev->geneve.num_filters--;
2864
2865                 /* Disable VXLAN if VXLAN filters become 0 */
2866                 if ((qdev->vxlan.num_filters == 0) ||
2867                     (qdev->geneve.num_filters == 0))
2868                         return qede_tunn_enable(eth_dev, clss,
2869                                                 conf->tunnel_type,
2870                                                 false);
2871         }
2872
2873         return 0;
2874 }
2875
2876 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2877                          enum rte_filter_type filter_type,
2878                          enum rte_filter_op filter_op,
2879                          void *arg)
2880 {
2881         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2882         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2883         struct rte_eth_tunnel_filter_conf *filter_conf =
2884                         (struct rte_eth_tunnel_filter_conf *)arg;
2885
2886         switch (filter_type) {
2887         case RTE_ETH_FILTER_TUNNEL:
2888                 switch (filter_conf->tunnel_type) {
2889                 case RTE_TUNNEL_TYPE_VXLAN:
2890                 case RTE_TUNNEL_TYPE_GENEVE:
2891                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2892                         DP_INFO(edev,
2893                                 "Packet steering to the specified Rx queue"
2894                                 " is not supported with UDP tunneling");
2895                         return(qede_tunn_filter_config(eth_dev, filter_op,
2896                                                       filter_conf));
2897                 case RTE_TUNNEL_TYPE_TEREDO:
2898                 case RTE_TUNNEL_TYPE_NVGRE:
2899                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2900                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2901                                 filter_conf->tunnel_type);
2902                         return -EINVAL;
2903                 case RTE_TUNNEL_TYPE_NONE:
2904                 default:
2905                         return 0;
2906                 }
2907                 break;
2908         case RTE_ETH_FILTER_FDIR:
2909                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2910         case RTE_ETH_FILTER_NTUPLE:
2911                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2912         case RTE_ETH_FILTER_MACVLAN:
2913         case RTE_ETH_FILTER_ETHERTYPE:
2914         case RTE_ETH_FILTER_FLEXIBLE:
2915         case RTE_ETH_FILTER_SYN:
2916         case RTE_ETH_FILTER_HASH:
2917         case RTE_ETH_FILTER_L2_TUNNEL:
2918         case RTE_ETH_FILTER_MAX:
2919         default:
2920                 DP_ERR(edev, "Unsupported filter type %d\n",
2921                         filter_type);
2922                 return -EINVAL;
2923         }
2924
2925         return 0;
2926 }
2927
2928 static const struct eth_dev_ops qede_eth_dev_ops = {
2929         .dev_configure = qede_dev_configure,
2930         .dev_infos_get = qede_dev_info_get,
2931         .rx_queue_setup = qede_rx_queue_setup,
2932         .rx_queue_release = qede_rx_queue_release,
2933         .tx_queue_setup = qede_tx_queue_setup,
2934         .tx_queue_release = qede_tx_queue_release,
2935         .dev_start = qede_dev_start,
2936         .dev_set_link_up = qede_dev_set_link_up,
2937         .dev_set_link_down = qede_dev_set_link_down,
2938         .link_update = qede_link_update,
2939         .promiscuous_enable = qede_promiscuous_enable,
2940         .promiscuous_disable = qede_promiscuous_disable,
2941         .allmulticast_enable = qede_allmulticast_enable,
2942         .allmulticast_disable = qede_allmulticast_disable,
2943         .set_mc_addr_list = qede_set_mc_addr_list,
2944         .dev_stop = qede_dev_stop,
2945         .dev_close = qede_dev_close,
2946         .stats_get = qede_get_stats,
2947         .stats_reset = qede_reset_stats,
2948         .xstats_get = qede_get_xstats,
2949         .xstats_reset = qede_reset_xstats,
2950         .xstats_get_names = qede_get_xstats_names,
2951         .mac_addr_add = qede_mac_addr_add,
2952         .mac_addr_remove = qede_mac_addr_remove,
2953         .mac_addr_set = qede_mac_addr_set,
2954         .vlan_offload_set = qede_vlan_offload_set,
2955         .vlan_filter_set = qede_vlan_filter_set,
2956         .flow_ctrl_set = qede_flow_ctrl_set,
2957         .flow_ctrl_get = qede_flow_ctrl_get,
2958         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2959         .rss_hash_update = qede_rss_hash_update,
2960         .rss_hash_conf_get = qede_rss_hash_conf_get,
2961         .reta_update  = qede_rss_reta_update,
2962         .reta_query  = qede_rss_reta_query,
2963         .mtu_set = qede_set_mtu,
2964         .filter_ctrl = qede_dev_filter_ctrl,
2965         .udp_tunnel_port_add = qede_udp_dst_port_add,
2966         .udp_tunnel_port_del = qede_udp_dst_port_del,
2967 };
2968
2969 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2970         .dev_configure = qede_dev_configure,
2971         .dev_infos_get = qede_dev_info_get,
2972         .rx_queue_setup = qede_rx_queue_setup,
2973         .rx_queue_release = qede_rx_queue_release,
2974         .tx_queue_setup = qede_tx_queue_setup,
2975         .tx_queue_release = qede_tx_queue_release,
2976         .dev_start = qede_dev_start,
2977         .dev_set_link_up = qede_dev_set_link_up,
2978         .dev_set_link_down = qede_dev_set_link_down,
2979         .link_update = qede_link_update,
2980         .promiscuous_enable = qede_promiscuous_enable,
2981         .promiscuous_disable = qede_promiscuous_disable,
2982         .allmulticast_enable = qede_allmulticast_enable,
2983         .allmulticast_disable = qede_allmulticast_disable,
2984         .set_mc_addr_list = qede_set_mc_addr_list,
2985         .dev_stop = qede_dev_stop,
2986         .dev_close = qede_dev_close,
2987         .stats_get = qede_get_stats,
2988         .stats_reset = qede_reset_stats,
2989         .xstats_get = qede_get_xstats,
2990         .xstats_reset = qede_reset_xstats,
2991         .xstats_get_names = qede_get_xstats_names,
2992         .vlan_offload_set = qede_vlan_offload_set,
2993         .vlan_filter_set = qede_vlan_filter_set,
2994         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2995         .rss_hash_update = qede_rss_hash_update,
2996         .rss_hash_conf_get = qede_rss_hash_conf_get,
2997         .reta_update  = qede_rss_reta_update,
2998         .reta_query  = qede_rss_reta_query,
2999         .mtu_set = qede_set_mtu,
3000         .udp_tunnel_port_add = qede_udp_dst_port_add,
3001         .udp_tunnel_port_del = qede_udp_dst_port_del,
3002 };
3003
3004 static void qede_update_pf_params(struct ecore_dev *edev)
3005 {
3006         struct ecore_pf_params pf_params;
3007
3008         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
3009         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
3010         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
3011         qed_ops->common->update_pf_params(edev, &pf_params);
3012 }
3013
3014 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
3015 {
3016         struct rte_pci_device *pci_dev;
3017         struct rte_pci_addr pci_addr;
3018         struct qede_dev *adapter;
3019         struct ecore_dev *edev;
3020         struct qed_dev_eth_info dev_info;
3021         struct qed_slowpath_params params;
3022         static bool do_once = true;
3023         uint8_t bulletin_change;
3024         uint8_t vf_mac[ETHER_ADDR_LEN];
3025         uint8_t is_mac_forced;
3026         bool is_mac_exist;
3027         /* Fix up ecore debug level */
3028         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3029         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3030         int rc;
3031
3032         /* Extract key data structures */
3033         adapter = eth_dev->data->dev_private;
3034         adapter->ethdev = eth_dev;
3035         edev = &adapter->edev;
3036         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3037         pci_addr = pci_dev->addr;
3038
3039         PMD_INIT_FUNC_TRACE(edev);
3040
3041         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3042                  pci_addr.bus, pci_addr.devid, pci_addr.function,
3043                  eth_dev->data->port_id);
3044
3045         eth_dev->rx_pkt_burst = qede_recv_pkts;
3046         eth_dev->tx_pkt_burst = qede_xmit_pkts;
3047         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3048
3049         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3050                 DP_ERR(edev, "Skipping device init from secondary process\n");
3051                 return 0;
3052         }
3053
3054         rte_eth_copy_pci_info(eth_dev, pci_dev);
3055
3056         /* @DPDK */
3057         edev->vendor_id = pci_dev->id.vendor_id;
3058         edev->device_id = pci_dev->id.device_id;
3059
3060         qed_ops = qed_get_eth_ops();
3061         if (!qed_ops) {
3062                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3063                 return -EINVAL;
3064         }
3065
3066         DP_INFO(edev, "Starting qede probe\n");
3067         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3068                                     dp_level, is_vf);
3069         if (rc != 0) {
3070                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3071                 return -ENODEV;
3072         }
3073         qede_update_pf_params(edev);
3074         rte_intr_callback_register(&pci_dev->intr_handle,
3075                                    qede_interrupt_handler, (void *)eth_dev);
3076         if (rte_intr_enable(&pci_dev->intr_handle)) {
3077                 DP_ERR(edev, "rte_intr_enable() failed\n");
3078                 return -ENODEV;
3079         }
3080
3081         /* Start the Slowpath-process */
3082         memset(&params, 0, sizeof(struct qed_slowpath_params));
3083         params.int_mode = ECORE_INT_MODE_MSIX;
3084         params.drv_major = QEDE_PMD_VERSION_MAJOR;
3085         params.drv_minor = QEDE_PMD_VERSION_MINOR;
3086         params.drv_rev = QEDE_PMD_VERSION_REVISION;
3087         params.drv_eng = QEDE_PMD_VERSION_PATCH;
3088         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3089                 QEDE_PMD_DRV_VER_STR_SIZE);
3090
3091         /* For CMT mode device do periodic polling for slowpath events.
3092          * This is required since uio device uses only one MSI-x
3093          * interrupt vector but we need one for each engine.
3094          */
3095         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3096                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
3097                                        qede_poll_sp_sb_cb,
3098                                        (void *)eth_dev);
3099                 if (rc != 0) {
3100                         DP_ERR(edev, "Unable to start periodic"
3101                                      " timer rc %d\n", rc);
3102                         return -EINVAL;
3103                 }
3104         }
3105
3106         rc = qed_ops->common->slowpath_start(edev, &params);
3107         if (rc) {
3108                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3109                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3110                                      (void *)eth_dev);
3111                 return -ENODEV;
3112         }
3113
3114         rc = qed_ops->fill_dev_info(edev, &dev_info);
3115         if (rc) {
3116                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3117                 qed_ops->common->slowpath_stop(edev);
3118                 qed_ops->common->remove(edev);
3119                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3120                                      (void *)eth_dev);
3121                 return -ENODEV;
3122         }
3123
3124         qede_alloc_etherdev(adapter, &dev_info);
3125
3126         adapter->ops->common->set_name(edev, edev->name);
3127
3128         if (!is_vf)
3129                 adapter->dev_info.num_mac_filters =
3130                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3131                                             ECORE_MAC);
3132         else
3133                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3134                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
3135
3136         /* Allocate memory for storing MAC addr */
3137         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3138                                         (ETHER_ADDR_LEN *
3139                                         adapter->dev_info.num_mac_filters),
3140                                         RTE_CACHE_LINE_SIZE);
3141
3142         if (eth_dev->data->mac_addrs == NULL) {
3143                 DP_ERR(edev, "Failed to allocate MAC address\n");
3144                 qed_ops->common->slowpath_stop(edev);
3145                 qed_ops->common->remove(edev);
3146                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3147                                      (void *)eth_dev);
3148                 return -ENOMEM;
3149         }
3150
3151         if (!is_vf) {
3152                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3153                                 hw_info.hw_mac_addr,
3154                                 &eth_dev->data->mac_addrs[0]);
3155                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3156                                 &adapter->primary_mac);
3157         } else {
3158                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3159                                        &bulletin_change);
3160                 if (bulletin_change) {
3161                         is_mac_exist =
3162                             ecore_vf_bulletin_get_forced_mac(
3163                                                 ECORE_LEADING_HWFN(edev),
3164                                                 vf_mac,
3165                                                 &is_mac_forced);
3166                         if (is_mac_exist && is_mac_forced) {
3167                                 DP_INFO(edev, "VF macaddr received from PF\n");
3168                                 ether_addr_copy((struct ether_addr *)&vf_mac,
3169                                                 &eth_dev->data->mac_addrs[0]);
3170                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3171                                                 &adapter->primary_mac);
3172                         } else {
3173                                 DP_ERR(edev, "No VF macaddr assigned\n");
3174                         }
3175                 }
3176         }
3177
3178         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3179
3180         if (do_once) {
3181                 qede_print_adapter_info(adapter);
3182                 do_once = false;
3183         }
3184
3185         /* Bring-up the link */
3186         qede_dev_set_link_state(eth_dev, true);
3187
3188         adapter->num_tx_queues = 0;
3189         adapter->num_rx_queues = 0;
3190         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3191         SLIST_INIT(&adapter->vlan_list_head);
3192         SLIST_INIT(&adapter->uc_list_head);
3193         SLIST_INIT(&adapter->mc_list_head);
3194         adapter->mtu = ETHER_MTU;
3195         adapter->vport_started = false;
3196
3197         /* VF tunnel offloads is enabled by default in PF driver */
3198         adapter->vxlan.num_filters = 0;
3199         adapter->geneve.num_filters = 0;
3200         adapter->ipgre.num_filters = 0;
3201         if (is_vf) {
3202                 adapter->vxlan.enable = true;
3203                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3204                                              ETH_TUNNEL_FILTER_IVLAN;
3205                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3206                 adapter->geneve.enable = true;
3207                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3208                                               ETH_TUNNEL_FILTER_IVLAN;
3209                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3210                 adapter->ipgre.enable = true;
3211                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3212                                              ETH_TUNNEL_FILTER_IVLAN;
3213         } else {
3214                 adapter->vxlan.enable = false;
3215                 adapter->geneve.enable = false;
3216                 adapter->ipgre.enable = false;
3217         }
3218
3219         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3220                 adapter->primary_mac.addr_bytes[0],
3221                 adapter->primary_mac.addr_bytes[1],
3222                 adapter->primary_mac.addr_bytes[2],
3223                 adapter->primary_mac.addr_bytes[3],
3224                 adapter->primary_mac.addr_bytes[4],
3225                 adapter->primary_mac.addr_bytes[5]);
3226
3227         DP_INFO(edev, "Device initialized\n");
3228
3229         return 0;
3230 }
3231
3232 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3233 {
3234         return qede_common_dev_init(eth_dev, 1);
3235 }
3236
3237 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3238 {
3239         return qede_common_dev_init(eth_dev, 0);
3240 }
3241
3242 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3243 {
3244 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3245         struct qede_dev *qdev = eth_dev->data->dev_private;
3246         struct ecore_dev *edev = &qdev->edev;
3247
3248         PMD_INIT_FUNC_TRACE(edev);
3249 #endif
3250
3251         /* only uninitialize in the primary process */
3252         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3253                 return 0;
3254
3255         /* safe to close dev here */
3256         qede_dev_close(eth_dev);
3257
3258         eth_dev->dev_ops = NULL;
3259         eth_dev->rx_pkt_burst = NULL;
3260         eth_dev->tx_pkt_burst = NULL;
3261
3262         if (eth_dev->data->mac_addrs)
3263                 rte_free(eth_dev->data->mac_addrs);
3264
3265         eth_dev->data->mac_addrs = NULL;
3266
3267         return 0;
3268 }
3269
3270 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3271 {
3272         return qede_dev_common_uninit(eth_dev);
3273 }
3274
3275 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3276 {
3277         return qede_dev_common_uninit(eth_dev);
3278 }
3279
3280 static const struct rte_pci_id pci_id_qedevf_map[] = {
3281 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3282         {
3283                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3284         },
3285         {
3286                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3287         },
3288         {
3289                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3290         },
3291         {.vendor_id = 0,}
3292 };
3293
3294 static const struct rte_pci_id pci_id_qede_map[] = {
3295 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3296         {
3297                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3298         },
3299         {
3300                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3301         },
3302         {
3303                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3304         },
3305         {
3306                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3307         },
3308         {
3309                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3310         },
3311         {
3312                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3313         },
3314         {
3315                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3316         },
3317         {
3318                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3319         },
3320         {
3321                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3322         },
3323         {
3324                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3325         },
3326         {.vendor_id = 0,}
3327 };
3328
3329 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3330         struct rte_pci_device *pci_dev)
3331 {
3332         return rte_eth_dev_pci_generic_probe(pci_dev,
3333                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3334 }
3335
3336 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3337 {
3338         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3339 }
3340
3341 static struct rte_pci_driver rte_qedevf_pmd = {
3342         .id_table = pci_id_qedevf_map,
3343         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3344         .probe = qedevf_eth_dev_pci_probe,
3345         .remove = qedevf_eth_dev_pci_remove,
3346 };
3347
3348 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3349         struct rte_pci_device *pci_dev)
3350 {
3351         return rte_eth_dev_pci_generic_probe(pci_dev,
3352                 sizeof(struct qede_dev), qede_eth_dev_init);
3353 }
3354
3355 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3356 {
3357         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3358 }
3359
3360 static struct rte_pci_driver rte_qede_pmd = {
3361         .id_table = pci_id_qede_map,
3362         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3363         .probe = qede_eth_dev_pci_probe,
3364         .remove = qede_eth_dev_pci_remove,
3365 };
3366
3367 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3368 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3369 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3370 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3371 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3372 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3373
3374 RTE_INIT(qede_init_log);
3375 static void
3376 qede_init_log(void)
3377 {
3378         qede_logtype_init = rte_log_register("pmd.net.qede.init");
3379         if (qede_logtype_init >= 0)
3380                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3381         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3382         if (qede_logtype_driver >= 0)
3383                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
3384 }