1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #include "qede_ethdev.h"
9 #include <rte_version.h>
10 #include <rte_kvargs.h>
13 int qede_logtype_init;
14 int qede_logtype_driver;
16 static const struct qed_eth_ops *qed_ops;
17 #define QEDE_SP_TIMER_PERIOD 10000 /* 100ms */
19 /* VXLAN tunnel classification mapping */
20 const struct _qede_udp_tunn_types {
21 uint16_t rte_filter_type;
22 enum ecore_filter_ucast_type qede_type;
23 enum ecore_tunn_clss qede_tunn_clss;
25 } qede_tunn_types[] = {
27 ETH_TUNNEL_FILTER_OMAC,
29 ECORE_TUNN_CLSS_MAC_VLAN,
33 ETH_TUNNEL_FILTER_TENID,
35 ECORE_TUNN_CLSS_MAC_VNI,
39 ETH_TUNNEL_FILTER_IMAC,
40 ECORE_FILTER_INNER_MAC,
41 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
45 ETH_TUNNEL_FILTER_IVLAN,
46 ECORE_FILTER_INNER_VLAN,
47 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
51 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
52 ECORE_FILTER_MAC_VNI_PAIR,
53 ECORE_TUNN_CLSS_MAC_VNI,
57 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
60 "outer-mac and inner-mac"
63 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
66 "outer-mac and inner-vlan"
69 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
70 ECORE_FILTER_INNER_MAC_VNI_PAIR,
71 ECORE_TUNN_CLSS_INNER_MAC_VNI,
75 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
81 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
82 ECORE_FILTER_INNER_PAIR,
83 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
84 "inner-mac and inner-vlan",
87 ETH_TUNNEL_FILTER_OIP,
93 ETH_TUNNEL_FILTER_IIP,
99 RTE_TUNNEL_FILTER_IMAC_IVLAN,
105 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
111 RTE_TUNNEL_FILTER_IMAC_TENID,
117 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
124 struct rte_qede_xstats_name_off {
125 char name[RTE_ETH_XSTATS_NAME_SIZE];
129 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
131 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
132 {"rx_multicast_bytes",
133 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
134 {"rx_broadcast_bytes",
135 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
136 {"rx_unicast_packets",
137 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
138 {"rx_multicast_packets",
139 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
140 {"rx_broadcast_packets",
141 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
144 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
145 {"tx_multicast_bytes",
146 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
147 {"tx_broadcast_bytes",
148 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
149 {"tx_unicast_packets",
150 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
151 {"tx_multicast_packets",
152 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
153 {"tx_broadcast_packets",
154 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
156 {"rx_64_byte_packets",
157 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
158 {"rx_65_to_127_byte_packets",
159 offsetof(struct ecore_eth_stats_common,
160 rx_65_to_127_byte_packets)},
161 {"rx_128_to_255_byte_packets",
162 offsetof(struct ecore_eth_stats_common,
163 rx_128_to_255_byte_packets)},
164 {"rx_256_to_511_byte_packets",
165 offsetof(struct ecore_eth_stats_common,
166 rx_256_to_511_byte_packets)},
167 {"rx_512_to_1023_byte_packets",
168 offsetof(struct ecore_eth_stats_common,
169 rx_512_to_1023_byte_packets)},
170 {"rx_1024_to_1518_byte_packets",
171 offsetof(struct ecore_eth_stats_common,
172 rx_1024_to_1518_byte_packets)},
173 {"tx_64_byte_packets",
174 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
175 {"tx_65_to_127_byte_packets",
176 offsetof(struct ecore_eth_stats_common,
177 tx_65_to_127_byte_packets)},
178 {"tx_128_to_255_byte_packets",
179 offsetof(struct ecore_eth_stats_common,
180 tx_128_to_255_byte_packets)},
181 {"tx_256_to_511_byte_packets",
182 offsetof(struct ecore_eth_stats_common,
183 tx_256_to_511_byte_packets)},
184 {"tx_512_to_1023_byte_packets",
185 offsetof(struct ecore_eth_stats_common,
186 tx_512_to_1023_byte_packets)},
187 {"tx_1024_to_1518_byte_packets",
188 offsetof(struct ecore_eth_stats_common,
189 tx_1024_to_1518_byte_packets)},
191 {"rx_mac_crtl_frames",
192 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
193 {"tx_mac_control_frames",
194 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
196 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
198 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
199 {"rx_priority_flow_control_frames",
200 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
201 {"tx_priority_flow_control_frames",
202 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
205 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
207 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
208 {"rx_carrier_errors",
209 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
210 {"rx_oversize_packet_errors",
211 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
213 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
214 {"rx_undersize_packet_errors",
215 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
216 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
217 {"rx_host_buffer_not_available",
218 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
219 /* Number of packets discarded because they are bigger than MTU */
220 {"rx_packet_too_big_discards",
221 offsetof(struct ecore_eth_stats_common,
222 packet_too_big_discard)},
223 {"rx_ttl_zero_discards",
224 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
225 {"rx_multi_function_tag_filter_discards",
226 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
227 {"rx_mac_filter_discards",
228 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
229 {"rx_hw_buffer_truncates",
230 offsetof(struct ecore_eth_stats_common, brb_truncates)},
231 {"rx_hw_buffer_discards",
232 offsetof(struct ecore_eth_stats_common, brb_discards)},
233 {"tx_error_drop_packets",
234 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
236 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
237 {"rx_mac_unicast_packets",
238 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
239 {"rx_mac_multicast_packets",
240 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
241 {"rx_mac_broadcast_packets",
242 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
244 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
245 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
246 {"tx_mac_unicast_packets",
247 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
248 {"tx_mac_multicast_packets",
249 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
250 {"tx_mac_broadcast_packets",
251 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
253 {"lro_coalesced_packets",
254 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
255 {"lro_coalesced_events",
256 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
258 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
259 {"lro_not_coalesced_packets",
260 offsetof(struct ecore_eth_stats_common,
261 tpa_not_coalesced_pkts)},
262 {"lro_coalesced_bytes",
263 offsetof(struct ecore_eth_stats_common,
264 tpa_coalesced_bytes)},
267 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
268 {"rx_1519_to_1522_byte_packets",
269 offsetof(struct ecore_eth_stats, bb) +
270 offsetof(struct ecore_eth_stats_bb,
271 rx_1519_to_1522_byte_packets)},
272 {"rx_1519_to_2047_byte_packets",
273 offsetof(struct ecore_eth_stats, bb) +
274 offsetof(struct ecore_eth_stats_bb,
275 rx_1519_to_2047_byte_packets)},
276 {"rx_2048_to_4095_byte_packets",
277 offsetof(struct ecore_eth_stats, bb) +
278 offsetof(struct ecore_eth_stats_bb,
279 rx_2048_to_4095_byte_packets)},
280 {"rx_4096_to_9216_byte_packets",
281 offsetof(struct ecore_eth_stats, bb) +
282 offsetof(struct ecore_eth_stats_bb,
283 rx_4096_to_9216_byte_packets)},
284 {"rx_9217_to_16383_byte_packets",
285 offsetof(struct ecore_eth_stats, bb) +
286 offsetof(struct ecore_eth_stats_bb,
287 rx_9217_to_16383_byte_packets)},
289 {"tx_1519_to_2047_byte_packets",
290 offsetof(struct ecore_eth_stats, bb) +
291 offsetof(struct ecore_eth_stats_bb,
292 tx_1519_to_2047_byte_packets)},
293 {"tx_2048_to_4095_byte_packets",
294 offsetof(struct ecore_eth_stats, bb) +
295 offsetof(struct ecore_eth_stats_bb,
296 tx_2048_to_4095_byte_packets)},
297 {"tx_4096_to_9216_byte_packets",
298 offsetof(struct ecore_eth_stats, bb) +
299 offsetof(struct ecore_eth_stats_bb,
300 tx_4096_to_9216_byte_packets)},
301 {"tx_9217_to_16383_byte_packets",
302 offsetof(struct ecore_eth_stats, bb) +
303 offsetof(struct ecore_eth_stats_bb,
304 tx_9217_to_16383_byte_packets)},
306 {"tx_lpi_entry_count",
307 offsetof(struct ecore_eth_stats, bb) +
308 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
309 {"tx_total_collisions",
310 offsetof(struct ecore_eth_stats, bb) +
311 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
314 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
315 {"rx_1519_to_max_byte_packets",
316 offsetof(struct ecore_eth_stats, ah) +
317 offsetof(struct ecore_eth_stats_ah,
318 rx_1519_to_max_byte_packets)},
319 {"tx_1519_to_max_byte_packets",
320 offsetof(struct ecore_eth_stats, ah) +
321 offsetof(struct ecore_eth_stats_ah,
322 tx_1519_to_max_byte_packets)},
325 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
327 offsetof(struct qede_rx_queue, rx_segs)},
329 offsetof(struct qede_rx_queue, rx_hw_errors)},
330 {"rx_q_allocation_errors",
331 offsetof(struct qede_rx_queue, rx_alloc_errors)}
334 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
336 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
340 qede_interrupt_handler_intx(void *param)
342 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
343 struct qede_dev *qdev = eth_dev->data->dev_private;
344 struct ecore_dev *edev = &qdev->edev;
347 /* Check if our device actually raised an interrupt */
348 status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
350 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
352 if (rte_intr_enable(eth_dev->intr_handle))
353 DP_ERR(edev, "rte_intr_enable failed\n");
358 qede_interrupt_handler(void *param)
360 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
361 struct qede_dev *qdev = eth_dev->data->dev_private;
362 struct ecore_dev *edev = &qdev->edev;
364 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
365 if (rte_intr_enable(eth_dev->intr_handle))
366 DP_ERR(edev, "rte_intr_enable failed\n");
370 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
372 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
376 static void qede_print_adapter_info(struct qede_dev *qdev)
378 struct ecore_dev *edev = &qdev->edev;
379 struct qed_dev_info *info = &qdev->dev_info.common;
380 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
381 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
383 DP_INFO(edev, "*********************************\n");
384 DP_INFO(edev, " DPDK version:%s\n", rte_version());
385 DP_INFO(edev, " Chip details : %s %c%d\n",
386 ECORE_IS_BB(edev) ? "BB" : "AH",
387 'A' + edev->chip_rev,
388 (int)edev->chip_metal);
389 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
390 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
391 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
392 ver_str, QEDE_PMD_VERSION);
393 DP_INFO(edev, " Driver version : %s\n", drv_ver);
394 DP_INFO(edev, " Firmware version : %s\n", ver_str);
396 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
398 (info->mfw_rev >> 24) & 0xff,
399 (info->mfw_rev >> 16) & 0xff,
400 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
401 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
402 DP_INFO(edev, " Firmware file : %s\n", fw_file);
403 DP_INFO(edev, "*********************************\n");
406 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
408 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
409 unsigned int i = 0, j = 0, qid;
410 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
411 struct qede_tx_queue *txq;
413 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
415 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
416 RTE_ETHDEV_QUEUE_STAT_CNTRS);
417 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
418 RTE_ETHDEV_QUEUE_STAT_CNTRS);
421 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
422 offsetof(struct qede_rx_queue, rcv_pkts), 0,
424 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
425 offsetof(struct qede_rx_queue, rx_hw_errors), 0,
427 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
428 offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
432 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
433 OSAL_MEMSET((((char *)
434 (qdev->fp_array[qid].rxq)) +
435 qede_rxq_xstats_strings[j].offset),
440 if (i == rxq_stat_cntrs)
447 txq = qdev->fp_array[qid].txq;
449 OSAL_MEMSET((uint64_t *)(uintptr_t)
450 (((uint64_t)(uintptr_t)(txq)) +
451 offsetof(struct qede_tx_queue, xmit_pkts)), 0,
455 if (i == txq_stat_cntrs)
461 qede_stop_vport(struct ecore_dev *edev)
463 struct ecore_hwfn *p_hwfn;
469 for_each_hwfn(edev, i) {
470 p_hwfn = &edev->hwfns[i];
471 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
473 if (rc != ECORE_SUCCESS) {
474 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
479 DP_INFO(edev, "vport stopped\n");
485 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
487 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
488 struct ecore_sp_vport_start_params params;
489 struct ecore_hwfn *p_hwfn;
493 if (qdev->vport_started)
494 qede_stop_vport(edev);
496 memset(¶ms, 0, sizeof(params));
499 /* @DPDK - Disable FW placement */
500 params.zero_placement_offset = 1;
501 for_each_hwfn(edev, i) {
502 p_hwfn = &edev->hwfns[i];
503 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
504 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
505 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
506 if (rc != ECORE_SUCCESS) {
507 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
511 ecore_reset_vport_stats(edev);
512 qdev->vport_started = true;
513 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
518 #define QEDE_NPAR_TX_SWITCHING "npar_tx_switching"
519 #define QEDE_VF_TX_SWITCHING "vf_tx_switching"
521 /* Activate or deactivate vport via vport-update */
522 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
524 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
525 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
526 struct ecore_sp_vport_update_params params;
527 struct ecore_hwfn *p_hwfn;
531 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
533 params.update_vport_active_rx_flg = 1;
534 params.update_vport_active_tx_flg = 1;
535 params.vport_active_rx_flg = flg;
536 params.vport_active_tx_flg = flg;
537 if (~qdev->enable_tx_switching & flg) {
538 params.update_tx_switching_flg = 1;
539 params.tx_switching_flg = !flg;
541 for_each_hwfn(edev, i) {
542 p_hwfn = &edev->hwfns[i];
543 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
544 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
545 ECORE_SPQ_MODE_EBLOCK, NULL);
546 if (rc != ECORE_SUCCESS) {
547 DP_ERR(edev, "Failed to update vport\n");
551 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
557 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
558 uint16_t mtu, bool enable)
560 /* Enable LRO in split mode */
561 sge_tpa_params->tpa_ipv4_en_flg = enable;
562 sge_tpa_params->tpa_ipv6_en_flg = enable;
563 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
564 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
565 /* set if tpa enable changes */
566 sge_tpa_params->update_tpa_en_flg = 1;
567 /* set if tpa parameters should be handled */
568 sge_tpa_params->update_tpa_param_flg = enable;
570 sge_tpa_params->max_buffers_per_cqe = 20;
571 /* Enable TPA in split mode. In this mode each TPA segment
572 * starts on the new BD, so there is one BD per segment.
574 sge_tpa_params->tpa_pkt_split_flg = 1;
575 sge_tpa_params->tpa_hdr_data_split_flg = 0;
576 sge_tpa_params->tpa_gro_consistent_flg = 0;
577 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
578 sge_tpa_params->tpa_max_size = 0x7FFF;
579 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
580 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
583 /* Enable/disable LRO via vport-update */
584 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
586 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
587 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
588 struct ecore_sp_vport_update_params params;
589 struct ecore_sge_tpa_params tpa_params;
590 struct ecore_hwfn *p_hwfn;
594 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
595 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
596 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
598 params.sge_tpa_params = &tpa_params;
599 for_each_hwfn(edev, i) {
600 p_hwfn = &edev->hwfns[i];
601 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
602 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
603 ECORE_SPQ_MODE_EBLOCK, NULL);
604 if (rc != ECORE_SUCCESS) {
605 DP_ERR(edev, "Failed to update LRO\n");
609 qdev->enable_lro = flg;
610 eth_dev->data->lro = flg;
612 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
617 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
619 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
620 ucast->is_rx_filter = true;
621 ucast->is_tx_filter = true;
622 /* ucast->assert_on_error = true; - For debug */
626 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
627 enum qed_filter_rx_mode_type type)
629 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
630 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
631 struct ecore_filter_accept_flags flags;
633 memset(&flags, 0, sizeof(flags));
635 flags.update_rx_mode_config = 1;
636 flags.update_tx_mode_config = 1;
637 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
638 ECORE_ACCEPT_MCAST_MATCHED |
641 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
642 ECORE_ACCEPT_MCAST_MATCHED |
645 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
646 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
648 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
649 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
651 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
652 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
653 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
654 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
655 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
656 ECORE_ACCEPT_MCAST_UNMATCHED;
659 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
660 ECORE_SPQ_MODE_CB, NULL);
664 qede_tunnel_update(struct qede_dev *qdev,
665 struct ecore_tunnel_info *tunn_info)
667 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
668 enum _ecore_status_t rc = ECORE_INVAL;
669 struct ecore_hwfn *p_hwfn;
670 struct ecore_ptt *p_ptt;
673 for_each_hwfn(edev, i) {
674 p_hwfn = &edev->hwfns[i];
676 p_ptt = ecore_ptt_acquire(p_hwfn);
678 DP_ERR(p_hwfn, "Can't acquire PTT\n");
685 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
686 tunn_info, ECORE_SPQ_MODE_CB, NULL);
688 ecore_ptt_release(p_hwfn, p_ptt);
690 if (rc != ECORE_SUCCESS)
698 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
701 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
702 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
703 enum _ecore_status_t rc = ECORE_INVAL;
704 struct ecore_tunnel_info tunn;
706 if (qdev->vxlan.enable == enable)
707 return ECORE_SUCCESS;
709 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
710 tunn.vxlan.b_update_mode = true;
711 tunn.vxlan.b_mode_enabled = enable;
712 tunn.b_update_rx_cls = true;
713 tunn.b_update_tx_cls = true;
714 tunn.vxlan.tun_cls = clss;
716 tunn.vxlan_port.b_update_port = true;
717 tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
719 rc = qede_tunnel_update(qdev, &tunn);
720 if (rc == ECORE_SUCCESS) {
721 qdev->vxlan.enable = enable;
722 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
723 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
724 enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
726 DP_ERR(edev, "Failed to update tunn_clss %u\n",
734 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
737 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
738 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
739 enum _ecore_status_t rc = ECORE_INVAL;
740 struct ecore_tunnel_info tunn;
742 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
743 tunn.l2_geneve.b_update_mode = true;
744 tunn.l2_geneve.b_mode_enabled = enable;
745 tunn.ip_geneve.b_update_mode = true;
746 tunn.ip_geneve.b_mode_enabled = enable;
747 tunn.l2_geneve.tun_cls = clss;
748 tunn.ip_geneve.tun_cls = clss;
749 tunn.b_update_rx_cls = true;
750 tunn.b_update_tx_cls = true;
752 tunn.geneve_port.b_update_port = true;
753 tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
755 rc = qede_tunnel_update(qdev, &tunn);
756 if (rc == ECORE_SUCCESS) {
757 qdev->geneve.enable = enable;
758 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
759 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
760 enable ? "enabled" : "disabled", qdev->geneve.udp_port);
762 DP_ERR(edev, "Failed to update tunn_clss %u\n",
770 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
773 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
774 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
775 enum _ecore_status_t rc = ECORE_INVAL;
776 struct ecore_tunnel_info tunn;
778 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
779 tunn.ip_gre.b_update_mode = true;
780 tunn.ip_gre.b_mode_enabled = enable;
781 tunn.ip_gre.tun_cls = clss;
782 tunn.ip_gre.tun_cls = clss;
783 tunn.b_update_rx_cls = true;
784 tunn.b_update_tx_cls = true;
786 rc = qede_tunnel_update(qdev, &tunn);
787 if (rc == ECORE_SUCCESS) {
788 qdev->ipgre.enable = enable;
789 DP_INFO(edev, "IPGRE is %s\n",
790 enable ? "enabled" : "disabled");
792 DP_ERR(edev, "Failed to update tunn_clss %u\n",
800 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
801 enum rte_eth_tunnel_type tunn_type, bool enable)
806 case RTE_TUNNEL_TYPE_VXLAN:
807 rc = qede_vxlan_enable(eth_dev, clss, enable);
809 case RTE_TUNNEL_TYPE_GENEVE:
810 rc = qede_geneve_enable(eth_dev, clss, enable);
812 case RTE_TUNNEL_TYPE_IP_IN_GRE:
813 rc = qede_ipgre_enable(eth_dev, clss, enable);
824 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
827 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
828 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
829 struct qede_ucast_entry *tmp = NULL;
830 struct qede_ucast_entry *u;
831 struct ether_addr *mac_addr;
833 mac_addr = (struct ether_addr *)ucast->mac;
835 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
836 if ((memcmp(mac_addr, &tmp->mac,
837 ETHER_ADDR_LEN) == 0) &&
838 ucast->vni == tmp->vni &&
839 ucast->vlan == tmp->vlan) {
840 DP_INFO(edev, "Unicast MAC is already added"
841 " with vlan = %u, vni = %u\n",
842 ucast->vlan, ucast->vni);
846 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
847 RTE_CACHE_LINE_SIZE);
849 DP_ERR(edev, "Did not allocate memory for ucast\n");
852 ether_addr_copy(mac_addr, &u->mac);
853 u->vlan = ucast->vlan;
855 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
858 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
859 if ((memcmp(mac_addr, &tmp->mac,
860 ETHER_ADDR_LEN) == 0) &&
861 ucast->vlan == tmp->vlan &&
862 ucast->vni == tmp->vni)
866 DP_INFO(edev, "Unicast MAC is not found\n");
869 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
877 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
878 uint32_t mc_addrs_num)
880 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
881 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
882 struct ecore_filter_mcast mcast;
883 struct qede_mcast_entry *m = NULL;
887 for (i = 0; i < mc_addrs_num; i++) {
888 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
889 RTE_CACHE_LINE_SIZE);
891 DP_ERR(edev, "Did not allocate memory for mcast\n");
894 ether_addr_copy(&mc_addrs[i], &m->mac);
895 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
897 memset(&mcast, 0, sizeof(mcast));
898 mcast.num_mc_addrs = mc_addrs_num;
899 mcast.opcode = ECORE_FILTER_ADD;
900 for (i = 0; i < mc_addrs_num; i++)
901 ether_addr_copy(&mc_addrs[i], (struct ether_addr *)
903 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
904 if (rc != ECORE_SUCCESS) {
905 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
912 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
914 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
915 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
916 struct qede_mcast_entry *tmp = NULL;
917 struct ecore_filter_mcast mcast;
921 memset(&mcast, 0, sizeof(mcast));
922 mcast.num_mc_addrs = qdev->num_mc_addr;
923 mcast.opcode = ECORE_FILTER_REMOVE;
925 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
926 ether_addr_copy(&tmp->mac, (struct ether_addr *)&mcast.mac[j]);
929 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
930 if (rc != ECORE_SUCCESS) {
931 DP_ERR(edev, "Failed to delete multicast filter\n");
935 while (!SLIST_EMPTY(&qdev->mc_list_head)) {
936 tmp = SLIST_FIRST(&qdev->mc_list_head);
937 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
939 SLIST_INIT(&qdev->mc_list_head);
944 static enum _ecore_status_t
945 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
948 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
949 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
950 enum _ecore_status_t rc = ECORE_INVAL;
952 if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
953 DP_ERR(edev, "Ucast filter table limit exceeded,"
954 " Please enable promisc mode\n");
958 rc = qede_ucast_filter(eth_dev, ucast, add);
960 rc = ecore_filter_ucast_cmd(edev, ucast,
961 ECORE_SPQ_MODE_CB, NULL);
962 if (rc != ECORE_SUCCESS)
963 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
970 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
971 __rte_unused uint32_t index, __rte_unused uint32_t pool)
973 struct ecore_filter_ucast ucast;
976 if (!is_valid_assigned_ether_addr(mac_addr))
979 qede_set_ucast_cmn_params(&ucast);
980 ucast.opcode = ECORE_FILTER_ADD;
981 ucast.type = ECORE_FILTER_MAC;
982 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
983 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
988 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
990 struct qede_dev *qdev = eth_dev->data->dev_private;
991 struct ecore_dev *edev = &qdev->edev;
992 struct ecore_filter_ucast ucast;
994 PMD_INIT_FUNC_TRACE(edev);
996 if (index >= qdev->dev_info.num_mac_filters) {
997 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
998 index, qdev->dev_info.num_mac_filters);
1002 if (!is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index]))
1005 qede_set_ucast_cmn_params(&ucast);
1006 ucast.opcode = ECORE_FILTER_REMOVE;
1007 ucast.type = ECORE_FILTER_MAC;
1009 /* Use the index maintained by rte */
1010 ether_addr_copy(ð_dev->data->mac_addrs[index],
1011 (struct ether_addr *)&ucast.mac);
1013 qede_mac_int_ops(eth_dev, &ucast, false);
1017 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1019 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1020 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1022 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1023 mac_addr->addr_bytes)) {
1024 DP_ERR(edev, "Setting MAC address is not allowed\n");
1028 qede_mac_addr_remove(eth_dev, 0);
1030 return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1033 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1035 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1036 struct ecore_sp_vport_update_params params;
1037 struct ecore_hwfn *p_hwfn;
1041 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1042 params.vport_id = 0;
1043 params.update_accept_any_vlan_flg = 1;
1044 params.accept_any_vlan = flg;
1045 for_each_hwfn(edev, i) {
1046 p_hwfn = &edev->hwfns[i];
1047 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1048 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1049 ECORE_SPQ_MODE_EBLOCK, NULL);
1050 if (rc != ECORE_SUCCESS) {
1051 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1056 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1059 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1061 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1062 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1063 struct ecore_sp_vport_update_params params;
1064 struct ecore_hwfn *p_hwfn;
1068 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
1069 params.vport_id = 0;
1070 params.update_inner_vlan_removal_flg = 1;
1071 params.inner_vlan_removal_flg = flg;
1072 for_each_hwfn(edev, i) {
1073 p_hwfn = &edev->hwfns[i];
1074 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1075 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
1076 ECORE_SPQ_MODE_EBLOCK, NULL);
1077 if (rc != ECORE_SUCCESS) {
1078 DP_ERR(edev, "Failed to update vport\n");
1083 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1087 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1088 uint16_t vlan_id, int on)
1090 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1091 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1092 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1093 struct qede_vlan_entry *tmp = NULL;
1094 struct qede_vlan_entry *vlan;
1095 struct ecore_filter_ucast ucast;
1099 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1100 DP_ERR(edev, "Reached max VLAN filter limit"
1101 " enabling accept_any_vlan\n");
1102 qede_config_accept_any_vlan(qdev, true);
1106 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1107 if (tmp->vid == vlan_id) {
1108 DP_INFO(edev, "VLAN %u already configured\n",
1114 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1115 RTE_CACHE_LINE_SIZE);
1118 DP_ERR(edev, "Did not allocate memory for VLAN\n");
1122 qede_set_ucast_cmn_params(&ucast);
1123 ucast.opcode = ECORE_FILTER_ADD;
1124 ucast.type = ECORE_FILTER_VLAN;
1125 ucast.vlan = vlan_id;
1126 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1129 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1133 vlan->vid = vlan_id;
1134 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1135 qdev->configured_vlans++;
1136 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1137 vlan_id, qdev->configured_vlans);
1140 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1141 if (tmp->vid == vlan_id)
1146 if (qdev->configured_vlans == 0) {
1148 "No VLAN filters configured yet\n");
1152 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1156 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1158 qede_set_ucast_cmn_params(&ucast);
1159 ucast.opcode = ECORE_FILTER_REMOVE;
1160 ucast.type = ECORE_FILTER_VLAN;
1161 ucast.vlan = vlan_id;
1162 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1165 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1168 qdev->configured_vlans--;
1169 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1170 vlan_id, qdev->configured_vlans);
1177 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1179 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1180 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1181 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1183 if (mask & ETH_VLAN_STRIP_MASK) {
1184 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1185 (void)qede_vlan_stripping(eth_dev, 1);
1187 (void)qede_vlan_stripping(eth_dev, 0);
1190 if (mask & ETH_VLAN_FILTER_MASK) {
1191 /* VLAN filtering kicks in when a VLAN is added */
1192 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1193 qede_vlan_filter_set(eth_dev, 0, 1);
1195 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1197 " Please remove existing VLAN filters"
1198 " before disabling VLAN filtering\n");
1199 /* Signal app that VLAN filtering is still
1202 eth_dev->data->dev_conf.rxmode.offloads |=
1203 DEV_RX_OFFLOAD_VLAN_FILTER;
1205 qede_vlan_filter_set(eth_dev, 0, 0);
1210 if (mask & ETH_VLAN_EXTEND_MASK)
1211 DP_ERR(edev, "Extend VLAN not supported\n");
1213 qdev->vlan_offload_mask = mask;
1215 DP_INFO(edev, "VLAN offload mask %d\n", mask);
1220 static void qede_prandom_bytes(uint32_t *buff)
1224 srand((unsigned int)time(NULL));
1225 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1229 int qede_config_rss(struct rte_eth_dev *eth_dev)
1231 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1232 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1233 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1234 struct rte_eth_rss_reta_entry64 reta_conf[2];
1235 struct rte_eth_rss_conf rss_conf;
1236 uint32_t i, id, pos, q;
1238 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1239 if (!rss_conf.rss_key) {
1240 DP_INFO(edev, "Applying driver default key\n");
1241 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1242 qede_prandom_bytes(&def_rss_key[0]);
1243 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1246 /* Configure RSS hash */
1247 if (qede_rss_hash_update(eth_dev, &rss_conf))
1250 /* Configure default RETA */
1251 memset(reta_conf, 0, sizeof(reta_conf));
1252 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1253 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1255 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1256 id = i / RTE_RETA_GROUP_SIZE;
1257 pos = i % RTE_RETA_GROUP_SIZE;
1258 q = i % QEDE_RSS_COUNT(qdev);
1259 reta_conf[id].reta[pos] = q;
1261 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1262 ECORE_RSS_IND_TABLE_SIZE))
1268 static void qede_fastpath_start(struct ecore_dev *edev)
1270 struct ecore_hwfn *p_hwfn;
1273 for_each_hwfn(edev, i) {
1274 p_hwfn = &edev->hwfns[i];
1275 ecore_hw_start_fastpath(p_hwfn);
1279 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1281 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1282 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1283 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1285 PMD_INIT_FUNC_TRACE(edev);
1287 /* Update MTU only if it has changed */
1288 if (eth_dev->data->mtu != qdev->mtu) {
1289 if (qede_update_mtu(eth_dev, qdev->mtu))
1293 /* Configure TPA parameters */
1294 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1295 if (qede_enable_tpa(eth_dev, true))
1297 /* Enable scatter mode for LRO */
1298 if (!eth_dev->data->scattered_rx)
1299 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1303 if (qede_start_queues(eth_dev))
1307 qede_reset_queue_stats(qdev, true);
1309 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1310 * enabling RSS. Hence RSS configuration is deferred upto this point.
1311 * Also, we would like to retain similar behavior in PF case, so we
1312 * don't do PF/VF specific check here.
1314 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1315 if (qede_config_rss(eth_dev))
1319 if (qede_activate_vport(eth_dev, true))
1322 /* Update link status */
1323 qede_link_update(eth_dev, 0);
1325 /* Start/resume traffic */
1326 qede_fastpath_start(edev);
1328 DP_INFO(edev, "Device started\n");
1332 DP_ERR(edev, "Device start fails\n");
1333 return -1; /* common error code is < 0 */
1336 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1338 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1339 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1341 PMD_INIT_FUNC_TRACE(edev);
1344 if (qede_activate_vport(eth_dev, false))
1347 if (qdev->enable_lro)
1348 qede_enable_tpa(eth_dev, false);
1351 qede_stop_queues(eth_dev);
1353 /* Disable traffic */
1354 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1356 DP_INFO(edev, "Device is stopped\n");
1359 const char *valid_args[] = {
1360 QEDE_NPAR_TX_SWITCHING,
1361 QEDE_VF_TX_SWITCHING,
1365 static int qede_args_check(const char *key, const char *val, void *opaque)
1369 struct rte_eth_dev *eth_dev = opaque;
1370 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1371 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1374 tmp = strtoul(val, NULL, 0);
1376 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1380 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1381 ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1382 qdev->enable_tx_switching = !!tmp;
1383 DP_INFO(edev, "Disabling %s tx-switching\n",
1384 strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1391 static int qede_args(struct rte_eth_dev *eth_dev)
1393 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1394 struct rte_kvargs *kvlist;
1395 struct rte_devargs *devargs;
1399 devargs = pci_dev->device.devargs;
1401 return 0; /* return success */
1403 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1407 /* Process parameters. */
1408 for (i = 0; (valid_args[i] != NULL); ++i) {
1409 if (rte_kvargs_count(kvlist, valid_args[i])) {
1410 ret = rte_kvargs_process(kvlist, valid_args[i],
1411 qede_args_check, eth_dev);
1412 if (ret != ECORE_SUCCESS) {
1413 rte_kvargs_free(kvlist);
1418 rte_kvargs_free(kvlist);
1423 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1425 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1426 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1427 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1430 PMD_INIT_FUNC_TRACE(edev);
1432 /* Check requirements for 100G mode */
1433 if (ECORE_IS_CMT(edev)) {
1434 if (eth_dev->data->nb_rx_queues < 2 ||
1435 eth_dev->data->nb_tx_queues < 2) {
1436 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1440 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1441 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1443 "100G mode needs even no. of RX/TX queues\n");
1448 /* We need to have min 1 RX queue.There is no min check in
1449 * rte_eth_dev_configure(), so we are checking it here.
1451 if (eth_dev->data->nb_rx_queues == 0) {
1452 DP_ERR(edev, "Minimum one RX queue is required\n");
1456 /* Enable Tx switching by default */
1457 qdev->enable_tx_switching = 1;
1459 /* Parse devargs and fix up rxmode */
1460 if (qede_args(eth_dev))
1461 DP_NOTICE(edev, false,
1462 "Invalid devargs supplied, requested change will not take effect\n");
1464 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1465 rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1466 DP_ERR(edev, "Unsupported multi-queue mode\n");
1469 /* Flow director mode check */
1470 if (qede_check_fdir_support(eth_dev))
1473 qede_dealloc_fp_resc(eth_dev);
1474 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1475 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1476 if (qede_alloc_fp_resc(qdev))
1479 /* If jumbo enabled adjust MTU */
1480 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1481 eth_dev->data->mtu =
1482 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1483 ETHER_HDR_LEN - ETHER_CRC_LEN;
1485 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1486 eth_dev->data->scattered_rx = 1;
1488 if (qede_start_vport(qdev, eth_dev->data->mtu))
1491 qdev->mtu = eth_dev->data->mtu;
1493 /* Enable VLAN offloads by default */
1494 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1495 ETH_VLAN_FILTER_MASK);
1499 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1500 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1505 /* Info about HW descriptor ring limitations */
1506 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1507 .nb_max = 0x8000, /* 32K */
1509 .nb_align = 128 /* lowest common multiple */
1512 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1513 .nb_max = 0x8000, /* 32K */
1516 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1517 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1521 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1522 struct rte_eth_dev_info *dev_info)
1524 struct qede_dev *qdev = eth_dev->data->dev_private;
1525 struct ecore_dev *edev = &qdev->edev;
1526 struct qed_link_output link;
1527 uint32_t speed_cap = 0;
1529 PMD_INIT_FUNC_TRACE(edev);
1531 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1532 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1533 dev_info->rx_desc_lim = qede_rx_desc_lim;
1534 dev_info->tx_desc_lim = qede_tx_desc_lim;
1537 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1538 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1540 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1541 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1542 dev_info->max_tx_queues = dev_info->max_rx_queues;
1544 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1545 dev_info->max_vfs = 0;
1546 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1547 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1548 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1549 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1550 DEV_RX_OFFLOAD_UDP_CKSUM |
1551 DEV_RX_OFFLOAD_TCP_CKSUM |
1552 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1553 DEV_RX_OFFLOAD_TCP_LRO |
1554 DEV_RX_OFFLOAD_CRC_STRIP |
1555 DEV_RX_OFFLOAD_KEEP_CRC |
1556 DEV_RX_OFFLOAD_SCATTER |
1557 DEV_RX_OFFLOAD_JUMBO_FRAME |
1558 DEV_RX_OFFLOAD_VLAN_FILTER |
1559 DEV_RX_OFFLOAD_VLAN_STRIP);
1560 dev_info->rx_queue_offload_capa = 0;
1562 /* TX offloads are on a per-packet basis, so it is applicable
1563 * to both at port and queue levels.
1565 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1566 DEV_TX_OFFLOAD_IPV4_CKSUM |
1567 DEV_TX_OFFLOAD_UDP_CKSUM |
1568 DEV_TX_OFFLOAD_TCP_CKSUM |
1569 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1570 DEV_TX_OFFLOAD_MULTI_SEGS |
1571 DEV_TX_OFFLOAD_TCP_TSO |
1572 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1573 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1574 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1576 dev_info->default_txconf = (struct rte_eth_txconf) {
1577 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1580 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1581 /* Packets are always dropped if no descriptors are available */
1586 memset(&link, 0, sizeof(struct qed_link_output));
1587 qdev->ops->common->get_link(edev, &link);
1588 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1589 speed_cap |= ETH_LINK_SPEED_1G;
1590 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1591 speed_cap |= ETH_LINK_SPEED_10G;
1592 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1593 speed_cap |= ETH_LINK_SPEED_25G;
1594 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1595 speed_cap |= ETH_LINK_SPEED_40G;
1596 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1597 speed_cap |= ETH_LINK_SPEED_50G;
1598 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1599 speed_cap |= ETH_LINK_SPEED_100G;
1600 dev_info->speed_capa = speed_cap;
1603 /* return 0 means link status changed, -1 means not changed */
1605 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1607 struct qede_dev *qdev = eth_dev->data->dev_private;
1608 struct ecore_dev *edev = &qdev->edev;
1609 struct qed_link_output q_link;
1610 struct rte_eth_link link;
1611 uint16_t link_duplex;
1613 memset(&q_link, 0, sizeof(q_link));
1614 memset(&link, 0, sizeof(link));
1616 qdev->ops->common->get_link(edev, &q_link);
1619 link.link_speed = q_link.speed;
1622 switch (q_link.duplex) {
1623 case QEDE_DUPLEX_HALF:
1624 link_duplex = ETH_LINK_HALF_DUPLEX;
1626 case QEDE_DUPLEX_FULL:
1627 link_duplex = ETH_LINK_FULL_DUPLEX;
1629 case QEDE_DUPLEX_UNKNOWN:
1633 link.link_duplex = link_duplex;
1636 link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1639 link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1640 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1642 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1643 link.link_speed, link.link_duplex,
1644 link.link_autoneg, link.link_status);
1646 return rte_eth_linkstatus_set(eth_dev, &link);
1649 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1651 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1652 struct qede_dev *qdev = eth_dev->data->dev_private;
1653 struct ecore_dev *edev = &qdev->edev;
1655 PMD_INIT_FUNC_TRACE(edev);
1658 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1660 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1661 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1663 qed_configure_filter_rx_mode(eth_dev, type);
1666 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1668 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1669 struct qede_dev *qdev = eth_dev->data->dev_private;
1670 struct ecore_dev *edev = &qdev->edev;
1672 PMD_INIT_FUNC_TRACE(edev);
1675 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1676 qed_configure_filter_rx_mode(eth_dev,
1677 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1679 qed_configure_filter_rx_mode(eth_dev,
1680 QED_FILTER_RX_MODE_TYPE_REGULAR);
1683 static void qede_poll_sp_sb_cb(void *param)
1685 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1686 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1687 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1690 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1691 qede_interrupt_action(&edev->hwfns[1]);
1693 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1697 DP_ERR(edev, "Unable to start periodic"
1698 " timer rc %d\n", rc);
1699 assert(false && "Unable to start periodic timer");
1703 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1705 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1706 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1707 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1709 PMD_INIT_FUNC_TRACE(edev);
1711 /* dev_stop() shall cleanup fp resources in hw but without releasing
1712 * dma memories and sw structures so that dev_start() can be called
1713 * by the app without reconfiguration. However, in dev_close() we
1714 * can release all the resources and device can be brought up newly
1716 if (eth_dev->data->dev_started)
1717 qede_dev_stop(eth_dev);
1719 qede_stop_vport(edev);
1720 qdev->vport_started = false;
1721 qede_fdir_dealloc_resc(eth_dev);
1722 qede_dealloc_fp_resc(eth_dev);
1724 eth_dev->data->nb_rx_queues = 0;
1725 eth_dev->data->nb_tx_queues = 0;
1727 /* Bring the link down */
1728 qede_dev_set_link_state(eth_dev, false);
1729 qdev->ops->common->slowpath_stop(edev);
1730 qdev->ops->common->remove(edev);
1731 rte_intr_disable(&pci_dev->intr_handle);
1733 switch (pci_dev->intr_handle.type) {
1734 case RTE_INTR_HANDLE_UIO_INTX:
1735 case RTE_INTR_HANDLE_VFIO_LEGACY:
1736 rte_intr_callback_unregister(&pci_dev->intr_handle,
1737 qede_interrupt_handler_intx,
1741 rte_intr_callback_unregister(&pci_dev->intr_handle,
1742 qede_interrupt_handler,
1746 if (ECORE_IS_CMT(edev))
1747 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1751 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1753 struct qede_dev *qdev = eth_dev->data->dev_private;
1754 struct ecore_dev *edev = &qdev->edev;
1755 struct ecore_eth_stats stats;
1756 unsigned int i = 0, j = 0, qid;
1757 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1758 struct qede_tx_queue *txq;
1760 ecore_get_vport_stats(edev, &stats);
1763 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1764 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1766 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1767 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1769 eth_stats->ierrors = stats.common.rx_crc_errors +
1770 stats.common.rx_align_errors +
1771 stats.common.rx_carrier_errors +
1772 stats.common.rx_oversize_packets +
1773 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1775 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1777 eth_stats->imissed = stats.common.mftag_filter_discards +
1778 stats.common.mac_filter_discards +
1779 stats.common.no_buff_discards +
1780 stats.common.brb_truncates + stats.common.brb_discards;
1783 eth_stats->opackets = stats.common.tx_ucast_pkts +
1784 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1786 eth_stats->obytes = stats.common.tx_ucast_bytes +
1787 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1789 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1792 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1793 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1794 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1795 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1796 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1797 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1798 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1799 "Not all the queue stats will be displayed. Set"
1800 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1801 " appropriately and retry.\n");
1804 eth_stats->q_ipackets[i] =
1806 ((char *)(qdev->fp_array[qid].rxq)) +
1807 offsetof(struct qede_rx_queue,
1809 eth_stats->q_errors[i] =
1811 ((char *)(qdev->fp_array[qid].rxq)) +
1812 offsetof(struct qede_rx_queue,
1815 ((char *)(qdev->fp_array[qid].rxq)) +
1816 offsetof(struct qede_rx_queue,
1819 if (i == rxq_stat_cntrs)
1824 txq = qdev->fp_array[qid].txq;
1825 eth_stats->q_opackets[j] =
1826 *((uint64_t *)(uintptr_t)
1827 (((uint64_t)(uintptr_t)(txq)) +
1828 offsetof(struct qede_tx_queue,
1831 if (j == txq_stat_cntrs)
1839 qede_get_xstats_count(struct qede_dev *qdev) {
1840 if (ECORE_IS_BB(&qdev->edev))
1841 return RTE_DIM(qede_xstats_strings) +
1842 RTE_DIM(qede_bb_xstats_strings) +
1843 (RTE_DIM(qede_rxq_xstats_strings) *
1844 RTE_MIN(QEDE_RSS_COUNT(qdev),
1845 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1847 return RTE_DIM(qede_xstats_strings) +
1848 RTE_DIM(qede_ah_xstats_strings) +
1849 (RTE_DIM(qede_rxq_xstats_strings) *
1850 RTE_MIN(QEDE_RSS_COUNT(qdev),
1851 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1855 qede_get_xstats_names(struct rte_eth_dev *dev,
1856 struct rte_eth_xstat_name *xstats_names,
1857 __rte_unused unsigned int limit)
1859 struct qede_dev *qdev = dev->data->dev_private;
1860 struct ecore_dev *edev = &qdev->edev;
1861 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1862 unsigned int i, qid, stat_idx = 0;
1863 unsigned int rxq_stat_cntrs;
1865 if (xstats_names != NULL) {
1866 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1867 snprintf(xstats_names[stat_idx].name,
1868 sizeof(xstats_names[stat_idx].name),
1870 qede_xstats_strings[i].name);
1874 if (ECORE_IS_BB(edev)) {
1875 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1876 snprintf(xstats_names[stat_idx].name,
1877 sizeof(xstats_names[stat_idx].name),
1879 qede_bb_xstats_strings[i].name);
1883 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1884 snprintf(xstats_names[stat_idx].name,
1885 sizeof(xstats_names[stat_idx].name),
1887 qede_ah_xstats_strings[i].name);
1892 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1893 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1894 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1895 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1896 snprintf(xstats_names[stat_idx].name,
1897 sizeof(xstats_names[stat_idx].name),
1899 qede_rxq_xstats_strings[i].name, qid,
1900 qede_rxq_xstats_strings[i].name + 4);
1910 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1913 struct qede_dev *qdev = dev->data->dev_private;
1914 struct ecore_dev *edev = &qdev->edev;
1915 struct ecore_eth_stats stats;
1916 const unsigned int num = qede_get_xstats_count(qdev);
1917 unsigned int i, qid, stat_idx = 0;
1918 unsigned int rxq_stat_cntrs;
1923 ecore_get_vport_stats(edev, &stats);
1925 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1926 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1927 qede_xstats_strings[i].offset);
1928 xstats[stat_idx].id = stat_idx;
1932 if (ECORE_IS_BB(edev)) {
1933 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1934 xstats[stat_idx].value =
1935 *(uint64_t *)(((char *)&stats) +
1936 qede_bb_xstats_strings[i].offset);
1937 xstats[stat_idx].id = stat_idx;
1941 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1942 xstats[stat_idx].value =
1943 *(uint64_t *)(((char *)&stats) +
1944 qede_ah_xstats_strings[i].offset);
1945 xstats[stat_idx].id = stat_idx;
1950 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1951 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1952 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1954 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1955 xstats[stat_idx].value = *(uint64_t *)(
1956 ((char *)(qdev->fp_array[qid].rxq)) +
1957 qede_rxq_xstats_strings[i].offset);
1958 xstats[stat_idx].id = stat_idx;
1968 qede_reset_xstats(struct rte_eth_dev *dev)
1970 struct qede_dev *qdev = dev->data->dev_private;
1971 struct ecore_dev *edev = &qdev->edev;
1973 ecore_reset_vport_stats(edev);
1974 qede_reset_queue_stats(qdev, true);
1977 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1979 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1980 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1981 struct qed_link_params link_params;
1984 DP_INFO(edev, "setting link state %d\n", link_up);
1985 memset(&link_params, 0, sizeof(link_params));
1986 link_params.link_up = link_up;
1987 rc = qdev->ops->common->set_link(edev, &link_params);
1988 if (rc != ECORE_SUCCESS)
1989 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1994 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1996 return qede_dev_set_link_state(eth_dev, true);
1999 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
2001 return qede_dev_set_link_state(eth_dev, false);
2004 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
2006 struct qede_dev *qdev = eth_dev->data->dev_private;
2007 struct ecore_dev *edev = &qdev->edev;
2009 ecore_reset_vport_stats(edev);
2010 qede_reset_queue_stats(qdev, false);
2013 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
2015 enum qed_filter_rx_mode_type type =
2016 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
2018 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2019 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
2021 qed_configure_filter_rx_mode(eth_dev, type);
2024 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
2026 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2027 qed_configure_filter_rx_mode(eth_dev,
2028 QED_FILTER_RX_MODE_TYPE_PROMISC);
2030 qed_configure_filter_rx_mode(eth_dev,
2031 QED_FILTER_RX_MODE_TYPE_REGULAR);
2035 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
2036 uint32_t mc_addrs_num)
2038 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2039 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2042 if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
2043 DP_ERR(edev, "Reached max multicast filters limit,"
2044 "Please enable multicast promisc mode\n");
2048 for (i = 0; i < mc_addrs_num; i++) {
2049 if (!is_multicast_ether_addr(&mc_addrs[i])) {
2050 DP_ERR(edev, "Not a valid multicast MAC\n");
2055 /* Flush all existing entries */
2056 if (qede_del_mcast_filters(eth_dev))
2059 /* Set new mcast list */
2060 return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
2063 /* Update MTU via vport-update without doing port restart.
2064 * The vport must be deactivated before calling this API.
2066 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
2068 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2069 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2070 struct ecore_hwfn *p_hwfn;
2075 struct ecore_sp_vport_update_params params;
2077 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
2078 params.vport_id = 0;
2080 params.vport_id = 0;
2081 for_each_hwfn(edev, i) {
2082 p_hwfn = &edev->hwfns[i];
2083 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2084 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
2085 ECORE_SPQ_MODE_EBLOCK, NULL);
2086 if (rc != ECORE_SUCCESS)
2090 for_each_hwfn(edev, i) {
2091 p_hwfn = &edev->hwfns[i];
2092 rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
2093 if (rc == ECORE_INVAL) {
2094 DP_INFO(edev, "VF MTU Update TLV not supported\n");
2095 /* Recreate vport */
2096 rc = qede_start_vport(qdev, mtu);
2097 if (rc != ECORE_SUCCESS)
2100 /* Restore config lost due to vport stop */
2101 if (eth_dev->data->promiscuous)
2102 qede_promiscuous_enable(eth_dev);
2104 qede_promiscuous_disable(eth_dev);
2106 if (eth_dev->data->all_multicast)
2107 qede_allmulticast_enable(eth_dev);
2109 qede_allmulticast_disable(eth_dev);
2111 qede_vlan_offload_set(eth_dev,
2112 qdev->vlan_offload_mask);
2113 } else if (rc != ECORE_SUCCESS) {
2118 DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
2123 DP_ERR(edev, "Failed to update MTU\n");
2127 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2128 struct rte_eth_fc_conf *fc_conf)
2130 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2131 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2132 struct qed_link_output current_link;
2133 struct qed_link_params params;
2135 memset(¤t_link, 0, sizeof(current_link));
2136 qdev->ops->common->get_link(edev, ¤t_link);
2138 memset(¶ms, 0, sizeof(params));
2139 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2140 if (fc_conf->autoneg) {
2141 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2142 DP_ERR(edev, "Autoneg not supported\n");
2145 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2148 /* Pause is assumed to be supported (SUPPORTED_Pause) */
2149 if (fc_conf->mode == RTE_FC_FULL)
2150 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2151 QED_LINK_PAUSE_RX_ENABLE);
2152 if (fc_conf->mode == RTE_FC_TX_PAUSE)
2153 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2154 if (fc_conf->mode == RTE_FC_RX_PAUSE)
2155 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2157 params.link_up = true;
2158 (void)qdev->ops->common->set_link(edev, ¶ms);
2163 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2164 struct rte_eth_fc_conf *fc_conf)
2166 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2167 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2168 struct qed_link_output current_link;
2170 memset(¤t_link, 0, sizeof(current_link));
2171 qdev->ops->common->get_link(edev, ¤t_link);
2173 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2174 fc_conf->autoneg = true;
2176 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2177 QED_LINK_PAUSE_TX_ENABLE))
2178 fc_conf->mode = RTE_FC_FULL;
2179 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2180 fc_conf->mode = RTE_FC_RX_PAUSE;
2181 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2182 fc_conf->mode = RTE_FC_TX_PAUSE;
2184 fc_conf->mode = RTE_FC_NONE;
2189 static const uint32_t *
2190 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2192 static const uint32_t ptypes[] = {
2194 RTE_PTYPE_L2_ETHER_VLAN,
2199 RTE_PTYPE_TUNNEL_VXLAN,
2201 RTE_PTYPE_TUNNEL_GENEVE,
2202 RTE_PTYPE_TUNNEL_GRE,
2204 RTE_PTYPE_INNER_L2_ETHER,
2205 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2206 RTE_PTYPE_INNER_L3_IPV4,
2207 RTE_PTYPE_INNER_L3_IPV6,
2208 RTE_PTYPE_INNER_L4_TCP,
2209 RTE_PTYPE_INNER_L4_UDP,
2210 RTE_PTYPE_INNER_L4_FRAG,
2214 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2220 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2223 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
2224 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
2225 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
2226 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
2227 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
2228 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
2229 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
2230 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
2233 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2234 struct rte_eth_rss_conf *rss_conf)
2236 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2237 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2238 struct ecore_sp_vport_update_params vport_update_params;
2239 struct ecore_rss_params rss_params;
2240 struct ecore_hwfn *p_hwfn;
2241 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2242 uint64_t hf = rss_conf->rss_hf;
2243 uint8_t len = rss_conf->rss_key_len;
2248 memset(&vport_update_params, 0, sizeof(vport_update_params));
2249 memset(&rss_params, 0, sizeof(rss_params));
2251 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2252 (unsigned long)hf, len, key);
2256 DP_INFO(edev, "Enabling rss\n");
2259 qede_init_rss_caps(&rss_params.rss_caps, hf);
2260 rss_params.update_rss_capabilities = 1;
2264 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2265 DP_ERR(edev, "RSS key length exceeds limit\n");
2268 DP_INFO(edev, "Applying user supplied hash key\n");
2269 rss_params.update_rss_key = 1;
2270 memcpy(&rss_params.rss_key, key, len);
2272 rss_params.rss_enable = 1;
2275 rss_params.update_rss_config = 1;
2276 /* tbl_size has to be set with capabilities */
2277 rss_params.rss_table_size_log = 7;
2278 vport_update_params.vport_id = 0;
2279 /* pass the L2 handles instead of qids */
2280 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2281 idx = i % QEDE_RSS_COUNT(qdev);
2282 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2284 vport_update_params.rss_params = &rss_params;
2286 for_each_hwfn(edev, i) {
2287 p_hwfn = &edev->hwfns[i];
2288 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2289 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2290 ECORE_SPQ_MODE_EBLOCK, NULL);
2292 DP_ERR(edev, "vport-update for RSS failed\n");
2296 qdev->rss_enable = rss_params.rss_enable;
2298 /* Update local structure for hash query */
2299 qdev->rss_conf.rss_hf = hf;
2300 qdev->rss_conf.rss_key_len = len;
2301 if (qdev->rss_enable) {
2302 if (qdev->rss_conf.rss_key == NULL) {
2303 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2304 if (qdev->rss_conf.rss_key == NULL) {
2305 DP_ERR(edev, "No memory to store RSS key\n");
2310 DP_INFO(edev, "Storing RSS key\n");
2311 memcpy(qdev->rss_conf.rss_key, key, len);
2313 } else if (!qdev->rss_enable && len == 0) {
2314 if (qdev->rss_conf.rss_key) {
2315 free(qdev->rss_conf.rss_key);
2316 qdev->rss_conf.rss_key = NULL;
2317 DP_INFO(edev, "Free RSS key\n");
2324 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2325 struct rte_eth_rss_conf *rss_conf)
2327 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2329 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2330 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2332 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2333 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2334 rss_conf->rss_key_len);
2338 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2339 struct ecore_rss_params *rss)
2342 bool rss_mode = 1; /* enable */
2343 struct ecore_queue_cid *cid;
2344 struct ecore_rss_params *t_rss;
2346 /* In regular scenario, we'd simply need to take input handlers.
2347 * But in CMT, we'd have to split the handlers according to the
2348 * engine they were configured on. We'd then have to understand
2349 * whether RSS is really required, since 2-queues on CMT doesn't
2353 /* CMT should be round-robin */
2354 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2355 cid = rss->rss_ind_table[i];
2357 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2362 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2366 t_rss->update_rss_ind_table = 1;
2367 t_rss->rss_table_size_log = 7;
2368 t_rss->update_rss_config = 1;
2370 /* Make sure RSS is actually required */
2371 for_each_hwfn(edev, fn) {
2372 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2374 if (rss[fn].rss_ind_table[i] !=
2375 rss[fn].rss_ind_table[0])
2379 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2381 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2388 t_rss->rss_enable = rss_mode;
2393 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2394 struct rte_eth_rss_reta_entry64 *reta_conf,
2397 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2398 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2399 struct ecore_sp_vport_update_params vport_update_params;
2400 struct ecore_rss_params *params;
2401 struct ecore_hwfn *p_hwfn;
2402 uint16_t i, idx, shift;
2406 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2407 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2412 memset(&vport_update_params, 0, sizeof(vport_update_params));
2413 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2414 RTE_CACHE_LINE_SIZE);
2415 if (params == NULL) {
2416 DP_ERR(edev, "failed to allocate memory\n");
2420 for (i = 0; i < reta_size; i++) {
2421 idx = i / RTE_RETA_GROUP_SIZE;
2422 shift = i % RTE_RETA_GROUP_SIZE;
2423 if (reta_conf[idx].mask & (1ULL << shift)) {
2424 entry = reta_conf[idx].reta[shift];
2425 /* Pass rxq handles to ecore */
2426 params->rss_ind_table[i] =
2427 qdev->fp_array[entry].rxq->handle;
2428 /* Update the local copy for RETA query command */
2429 qdev->rss_ind_table[i] = entry;
2433 params->update_rss_ind_table = 1;
2434 params->rss_table_size_log = 7;
2435 params->update_rss_config = 1;
2437 /* Fix up RETA for CMT mode device */
2438 if (ECORE_IS_CMT(edev))
2439 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2441 vport_update_params.vport_id = 0;
2442 /* Use the current value of rss_enable */
2443 params->rss_enable = qdev->rss_enable;
2444 vport_update_params.rss_params = params;
2446 for_each_hwfn(edev, i) {
2447 p_hwfn = &edev->hwfns[i];
2448 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2449 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2450 ECORE_SPQ_MODE_EBLOCK, NULL);
2452 DP_ERR(edev, "vport-update for RSS failed\n");
2462 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2463 struct rte_eth_rss_reta_entry64 *reta_conf,
2466 struct qede_dev *qdev = eth_dev->data->dev_private;
2467 struct ecore_dev *edev = &qdev->edev;
2468 uint16_t i, idx, shift;
2471 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2472 DP_ERR(edev, "reta_size %d is not supported\n",
2477 for (i = 0; i < reta_size; i++) {
2478 idx = i / RTE_RETA_GROUP_SIZE;
2479 shift = i % RTE_RETA_GROUP_SIZE;
2480 if (reta_conf[idx].mask & (1ULL << shift)) {
2481 entry = qdev->rss_ind_table[i];
2482 reta_conf[idx].reta[shift] = entry;
2491 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2493 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2494 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2495 struct rte_eth_dev_info dev_info = {0};
2496 struct qede_fastpath *fp;
2497 uint32_t max_rx_pkt_len;
2498 uint32_t frame_size;
2499 uint16_t rx_buf_size;
2501 bool restart = false;
2504 PMD_INIT_FUNC_TRACE(edev);
2505 qede_dev_info_get(dev, &dev_info);
2506 max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2507 frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2508 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2509 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2510 mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2511 ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2514 if (!dev->data->scattered_rx &&
2515 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2516 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2517 dev->data->min_rx_buf_size);
2520 /* Temporarily replace I/O functions with dummy ones. It cannot
2521 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2523 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2524 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2525 if (dev->data->dev_started) {
2526 dev->data->dev_started = 0;
2533 /* Fix up RX buf size for all queues of the port */
2535 fp = &qdev->fp_array[i];
2536 if (fp->rxq != NULL) {
2537 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2538 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2539 if (dev->data->scattered_rx)
2540 rx_buf_size = bufsz + ETHER_HDR_LEN +
2541 ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2543 rx_buf_size = frame_size;
2544 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2545 fp->rxq->rx_buf_size = rx_buf_size;
2546 DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2549 if (max_rx_pkt_len > ETHER_MAX_LEN)
2550 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2552 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2554 if (!dev->data->dev_started && restart) {
2555 qede_dev_start(dev);
2556 dev->data->dev_started = 1;
2559 /* update max frame size */
2560 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2562 dev->rx_pkt_burst = qede_recv_pkts;
2563 dev->tx_pkt_burst = qede_xmit_pkts;
2569 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2570 struct rte_eth_udp_tunnel *tunnel_udp)
2572 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2573 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2574 struct ecore_tunnel_info tunn; /* @DPDK */
2578 PMD_INIT_FUNC_TRACE(edev);
2580 memset(&tunn, 0, sizeof(tunn));
2582 switch (tunnel_udp->prot_type) {
2583 case RTE_TUNNEL_TYPE_VXLAN:
2584 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2585 DP_ERR(edev, "UDP port %u doesn't exist\n",
2586 tunnel_udp->udp_port);
2591 tunn.vxlan_port.b_update_port = true;
2592 tunn.vxlan_port.port = udp_port;
2594 rc = qede_tunnel_update(qdev, &tunn);
2595 if (rc != ECORE_SUCCESS) {
2596 DP_ERR(edev, "Unable to config UDP port %u\n",
2597 tunn.vxlan_port.port);
2601 qdev->vxlan.udp_port = udp_port;
2602 /* If the request is to delete UDP port and if the number of
2603 * VXLAN filters have reached 0 then VxLAN offload can be be
2606 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2607 return qede_vxlan_enable(eth_dev,
2608 ECORE_TUNN_CLSS_MAC_VLAN, false);
2611 case RTE_TUNNEL_TYPE_GENEVE:
2612 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2613 DP_ERR(edev, "UDP port %u doesn't exist\n",
2614 tunnel_udp->udp_port);
2620 tunn.geneve_port.b_update_port = true;
2621 tunn.geneve_port.port = udp_port;
2623 rc = qede_tunnel_update(qdev, &tunn);
2624 if (rc != ECORE_SUCCESS) {
2625 DP_ERR(edev, "Unable to config UDP port %u\n",
2626 tunn.vxlan_port.port);
2630 qdev->vxlan.udp_port = udp_port;
2631 /* If the request is to delete UDP port and if the number of
2632 * GENEVE filters have reached 0 then GENEVE offload can be be
2635 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2636 return qede_geneve_enable(eth_dev,
2637 ECORE_TUNN_CLSS_MAC_VLAN, false);
2649 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2650 struct rte_eth_udp_tunnel *tunnel_udp)
2652 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2653 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2654 struct ecore_tunnel_info tunn; /* @DPDK */
2658 PMD_INIT_FUNC_TRACE(edev);
2660 memset(&tunn, 0, sizeof(tunn));
2662 switch (tunnel_udp->prot_type) {
2663 case RTE_TUNNEL_TYPE_VXLAN:
2664 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2666 "UDP port %u for VXLAN was already configured\n",
2667 tunnel_udp->udp_port);
2668 return ECORE_SUCCESS;
2671 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2672 * it was not enabled while adding VXLAN filter before UDP port
2675 if (!qdev->vxlan.enable) {
2676 rc = qede_vxlan_enable(eth_dev,
2677 ECORE_TUNN_CLSS_MAC_VLAN, true);
2678 if (rc != ECORE_SUCCESS) {
2679 DP_ERR(edev, "Failed to enable VXLAN "
2680 "prior to updating UDP port\n");
2684 udp_port = tunnel_udp->udp_port;
2686 tunn.vxlan_port.b_update_port = true;
2687 tunn.vxlan_port.port = udp_port;
2689 rc = qede_tunnel_update(qdev, &tunn);
2690 if (rc != ECORE_SUCCESS) {
2691 DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2696 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2698 qdev->vxlan.udp_port = udp_port;
2700 case RTE_TUNNEL_TYPE_GENEVE:
2701 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2703 "UDP port %u for GENEVE was already configured\n",
2704 tunnel_udp->udp_port);
2705 return ECORE_SUCCESS;
2708 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2709 * it was not enabled while adding GENEVE filter before UDP port
2712 if (!qdev->geneve.enable) {
2713 rc = qede_geneve_enable(eth_dev,
2714 ECORE_TUNN_CLSS_MAC_VLAN, true);
2715 if (rc != ECORE_SUCCESS) {
2716 DP_ERR(edev, "Failed to enable GENEVE "
2717 "prior to updating UDP port\n");
2721 udp_port = tunnel_udp->udp_port;
2723 tunn.geneve_port.b_update_port = true;
2724 tunn.geneve_port.port = udp_port;
2726 rc = qede_tunnel_update(qdev, &tunn);
2727 if (rc != ECORE_SUCCESS) {
2728 DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2733 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2735 qdev->geneve.udp_port = udp_port;
2744 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2745 uint32_t *clss, char *str)
2748 *clss = MAX_ECORE_TUNN_CLSS;
2750 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2751 if (filter == qede_tunn_types[j].rte_filter_type) {
2752 *type = qede_tunn_types[j].qede_type;
2753 *clss = qede_tunn_types[j].qede_tunn_clss;
2754 strcpy(str, qede_tunn_types[j].string);
2761 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2762 const struct rte_eth_tunnel_filter_conf *conf,
2765 /* Init commmon ucast params first */
2766 qede_set_ucast_cmn_params(ucast);
2768 /* Copy out the required fields based on classification type */
2772 case ECORE_FILTER_VNI:
2773 ucast->vni = conf->tenant_id;
2775 case ECORE_FILTER_INNER_VLAN:
2776 ucast->vlan = conf->inner_vlan;
2778 case ECORE_FILTER_MAC:
2779 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2782 case ECORE_FILTER_INNER_MAC:
2783 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2786 case ECORE_FILTER_MAC_VNI_PAIR:
2787 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2789 ucast->vni = conf->tenant_id;
2791 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2792 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2794 ucast->vni = conf->tenant_id;
2796 case ECORE_FILTER_INNER_PAIR:
2797 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2799 ucast->vlan = conf->inner_vlan;
2805 return ECORE_SUCCESS;
2809 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2810 const struct rte_eth_tunnel_filter_conf *conf,
2811 __attribute__((unused)) enum rte_filter_op filter_op,
2812 enum ecore_tunn_clss *clss,
2815 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2816 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2817 struct ecore_filter_ucast ucast = {0};
2818 enum ecore_filter_ucast_type type;
2819 uint16_t filter_type = 0;
2823 filter_type = conf->filter_type;
2824 /* Determine if the given filter classification is supported */
2825 qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2826 if (*clss == MAX_ECORE_TUNN_CLSS) {
2827 DP_ERR(edev, "Unsupported filter type\n");
2830 /* Init tunnel ucast params */
2831 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2832 if (rc != ECORE_SUCCESS) {
2833 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2837 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2838 str, filter_op, ucast.type);
2840 ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2842 /* Skip MAC/VLAN if filter is based on VNI */
2843 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2844 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2845 if ((rc == 0) && add) {
2846 /* Enable accept anyvlan */
2847 qede_config_accept_any_vlan(qdev, true);
2850 rc = qede_ucast_filter(eth_dev, &ucast, add);
2852 rc = ecore_filter_ucast_cmd(edev, &ucast,
2853 ECORE_SPQ_MODE_CB, NULL);
2860 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2861 enum rte_filter_op filter_op,
2862 const struct rte_eth_tunnel_filter_conf *conf)
2864 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2865 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2866 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2870 PMD_INIT_FUNC_TRACE(edev);
2872 switch (filter_op) {
2873 case RTE_ETH_FILTER_ADD:
2876 case RTE_ETH_FILTER_DELETE:
2880 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2885 return qede_tunn_enable(eth_dev,
2886 ECORE_TUNN_CLSS_MAC_VLAN,
2887 conf->tunnel_type, add);
2889 rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2890 if (rc != ECORE_SUCCESS)
2894 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2895 qdev->vxlan.num_filters++;
2896 qdev->vxlan.filter_type = conf->filter_type;
2897 } else { /* GENEVE */
2898 qdev->geneve.num_filters++;
2899 qdev->geneve.filter_type = conf->filter_type;
2902 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2903 !qdev->ipgre.enable)
2904 return qede_tunn_enable(eth_dev, clss,
2908 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2909 qdev->vxlan.num_filters--;
2911 qdev->geneve.num_filters--;
2913 /* Disable VXLAN if VXLAN filters become 0 */
2914 if ((qdev->vxlan.num_filters == 0) ||
2915 (qdev->geneve.num_filters == 0))
2916 return qede_tunn_enable(eth_dev, clss,
2924 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2925 enum rte_filter_type filter_type,
2926 enum rte_filter_op filter_op,
2929 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2930 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2931 struct rte_eth_tunnel_filter_conf *filter_conf =
2932 (struct rte_eth_tunnel_filter_conf *)arg;
2934 switch (filter_type) {
2935 case RTE_ETH_FILTER_TUNNEL:
2936 switch (filter_conf->tunnel_type) {
2937 case RTE_TUNNEL_TYPE_VXLAN:
2938 case RTE_TUNNEL_TYPE_GENEVE:
2939 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2941 "Packet steering to the specified Rx queue"
2942 " is not supported with UDP tunneling");
2943 return(qede_tunn_filter_config(eth_dev, filter_op,
2945 case RTE_TUNNEL_TYPE_TEREDO:
2946 case RTE_TUNNEL_TYPE_NVGRE:
2947 case RTE_L2_TUNNEL_TYPE_E_TAG:
2948 DP_ERR(edev, "Unsupported tunnel type %d\n",
2949 filter_conf->tunnel_type);
2951 case RTE_TUNNEL_TYPE_NONE:
2956 case RTE_ETH_FILTER_FDIR:
2957 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2958 case RTE_ETH_FILTER_NTUPLE:
2959 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2960 case RTE_ETH_FILTER_MACVLAN:
2961 case RTE_ETH_FILTER_ETHERTYPE:
2962 case RTE_ETH_FILTER_FLEXIBLE:
2963 case RTE_ETH_FILTER_SYN:
2964 case RTE_ETH_FILTER_HASH:
2965 case RTE_ETH_FILTER_L2_TUNNEL:
2966 case RTE_ETH_FILTER_MAX:
2968 DP_ERR(edev, "Unsupported filter type %d\n",
2976 static const struct eth_dev_ops qede_eth_dev_ops = {
2977 .dev_configure = qede_dev_configure,
2978 .dev_infos_get = qede_dev_info_get,
2979 .rx_queue_setup = qede_rx_queue_setup,
2980 .rx_queue_release = qede_rx_queue_release,
2981 .tx_queue_setup = qede_tx_queue_setup,
2982 .tx_queue_release = qede_tx_queue_release,
2983 .dev_start = qede_dev_start,
2984 .dev_set_link_up = qede_dev_set_link_up,
2985 .dev_set_link_down = qede_dev_set_link_down,
2986 .link_update = qede_link_update,
2987 .promiscuous_enable = qede_promiscuous_enable,
2988 .promiscuous_disable = qede_promiscuous_disable,
2989 .allmulticast_enable = qede_allmulticast_enable,
2990 .allmulticast_disable = qede_allmulticast_disable,
2991 .set_mc_addr_list = qede_set_mc_addr_list,
2992 .dev_stop = qede_dev_stop,
2993 .dev_close = qede_dev_close,
2994 .stats_get = qede_get_stats,
2995 .stats_reset = qede_reset_stats,
2996 .xstats_get = qede_get_xstats,
2997 .xstats_reset = qede_reset_xstats,
2998 .xstats_get_names = qede_get_xstats_names,
2999 .mac_addr_add = qede_mac_addr_add,
3000 .mac_addr_remove = qede_mac_addr_remove,
3001 .mac_addr_set = qede_mac_addr_set,
3002 .vlan_offload_set = qede_vlan_offload_set,
3003 .vlan_filter_set = qede_vlan_filter_set,
3004 .flow_ctrl_set = qede_flow_ctrl_set,
3005 .flow_ctrl_get = qede_flow_ctrl_get,
3006 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
3007 .rss_hash_update = qede_rss_hash_update,
3008 .rss_hash_conf_get = qede_rss_hash_conf_get,
3009 .reta_update = qede_rss_reta_update,
3010 .reta_query = qede_rss_reta_query,
3011 .mtu_set = qede_set_mtu,
3012 .filter_ctrl = qede_dev_filter_ctrl,
3013 .udp_tunnel_port_add = qede_udp_dst_port_add,
3014 .udp_tunnel_port_del = qede_udp_dst_port_del,
3017 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
3018 .dev_configure = qede_dev_configure,
3019 .dev_infos_get = qede_dev_info_get,
3020 .rx_queue_setup = qede_rx_queue_setup,
3021 .rx_queue_release = qede_rx_queue_release,
3022 .tx_queue_setup = qede_tx_queue_setup,
3023 .tx_queue_release = qede_tx_queue_release,
3024 .dev_start = qede_dev_start,
3025 .dev_set_link_up = qede_dev_set_link_up,
3026 .dev_set_link_down = qede_dev_set_link_down,
3027 .link_update = qede_link_update,
3028 .promiscuous_enable = qede_promiscuous_enable,
3029 .promiscuous_disable = qede_promiscuous_disable,
3030 .allmulticast_enable = qede_allmulticast_enable,
3031 .allmulticast_disable = qede_allmulticast_disable,
3032 .set_mc_addr_list = qede_set_mc_addr_list,
3033 .dev_stop = qede_dev_stop,
3034 .dev_close = qede_dev_close,
3035 .stats_get = qede_get_stats,
3036 .stats_reset = qede_reset_stats,
3037 .xstats_get = qede_get_xstats,
3038 .xstats_reset = qede_reset_xstats,
3039 .xstats_get_names = qede_get_xstats_names,
3040 .vlan_offload_set = qede_vlan_offload_set,
3041 .vlan_filter_set = qede_vlan_filter_set,
3042 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
3043 .rss_hash_update = qede_rss_hash_update,
3044 .rss_hash_conf_get = qede_rss_hash_conf_get,
3045 .reta_update = qede_rss_reta_update,
3046 .reta_query = qede_rss_reta_query,
3047 .mtu_set = qede_set_mtu,
3048 .udp_tunnel_port_add = qede_udp_dst_port_add,
3049 .udp_tunnel_port_del = qede_udp_dst_port_del,
3050 .mac_addr_add = qede_mac_addr_add,
3051 .mac_addr_remove = qede_mac_addr_remove,
3052 .mac_addr_set = qede_mac_addr_set,
3055 static void qede_update_pf_params(struct ecore_dev *edev)
3057 struct ecore_pf_params pf_params;
3059 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
3060 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
3061 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
3062 qed_ops->common->update_pf_params(edev, &pf_params);
3065 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
3067 struct rte_pci_device *pci_dev;
3068 struct rte_pci_addr pci_addr;
3069 struct qede_dev *adapter;
3070 struct ecore_dev *edev;
3071 struct qed_dev_eth_info dev_info;
3072 struct qed_slowpath_params params;
3073 static bool do_once = true;
3074 uint8_t bulletin_change;
3075 uint8_t vf_mac[ETHER_ADDR_LEN];
3076 uint8_t is_mac_forced;
3078 /* Fix up ecore debug level */
3079 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3080 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3084 /* Extract key data structures */
3085 adapter = eth_dev->data->dev_private;
3086 adapter->ethdev = eth_dev;
3087 edev = &adapter->edev;
3088 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3089 pci_addr = pci_dev->addr;
3091 PMD_INIT_FUNC_TRACE(edev);
3093 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3094 pci_addr.bus, pci_addr.devid, pci_addr.function,
3095 eth_dev->data->port_id);
3097 eth_dev->rx_pkt_burst = qede_recv_pkts;
3098 eth_dev->tx_pkt_burst = qede_xmit_pkts;
3099 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3101 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3102 DP_ERR(edev, "Skipping device init from secondary process\n");
3106 rte_eth_copy_pci_info(eth_dev, pci_dev);
3109 edev->vendor_id = pci_dev->id.vendor_id;
3110 edev->device_id = pci_dev->id.device_id;
3112 qed_ops = qed_get_eth_ops();
3114 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3118 DP_INFO(edev, "Starting qede probe\n");
3119 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3122 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3125 qede_update_pf_params(edev);
3127 switch (pci_dev->intr_handle.type) {
3128 case RTE_INTR_HANDLE_UIO_INTX:
3129 case RTE_INTR_HANDLE_VFIO_LEGACY:
3130 int_mode = ECORE_INT_MODE_INTA;
3131 rte_intr_callback_register(&pci_dev->intr_handle,
3132 qede_interrupt_handler_intx,
3136 int_mode = ECORE_INT_MODE_MSIX;
3137 rte_intr_callback_register(&pci_dev->intr_handle,
3138 qede_interrupt_handler,
3142 if (rte_intr_enable(&pci_dev->intr_handle)) {
3143 DP_ERR(edev, "rte_intr_enable() failed\n");
3147 /* Start the Slowpath-process */
3148 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
3150 params.int_mode = int_mode;
3151 params.drv_major = QEDE_PMD_VERSION_MAJOR;
3152 params.drv_minor = QEDE_PMD_VERSION_MINOR;
3153 params.drv_rev = QEDE_PMD_VERSION_REVISION;
3154 params.drv_eng = QEDE_PMD_VERSION_PATCH;
3155 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3156 QEDE_PMD_DRV_VER_STR_SIZE);
3158 /* For CMT mode device do periodic polling for slowpath events.
3159 * This is required since uio device uses only one MSI-x
3160 * interrupt vector but we need one for each engine.
3162 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3163 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
3167 DP_ERR(edev, "Unable to start periodic"
3168 " timer rc %d\n", rc);
3173 rc = qed_ops->common->slowpath_start(edev, ¶ms);
3175 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3176 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3181 rc = qed_ops->fill_dev_info(edev, &dev_info);
3183 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3184 qed_ops->common->slowpath_stop(edev);
3185 qed_ops->common->remove(edev);
3186 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3191 qede_alloc_etherdev(adapter, &dev_info);
3193 adapter->ops->common->set_name(edev, edev->name);
3196 adapter->dev_info.num_mac_filters =
3197 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3200 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3201 (uint32_t *)&adapter->dev_info.num_mac_filters);
3203 /* Allocate memory for storing MAC addr */
3204 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3206 adapter->dev_info.num_mac_filters),
3207 RTE_CACHE_LINE_SIZE);
3209 if (eth_dev->data->mac_addrs == NULL) {
3210 DP_ERR(edev, "Failed to allocate MAC address\n");
3211 qed_ops->common->slowpath_stop(edev);
3212 qed_ops->common->remove(edev);
3213 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3219 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3220 hw_info.hw_mac_addr,
3221 ð_dev->data->mac_addrs[0]);
3222 ether_addr_copy(ð_dev->data->mac_addrs[0],
3223 &adapter->primary_mac);
3225 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3227 if (bulletin_change) {
3229 ecore_vf_bulletin_get_forced_mac(
3230 ECORE_LEADING_HWFN(edev),
3234 DP_INFO(edev, "VF macaddr received from PF\n");
3235 ether_addr_copy((struct ether_addr *)&vf_mac,
3236 ð_dev->data->mac_addrs[0]);
3237 ether_addr_copy(ð_dev->data->mac_addrs[0],
3238 &adapter->primary_mac);
3240 DP_ERR(edev, "No VF macaddr assigned\n");
3245 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3248 qede_print_adapter_info(adapter);
3252 /* Bring-up the link */
3253 qede_dev_set_link_state(eth_dev, true);
3255 adapter->num_tx_queues = 0;
3256 adapter->num_rx_queues = 0;
3257 SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3258 SLIST_INIT(&adapter->vlan_list_head);
3259 SLIST_INIT(&adapter->uc_list_head);
3260 SLIST_INIT(&adapter->mc_list_head);
3261 adapter->mtu = ETHER_MTU;
3262 adapter->vport_started = false;
3264 /* VF tunnel offloads is enabled by default in PF driver */
3265 adapter->vxlan.num_filters = 0;
3266 adapter->geneve.num_filters = 0;
3267 adapter->ipgre.num_filters = 0;
3269 adapter->vxlan.enable = true;
3270 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3271 ETH_TUNNEL_FILTER_IVLAN;
3272 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3273 adapter->geneve.enable = true;
3274 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3275 ETH_TUNNEL_FILTER_IVLAN;
3276 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3277 adapter->ipgre.enable = true;
3278 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3279 ETH_TUNNEL_FILTER_IVLAN;
3281 adapter->vxlan.enable = false;
3282 adapter->geneve.enable = false;
3283 adapter->ipgre.enable = false;
3286 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3287 adapter->primary_mac.addr_bytes[0],
3288 adapter->primary_mac.addr_bytes[1],
3289 adapter->primary_mac.addr_bytes[2],
3290 adapter->primary_mac.addr_bytes[3],
3291 adapter->primary_mac.addr_bytes[4],
3292 adapter->primary_mac.addr_bytes[5]);
3294 DP_INFO(edev, "Device initialized\n");
3299 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3301 return qede_common_dev_init(eth_dev, 1);
3304 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3306 return qede_common_dev_init(eth_dev, 0);
3309 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3311 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3312 struct qede_dev *qdev = eth_dev->data->dev_private;
3313 struct ecore_dev *edev = &qdev->edev;
3315 PMD_INIT_FUNC_TRACE(edev);
3318 /* only uninitialize in the primary process */
3319 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3322 /* safe to close dev here */
3323 qede_dev_close(eth_dev);
3325 eth_dev->dev_ops = NULL;
3326 eth_dev->rx_pkt_burst = NULL;
3327 eth_dev->tx_pkt_burst = NULL;
3329 if (eth_dev->data->mac_addrs)
3330 rte_free(eth_dev->data->mac_addrs);
3332 eth_dev->data->mac_addrs = NULL;
3337 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3339 return qede_dev_common_uninit(eth_dev);
3342 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3344 return qede_dev_common_uninit(eth_dev);
3347 static const struct rte_pci_id pci_id_qedevf_map[] = {
3348 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3350 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3353 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3356 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3361 static const struct rte_pci_id pci_id_qede_map[] = {
3362 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3364 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3367 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3370 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3373 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3376 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3379 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3382 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3385 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3388 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3391 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3396 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3397 struct rte_pci_device *pci_dev)
3399 return rte_eth_dev_pci_generic_probe(pci_dev,
3400 sizeof(struct qede_dev), qedevf_eth_dev_init);
3403 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3405 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3408 static struct rte_pci_driver rte_qedevf_pmd = {
3409 .id_table = pci_id_qedevf_map,
3410 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3411 .probe = qedevf_eth_dev_pci_probe,
3412 .remove = qedevf_eth_dev_pci_remove,
3415 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3416 struct rte_pci_device *pci_dev)
3418 return rte_eth_dev_pci_generic_probe(pci_dev,
3419 sizeof(struct qede_dev), qede_eth_dev_init);
3422 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3424 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3427 static struct rte_pci_driver rte_qede_pmd = {
3428 .id_table = pci_id_qede_map,
3429 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3430 .probe = qede_eth_dev_pci_probe,
3431 .remove = qede_eth_dev_pci_remove,
3434 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3435 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3436 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3437 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3438 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3439 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3441 RTE_INIT(qede_init_log)
3443 qede_logtype_init = rte_log_register("pmd.net.qede.init");
3444 if (qede_logtype_init >= 0)
3445 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3446 qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3447 if (qede_logtype_driver >= 0)
3448 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);