2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
14 static const struct qed_eth_ops *qed_ops;
15 static int64_t timer_period = 1;
17 /* VXLAN tunnel classification mapping */
18 const struct _qede_vxlan_tunn_types {
19 uint16_t rte_filter_type;
20 enum ecore_filter_ucast_type qede_type;
21 enum ecore_tunn_clss qede_tunn_clss;
23 } qede_tunn_types[] = {
25 ETH_TUNNEL_FILTER_OMAC,
27 ECORE_TUNN_CLSS_MAC_VLAN,
31 ETH_TUNNEL_FILTER_TENID,
33 ECORE_TUNN_CLSS_MAC_VNI,
37 ETH_TUNNEL_FILTER_IMAC,
38 ECORE_FILTER_INNER_MAC,
39 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
43 ETH_TUNNEL_FILTER_IVLAN,
44 ECORE_FILTER_INNER_VLAN,
45 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
49 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
50 ECORE_FILTER_MAC_VNI_PAIR,
51 ECORE_TUNN_CLSS_MAC_VNI,
55 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
58 "outer-mac and inner-mac"
61 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
64 "outer-mac and inner-vlan"
67 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
68 ECORE_FILTER_INNER_MAC_VNI_PAIR,
69 ECORE_TUNN_CLSS_INNER_MAC_VNI,
73 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
79 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
80 ECORE_FILTER_INNER_PAIR,
81 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
82 "inner-mac and inner-vlan",
85 ETH_TUNNEL_FILTER_OIP,
91 ETH_TUNNEL_FILTER_IIP,
97 RTE_TUNNEL_FILTER_IMAC_IVLAN,
103 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
109 RTE_TUNNEL_FILTER_IMAC_TENID,
115 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
122 struct rte_qede_xstats_name_off {
123 char name[RTE_ETH_XSTATS_NAME_SIZE];
127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
128 {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
129 {"rx_multicast_bytes",
130 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
131 {"rx_broadcast_bytes",
132 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
133 {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
134 {"rx_multicast_packets",
135 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
136 {"rx_broadcast_packets",
137 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
139 {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
140 {"tx_multicast_bytes",
141 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
142 {"tx_broadcast_bytes",
143 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
144 {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
145 {"tx_multicast_packets",
146 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
147 {"tx_broadcast_packets",
148 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
150 {"rx_64_byte_packets",
151 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
152 {"rx_65_to_127_byte_packets",
153 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
154 {"rx_128_to_255_byte_packets",
155 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
156 {"rx_256_to_511_byte_packets",
157 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
158 {"rx_512_to_1023_byte_packets",
159 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
160 {"rx_1024_to_1518_byte_packets",
161 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
162 {"rx_1519_to_1522_byte_packets",
163 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
164 {"rx_1519_to_2047_byte_packets",
165 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
166 {"rx_2048_to_4095_byte_packets",
167 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
168 {"rx_4096_to_9216_byte_packets",
169 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
170 {"rx_9217_to_16383_byte_packets",
171 offsetof(struct ecore_eth_stats,
172 rx_9217_to_16383_byte_packets)},
173 {"tx_64_byte_packets",
174 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
175 {"tx_65_to_127_byte_packets",
176 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
177 {"tx_128_to_255_byte_packets",
178 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
179 {"tx_256_to_511_byte_packets",
180 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
181 {"tx_512_to_1023_byte_packets",
182 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
183 {"tx_1024_to_1518_byte_packets",
184 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
185 {"trx_1519_to_1522_byte_packets",
186 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
187 {"tx_2048_to_4095_byte_packets",
188 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
189 {"tx_4096_to_9216_byte_packets",
190 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
191 {"tx_9217_to_16383_byte_packets",
192 offsetof(struct ecore_eth_stats,
193 tx_9217_to_16383_byte_packets)},
195 {"rx_mac_crtl_frames",
196 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
197 {"tx_mac_control_frames",
198 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
199 {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
200 {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
201 {"rx_priority_flow_control_frames",
202 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
203 {"tx_priority_flow_control_frames",
204 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
206 {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
207 {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
208 {"rx_carrier_errors",
209 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
210 {"rx_oversize_packet_errors",
211 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
212 {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
213 {"rx_undersize_packet_errors",
214 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
215 {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
216 {"rx_host_buffer_not_available",
217 offsetof(struct ecore_eth_stats, no_buff_discards)},
218 /* Number of packets discarded because they are bigger than MTU */
219 {"rx_packet_too_big_discards",
220 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
221 {"rx_ttl_zero_discards",
222 offsetof(struct ecore_eth_stats, ttl0_discard)},
223 {"rx_multi_function_tag_filter_discards",
224 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
225 {"rx_mac_filter_discards",
226 offsetof(struct ecore_eth_stats, mac_filter_discards)},
227 {"rx_hw_buffer_truncates",
228 offsetof(struct ecore_eth_stats, brb_truncates)},
229 {"rx_hw_buffer_discards",
230 offsetof(struct ecore_eth_stats, brb_discards)},
231 {"tx_lpi_entry_count",
232 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
233 {"tx_total_collisions",
234 offsetof(struct ecore_eth_stats, tx_total_collisions)},
235 {"tx_error_drop_packets",
236 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
239 {"rx_mac_unicast_packets",
240 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
241 {"rx_mac_multicast_packets",
242 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
243 {"rx_mac_broadcast_packets",
244 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
246 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
248 {"tx_mac_unicast_packets",
249 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
250 {"tx_mac_multicast_packets",
251 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
252 {"tx_mac_broadcast_packets",
253 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
255 {"lro_coalesced_packets",
256 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
257 {"lro_coalesced_events",
258 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
260 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
261 {"lro_not_coalesced_packets",
262 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
263 {"lro_coalesced_bytes",
264 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
269 offsetof(struct qede_rx_queue, rx_segs)},
271 offsetof(struct qede_rx_queue, rx_hw_errors)},
272 {"rx_q_allocation_errors",
273 offsetof(struct qede_rx_queue, rx_alloc_errors)}
276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
278 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
282 qede_interrupt_handler(void *param)
284 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
285 struct qede_dev *qdev = eth_dev->data->dev_private;
286 struct ecore_dev *edev = &qdev->edev;
288 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
289 if (rte_intr_enable(eth_dev->intr_handle))
290 DP_ERR(edev, "rte_intr_enable failed\n");
294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
296 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
300 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
301 static void qede_print_adapter_info(struct qede_dev *qdev)
303 struct ecore_dev *edev = &qdev->edev;
304 struct qed_dev_info *info = &qdev->dev_info.common;
305 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
306 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
308 DP_INFO(edev, "*********************************\n");
309 DP_INFO(edev, " DPDK version:%s\n", rte_version());
310 DP_INFO(edev, " Chip details : %s%d\n",
311 ECORE_IS_BB(edev) ? "BB" : "AH",
312 CHIP_REV_IS_A0(edev) ? 0 : 1);
313 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
314 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
315 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
316 ver_str, QEDE_PMD_VERSION);
317 DP_INFO(edev, " Driver version : %s\n", drv_ver);
318 DP_INFO(edev, " Firmware version : %s\n", ver_str);
320 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
322 (info->mfw_rev >> 24) & 0xff,
323 (info->mfw_rev >> 16) & 0xff,
324 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
325 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
326 DP_INFO(edev, " Firmware file : %s\n", fw_file);
327 DP_INFO(edev, "*********************************\n");
332 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
334 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
335 struct ecore_sp_vport_start_params params;
336 struct ecore_hwfn *p_hwfn;
340 memset(¶ms, 0, sizeof(params));
343 /* @DPDK - Disable FW placement */
344 params.zero_placement_offset = 1;
345 for_each_hwfn(edev, i) {
346 p_hwfn = &edev->hwfns[i];
347 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
348 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
349 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
350 if (rc != ECORE_SUCCESS) {
351 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
355 ecore_reset_vport_stats(edev);
356 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
362 qede_stop_vport(struct ecore_dev *edev)
364 struct ecore_hwfn *p_hwfn;
370 for_each_hwfn(edev, i) {
371 p_hwfn = &edev->hwfns[i];
372 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
374 if (rc != ECORE_SUCCESS) {
375 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
383 /* Activate or deactivate vport via vport-update */
384 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
386 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
387 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
388 struct ecore_sp_vport_update_params params;
389 struct ecore_hwfn *p_hwfn;
393 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
395 params.update_vport_active_rx_flg = 1;
396 params.update_vport_active_tx_flg = 1;
397 params.vport_active_rx_flg = flg;
398 params.vport_active_tx_flg = flg;
399 for_each_hwfn(edev, i) {
400 p_hwfn = &edev->hwfns[i];
401 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
402 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
403 ECORE_SPQ_MODE_EBLOCK, NULL);
404 if (rc != ECORE_SUCCESS) {
405 DP_ERR(edev, "Failed to update vport\n");
409 DP_INFO(edev, "vport %s\n", flg ? "activated" : "deactivated");
414 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
415 uint16_t mtu, bool enable)
417 /* Enable LRO in split mode */
418 sge_tpa_params->tpa_ipv4_en_flg = enable;
419 sge_tpa_params->tpa_ipv6_en_flg = enable;
420 sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
421 sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
422 /* set if tpa enable changes */
423 sge_tpa_params->update_tpa_en_flg = 1;
424 /* set if tpa parameters should be handled */
425 sge_tpa_params->update_tpa_param_flg = enable;
427 sge_tpa_params->max_buffers_per_cqe = 20;
428 /* Enable TPA in split mode. In this mode each TPA segment
429 * starts on the new BD, so there is one BD per segment.
431 sge_tpa_params->tpa_pkt_split_flg = 1;
432 sge_tpa_params->tpa_hdr_data_split_flg = 0;
433 sge_tpa_params->tpa_gro_consistent_flg = 0;
434 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
435 sge_tpa_params->tpa_max_size = 0x7FFF;
436 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
437 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
440 /* Enable/disable LRO via vport-update */
441 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
443 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
444 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
445 struct ecore_sp_vport_update_params params;
446 struct ecore_sge_tpa_params tpa_params;
447 struct ecore_hwfn *p_hwfn;
451 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
452 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
453 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
455 params.sge_tpa_params = &tpa_params;
456 for_each_hwfn(edev, i) {
457 p_hwfn = &edev->hwfns[i];
458 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
459 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
460 ECORE_SPQ_MODE_EBLOCK, NULL);
461 if (rc != ECORE_SUCCESS) {
462 DP_ERR(edev, "Failed to update LRO\n");
467 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
472 /* Update MTU via vport-update without doing port restart.
473 * The vport must be deactivated before calling this API.
475 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
477 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
478 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
479 struct ecore_sp_vport_update_params params;
480 struct ecore_hwfn *p_hwfn;
484 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
488 for_each_hwfn(edev, i) {
489 p_hwfn = &edev->hwfns[i];
490 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
491 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
492 ECORE_SPQ_MODE_EBLOCK, NULL);
493 if (rc != ECORE_SUCCESS) {
494 DP_ERR(edev, "Failed to update MTU\n");
498 DP_INFO(edev, "MTU updated to %u\n", mtu);
503 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
505 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
506 ucast->is_rx_filter = true;
507 ucast->is_tx_filter = true;
508 /* ucast->assert_on_error = true; - For debug */
512 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
513 enum qed_filter_rx_mode_type type)
515 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
516 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
517 struct ecore_filter_accept_flags flags;
519 memset(&flags, 0, sizeof(flags));
521 flags.update_rx_mode_config = 1;
522 flags.update_tx_mode_config = 1;
523 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
524 ECORE_ACCEPT_MCAST_MATCHED |
527 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
528 ECORE_ACCEPT_MCAST_MATCHED |
531 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
532 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
534 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
535 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
537 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
538 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
539 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
540 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
541 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
542 ECORE_ACCEPT_MCAST_UNMATCHED;
545 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
546 ECORE_SPQ_MODE_CB, NULL);
548 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
549 uint8_t clss, bool mode, bool mask)
551 memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
552 p_tunn->vxlan.b_update_mode = mode;
553 p_tunn->vxlan.b_mode_enabled = mask;
554 p_tunn->b_update_rx_cls = true;
555 p_tunn->b_update_tx_cls = true;
556 p_tunn->vxlan.tun_cls = clss;
560 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
563 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
564 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
565 struct qede_ucast_entry *tmp = NULL;
566 struct qede_ucast_entry *u;
567 struct ether_addr *mac_addr;
569 mac_addr = (struct ether_addr *)ucast->mac;
571 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
572 if ((memcmp(mac_addr, &tmp->mac,
573 ETHER_ADDR_LEN) == 0) &&
574 ucast->vlan == tmp->vlan) {
575 DP_ERR(edev, "Unicast MAC is already added"
576 " with vlan = %u, vni = %u\n",
577 ucast->vlan, ucast->vni);
581 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
582 RTE_CACHE_LINE_SIZE);
584 DP_ERR(edev, "Did not allocate memory for ucast\n");
587 ether_addr_copy(mac_addr, &u->mac);
588 u->vlan = ucast->vlan;
590 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
593 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
594 if ((memcmp(mac_addr, &tmp->mac,
595 ETHER_ADDR_LEN) == 0) &&
596 ucast->vlan == tmp->vlan &&
597 ucast->vni == tmp->vni)
601 DP_INFO(edev, "Unicast MAC is not found\n");
604 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
612 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
615 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
616 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
617 struct ether_addr *mac_addr;
618 struct qede_mcast_entry *tmp = NULL;
619 struct qede_mcast_entry *m;
621 mac_addr = (struct ether_addr *)mcast->mac;
623 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
624 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
626 "Multicast MAC is already added\n");
630 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
631 RTE_CACHE_LINE_SIZE);
634 "Did not allocate memory for mcast\n");
637 ether_addr_copy(mac_addr, &m->mac);
638 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
641 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
642 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
646 DP_INFO(edev, "Multicast mac is not found\n");
649 SLIST_REMOVE(&qdev->mc_list_head, tmp,
650 qede_mcast_entry, list);
657 static enum _ecore_status_t
658 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
661 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
662 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
663 enum _ecore_status_t rc;
664 struct ecore_filter_mcast mcast;
665 struct qede_mcast_entry *tmp;
669 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
671 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
673 "Mcast filter table limit exceeded, "
674 "Please enable mcast promisc mode\n");
678 rc = qede_mcast_filter(eth_dev, ucast, add);
680 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
681 memset(&mcast, 0, sizeof(mcast));
682 mcast.num_mc_addrs = qdev->num_mc_addr;
683 mcast.opcode = ECORE_FILTER_ADD;
684 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
685 ether_addr_copy(&tmp->mac,
686 (struct ether_addr *)&mcast.mac[j]);
689 rc = ecore_filter_mcast_cmd(edev, &mcast,
690 ECORE_SPQ_MODE_CB, NULL);
692 if (rc != ECORE_SUCCESS) {
693 DP_ERR(edev, "Failed to add multicast filter"
694 " rc = %d, op = %d\n", rc, add);
696 } else { /* Unicast */
698 if (qdev->num_uc_addr >=
699 qdev->dev_info.num_mac_filters) {
701 "Ucast filter table limit exceeded,"
702 " Please enable promisc mode\n");
706 rc = qede_ucast_filter(eth_dev, ucast, add);
708 rc = ecore_filter_ucast_cmd(edev, ucast,
709 ECORE_SPQ_MODE_CB, NULL);
710 if (rc != ECORE_SUCCESS) {
711 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
720 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
721 __rte_unused uint32_t index, __rte_unused uint32_t pool)
723 struct ecore_filter_ucast ucast;
726 qede_set_ucast_cmn_params(&ucast);
727 ucast.type = ECORE_FILTER_MAC;
728 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
729 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
734 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
736 struct qede_dev *qdev = eth_dev->data->dev_private;
737 struct ecore_dev *edev = &qdev->edev;
738 struct ecore_filter_ucast ucast;
740 PMD_INIT_FUNC_TRACE(edev);
742 if (index >= qdev->dev_info.num_mac_filters) {
743 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
744 index, qdev->dev_info.num_mac_filters);
748 qede_set_ucast_cmn_params(&ucast);
749 ucast.opcode = ECORE_FILTER_REMOVE;
750 ucast.type = ECORE_FILTER_MAC;
752 /* Use the index maintained by rte */
753 ether_addr_copy(ð_dev->data->mac_addrs[index],
754 (struct ether_addr *)&ucast.mac);
756 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
760 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
762 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
763 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
765 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
766 mac_addr->addr_bytes)) {
767 DP_ERR(edev, "Setting MAC address is not allowed\n");
768 ether_addr_copy(&qdev->primary_mac,
769 ð_dev->data->mac_addrs[0]);
773 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
776 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
778 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
779 struct ecore_sp_vport_update_params params;
780 struct ecore_hwfn *p_hwfn;
784 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
786 params.update_accept_any_vlan_flg = 1;
787 params.accept_any_vlan = flg;
788 for_each_hwfn(edev, i) {
789 p_hwfn = &edev->hwfns[i];
790 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
791 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
792 ECORE_SPQ_MODE_EBLOCK, NULL);
793 if (rc != ECORE_SUCCESS) {
794 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
799 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
802 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
804 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
805 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
806 struct ecore_sp_vport_update_params params;
807 struct ecore_hwfn *p_hwfn;
811 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
813 params.update_inner_vlan_removal_flg = 1;
814 params.inner_vlan_removal_flg = flg;
815 for_each_hwfn(edev, i) {
816 p_hwfn = &edev->hwfns[i];
817 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
818 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
819 ECORE_SPQ_MODE_EBLOCK, NULL);
820 if (rc != ECORE_SUCCESS) {
821 DP_ERR(edev, "Failed to update vport\n");
826 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
830 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
831 uint16_t vlan_id, int on)
833 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
834 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
835 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
836 struct qede_vlan_entry *tmp = NULL;
837 struct qede_vlan_entry *vlan;
838 struct ecore_filter_ucast ucast;
842 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
843 DP_ERR(edev, "Reached max VLAN filter limit"
844 " enabling accept_any_vlan\n");
845 qede_config_accept_any_vlan(qdev, true);
849 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
850 if (tmp->vid == vlan_id) {
851 DP_ERR(edev, "VLAN %u already configured\n",
857 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
858 RTE_CACHE_LINE_SIZE);
861 DP_ERR(edev, "Did not allocate memory for VLAN\n");
865 qede_set_ucast_cmn_params(&ucast);
866 ucast.opcode = ECORE_FILTER_ADD;
867 ucast.type = ECORE_FILTER_VLAN;
868 ucast.vlan = vlan_id;
869 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
872 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
877 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
878 qdev->configured_vlans++;
879 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
880 vlan_id, qdev->configured_vlans);
883 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
884 if (tmp->vid == vlan_id)
889 if (qdev->configured_vlans == 0) {
891 "No VLAN filters configured yet\n");
895 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
899 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
901 qede_set_ucast_cmn_params(&ucast);
902 ucast.opcode = ECORE_FILTER_REMOVE;
903 ucast.type = ECORE_FILTER_VLAN;
904 ucast.vlan = vlan_id;
905 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
908 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
911 qdev->configured_vlans--;
912 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
913 vlan_id, qdev->configured_vlans);
920 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
922 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
923 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
924 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
926 if (mask & ETH_VLAN_STRIP_MASK) {
927 if (rxmode->hw_vlan_strip)
928 (void)qede_vlan_stripping(eth_dev, 1);
930 (void)qede_vlan_stripping(eth_dev, 0);
933 if (mask & ETH_VLAN_FILTER_MASK) {
934 /* VLAN filtering kicks in when a VLAN is added */
935 if (rxmode->hw_vlan_filter) {
936 qede_vlan_filter_set(eth_dev, 0, 1);
938 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
940 " Please remove existing VLAN filters"
941 " before disabling VLAN filtering\n");
942 /* Signal app that VLAN filtering is still
945 rxmode->hw_vlan_filter = true;
947 qede_vlan_filter_set(eth_dev, 0, 0);
952 if (mask & ETH_VLAN_EXTEND_MASK)
953 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
954 " and classification is based on outer tag only\n");
956 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
957 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
960 static void qede_prandom_bytes(uint32_t *buff)
964 srand((unsigned int)time(NULL));
965 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
969 int qede_config_rss(struct rte_eth_dev *eth_dev)
971 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
972 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
973 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
975 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
976 struct rte_eth_rss_reta_entry64 reta_conf[2];
977 struct rte_eth_rss_conf rss_conf;
978 uint32_t i, id, pos, q;
980 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
981 if (!rss_conf.rss_key) {
982 DP_INFO(edev, "Applying driver default key\n");
983 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
984 qede_prandom_bytes(&def_rss_key[0]);
985 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
988 /* Configure RSS hash */
989 if (qede_rss_hash_update(eth_dev, &rss_conf))
992 /* Configure default RETA */
993 memset(reta_conf, 0, sizeof(reta_conf));
994 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
995 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
997 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
998 id = i / RTE_RETA_GROUP_SIZE;
999 pos = i % RTE_RETA_GROUP_SIZE;
1000 q = i % QEDE_RSS_COUNT(qdev);
1001 reta_conf[id].reta[pos] = q;
1003 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1004 ECORE_RSS_IND_TABLE_SIZE))
1010 static void qede_fastpath_start(struct ecore_dev *edev)
1012 struct ecore_hwfn *p_hwfn;
1015 for_each_hwfn(edev, i) {
1016 p_hwfn = &edev->hwfns[i];
1017 ecore_hw_start_fastpath(p_hwfn);
1021 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1023 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1024 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1026 PMD_INIT_FUNC_TRACE(edev);
1028 /* Update MTU only if it has changed */
1029 if (qdev->mtu != qdev->new_mtu) {
1030 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1032 qdev->mtu = qdev->new_mtu;
1033 /* If MTU has changed then update TPA too */
1034 if (qdev->enable_lro)
1035 if (qede_enable_tpa(eth_dev, true))
1040 if (qede_start_queues(eth_dev))
1043 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1044 * enabling RSS. Hence RSS configuration is deferred upto this point.
1045 * Also, we would like to retain similar behavior in PF case, so we
1046 * don't do PF/VF specific check here.
1048 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1049 if (qede_config_rss(eth_dev))
1053 if (qede_activate_vport(eth_dev, true))
1056 /* Bring-up the link */
1057 qede_dev_set_link_state(eth_dev, true);
1059 /* Start/resume traffic */
1060 qede_fastpath_start(edev);
1062 DP_INFO(edev, "Device started\n");
1066 DP_ERR(edev, "Device start fails\n");
1067 return -1; /* common error code is < 0 */
1070 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1072 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1073 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1075 PMD_INIT_FUNC_TRACE(edev);
1078 if (qede_activate_vport(eth_dev, false))
1081 if (qdev->enable_lro)
1082 qede_enable_tpa(eth_dev, false);
1084 /* TODO: Do we need disable LRO or RSS */
1086 qede_stop_queues(eth_dev);
1088 /* Disable traffic */
1089 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1091 /* Bring the link down */
1092 qede_dev_set_link_state(eth_dev, false);
1094 DP_INFO(edev, "Device is stopped\n");
1097 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1099 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1100 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1101 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1103 PMD_INIT_FUNC_TRACE(edev);
1105 /* Check requirements for 100G mode */
1106 if (edev->num_hwfns > 1) {
1107 if (eth_dev->data->nb_rx_queues < 2 ||
1108 eth_dev->data->nb_tx_queues < 2) {
1109 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1113 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1114 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1116 "100G mode needs even no. of RX/TX queues\n");
1121 /* Sanity checks and throw warnings */
1122 if (rxmode->enable_scatter)
1123 eth_dev->data->scattered_rx = 1;
1125 if (!rxmode->hw_strip_crc)
1126 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1128 if (!rxmode->hw_ip_checksum)
1129 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1131 if (rxmode->header_split)
1132 DP_INFO(edev, "Header split enable is not supported\n");
1133 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1135 DP_ERR(edev, "Unsupported multi-queue mode\n");
1138 /* Flow director mode check */
1139 if (qede_check_fdir_support(eth_dev))
1142 /* Deallocate resources if held previously. It is needed only if the
1143 * queue count has been changed from previous configuration. If its
1144 * going to change then it means RX/TX queue setup will be called
1145 * again and the fastpath pointers will be reinitialized there.
1147 if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1148 qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1149 qede_dealloc_fp_resc(eth_dev);
1150 /* Proceed with updated queue count */
1151 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1152 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1153 if (qede_alloc_fp_resc(qdev))
1157 /* VF's MTU has to be set using vport-start where as
1158 * PF's MTU can be updated via vport-update.
1161 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1164 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1168 qdev->mtu = rxmode->max_rx_pkt_len;
1169 qdev->new_mtu = qdev->mtu;
1171 /* Configure TPA parameters */
1172 if (rxmode->enable_lro) {
1173 if (qede_enable_tpa(eth_dev, true))
1175 /* Enable scatter mode for LRO */
1176 if (!rxmode->enable_scatter)
1177 eth_dev->data->scattered_rx = 1;
1179 qdev->enable_lro = rxmode->enable_lro;
1181 /* Enable VLAN offloads by default */
1182 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1183 ETH_VLAN_FILTER_MASK |
1184 ETH_VLAN_EXTEND_MASK);
1186 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1187 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1192 /* Info about HW descriptor ring limitations */
1193 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1194 .nb_max = 0x8000, /* 32K */
1196 .nb_align = 128 /* lowest common multiple */
1199 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1200 .nb_max = 0x8000, /* 32K */
1203 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1204 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1208 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1209 struct rte_eth_dev_info *dev_info)
1211 struct qede_dev *qdev = eth_dev->data->dev_private;
1212 struct ecore_dev *edev = &qdev->edev;
1213 struct qed_link_output link;
1214 uint32_t speed_cap = 0;
1216 PMD_INIT_FUNC_TRACE(edev);
1218 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1219 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1220 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1221 dev_info->rx_desc_lim = qede_rx_desc_lim;
1222 dev_info->tx_desc_lim = qede_tx_desc_lim;
1225 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1226 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1228 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1229 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1230 dev_info->max_tx_queues = dev_info->max_rx_queues;
1232 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1233 dev_info->max_vfs = 0;
1234 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1235 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1236 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1238 dev_info->default_txconf = (struct rte_eth_txconf) {
1239 .txq_flags = QEDE_TXQ_FLAGS,
1242 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
1243 DEV_RX_OFFLOAD_IPV4_CKSUM |
1244 DEV_RX_OFFLOAD_UDP_CKSUM |
1245 DEV_RX_OFFLOAD_TCP_CKSUM |
1246 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1247 DEV_RX_OFFLOAD_TCP_LRO);
1249 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1250 DEV_TX_OFFLOAD_IPV4_CKSUM |
1251 DEV_TX_OFFLOAD_UDP_CKSUM |
1252 DEV_TX_OFFLOAD_TCP_CKSUM |
1253 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1254 DEV_TX_OFFLOAD_TCP_TSO |
1255 DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1257 memset(&link, 0, sizeof(struct qed_link_output));
1258 qdev->ops->common->get_link(edev, &link);
1259 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1260 speed_cap |= ETH_LINK_SPEED_1G;
1261 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1262 speed_cap |= ETH_LINK_SPEED_10G;
1263 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1264 speed_cap |= ETH_LINK_SPEED_25G;
1265 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1266 speed_cap |= ETH_LINK_SPEED_40G;
1267 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1268 speed_cap |= ETH_LINK_SPEED_50G;
1269 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1270 speed_cap |= ETH_LINK_SPEED_100G;
1271 dev_info->speed_capa = speed_cap;
1274 /* return 0 means link status changed, -1 means not changed */
1276 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1278 struct qede_dev *qdev = eth_dev->data->dev_private;
1279 struct ecore_dev *edev = &qdev->edev;
1280 uint16_t link_duplex;
1281 struct qed_link_output link;
1282 struct rte_eth_link *curr = ð_dev->data->dev_link;
1284 memset(&link, 0, sizeof(struct qed_link_output));
1285 qdev->ops->common->get_link(edev, &link);
1288 curr->link_speed = link.speed;
1291 switch (link.duplex) {
1292 case QEDE_DUPLEX_HALF:
1293 link_duplex = ETH_LINK_HALF_DUPLEX;
1295 case QEDE_DUPLEX_FULL:
1296 link_duplex = ETH_LINK_FULL_DUPLEX;
1298 case QEDE_DUPLEX_UNKNOWN:
1302 curr->link_duplex = link_duplex;
1305 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1308 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1309 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1311 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1312 curr->link_speed, curr->link_duplex,
1313 curr->link_autoneg, curr->link_status);
1315 /* return 0 means link status changed, -1 means not changed */
1316 return ((curr->link_status == link.link_up) ? -1 : 0);
1319 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1321 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1322 struct qede_dev *qdev = eth_dev->data->dev_private;
1323 struct ecore_dev *edev = &qdev->edev;
1325 PMD_INIT_FUNC_TRACE(edev);
1328 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1330 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1331 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1333 qed_configure_filter_rx_mode(eth_dev, type);
1336 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1338 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1339 struct qede_dev *qdev = eth_dev->data->dev_private;
1340 struct ecore_dev *edev = &qdev->edev;
1342 PMD_INIT_FUNC_TRACE(edev);
1345 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1346 qed_configure_filter_rx_mode(eth_dev,
1347 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1349 qed_configure_filter_rx_mode(eth_dev,
1350 QED_FILTER_RX_MODE_TYPE_REGULAR);
1353 static void qede_poll_sp_sb_cb(void *param)
1355 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1356 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1357 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1360 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1361 qede_interrupt_action(&edev->hwfns[1]);
1363 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1367 DP_ERR(edev, "Unable to start periodic"
1368 " timer rc %d\n", rc);
1369 assert(false && "Unable to start periodic timer");
1373 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1375 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1376 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1377 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1379 PMD_INIT_FUNC_TRACE(edev);
1381 /* dev_stop() shall cleanup fp resources in hw but without releasing
1382 * dma memories and sw structures so that dev_start() can be called
1383 * by the app without reconfiguration. However, in dev_close() we
1384 * can release all the resources and device can be brought up newly
1386 if (eth_dev->data->dev_started)
1387 qede_dev_stop(eth_dev);
1389 qede_stop_vport(edev);
1390 qede_fdir_dealloc_resc(eth_dev);
1391 qede_dealloc_fp_resc(eth_dev);
1393 eth_dev->data->nb_rx_queues = 0;
1394 eth_dev->data->nb_tx_queues = 0;
1396 qdev->ops->common->slowpath_stop(edev);
1397 qdev->ops->common->remove(edev);
1398 rte_intr_disable(&pci_dev->intr_handle);
1399 rte_intr_callback_unregister(&pci_dev->intr_handle,
1400 qede_interrupt_handler, (void *)eth_dev);
1401 if (edev->num_hwfns > 1)
1402 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1406 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1408 struct qede_dev *qdev = eth_dev->data->dev_private;
1409 struct ecore_dev *edev = &qdev->edev;
1410 struct ecore_eth_stats stats;
1411 unsigned int i = 0, j = 0, qid;
1412 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1413 struct qede_tx_queue *txq;
1415 ecore_get_vport_stats(edev, &stats);
1418 eth_stats->ipackets = stats.rx_ucast_pkts +
1419 stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1421 eth_stats->ibytes = stats.rx_ucast_bytes +
1422 stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1424 eth_stats->ierrors = stats.rx_crc_errors +
1425 stats.rx_align_errors +
1426 stats.rx_carrier_errors +
1427 stats.rx_oversize_packets +
1428 stats.rx_jabbers + stats.rx_undersize_packets;
1430 eth_stats->rx_nombuf = stats.no_buff_discards;
1432 eth_stats->imissed = stats.mftag_filter_discards +
1433 stats.mac_filter_discards +
1434 stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1437 eth_stats->opackets = stats.tx_ucast_pkts +
1438 stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1440 eth_stats->obytes = stats.tx_ucast_bytes +
1441 stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1443 eth_stats->oerrors = stats.tx_err_drop_pkts;
1446 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1447 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1448 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1449 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1450 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1451 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1452 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1453 "Not all the queue stats will be displayed. Set"
1454 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1455 " appropriately and retry.\n");
1458 eth_stats->q_ipackets[i] =
1460 ((char *)(qdev->fp_array[qid].rxq)) +
1461 offsetof(struct qede_rx_queue,
1463 eth_stats->q_errors[i] =
1465 ((char *)(qdev->fp_array[qid].rxq)) +
1466 offsetof(struct qede_rx_queue,
1469 ((char *)(qdev->fp_array[qid].rxq)) +
1470 offsetof(struct qede_rx_queue,
1473 if (i == rxq_stat_cntrs)
1478 txq = qdev->fp_array[qid].txq;
1479 eth_stats->q_opackets[j] =
1480 *((uint64_t *)(uintptr_t)
1481 (((uint64_t)(uintptr_t)(txq)) +
1482 offsetof(struct qede_tx_queue,
1485 if (j == txq_stat_cntrs)
1491 qede_get_xstats_count(struct qede_dev *qdev) {
1492 return RTE_DIM(qede_xstats_strings) +
1493 (RTE_DIM(qede_rxq_xstats_strings) *
1494 RTE_MIN(QEDE_RSS_COUNT(qdev),
1495 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1499 qede_get_xstats_names(struct rte_eth_dev *dev,
1500 struct rte_eth_xstat_name *xstats_names,
1501 __rte_unused unsigned int limit)
1503 struct qede_dev *qdev = dev->data->dev_private;
1504 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1505 unsigned int i, qid, stat_idx = 0;
1506 unsigned int rxq_stat_cntrs;
1508 if (xstats_names != NULL) {
1509 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1510 snprintf(xstats_names[stat_idx].name,
1511 sizeof(xstats_names[stat_idx].name),
1513 qede_xstats_strings[i].name);
1517 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1518 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1519 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1520 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1521 snprintf(xstats_names[stat_idx].name,
1522 sizeof(xstats_names[stat_idx].name),
1524 qede_rxq_xstats_strings[i].name, qid,
1525 qede_rxq_xstats_strings[i].name + 4);
1535 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1538 struct qede_dev *qdev = dev->data->dev_private;
1539 struct ecore_dev *edev = &qdev->edev;
1540 struct ecore_eth_stats stats;
1541 const unsigned int num = qede_get_xstats_count(qdev);
1542 unsigned int i, qid, stat_idx = 0;
1543 unsigned int rxq_stat_cntrs;
1548 ecore_get_vport_stats(edev, &stats);
1550 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1551 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1552 qede_xstats_strings[i].offset);
1553 xstats[stat_idx].id = stat_idx;
1557 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1558 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1559 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1561 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1562 xstats[stat_idx].value = *(uint64_t *)(
1563 ((char *)(qdev->fp_array[qid].rxq)) +
1564 qede_rxq_xstats_strings[i].offset);
1565 xstats[stat_idx].id = stat_idx;
1575 qede_reset_xstats(struct rte_eth_dev *dev)
1577 struct qede_dev *qdev = dev->data->dev_private;
1578 struct ecore_dev *edev = &qdev->edev;
1580 ecore_reset_vport_stats(edev);
1583 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1585 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1586 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1587 struct qed_link_params link_params;
1590 DP_INFO(edev, "setting link state %d\n", link_up);
1591 memset(&link_params, 0, sizeof(link_params));
1592 link_params.link_up = link_up;
1593 rc = qdev->ops->common->set_link(edev, &link_params);
1594 if (rc != ECORE_SUCCESS)
1595 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1600 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1602 return qede_dev_set_link_state(eth_dev, true);
1605 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1607 return qede_dev_set_link_state(eth_dev, false);
1610 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1612 struct qede_dev *qdev = eth_dev->data->dev_private;
1613 struct ecore_dev *edev = &qdev->edev;
1615 ecore_reset_vport_stats(edev);
1618 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1620 enum qed_filter_rx_mode_type type =
1621 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1623 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1624 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1626 qed_configure_filter_rx_mode(eth_dev, type);
1629 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1631 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1632 qed_configure_filter_rx_mode(eth_dev,
1633 QED_FILTER_RX_MODE_TYPE_PROMISC);
1635 qed_configure_filter_rx_mode(eth_dev,
1636 QED_FILTER_RX_MODE_TYPE_REGULAR);
1639 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1640 struct rte_eth_fc_conf *fc_conf)
1642 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1643 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1644 struct qed_link_output current_link;
1645 struct qed_link_params params;
1647 memset(¤t_link, 0, sizeof(current_link));
1648 qdev->ops->common->get_link(edev, ¤t_link);
1650 memset(¶ms, 0, sizeof(params));
1651 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1652 if (fc_conf->autoneg) {
1653 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1654 DP_ERR(edev, "Autoneg not supported\n");
1657 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1660 /* Pause is assumed to be supported (SUPPORTED_Pause) */
1661 if (fc_conf->mode == RTE_FC_FULL)
1662 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1663 QED_LINK_PAUSE_RX_ENABLE);
1664 if (fc_conf->mode == RTE_FC_TX_PAUSE)
1665 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1666 if (fc_conf->mode == RTE_FC_RX_PAUSE)
1667 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1669 params.link_up = true;
1670 (void)qdev->ops->common->set_link(edev, ¶ms);
1675 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1676 struct rte_eth_fc_conf *fc_conf)
1678 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1679 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1680 struct qed_link_output current_link;
1682 memset(¤t_link, 0, sizeof(current_link));
1683 qdev->ops->common->get_link(edev, ¤t_link);
1685 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1686 fc_conf->autoneg = true;
1688 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1689 QED_LINK_PAUSE_TX_ENABLE))
1690 fc_conf->mode = RTE_FC_FULL;
1691 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1692 fc_conf->mode = RTE_FC_RX_PAUSE;
1693 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1694 fc_conf->mode = RTE_FC_TX_PAUSE;
1696 fc_conf->mode = RTE_FC_NONE;
1701 static const uint32_t *
1702 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1704 static const uint32_t ptypes[] = {
1710 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1716 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1719 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
1720 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
1721 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
1722 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
1723 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
1724 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
1725 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
1726 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
1729 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1730 struct rte_eth_rss_conf *rss_conf)
1732 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1733 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1734 struct ecore_sp_vport_update_params vport_update_params;
1735 struct ecore_rss_params rss_params;
1736 struct ecore_hwfn *p_hwfn;
1737 uint32_t *key = (uint32_t *)rss_conf->rss_key;
1738 uint64_t hf = rss_conf->rss_hf;
1739 uint8_t len = rss_conf->rss_key_len;
1744 memset(&vport_update_params, 0, sizeof(vport_update_params));
1745 memset(&rss_params, 0, sizeof(rss_params));
1747 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1748 (unsigned long)hf, len, key);
1752 DP_INFO(edev, "Enabling rss\n");
1755 qede_init_rss_caps(&rss_params.rss_caps, hf);
1756 rss_params.update_rss_capabilities = 1;
1760 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1761 DP_ERR(edev, "RSS key length exceeds limit\n");
1764 DP_INFO(edev, "Applying user supplied hash key\n");
1765 rss_params.update_rss_key = 1;
1766 memcpy(&rss_params.rss_key, key, len);
1768 rss_params.rss_enable = 1;
1771 rss_params.update_rss_config = 1;
1772 /* tbl_size has to be set with capabilities */
1773 rss_params.rss_table_size_log = 7;
1774 vport_update_params.vport_id = 0;
1775 /* pass the L2 handles instead of qids */
1776 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1777 idx = qdev->rss_ind_table[i];
1778 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1780 vport_update_params.rss_params = &rss_params;
1782 for_each_hwfn(edev, i) {
1783 p_hwfn = &edev->hwfns[i];
1784 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1785 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1786 ECORE_SPQ_MODE_EBLOCK, NULL);
1788 DP_ERR(edev, "vport-update for RSS failed\n");
1792 qdev->rss_enable = rss_params.rss_enable;
1794 /* Update local structure for hash query */
1795 qdev->rss_conf.rss_hf = hf;
1796 qdev->rss_conf.rss_key_len = len;
1797 if (qdev->rss_enable) {
1798 if (qdev->rss_conf.rss_key == NULL) {
1799 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1800 if (qdev->rss_conf.rss_key == NULL) {
1801 DP_ERR(edev, "No memory to store RSS key\n");
1806 DP_INFO(edev, "Storing RSS key\n");
1807 memcpy(qdev->rss_conf.rss_key, key, len);
1809 } else if (!qdev->rss_enable && len == 0) {
1810 if (qdev->rss_conf.rss_key) {
1811 free(qdev->rss_conf.rss_key);
1812 qdev->rss_conf.rss_key = NULL;
1813 DP_INFO(edev, "Free RSS key\n");
1820 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1821 struct rte_eth_rss_conf *rss_conf)
1823 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1825 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1826 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1828 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1829 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1830 rss_conf->rss_key_len);
1834 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1835 struct ecore_rss_params *rss)
1838 bool rss_mode = 1; /* enable */
1839 struct ecore_queue_cid *cid;
1840 struct ecore_rss_params *t_rss;
1842 /* In regular scenario, we'd simply need to take input handlers.
1843 * But in CMT, we'd have to split the handlers according to the
1844 * engine they were configured on. We'd then have to understand
1845 * whether RSS is really required, since 2-queues on CMT doesn't
1849 /* CMT should be round-robin */
1850 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1851 cid = rss->rss_ind_table[i];
1853 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
1858 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
1862 t_rss->update_rss_ind_table = 1;
1863 t_rss->rss_table_size_log = 7;
1864 t_rss->update_rss_config = 1;
1866 /* Make sure RSS is actually required */
1867 for_each_hwfn(edev, fn) {
1868 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
1870 if (rss[fn].rss_ind_table[i] !=
1871 rss[fn].rss_ind_table[0])
1875 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
1877 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1884 t_rss->rss_enable = rss_mode;
1889 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1890 struct rte_eth_rss_reta_entry64 *reta_conf,
1893 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1894 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1895 struct ecore_sp_vport_update_params vport_update_params;
1896 struct ecore_rss_params *params;
1897 struct ecore_hwfn *p_hwfn;
1898 uint16_t i, idx, shift;
1902 if (reta_size > ETH_RSS_RETA_SIZE_128) {
1903 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1908 memset(&vport_update_params, 0, sizeof(vport_update_params));
1909 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
1910 RTE_CACHE_LINE_SIZE);
1912 for (i = 0; i < reta_size; i++) {
1913 idx = i / RTE_RETA_GROUP_SIZE;
1914 shift = i % RTE_RETA_GROUP_SIZE;
1915 if (reta_conf[idx].mask & (1ULL << shift)) {
1916 entry = reta_conf[idx].reta[shift];
1917 /* Pass rxq handles to ecore */
1918 params->rss_ind_table[i] =
1919 qdev->fp_array[entry].rxq->handle;
1920 /* Update the local copy for RETA query command */
1921 qdev->rss_ind_table[i] = entry;
1925 params->update_rss_ind_table = 1;
1926 params->rss_table_size_log = 7;
1927 params->update_rss_config = 1;
1929 /* Fix up RETA for CMT mode device */
1930 if (edev->num_hwfns > 1)
1931 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
1933 vport_update_params.vport_id = 0;
1934 /* Use the current value of rss_enable */
1935 params->rss_enable = qdev->rss_enable;
1936 vport_update_params.rss_params = params;
1938 for_each_hwfn(edev, i) {
1939 p_hwfn = &edev->hwfns[i];
1940 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1941 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1942 ECORE_SPQ_MODE_EBLOCK, NULL);
1944 DP_ERR(edev, "vport-update for RSS failed\n");
1954 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1955 struct rte_eth_rss_reta_entry64 *reta_conf,
1958 struct qede_dev *qdev = eth_dev->data->dev_private;
1959 struct ecore_dev *edev = &qdev->edev;
1960 uint16_t i, idx, shift;
1963 if (reta_size > ETH_RSS_RETA_SIZE_128) {
1964 DP_ERR(edev, "reta_size %d is not supported\n",
1969 for (i = 0; i < reta_size; i++) {
1970 idx = i / RTE_RETA_GROUP_SIZE;
1971 shift = i % RTE_RETA_GROUP_SIZE;
1972 if (reta_conf[idx].mask & (1ULL << shift)) {
1973 entry = qdev->rss_ind_table[i];
1974 reta_conf[idx].reta[shift] = entry;
1983 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1985 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
1986 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1987 struct rte_eth_dev_info dev_info = {0};
1988 struct qede_fastpath *fp;
1989 uint32_t frame_size;
1990 uint16_t rx_buf_size;
1994 PMD_INIT_FUNC_TRACE(edev);
1995 qede_dev_info_get(dev, &dev_info);
1996 frame_size = mtu + QEDE_ETH_OVERHEAD;
1997 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
1998 DP_ERR(edev, "MTU %u out of range\n", mtu);
2001 if (!dev->data->scattered_rx &&
2002 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2003 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2004 dev->data->min_rx_buf_size);
2007 /* Temporarily replace I/O functions with dummy ones. It cannot
2008 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2010 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2011 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2015 /* Fix up RX buf size for all queues of the port */
2017 fp = &qdev->fp_array[i];
2018 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2019 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2020 if (dev->data->scattered_rx)
2021 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2023 rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2024 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2025 fp->rxq->rx_buf_size = rx_buf_size;
2026 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2028 qede_dev_start(dev);
2029 if (frame_size > ETHER_MAX_LEN)
2030 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2032 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2033 /* update max frame size */
2034 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2036 dev->rx_pkt_burst = qede_recv_pkts;
2037 dev->tx_pkt_burst = qede_xmit_pkts;
2043 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2044 struct rte_eth_udp_tunnel *tunnel_udp,
2047 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2048 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2049 struct ecore_tunnel_info tunn; /* @DPDK */
2050 struct ecore_hwfn *p_hwfn;
2053 PMD_INIT_FUNC_TRACE(edev);
2055 memset(&tunn, 0, sizeof(tunn));
2056 if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2057 tunn.vxlan_port.b_update_port = true;
2058 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
2059 QEDE_VXLAN_DEF_PORT;
2060 for_each_hwfn(edev, i) {
2061 p_hwfn = &edev->hwfns[i];
2062 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
2063 ECORE_SPQ_MODE_CB, NULL);
2064 if (rc != ECORE_SUCCESS) {
2065 DP_ERR(edev, "Unable to config UDP port %u\n",
2066 tunn.vxlan_port.port);
2076 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2077 struct rte_eth_udp_tunnel *tunnel_udp)
2079 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2083 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2084 struct rte_eth_udp_tunnel *tunnel_udp)
2086 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2089 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2090 uint32_t *clss, char *str)
2093 *clss = MAX_ECORE_TUNN_CLSS;
2095 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2096 if (filter == qede_tunn_types[j].rte_filter_type) {
2097 *type = qede_tunn_types[j].qede_type;
2098 *clss = qede_tunn_types[j].qede_tunn_clss;
2099 strcpy(str, qede_tunn_types[j].string);
2106 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2107 const struct rte_eth_tunnel_filter_conf *conf,
2110 /* Init commmon ucast params first */
2111 qede_set_ucast_cmn_params(ucast);
2113 /* Copy out the required fields based on classification type */
2117 case ECORE_FILTER_VNI:
2118 ucast->vni = conf->tenant_id;
2120 case ECORE_FILTER_INNER_VLAN:
2121 ucast->vlan = conf->inner_vlan;
2123 case ECORE_FILTER_MAC:
2124 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2127 case ECORE_FILTER_INNER_MAC:
2128 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2131 case ECORE_FILTER_MAC_VNI_PAIR:
2132 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2134 ucast->vni = conf->tenant_id;
2136 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2137 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2139 ucast->vni = conf->tenant_id;
2141 case ECORE_FILTER_INNER_PAIR:
2142 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2144 ucast->vlan = conf->inner_vlan;
2150 return ECORE_SUCCESS;
2153 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2154 enum rte_filter_op filter_op,
2155 const struct rte_eth_tunnel_filter_conf *conf)
2157 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2158 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2159 struct ecore_tunnel_info tunn;
2160 struct ecore_hwfn *p_hwfn;
2161 enum ecore_filter_ucast_type type;
2162 enum ecore_tunn_clss clss;
2163 struct ecore_filter_ucast ucast;
2165 uint16_t filter_type;
2168 PMD_INIT_FUNC_TRACE(edev);
2170 filter_type = conf->filter_type | qdev->vxlan_filter_type;
2171 /* First determine if the given filter classification is supported */
2172 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2173 if (clss == MAX_ECORE_TUNN_CLSS) {
2174 DP_ERR(edev, "Wrong filter type\n");
2177 /* Init tunnel ucast params */
2178 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2179 if (rc != ECORE_SUCCESS) {
2180 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2184 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2185 str, filter_op, ucast.type);
2186 switch (filter_op) {
2187 case RTE_ETH_FILTER_ADD:
2188 ucast.opcode = ECORE_FILTER_ADD;
2190 /* Skip MAC/VLAN if filter is based on VNI */
2191 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2192 rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2194 /* Enable accept anyvlan */
2195 qede_config_accept_any_vlan(qdev, true);
2198 rc = qede_ucast_filter(eth_dev, &ucast, 1);
2200 rc = ecore_filter_ucast_cmd(edev, &ucast,
2201 ECORE_SPQ_MODE_CB, NULL);
2204 if (rc != ECORE_SUCCESS)
2207 qdev->vxlan_filter_type = filter_type;
2209 DP_INFO(edev, "Enabling VXLAN tunneling\n");
2210 qede_set_cmn_tunn_param(&tunn, clss, true, true);
2211 for_each_hwfn(edev, i) {
2212 p_hwfn = &edev->hwfns[i];
2213 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
2214 &tunn, ECORE_SPQ_MODE_CB, NULL);
2215 if (rc != ECORE_SUCCESS) {
2216 DP_ERR(edev, "Failed to update tunn_clss %u\n",
2217 tunn.vxlan.tun_cls);
2220 qdev->num_tunn_filters++; /* Filter added successfully */
2222 case RTE_ETH_FILTER_DELETE:
2223 ucast.opcode = ECORE_FILTER_REMOVE;
2225 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2226 rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2228 rc = qede_ucast_filter(eth_dev, &ucast, 0);
2230 rc = ecore_filter_ucast_cmd(edev, &ucast,
2231 ECORE_SPQ_MODE_CB, NULL);
2233 if (rc != ECORE_SUCCESS)
2236 qdev->vxlan_filter_type = filter_type;
2237 qdev->num_tunn_filters--;
2239 /* Disable VXLAN if VXLAN filters become 0 */
2240 if (qdev->num_tunn_filters == 0) {
2241 DP_INFO(edev, "Disabling VXLAN tunneling\n");
2243 /* Use 0 as tunnel mode */
2244 qede_set_cmn_tunn_param(&tunn, clss, false, true);
2245 for_each_hwfn(edev, i) {
2246 p_hwfn = &edev->hwfns[i];
2247 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
2248 ECORE_SPQ_MODE_CB, NULL);
2249 if (rc != ECORE_SUCCESS) {
2251 "Failed to update tunn_clss %u\n",
2252 tunn.vxlan.tun_cls);
2259 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2262 DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
2267 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2268 enum rte_filter_type filter_type,
2269 enum rte_filter_op filter_op,
2272 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2273 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2274 struct rte_eth_tunnel_filter_conf *filter_conf =
2275 (struct rte_eth_tunnel_filter_conf *)arg;
2277 switch (filter_type) {
2278 case RTE_ETH_FILTER_TUNNEL:
2279 switch (filter_conf->tunnel_type) {
2280 case RTE_TUNNEL_TYPE_VXLAN:
2282 "Packet steering to the specified Rx queue"
2283 " is not supported with VXLAN tunneling");
2284 return(qede_vxlan_tunn_config(eth_dev, filter_op,
2286 /* Place holders for future tunneling support */
2287 case RTE_TUNNEL_TYPE_GENEVE:
2288 case RTE_TUNNEL_TYPE_TEREDO:
2289 case RTE_TUNNEL_TYPE_NVGRE:
2290 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2291 case RTE_L2_TUNNEL_TYPE_E_TAG:
2292 DP_ERR(edev, "Unsupported tunnel type %d\n",
2293 filter_conf->tunnel_type);
2295 case RTE_TUNNEL_TYPE_NONE:
2300 case RTE_ETH_FILTER_FDIR:
2301 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2302 case RTE_ETH_FILTER_NTUPLE:
2303 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2304 case RTE_ETH_FILTER_MACVLAN:
2305 case RTE_ETH_FILTER_ETHERTYPE:
2306 case RTE_ETH_FILTER_FLEXIBLE:
2307 case RTE_ETH_FILTER_SYN:
2308 case RTE_ETH_FILTER_HASH:
2309 case RTE_ETH_FILTER_L2_TUNNEL:
2310 case RTE_ETH_FILTER_MAX:
2312 DP_ERR(edev, "Unsupported filter type %d\n",
2320 static const struct eth_dev_ops qede_eth_dev_ops = {
2321 .dev_configure = qede_dev_configure,
2322 .dev_infos_get = qede_dev_info_get,
2323 .rx_queue_setup = qede_rx_queue_setup,
2324 .rx_queue_release = qede_rx_queue_release,
2325 .tx_queue_setup = qede_tx_queue_setup,
2326 .tx_queue_release = qede_tx_queue_release,
2327 .dev_start = qede_dev_start,
2328 .dev_set_link_up = qede_dev_set_link_up,
2329 .dev_set_link_down = qede_dev_set_link_down,
2330 .link_update = qede_link_update,
2331 .promiscuous_enable = qede_promiscuous_enable,
2332 .promiscuous_disable = qede_promiscuous_disable,
2333 .allmulticast_enable = qede_allmulticast_enable,
2334 .allmulticast_disable = qede_allmulticast_disable,
2335 .dev_stop = qede_dev_stop,
2336 .dev_close = qede_dev_close,
2337 .stats_get = qede_get_stats,
2338 .stats_reset = qede_reset_stats,
2339 .xstats_get = qede_get_xstats,
2340 .xstats_reset = qede_reset_xstats,
2341 .xstats_get_names = qede_get_xstats_names,
2342 .mac_addr_add = qede_mac_addr_add,
2343 .mac_addr_remove = qede_mac_addr_remove,
2344 .mac_addr_set = qede_mac_addr_set,
2345 .vlan_offload_set = qede_vlan_offload_set,
2346 .vlan_filter_set = qede_vlan_filter_set,
2347 .flow_ctrl_set = qede_flow_ctrl_set,
2348 .flow_ctrl_get = qede_flow_ctrl_get,
2349 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2350 .rss_hash_update = qede_rss_hash_update,
2351 .rss_hash_conf_get = qede_rss_hash_conf_get,
2352 .reta_update = qede_rss_reta_update,
2353 .reta_query = qede_rss_reta_query,
2354 .mtu_set = qede_set_mtu,
2355 .filter_ctrl = qede_dev_filter_ctrl,
2356 .udp_tunnel_port_add = qede_udp_dst_port_add,
2357 .udp_tunnel_port_del = qede_udp_dst_port_del,
2360 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2361 .dev_configure = qede_dev_configure,
2362 .dev_infos_get = qede_dev_info_get,
2363 .rx_queue_setup = qede_rx_queue_setup,
2364 .rx_queue_release = qede_rx_queue_release,
2365 .tx_queue_setup = qede_tx_queue_setup,
2366 .tx_queue_release = qede_tx_queue_release,
2367 .dev_start = qede_dev_start,
2368 .dev_set_link_up = qede_dev_set_link_up,
2369 .dev_set_link_down = qede_dev_set_link_down,
2370 .link_update = qede_link_update,
2371 .promiscuous_enable = qede_promiscuous_enable,
2372 .promiscuous_disable = qede_promiscuous_disable,
2373 .allmulticast_enable = qede_allmulticast_enable,
2374 .allmulticast_disable = qede_allmulticast_disable,
2375 .dev_stop = qede_dev_stop,
2376 .dev_close = qede_dev_close,
2377 .stats_get = qede_get_stats,
2378 .stats_reset = qede_reset_stats,
2379 .xstats_get = qede_get_xstats,
2380 .xstats_reset = qede_reset_xstats,
2381 .xstats_get_names = qede_get_xstats_names,
2382 .vlan_offload_set = qede_vlan_offload_set,
2383 .vlan_filter_set = qede_vlan_filter_set,
2384 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2385 .rss_hash_update = qede_rss_hash_update,
2386 .rss_hash_conf_get = qede_rss_hash_conf_get,
2387 .reta_update = qede_rss_reta_update,
2388 .reta_query = qede_rss_reta_query,
2389 .mtu_set = qede_set_mtu,
2392 static void qede_update_pf_params(struct ecore_dev *edev)
2394 struct ecore_pf_params pf_params;
2396 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2397 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2398 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2399 qed_ops->common->update_pf_params(edev, &pf_params);
2402 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2404 struct rte_pci_device *pci_dev;
2405 struct rte_pci_addr pci_addr;
2406 struct qede_dev *adapter;
2407 struct ecore_dev *edev;
2408 struct qed_dev_eth_info dev_info;
2409 struct qed_slowpath_params params;
2410 static bool do_once = true;
2411 uint8_t bulletin_change;
2412 uint8_t vf_mac[ETHER_ADDR_LEN];
2413 uint8_t is_mac_forced;
2415 /* Fix up ecore debug level */
2416 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2417 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2420 /* Extract key data structures */
2421 adapter = eth_dev->data->dev_private;
2422 edev = &adapter->edev;
2423 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2424 pci_addr = pci_dev->addr;
2426 PMD_INIT_FUNC_TRACE(edev);
2428 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2429 pci_addr.bus, pci_addr.devid, pci_addr.function,
2430 eth_dev->data->port_id);
2432 eth_dev->rx_pkt_burst = qede_recv_pkts;
2433 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2434 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2436 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2437 DP_ERR(edev, "Skipping device init from secondary process\n");
2441 rte_eth_copy_pci_info(eth_dev, pci_dev);
2444 edev->vendor_id = pci_dev->id.vendor_id;
2445 edev->device_id = pci_dev->id.device_id;
2447 qed_ops = qed_get_eth_ops();
2449 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2453 DP_INFO(edev, "Starting qede probe\n");
2454 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2457 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2460 qede_update_pf_params(edev);
2461 rte_intr_callback_register(&pci_dev->intr_handle,
2462 qede_interrupt_handler, (void *)eth_dev);
2463 if (rte_intr_enable(&pci_dev->intr_handle)) {
2464 DP_ERR(edev, "rte_intr_enable() failed\n");
2468 /* Start the Slowpath-process */
2469 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2470 params.int_mode = ECORE_INT_MODE_MSIX;
2471 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2472 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2473 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2474 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2475 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2476 QEDE_PMD_DRV_VER_STR_SIZE);
2478 /* For CMT mode device do periodic polling for slowpath events.
2479 * This is required since uio device uses only one MSI-x
2480 * interrupt vector but we need one for each engine.
2482 if (edev->num_hwfns > 1 && IS_PF(edev)) {
2483 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2487 DP_ERR(edev, "Unable to start periodic"
2488 " timer rc %d\n", rc);
2493 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2495 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2496 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2501 rc = qed_ops->fill_dev_info(edev, &dev_info);
2503 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2504 qed_ops->common->slowpath_stop(edev);
2505 qed_ops->common->remove(edev);
2506 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2511 qede_alloc_etherdev(adapter, &dev_info);
2513 adapter->ops->common->set_name(edev, edev->name);
2516 adapter->dev_info.num_mac_filters =
2517 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2520 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2521 (uint32_t *)&adapter->dev_info.num_mac_filters);
2523 /* Allocate memory for storing MAC addr */
2524 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2526 adapter->dev_info.num_mac_filters),
2527 RTE_CACHE_LINE_SIZE);
2529 if (eth_dev->data->mac_addrs == NULL) {
2530 DP_ERR(edev, "Failed to allocate MAC address\n");
2531 qed_ops->common->slowpath_stop(edev);
2532 qed_ops->common->remove(edev);
2533 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2539 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2540 hw_info.hw_mac_addr,
2541 ð_dev->data->mac_addrs[0]);
2542 ether_addr_copy(ð_dev->data->mac_addrs[0],
2543 &adapter->primary_mac);
2545 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2547 if (bulletin_change) {
2549 ecore_vf_bulletin_get_forced_mac(
2550 ECORE_LEADING_HWFN(edev),
2553 if (is_mac_exist && is_mac_forced) {
2554 DP_INFO(edev, "VF macaddr received from PF\n");
2555 ether_addr_copy((struct ether_addr *)&vf_mac,
2556 ð_dev->data->mac_addrs[0]);
2557 ether_addr_copy(ð_dev->data->mac_addrs[0],
2558 &adapter->primary_mac);
2560 DP_ERR(edev, "No VF macaddr assigned\n");
2565 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2568 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2569 qede_print_adapter_info(adapter);
2574 adapter->num_tx_queues = 0;
2575 adapter->num_rx_queues = 0;
2576 SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2577 SLIST_INIT(&adapter->vlan_list_head);
2578 SLIST_INIT(&adapter->uc_list_head);
2579 adapter->mtu = ETHER_MTU;
2580 adapter->new_mtu = ETHER_MTU;
2582 if (qede_start_vport(adapter, adapter->mtu))
2585 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2586 adapter->primary_mac.addr_bytes[0],
2587 adapter->primary_mac.addr_bytes[1],
2588 adapter->primary_mac.addr_bytes[2],
2589 adapter->primary_mac.addr_bytes[3],
2590 adapter->primary_mac.addr_bytes[4],
2591 adapter->primary_mac.addr_bytes[5]);
2593 DP_INFO(edev, "Device initialized\n");
2598 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2600 return qede_common_dev_init(eth_dev, 1);
2603 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2605 return qede_common_dev_init(eth_dev, 0);
2608 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2610 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2611 struct qede_dev *qdev = eth_dev->data->dev_private;
2612 struct ecore_dev *edev = &qdev->edev;
2614 PMD_INIT_FUNC_TRACE(edev);
2617 /* only uninitialize in the primary process */
2618 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2621 /* safe to close dev here */
2622 qede_dev_close(eth_dev);
2624 eth_dev->dev_ops = NULL;
2625 eth_dev->rx_pkt_burst = NULL;
2626 eth_dev->tx_pkt_burst = NULL;
2628 if (eth_dev->data->mac_addrs)
2629 rte_free(eth_dev->data->mac_addrs);
2631 eth_dev->data->mac_addrs = NULL;
2636 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2638 return qede_dev_common_uninit(eth_dev);
2641 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2643 return qede_dev_common_uninit(eth_dev);
2646 static const struct rte_pci_id pci_id_qedevf_map[] = {
2647 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2649 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2652 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2655 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2660 static const struct rte_pci_id pci_id_qede_map[] = {
2661 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2663 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2666 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2669 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2672 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2675 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2678 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2681 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2684 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2687 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2690 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2695 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2696 struct rte_pci_device *pci_dev)
2698 return rte_eth_dev_pci_generic_probe(pci_dev,
2699 sizeof(struct qede_dev), qedevf_eth_dev_init);
2702 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2704 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2707 static struct rte_pci_driver rte_qedevf_pmd = {
2708 .id_table = pci_id_qedevf_map,
2709 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2710 .probe = qedevf_eth_dev_pci_probe,
2711 .remove = qedevf_eth_dev_pci_remove,
2714 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2715 struct rte_pci_device *pci_dev)
2717 return rte_eth_dev_pci_generic_probe(pci_dev,
2718 sizeof(struct qede_dev), qede_eth_dev_init);
2721 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2723 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2726 static struct rte_pci_driver rte_qede_pmd = {
2727 .id_table = pci_id_qede_map,
2728 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2729 .probe = qede_eth_dev_pci_probe,
2730 .remove = qede_eth_dev_pci_remove,
2733 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2734 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2735 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2736 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2737 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2738 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");