drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12 #include <rte_kvargs.h>
  13
  14 /* Globals */
  15 int qede_logtype_init;
  16 int qede_logtype_driver;
  17
  18 static const struct qed_eth_ops *qed_ops;
  19 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  20
  21 /* VXLAN tunnel classification mapping */
  22 const struct _qede_udp_tunn_types {
  23         uint16_t rte_filter_type;
  24         enum ecore_filter_ucast_type qede_type;
  25         enum ecore_tunn_clss qede_tunn_clss;
  26         const char *string;
  27 } qede_tunn_types[] = {
  28         {
  29                 ETH_TUNNEL_FILTER_OMAC,
  30                 ECORE_FILTER_MAC,
  31                 ECORE_TUNN_CLSS_MAC_VLAN,
  32                 "outer-mac"
  33         },
  34         {
  35                 ETH_TUNNEL_FILTER_TENID,
  36                 ECORE_FILTER_VNI,
  37                 ECORE_TUNN_CLSS_MAC_VNI,
  38                 "vni"
  39         },
  40         {
  41                 ETH_TUNNEL_FILTER_IMAC,
  42                 ECORE_FILTER_INNER_MAC,
  43                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  44                 "inner-mac"
  45         },
  46         {
  47                 ETH_TUNNEL_FILTER_IVLAN,
  48                 ECORE_FILTER_INNER_VLAN,
  49                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  50                 "inner-vlan"
  51         },
  52         {
  53                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  54                 ECORE_FILTER_MAC_VNI_PAIR,
  55                 ECORE_TUNN_CLSS_MAC_VNI,
  56                 "outer-mac and vni"
  57         },
  58         {
  59                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  60                 ECORE_FILTER_UNUSED,
  61                 MAX_ECORE_TUNN_CLSS,
  62                 "outer-mac and inner-mac"
  63         },
  64         {
  65                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  66                 ECORE_FILTER_UNUSED,
  67                 MAX_ECORE_TUNN_CLSS,
  68                 "outer-mac and inner-vlan"
  69         },
  70         {
  71                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  72                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  73                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  74                 "vni and inner-mac",
  75         },
  76         {
  77                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  78                 ECORE_FILTER_UNUSED,
  79                 MAX_ECORE_TUNN_CLSS,
  80                 "vni and inner-vlan",
  81         },
  82         {
  83                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  84                 ECORE_FILTER_INNER_PAIR,
  85                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  86                 "inner-mac and inner-vlan",
  87         },
  88         {
  89                 ETH_TUNNEL_FILTER_OIP,
  90                 ECORE_FILTER_UNUSED,
  91                 MAX_ECORE_TUNN_CLSS,
  92                 "outer-IP"
  93         },
  94         {
  95                 ETH_TUNNEL_FILTER_IIP,
  96                 ECORE_FILTER_UNUSED,
  97                 MAX_ECORE_TUNN_CLSS,
  98                 "inner-IP"
  99         },
 100         {
 101                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
 102                 ECORE_FILTER_UNUSED,
 103                 MAX_ECORE_TUNN_CLSS,
 104                 "IMAC_IVLAN"
 105         },
 106         {
 107                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 108                 ECORE_FILTER_UNUSED,
 109                 MAX_ECORE_TUNN_CLSS,
 110                 "IMAC_IVLAN_TENID"
 111         },
 112         {
 113                 RTE_TUNNEL_FILTER_IMAC_TENID,
 114                 ECORE_FILTER_UNUSED,
 115                 MAX_ECORE_TUNN_CLSS,
 116                 "IMAC_TENID"
 117         },
 118         {
 119                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 120                 ECORE_FILTER_UNUSED,
 121                 MAX_ECORE_TUNN_CLSS,
 122                 "OMAC_TENID_IMAC"
 123         },
 124 };
 125
 126 struct rte_qede_xstats_name_off {
 127         char name[RTE_ETH_XSTATS_NAME_SIZE];
 128         uint64_t offset;
 129 };
 130
 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 132         {"rx_unicast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 134         {"rx_multicast_bytes",
 135                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 136         {"rx_broadcast_bytes",
 137                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 138         {"rx_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 140         {"rx_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 142         {"rx_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 144
 145         {"tx_unicast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 147         {"tx_multicast_bytes",
 148                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 149         {"tx_broadcast_bytes",
 150                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 151         {"tx_unicast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 153         {"tx_multicast_packets",
 154                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 155         {"tx_broadcast_packets",
 156                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 157
 158         {"rx_64_byte_packets",
 159                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 160         {"rx_65_to_127_byte_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          rx_65_to_127_byte_packets)},
 163         {"rx_128_to_255_byte_packets",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          rx_128_to_255_byte_packets)},
 166         {"rx_256_to_511_byte_packets",
 167                 offsetof(struct ecore_eth_stats_common,
 168                          rx_256_to_511_byte_packets)},
 169         {"rx_512_to_1023_byte_packets",
 170                 offsetof(struct ecore_eth_stats_common,
 171                          rx_512_to_1023_byte_packets)},
 172         {"rx_1024_to_1518_byte_packets",
 173                 offsetof(struct ecore_eth_stats_common,
 174                          rx_1024_to_1518_byte_packets)},
 175         {"tx_64_byte_packets",
 176                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 177         {"tx_65_to_127_byte_packets",
 178                 offsetof(struct ecore_eth_stats_common,
 179                          tx_65_to_127_byte_packets)},
 180         {"tx_128_to_255_byte_packets",
 181                 offsetof(struct ecore_eth_stats_common,
 182                          tx_128_to_255_byte_packets)},
 183         {"tx_256_to_511_byte_packets",
 184                 offsetof(struct ecore_eth_stats_common,
 185                          tx_256_to_511_byte_packets)},
 186         {"tx_512_to_1023_byte_packets",
 187                 offsetof(struct ecore_eth_stats_common,
 188                          tx_512_to_1023_byte_packets)},
 189         {"tx_1024_to_1518_byte_packets",
 190                 offsetof(struct ecore_eth_stats_common,
 191                          tx_1024_to_1518_byte_packets)},
 192
 193         {"rx_mac_crtl_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 195         {"tx_mac_control_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 197         {"rx_pause_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 199         {"tx_pause_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 205
 206         {"rx_crc_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 208         {"rx_align_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 210         {"rx_carrier_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 212         {"rx_oversize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 214         {"rx_jabber_errors",
 215                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 216         {"rx_undersize_packet_errors",
 217                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 218         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 219         {"rx_host_buffer_not_available",
 220                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 221         /* Number of packets discarded because they are bigger than MTU */
 222         {"rx_packet_too_big_discards",
 223                 offsetof(struct ecore_eth_stats_common,
 224                          packet_too_big_discard)},
 225         {"rx_ttl_zero_discards",
 226                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 227         {"rx_multi_function_tag_filter_discards",
 228                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 229         {"rx_mac_filter_discards",
 230                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 231         {"rx_hw_buffer_truncates",
 232                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 233         {"rx_hw_buffer_discards",
 234                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats_common,
 263                          tpa_not_coalesced_pkts)},
 264         {"lro_coalesced_bytes",
 265                 offsetof(struct ecore_eth_stats_common,
 266                          tpa_coalesced_bytes)},
 267 };
 268
 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 270         {"rx_1519_to_1522_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_1522_byte_packets)},
 274         {"rx_1519_to_2047_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_1519_to_2047_byte_packets)},
 278         {"rx_2048_to_4095_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_2048_to_4095_byte_packets)},
 282         {"rx_4096_to_9216_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_4096_to_9216_byte_packets)},
 286         {"rx_9217_to_16383_byte_packets",
 287                 offsetof(struct ecore_eth_stats, bb) +
 288                 offsetof(struct ecore_eth_stats_bb,
 289                          rx_9217_to_16383_byte_packets)},
 290
 291         {"tx_1519_to_2047_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_1519_to_2047_byte_packets)},
 295         {"tx_2048_to_4095_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_2048_to_4095_byte_packets)},
 299         {"tx_4096_to_9216_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_4096_to_9216_byte_packets)},
 303         {"tx_9217_to_16383_byte_packets",
 304                 offsetof(struct ecore_eth_stats, bb) +
 305                 offsetof(struct ecore_eth_stats_bb,
 306                          tx_9217_to_16383_byte_packets)},
 307
 308         {"tx_lpi_entry_count",
 309                 offsetof(struct ecore_eth_stats, bb) +
 310                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 311         {"tx_total_collisions",
 312                 offsetof(struct ecore_eth_stats, bb) +
 313                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 314 };
 315
 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 317         {"rx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          rx_1519_to_max_byte_packets)},
 321         {"tx_1519_to_max_byte_packets",
 322                 offsetof(struct ecore_eth_stats, ah) +
 323                 offsetof(struct ecore_eth_stats_ah,
 324                          tx_1519_to_max_byte_packets)},
 325 };
 326
 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 328         {"rx_q_segments",
 329                 offsetof(struct qede_rx_queue, rx_segs)},
 330         {"rx_q_hw_errors",
 331                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 332         {"rx_q_allocation_errors",
 333                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 334 };
 335
 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 337 {
 338         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 339 }
 340
 341 static void
 342 qede_interrupt_handler(void *param)
 343 {
 344         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 345         struct qede_dev *qdev = eth_dev->data->dev_private;
 346         struct ecore_dev *edev = &qdev->edev;
 347
 348         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 349         if (rte_intr_enable(eth_dev->intr_handle))
 350                 DP_ERR(edev, "rte_intr_enable failed\n");
 351 }
 352
 353 static void
 354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 355 {
 356         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 357         qdev->ops = qed_ops;
 358 }
 359
 360 static void qede_print_adapter_info(struct qede_dev *qdev)
 361 {
 362         struct ecore_dev *edev = &qdev->edev;
 363         struct qed_dev_info *info = &qdev->dev_info.common;
 364         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 365         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 366
 367         DP_INFO(edev, "*********************************\n");
 368         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 369         DP_INFO(edev, " Chip details : %s %c%d\n",
 370                   ECORE_IS_BB(edev) ? "BB" : "AH",
 371                   'A' + edev->chip_rev,
 372                   (int)edev->chip_metal);
 373         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 374                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 375         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 376                  ver_str, QEDE_PMD_VERSION);
 377         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 378         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 379
 380         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 381                  "%d.%d.%d.%d",
 382                 (info->mfw_rev >> 24) & 0xff,
 383                 (info->mfw_rev >> 16) & 0xff,
 384                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 385         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 386         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 387         DP_INFO(edev, "*********************************\n");
 388 }
 389
 390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 391 {
 392         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 393         unsigned int i = 0, j = 0, qid;
 394         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 395         struct qede_tx_queue *txq;
 396
 397         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 398
 399         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 400                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 401         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 402                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 403
 404         for_each_rss(qid) {
 405                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 406                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 407                             sizeof(uint64_t));
 408                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 409                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 410                             sizeof(uint64_t));
 411                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 412                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 413                             sizeof(uint64_t));
 414
 415                 if (xstats)
 416                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 417                                 OSAL_MEMSET((((char *)
 418                                               (qdev->fp_array[qid].rxq)) +
 419                                              qede_rxq_xstats_strings[j].offset),
 420                                             0,
 421                                             sizeof(uint64_t));
 422
 423                 i++;
 424                 if (i == rxq_stat_cntrs)
 425                         break;
 426         }
 427
 428         i = 0;
 429
 430         for_each_tss(qid) {
 431                 txq = qdev->fp_array[qid].txq;
 432
 433                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 434                                 (((uint64_t)(uintptr_t)(txq)) +
 435                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 436                             sizeof(uint64_t));
 437
 438                 i++;
 439                 if (i == txq_stat_cntrs)
 440                         break;
 441         }
 442 }
 443
 444 static int
 445 qede_stop_vport(struct ecore_dev *edev)
 446 {
 447         struct ecore_hwfn *p_hwfn;
 448         uint8_t vport_id;
 449         int rc;
 450         int i;
 451
 452         vport_id = 0;
 453         for_each_hwfn(edev, i) {
 454                 p_hwfn = &edev->hwfns[i];
 455                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 456                                          vport_id);
 457                 if (rc != ECORE_SUCCESS) {
 458                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 459                         return rc;
 460                 }
 461         }
 462
 463         DP_INFO(edev, "vport stopped\n");
 464
 465         return 0;
 466 }
 467
 468 static int
 469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 470 {
 471         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 472         struct ecore_sp_vport_start_params params;
 473         struct ecore_hwfn *p_hwfn;
 474         int rc;
 475         int i;
 476
 477         if (qdev->vport_started)
 478                 qede_stop_vport(edev);
 479
 480         memset(&params, 0, sizeof(params));
 481         params.vport_id = 0;
 482         params.mtu = mtu;
 483         /* @DPDK - Disable FW placement */
 484         params.zero_placement_offset = 1;
 485         for_each_hwfn(edev, i) {
 486                 p_hwfn = &edev->hwfns[i];
 487                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 488                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 489                 rc = ecore_sp_vport_start(p_hwfn, &params);
 490                 if (rc != ECORE_SUCCESS) {
 491                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 492                         return rc;
 493                 }
 494         }
 495         ecore_reset_vport_stats(edev);
 496         qdev->vport_started = true;
 497         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 498
 499         return 0;
 500 }
 501
 502 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 503 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 504
 505 /* Activate or deactivate vport via vport-update */
 506 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 507 {
 508         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 509         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 510         struct ecore_sp_vport_update_params params;
 511         struct ecore_hwfn *p_hwfn;
 512         uint8_t i;
 513         int rc = -1;
 514
 515         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 516         params.vport_id = 0;
 517         params.update_vport_active_rx_flg = 1;
 518         params.update_vport_active_tx_flg = 1;
 519         params.vport_active_rx_flg = flg;
 520         params.vport_active_tx_flg = flg;
 521         if (~qdev->enable_tx_switching & flg) {
 522                 params.update_tx_switching_flg = 1;
 523                 params.tx_switching_flg = !flg;
 524         }
 525         for_each_hwfn(edev, i) {
 526                 p_hwfn = &edev->hwfns[i];
 527                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 528                 rc = ecore_sp_vport_update(p_hwfn, &params,
 529                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 530                 if (rc != ECORE_SUCCESS) {
 531                         DP_ERR(edev, "Failed to update vport\n");
 532                         break;
 533                 }
 534         }
 535         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 536
 537         return rc;
 538 }
 539
 540 static void
 541 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 542                            uint16_t mtu, bool enable)
 543 {
 544         /* Enable LRO in split mode */
 545         sge_tpa_params->tpa_ipv4_en_flg = enable;
 546         sge_tpa_params->tpa_ipv6_en_flg = enable;
 547         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 548         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 549         /* set if tpa enable changes */
 550         sge_tpa_params->update_tpa_en_flg = 1;
 551         /* set if tpa parameters should be handled */
 552         sge_tpa_params->update_tpa_param_flg = enable;
 553
 554         sge_tpa_params->max_buffers_per_cqe = 20;
 555         /* Enable TPA in split mode. In this mode each TPA segment
 556          * starts on the new BD, so there is one BD per segment.
 557          */
 558         sge_tpa_params->tpa_pkt_split_flg = 1;
 559         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 560         sge_tpa_params->tpa_gro_consistent_flg = 0;
 561         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 562         sge_tpa_params->tpa_max_size = 0x7FFF;
 563         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 564         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 565 }
 566
 567 /* Enable/disable LRO via vport-update */
 568 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 569 {
 570         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 571         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 572         struct ecore_sp_vport_update_params params;
 573         struct ecore_sge_tpa_params tpa_params;
 574         struct ecore_hwfn *p_hwfn;
 575         int rc;
 576         int i;
 577
 578         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 579         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 580         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 581         params.vport_id = 0;
 582         params.sge_tpa_params = &tpa_params;
 583         for_each_hwfn(edev, i) {
 584                 p_hwfn = &edev->hwfns[i];
 585                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 586                 rc = ecore_sp_vport_update(p_hwfn, &params,
 587                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 588                 if (rc != ECORE_SUCCESS) {
 589                         DP_ERR(edev, "Failed to update LRO\n");
 590                         return -1;
 591                 }
 592         }
 593         qdev->enable_lro = flg;
 594         eth_dev->data->lro = flg;
 595
 596         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 597
 598         return 0;
 599 }
 600
 601 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 602 {
 603         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 604         ucast->is_rx_filter = true;
 605         ucast->is_tx_filter = true;
 606         /* ucast->assert_on_error = true; - For debug */
 607 }
 608
 609 static int
 610 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 611                              enum qed_filter_rx_mode_type type)
 612 {
 613         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 614         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 615         struct ecore_filter_accept_flags flags;
 616
 617         memset(&flags, 0, sizeof(flags));
 618
 619         flags.update_rx_mode_config = 1;
 620         flags.update_tx_mode_config = 1;
 621         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 622                 ECORE_ACCEPT_MCAST_MATCHED |
 623                 ECORE_ACCEPT_BCAST;
 624
 625         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 626                 ECORE_ACCEPT_MCAST_MATCHED |
 627                 ECORE_ACCEPT_BCAST;
 628
 629         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 630                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 631                 if (IS_VF(edev)) {
 632                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 633                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 634                 }
 635         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 636                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 637         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 638                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 639                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 640                         ECORE_ACCEPT_MCAST_UNMATCHED;
 641         }
 642
 643         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 644                         ECORE_SPQ_MODE_CB, NULL);
 645 }
 646
 647 static int
 648 qede_tunnel_update(struct qede_dev *qdev,
 649                    struct ecore_tunnel_info *tunn_info)
 650 {
 651         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 652         enum _ecore_status_t rc = ECORE_INVAL;
 653         struct ecore_hwfn *p_hwfn;
 654         struct ecore_ptt *p_ptt;
 655         int i;
 656
 657         for_each_hwfn(edev, i) {
 658                 p_hwfn = &edev->hwfns[i];
 659                 if (IS_PF(edev)) {
 660                         p_ptt = ecore_ptt_acquire(p_hwfn);
 661                         if (!p_ptt) {
 662                                 DP_ERR(p_hwfn, "Can't acquire PTT\n");
 663                                 return -EAGAIN;
 664                         }
 665                 } else {
 666                         p_ptt = NULL;
 667                 }
 668
 669                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 670                                 tunn_info, ECORE_SPQ_MODE_CB, NULL);
 671                 if (IS_PF(edev))
 672                         ecore_ptt_release(p_hwfn, p_ptt);
 673
 674                 if (rc != ECORE_SUCCESS)
 675                         break;
 676         }
 677
 678         return rc;
 679 }
 680
 681 static int
 682 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 683                   bool enable)
 684 {
 685         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 686         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 687         enum _ecore_status_t rc = ECORE_INVAL;
 688         struct ecore_tunnel_info tunn;
 689
 690         if (qdev->vxlan.enable == enable)
 691                 return ECORE_SUCCESS;
 692
 693         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 694         tunn.vxlan.b_update_mode = true;
 695         tunn.vxlan.b_mode_enabled = enable;
 696         tunn.b_update_rx_cls = true;
 697         tunn.b_update_tx_cls = true;
 698         tunn.vxlan.tun_cls = clss;
 699
 700         tunn.vxlan_port.b_update_port = true;
 701         tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
 702
 703         rc = qede_tunnel_update(qdev, &tunn);
 704         if (rc == ECORE_SUCCESS) {
 705                 qdev->vxlan.enable = enable;
 706                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 707                 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
 708                         enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
 709         } else {
 710                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 711                        tunn.vxlan.tun_cls);
 712         }
 713
 714         return rc;
 715 }
 716
 717 static int
 718 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 719                   bool enable)
 720 {
 721         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 722         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 723         enum _ecore_status_t rc = ECORE_INVAL;
 724         struct ecore_tunnel_info tunn;
 725
 726         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 727         tunn.l2_geneve.b_update_mode = true;
 728         tunn.l2_geneve.b_mode_enabled = enable;
 729         tunn.ip_geneve.b_update_mode = true;
 730         tunn.ip_geneve.b_mode_enabled = enable;
 731         tunn.l2_geneve.tun_cls = clss;
 732         tunn.ip_geneve.tun_cls = clss;
 733         tunn.b_update_rx_cls = true;
 734         tunn.b_update_tx_cls = true;
 735
 736         tunn.geneve_port.b_update_port = true;
 737         tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
 738
 739         rc = qede_tunnel_update(qdev, &tunn);
 740         if (rc == ECORE_SUCCESS) {
 741                 qdev->geneve.enable = enable;
 742                 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
 743                 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
 744                         enable ? "enabled" : "disabled", qdev->geneve.udp_port);
 745         } else {
 746                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 747                        clss);
 748         }
 749
 750         return rc;
 751 }
 752
 753 static int
 754 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 755                   bool enable)
 756 {
 757         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 758         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 759         enum _ecore_status_t rc = ECORE_INVAL;
 760         struct ecore_tunnel_info tunn;
 761
 762         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 763         tunn.ip_gre.b_update_mode = true;
 764         tunn.ip_gre.b_mode_enabled = enable;
 765         tunn.ip_gre.tun_cls = clss;
 766         tunn.ip_gre.tun_cls = clss;
 767         tunn.b_update_rx_cls = true;
 768         tunn.b_update_tx_cls = true;
 769
 770         rc = qede_tunnel_update(qdev, &tunn);
 771         if (rc == ECORE_SUCCESS) {
 772                 qdev->ipgre.enable = enable;
 773                 DP_INFO(edev, "IPGRE is %s\n",
 774                         enable ? "enabled" : "disabled");
 775         } else {
 776                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 777                        clss);
 778         }
 779
 780         return rc;
 781 }
 782
 783 static int
 784 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 785                  enum rte_eth_tunnel_type tunn_type, bool enable)
 786 {
 787         int rc = -EINVAL;
 788
 789         switch (tunn_type) {
 790         case RTE_TUNNEL_TYPE_VXLAN:
 791                 rc = qede_vxlan_enable(eth_dev, clss, enable);
 792                 break;
 793         case RTE_TUNNEL_TYPE_GENEVE:
 794                 rc = qede_geneve_enable(eth_dev, clss, enable);
 795                 break;
 796         case RTE_TUNNEL_TYPE_IP_IN_GRE:
 797                 rc = qede_ipgre_enable(eth_dev, clss, enable);
 798                 break;
 799         default:
 800                 rc = -EINVAL;
 801                 break;
 802         }
 803
 804         return rc;
 805 }
 806
 807 static int
 808 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 809                   bool add)
 810 {
 811         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 812         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 813         struct qede_ucast_entry *tmp = NULL;
 814         struct qede_ucast_entry *u;
 815         struct ether_addr *mac_addr;
 816
 817         mac_addr  = (struct ether_addr *)ucast->mac;
 818         if (add) {
 819                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 820                         if ((memcmp(mac_addr, &tmp->mac,
 821                                     ETHER_ADDR_LEN) == 0) &&
 822                              ucast->vni == tmp->vni &&
 823                              ucast->vlan == tmp->vlan) {
 824                                 DP_INFO(edev, "Unicast MAC is already added"
 825                                         " with vlan = %u, vni = %u\n",
 826                                         ucast->vlan,  ucast->vni);
 827                                         return 0;
 828                         }
 829                 }
 830                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 831                                RTE_CACHE_LINE_SIZE);
 832                 if (!u) {
 833                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 834                         return -ENOMEM;
 835                 }
 836                 ether_addr_copy(mac_addr, &u->mac);
 837                 u->vlan = ucast->vlan;
 838                 u->vni = ucast->vni;
 839                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 840                 qdev->num_uc_addr++;
 841         } else {
 842                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 843                         if ((memcmp(mac_addr, &tmp->mac,
 844                                     ETHER_ADDR_LEN) == 0) &&
 845                             ucast->vlan == tmp->vlan      &&
 846                             ucast->vni == tmp->vni)
 847                         break;
 848                 }
 849                 if (tmp == NULL) {
 850                         DP_INFO(edev, "Unicast MAC is not found\n");
 851                         return -EINVAL;
 852                 }
 853                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 854                 qdev->num_uc_addr--;
 855         }
 856
 857         return 0;
 858 }
 859
 860 static int
 861 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
 862                        uint32_t mc_addrs_num)
 863 {
 864         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 865         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 866         struct ecore_filter_mcast mcast;
 867         struct qede_mcast_entry *m = NULL;
 868         uint8_t i;
 869         int rc;
 870
 871         for (i = 0; i < mc_addrs_num; i++) {
 872                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 873                                RTE_CACHE_LINE_SIZE);
 874                 if (!m) {
 875                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 876                         return -ENOMEM;
 877                 }
 878                 ether_addr_copy(&mc_addrs[i], &m->mac);
 879                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 880         }
 881         memset(&mcast, 0, sizeof(mcast));
 882         mcast.num_mc_addrs = mc_addrs_num;
 883         mcast.opcode = ECORE_FILTER_ADD;
 884         for (i = 0; i < mc_addrs_num; i++)
 885                 ether_addr_copy(&mc_addrs[i], (struct ether_addr *)
 886                                                         &mcast.mac[i]);
 887         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 888         if (rc != ECORE_SUCCESS) {
 889                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 890                 return -1;
 891         }
 892
 893         return 0;
 894 }
 895
 896 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 897 {
 898         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 899         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 900         struct qede_mcast_entry *tmp = NULL;
 901         struct ecore_filter_mcast mcast;
 902         int j;
 903         int rc;
 904
 905         memset(&mcast, 0, sizeof(mcast));
 906         mcast.num_mc_addrs = qdev->num_mc_addr;
 907         mcast.opcode = ECORE_FILTER_REMOVE;
 908         j = 0;
 909         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 910                 ether_addr_copy(&tmp->mac, (struct ether_addr *)&mcast.mac[j]);
 911                 j++;
 912         }
 913         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 914         if (rc != ECORE_SUCCESS) {
 915                 DP_ERR(edev, "Failed to delete multicast filter\n");
 916                 return -1;
 917         }
 918         /* Init the list */
 919         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 920                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 921                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 922         }
 923         SLIST_INIT(&qdev->mc_list_head);
 924
 925         return 0;
 926 }
 927
 928 static enum _ecore_status_t
 929 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 930                  bool add)
 931 {
 932         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 933         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 934         enum _ecore_status_t rc = ECORE_INVAL;
 935
 936         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 937                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 938                               " Please enable promisc mode\n");
 939                         return ECORE_INVAL;
 940         }
 941
 942         rc = qede_ucast_filter(eth_dev, ucast, add);
 943         if (rc == 0)
 944                 rc = ecore_filter_ucast_cmd(edev, ucast,
 945                                             ECORE_SPQ_MODE_CB, NULL);
 946         if (rc != ECORE_SUCCESS)
 947                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 948                        rc, add);
 949
 950         return rc;
 951 }
 952
 953 static int
 954 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 955                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 956 {
 957         struct ecore_filter_ucast ucast;
 958         int re;
 959
 960         if (!is_valid_assigned_ether_addr(mac_addr))
 961                 return -EINVAL;
 962
 963         qede_set_ucast_cmn_params(&ucast);
 964         ucast.opcode = ECORE_FILTER_ADD;
 965         ucast.type = ECORE_FILTER_MAC;
 966         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 967         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 968         return re;
 969 }
 970
 971 static void
 972 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 973 {
 974         struct qede_dev *qdev = eth_dev->data->dev_private;
 975         struct ecore_dev *edev = &qdev->edev;
 976         struct ecore_filter_ucast ucast;
 977
 978         PMD_INIT_FUNC_TRACE(edev);
 979
 980         if (index >= qdev->dev_info.num_mac_filters) {
 981                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 982                        index, qdev->dev_info.num_mac_filters);
 983                 return;
 984         }
 985
 986         if (!is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 987                 return;
 988
 989         qede_set_ucast_cmn_params(&ucast);
 990         ucast.opcode = ECORE_FILTER_REMOVE;
 991         ucast.type = ECORE_FILTER_MAC;
 992
 993         /* Use the index maintained by rte */
 994         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 995                         (struct ether_addr *)&ucast.mac);
 996
 997         qede_mac_int_ops(eth_dev, &ucast, false);
 998 }
 999
1000 static int
1001 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1002 {
1003         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1004         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1005
1006         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1007                                                mac_addr->addr_bytes)) {
1008                 DP_ERR(edev, "Setting MAC address is not allowed\n");
1009                 return -EPERM;
1010         }
1011
1012         qede_mac_addr_remove(eth_dev, 0);
1013
1014         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1015 }
1016
1017 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1018 {
1019         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1020         struct ecore_sp_vport_update_params params;
1021         struct ecore_hwfn *p_hwfn;
1022         uint8_t i;
1023         int rc;
1024
1025         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1026         params.vport_id = 0;
1027         params.update_accept_any_vlan_flg = 1;
1028         params.accept_any_vlan = flg;
1029         for_each_hwfn(edev, i) {
1030                 p_hwfn = &edev->hwfns[i];
1031                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1032                 rc = ecore_sp_vport_update(p_hwfn, &params,
1033                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1034                 if (rc != ECORE_SUCCESS) {
1035                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1036                         return;
1037                 }
1038         }
1039
1040         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1041 }
1042
1043 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1044 {
1045         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1046         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1047         struct ecore_sp_vport_update_params params;
1048         struct ecore_hwfn *p_hwfn;
1049         uint8_t i;
1050         int rc;
1051
1052         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1053         params.vport_id = 0;
1054         params.update_inner_vlan_removal_flg = 1;
1055         params.inner_vlan_removal_flg = flg;
1056         for_each_hwfn(edev, i) {
1057                 p_hwfn = &edev->hwfns[i];
1058                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1059                 rc = ecore_sp_vport_update(p_hwfn, &params,
1060                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1061                 if (rc != ECORE_SUCCESS) {
1062                         DP_ERR(edev, "Failed to update vport\n");
1063                         return -1;
1064                 }
1065         }
1066
1067         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1068         return 0;
1069 }
1070
1071 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1072                                 uint16_t vlan_id, int on)
1073 {
1074         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1075         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1076         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1077         struct qede_vlan_entry *tmp = NULL;
1078         struct qede_vlan_entry *vlan;
1079         struct ecore_filter_ucast ucast;
1080         int rc;
1081
1082         if (on) {
1083                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1084                         DP_ERR(edev, "Reached max VLAN filter limit"
1085                                       " enabling accept_any_vlan\n");
1086                         qede_config_accept_any_vlan(qdev, true);
1087                         return 0;
1088                 }
1089
1090                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1091                         if (tmp->vid == vlan_id) {
1092                                 DP_INFO(edev, "VLAN %u already configured\n",
1093                                         vlan_id);
1094                                 return 0;
1095                         }
1096                 }
1097
1098                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1099                                   RTE_CACHE_LINE_SIZE);
1100
1101                 if (!vlan) {
1102                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1103                         return -ENOMEM;
1104                 }
1105
1106                 qede_set_ucast_cmn_params(&ucast);
1107                 ucast.opcode = ECORE_FILTER_ADD;
1108                 ucast.type = ECORE_FILTER_VLAN;
1109                 ucast.vlan = vlan_id;
1110                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1111                                             NULL);
1112                 if (rc != 0) {
1113                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1114                                rc);
1115                         rte_free(vlan);
1116                 } else {
1117                         vlan->vid = vlan_id;
1118                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1119                         qdev->configured_vlans++;
1120                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1121                                 vlan_id, qdev->configured_vlans);
1122                 }
1123         } else {
1124                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1125                         if (tmp->vid == vlan_id)
1126                                 break;
1127                 }
1128
1129                 if (!tmp) {
1130                         if (qdev->configured_vlans == 0) {
1131                                 DP_INFO(edev,
1132                                         "No VLAN filters configured yet\n");
1133                                 return 0;
1134                         }
1135
1136                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1137                         return -EINVAL;
1138                 }
1139
1140                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1141
1142                 qede_set_ucast_cmn_params(&ucast);
1143                 ucast.opcode = ECORE_FILTER_REMOVE;
1144                 ucast.type = ECORE_FILTER_VLAN;
1145                 ucast.vlan = vlan_id;
1146                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1147                                             NULL);
1148                 if (rc != 0) {
1149                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1150                                vlan_id, rc);
1151                 } else {
1152                         qdev->configured_vlans--;
1153                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1154                                 vlan_id, qdev->configured_vlans);
1155                 }
1156         }
1157
1158         return rc;
1159 }
1160
1161 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1162 {
1163         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1164         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1165         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1166
1167         if (mask & ETH_VLAN_STRIP_MASK) {
1168                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1169                         (void)qede_vlan_stripping(eth_dev, 1);
1170                 else
1171                         (void)qede_vlan_stripping(eth_dev, 0);
1172         }
1173
1174         if (mask & ETH_VLAN_FILTER_MASK) {
1175                 /* VLAN filtering kicks in when a VLAN is added */
1176                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1177                         qede_vlan_filter_set(eth_dev, 0, 1);
1178                 } else {
1179                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1180                                 DP_ERR(edev,
1181                                   " Please remove existing VLAN filters"
1182                                   " before disabling VLAN filtering\n");
1183                                 /* Signal app that VLAN filtering is still
1184                                  * enabled
1185                                  */
1186                                 eth_dev->data->dev_conf.rxmode.offloads |=
1187                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1188                         } else {
1189                                 qede_vlan_filter_set(eth_dev, 0, 0);
1190                         }
1191                 }
1192         }
1193
1194         if (mask & ETH_VLAN_EXTEND_MASK)
1195                 DP_ERR(edev, "Extend VLAN not supported\n");
1196
1197         qdev->vlan_offload_mask = mask;
1198
1199         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1200
1201         return 0;
1202 }
1203
1204 static void qede_prandom_bytes(uint32_t *buff)
1205 {
1206         uint8_t i;
1207
1208         srand((unsigned int)time(NULL));
1209         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1210                 buff[i] = rand();
1211 }
1212
1213 int qede_config_rss(struct rte_eth_dev *eth_dev)
1214 {
1215         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1216         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1217         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1218         struct rte_eth_rss_reta_entry64 reta_conf[2];
1219         struct rte_eth_rss_conf rss_conf;
1220         uint32_t i, id, pos, q;
1221
1222         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1223         if (!rss_conf.rss_key) {
1224                 DP_INFO(edev, "Applying driver default key\n");
1225                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1226                 qede_prandom_bytes(&def_rss_key[0]);
1227                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1228         }
1229
1230         /* Configure RSS hash */
1231         if (qede_rss_hash_update(eth_dev, &rss_conf))
1232                 return -EINVAL;
1233
1234         /* Configure default RETA */
1235         memset(reta_conf, 0, sizeof(reta_conf));
1236         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1237                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1238
1239         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1240                 id = i / RTE_RETA_GROUP_SIZE;
1241                 pos = i % RTE_RETA_GROUP_SIZE;
1242                 q = i % QEDE_RSS_COUNT(qdev);
1243                 reta_conf[id].reta[pos] = q;
1244         }
1245         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1246                                  ECORE_RSS_IND_TABLE_SIZE))
1247                 return -EINVAL;
1248
1249         return 0;
1250 }
1251
1252 static void qede_fastpath_start(struct ecore_dev *edev)
1253 {
1254         struct ecore_hwfn *p_hwfn;
1255         int i;
1256
1257         for_each_hwfn(edev, i) {
1258                 p_hwfn = &edev->hwfns[i];
1259                 ecore_hw_start_fastpath(p_hwfn);
1260         }
1261 }
1262
1263 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1264 {
1265         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1266         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1267         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1268
1269         PMD_INIT_FUNC_TRACE(edev);
1270
1271         /* Update MTU only if it has changed */
1272         if (eth_dev->data->mtu != qdev->mtu) {
1273                 if (qede_update_mtu(eth_dev, qdev->mtu))
1274                         goto err;
1275         }
1276
1277         /* Configure TPA parameters */
1278         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1279                 if (qede_enable_tpa(eth_dev, true))
1280                         return -EINVAL;
1281                 /* Enable scatter mode for LRO */
1282                 if (!eth_dev->data->scattered_rx)
1283                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1284         }
1285
1286         /* Start queues */
1287         if (qede_start_queues(eth_dev))
1288                 goto err;
1289
1290         if (IS_PF(edev))
1291                 qede_reset_queue_stats(qdev, true);
1292
1293         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1294          * enabling RSS. Hence RSS configuration is deferred upto this point.
1295          * Also, we would like to retain similar behavior in PF case, so we
1296          * don't do PF/VF specific check here.
1297          */
1298         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1299                 if (qede_config_rss(eth_dev))
1300                         goto err;
1301
1302         /* Enable vport*/
1303         if (qede_activate_vport(eth_dev, true))
1304                 goto err;
1305
1306         /* Update link status */
1307         qede_link_update(eth_dev, 0);
1308
1309         /* Start/resume traffic */
1310         qede_fastpath_start(edev);
1311
1312         DP_INFO(edev, "Device started\n");
1313
1314         return 0;
1315 err:
1316         DP_ERR(edev, "Device start fails\n");
1317         return -1; /* common error code is < 0 */
1318 }
1319
1320 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1321 {
1322         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1323         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1324
1325         PMD_INIT_FUNC_TRACE(edev);
1326
1327         /* Disable vport */
1328         if (qede_activate_vport(eth_dev, false))
1329                 return;
1330
1331         if (qdev->enable_lro)
1332                 qede_enable_tpa(eth_dev, false);
1333
1334         /* Stop queues */
1335         qede_stop_queues(eth_dev);
1336
1337         /* Disable traffic */
1338         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1339
1340         if (IS_PF(edev))
1341                 qede_mac_addr_remove(eth_dev, 0);
1342
1343         DP_INFO(edev, "Device is stopped\n");
1344 }
1345
1346 const char *valid_args[] = {
1347         QEDE_NPAR_TX_SWITCHING,
1348         QEDE_VF_TX_SWITCHING,
1349         NULL,
1350 };
1351
1352 static int qede_args_check(const char *key, const char *val, void *opaque)
1353 {
1354         unsigned long tmp;
1355         int ret = 0;
1356         struct rte_eth_dev *eth_dev = opaque;
1357         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1358         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1359
1360         errno = 0;
1361         tmp = strtoul(val, NULL, 0);
1362         if (errno) {
1363                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1364                 return errno;
1365         }
1366
1367         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1368             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1369                 qdev->enable_tx_switching = !!tmp;
1370                 DP_INFO(edev, "Disabling %s tx-switching\n",
1371                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1372                         "VF" : "NPAR");
1373         }
1374
1375         return ret;
1376 }
1377
1378 static int qede_args(struct rte_eth_dev *eth_dev)
1379 {
1380         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1381         struct rte_kvargs *kvlist;
1382         struct rte_devargs *devargs;
1383         int ret;
1384         int i;
1385
1386         devargs = pci_dev->device.devargs;
1387         if (!devargs)
1388                 return 0; /* return success */
1389
1390         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1391         if (kvlist == NULL)
1392                 return -EINVAL;
1393
1394          /* Process parameters. */
1395         for (i = 0; (valid_args[i] != NULL); ++i) {
1396                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1397                         ret = rte_kvargs_process(kvlist, valid_args[i],
1398                                                  qede_args_check, eth_dev);
1399                         if (ret != ECORE_SUCCESS) {
1400                                 rte_kvargs_free(kvlist);
1401                                 return ret;
1402                         }
1403                 }
1404         }
1405         rte_kvargs_free(kvlist);
1406
1407         return 0;
1408 }
1409
1410 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1411 {
1412         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1413         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1414         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1415         int ret;
1416
1417         PMD_INIT_FUNC_TRACE(edev);
1418
1419         /* Check requirements for 100G mode */
1420         if (ECORE_IS_CMT(edev)) {
1421                 if (eth_dev->data->nb_rx_queues < 2 ||
1422                     eth_dev->data->nb_tx_queues < 2) {
1423                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1424                         return -EINVAL;
1425                 }
1426
1427                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1428                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
1429                         DP_ERR(edev,
1430                                "100G mode needs even no. of RX/TX queues\n");
1431                         return -EINVAL;
1432                 }
1433         }
1434
1435         /* We need to have min 1 RX queue.There is no min check in
1436          * rte_eth_dev_configure(), so we are checking it here.
1437          */
1438         if (eth_dev->data->nb_rx_queues == 0) {
1439                 DP_ERR(edev, "Minimum one RX queue is required\n");
1440                 return -EINVAL;
1441         }
1442
1443         /* Enable Tx switching by default */
1444         qdev->enable_tx_switching = 1;
1445
1446         /* Parse devargs and fix up rxmode */
1447         if (qede_args(eth_dev))
1448                 DP_NOTICE(edev, false,
1449                           "Invalid devargs supplied, requested change will not take effect\n");
1450
1451         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1452               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1453                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1454                 return -ENOTSUP;
1455         }
1456         /* Flow director mode check */
1457         if (qede_check_fdir_support(eth_dev))
1458                 return -ENOTSUP;
1459
1460         qede_dealloc_fp_resc(eth_dev);
1461         qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1462         qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1463         if (qede_alloc_fp_resc(qdev))
1464                 return -ENOMEM;
1465
1466         /* If jumbo enabled adjust MTU */
1467         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1468                 eth_dev->data->mtu =
1469                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1470                         ETHER_HDR_LEN - ETHER_CRC_LEN;
1471
1472         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1473                 eth_dev->data->scattered_rx = 1;
1474
1475         if (qede_start_vport(qdev, eth_dev->data->mtu))
1476                 return -1;
1477
1478         qdev->mtu = eth_dev->data->mtu;
1479
1480         /* Enable VLAN offloads by default */
1481         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1482                                              ETH_VLAN_FILTER_MASK |
1483                                              ETH_VLAN_EXTEND_MASK);
1484         if (ret)
1485                 return ret;
1486
1487         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1488                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1489
1490         return 0;
1491 }
1492
1493 /* Info about HW descriptor ring limitations */
1494 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1495         .nb_max = 0x8000, /* 32K */
1496         .nb_min = 128,
1497         .nb_align = 128 /* lowest common multiple */
1498 };
1499
1500 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1501         .nb_max = 0x8000, /* 32K */
1502         .nb_min = 256,
1503         .nb_align = 256,
1504         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1505         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1506 };
1507
1508 static void
1509 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1510                   struct rte_eth_dev_info *dev_info)
1511 {
1512         struct qede_dev *qdev = eth_dev->data->dev_private;
1513         struct ecore_dev *edev = &qdev->edev;
1514         struct qed_link_output link;
1515         uint32_t speed_cap = 0;
1516
1517         PMD_INIT_FUNC_TRACE(edev);
1518
1519         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1520         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1521         dev_info->rx_desc_lim = qede_rx_desc_lim;
1522         dev_info->tx_desc_lim = qede_tx_desc_lim;
1523
1524         if (IS_PF(edev))
1525                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1526                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1527         else
1528                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1529                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1530         dev_info->max_tx_queues = dev_info->max_rx_queues;
1531
1532         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1533         dev_info->max_vfs = 0;
1534         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1535         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1536         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1537         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1538                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1539                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1540                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1541                                      DEV_RX_OFFLOAD_TCP_LRO     |
1542                                      DEV_RX_OFFLOAD_CRC_STRIP   |
1543                                      DEV_RX_OFFLOAD_SCATTER     |
1544                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1545                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1546                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1547         dev_info->rx_queue_offload_capa = 0;
1548
1549         /* TX offloads are on a per-packet basis, so it is applicable
1550          * to both at port and queue levels.
1551          */
1552         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1553                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1554                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1555                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1556                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1557                                      DEV_TX_OFFLOAD_QINQ_INSERT |
1558                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1559                                      DEV_TX_OFFLOAD_TCP_TSO     |
1560                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1561                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1562         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1563
1564         dev_info->default_txconf = (struct rte_eth_txconf) {
1565                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1566         };
1567
1568         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1569                 /* Packets are always dropped if no descriptors are available */
1570                 .rx_drop_en = 1,
1571                 /* The below RX offloads are always enabled */
1572                 .offloads = (DEV_RX_OFFLOAD_CRC_STRIP  |
1573                              DEV_RX_OFFLOAD_IPV4_CKSUM |
1574                              DEV_RX_OFFLOAD_TCP_CKSUM  |
1575                              DEV_RX_OFFLOAD_UDP_CKSUM),
1576         };
1577
1578         memset(&link, 0, sizeof(struct qed_link_output));
1579         qdev->ops->common->get_link(edev, &link);
1580         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1581                 speed_cap |= ETH_LINK_SPEED_1G;
1582         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1583                 speed_cap |= ETH_LINK_SPEED_10G;
1584         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1585                 speed_cap |= ETH_LINK_SPEED_25G;
1586         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1587                 speed_cap |= ETH_LINK_SPEED_40G;
1588         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1589                 speed_cap |= ETH_LINK_SPEED_50G;
1590         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1591                 speed_cap |= ETH_LINK_SPEED_100G;
1592         dev_info->speed_capa = speed_cap;
1593 }
1594
1595 /* return 0 means link status changed, -1 means not changed */
1596 int
1597 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1598 {
1599         struct qede_dev *qdev = eth_dev->data->dev_private;
1600         struct ecore_dev *edev = &qdev->edev;
1601         struct qed_link_output q_link;
1602         struct rte_eth_link link;
1603         uint16_t link_duplex;
1604
1605         memset(&q_link, 0, sizeof(q_link));
1606         memset(&link, 0, sizeof(link));
1607
1608         qdev->ops->common->get_link(edev, &q_link);
1609
1610         /* Link Speed */
1611         link.link_speed = q_link.speed;
1612
1613         /* Link Mode */
1614         switch (q_link.duplex) {
1615         case QEDE_DUPLEX_HALF:
1616                 link_duplex = ETH_LINK_HALF_DUPLEX;
1617                 break;
1618         case QEDE_DUPLEX_FULL:
1619                 link_duplex = ETH_LINK_FULL_DUPLEX;
1620                 break;
1621         case QEDE_DUPLEX_UNKNOWN:
1622         default:
1623                 link_duplex = -1;
1624         }
1625         link.link_duplex = link_duplex;
1626
1627         /* Link Status */
1628         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1629
1630         /* AN */
1631         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1632                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1633
1634         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1635                 link.link_speed, link.link_duplex,
1636                 link.link_autoneg, link.link_status);
1637
1638         return rte_eth_linkstatus_set(eth_dev, &link);
1639 }
1640
1641 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1642 {
1643 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1644         struct qede_dev *qdev = eth_dev->data->dev_private;
1645         struct ecore_dev *edev = &qdev->edev;
1646
1647         PMD_INIT_FUNC_TRACE(edev);
1648 #endif
1649
1650         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1651
1652         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1653                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1654
1655         qed_configure_filter_rx_mode(eth_dev, type);
1656 }
1657
1658 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1659 {
1660 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1661         struct qede_dev *qdev = eth_dev->data->dev_private;
1662         struct ecore_dev *edev = &qdev->edev;
1663
1664         PMD_INIT_FUNC_TRACE(edev);
1665 #endif
1666
1667         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1668                 qed_configure_filter_rx_mode(eth_dev,
1669                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1670         else
1671                 qed_configure_filter_rx_mode(eth_dev,
1672                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1673 }
1674
1675 static void qede_poll_sp_sb_cb(void *param)
1676 {
1677         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1678         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1679         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1680         int rc;
1681
1682         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1683         qede_interrupt_action(&edev->hwfns[1]);
1684
1685         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1686                                qede_poll_sp_sb_cb,
1687                                (void *)eth_dev);
1688         if (rc != 0) {
1689                 DP_ERR(edev, "Unable to start periodic"
1690                              " timer rc %d\n", rc);
1691                 assert(false && "Unable to start periodic timer");
1692         }
1693 }
1694
1695 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1696 {
1697         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1698         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1699         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1700
1701         PMD_INIT_FUNC_TRACE(edev);
1702
1703         /* dev_stop() shall cleanup fp resources in hw but without releasing
1704          * dma memories and sw structures so that dev_start() can be called
1705          * by the app without reconfiguration. However, in dev_close() we
1706          * can release all the resources and device can be brought up newly
1707          */
1708         if (eth_dev->data->dev_started)
1709                 qede_dev_stop(eth_dev);
1710
1711         qede_stop_vport(edev);
1712         qdev->vport_started = false;
1713         qede_fdir_dealloc_resc(eth_dev);
1714         qede_dealloc_fp_resc(eth_dev);
1715
1716         eth_dev->data->nb_rx_queues = 0;
1717         eth_dev->data->nb_tx_queues = 0;
1718
1719         /* Bring the link down */
1720         qede_dev_set_link_state(eth_dev, false);
1721         qdev->ops->common->slowpath_stop(edev);
1722         qdev->ops->common->remove(edev);
1723         rte_intr_disable(&pci_dev->intr_handle);
1724         rte_intr_callback_unregister(&pci_dev->intr_handle,
1725                                      qede_interrupt_handler, (void *)eth_dev);
1726         if (ECORE_IS_CMT(edev))
1727                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1728 }
1729
1730 static int
1731 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1732 {
1733         struct qede_dev *qdev = eth_dev->data->dev_private;
1734         struct ecore_dev *edev = &qdev->edev;
1735         struct ecore_eth_stats stats;
1736         unsigned int i = 0, j = 0, qid;
1737         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1738         struct qede_tx_queue *txq;
1739
1740         ecore_get_vport_stats(edev, &stats);
1741
1742         /* RX Stats */
1743         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1744             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1745
1746         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1747             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1748
1749         eth_stats->ierrors = stats.common.rx_crc_errors +
1750             stats.common.rx_align_errors +
1751             stats.common.rx_carrier_errors +
1752             stats.common.rx_oversize_packets +
1753             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1754
1755         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1756
1757         eth_stats->imissed = stats.common.mftag_filter_discards +
1758             stats.common.mac_filter_discards +
1759             stats.common.no_buff_discards +
1760             stats.common.brb_truncates + stats.common.brb_discards;
1761
1762         /* TX stats */
1763         eth_stats->opackets = stats.common.tx_ucast_pkts +
1764             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1765
1766         eth_stats->obytes = stats.common.tx_ucast_bytes +
1767             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1768
1769         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1770
1771         /* Queue stats */
1772         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1773                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1774         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1775                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1776         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1777             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1778                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1779                        "Not all the queue stats will be displayed. Set"
1780                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1781                        " appropriately and retry.\n");
1782
1783         for_each_rss(qid) {
1784                 eth_stats->q_ipackets[i] =
1785                         *(uint64_t *)(
1786                                 ((char *)(qdev->fp_array[qid].rxq)) +
1787                                 offsetof(struct qede_rx_queue,
1788                                 rcv_pkts));
1789                 eth_stats->q_errors[i] =
1790                         *(uint64_t *)(
1791                                 ((char *)(qdev->fp_array[qid].rxq)) +
1792                                 offsetof(struct qede_rx_queue,
1793                                 rx_hw_errors)) +
1794                         *(uint64_t *)(
1795                                 ((char *)(qdev->fp_array[qid].rxq)) +
1796                                 offsetof(struct qede_rx_queue,
1797                                 rx_alloc_errors));
1798                 i++;
1799                 if (i == rxq_stat_cntrs)
1800                         break;
1801         }
1802
1803         for_each_tss(qid) {
1804                 txq = qdev->fp_array[qid].txq;
1805                 eth_stats->q_opackets[j] =
1806                         *((uint64_t *)(uintptr_t)
1807                                 (((uint64_t)(uintptr_t)(txq)) +
1808                                  offsetof(struct qede_tx_queue,
1809                                           xmit_pkts)));
1810                 j++;
1811                 if (j == txq_stat_cntrs)
1812                         break;
1813         }
1814
1815         return 0;
1816 }
1817
1818 static unsigned
1819 qede_get_xstats_count(struct qede_dev *qdev) {
1820         if (ECORE_IS_BB(&qdev->edev))
1821                 return RTE_DIM(qede_xstats_strings) +
1822                        RTE_DIM(qede_bb_xstats_strings) +
1823                        (RTE_DIM(qede_rxq_xstats_strings) *
1824                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1825                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1826         else
1827                 return RTE_DIM(qede_xstats_strings) +
1828                        RTE_DIM(qede_ah_xstats_strings) +
1829                        (RTE_DIM(qede_rxq_xstats_strings) *
1830                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1831                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1832 }
1833
1834 static int
1835 qede_get_xstats_names(struct rte_eth_dev *dev,
1836                       struct rte_eth_xstat_name *xstats_names,
1837                       __rte_unused unsigned int limit)
1838 {
1839         struct qede_dev *qdev = dev->data->dev_private;
1840         struct ecore_dev *edev = &qdev->edev;
1841         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1842         unsigned int i, qid, stat_idx = 0;
1843         unsigned int rxq_stat_cntrs;
1844
1845         if (xstats_names != NULL) {
1846                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1847                         snprintf(xstats_names[stat_idx].name,
1848                                 sizeof(xstats_names[stat_idx].name),
1849                                 "%s",
1850                                 qede_xstats_strings[i].name);
1851                         stat_idx++;
1852                 }
1853
1854                 if (ECORE_IS_BB(edev)) {
1855                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1856                                 snprintf(xstats_names[stat_idx].name,
1857                                         sizeof(xstats_names[stat_idx].name),
1858                                         "%s",
1859                                         qede_bb_xstats_strings[i].name);
1860                                 stat_idx++;
1861                         }
1862                 } else {
1863                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1864                                 snprintf(xstats_names[stat_idx].name,
1865                                         sizeof(xstats_names[stat_idx].name),
1866                                         "%s",
1867                                         qede_ah_xstats_strings[i].name);
1868                                 stat_idx++;
1869                         }
1870                 }
1871
1872                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1873                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1874                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1875                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1876                                 snprintf(xstats_names[stat_idx].name,
1877                                         sizeof(xstats_names[stat_idx].name),
1878                                         "%.4s%d%s",
1879                                         qede_rxq_xstats_strings[i].name, qid,
1880                                         qede_rxq_xstats_strings[i].name + 4);
1881                                 stat_idx++;
1882                         }
1883                 }
1884         }
1885
1886         return stat_cnt;
1887 }
1888
1889 static int
1890 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1891                 unsigned int n)
1892 {
1893         struct qede_dev *qdev = dev->data->dev_private;
1894         struct ecore_dev *edev = &qdev->edev;
1895         struct ecore_eth_stats stats;
1896         const unsigned int num = qede_get_xstats_count(qdev);
1897         unsigned int i, qid, stat_idx = 0;
1898         unsigned int rxq_stat_cntrs;
1899
1900         if (n < num)
1901                 return num;
1902
1903         ecore_get_vport_stats(edev, &stats);
1904
1905         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1906                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1907                                              qede_xstats_strings[i].offset);
1908                 xstats[stat_idx].id = stat_idx;
1909                 stat_idx++;
1910         }
1911
1912         if (ECORE_IS_BB(edev)) {
1913                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1914                         xstats[stat_idx].value =
1915                                         *(uint64_t *)(((char *)&stats) +
1916                                         qede_bb_xstats_strings[i].offset);
1917                         xstats[stat_idx].id = stat_idx;
1918                         stat_idx++;
1919                 }
1920         } else {
1921                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1922                         xstats[stat_idx].value =
1923                                         *(uint64_t *)(((char *)&stats) +
1924                                         qede_ah_xstats_strings[i].offset);
1925                         xstats[stat_idx].id = stat_idx;
1926                         stat_idx++;
1927                 }
1928         }
1929
1930         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1931                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1932         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1933                 for_each_rss(qid) {
1934                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1935                                 xstats[stat_idx].value = *(uint64_t *)(
1936                                         ((char *)(qdev->fp_array[qid].rxq)) +
1937                                          qede_rxq_xstats_strings[i].offset);
1938                                 xstats[stat_idx].id = stat_idx;
1939                                 stat_idx++;
1940                         }
1941                 }
1942         }
1943
1944         return stat_idx;
1945 }
1946
1947 static void
1948 qede_reset_xstats(struct rte_eth_dev *dev)
1949 {
1950         struct qede_dev *qdev = dev->data->dev_private;
1951         struct ecore_dev *edev = &qdev->edev;
1952
1953         ecore_reset_vport_stats(edev);
1954         qede_reset_queue_stats(qdev, true);
1955 }
1956
1957 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1958 {
1959         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1960         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1961         struct qed_link_params link_params;
1962         int rc;
1963
1964         DP_INFO(edev, "setting link state %d\n", link_up);
1965         memset(&link_params, 0, sizeof(link_params));
1966         link_params.link_up = link_up;
1967         rc = qdev->ops->common->set_link(edev, &link_params);
1968         if (rc != ECORE_SUCCESS)
1969                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1970
1971         return rc;
1972 }
1973
1974 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1975 {
1976         return qede_dev_set_link_state(eth_dev, true);
1977 }
1978
1979 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1980 {
1981         return qede_dev_set_link_state(eth_dev, false);
1982 }
1983
1984 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1985 {
1986         struct qede_dev *qdev = eth_dev->data->dev_private;
1987         struct ecore_dev *edev = &qdev->edev;
1988
1989         ecore_reset_vport_stats(edev);
1990         qede_reset_queue_stats(qdev, false);
1991 }
1992
1993 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1994 {
1995         enum qed_filter_rx_mode_type type =
1996             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1997
1998         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1999                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
2000
2001         qed_configure_filter_rx_mode(eth_dev, type);
2002 }
2003
2004 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
2005 {
2006         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2007                 qed_configure_filter_rx_mode(eth_dev,
2008                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
2009         else
2010                 qed_configure_filter_rx_mode(eth_dev,
2011                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
2012 }
2013
2014 static int
2015 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
2016                       uint32_t mc_addrs_num)
2017 {
2018         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2019         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2020         uint8_t i;
2021
2022         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
2023                 DP_ERR(edev, "Reached max multicast filters limit,"
2024                              "Please enable multicast promisc mode\n");
2025                 return -ENOSPC;
2026         }
2027
2028         for (i = 0; i < mc_addrs_num; i++) {
2029                 if (!is_multicast_ether_addr(&mc_addrs[i])) {
2030                         DP_ERR(edev, "Not a valid multicast MAC\n");
2031                         return -EINVAL;
2032                 }
2033         }
2034
2035         /* Flush all existing entries */
2036         if (qede_del_mcast_filters(eth_dev))
2037                 return -1;
2038
2039         /* Set new mcast list */
2040         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
2041 }
2042
2043 /* Update MTU via vport-update without doing port restart.
2044  * The vport must be deactivated before calling this API.
2045  */
2046 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
2047 {
2048         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2049         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2050         struct ecore_hwfn *p_hwfn;
2051         int rc;
2052         int i;
2053
2054         if (IS_PF(edev)) {
2055                 struct ecore_sp_vport_update_params params;
2056
2057                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
2058                 params.vport_id = 0;
2059                 params.mtu = mtu;
2060                 params.vport_id = 0;
2061                 for_each_hwfn(edev, i) {
2062                         p_hwfn = &edev->hwfns[i];
2063                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2064                         rc = ecore_sp_vport_update(p_hwfn, &params,
2065                                         ECORE_SPQ_MODE_EBLOCK, NULL);
2066                         if (rc != ECORE_SUCCESS)
2067                                 goto err;
2068                 }
2069         } else {
2070                 for_each_hwfn(edev, i) {
2071                         p_hwfn = &edev->hwfns[i];
2072                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
2073                         if (rc == ECORE_INVAL) {
2074                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
2075                                 /* Recreate vport */
2076                                 rc = qede_start_vport(qdev, mtu);
2077                                 if (rc != ECORE_SUCCESS)
2078                                         goto err;
2079
2080                                 /* Restore config lost due to vport stop */
2081                                 qede_mac_addr_set(eth_dev, &qdev->primary_mac);
2082
2083                                 if (eth_dev->data->promiscuous)
2084                                         qede_promiscuous_enable(eth_dev);
2085                                 else
2086                                         qede_promiscuous_disable(eth_dev);
2087
2088                                 if (eth_dev->data->all_multicast)
2089                                         qede_allmulticast_enable(eth_dev);
2090                                 else
2091                                         qede_allmulticast_disable(eth_dev);
2092
2093                                 qede_vlan_offload_set(eth_dev,
2094                                                       qdev->vlan_offload_mask);
2095                         } else if (rc != ECORE_SUCCESS) {
2096                                 goto err;
2097                         }
2098                 }
2099         }
2100         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
2101
2102         return 0;
2103
2104 err:
2105         DP_ERR(edev, "Failed to update MTU\n");
2106         return -1;
2107 }
2108
2109 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2110                               struct rte_eth_fc_conf *fc_conf)
2111 {
2112         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2113         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2114         struct qed_link_output current_link;
2115         struct qed_link_params params;
2116
2117         memset(&current_link, 0, sizeof(current_link));
2118         qdev->ops->common->get_link(edev, &current_link);
2119
2120         memset(&params, 0, sizeof(params));
2121         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2122         if (fc_conf->autoneg) {
2123                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2124                         DP_ERR(edev, "Autoneg not supported\n");
2125                         return -EINVAL;
2126                 }
2127                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2128         }
2129
2130         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2131         if (fc_conf->mode == RTE_FC_FULL)
2132                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2133                                         QED_LINK_PAUSE_RX_ENABLE);
2134         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2135                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2136         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2137                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2138
2139         params.link_up = true;
2140         (void)qdev->ops->common->set_link(edev, &params);
2141
2142         return 0;
2143 }
2144
2145 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2146                               struct rte_eth_fc_conf *fc_conf)
2147 {
2148         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2149         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2150         struct qed_link_output current_link;
2151
2152         memset(&current_link, 0, sizeof(current_link));
2153         qdev->ops->common->get_link(edev, &current_link);
2154
2155         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2156                 fc_conf->autoneg = true;
2157
2158         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2159                                          QED_LINK_PAUSE_TX_ENABLE))
2160                 fc_conf->mode = RTE_FC_FULL;
2161         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2162                 fc_conf->mode = RTE_FC_RX_PAUSE;
2163         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2164                 fc_conf->mode = RTE_FC_TX_PAUSE;
2165         else
2166                 fc_conf->mode = RTE_FC_NONE;
2167
2168         return 0;
2169 }
2170
2171 static const uint32_t *
2172 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2173 {
2174         static const uint32_t ptypes[] = {
2175                 RTE_PTYPE_L2_ETHER,
2176                 RTE_PTYPE_L2_ETHER_VLAN,
2177                 RTE_PTYPE_L3_IPV4,
2178                 RTE_PTYPE_L3_IPV6,
2179                 RTE_PTYPE_L4_TCP,
2180                 RTE_PTYPE_L4_UDP,
2181                 RTE_PTYPE_TUNNEL_VXLAN,
2182                 RTE_PTYPE_L4_FRAG,
2183                 RTE_PTYPE_TUNNEL_GENEVE,
2184                 RTE_PTYPE_TUNNEL_GRE,
2185                 /* Inner */
2186                 RTE_PTYPE_INNER_L2_ETHER,
2187                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2188                 RTE_PTYPE_INNER_L3_IPV4,
2189                 RTE_PTYPE_INNER_L3_IPV6,
2190                 RTE_PTYPE_INNER_L4_TCP,
2191                 RTE_PTYPE_INNER_L4_UDP,
2192                 RTE_PTYPE_INNER_L4_FRAG,
2193                 RTE_PTYPE_UNKNOWN
2194         };
2195
2196         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2197                 return ptypes;
2198
2199         return NULL;
2200 }
2201
2202 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2203 {
2204         *rss_caps = 0;
2205         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2206         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2207         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2208         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2209         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2210         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2211         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2212         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2213 }
2214
2215 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2216                          struct rte_eth_rss_conf *rss_conf)
2217 {
2218         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2219         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2220         struct ecore_sp_vport_update_params vport_update_params;
2221         struct ecore_rss_params rss_params;
2222         struct ecore_hwfn *p_hwfn;
2223         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2224         uint64_t hf = rss_conf->rss_hf;
2225         uint8_t len = rss_conf->rss_key_len;
2226         uint8_t idx;
2227         uint8_t i;
2228         int rc;
2229
2230         memset(&vport_update_params, 0, sizeof(vport_update_params));
2231         memset(&rss_params, 0, sizeof(rss_params));
2232
2233         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2234                 (unsigned long)hf, len, key);
2235
2236         if (hf != 0) {
2237                 /* Enabling RSS */
2238                 DP_INFO(edev, "Enabling rss\n");
2239
2240                 /* RSS caps */
2241                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2242                 rss_params.update_rss_capabilities = 1;
2243
2244                 /* RSS hash key */
2245                 if (key) {
2246                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2247                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2248                                 return -EINVAL;
2249                         }
2250                         DP_INFO(edev, "Applying user supplied hash key\n");
2251                         rss_params.update_rss_key = 1;
2252                         memcpy(&rss_params.rss_key, key, len);
2253                 }
2254                 rss_params.rss_enable = 1;
2255         }
2256
2257         rss_params.update_rss_config = 1;
2258         /* tbl_size has to be set with capabilities */
2259         rss_params.rss_table_size_log = 7;
2260         vport_update_params.vport_id = 0;
2261         /* pass the L2 handles instead of qids */
2262         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2263                 idx = i % QEDE_RSS_COUNT(qdev);
2264                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2265         }
2266         vport_update_params.rss_params = &rss_params;
2267
2268         for_each_hwfn(edev, i) {
2269                 p_hwfn = &edev->hwfns[i];
2270                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2271                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2272                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2273                 if (rc) {
2274                         DP_ERR(edev, "vport-update for RSS failed\n");
2275                         return rc;
2276                 }
2277         }
2278         qdev->rss_enable = rss_params.rss_enable;
2279
2280         /* Update local structure for hash query */
2281         qdev->rss_conf.rss_hf = hf;
2282         qdev->rss_conf.rss_key_len = len;
2283         if (qdev->rss_enable) {
2284                 if  (qdev->rss_conf.rss_key == NULL) {
2285                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2286                         if (qdev->rss_conf.rss_key == NULL) {
2287                                 DP_ERR(edev, "No memory to store RSS key\n");
2288                                 return -ENOMEM;
2289                         }
2290                 }
2291                 if (key && len) {
2292                         DP_INFO(edev, "Storing RSS key\n");
2293                         memcpy(qdev->rss_conf.rss_key, key, len);
2294                 }
2295         } else if (!qdev->rss_enable && len == 0) {
2296                 if (qdev->rss_conf.rss_key) {
2297                         free(qdev->rss_conf.rss_key);
2298                         qdev->rss_conf.rss_key = NULL;
2299                         DP_INFO(edev, "Free RSS key\n");
2300                 }
2301         }
2302
2303         return 0;
2304 }
2305
2306 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2307                            struct rte_eth_rss_conf *rss_conf)
2308 {
2309         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2310
2311         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2312         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2313
2314         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2315                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2316                        rss_conf->rss_key_len);
2317         return 0;
2318 }
2319
2320 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2321                                     struct ecore_rss_params *rss)
2322 {
2323         int i, fn;
2324         bool rss_mode = 1; /* enable */
2325         struct ecore_queue_cid *cid;
2326         struct ecore_rss_params *t_rss;
2327
2328         /* In regular scenario, we'd simply need to take input handlers.
2329          * But in CMT, we'd have to split the handlers according to the
2330          * engine they were configured on. We'd then have to understand
2331          * whether RSS is really required, since 2-queues on CMT doesn't
2332          * require RSS.
2333          */
2334
2335         /* CMT should be round-robin */
2336         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2337                 cid = rss->rss_ind_table[i];
2338
2339                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2340                         t_rss = &rss[0];
2341                 else
2342                         t_rss = &rss[1];
2343
2344                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2345         }
2346
2347         t_rss = &rss[1];
2348         t_rss->update_rss_ind_table = 1;
2349         t_rss->rss_table_size_log = 7;
2350         t_rss->update_rss_config = 1;
2351
2352         /* Make sure RSS is actually required */
2353         for_each_hwfn(edev, fn) {
2354                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2355                      i++) {
2356                         if (rss[fn].rss_ind_table[i] !=
2357                             rss[fn].rss_ind_table[0])
2358                                 break;
2359                 }
2360
2361                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2362                         DP_INFO(edev,
2363                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2364                         rss_mode = 0;
2365                         goto out;
2366                 }
2367         }
2368
2369 out:
2370         t_rss->rss_enable = rss_mode;
2371
2372         return rss_mode;
2373 }
2374
2375 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2376                          struct rte_eth_rss_reta_entry64 *reta_conf,
2377                          uint16_t reta_size)
2378 {
2379         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2380         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2381         struct ecore_sp_vport_update_params vport_update_params;
2382         struct ecore_rss_params *params;
2383         struct ecore_hwfn *p_hwfn;
2384         uint16_t i, idx, shift;
2385         uint8_t entry;
2386         int rc = 0;
2387
2388         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2389                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2390                        reta_size);
2391                 return -EINVAL;
2392         }
2393
2394         memset(&vport_update_params, 0, sizeof(vport_update_params));
2395         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2396                              RTE_CACHE_LINE_SIZE);
2397         if (params == NULL) {
2398                 DP_ERR(edev, "failed to allocate memory\n");
2399                 return -ENOMEM;
2400         }
2401
2402         for (i = 0; i < reta_size; i++) {
2403                 idx = i / RTE_RETA_GROUP_SIZE;
2404                 shift = i % RTE_RETA_GROUP_SIZE;
2405                 if (reta_conf[idx].mask & (1ULL << shift)) {
2406                         entry = reta_conf[idx].reta[shift];
2407                         /* Pass rxq handles to ecore */
2408                         params->rss_ind_table[i] =
2409                                         qdev->fp_array[entry].rxq->handle;
2410                         /* Update the local copy for RETA query command */
2411                         qdev->rss_ind_table[i] = entry;
2412                 }
2413         }
2414
2415         params->update_rss_ind_table = 1;
2416         params->rss_table_size_log = 7;
2417         params->update_rss_config = 1;
2418
2419         /* Fix up RETA for CMT mode device */
2420         if (ECORE_IS_CMT(edev))
2421                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2422                                                             params);
2423         vport_update_params.vport_id = 0;
2424         /* Use the current value of rss_enable */
2425         params->rss_enable = qdev->rss_enable;
2426         vport_update_params.rss_params = params;
2427
2428         for_each_hwfn(edev, i) {
2429                 p_hwfn = &edev->hwfns[i];
2430                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2431                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2432                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2433                 if (rc) {
2434                         DP_ERR(edev, "vport-update for RSS failed\n");
2435                         goto out;
2436                 }
2437         }
2438
2439 out:
2440         rte_free(params);
2441         return rc;
2442 }
2443
2444 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2445                                struct rte_eth_rss_reta_entry64 *reta_conf,
2446                                uint16_t reta_size)
2447 {
2448         struct qede_dev *qdev = eth_dev->data->dev_private;
2449         struct ecore_dev *edev = &qdev->edev;
2450         uint16_t i, idx, shift;
2451         uint8_t entry;
2452
2453         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2454                 DP_ERR(edev, "reta_size %d is not supported\n",
2455                        reta_size);
2456                 return -EINVAL;
2457         }
2458
2459         for (i = 0; i < reta_size; i++) {
2460                 idx = i / RTE_RETA_GROUP_SIZE;
2461                 shift = i % RTE_RETA_GROUP_SIZE;
2462                 if (reta_conf[idx].mask & (1ULL << shift)) {
2463                         entry = qdev->rss_ind_table[i];
2464                         reta_conf[idx].reta[shift] = entry;
2465                 }
2466         }
2467
2468         return 0;
2469 }
2470
2471
2472
2473 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2474 {
2475         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2476         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2477         struct rte_eth_dev_info dev_info = {0};
2478         struct qede_fastpath *fp;
2479         uint32_t max_rx_pkt_len;
2480         uint32_t frame_size;
2481         uint16_t rx_buf_size;
2482         uint16_t bufsz;
2483         bool restart = false;
2484         int i;
2485
2486         PMD_INIT_FUNC_TRACE(edev);
2487         qede_dev_info_get(dev, &dev_info);
2488         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2489         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2490         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2491                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2492                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2493                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2494                 return -EINVAL;
2495         }
2496         if (!dev->data->scattered_rx &&
2497             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2498                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2499                         dev->data->min_rx_buf_size);
2500                 return -EINVAL;
2501         }
2502         /* Temporarily replace I/O functions with dummy ones. It cannot
2503          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2504          */
2505         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2506         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2507         if (dev->data->dev_started) {
2508                 dev->data->dev_started = 0;
2509                 qede_dev_stop(dev);
2510                 restart = true;
2511         } else {
2512                 if (IS_PF(edev))
2513                         qede_mac_addr_remove(dev, 0);
2514         }
2515         rte_delay_ms(1000);
2516         qdev->mtu = mtu;
2517
2518         /* Fix up RX buf size for all queues of the port */
2519         for_each_rss(i) {
2520                 fp = &qdev->fp_array[i];
2521                 if (fp->rxq != NULL) {
2522                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2523                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2524                         if (dev->data->scattered_rx)
2525                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2526                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2527                         else
2528                                 rx_buf_size = frame_size;
2529                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2530                         fp->rxq->rx_buf_size = rx_buf_size;
2531                         DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2532                 }
2533         }
2534         if (max_rx_pkt_len > ETHER_MAX_LEN)
2535                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2536         else
2537                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2538
2539         if (!dev->data->dev_started && restart) {
2540                 qede_dev_start(dev);
2541                 dev->data->dev_started = 1;
2542         }
2543
2544         /* update max frame size */
2545         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2546         /* Reassign back */
2547         dev->rx_pkt_burst = qede_recv_pkts;
2548         dev->tx_pkt_burst = qede_xmit_pkts;
2549
2550         return 0;
2551 }
2552
2553 static int
2554 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2555                       struct rte_eth_udp_tunnel *tunnel_udp)
2556 {
2557         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2558         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2559         struct ecore_tunnel_info tunn; /* @DPDK */
2560         uint16_t udp_port;
2561         int rc;
2562
2563         PMD_INIT_FUNC_TRACE(edev);
2564
2565         memset(&tunn, 0, sizeof(tunn));
2566
2567         switch (tunnel_udp->prot_type) {
2568         case RTE_TUNNEL_TYPE_VXLAN:
2569                 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2570                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2571                                 tunnel_udp->udp_port);
2572                         return ECORE_INVAL;
2573                 }
2574                 udp_port = 0;
2575
2576                 tunn.vxlan_port.b_update_port = true;
2577                 tunn.vxlan_port.port = udp_port;
2578
2579                 rc = qede_tunnel_update(qdev, &tunn);
2580                 if (rc != ECORE_SUCCESS) {
2581                         DP_ERR(edev, "Unable to config UDP port %u\n",
2582                                tunn.vxlan_port.port);
2583                         return rc;
2584                 }
2585
2586                 qdev->vxlan.udp_port = udp_port;
2587                 /* If the request is to delete UDP port and if the number of
2588                  * VXLAN filters have reached 0 then VxLAN offload can be be
2589                  * disabled.
2590                  */
2591                 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2592                         return qede_vxlan_enable(eth_dev,
2593                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2594
2595                 break;
2596         case RTE_TUNNEL_TYPE_GENEVE:
2597                 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2598                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2599                                 tunnel_udp->udp_port);
2600                         return ECORE_INVAL;
2601                 }
2602
2603                 udp_port = 0;
2604
2605                 tunn.geneve_port.b_update_port = true;
2606                 tunn.geneve_port.port = udp_port;
2607
2608                 rc = qede_tunnel_update(qdev, &tunn);
2609                 if (rc != ECORE_SUCCESS) {
2610                         DP_ERR(edev, "Unable to config UDP port %u\n",
2611                                tunn.vxlan_port.port);
2612                         return rc;
2613                 }
2614
2615                 qdev->vxlan.udp_port = udp_port;
2616                 /* If the request is to delete UDP port and if the number of
2617                  * GENEVE filters have reached 0 then GENEVE offload can be be
2618                  * disabled.
2619                  */
2620                 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2621                         return qede_geneve_enable(eth_dev,
2622                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2623
2624                 break;
2625
2626         default:
2627                 return ECORE_INVAL;
2628         }
2629
2630         return 0;
2631
2632 }
2633 static int
2634 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2635                       struct rte_eth_udp_tunnel *tunnel_udp)
2636 {
2637         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2638         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2639         struct ecore_tunnel_info tunn; /* @DPDK */
2640         uint16_t udp_port;
2641         int rc;
2642
2643         PMD_INIT_FUNC_TRACE(edev);
2644
2645         memset(&tunn, 0, sizeof(tunn));
2646
2647         switch (tunnel_udp->prot_type) {
2648         case RTE_TUNNEL_TYPE_VXLAN:
2649                 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2650                         DP_INFO(edev,
2651                                 "UDP port %u for VXLAN was already configured\n",
2652                                 tunnel_udp->udp_port);
2653                         return ECORE_SUCCESS;
2654                 }
2655
2656                 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2657                  * it was not enabled while adding VXLAN filter before UDP port
2658                  * update.
2659                  */
2660                 if (!qdev->vxlan.enable) {
2661                         rc = qede_vxlan_enable(eth_dev,
2662                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2663                         if (rc != ECORE_SUCCESS) {
2664                                 DP_ERR(edev, "Failed to enable VXLAN "
2665                                         "prior to updating UDP port\n");
2666                                 return rc;
2667                         }
2668                 }
2669                 udp_port = tunnel_udp->udp_port;
2670
2671                 tunn.vxlan_port.b_update_port = true;
2672                 tunn.vxlan_port.port = udp_port;
2673
2674                 rc = qede_tunnel_update(qdev, &tunn);
2675                 if (rc != ECORE_SUCCESS) {
2676                         DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2677                                udp_port);
2678                         return rc;
2679                 }
2680
2681                 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2682
2683                 qdev->vxlan.udp_port = udp_port;
2684                 break;
2685         case RTE_TUNNEL_TYPE_GENEVE:
2686                 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2687                         DP_INFO(edev,
2688                                 "UDP port %u for GENEVE was already configured\n",
2689                                 tunnel_udp->udp_port);
2690                         return ECORE_SUCCESS;
2691                 }
2692
2693                 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2694                  * it was not enabled while adding GENEVE filter before UDP port
2695                  * update.
2696                  */
2697                 if (!qdev->geneve.enable) {
2698                         rc = qede_geneve_enable(eth_dev,
2699                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2700                         if (rc != ECORE_SUCCESS) {
2701                                 DP_ERR(edev, "Failed to enable GENEVE "
2702                                         "prior to updating UDP port\n");
2703                                 return rc;
2704                         }
2705                 }
2706                 udp_port = tunnel_udp->udp_port;
2707
2708                 tunn.geneve_port.b_update_port = true;
2709                 tunn.geneve_port.port = udp_port;
2710
2711                 rc = qede_tunnel_update(qdev, &tunn);
2712                 if (rc != ECORE_SUCCESS) {
2713                         DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2714                                udp_port);
2715                         return rc;
2716                 }
2717
2718                 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2719
2720                 qdev->geneve.udp_port = udp_port;
2721                 break;
2722         default:
2723                 return ECORE_INVAL;
2724         }
2725
2726         return 0;
2727 }
2728
2729 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2730                                        uint32_t *clss, char *str)
2731 {
2732         uint16_t j;
2733         *clss = MAX_ECORE_TUNN_CLSS;
2734
2735         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2736                 if (filter == qede_tunn_types[j].rte_filter_type) {
2737                         *type = qede_tunn_types[j].qede_type;
2738                         *clss = qede_tunn_types[j].qede_tunn_clss;
2739                         strcpy(str, qede_tunn_types[j].string);
2740                         return;
2741                 }
2742         }
2743 }
2744
2745 static int
2746 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2747                               const struct rte_eth_tunnel_filter_conf *conf,
2748                               uint32_t type)
2749 {
2750         /* Init commmon ucast params first */
2751         qede_set_ucast_cmn_params(ucast);
2752
2753         /* Copy out the required fields based on classification type */
2754         ucast->type = type;
2755
2756         switch (type) {
2757         case ECORE_FILTER_VNI:
2758                 ucast->vni = conf->tenant_id;
2759         break;
2760         case ECORE_FILTER_INNER_VLAN:
2761                 ucast->vlan = conf->inner_vlan;
2762         break;
2763         case ECORE_FILTER_MAC:
2764                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2765                        ETHER_ADDR_LEN);
2766         break;
2767         case ECORE_FILTER_INNER_MAC:
2768                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2769                        ETHER_ADDR_LEN);
2770         break;
2771         case ECORE_FILTER_MAC_VNI_PAIR:
2772                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2773                         ETHER_ADDR_LEN);
2774                 ucast->vni = conf->tenant_id;
2775         break;
2776         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2777                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2778                         ETHER_ADDR_LEN);
2779                 ucast->vni = conf->tenant_id;
2780         break;
2781         case ECORE_FILTER_INNER_PAIR:
2782                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2783                         ETHER_ADDR_LEN);
2784                 ucast->vlan = conf->inner_vlan;
2785         break;
2786         default:
2787                 return -EINVAL;
2788         }
2789
2790         return ECORE_SUCCESS;
2791 }
2792
2793 static int
2794 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2795                          const struct rte_eth_tunnel_filter_conf *conf,
2796                          __attribute__((unused)) enum rte_filter_op filter_op,
2797                          enum ecore_tunn_clss *clss,
2798                          bool add)
2799 {
2800         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2801         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2802         struct ecore_filter_ucast ucast = {0};
2803         enum ecore_filter_ucast_type type;
2804         uint16_t filter_type = 0;
2805         char str[80];
2806         int rc;
2807
2808         filter_type = conf->filter_type;
2809         /* Determine if the given filter classification is supported */
2810         qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2811         if (*clss == MAX_ECORE_TUNN_CLSS) {
2812                 DP_ERR(edev, "Unsupported filter type\n");
2813                 return -EINVAL;
2814         }
2815         /* Init tunnel ucast params */
2816         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2817         if (rc != ECORE_SUCCESS) {
2818                 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2819                 conf->filter_type);
2820                 return rc;
2821         }
2822         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2823                 str, filter_op, ucast.type);
2824
2825         ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2826
2827         /* Skip MAC/VLAN if filter is based on VNI */
2828         if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2829                 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2830                 if ((rc == 0) && add) {
2831                         /* Enable accept anyvlan */
2832                         qede_config_accept_any_vlan(qdev, true);
2833                 }
2834         } else {
2835                 rc = qede_ucast_filter(eth_dev, &ucast, add);
2836                 if (rc == 0)
2837                         rc = ecore_filter_ucast_cmd(edev, &ucast,
2838                                             ECORE_SPQ_MODE_CB, NULL);
2839         }
2840
2841         return rc;
2842 }
2843
2844 static int
2845 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2846                         enum rte_filter_op filter_op,
2847                         const struct rte_eth_tunnel_filter_conf *conf)
2848 {
2849         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2850         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2851         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2852         bool add;
2853         int rc;
2854
2855         PMD_INIT_FUNC_TRACE(edev);
2856
2857         switch (filter_op) {
2858         case RTE_ETH_FILTER_ADD:
2859                 add = true;
2860                 break;
2861         case RTE_ETH_FILTER_DELETE:
2862                 add = false;
2863                 break;
2864         default:
2865                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2866                 return -EINVAL;
2867         }
2868
2869         if (IS_VF(edev))
2870                 return qede_tunn_enable(eth_dev,
2871                                         ECORE_TUNN_CLSS_MAC_VLAN,
2872                                         conf->tunnel_type, add);
2873
2874         rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2875         if (rc != ECORE_SUCCESS)
2876                 return rc;
2877
2878         if (add) {
2879                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2880                         qdev->vxlan.num_filters++;
2881                         qdev->vxlan.filter_type = conf->filter_type;
2882                 } else { /* GENEVE */
2883                         qdev->geneve.num_filters++;
2884                         qdev->geneve.filter_type = conf->filter_type;
2885                 }
2886
2887                 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2888                     !qdev->ipgre.enable)
2889                         return qede_tunn_enable(eth_dev, clss,
2890                                                 conf->tunnel_type,
2891                                                 true);
2892         } else {
2893                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2894                         qdev->vxlan.num_filters--;
2895                 else /*GENEVE*/
2896                         qdev->geneve.num_filters--;
2897
2898                 /* Disable VXLAN if VXLAN filters become 0 */
2899                 if ((qdev->vxlan.num_filters == 0) ||
2900                     (qdev->geneve.num_filters == 0))
2901                         return qede_tunn_enable(eth_dev, clss,
2902                                                 conf->tunnel_type,
2903                                                 false);
2904         }
2905
2906         return 0;
2907 }
2908
2909 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2910                          enum rte_filter_type filter_type,
2911                          enum rte_filter_op filter_op,
2912                          void *arg)
2913 {
2914         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2915         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2916         struct rte_eth_tunnel_filter_conf *filter_conf =
2917                         (struct rte_eth_tunnel_filter_conf *)arg;
2918
2919         switch (filter_type) {
2920         case RTE_ETH_FILTER_TUNNEL:
2921                 switch (filter_conf->tunnel_type) {
2922                 case RTE_TUNNEL_TYPE_VXLAN:
2923                 case RTE_TUNNEL_TYPE_GENEVE:
2924                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2925                         DP_INFO(edev,
2926                                 "Packet steering to the specified Rx queue"
2927                                 " is not supported with UDP tunneling");
2928                         return(qede_tunn_filter_config(eth_dev, filter_op,
2929                                                       filter_conf));
2930                 case RTE_TUNNEL_TYPE_TEREDO:
2931                 case RTE_TUNNEL_TYPE_NVGRE:
2932                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2933                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2934                                 filter_conf->tunnel_type);
2935                         return -EINVAL;
2936                 case RTE_TUNNEL_TYPE_NONE:
2937                 default:
2938                         return 0;
2939                 }
2940                 break;
2941         case RTE_ETH_FILTER_FDIR:
2942                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2943         case RTE_ETH_FILTER_NTUPLE:
2944                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2945         case RTE_ETH_FILTER_MACVLAN:
2946         case RTE_ETH_FILTER_ETHERTYPE:
2947         case RTE_ETH_FILTER_FLEXIBLE:
2948         case RTE_ETH_FILTER_SYN:
2949         case RTE_ETH_FILTER_HASH:
2950         case RTE_ETH_FILTER_L2_TUNNEL:
2951         case RTE_ETH_FILTER_MAX:
2952         default:
2953                 DP_ERR(edev, "Unsupported filter type %d\n",
2954                         filter_type);
2955                 return -EINVAL;
2956         }
2957
2958         return 0;
2959 }
2960
2961 static const struct eth_dev_ops qede_eth_dev_ops = {
2962         .dev_configure = qede_dev_configure,
2963         .dev_infos_get = qede_dev_info_get,
2964         .rx_queue_setup = qede_rx_queue_setup,
2965         .rx_queue_release = qede_rx_queue_release,
2966         .tx_queue_setup = qede_tx_queue_setup,
2967         .tx_queue_release = qede_tx_queue_release,
2968         .dev_start = qede_dev_start,
2969         .dev_set_link_up = qede_dev_set_link_up,
2970         .dev_set_link_down = qede_dev_set_link_down,
2971         .link_update = qede_link_update,
2972         .promiscuous_enable = qede_promiscuous_enable,
2973         .promiscuous_disable = qede_promiscuous_disable,
2974         .allmulticast_enable = qede_allmulticast_enable,
2975         .allmulticast_disable = qede_allmulticast_disable,
2976         .set_mc_addr_list = qede_set_mc_addr_list,
2977         .dev_stop = qede_dev_stop,
2978         .dev_close = qede_dev_close,
2979         .stats_get = qede_get_stats,
2980         .stats_reset = qede_reset_stats,
2981         .xstats_get = qede_get_xstats,
2982         .xstats_reset = qede_reset_xstats,
2983         .xstats_get_names = qede_get_xstats_names,
2984         .mac_addr_add = qede_mac_addr_add,
2985         .mac_addr_remove = qede_mac_addr_remove,
2986         .mac_addr_set = qede_mac_addr_set,
2987         .vlan_offload_set = qede_vlan_offload_set,
2988         .vlan_filter_set = qede_vlan_filter_set,
2989         .flow_ctrl_set = qede_flow_ctrl_set,
2990         .flow_ctrl_get = qede_flow_ctrl_get,
2991         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2992         .rss_hash_update = qede_rss_hash_update,
2993         .rss_hash_conf_get = qede_rss_hash_conf_get,
2994         .reta_update  = qede_rss_reta_update,
2995         .reta_query  = qede_rss_reta_query,
2996         .mtu_set = qede_set_mtu,
2997         .filter_ctrl = qede_dev_filter_ctrl,
2998         .udp_tunnel_port_add = qede_udp_dst_port_add,
2999         .udp_tunnel_port_del = qede_udp_dst_port_del,
3000 };
3001
3002 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
3003         .dev_configure = qede_dev_configure,
3004         .dev_infos_get = qede_dev_info_get,
3005         .rx_queue_setup = qede_rx_queue_setup,
3006         .rx_queue_release = qede_rx_queue_release,
3007         .tx_queue_setup = qede_tx_queue_setup,
3008         .tx_queue_release = qede_tx_queue_release,
3009         .dev_start = qede_dev_start,
3010         .dev_set_link_up = qede_dev_set_link_up,
3011         .dev_set_link_down = qede_dev_set_link_down,
3012         .link_update = qede_link_update,
3013         .promiscuous_enable = qede_promiscuous_enable,
3014         .promiscuous_disable = qede_promiscuous_disable,
3015         .allmulticast_enable = qede_allmulticast_enable,
3016         .allmulticast_disable = qede_allmulticast_disable,
3017         .set_mc_addr_list = qede_set_mc_addr_list,
3018         .dev_stop = qede_dev_stop,
3019         .dev_close = qede_dev_close,
3020         .stats_get = qede_get_stats,
3021         .stats_reset = qede_reset_stats,
3022         .xstats_get = qede_get_xstats,
3023         .xstats_reset = qede_reset_xstats,
3024         .xstats_get_names = qede_get_xstats_names,
3025         .vlan_offload_set = qede_vlan_offload_set,
3026         .vlan_filter_set = qede_vlan_filter_set,
3027         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
3028         .rss_hash_update = qede_rss_hash_update,
3029         .rss_hash_conf_get = qede_rss_hash_conf_get,
3030         .reta_update  = qede_rss_reta_update,
3031         .reta_query  = qede_rss_reta_query,
3032         .mtu_set = qede_set_mtu,
3033         .udp_tunnel_port_add = qede_udp_dst_port_add,
3034         .udp_tunnel_port_del = qede_udp_dst_port_del,
3035         .mac_addr_add = qede_mac_addr_add,
3036         .mac_addr_remove = qede_mac_addr_remove,
3037         .mac_addr_set = qede_mac_addr_set,
3038 };
3039
3040 static void qede_update_pf_params(struct ecore_dev *edev)
3041 {
3042         struct ecore_pf_params pf_params;
3043
3044         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
3045         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
3046         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
3047         qed_ops->common->update_pf_params(edev, &pf_params);
3048 }
3049
3050 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
3051 {
3052         struct rte_pci_device *pci_dev;
3053         struct rte_pci_addr pci_addr;
3054         struct qede_dev *adapter;
3055         struct ecore_dev *edev;
3056         struct qed_dev_eth_info dev_info;
3057         struct qed_slowpath_params params;
3058         static bool do_once = true;
3059         uint8_t bulletin_change;
3060         uint8_t vf_mac[ETHER_ADDR_LEN];
3061         uint8_t is_mac_forced;
3062         bool is_mac_exist;
3063         /* Fix up ecore debug level */
3064         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3065         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3066         int rc;
3067
3068         /* Extract key data structures */
3069         adapter = eth_dev->data->dev_private;
3070         adapter->ethdev = eth_dev;
3071         edev = &adapter->edev;
3072         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3073         pci_addr = pci_dev->addr;
3074
3075         PMD_INIT_FUNC_TRACE(edev);
3076
3077         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3078                  pci_addr.bus, pci_addr.devid, pci_addr.function,
3079                  eth_dev->data->port_id);
3080
3081         eth_dev->rx_pkt_burst = qede_recv_pkts;
3082         eth_dev->tx_pkt_burst = qede_xmit_pkts;
3083         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3084
3085         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3086                 DP_ERR(edev, "Skipping device init from secondary process\n");
3087                 return 0;
3088         }
3089
3090         rte_eth_copy_pci_info(eth_dev, pci_dev);
3091
3092         /* @DPDK */
3093         edev->vendor_id = pci_dev->id.vendor_id;
3094         edev->device_id = pci_dev->id.device_id;
3095
3096         qed_ops = qed_get_eth_ops();
3097         if (!qed_ops) {
3098                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3099                 return -EINVAL;
3100         }
3101
3102         DP_INFO(edev, "Starting qede probe\n");
3103         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3104                                     dp_level, is_vf);
3105         if (rc != 0) {
3106                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3107                 return -ENODEV;
3108         }
3109         qede_update_pf_params(edev);
3110         rte_intr_callback_register(&pci_dev->intr_handle,
3111                                    qede_interrupt_handler, (void *)eth_dev);
3112         if (rte_intr_enable(&pci_dev->intr_handle)) {
3113                 DP_ERR(edev, "rte_intr_enable() failed\n");
3114                 return -ENODEV;
3115         }
3116
3117         /* Start the Slowpath-process */
3118         memset(&params, 0, sizeof(struct qed_slowpath_params));
3119         params.int_mode = ECORE_INT_MODE_MSIX;
3120         params.drv_major = QEDE_PMD_VERSION_MAJOR;
3121         params.drv_minor = QEDE_PMD_VERSION_MINOR;
3122         params.drv_rev = QEDE_PMD_VERSION_REVISION;
3123         params.drv_eng = QEDE_PMD_VERSION_PATCH;
3124         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3125                 QEDE_PMD_DRV_VER_STR_SIZE);
3126
3127         /* For CMT mode device do periodic polling for slowpath events.
3128          * This is required since uio device uses only one MSI-x
3129          * interrupt vector but we need one for each engine.
3130          */
3131         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3132                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
3133                                        qede_poll_sp_sb_cb,
3134                                        (void *)eth_dev);
3135                 if (rc != 0) {
3136                         DP_ERR(edev, "Unable to start periodic"
3137                                      " timer rc %d\n", rc);
3138                         return -EINVAL;
3139                 }
3140         }
3141
3142         rc = qed_ops->common->slowpath_start(edev, &params);
3143         if (rc) {
3144                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3145                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3146                                      (void *)eth_dev);
3147                 return -ENODEV;
3148         }
3149
3150         rc = qed_ops->fill_dev_info(edev, &dev_info);
3151         if (rc) {
3152                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3153                 qed_ops->common->slowpath_stop(edev);
3154                 qed_ops->common->remove(edev);
3155                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3156                                      (void *)eth_dev);
3157                 return -ENODEV;
3158         }
3159
3160         qede_alloc_etherdev(adapter, &dev_info);
3161
3162         adapter->ops->common->set_name(edev, edev->name);
3163
3164         if (!is_vf)
3165                 adapter->dev_info.num_mac_filters =
3166                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3167                                             ECORE_MAC);
3168         else
3169                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3170                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
3171
3172         /* Allocate memory for storing MAC addr */
3173         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3174                                         (ETHER_ADDR_LEN *
3175                                         adapter->dev_info.num_mac_filters),
3176                                         RTE_CACHE_LINE_SIZE);
3177
3178         if (eth_dev->data->mac_addrs == NULL) {
3179                 DP_ERR(edev, "Failed to allocate MAC address\n");
3180                 qed_ops->common->slowpath_stop(edev);
3181                 qed_ops->common->remove(edev);
3182                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3183                                      (void *)eth_dev);
3184                 return -ENOMEM;
3185         }
3186
3187         if (!is_vf) {
3188                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3189                                 hw_info.hw_mac_addr,
3190                                 &eth_dev->data->mac_addrs[0]);
3191                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3192                                 &adapter->primary_mac);
3193         } else {
3194                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3195                                        &bulletin_change);
3196                 if (bulletin_change) {
3197                         is_mac_exist =
3198                             ecore_vf_bulletin_get_forced_mac(
3199                                                 ECORE_LEADING_HWFN(edev),
3200                                                 vf_mac,
3201                                                 &is_mac_forced);
3202                         if (is_mac_exist) {
3203                                 DP_INFO(edev, "VF macaddr received from PF\n");
3204                                 ether_addr_copy((struct ether_addr *)&vf_mac,
3205                                                 &eth_dev->data->mac_addrs[0]);
3206                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3207                                                 &adapter->primary_mac);
3208                         } else {
3209                                 DP_ERR(edev, "No VF macaddr assigned\n");
3210                         }
3211                 }
3212         }
3213
3214         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3215
3216         if (do_once) {
3217                 qede_print_adapter_info(adapter);
3218                 do_once = false;
3219         }
3220
3221         /* Bring-up the link */
3222         qede_dev_set_link_state(eth_dev, true);
3223
3224         adapter->num_tx_queues = 0;
3225         adapter->num_rx_queues = 0;
3226         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3227         SLIST_INIT(&adapter->vlan_list_head);
3228         SLIST_INIT(&adapter->uc_list_head);
3229         SLIST_INIT(&adapter->mc_list_head);
3230         adapter->mtu = ETHER_MTU;
3231         adapter->vport_started = false;
3232
3233         /* VF tunnel offloads is enabled by default in PF driver */
3234         adapter->vxlan.num_filters = 0;
3235         adapter->geneve.num_filters = 0;
3236         adapter->ipgre.num_filters = 0;
3237         if (is_vf) {
3238                 adapter->vxlan.enable = true;
3239                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3240                                              ETH_TUNNEL_FILTER_IVLAN;
3241                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3242                 adapter->geneve.enable = true;
3243                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3244                                               ETH_TUNNEL_FILTER_IVLAN;
3245                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3246                 adapter->ipgre.enable = true;
3247                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3248                                              ETH_TUNNEL_FILTER_IVLAN;
3249         } else {
3250                 adapter->vxlan.enable = false;
3251                 adapter->geneve.enable = false;
3252                 adapter->ipgre.enable = false;
3253         }
3254
3255         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3256                 adapter->primary_mac.addr_bytes[0],
3257                 adapter->primary_mac.addr_bytes[1],
3258                 adapter->primary_mac.addr_bytes[2],
3259                 adapter->primary_mac.addr_bytes[3],
3260                 adapter->primary_mac.addr_bytes[4],
3261                 adapter->primary_mac.addr_bytes[5]);
3262
3263         DP_INFO(edev, "Device initialized\n");
3264
3265         return 0;
3266 }
3267
3268 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3269 {
3270         return qede_common_dev_init(eth_dev, 1);
3271 }
3272
3273 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3274 {
3275         return qede_common_dev_init(eth_dev, 0);
3276 }
3277
3278 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3279 {
3280 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3281         struct qede_dev *qdev = eth_dev->data->dev_private;
3282         struct ecore_dev *edev = &qdev->edev;
3283
3284         PMD_INIT_FUNC_TRACE(edev);
3285 #endif
3286
3287         /* only uninitialize in the primary process */
3288         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3289                 return 0;
3290
3291         /* safe to close dev here */
3292         qede_dev_close(eth_dev);
3293
3294         eth_dev->dev_ops = NULL;
3295         eth_dev->rx_pkt_burst = NULL;
3296         eth_dev->tx_pkt_burst = NULL;
3297
3298         if (eth_dev->data->mac_addrs)
3299                 rte_free(eth_dev->data->mac_addrs);
3300
3301         eth_dev->data->mac_addrs = NULL;
3302
3303         return 0;
3304 }
3305
3306 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3307 {
3308         return qede_dev_common_uninit(eth_dev);
3309 }
3310
3311 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3312 {
3313         return qede_dev_common_uninit(eth_dev);
3314 }
3315
3316 static const struct rte_pci_id pci_id_qedevf_map[] = {
3317 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3318         {
3319                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3320         },
3321         {
3322                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3323         },
3324         {
3325                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3326         },
3327         {.vendor_id = 0,}
3328 };
3329
3330 static const struct rte_pci_id pci_id_qede_map[] = {
3331 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3332         {
3333                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3334         },
3335         {
3336                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3337         },
3338         {
3339                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3340         },
3341         {
3342                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3343         },
3344         {
3345                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3346         },
3347         {
3348                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3349         },
3350         {
3351                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3352         },
3353         {
3354                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3355         },
3356         {
3357                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3358         },
3359         {
3360                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3361         },
3362         {.vendor_id = 0,}
3363 };
3364
3365 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3366         struct rte_pci_device *pci_dev)
3367 {
3368         return rte_eth_dev_pci_generic_probe(pci_dev,
3369                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3370 }
3371
3372 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3373 {
3374         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3375 }
3376
3377 static struct rte_pci_driver rte_qedevf_pmd = {
3378         .id_table = pci_id_qedevf_map,
3379         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3380         .probe = qedevf_eth_dev_pci_probe,
3381         .remove = qedevf_eth_dev_pci_remove,
3382 };
3383
3384 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3385         struct rte_pci_device *pci_dev)
3386 {
3387         return rte_eth_dev_pci_generic_probe(pci_dev,
3388                 sizeof(struct qede_dev), qede_eth_dev_init);
3389 }
3390
3391 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3392 {
3393         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3394 }
3395
3396 static struct rte_pci_driver rte_qede_pmd = {
3397         .id_table = pci_id_qede_map,
3398         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3399         .probe = qede_eth_dev_pci_probe,
3400         .remove = qede_eth_dev_pci_remove,
3401 };
3402
3403 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3404 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3405 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3406 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3407 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3408 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3409
3410 RTE_INIT(qede_init_log);
3411 static void
3412 qede_init_log(void)
3413 {
3414         qede_logtype_init = rte_log_register("pmd.net.qede.init");
3415         if (qede_logtype_init >= 0)
3416                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3417         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3418         if (qede_logtype_driver >= 0)
3419                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
3420 }