1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
9 #if EFSYS_OPT_MON_STATS
16 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
18 (_eep)->ee_stat[_stat]++; \
19 _NOTE(CONSTANTCONDITION) \
22 #define EFX_EV_QSTAT_INCR(_eep, _stat)
26 * Non-interrupting event queue requires interrrupting event queue to
27 * refer to for wake-up events even if wake ups are never used.
28 * It could be even non-allocated event queue.
30 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
32 static __checkReturn boolean_t
35 __in efx_qword_t *eqp,
36 __in const efx_ev_callbacks_t *eecp,
39 static __checkReturn boolean_t
42 __in efx_qword_t *eqp,
43 __in const efx_ev_callbacks_t *eecp,
46 static __checkReturn boolean_t
49 __in efx_qword_t *eqp,
50 __in const efx_ev_callbacks_t *eecp,
53 static __checkReturn boolean_t
56 __in efx_qword_t *eqp,
57 __in const efx_ev_callbacks_t *eecp,
60 static __checkReturn boolean_t
63 __in efx_qword_t *eqp,
64 __in const efx_ev_callbacks_t *eecp,
68 static __checkReturn efx_rc_t
71 __in uint32_t instance,
73 __in uint32_t timer_ns)
76 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_EVQ_TMR_IN_LEN,
77 MC_CMD_SET_EVQ_TMR_OUT_LEN);
80 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
81 req.emr_in_buf = payload;
82 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
83 req.emr_out_buf = payload;
84 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
86 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
87 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
88 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
89 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
91 efx_mcdi_execute(enp, &req);
93 if (req.emr_rc != 0) {
98 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
108 EFSYS_PROBE1(fail1, efx_rc_t, rc);
113 static __checkReturn efx_rc_t
116 __in unsigned int instance,
117 __in efsys_mem_t *esmp,
122 __in boolean_t low_latency)
125 EFX_MCDI_DECLARE_BUF(payload,
126 MC_CMD_INIT_EVQ_IN_LEN(EF10_EVQ_MAXNBUFS),
127 MC_CMD_INIT_EVQ_OUT_LEN);
128 efx_qword_t *dma_addr;
132 boolean_t interrupting;
136 npages = efx_evq_nbufs(enp, nevs);
137 if (npages > EF10_EVQ_MAXNBUFS) {
142 req.emr_cmd = MC_CMD_INIT_EVQ;
143 req.emr_in_buf = payload;
144 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
145 req.emr_out_buf = payload;
146 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
148 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
149 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
150 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
152 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
153 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
156 * On Huntington RX and TX event batching can only be requested together
157 * (even if the datapath firmware doesn't actually support RX
158 * batching). If event cut through is enabled no RX batching will occur.
160 * So always enable RX and TX event batching, and enable event cut
161 * through if we want low latency operation.
163 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
164 case EFX_EVQ_FLAGS_TYPE_AUTO:
165 ev_cut_through = low_latency ? 1 : 0;
167 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
170 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
177 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
178 INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting,
179 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
180 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
181 INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through,
182 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
183 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
185 /* If the value is zero then disable the timer */
187 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
188 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
189 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
190 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
194 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
197 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
198 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
199 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks);
200 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks);
203 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
204 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
205 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
207 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
208 addr = EFSYS_MEM_ADDR(esmp);
210 for (i = 0; i < npages; i++) {
211 EFX_POPULATE_QWORD_2(*dma_addr,
212 EFX_DWORD_1, (uint32_t)(addr >> 32),
213 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
216 addr += EFX_BUF_SIZE;
219 efx_mcdi_execute(enp, &req);
221 if (req.emr_rc != 0) {
226 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
231 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
244 EFSYS_PROBE1(fail1, efx_rc_t, rc);
250 static __checkReturn efx_rc_t
251 efx_mcdi_init_evq_v2(
253 __in unsigned int instance,
254 __in efsys_mem_t *esmp,
261 EFX_MCDI_DECLARE_BUF(payload,
262 MC_CMD_INIT_EVQ_V2_IN_LEN(EF10_EVQ_MAXNBUFS),
263 MC_CMD_INIT_EVQ_V2_OUT_LEN);
264 boolean_t interrupting;
265 unsigned int evq_type;
266 efx_qword_t *dma_addr;
272 npages = efx_evq_nbufs(enp, nevs);
273 if (npages > EF10_EVQ_MAXNBUFS) {
278 req.emr_cmd = MC_CMD_INIT_EVQ;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;
284 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);
285 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);
286 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);
288 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
289 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
291 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
292 case EFX_EVQ_FLAGS_TYPE_AUTO:
293 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;
295 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
296 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;
298 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
299 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;
305 MCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,
306 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,
307 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,
308 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,
309 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);
311 /* If the value is zero then disable the timer */
313 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
314 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);
315 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);
316 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);
320 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
323 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
324 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);
325 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);
326 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);
329 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,
330 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);
331 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);
333 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);
334 addr = EFSYS_MEM_ADDR(esmp);
336 for (i = 0; i < npages; i++) {
337 EFX_POPULATE_QWORD_2(*dma_addr,
338 EFX_DWORD_1, (uint32_t)(addr >> 32),
339 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
342 addr += EFX_BUF_SIZE;
345 efx_mcdi_execute(enp, &req);
347 if (req.emr_rc != 0) {
352 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {
357 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
359 EFSYS_PROBE1(mcdi_evq_flags, uint32_t,
360 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));
373 EFSYS_PROBE1(fail1, efx_rc_t, rc);
378 static __checkReturn efx_rc_t
381 __in uint32_t instance)
384 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_EVQ_IN_LEN,
385 MC_CMD_FINI_EVQ_OUT_LEN);
388 req.emr_cmd = MC_CMD_FINI_EVQ;
389 req.emr_in_buf = payload;
390 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
391 req.emr_out_buf = payload;
392 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
394 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
396 efx_mcdi_execute_quiet(enp, &req);
398 if (req.emr_rc != 0) {
407 * EALREADY is not an error, but indicates that the MC has rebooted and
408 * that the EVQ has already been destroyed.
411 EFSYS_PROBE1(fail1, efx_rc_t, rc);
418 __checkReturn efx_rc_t
422 _NOTE(ARGUNUSED(enp))
430 _NOTE(ARGUNUSED(enp))
433 __checkReturn efx_rc_t
436 __in unsigned int index,
437 __in efsys_mem_t *esmp,
444 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
448 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
450 if (index >= encp->enc_evq_limit) {
455 if (us > encp->enc_evq_timer_max_us) {
461 * NO_CONT_EV mode is only requested from the firmware when creating
462 * receive queues, but here it needs to be specified at event queue
463 * creation, as the event handler needs to know which format is in use.
465 * If EFX_EVQ_FLAGS_NO_CONT_EV is specified, all receive queues for this
466 * event queue will be created in NO_CONT_EV mode.
468 * See SF-109306-TC 5.11 "Events for RXQs in NO_CONT_EV mode".
470 if (flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
471 if (enp->en_nic_cfg.enc_no_cont_ev_mode_supported == B_FALSE) {
477 /* Set up the handler table */
478 eep->ee_rx = ef10_ev_rx;
479 eep->ee_tx = ef10_ev_tx;
480 eep->ee_driver = ef10_ev_driver;
481 eep->ee_drv_gen = ef10_ev_drv_gen;
482 eep->ee_mcdi = ef10_ev_mcdi;
484 /* Set up the event queue */
485 /* INIT_EVQ expects function-relative vector number */
486 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
487 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
489 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
491 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
492 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
494 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
498 * Interrupts may be raised for events immediately after the queue is
499 * created. See bug58606.
502 if (encp->enc_init_evq_v2_supported) {
504 * On Medford the low latency license is required to enable RX
505 * and event cut through and to disable RX batching. If event
506 * queue type in flags is auto, we let the firmware decide the
507 * settings to use. If the adapter has a low latency license,
508 * it will choose the best settings for low latency, otherwise
509 * it will choose the best settings for throughput.
511 rc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,
517 * On Huntington we need to specify the settings to use.
518 * If event queue type in flags is auto, we favour throughput
519 * if the adapter is running virtualization supporting firmware
520 * (i.e. the full featured firmware variant)
521 * and latency otherwise. The Ethernet Virtual Bridging
522 * capability is used to make this decision. (Note though that
523 * the low latency firmware variant is also best for
524 * throughput and corresponding type should be specified
527 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
528 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
545 EFSYS_PROBE1(fail1, efx_rc_t, rc);
554 efx_nic_t *enp = eep->ee_enp;
556 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
558 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
561 __checkReturn efx_rc_t
564 __in unsigned int count)
566 efx_nic_t *enp = eep->ee_enp;
570 rptr = count & eep->ee_mask;
572 if (enp->en_nic_cfg.enc_bug35388_workaround) {
573 EFX_STATIC_ASSERT(EF10_EVQ_MINNEVS >
574 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
575 EFX_STATIC_ASSERT(EF10_EVQ_MAXNEVS <
576 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
578 EFX_POPULATE_DWORD_2(dword,
579 ERF_DD_EVQ_IND_RPTR_FLAGS,
580 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
582 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
583 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
586 EFX_POPULATE_DWORD_2(dword,
587 ERF_DD_EVQ_IND_RPTR_FLAGS,
588 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
590 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
591 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
594 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
595 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
602 static __checkReturn efx_rc_t
603 efx_mcdi_driver_event(
606 __in efx_qword_t data)
609 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRIVER_EVENT_IN_LEN,
610 MC_CMD_DRIVER_EVENT_OUT_LEN);
613 req.emr_cmd = MC_CMD_DRIVER_EVENT;
614 req.emr_in_buf = payload;
615 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
616 req.emr_out_buf = payload;
617 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
619 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
621 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
622 EFX_QWORD_FIELD(data, EFX_DWORD_0));
623 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
624 EFX_QWORD_FIELD(data, EFX_DWORD_1));
626 efx_mcdi_execute(enp, &req);
628 if (req.emr_rc != 0) {
636 EFSYS_PROBE1(fail1, efx_rc_t, rc);
646 efx_nic_t *enp = eep->ee_enp;
649 EFX_POPULATE_QWORD_3(event,
650 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
651 ESF_DZ_DRV_SUB_CODE, 0,
652 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
654 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
657 __checkReturn efx_rc_t
660 __in unsigned int us)
662 efx_nic_t *enp = eep->ee_enp;
663 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
668 /* Check that hardware and MCDI use the same timer MODE values */
669 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
670 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
671 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
672 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
673 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
674 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
675 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
676 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
678 if (us > encp->enc_evq_timer_max_us) {
683 /* If the value is zero then disable the timer */
685 mode = FFE_CZ_TIMER_MODE_DIS;
687 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
690 if (encp->enc_bug61265_workaround) {
691 uint32_t ns = us * 1000;
693 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
699 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
702 if (encp->enc_bug35388_workaround) {
703 EFX_POPULATE_DWORD_3(dword,
704 ERF_DD_EVQ_IND_TIMER_FLAGS,
705 EFE_DD_EVQ_IND_TIMER_FLAGS,
706 ERF_DD_EVQ_IND_TIMER_MODE, mode,
707 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
708 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
709 eep->ee_index, &dword, 0);
712 * NOTE: The TMR_REL field introduced in Medford2 is
713 * ignored on earlier EF10 controllers. See bug66418
714 * comment 9 for details.
716 EFX_POPULATE_DWORD_3(dword,
717 ERF_DZ_TC_TIMER_MODE, mode,
718 ERF_DZ_TC_TIMER_VAL, ticks,
719 ERF_FZ_TC_TMR_REL_VAL, ticks);
720 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
721 eep->ee_index, &dword, 0);
732 EFSYS_PROBE1(fail1, efx_rc_t, rc);
740 ef10_ev_qstats_update(
742 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
746 for (id = 0; id < EV_NQSTATS; id++) {
747 efsys_stat_t *essp = &stat[id];
749 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
750 eep->ee_stat[id] = 0;
753 #endif /* EFSYS_OPT_QSTATS */
755 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
757 static __checkReturn boolean_t
758 ef10_ev_rx_packed_stream(
760 __in efx_qword_t *eqp,
761 __in const efx_ev_callbacks_t *eecp,
765 uint32_t pkt_count_lbits;
767 boolean_t should_abort;
768 efx_evq_rxq_state_t *eersp;
769 unsigned int pkt_count;
770 unsigned int current_id;
771 boolean_t new_buffer;
773 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
774 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
775 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
779 eersp = &eep->ee_rxq_state[label];
782 * RX_DSC_PTR_LBITS has least significant bits of the global
783 * (not per-buffer) packet counter. It is guaranteed that
784 * maximum number of completed packets fits in lbits-mask.
785 * So, modulo lbits-mask arithmetic should be used to calculate
786 * packet counter increment.
788 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
789 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
790 eersp->eers_rx_stream_npackets += pkt_count;
793 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
794 #if EFSYS_OPT_RX_PACKED_STREAM
796 * If both packed stream and equal stride super-buffer
797 * modes are compiled in, in theory credits should be
798 * be maintained for packed stream only, but right now
799 * these modes are not distinguished in the event queue
800 * Rx queue state and it is OK to increment the counter
801 * regardless (it might be event cheaper than branching
802 * since neighbour structure member are updated as well).
804 eersp->eers_rx_packed_stream_credits++;
806 eersp->eers_rx_read_ptr++;
808 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
810 /* Check for errors that invalidate checksum and L3/L4 fields */
811 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
812 /* RX frame truncated */
813 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
814 flags |= EFX_DISCARD;
817 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
818 /* Bad Ethernet frame CRC */
819 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
820 flags |= EFX_DISCARD;
824 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
825 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
826 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
830 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
831 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
833 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
834 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
837 /* If we're not discarding the packet then it is ok */
838 if (~flags & EFX_DISCARD)
839 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
841 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
842 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
845 return (should_abort);
848 #endif /* EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER */
850 static __checkReturn boolean_t
853 __in efx_qword_t *eqp,
854 __in const efx_ev_callbacks_t *eecp,
857 efx_nic_t *enp = eep->ee_enp;
861 uint32_t eth_tag_class;
864 uint32_t next_read_lbits;
867 boolean_t should_abort;
868 efx_evq_rxq_state_t *eersp;
869 unsigned int desc_count;
870 unsigned int last_used_id;
872 EFX_EV_QSTAT_INCR(eep, EV_RX);
874 /* Discard events after RXQ/TXQ errors, or hardware not available */
875 if (enp->en_reset_flags &
876 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
879 /* Basic packet information */
880 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
881 eersp = &eep->ee_rxq_state[label];
883 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
885 * Packed stream events are very different,
886 * so handle them separately
888 if (eersp->eers_rx_packed_stream)
889 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
892 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
893 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
894 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
895 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
896 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
897 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
900 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
901 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
902 * and values for all EF10 controllers.
904 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
905 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
906 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
907 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
909 l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
911 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
912 /* Drop this event */
919 * This may be part of a scattered frame, or it may be a
920 * truncated frame if scatter is disabled on this RXQ.
921 * Overlength frames can be received if e.g. a VF is configured
922 * for 1500 MTU but connected to a port set to 9000 MTU
924 * FIXME: There is not yet any driver that supports scatter on
925 * Huntington. Scatter support is required for OSX.
927 flags |= EFX_PKT_CONT;
930 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
931 flags |= EFX_PKT_UNICAST;
934 * Increment the count of descriptors read.
936 * In NO_CONT_EV mode, RX_DSC_PTR_LBITS is actually a packet count, but
937 * when scatter is disabled, there is only one descriptor per packet and
938 * so it can be treated the same.
940 * TODO: Support scatter in NO_CONT_EV mode.
942 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
943 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
944 eersp->eers_rx_read_ptr += desc_count;
946 /* Calculate the index of the last descriptor consumed */
947 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
949 if (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
951 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
953 /* Always read the length from the prefix in NO_CONT_EV mode. */
954 flags |= EFX_PKT_PREFIX_LEN;
957 * Check for an aborted scatter, signalled by the ABORT bit in
958 * NO_CONT_EV mode. The ABORT bit was not used before NO_CONT_EV
959 * mode was added as it was broken in Huntington silicon.
961 if (EFX_QWORD_FIELD(*eqp, ESF_EZ_RX_ABORT) != 0) {
962 flags |= EFX_DISCARD;
965 } else if (desc_count > 1) {
967 * FIXME: add error checking to make sure this a batched event.
968 * This could also be an aborted scatter, see Bug36629.
970 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
971 flags |= EFX_PKT_PREFIX_LEN;
974 /* Check for errors that invalidate checksum and L3/L4 fields */
975 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
976 /* RX frame truncated */
977 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
978 flags |= EFX_DISCARD;
981 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
982 /* Bad Ethernet frame CRC */
983 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
984 flags |= EFX_DISCARD;
987 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
989 * Hardware parse failed, due to malformed headers
990 * or headers that are too long for the parser.
991 * Headers and checksums must be validated by the host.
993 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
997 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
998 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
999 flags |= EFX_PKT_VLAN_TAGGED;
1003 case ESE_DZ_L3_CLASS_IP4:
1004 case ESE_DZ_L3_CLASS_IP4_FRAG:
1005 flags |= EFX_PKT_IPV4;
1006 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
1007 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
1009 flags |= EFX_CKSUM_IPV4;
1013 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
1014 * only 2 bits wide on Medford2. Check it is safe to use the
1015 * Medford2 field and values for all EF10 controllers.
1017 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
1018 ESF_DE_RX_L4_CLASS_LBN);
1019 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
1020 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
1021 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
1022 ESE_DE_L4_CLASS_UNKNOWN);
1024 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
1025 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
1026 flags |= EFX_PKT_TCP;
1027 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
1028 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
1029 flags |= EFX_PKT_UDP;
1031 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
1035 case ESE_DZ_L3_CLASS_IP6:
1036 case ESE_DZ_L3_CLASS_IP6_FRAG:
1037 flags |= EFX_PKT_IPV6;
1040 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
1041 * only 2 bits wide on Medford2. Check it is safe to use the
1042 * Medford2 field and values for all EF10 controllers.
1044 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
1045 ESF_DE_RX_L4_CLASS_LBN);
1046 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
1047 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
1048 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
1049 ESE_DE_L4_CLASS_UNKNOWN);
1051 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
1052 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
1053 flags |= EFX_PKT_TCP;
1054 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
1055 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
1056 flags |= EFX_PKT_UDP;
1058 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
1063 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
1067 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
1068 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
1069 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
1071 flags |= EFX_CKSUM_TCPUDP;
1076 /* If we're not discarding the packet then it is ok */
1077 if (~flags & EFX_DISCARD)
1078 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
1080 EFSYS_ASSERT(eecp->eec_rx != NULL);
1081 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
1083 return (should_abort);
1086 static __checkReturn boolean_t
1088 __in efx_evq_t *eep,
1089 __in efx_qword_t *eqp,
1090 __in const efx_ev_callbacks_t *eecp,
1093 efx_nic_t *enp = eep->ee_enp;
1096 boolean_t should_abort;
1098 EFX_EV_QSTAT_INCR(eep, EV_TX);
1100 /* Discard events after RXQ/TXQ errors, or hardware not available */
1101 if (enp->en_reset_flags &
1102 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
1105 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
1106 /* Drop this event */
1110 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
1111 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
1112 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
1114 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
1116 EFSYS_ASSERT(eecp->eec_tx != NULL);
1117 should_abort = eecp->eec_tx(arg, label, id);
1119 return (should_abort);
1122 static __checkReturn boolean_t
1124 __in efx_evq_t *eep,
1125 __in efx_qword_t *eqp,
1126 __in const efx_ev_callbacks_t *eecp,
1130 boolean_t should_abort;
1132 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
1133 should_abort = B_FALSE;
1135 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
1137 case ESE_DZ_DRV_TIMER_EV: {
1140 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
1142 EFSYS_ASSERT(eecp->eec_timer != NULL);
1143 should_abort = eecp->eec_timer(arg, id);
1147 case ESE_DZ_DRV_WAKE_UP_EV: {
1150 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
1152 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1153 should_abort = eecp->eec_wake_up(arg, id);
1157 case ESE_DZ_DRV_START_UP_EV:
1158 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1159 should_abort = eecp->eec_initialized(arg);
1163 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1164 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1165 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1169 return (should_abort);
1172 static __checkReturn boolean_t
1174 __in efx_evq_t *eep,
1175 __in efx_qword_t *eqp,
1176 __in const efx_ev_callbacks_t *eecp,
1180 boolean_t should_abort;
1182 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1183 should_abort = B_FALSE;
1185 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
1186 if (data >= ((uint32_t)1 << 16)) {
1187 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1188 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1189 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1194 EFSYS_ASSERT(eecp->eec_software != NULL);
1195 should_abort = eecp->eec_software(arg, (uint16_t)data);
1197 return (should_abort);
1200 static __checkReturn boolean_t
1202 __in efx_evq_t *eep,
1203 __in efx_qword_t *eqp,
1204 __in const efx_ev_callbacks_t *eecp,
1207 efx_nic_t *enp = eep->ee_enp;
1209 boolean_t should_abort = B_FALSE;
1211 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1213 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1215 case MCDI_EVENT_CODE_BADSSERT:
1216 efx_mcdi_ev_death(enp, EINTR);
1219 case MCDI_EVENT_CODE_CMDDONE:
1220 efx_mcdi_ev_cpl(enp,
1221 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1222 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1223 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1226 #if EFSYS_OPT_MCDI_PROXY_AUTH
1227 case MCDI_EVENT_CODE_PROXY_RESPONSE:
1229 * This event notifies a function that an authorization request
1230 * has been processed. If the request was authorized then the
1231 * function can now re-send the original MCDI request.
1232 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
1234 efx_mcdi_ev_proxy_response(enp,
1235 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
1236 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
1238 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
1240 case MCDI_EVENT_CODE_LINKCHANGE: {
1241 efx_link_mode_t link_mode;
1243 ef10_phy_link_ev(enp, eqp, &link_mode);
1244 should_abort = eecp->eec_link_change(arg, link_mode);
1248 case MCDI_EVENT_CODE_SENSOREVT: {
1249 #if EFSYS_OPT_MON_STATS
1251 efx_mon_stat_value_t value;
1254 /* Decode monitor stat for MCDI sensor (if supported) */
1255 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
1256 /* Report monitor stat change */
1257 should_abort = eecp->eec_monitor(arg, id, value);
1258 } else if (rc == ENOTSUP) {
1259 should_abort = eecp->eec_exception(arg,
1260 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1261 MCDI_EV_FIELD(eqp, DATA));
1263 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1269 case MCDI_EVENT_CODE_SCHEDERR:
1270 /* Informational only */
1273 case MCDI_EVENT_CODE_REBOOT:
1274 /* Falcon/Siena only (should not been seen with Huntington). */
1275 efx_mcdi_ev_death(enp, EIO);
1278 case MCDI_EVENT_CODE_MC_REBOOT:
1279 /* MC_REBOOT event is used for Huntington (EF10) and later. */
1280 efx_mcdi_ev_death(enp, EIO);
1283 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1284 #if EFSYS_OPT_MAC_STATS
1285 if (eecp->eec_mac_stats != NULL) {
1286 eecp->eec_mac_stats(arg,
1287 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1292 case MCDI_EVENT_CODE_FWALERT: {
1293 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1295 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1296 should_abort = eecp->eec_exception(arg,
1297 EFX_EXCEPTION_FWALERT_SRAM,
1298 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1300 should_abort = eecp->eec_exception(arg,
1301 EFX_EXCEPTION_UNKNOWN_FWALERT,
1302 MCDI_EV_FIELD(eqp, DATA));
1306 case MCDI_EVENT_CODE_TX_ERR: {
1308 * After a TXQ error is detected, firmware sends a TX_ERR event.
1309 * This may be followed by TX completions (which we discard),
1310 * and then finally by a TX_FLUSH event. Firmware destroys the
1311 * TXQ automatically after sending the TX_FLUSH event.
1313 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1315 EFSYS_PROBE2(tx_descq_err,
1316 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1317 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1319 /* Inform the driver that a reset is required. */
1320 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1321 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1325 case MCDI_EVENT_CODE_TX_FLUSH: {
1326 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1329 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1330 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1331 * We want to wait for all completions, so ignore the events
1332 * with TX_FLUSH_TO_DRIVER.
1334 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1335 should_abort = B_FALSE;
1339 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1341 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1343 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1344 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1348 case MCDI_EVENT_CODE_RX_ERR: {
1350 * After an RXQ error is detected, firmware sends an RX_ERR
1351 * event. This may be followed by RX events (which we discard),
1352 * and then finally by an RX_FLUSH event. Firmware destroys the
1353 * RXQ automatically after sending the RX_FLUSH event.
1355 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1357 EFSYS_PROBE2(rx_descq_err,
1358 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1359 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1361 /* Inform the driver that a reset is required. */
1362 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1363 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1367 case MCDI_EVENT_CODE_RX_FLUSH: {
1368 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1371 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1372 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1373 * We want to wait for all completions, so ignore the events
1374 * with RX_FLUSH_TO_DRIVER.
1376 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1377 should_abort = B_FALSE;
1381 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1383 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1385 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1386 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1391 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1392 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1393 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1397 return (should_abort);
1401 ef10_ev_rxlabel_init(
1402 __in efx_evq_t *eep,
1403 __in efx_rxq_t *erp,
1404 __in unsigned int label,
1405 __in efx_rxq_type_t type)
1407 efx_evq_rxq_state_t *eersp;
1408 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1409 boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
1410 boolean_t es_super_buffer = (type == EFX_RXQ_TYPE_ES_SUPER_BUFFER);
1413 _NOTE(ARGUNUSED(type))
1414 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1415 eersp = &eep->ee_rxq_state[label];
1417 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1419 #if EFSYS_OPT_RX_PACKED_STREAM
1421 * For packed stream modes, the very first event will
1422 * have a new buffer flag set, so it will be incremented,
1423 * yielding the correct pointer. That results in a simpler
1424 * code than trying to detect start-of-the-world condition
1425 * in the event handler.
1427 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1429 eersp->eers_rx_read_ptr = 0;
1431 eersp->eers_rx_mask = erp->er_mask;
1432 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1433 eersp->eers_rx_stream_npackets = 0;
1434 eersp->eers_rx_packed_stream = packed_stream || es_super_buffer;
1436 #if EFSYS_OPT_RX_PACKED_STREAM
1437 if (packed_stream) {
1438 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1439 EFX_DIV_ROUND_UP(EFX_RX_PACKED_STREAM_MEM_PER_CREDIT,
1440 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1441 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1443 * A single credit is allocated to the queue when it is started.
1444 * It is immediately spent by the first packet which has NEW
1445 * BUFFER flag set, though, but still we shall take into
1446 * account, as to not wrap around the maximum number of credits
1449 eersp->eers_rx_packed_stream_credits--;
1450 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1451 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1457 ef10_ev_rxlabel_fini(
1458 __in efx_evq_t *eep,
1459 __in unsigned int label)
1461 efx_evq_rxq_state_t *eersp;
1463 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1464 eersp = &eep->ee_rxq_state[label];
1466 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1468 eersp->eers_rx_read_ptr = 0;
1469 eersp->eers_rx_mask = 0;
1470 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1471 eersp->eers_rx_stream_npackets = 0;
1472 eersp->eers_rx_packed_stream = B_FALSE;
1474 #if EFSYS_OPT_RX_PACKED_STREAM
1475 eersp->eers_rx_packed_stream_credits = 0;
1479 #endif /* EFX_OPTS_EF10() */