1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
9 #if EFSYS_OPT_MON_STATS
16 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
18 (_eep)->ee_stat[_stat]++; \
19 _NOTE(CONSTANTCONDITION) \
22 #define EFX_EV_QSTAT_INCR(_eep, _stat)
26 * Non-interrupting event queue requires interrrupting event queue to
27 * refer to for wake-up events even if wake ups are never used.
28 * It could be even non-allocated event queue.
30 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
32 static __checkReturn boolean_t
35 __in efx_qword_t *eqp,
36 __in const efx_ev_callbacks_t *eecp,
39 static __checkReturn boolean_t
42 __in efx_qword_t *eqp,
43 __in const efx_ev_callbacks_t *eecp,
46 static __checkReturn boolean_t
49 __in efx_qword_t *eqp,
50 __in const efx_ev_callbacks_t *eecp,
53 static __checkReturn boolean_t
56 __in efx_qword_t *eqp,
57 __in const efx_ev_callbacks_t *eecp,
60 static __checkReturn boolean_t
63 __in efx_qword_t *eqp,
64 __in const efx_ev_callbacks_t *eecp,
68 static __checkReturn efx_rc_t
71 __in uint32_t instance,
73 __in uint32_t timer_ns)
76 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_EVQ_TMR_IN_LEN,
77 MC_CMD_SET_EVQ_TMR_OUT_LEN);
80 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
81 req.emr_in_buf = payload;
82 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
83 req.emr_out_buf = payload;
84 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
86 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
87 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
88 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
89 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
91 efx_mcdi_execute(enp, &req);
93 if (req.emr_rc != 0) {
98 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
108 EFSYS_PROBE1(fail1, efx_rc_t, rc);
113 static __checkReturn efx_rc_t
116 __in unsigned int instance,
117 __in efsys_mem_t *esmp,
122 __in boolean_t low_latency)
125 EFX_MCDI_DECLARE_BUF(payload,
126 MC_CMD_INIT_EVQ_IN_LEN(EF10_EVQ_MAXNBUFS),
127 MC_CMD_INIT_EVQ_OUT_LEN);
128 efx_qword_t *dma_addr;
132 boolean_t interrupting;
136 npages = efx_evq_nbufs(enp, nevs);
137 if (npages > EF10_EVQ_MAXNBUFS) {
142 req.emr_cmd = MC_CMD_INIT_EVQ;
143 req.emr_in_buf = payload;
144 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
145 req.emr_out_buf = payload;
146 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
148 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
149 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
150 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
152 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
153 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
156 * On Huntington RX and TX event batching can only be requested together
157 * (even if the datapath firmware doesn't actually support RX
158 * batching). If event cut through is enabled no RX batching will occur.
160 * So always enable RX and TX event batching, and enable event cut
161 * through if we want low latency operation.
163 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
164 case EFX_EVQ_FLAGS_TYPE_AUTO:
165 ev_cut_through = low_latency ? 1 : 0;
167 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
170 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
177 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
178 INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting,
179 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
180 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
181 INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through,
182 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
183 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
185 /* If the value is zero then disable the timer */
187 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
188 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
189 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
190 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
194 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
197 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
198 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
199 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks);
200 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks);
203 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
204 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
205 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
207 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
208 addr = EFSYS_MEM_ADDR(esmp);
210 for (i = 0; i < npages; i++) {
211 EFX_POPULATE_QWORD_2(*dma_addr,
212 EFX_DWORD_1, (uint32_t)(addr >> 32),
213 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
216 addr += EFX_BUF_SIZE;
219 efx_mcdi_execute(enp, &req);
221 if (req.emr_rc != 0) {
226 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
231 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
244 EFSYS_PROBE1(fail1, efx_rc_t, rc);
250 static __checkReturn efx_rc_t
251 efx_mcdi_init_evq_v2(
253 __in unsigned int instance,
254 __in efsys_mem_t *esmp,
261 EFX_MCDI_DECLARE_BUF(payload,
262 MC_CMD_INIT_EVQ_V2_IN_LEN(EF10_EVQ_MAXNBUFS),
263 MC_CMD_INIT_EVQ_V2_OUT_LEN);
264 boolean_t interrupting;
265 unsigned int evq_type;
266 efx_qword_t *dma_addr;
272 npages = efx_evq_nbufs(enp, nevs);
273 if (npages > EF10_EVQ_MAXNBUFS) {
278 req.emr_cmd = MC_CMD_INIT_EVQ;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;
284 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);
285 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);
286 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);
288 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
289 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
291 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
292 case EFX_EVQ_FLAGS_TYPE_AUTO:
293 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;
295 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
296 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;
298 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
299 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;
305 MCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,
306 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,
307 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,
308 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,
309 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);
311 /* If the value is zero then disable the timer */
313 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
314 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);
315 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);
316 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);
320 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
323 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
324 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);
325 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);
326 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);
329 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,
330 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);
331 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);
333 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);
334 addr = EFSYS_MEM_ADDR(esmp);
336 for (i = 0; i < npages; i++) {
337 EFX_POPULATE_QWORD_2(*dma_addr,
338 EFX_DWORD_1, (uint32_t)(addr >> 32),
339 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
342 addr += EFX_BUF_SIZE;
345 efx_mcdi_execute(enp, &req);
347 if (req.emr_rc != 0) {
352 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {
357 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
359 EFSYS_PROBE1(mcdi_evq_flags, uint32_t,
360 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));
373 EFSYS_PROBE1(fail1, efx_rc_t, rc);
378 static __checkReturn efx_rc_t
381 __in uint32_t instance)
384 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_EVQ_IN_LEN,
385 MC_CMD_FINI_EVQ_OUT_LEN);
388 req.emr_cmd = MC_CMD_FINI_EVQ;
389 req.emr_in_buf = payload;
390 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
391 req.emr_out_buf = payload;
392 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
394 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
396 efx_mcdi_execute_quiet(enp, &req);
398 if (req.emr_rc != 0) {
407 * EALREADY is not an error, but indicates that the MC has rebooted and
408 * that the EVQ has already been destroyed.
411 EFSYS_PROBE1(fail1, efx_rc_t, rc);
418 __checkReturn efx_rc_t
422 _NOTE(ARGUNUSED(enp))
430 _NOTE(ARGUNUSED(enp))
433 __checkReturn efx_rc_t
436 __in unsigned int index,
437 __in efsys_mem_t *esmp,
444 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
448 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
450 if (index >= encp->enc_evq_limit) {
455 if (us > encp->enc_evq_timer_max_us) {
461 * NO_CONT_EV mode is only requested from the firmware when creating
462 * receive queues, but here it needs to be specified at event queue
463 * creation, as the event handler needs to know which format is in use.
465 * If EFX_EVQ_FLAGS_NO_CONT_EV is specified, all receive queues for this
466 * event queue will be created in NO_CONT_EV mode.
468 * See SF-109306-TC 5.11 "Events for RXQs in NO_CONT_EV mode".
470 if (flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
471 if (enp->en_nic_cfg.enc_no_cont_ev_mode_supported == B_FALSE) {
477 /* Set up the handler table */
478 eep->ee_rx = ef10_ev_rx;
479 eep->ee_tx = ef10_ev_tx;
480 eep->ee_driver = ef10_ev_driver;
481 eep->ee_drv_gen = ef10_ev_drv_gen;
482 eep->ee_mcdi = ef10_ev_mcdi;
484 /* Set up the event queue */
485 /* INIT_EVQ expects function-relative vector number */
486 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
487 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
489 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
491 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
492 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
494 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
498 * Interrupts may be raised for events immediately after the queue is
499 * created. See bug58606.
502 if (encp->enc_init_evq_v2_supported) {
504 * On Medford the low latency license is required to enable RX
505 * and event cut through and to disable RX batching. If event
506 * queue type in flags is auto, we let the firmware decide the
507 * settings to use. If the adapter has a low latency license,
508 * it will choose the best settings for low latency, otherwise
509 * it will choose the best settings for throughput.
511 rc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,
517 * On Huntington we need to specify the settings to use.
518 * If event queue type in flags is auto, we favour throughput
519 * if the adapter is running virtualization supporting firmware
520 * (i.e. the full featured firmware variant)
521 * and latency otherwise. The Ethernet Virtual Bridging
522 * capability is used to make this decision. (Note though that
523 * the low latency firmware variant is also best for
524 * throughput and corresponding type should be specified
527 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
528 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
545 EFSYS_PROBE1(fail1, efx_rc_t, rc);
554 efx_nic_t *enp = eep->ee_enp;
556 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
557 enp->en_family == EFX_FAMILY_MEDFORD ||
558 enp->en_family == EFX_FAMILY_MEDFORD2);
560 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
563 __checkReturn efx_rc_t
566 __in unsigned int count)
568 efx_nic_t *enp = eep->ee_enp;
572 rptr = count & eep->ee_mask;
574 if (enp->en_nic_cfg.enc_bug35388_workaround) {
575 EFX_STATIC_ASSERT(EF10_EVQ_MINNEVS >
576 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
577 EFX_STATIC_ASSERT(EF10_EVQ_MAXNEVS <
578 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
580 EFX_POPULATE_DWORD_2(dword,
581 ERF_DD_EVQ_IND_RPTR_FLAGS,
582 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
584 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
585 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
588 EFX_POPULATE_DWORD_2(dword,
589 ERF_DD_EVQ_IND_RPTR_FLAGS,
590 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
592 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
593 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
596 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
597 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
604 static __checkReturn efx_rc_t
605 efx_mcdi_driver_event(
608 __in efx_qword_t data)
611 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRIVER_EVENT_IN_LEN,
612 MC_CMD_DRIVER_EVENT_OUT_LEN);
615 req.emr_cmd = MC_CMD_DRIVER_EVENT;
616 req.emr_in_buf = payload;
617 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
618 req.emr_out_buf = payload;
619 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
621 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
623 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
624 EFX_QWORD_FIELD(data, EFX_DWORD_0));
625 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
626 EFX_QWORD_FIELD(data, EFX_DWORD_1));
628 efx_mcdi_execute(enp, &req);
630 if (req.emr_rc != 0) {
638 EFSYS_PROBE1(fail1, efx_rc_t, rc);
648 efx_nic_t *enp = eep->ee_enp;
651 EFX_POPULATE_QWORD_3(event,
652 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
653 ESF_DZ_DRV_SUB_CODE, 0,
654 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
656 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
659 __checkReturn efx_rc_t
662 __in unsigned int us)
664 efx_nic_t *enp = eep->ee_enp;
665 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
670 /* Check that hardware and MCDI use the same timer MODE values */
671 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
672 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
673 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
674 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
675 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
676 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
677 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
678 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
680 if (us > encp->enc_evq_timer_max_us) {
685 /* If the value is zero then disable the timer */
687 mode = FFE_CZ_TIMER_MODE_DIS;
689 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
692 if (encp->enc_bug61265_workaround) {
693 uint32_t ns = us * 1000;
695 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
701 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
704 if (encp->enc_bug35388_workaround) {
705 EFX_POPULATE_DWORD_3(dword,
706 ERF_DD_EVQ_IND_TIMER_FLAGS,
707 EFE_DD_EVQ_IND_TIMER_FLAGS,
708 ERF_DD_EVQ_IND_TIMER_MODE, mode,
709 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
710 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
711 eep->ee_index, &dword, 0);
714 * NOTE: The TMR_REL field introduced in Medford2 is
715 * ignored on earlier EF10 controllers. See bug66418
716 * comment 9 for details.
718 EFX_POPULATE_DWORD_3(dword,
719 ERF_DZ_TC_TIMER_MODE, mode,
720 ERF_DZ_TC_TIMER_VAL, ticks,
721 ERF_FZ_TC_TMR_REL_VAL, ticks);
722 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
723 eep->ee_index, &dword, 0);
734 EFSYS_PROBE1(fail1, efx_rc_t, rc);
742 ef10_ev_qstats_update(
744 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
748 for (id = 0; id < EV_NQSTATS; id++) {
749 efsys_stat_t *essp = &stat[id];
751 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
752 eep->ee_stat[id] = 0;
755 #endif /* EFSYS_OPT_QSTATS */
757 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
759 static __checkReturn boolean_t
760 ef10_ev_rx_packed_stream(
762 __in efx_qword_t *eqp,
763 __in const efx_ev_callbacks_t *eecp,
767 uint32_t pkt_count_lbits;
769 boolean_t should_abort;
770 efx_evq_rxq_state_t *eersp;
771 unsigned int pkt_count;
772 unsigned int current_id;
773 boolean_t new_buffer;
775 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
776 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
777 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
781 eersp = &eep->ee_rxq_state[label];
784 * RX_DSC_PTR_LBITS has least significant bits of the global
785 * (not per-buffer) packet counter. It is guaranteed that
786 * maximum number of completed packets fits in lbits-mask.
787 * So, modulo lbits-mask arithmetic should be used to calculate
788 * packet counter increment.
790 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
791 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
792 eersp->eers_rx_stream_npackets += pkt_count;
795 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
796 #if EFSYS_OPT_RX_PACKED_STREAM
798 * If both packed stream and equal stride super-buffer
799 * modes are compiled in, in theory credits should be
800 * be maintained for packed stream only, but right now
801 * these modes are not distinguished in the event queue
802 * Rx queue state and it is OK to increment the counter
803 * regardless (it might be event cheaper than branching
804 * since neighbour structure member are updated as well).
806 eersp->eers_rx_packed_stream_credits++;
808 eersp->eers_rx_read_ptr++;
810 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
812 /* Check for errors that invalidate checksum and L3/L4 fields */
813 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
814 /* RX frame truncated */
815 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
816 flags |= EFX_DISCARD;
819 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
820 /* Bad Ethernet frame CRC */
821 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
822 flags |= EFX_DISCARD;
826 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
827 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
828 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
832 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
833 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
835 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
836 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
839 /* If we're not discarding the packet then it is ok */
840 if (~flags & EFX_DISCARD)
841 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
843 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
844 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
847 return (should_abort);
850 #endif /* EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER */
852 static __checkReturn boolean_t
855 __in efx_qword_t *eqp,
856 __in const efx_ev_callbacks_t *eecp,
859 efx_nic_t *enp = eep->ee_enp;
863 uint32_t eth_tag_class;
866 uint32_t next_read_lbits;
869 boolean_t should_abort;
870 efx_evq_rxq_state_t *eersp;
871 unsigned int desc_count;
872 unsigned int last_used_id;
874 EFX_EV_QSTAT_INCR(eep, EV_RX);
876 /* Discard events after RXQ/TXQ errors, or hardware not available */
877 if (enp->en_reset_flags &
878 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
881 /* Basic packet information */
882 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
883 eersp = &eep->ee_rxq_state[label];
885 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
887 * Packed stream events are very different,
888 * so handle them separately
890 if (eersp->eers_rx_packed_stream)
891 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
894 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
895 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
896 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
897 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
898 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
899 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
902 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
903 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
904 * and values for all EF10 controllers.
906 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
907 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
908 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
909 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
911 l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
913 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
914 /* Drop this event */
921 * This may be part of a scattered frame, or it may be a
922 * truncated frame if scatter is disabled on this RXQ.
923 * Overlength frames can be received if e.g. a VF is configured
924 * for 1500 MTU but connected to a port set to 9000 MTU
926 * FIXME: There is not yet any driver that supports scatter on
927 * Huntington. Scatter support is required for OSX.
929 flags |= EFX_PKT_CONT;
932 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
933 flags |= EFX_PKT_UNICAST;
936 * Increment the count of descriptors read.
938 * In NO_CONT_EV mode, RX_DSC_PTR_LBITS is actually a packet count, but
939 * when scatter is disabled, there is only one descriptor per packet and
940 * so it can be treated the same.
942 * TODO: Support scatter in NO_CONT_EV mode.
944 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
945 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
946 eersp->eers_rx_read_ptr += desc_count;
948 /* Calculate the index of the last descriptor consumed */
949 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
951 if (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
953 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
955 /* Always read the length from the prefix in NO_CONT_EV mode. */
956 flags |= EFX_PKT_PREFIX_LEN;
959 * Check for an aborted scatter, signalled by the ABORT bit in
960 * NO_CONT_EV mode. The ABORT bit was not used before NO_CONT_EV
961 * mode was added as it was broken in Huntington silicon.
963 if (EFX_QWORD_FIELD(*eqp, ESF_EZ_RX_ABORT) != 0) {
964 flags |= EFX_DISCARD;
967 } else if (desc_count > 1) {
969 * FIXME: add error checking to make sure this a batched event.
970 * This could also be an aborted scatter, see Bug36629.
972 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
973 flags |= EFX_PKT_PREFIX_LEN;
976 /* Check for errors that invalidate checksum and L3/L4 fields */
977 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
978 /* RX frame truncated */
979 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
980 flags |= EFX_DISCARD;
983 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
984 /* Bad Ethernet frame CRC */
985 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
986 flags |= EFX_DISCARD;
989 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
991 * Hardware parse failed, due to malformed headers
992 * or headers that are too long for the parser.
993 * Headers and checksums must be validated by the host.
995 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
999 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
1000 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
1001 flags |= EFX_PKT_VLAN_TAGGED;
1005 case ESE_DZ_L3_CLASS_IP4:
1006 case ESE_DZ_L3_CLASS_IP4_FRAG:
1007 flags |= EFX_PKT_IPV4;
1008 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
1009 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
1011 flags |= EFX_CKSUM_IPV4;
1015 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
1016 * only 2 bits wide on Medford2. Check it is safe to use the
1017 * Medford2 field and values for all EF10 controllers.
1019 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
1020 ESF_DE_RX_L4_CLASS_LBN);
1021 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
1022 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
1023 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
1024 ESE_DE_L4_CLASS_UNKNOWN);
1026 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
1027 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
1028 flags |= EFX_PKT_TCP;
1029 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
1030 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
1031 flags |= EFX_PKT_UDP;
1033 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
1037 case ESE_DZ_L3_CLASS_IP6:
1038 case ESE_DZ_L3_CLASS_IP6_FRAG:
1039 flags |= EFX_PKT_IPV6;
1042 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
1043 * only 2 bits wide on Medford2. Check it is safe to use the
1044 * Medford2 field and values for all EF10 controllers.
1046 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
1047 ESF_DE_RX_L4_CLASS_LBN);
1048 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
1049 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
1050 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
1051 ESE_DE_L4_CLASS_UNKNOWN);
1053 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
1054 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
1055 flags |= EFX_PKT_TCP;
1056 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
1057 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
1058 flags |= EFX_PKT_UDP;
1060 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
1065 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
1069 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
1070 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
1071 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
1073 flags |= EFX_CKSUM_TCPUDP;
1078 /* If we're not discarding the packet then it is ok */
1079 if (~flags & EFX_DISCARD)
1080 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
1082 EFSYS_ASSERT(eecp->eec_rx != NULL);
1083 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
1085 return (should_abort);
1088 static __checkReturn boolean_t
1090 __in efx_evq_t *eep,
1091 __in efx_qword_t *eqp,
1092 __in const efx_ev_callbacks_t *eecp,
1095 efx_nic_t *enp = eep->ee_enp;
1098 boolean_t should_abort;
1100 EFX_EV_QSTAT_INCR(eep, EV_TX);
1102 /* Discard events after RXQ/TXQ errors, or hardware not available */
1103 if (enp->en_reset_flags &
1104 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
1107 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
1108 /* Drop this event */
1112 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
1113 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
1114 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
1116 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
1118 EFSYS_ASSERT(eecp->eec_tx != NULL);
1119 should_abort = eecp->eec_tx(arg, label, id);
1121 return (should_abort);
1124 static __checkReturn boolean_t
1126 __in efx_evq_t *eep,
1127 __in efx_qword_t *eqp,
1128 __in const efx_ev_callbacks_t *eecp,
1132 boolean_t should_abort;
1134 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
1135 should_abort = B_FALSE;
1137 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
1139 case ESE_DZ_DRV_TIMER_EV: {
1142 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
1144 EFSYS_ASSERT(eecp->eec_timer != NULL);
1145 should_abort = eecp->eec_timer(arg, id);
1149 case ESE_DZ_DRV_WAKE_UP_EV: {
1152 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
1154 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1155 should_abort = eecp->eec_wake_up(arg, id);
1159 case ESE_DZ_DRV_START_UP_EV:
1160 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1161 should_abort = eecp->eec_initialized(arg);
1165 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1166 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1167 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1171 return (should_abort);
1174 static __checkReturn boolean_t
1176 __in efx_evq_t *eep,
1177 __in efx_qword_t *eqp,
1178 __in const efx_ev_callbacks_t *eecp,
1182 boolean_t should_abort;
1184 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1185 should_abort = B_FALSE;
1187 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
1188 if (data >= ((uint32_t)1 << 16)) {
1189 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1190 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1191 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1196 EFSYS_ASSERT(eecp->eec_software != NULL);
1197 should_abort = eecp->eec_software(arg, (uint16_t)data);
1199 return (should_abort);
1202 static __checkReturn boolean_t
1204 __in efx_evq_t *eep,
1205 __in efx_qword_t *eqp,
1206 __in const efx_ev_callbacks_t *eecp,
1209 efx_nic_t *enp = eep->ee_enp;
1211 boolean_t should_abort = B_FALSE;
1213 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1215 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1217 case MCDI_EVENT_CODE_BADSSERT:
1218 efx_mcdi_ev_death(enp, EINTR);
1221 case MCDI_EVENT_CODE_CMDDONE:
1222 efx_mcdi_ev_cpl(enp,
1223 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1224 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1225 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1228 #if EFSYS_OPT_MCDI_PROXY_AUTH
1229 case MCDI_EVENT_CODE_PROXY_RESPONSE:
1231 * This event notifies a function that an authorization request
1232 * has been processed. If the request was authorized then the
1233 * function can now re-send the original MCDI request.
1234 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
1236 efx_mcdi_ev_proxy_response(enp,
1237 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
1238 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
1240 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
1242 case MCDI_EVENT_CODE_LINKCHANGE: {
1243 efx_link_mode_t link_mode;
1245 ef10_phy_link_ev(enp, eqp, &link_mode);
1246 should_abort = eecp->eec_link_change(arg, link_mode);
1250 case MCDI_EVENT_CODE_SENSOREVT: {
1251 #if EFSYS_OPT_MON_STATS
1253 efx_mon_stat_value_t value;
1256 /* Decode monitor stat for MCDI sensor (if supported) */
1257 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
1258 /* Report monitor stat change */
1259 should_abort = eecp->eec_monitor(arg, id, value);
1260 } else if (rc == ENOTSUP) {
1261 should_abort = eecp->eec_exception(arg,
1262 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1263 MCDI_EV_FIELD(eqp, DATA));
1265 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1271 case MCDI_EVENT_CODE_SCHEDERR:
1272 /* Informational only */
1275 case MCDI_EVENT_CODE_REBOOT:
1276 /* Falcon/Siena only (should not been seen with Huntington). */
1277 efx_mcdi_ev_death(enp, EIO);
1280 case MCDI_EVENT_CODE_MC_REBOOT:
1281 /* MC_REBOOT event is used for Huntington (EF10) and later. */
1282 efx_mcdi_ev_death(enp, EIO);
1285 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1286 #if EFSYS_OPT_MAC_STATS
1287 if (eecp->eec_mac_stats != NULL) {
1288 eecp->eec_mac_stats(arg,
1289 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1294 case MCDI_EVENT_CODE_FWALERT: {
1295 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1297 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1298 should_abort = eecp->eec_exception(arg,
1299 EFX_EXCEPTION_FWALERT_SRAM,
1300 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1302 should_abort = eecp->eec_exception(arg,
1303 EFX_EXCEPTION_UNKNOWN_FWALERT,
1304 MCDI_EV_FIELD(eqp, DATA));
1308 case MCDI_EVENT_CODE_TX_ERR: {
1310 * After a TXQ error is detected, firmware sends a TX_ERR event.
1311 * This may be followed by TX completions (which we discard),
1312 * and then finally by a TX_FLUSH event. Firmware destroys the
1313 * TXQ automatically after sending the TX_FLUSH event.
1315 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1317 EFSYS_PROBE2(tx_descq_err,
1318 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1319 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1321 /* Inform the driver that a reset is required. */
1322 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1323 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1327 case MCDI_EVENT_CODE_TX_FLUSH: {
1328 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1331 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1332 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1333 * We want to wait for all completions, so ignore the events
1334 * with TX_FLUSH_TO_DRIVER.
1336 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1337 should_abort = B_FALSE;
1341 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1343 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1345 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1346 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1350 case MCDI_EVENT_CODE_RX_ERR: {
1352 * After an RXQ error is detected, firmware sends an RX_ERR
1353 * event. This may be followed by RX events (which we discard),
1354 * and then finally by an RX_FLUSH event. Firmware destroys the
1355 * RXQ automatically after sending the RX_FLUSH event.
1357 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1359 EFSYS_PROBE2(rx_descq_err,
1360 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1361 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1363 /* Inform the driver that a reset is required. */
1364 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1365 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1369 case MCDI_EVENT_CODE_RX_FLUSH: {
1370 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1373 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1374 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1375 * We want to wait for all completions, so ignore the events
1376 * with RX_FLUSH_TO_DRIVER.
1378 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1379 should_abort = B_FALSE;
1383 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1385 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1387 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1388 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1393 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1394 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1395 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1399 return (should_abort);
1403 ef10_ev_rxlabel_init(
1404 __in efx_evq_t *eep,
1405 __in efx_rxq_t *erp,
1406 __in unsigned int label,
1407 __in efx_rxq_type_t type)
1409 efx_evq_rxq_state_t *eersp;
1410 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1411 boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
1412 boolean_t es_super_buffer = (type == EFX_RXQ_TYPE_ES_SUPER_BUFFER);
1415 _NOTE(ARGUNUSED(type))
1416 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1417 eersp = &eep->ee_rxq_state[label];
1419 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1421 #if EFSYS_OPT_RX_PACKED_STREAM
1423 * For packed stream modes, the very first event will
1424 * have a new buffer flag set, so it will be incremented,
1425 * yielding the correct pointer. That results in a simpler
1426 * code than trying to detect start-of-the-world condition
1427 * in the event handler.
1429 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1431 eersp->eers_rx_read_ptr = 0;
1433 eersp->eers_rx_mask = erp->er_mask;
1434 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1435 eersp->eers_rx_stream_npackets = 0;
1436 eersp->eers_rx_packed_stream = packed_stream || es_super_buffer;
1438 #if EFSYS_OPT_RX_PACKED_STREAM
1439 if (packed_stream) {
1440 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1441 EFX_DIV_ROUND_UP(EFX_RX_PACKED_STREAM_MEM_PER_CREDIT,
1442 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1443 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1445 * A single credit is allocated to the queue when it is started.
1446 * It is immediately spent by the first packet which has NEW
1447 * BUFFER flag set, though, but still we shall take into
1448 * account, as to not wrap around the maximum number of credits
1451 eersp->eers_rx_packed_stream_credits--;
1452 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1453 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1459 ef10_ev_rxlabel_fini(
1460 __in efx_evq_t *eep,
1461 __in unsigned int label)
1463 efx_evq_rxq_state_t *eersp;
1465 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1466 eersp = &eep->ee_rxq_state[label];
1468 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1470 eersp->eers_rx_read_ptr = 0;
1471 eersp->eers_rx_mask = 0;
1472 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1473 eersp->eers_rx_stream_npackets = 0;
1474 eersp->eers_rx_packed_stream = B_FALSE;
1476 #if EFSYS_OPT_RX_PACKED_STREAM
1477 eersp->eers_rx_packed_stream_credits = 0;
1481 #endif /* EFX_OPTS_EF10() */