1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #define EF10_TXQ_MINNDESCS 512
16 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
17 #define EF10_MAX_PIOBUF_NBUFS (16)
19 #if EFSYS_OPT_HUNTINGTON
20 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
21 # error "EF10_MAX_PIOBUF_NBUFS too small"
23 #endif /* EFSYS_OPT_HUNTINGTON */
25 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
26 # error "EF10_MAX_PIOBUF_NBUFS too small"
28 #endif /* EFSYS_OPT_MEDFORD */
29 #if EFSYS_OPT_MEDFORD2
30 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
31 # error "EF10_MAX_PIOBUF_NBUFS too small"
33 #endif /* EFSYS_OPT_MEDFORD2 */
38 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
39 * possibly be increased, or the write size reported by newer firmware used
42 #define EF10_NVRAM_CHUNK 0x80
45 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
46 * to an 8 descriptor boundary.
48 #define EF10_RX_WPTR_ALIGN 8
51 * Max byte offset into the packet the TCP header must start for the hardware
52 * to be able to parse the packet correctly.
54 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
56 /* Invalid RSS context handle */
57 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
62 __checkReturn efx_rc_t
70 __checkReturn efx_rc_t
73 __in unsigned int index,
74 __in efsys_mem_t *esmp,
85 __checkReturn efx_rc_t
88 __in unsigned int count);
95 __checkReturn efx_rc_t
98 __in unsigned int us);
102 ef10_ev_qstats_update(
104 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
105 #endif /* EFSYS_OPT_QSTATS */
108 ef10_ev_rxlabel_init(
111 __in unsigned int label,
112 __in efx_rxq_type_t type);
115 ef10_ev_rxlabel_fini(
117 __in unsigned int label);
121 __checkReturn efx_rc_t
124 __in efx_intr_type_t type,
125 __in efsys_mem_t *esmp);
129 __in efx_nic_t *enp);
133 __in efx_nic_t *enp);
136 ef10_intr_disable_unlocked(
137 __in efx_nic_t *enp);
139 __checkReturn efx_rc_t
142 __in unsigned int level);
145 ef10_intr_status_line(
147 __out boolean_t *fatalp,
148 __out uint32_t *qmaskp);
151 ef10_intr_status_message(
153 __in unsigned int message,
154 __out boolean_t *fatalp);
158 __in efx_nic_t *enp);
161 __in efx_nic_t *enp);
165 extern __checkReturn efx_rc_t
167 __in efx_nic_t *enp);
169 extern __checkReturn efx_rc_t
170 ef10_nic_set_drv_limits(
171 __inout efx_nic_t *enp,
172 __in efx_drv_limits_t *edlp);
174 extern __checkReturn efx_rc_t
175 ef10_nic_get_vi_pool(
177 __out uint32_t *vi_countp);
179 extern __checkReturn efx_rc_t
180 ef10_nic_get_bar_region(
182 __in efx_nic_region_t region,
183 __out uint32_t *offsetp,
184 __out size_t *sizep);
186 extern __checkReturn efx_rc_t
188 __in efx_nic_t *enp);
190 extern __checkReturn efx_rc_t
192 __in efx_nic_t *enp);
194 extern __checkReturn boolean_t
195 ef10_nic_hw_unavailable(
196 __in efx_nic_t *enp);
199 ef10_nic_set_hw_unavailable(
200 __in efx_nic_t *enp);
204 extern __checkReturn efx_rc_t
205 ef10_nic_register_test(
206 __in efx_nic_t *enp);
208 #endif /* EFSYS_OPT_DIAG */
212 __in efx_nic_t *enp);
216 __in efx_nic_t *enp);
221 extern __checkReturn efx_rc_t
224 __out efx_link_mode_t *link_modep);
226 extern __checkReturn efx_rc_t
229 __out boolean_t *mac_upp);
231 extern __checkReturn efx_rc_t
233 __in efx_nic_t *enp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
239 extern __checkReturn efx_rc_t
244 extern __checkReturn efx_rc_t
245 ef10_mac_reconfigure(
246 __in efx_nic_t *enp);
248 extern __checkReturn efx_rc_t
249 ef10_mac_multicast_list_set(
250 __in efx_nic_t *enp);
252 extern __checkReturn efx_rc_t
253 ef10_mac_filter_default_rxq_set(
256 __in boolean_t using_rss);
259 ef10_mac_filter_default_rxq_clear(
260 __in efx_nic_t *enp);
262 #if EFSYS_OPT_LOOPBACK
264 extern __checkReturn efx_rc_t
265 ef10_mac_loopback_set(
267 __in efx_link_mode_t link_mode,
268 __in efx_loopback_type_t loopback_type);
270 #endif /* EFSYS_OPT_LOOPBACK */
272 #if EFSYS_OPT_MAC_STATS
274 extern __checkReturn efx_rc_t
275 ef10_mac_stats_get_mask(
277 __inout_bcount(mask_size) uint32_t *maskp,
278 __in size_t mask_size);
280 extern __checkReturn efx_rc_t
281 ef10_mac_stats_update(
283 __in efsys_mem_t *esmp,
284 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
285 __inout_opt uint32_t *generationp);
287 #endif /* EFSYS_OPT_MAC_STATS */
294 extern __checkReturn efx_rc_t
297 __in const efx_mcdi_transport_t *mtp);
301 __in efx_nic_t *enp);
304 ef10_mcdi_send_request(
306 __in_bcount(hdr_len) void *hdrp,
308 __in_bcount(sdu_len) void *sdup,
309 __in size_t sdu_len);
311 extern __checkReturn boolean_t
312 ef10_mcdi_poll_response(
313 __in efx_nic_t *enp);
316 ef10_mcdi_read_response(
318 __out_bcount(length) void *bufferp,
323 ef10_mcdi_poll_reboot(
324 __in efx_nic_t *enp);
326 extern __checkReturn efx_rc_t
327 ef10_mcdi_feature_supported(
329 __in efx_mcdi_feature_id_t id,
330 __out boolean_t *supportedp);
333 ef10_mcdi_get_timeout(
335 __in efx_mcdi_req_t *emrp,
336 __out uint32_t *timeoutp);
338 #endif /* EFSYS_OPT_MCDI */
342 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
344 extern __checkReturn efx_rc_t
345 ef10_nvram_buf_read_tlv(
347 __in_bcount(max_seg_size) caddr_t seg_data,
348 __in size_t max_seg_size,
350 __deref_out_bcount_opt(*sizep) caddr_t *datap,
351 __out size_t *sizep);
353 extern __checkReturn efx_rc_t
354 ef10_nvram_buf_write_tlv(
355 __inout_bcount(partn_size) caddr_t partn_data,
356 __in size_t partn_size,
358 __in_bcount(tag_size) caddr_t tag_data,
359 __in size_t tag_size,
360 __out size_t *total_lengthp);
362 extern __checkReturn efx_rc_t
363 ef10_nvram_partn_read_tlv(
367 __deref_out_bcount_opt(*sizep) caddr_t *datap,
368 __out size_t *sizep);
370 extern __checkReturn efx_rc_t
371 ef10_nvram_partn_write_tlv(
375 __in_bcount(size) caddr_t data,
378 extern __checkReturn efx_rc_t
379 ef10_nvram_partn_write_segment_tlv(
383 __in_bcount(size) caddr_t data,
385 __in boolean_t all_segments);
387 extern __checkReturn efx_rc_t
388 ef10_nvram_partn_lock(
390 __in uint32_t partn);
392 extern __checkReturn efx_rc_t
393 ef10_nvram_partn_unlock(
396 __out_opt uint32_t *resultp);
398 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
404 extern __checkReturn efx_rc_t
406 __in efx_nic_t *enp);
408 #endif /* EFSYS_OPT_DIAG */
410 extern __checkReturn efx_rc_t
411 ef10_nvram_type_to_partn(
413 __in efx_nvram_type_t type,
414 __out uint32_t *partnp);
416 extern __checkReturn efx_rc_t
417 ef10_nvram_partn_size(
420 __out size_t *sizep);
422 extern __checkReturn efx_rc_t
423 ef10_nvram_partn_rw_start(
426 __out size_t *chunk_sizep);
428 extern __checkReturn efx_rc_t
429 ef10_nvram_partn_read_mode(
432 __in unsigned int offset,
433 __out_bcount(size) caddr_t data,
437 extern __checkReturn efx_rc_t
438 ef10_nvram_partn_read(
441 __in unsigned int offset,
442 __out_bcount(size) caddr_t data,
445 extern __checkReturn efx_rc_t
446 ef10_nvram_partn_read_backup(
449 __in unsigned int offset,
450 __out_bcount(size) caddr_t data,
453 extern __checkReturn efx_rc_t
454 ef10_nvram_partn_erase(
457 __in unsigned int offset,
460 extern __checkReturn efx_rc_t
461 ef10_nvram_partn_write(
464 __in unsigned int offset,
465 __in_bcount(size) caddr_t data,
468 extern __checkReturn efx_rc_t
469 ef10_nvram_partn_rw_finish(
472 __out_opt uint32_t *verify_resultp);
474 extern __checkReturn efx_rc_t
475 ef10_nvram_partn_get_version(
478 __out uint32_t *subtypep,
479 __out_ecount(4) uint16_t version[4]);
481 extern __checkReturn efx_rc_t
482 ef10_nvram_partn_set_version(
485 __in_ecount(4) uint16_t version[4]);
487 extern __checkReturn efx_rc_t
488 ef10_nvram_buffer_validate(
490 __in_bcount(buffer_size)
492 __in size_t buffer_size);
495 ef10_nvram_buffer_init(
496 __out_bcount(buffer_size)
498 __in size_t buffer_size);
500 extern __checkReturn efx_rc_t
501 ef10_nvram_buffer_create(
502 __in uint32_t partn_type,
503 __out_bcount(buffer_size)
505 __in size_t buffer_size);
507 extern __checkReturn efx_rc_t
508 ef10_nvram_buffer_find_item_start(
509 __in_bcount(buffer_size)
511 __in size_t buffer_size,
512 __out uint32_t *startp);
514 extern __checkReturn efx_rc_t
515 ef10_nvram_buffer_find_end(
516 __in_bcount(buffer_size)
518 __in size_t buffer_size,
519 __in uint32_t offset,
520 __out uint32_t *endp);
522 extern __checkReturn __success(return != B_FALSE) boolean_t
523 ef10_nvram_buffer_find_item(
524 __in_bcount(buffer_size)
526 __in size_t buffer_size,
527 __in uint32_t offset,
528 __out uint32_t *startp,
529 __out uint32_t *lengthp);
531 extern __checkReturn efx_rc_t
532 ef10_nvram_buffer_peek_item(
533 __in_bcount(buffer_size)
535 __in size_t buffer_size,
536 __in uint32_t offset,
537 __out uint32_t *tagp,
538 __out uint32_t *lengthp,
539 __out uint32_t *value_offsetp);
541 extern __checkReturn efx_rc_t
542 ef10_nvram_buffer_get_item(
543 __in_bcount(buffer_size)
545 __in size_t buffer_size,
546 __in uint32_t offset,
547 __in uint32_t length,
548 __out uint32_t *tagp,
549 __out_bcount_part(value_max_size, *lengthp)
551 __in size_t value_max_size,
552 __out uint32_t *lengthp);
554 extern __checkReturn efx_rc_t
555 ef10_nvram_buffer_insert_item(
556 __in_bcount(buffer_size)
558 __in size_t buffer_size,
559 __in uint32_t offset,
561 __in_bcount(length) caddr_t valuep,
562 __in uint32_t length,
563 __out uint32_t *lengthp);
565 extern __checkReturn efx_rc_t
566 ef10_nvram_buffer_modify_item(
567 __in_bcount(buffer_size)
569 __in size_t buffer_size,
570 __in uint32_t offset,
572 __in_bcount(length) caddr_t valuep,
573 __in uint32_t length,
574 __out uint32_t *lengthp);
576 extern __checkReturn efx_rc_t
577 ef10_nvram_buffer_delete_item(
578 __in_bcount(buffer_size)
580 __in size_t buffer_size,
581 __in uint32_t offset,
582 __in uint32_t length,
585 extern __checkReturn efx_rc_t
586 ef10_nvram_buffer_finish(
587 __in_bcount(buffer_size)
589 __in size_t buffer_size);
591 #endif /* EFSYS_OPT_NVRAM */
596 typedef struct ef10_link_state_s {
597 efx_phy_link_state_t epls;
598 #if EFSYS_OPT_LOOPBACK
599 efx_loopback_type_t els_loopback;
601 boolean_t els_mac_up;
607 __in efx_qword_t *eqp,
608 __out efx_link_mode_t *link_modep);
610 extern __checkReturn efx_rc_t
613 __out ef10_link_state_t *elsp);
615 extern __checkReturn efx_rc_t
620 extern __checkReturn efx_rc_t
621 ef10_phy_reconfigure(
622 __in efx_nic_t *enp);
624 extern __checkReturn efx_rc_t
626 __in efx_nic_t *enp);
628 extern __checkReturn efx_rc_t
631 __out uint32_t *ouip);
633 extern __checkReturn efx_rc_t
634 ef10_phy_link_state_get(
636 __out efx_phy_link_state_t *eplsp);
638 #if EFSYS_OPT_PHY_STATS
640 extern __checkReturn efx_rc_t
641 ef10_phy_stats_update(
643 __in efsys_mem_t *esmp,
644 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
646 #endif /* EFSYS_OPT_PHY_STATS */
650 extern __checkReturn efx_rc_t
651 ef10_bist_enable_offline(
652 __in efx_nic_t *enp);
654 extern __checkReturn efx_rc_t
657 __in efx_bist_type_t type);
659 extern __checkReturn efx_rc_t
662 __in efx_bist_type_t type,
663 __out efx_bist_result_t *resultp,
664 __out_opt __drv_when(count > 0, __notnull)
665 uint32_t *value_maskp,
666 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
667 unsigned long *valuesp,
673 __in efx_bist_type_t type);
675 #endif /* EFSYS_OPT_BIST */
679 extern __checkReturn efx_rc_t
681 __in efx_nic_t *enp);
685 __in efx_nic_t *enp);
687 extern __checkReturn efx_rc_t
690 __in unsigned int index,
691 __in unsigned int label,
692 __in efsys_mem_t *esmp,
698 __out unsigned int *addedp);
702 __in efx_txq_t *etp);
704 extern __checkReturn efx_rc_t
707 __in_ecount(ndescs) efx_buffer_t *ebp,
708 __in unsigned int ndescs,
709 __in unsigned int completed,
710 __inout unsigned int *addedp);
715 __in unsigned int added,
716 __in unsigned int pushed);
718 #if EFSYS_OPT_RX_PACKED_STREAM
720 ef10_rx_qpush_ps_credits(
721 __in efx_rxq_t *erp);
723 extern __checkReturn uint8_t *
724 ef10_rx_qps_packet_info(
726 __in uint8_t *buffer,
727 __in uint32_t buffer_length,
728 __in uint32_t current_offset,
729 __out uint16_t *lengthp,
730 __out uint32_t *next_offsetp,
731 __out uint32_t *timestamp);
734 extern __checkReturn efx_rc_t
737 __in unsigned int ns);
739 extern __checkReturn efx_rc_t
741 __in efx_txq_t *etp);
745 __in efx_txq_t *etp);
747 extern __checkReturn efx_rc_t
749 __in efx_txq_t *etp);
752 ef10_tx_qpio_disable(
753 __in efx_txq_t *etp);
755 extern __checkReturn efx_rc_t
758 __in_ecount(buf_length) uint8_t *buffer,
759 __in size_t buf_length,
760 __in size_t pio_buf_offset);
762 extern __checkReturn efx_rc_t
765 __in size_t pkt_length,
766 __in unsigned int completed,
767 __inout unsigned int *addedp);
769 extern __checkReturn efx_rc_t
772 __in_ecount(n) efx_desc_t *ed,
774 __in unsigned int completed,
775 __inout unsigned int *addedp);
778 ef10_tx_qdesc_dma_create(
780 __in efsys_dma_addr_t addr,
783 __out efx_desc_t *edp);
786 ef10_tx_qdesc_tso_create(
788 __in uint16_t ipv4_id,
789 __in uint32_t tcp_seq,
790 __in uint8_t tcp_flags,
791 __out efx_desc_t *edp);
794 ef10_tx_qdesc_tso2_create(
796 __in uint16_t ipv4_id,
797 __in uint16_t outer_ipv4_id,
798 __in uint32_t tcp_seq,
799 __in uint16_t tcp_mss,
800 __out_ecount(count) efx_desc_t *edp,
804 ef10_tx_qdesc_vlantci_create(
806 __in uint16_t vlan_tci,
807 __out efx_desc_t *edp);
810 ef10_tx_qdesc_checksum_create(
813 __out efx_desc_t *edp);
818 ef10_tx_qstats_update(
820 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
822 #endif /* EFSYS_OPT_QSTATS */
824 typedef uint32_t efx_piobuf_handle_t;
826 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
828 extern __checkReturn efx_rc_t
830 __inout efx_nic_t *enp,
831 __out uint32_t *bufnump,
832 __out efx_piobuf_handle_t *handlep,
833 __out uint32_t *blknump,
834 __out uint32_t *offsetp,
835 __out size_t *sizep);
837 extern __checkReturn efx_rc_t
839 __inout efx_nic_t *enp,
840 __in uint32_t bufnum,
841 __in uint32_t blknum);
843 extern __checkReturn efx_rc_t
845 __inout efx_nic_t *enp,
846 __in uint32_t vi_index,
847 __in efx_piobuf_handle_t handle);
849 extern __checkReturn efx_rc_t
851 __inout efx_nic_t *enp,
852 __in uint32_t vi_index);
859 extern __checkReturn efx_rc_t
861 __in efx_nic_t *enp);
863 extern __checkReturn efx_rc_t
866 __out size_t *sizep);
868 extern __checkReturn efx_rc_t
871 __out_bcount(size) caddr_t data,
874 extern __checkReturn efx_rc_t
877 __in_bcount(size) caddr_t data,
880 extern __checkReturn efx_rc_t
883 __in_bcount(size) caddr_t data,
886 extern __checkReturn efx_rc_t
889 __in_bcount(size) caddr_t data,
891 __inout efx_vpd_value_t *evvp);
893 extern __checkReturn efx_rc_t
896 __in_bcount(size) caddr_t data,
898 __in efx_vpd_value_t *evvp);
900 extern __checkReturn efx_rc_t
903 __in_bcount(size) caddr_t data,
905 __out efx_vpd_value_t *evvp,
906 __inout unsigned int *contp);
908 extern __checkReturn efx_rc_t
911 __in_bcount(size) caddr_t data,
916 __in efx_nic_t *enp);
918 #endif /* EFSYS_OPT_VPD */
923 extern __checkReturn efx_rc_t
925 __in efx_nic_t *enp);
927 #if EFSYS_OPT_RX_SCATTER
928 extern __checkReturn efx_rc_t
929 ef10_rx_scatter_enable(
931 __in unsigned int buf_size);
932 #endif /* EFSYS_OPT_RX_SCATTER */
935 #if EFSYS_OPT_RX_SCALE
937 extern __checkReturn efx_rc_t
938 ef10_rx_scale_context_alloc(
940 __in efx_rx_scale_context_type_t type,
941 __in uint32_t num_queues,
942 __out uint32_t *rss_contextp);
944 extern __checkReturn efx_rc_t
945 ef10_rx_scale_context_free(
947 __in uint32_t rss_context);
949 extern __checkReturn efx_rc_t
950 ef10_rx_scale_mode_set(
952 __in uint32_t rss_context,
953 __in efx_rx_hash_alg_t alg,
954 __in efx_rx_hash_type_t type,
955 __in boolean_t insert);
957 extern __checkReturn efx_rc_t
958 ef10_rx_scale_key_set(
960 __in uint32_t rss_context,
961 __in_ecount(n) uint8_t *key,
964 extern __checkReturn efx_rc_t
965 ef10_rx_scale_tbl_set(
967 __in uint32_t rss_context,
968 __in_ecount(n) unsigned int *table,
971 extern __checkReturn uint32_t
974 __in efx_rx_hash_alg_t func,
975 __in uint8_t *buffer);
977 #endif /* EFSYS_OPT_RX_SCALE */
979 extern __checkReturn efx_rc_t
980 ef10_rx_prefix_pktlen(
982 __in uint8_t *buffer,
983 __out uint16_t *lengthp);
988 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
990 __in unsigned int ndescs,
991 __in unsigned int completed,
992 __in unsigned int added);
997 __in unsigned int added,
998 __inout unsigned int *pushedp);
1000 extern __checkReturn efx_rc_t
1002 __in efx_rxq_t *erp);
1006 __in efx_rxq_t *erp);
1008 union efx_rxq_type_data_u;
1010 extern __checkReturn efx_rc_t
1012 __in efx_nic_t *enp,
1013 __in unsigned int index,
1014 __in unsigned int label,
1015 __in efx_rxq_type_t type,
1016 __in_opt const union efx_rxq_type_data_u *type_data,
1017 __in efsys_mem_t *esmp,
1020 __in unsigned int flags,
1021 __in efx_evq_t *eep,
1022 __in efx_rxq_t *erp);
1026 __in efx_rxq_t *erp);
1030 __in efx_nic_t *enp);
1032 #if EFSYS_OPT_FILTER
1034 typedef struct ef10_filter_handle_s {
1037 } ef10_filter_handle_t;
1039 typedef struct ef10_filter_entry_s {
1040 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1041 ef10_filter_handle_t efe_handle;
1042 } ef10_filter_entry_t;
1045 * BUSY flag indicates that an update is in progress.
1046 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1048 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1049 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1050 #define EFX_EF10_FILTER_FLAGS 3U
1053 * Size of the hash table used by the driver. Doesn't need to be the
1054 * same size as the hardware's table.
1056 #define EFX_EF10_FILTER_TBL_ROWS 8192
1058 /* Only need to allow for one directed and one unknown unicast filter */
1059 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1061 /* Allow for the broadcast address to be added to the multicast list */
1062 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1065 * For encapsulated packets, there is one filter each for each combination of
1066 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1067 * multicast inner frames.
1069 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1071 typedef struct ef10_filter_table_s {
1072 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1073 efx_rxq_t *eft_default_rxq;
1074 boolean_t eft_using_rss;
1075 uint32_t eft_unicst_filter_indexes[
1076 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1077 uint32_t eft_unicst_filter_count;
1078 uint32_t eft_mulcst_filter_indexes[
1079 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1080 uint32_t eft_mulcst_filter_count;
1081 boolean_t eft_using_all_mulcst;
1082 uint32_t eft_encap_filter_indexes[
1083 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1084 uint32_t eft_encap_filter_count;
1085 } ef10_filter_table_t;
1087 __checkReturn efx_rc_t
1089 __in efx_nic_t *enp);
1093 __in efx_nic_t *enp);
1095 __checkReturn efx_rc_t
1096 ef10_filter_restore(
1097 __in efx_nic_t *enp);
1099 __checkReturn efx_rc_t
1101 __in efx_nic_t *enp,
1102 __inout efx_filter_spec_t *spec,
1103 __in boolean_t may_replace);
1105 __checkReturn efx_rc_t
1107 __in efx_nic_t *enp,
1108 __inout efx_filter_spec_t *spec);
1110 extern __checkReturn efx_rc_t
1111 ef10_filter_supported_filters(
1112 __in efx_nic_t *enp,
1113 __out_ecount(buffer_length) uint32_t *buffer,
1114 __in size_t buffer_length,
1115 __out size_t *list_lengthp);
1117 extern __checkReturn efx_rc_t
1118 ef10_filter_reconfigure(
1119 __in efx_nic_t *enp,
1120 __in_ecount(6) uint8_t const *mac_addr,
1121 __in boolean_t all_unicst,
1122 __in boolean_t mulcst,
1123 __in boolean_t all_mulcst,
1124 __in boolean_t brdcst,
1125 __in_ecount(6*count) uint8_t const *addrs,
1126 __in uint32_t count);
1129 ef10_filter_get_default_rxq(
1130 __in efx_nic_t *enp,
1131 __out efx_rxq_t **erpp,
1132 __out boolean_t *using_rss);
1135 ef10_filter_default_rxq_set(
1136 __in efx_nic_t *enp,
1137 __in efx_rxq_t *erp,
1138 __in boolean_t using_rss);
1141 ef10_filter_default_rxq_clear(
1142 __in efx_nic_t *enp);
1145 #endif /* EFSYS_OPT_FILTER */
1147 extern __checkReturn efx_rc_t
1148 efx_mcdi_get_function_info(
1149 __in efx_nic_t *enp,
1150 __out uint32_t *pfp,
1151 __out_opt uint32_t *vfp);
1153 extern __checkReturn efx_rc_t
1154 efx_mcdi_privilege_mask(
1155 __in efx_nic_t *enp,
1158 __out uint32_t *maskp);
1160 extern __checkReturn efx_rc_t
1161 efx_mcdi_get_port_assignment(
1162 __in efx_nic_t *enp,
1163 __out uint32_t *portp);
1165 extern __checkReturn efx_rc_t
1166 efx_mcdi_get_port_modes(
1167 __in efx_nic_t *enp,
1168 __out uint32_t *modesp,
1169 __out_opt uint32_t *current_modep,
1170 __out_opt uint32_t *default_modep);
1172 extern __checkReturn efx_rc_t
1173 ef10_nic_get_port_mode_bandwidth(
1174 __in efx_nic_t *enp,
1175 __out uint32_t *bandwidth_mbpsp);
1177 extern __checkReturn efx_rc_t
1178 efx_mcdi_get_mac_address_pf(
1179 __in efx_nic_t *enp,
1180 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1182 extern __checkReturn efx_rc_t
1183 efx_mcdi_get_mac_address_vf(
1184 __in efx_nic_t *enp,
1185 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1187 extern __checkReturn efx_rc_t
1189 __in efx_nic_t *enp,
1190 __out uint32_t *sys_freqp,
1191 __out uint32_t *dpcpu_freqp);
1194 extern __checkReturn efx_rc_t
1195 efx_mcdi_get_rxdp_config(
1196 __in efx_nic_t *enp,
1197 __out uint32_t *end_paddingp);
1199 extern __checkReturn efx_rc_t
1200 efx_mcdi_get_vector_cfg(
1201 __in efx_nic_t *enp,
1202 __out_opt uint32_t *vec_basep,
1203 __out_opt uint32_t *pf_nvecp,
1204 __out_opt uint32_t *vf_nvecp);
1206 extern __checkReturn efx_rc_t
1207 ef10_get_privilege_mask(
1208 __in efx_nic_t *enp,
1209 __out uint32_t *maskp);
1211 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1213 extern __checkReturn efx_rc_t
1214 efx_mcdi_get_nic_global(
1215 __in efx_nic_t *enp,
1217 __out uint32_t *valuep);
1219 extern __checkReturn efx_rc_t
1220 efx_mcdi_set_nic_global(
1221 __in efx_nic_t *enp,
1223 __in uint32_t value);
1225 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1228 #if EFSYS_OPT_RX_PACKED_STREAM
1230 /* Data space per credit in packed stream mode */
1231 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1234 * Received packets are always aligned at this boundary. Also there always
1235 * exists a gap of this size between packets.
1236 * (see SF-112241-TC, 4.5)
1238 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1241 * Size of a pseudo-header prepended to received packets
1242 * in packed stream mode
1244 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1246 /* Minimum space for packet in packed stream mode */
1247 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1248 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1250 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1251 EFX_RX_PACKED_STREAM_ALIGNMENT)
1253 /* Maximum number of credits */
1254 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1256 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1258 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1261 * Maximum DMA length and buffer stride alignment.
1262 * (see SF-119419-TC, 3.2)
1264 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1272 #endif /* _SYS_EF10_IMPL_H */