1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
27 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
28 enp->en_family == EFX_FAMILY_MEDFORD ||
29 enp->en_family == EFX_FAMILY_MEDFORD2);
31 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
32 req.emr_in_buf = payload;
33 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
34 req.emr_out_buf = payload;
35 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
37 efx_mcdi_execute(enp, &req);
39 if (req.emr_rc != 0) {
44 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
49 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
56 EFSYS_PROBE1(fail1, efx_rc_t, rc);
61 __checkReturn efx_rc_t
62 efx_mcdi_get_port_modes(
64 __out uint32_t *modesp,
65 __out_opt uint32_t *current_modep,
66 __out_opt uint32_t *default_modep)
69 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
70 MC_CMD_GET_PORT_MODES_OUT_LEN);
73 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
74 enp->en_family == EFX_FAMILY_MEDFORD ||
75 enp->en_family == EFX_FAMILY_MEDFORD2);
77 req.emr_cmd = MC_CMD_GET_PORT_MODES;
78 req.emr_in_buf = payload;
79 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
80 req.emr_out_buf = payload;
81 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
83 efx_mcdi_execute(enp, &req);
85 if (req.emr_rc != 0) {
91 * Require only Modes and DefaultMode fields, unless the current mode
92 * was requested (CurrentMode field was added for Medford).
94 if (req.emr_out_length_used <
95 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
99 if ((current_modep != NULL) && (req.emr_out_length_used <
100 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
105 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
107 if (current_modep != NULL) {
108 *current_modep = MCDI_OUT_DWORD(req,
109 GET_PORT_MODES_OUT_CURRENT_MODE);
112 if (default_modep != NULL) {
113 *default_modep = MCDI_OUT_DWORD(req,
114 GET_PORT_MODES_OUT_DEFAULT_MODE);
124 EFSYS_PROBE1(fail1, efx_rc_t, rc);
129 __checkReturn efx_rc_t
130 ef10_nic_get_port_mode_bandwidth(
131 __in uint32_t port_mode,
132 __out uint32_t *bandwidth_mbpsp)
134 uint32_t single_lane = 10000;
135 uint32_t dual_lane = 50000;
136 uint32_t quad_lane = 40000;
141 case TLV_PORT_MODE_1x1_NA: /* mode 0 */
142 bandwidth = single_lane;
144 case TLV_PORT_MODE_1x2_NA: /* mode 10 */
145 case TLV_PORT_MODE_NA_1x2: /* mode 11 */
146 bandwidth = dual_lane;
148 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
149 bandwidth = single_lane + single_lane;
151 case TLV_PORT_MODE_4x1_NA: /* mode 4 */
152 case TLV_PORT_MODE_NA_4x1: /* mode 8 */
153 bandwidth = 4 * single_lane;
155 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
156 bandwidth = (2 * single_lane) + (2 * single_lane);
158 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
159 bandwidth = dual_lane + dual_lane;
161 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */
162 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */
163 bandwidth = dual_lane + (2 * single_lane);
165 /* Legacy Medford-only mode. Do not use (see bug63270) */
166 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
167 bandwidth = 4 * single_lane;
169 case TLV_PORT_MODE_1x4_NA: /* mode 1 */
170 case TLV_PORT_MODE_NA_1x4: /* mode 22 */
171 bandwidth = quad_lane;
173 case TLV_PORT_MODE_2x2_NA: /* mode 13 */
174 case TLV_PORT_MODE_NA_2x2: /* mode 14 */
175 bandwidth = 2 * dual_lane;
177 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
178 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
179 bandwidth = quad_lane + (2 * single_lane);
181 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */
182 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */
183 bandwidth = quad_lane + dual_lane;
185 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
186 bandwidth = quad_lane + quad_lane;
193 *bandwidth_mbpsp = bandwidth;
198 EFSYS_PROBE1(fail1, efx_rc_t, rc);
203 static __checkReturn efx_rc_t
204 efx_mcdi_vadaptor_alloc(
206 __in uint32_t port_id)
209 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
210 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
213 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
215 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
216 req.emr_in_buf = payload;
217 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
218 req.emr_out_buf = payload;
219 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
221 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
222 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
223 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
224 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
226 efx_mcdi_execute(enp, &req);
228 if (req.emr_rc != 0) {
236 EFSYS_PROBE1(fail1, efx_rc_t, rc);
241 static __checkReturn efx_rc_t
242 efx_mcdi_vadaptor_free(
244 __in uint32_t port_id)
247 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
248 MC_CMD_VADAPTOR_FREE_OUT_LEN);
251 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
252 req.emr_in_buf = payload;
253 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
254 req.emr_out_buf = payload;
255 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
257 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
259 efx_mcdi_execute(enp, &req);
261 if (req.emr_rc != 0) {
269 EFSYS_PROBE1(fail1, efx_rc_t, rc);
274 __checkReturn efx_rc_t
275 efx_mcdi_get_mac_address_pf(
277 __out_ecount_opt(6) uint8_t mac_addrp[6])
280 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
281 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
284 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
285 enp->en_family == EFX_FAMILY_MEDFORD ||
286 enp->en_family == EFX_FAMILY_MEDFORD2);
288 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
289 req.emr_in_buf = payload;
290 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
291 req.emr_out_buf = payload;
292 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
294 efx_mcdi_execute(enp, &req);
296 if (req.emr_rc != 0) {
301 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
306 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
311 if (mac_addrp != NULL) {
314 addrp = MCDI_OUT2(req, uint8_t,
315 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
317 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
327 EFSYS_PROBE1(fail1, efx_rc_t, rc);
332 __checkReturn efx_rc_t
333 efx_mcdi_get_mac_address_vf(
335 __out_ecount_opt(6) uint8_t mac_addrp[6])
338 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
339 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
342 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
343 enp->en_family == EFX_FAMILY_MEDFORD ||
344 enp->en_family == EFX_FAMILY_MEDFORD2);
346 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
347 req.emr_in_buf = payload;
348 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
349 req.emr_out_buf = payload;
350 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
352 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
353 EVB_PORT_ID_ASSIGNED);
355 efx_mcdi_execute(enp, &req);
357 if (req.emr_rc != 0) {
362 if (req.emr_out_length_used <
363 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
368 if (MCDI_OUT_DWORD(req,
369 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
374 if (mac_addrp != NULL) {
377 addrp = MCDI_OUT2(req, uint8_t,
378 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
380 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
390 EFSYS_PROBE1(fail1, efx_rc_t, rc);
395 __checkReturn efx_rc_t
398 __out uint32_t *sys_freqp,
399 __out uint32_t *dpcpu_freqp)
402 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
403 MC_CMD_GET_CLOCK_OUT_LEN);
406 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
407 enp->en_family == EFX_FAMILY_MEDFORD ||
408 enp->en_family == EFX_FAMILY_MEDFORD2);
410 req.emr_cmd = MC_CMD_GET_CLOCK;
411 req.emr_in_buf = payload;
412 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
413 req.emr_out_buf = payload;
414 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
416 efx_mcdi_execute(enp, &req);
418 if (req.emr_rc != 0) {
423 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
428 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
429 if (*sys_freqp == 0) {
433 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
434 if (*dpcpu_freqp == 0) {
448 EFSYS_PROBE1(fail1, efx_rc_t, rc);
453 __checkReturn efx_rc_t
454 efx_mcdi_get_rxdp_config(
456 __out uint32_t *end_paddingp)
459 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
460 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
461 uint32_t end_padding;
464 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
465 req.emr_in_buf = payload;
466 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
467 req.emr_out_buf = payload;
468 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
470 efx_mcdi_execute(enp, &req);
471 if (req.emr_rc != 0) {
476 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
477 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
478 /* RX DMA end padding is disabled */
481 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
482 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
483 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
486 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
489 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
498 *end_paddingp = end_padding;
505 EFSYS_PROBE1(fail1, efx_rc_t, rc);
510 __checkReturn efx_rc_t
511 efx_mcdi_get_vector_cfg(
513 __out_opt uint32_t *vec_basep,
514 __out_opt uint32_t *pf_nvecp,
515 __out_opt uint32_t *vf_nvecp)
518 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
519 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
522 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
523 req.emr_in_buf = payload;
524 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
525 req.emr_out_buf = payload;
526 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
528 efx_mcdi_execute(enp, &req);
530 if (req.emr_rc != 0) {
535 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
540 if (vec_basep != NULL)
541 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
542 if (pf_nvecp != NULL)
543 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
544 if (vf_nvecp != NULL)
545 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
552 EFSYS_PROBE1(fail1, efx_rc_t, rc);
557 static __checkReturn efx_rc_t
560 __in uint32_t min_vi_count,
561 __in uint32_t max_vi_count,
562 __out uint32_t *vi_basep,
563 __out uint32_t *vi_countp,
564 __out uint32_t *vi_shiftp)
567 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
568 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
571 if (vi_countp == NULL) {
576 req.emr_cmd = MC_CMD_ALLOC_VIS;
577 req.emr_in_buf = payload;
578 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
579 req.emr_out_buf = payload;
580 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
582 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
583 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
585 efx_mcdi_execute(enp, &req);
587 if (req.emr_rc != 0) {
592 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
597 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
598 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
600 /* Report VI_SHIFT if available (always zero for Huntington) */
601 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
604 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
613 EFSYS_PROBE1(fail1, efx_rc_t, rc);
619 static __checkReturn efx_rc_t
626 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
627 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
629 req.emr_cmd = MC_CMD_FREE_VIS;
630 req.emr_in_buf = NULL;
631 req.emr_in_length = 0;
632 req.emr_out_buf = NULL;
633 req.emr_out_length = 0;
635 efx_mcdi_execute_quiet(enp, &req);
637 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
638 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
646 EFSYS_PROBE1(fail1, efx_rc_t, rc);
652 static __checkReturn efx_rc_t
653 efx_mcdi_alloc_piobuf(
655 __out efx_piobuf_handle_t *handlep)
658 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
659 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
662 if (handlep == NULL) {
667 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
668 req.emr_in_buf = payload;
669 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
670 req.emr_out_buf = payload;
671 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
673 efx_mcdi_execute_quiet(enp, &req);
675 if (req.emr_rc != 0) {
680 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
685 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
694 EFSYS_PROBE1(fail1, efx_rc_t, rc);
699 static __checkReturn efx_rc_t
700 efx_mcdi_free_piobuf(
702 __in efx_piobuf_handle_t handle)
705 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
706 MC_CMD_FREE_PIOBUF_OUT_LEN);
709 req.emr_cmd = MC_CMD_FREE_PIOBUF;
710 req.emr_in_buf = payload;
711 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
712 req.emr_out_buf = payload;
713 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
715 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
717 efx_mcdi_execute_quiet(enp, &req);
719 if (req.emr_rc != 0) {
727 EFSYS_PROBE1(fail1, efx_rc_t, rc);
732 static __checkReturn efx_rc_t
733 efx_mcdi_link_piobuf(
735 __in uint32_t vi_index,
736 __in efx_piobuf_handle_t handle)
739 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
740 MC_CMD_LINK_PIOBUF_OUT_LEN);
743 req.emr_cmd = MC_CMD_LINK_PIOBUF;
744 req.emr_in_buf = payload;
745 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
746 req.emr_out_buf = payload;
747 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
749 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
750 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
752 efx_mcdi_execute(enp, &req);
754 if (req.emr_rc != 0) {
762 EFSYS_PROBE1(fail1, efx_rc_t, rc);
767 static __checkReturn efx_rc_t
768 efx_mcdi_unlink_piobuf(
770 __in uint32_t vi_index)
773 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
774 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
777 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
778 req.emr_in_buf = payload;
779 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
780 req.emr_out_buf = payload;
781 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
783 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
785 efx_mcdi_execute_quiet(enp, &req);
787 if (req.emr_rc != 0) {
795 EFSYS_PROBE1(fail1, efx_rc_t, rc);
801 ef10_nic_alloc_piobufs(
803 __in uint32_t max_piobuf_count)
805 efx_piobuf_handle_t *handlep;
808 EFSYS_ASSERT3U(max_piobuf_count, <=,
809 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
811 enp->en_arch.ef10.ena_piobuf_count = 0;
813 for (i = 0; i < max_piobuf_count; i++) {
814 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
816 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
819 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
820 enp->en_arch.ef10.ena_piobuf_count++;
826 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
827 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
829 (void) efx_mcdi_free_piobuf(enp, *handlep);
830 *handlep = EFX_PIOBUF_HANDLE_INVALID;
832 enp->en_arch.ef10.ena_piobuf_count = 0;
837 ef10_nic_free_piobufs(
840 efx_piobuf_handle_t *handlep;
843 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
844 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
846 (void) efx_mcdi_free_piobuf(enp, *handlep);
847 *handlep = EFX_PIOBUF_HANDLE_INVALID;
849 enp->en_arch.ef10.ena_piobuf_count = 0;
852 /* Sub-allocate a block from a piobuf */
853 __checkReturn efx_rc_t
855 __inout efx_nic_t *enp,
856 __out uint32_t *bufnump,
857 __out efx_piobuf_handle_t *handlep,
858 __out uint32_t *blknump,
859 __out uint32_t *offsetp,
862 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
863 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
864 uint32_t blk_per_buf;
868 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
869 enp->en_family == EFX_FAMILY_MEDFORD ||
870 enp->en_family == EFX_FAMILY_MEDFORD2);
871 EFSYS_ASSERT(bufnump);
872 EFSYS_ASSERT(handlep);
873 EFSYS_ASSERT(blknump);
874 EFSYS_ASSERT(offsetp);
877 if ((edcp->edc_pio_alloc_size == 0) ||
878 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
882 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
884 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
885 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
890 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
891 for (blk = 0; blk < blk_per_buf; blk++) {
892 if ((*map & (1u << blk)) == 0) {
902 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
905 *sizep = edcp->edc_pio_alloc_size;
906 *offsetp = blk * (*sizep);
913 EFSYS_PROBE1(fail1, efx_rc_t, rc);
918 /* Free a piobuf sub-allocated block */
919 __checkReturn efx_rc_t
921 __inout efx_nic_t *enp,
922 __in uint32_t bufnum,
923 __in uint32_t blknum)
928 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
929 (blknum >= (8 * sizeof (*map)))) {
934 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
935 if ((*map & (1u << blknum)) == 0) {
939 *map &= ~(1u << blknum);
946 EFSYS_PROBE1(fail1, efx_rc_t, rc);
951 __checkReturn efx_rc_t
953 __inout efx_nic_t *enp,
954 __in uint32_t vi_index,
955 __in efx_piobuf_handle_t handle)
957 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
960 __checkReturn efx_rc_t
962 __inout efx_nic_t *enp,
963 __in uint32_t vi_index)
965 return (efx_mcdi_unlink_piobuf(enp, vi_index));
968 static __checkReturn efx_rc_t
969 ef10_mcdi_get_pf_count(
971 __out uint32_t *pf_countp)
974 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
975 MC_CMD_GET_PF_COUNT_OUT_LEN);
978 req.emr_cmd = MC_CMD_GET_PF_COUNT;
979 req.emr_in_buf = payload;
980 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
981 req.emr_out_buf = payload;
982 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
984 efx_mcdi_execute(enp, &req);
986 if (req.emr_rc != 0) {
991 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
996 *pf_countp = *MCDI_OUT(req, uint8_t,
997 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
999 EFSYS_ASSERT(*pf_countp != 0);
1006 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1011 static __checkReturn efx_rc_t
1012 ef10_get_datapath_caps(
1013 __in efx_nic_t *enp)
1015 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1017 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN,
1018 MC_CMD_GET_CAPABILITIES_V5_OUT_LEN);
1021 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1025 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1026 req.emr_in_buf = payload;
1027 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1028 req.emr_out_buf = payload;
1029 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN;
1031 efx_mcdi_execute_quiet(enp, &req);
1033 if (req.emr_rc != 0) {
1038 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1043 #define CAP_FLAGS1(_req, _flag) \
1044 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1045 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1047 #define CAP_FLAGS2(_req, _flag) \
1048 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1049 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1050 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1053 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1054 * We only support the 14 byte prefix here.
1056 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) {
1060 encp->enc_rx_prefix_size = 14;
1062 /* Check if the firmware supports additional RSS modes */
1063 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1064 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1066 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1068 /* Check if the firmware supports TSO */
1069 if (CAP_FLAGS1(req, TX_TSO))
1070 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1072 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1074 /* Check if the firmware supports FATSOv2 */
1075 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1076 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1077 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1078 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1080 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1081 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1084 /* Check if the firmware supports FATSOv2 encap */
1085 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1086 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1088 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1090 /* Check if the firmware has vadapter/vport/vswitch support */
1091 if (CAP_FLAGS1(req, EVB))
1092 encp->enc_datapath_cap_evb = B_TRUE;
1094 encp->enc_datapath_cap_evb = B_FALSE;
1096 /* Check if the firmware supports VLAN insertion */
1097 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1098 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1100 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1102 /* Check if the firmware supports RX event batching */
1103 if (CAP_FLAGS1(req, RX_BATCHING))
1104 encp->enc_rx_batching_enabled = B_TRUE;
1106 encp->enc_rx_batching_enabled = B_FALSE;
1109 * Even if batching isn't reported as supported, we may still get
1110 * batched events (see bug61153).
1112 encp->enc_rx_batch_max = 16;
1114 /* Check if the firmware supports disabling scatter on RXQs */
1115 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1116 encp->enc_rx_disable_scatter_supported = B_TRUE;
1118 encp->enc_rx_disable_scatter_supported = B_FALSE;
1120 /* Check if the firmware supports packed stream mode */
1121 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1122 encp->enc_rx_packed_stream_supported = B_TRUE;
1124 encp->enc_rx_packed_stream_supported = B_FALSE;
1127 * Check if the firmware supports configurable buffer sizes
1128 * for packed stream mode (otherwise buffer size is 1Mbyte)
1130 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1131 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1133 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1135 /* Check if the firmware supports equal stride super-buffer mode */
1136 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1137 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1139 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1141 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1142 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1143 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1145 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1147 /* Check if the firmware supports set mac with running filters */
1148 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1149 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1151 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1154 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1155 * specifying which parameters to configure.
1157 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1158 encp->enc_enhanced_set_mac_supported = B_TRUE;
1160 encp->enc_enhanced_set_mac_supported = B_FALSE;
1163 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1164 * us to let the firmware choose the settings to use on an EVQ.
1166 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1167 encp->enc_init_evq_v2_supported = B_TRUE;
1169 encp->enc_init_evq_v2_supported = B_FALSE;
1172 * Check if firmware-verified NVRAM updates must be used.
1174 * The firmware trusted installer requires all NVRAM updates to use
1175 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1176 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1177 * partition and report the result).
1179 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1180 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1182 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1185 * Check if firmware provides packet memory and Rx datapath
1188 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1189 encp->enc_pm_and_rxdp_counters = B_TRUE;
1191 encp->enc_pm_and_rxdp_counters = B_FALSE;
1194 * Check if the 40G MAC hardware is capable of reporting
1195 * statistics for Tx size bins.
1197 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1198 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1200 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1203 * Check if firmware supports VXLAN and NVGRE tunnels.
1204 * The capability indicates Geneve protocol support as well.
1206 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1207 encp->enc_tunnel_encapsulations_supported =
1208 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1209 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1210 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1212 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1213 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1214 encp->enc_tunnel_config_udp_entries_max =
1215 EFX_TUNNEL_MAXNENTRIES;
1217 encp->enc_tunnel_config_udp_entries_max = 0;
1221 * Check if firmware reports the VI window mode.
1222 * Medford2 has a variable VI window size (8K, 16K or 64K).
1223 * Medford and Huntington have a fixed 8K VI window size.
1225 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1227 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1230 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1231 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1233 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1234 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1236 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1237 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1240 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1243 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1244 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1245 /* Huntington and Medford have fixed 8K window size */
1246 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1248 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1251 /* Check if firmware supports extended MAC stats. */
1252 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1253 /* Extended stats buffer supported */
1254 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1255 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1257 /* Use Siena-compatible legacy MAC stats */
1258 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1261 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1262 encp->enc_fec_counters = B_TRUE;
1264 encp->enc_fec_counters = B_FALSE;
1266 /* Check if the firmware provides head-of-line blocking counters */
1267 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1268 encp->enc_hlb_counters = B_TRUE;
1270 encp->enc_hlb_counters = B_FALSE;
1272 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1273 /* Only one exclusive RSS context is available per port. */
1274 encp->enc_rx_scale_max_exclusive_contexts = 1;
1276 switch (enp->en_family) {
1277 case EFX_FAMILY_MEDFORD2:
1278 encp->enc_rx_scale_hash_alg_mask =
1279 (1U << EFX_RX_HASHALG_TOEPLITZ);
1282 case EFX_FAMILY_MEDFORD:
1283 case EFX_FAMILY_HUNTINGTON:
1285 * Packed stream firmware variant maintains a
1286 * non-standard algorithm for hash computation.
1287 * It implies explicit XORing together
1288 * source + destination IP addresses (or last
1289 * four bytes in the case of IPv6) and using the
1290 * resulting value as the input to a Toeplitz hash.
1292 encp->enc_rx_scale_hash_alg_mask =
1293 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1301 /* Port numbers cannot contribute to the hash value */
1302 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1305 * Maximum number of exclusive RSS contexts.
1306 * EF10 hardware supports 64 in total, but 6 are reserved
1307 * for shared contexts. They are a global resource so
1308 * not all may be available.
1310 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1312 encp->enc_rx_scale_hash_alg_mask =
1313 (1U << EFX_RX_HASHALG_TOEPLITZ);
1316 * It is possible to use port numbers as
1317 * the input data for hash computation.
1319 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1321 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1322 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1323 encp->enc_filter_action_flag_supported = B_TRUE;
1325 encp->enc_filter_action_flag_supported = B_FALSE;
1327 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1328 encp->enc_filter_action_mark_supported = B_TRUE;
1330 encp->enc_filter_action_mark_supported = B_FALSE;
1332 /* Get maximum supported value for "MARK" filter action */
1333 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1334 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1335 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1337 encp->enc_filter_action_mark_max = 0;
1353 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1359 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1360 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1361 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1362 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1363 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1364 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1365 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1366 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1367 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1368 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1369 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1370 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1372 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1375 __checkReturn efx_rc_t
1376 ef10_get_privilege_mask(
1377 __in efx_nic_t *enp,
1378 __out uint32_t *maskp)
1380 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1384 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1389 /* Fallback for old firmware without privilege mask support */
1390 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1391 /* Assume PF has admin privilege */
1392 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1394 /* VF is always unprivileged by default */
1395 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1404 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1411 * Table of mapping schemes from port number to external number.
1413 * Each port number ultimately corresponds to a connector: either as part of
1414 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1415 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1416 * "Salina"). In general:
1418 * Port number (0-based)
1420 * port mapping (n:1)
1423 * External port number (normally 1-based)
1425 * fixed (1:1) or cable assembly (1:m)
1430 * The external numbering refers to the cages or magjacks on the board,
1431 * as visibly annotated on the board or back panel. This table describes
1432 * how to determine which external cage/magjack corresponds to the port
1433 * numbers used by the driver.
1435 * The count of adjacent port numbers that map to each external number,
1436 * and the offset in the numbering, is determined by the chip family and
1437 * current port mode.
1439 * For the Huntington family, the current port mode cannot be discovered,
1440 * but a single mapping is used by all modes for a given chip variant,
1441 * so the mapping used is instead the last match in the table to the full
1442 * set of port modes to which the NIC can be configured. Therefore the
1443 * ordering of entries in the mapping table is significant.
1445 static struct ef10_external_port_map_s {
1446 efx_family_t family;
1447 uint32_t modes_mask;
1450 } __ef10_external_port_mappings[] = {
1452 * Modes used by Huntington family controllers where each port
1453 * number maps to a separate cage.
1454 * SFN7x22F (Torino):
1464 EFX_FAMILY_HUNTINGTON,
1465 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1466 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1467 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1468 1, /* ports per cage */
1472 * Modes which for Huntington identify a chip variant where 2
1473 * adjacent port numbers map to each cage.
1481 EFX_FAMILY_HUNTINGTON,
1482 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1483 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1484 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1485 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1486 2, /* ports per cage */
1490 * Modes that on Medford allocate each port number to a separate
1499 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1500 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1501 1, /* ports per cage */
1505 * Modes that on Medford allocate 2 adjacent port numbers to each
1514 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1515 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1516 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1517 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1518 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1519 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1520 2, /* ports per cage */
1524 * Modes that on Medford allocate 4 adjacent port numbers to each
1525 * connector, starting on cage 1.
1533 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
1534 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1535 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
1536 4, /* ports per cage */
1540 * Modes that on Medford allocate 4 adjacent port numbers to each
1541 * connector, starting on cage 2.
1549 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
1550 4, /* ports per cage */
1554 * Modes that on Medford2 allocate each port number to a separate
1562 EFX_FAMILY_MEDFORD2,
1563 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1564 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1565 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1566 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1567 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1568 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1569 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1570 1, /* ports per cage */
1574 * FIXME: Some port modes are not representable in this mapping:
1575 * - TLV_PORT_MODE_1x2_2x1 (mode 17):
1581 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1582 * cage, starting on cage 1.
1589 EFX_FAMILY_MEDFORD2,
1590 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1591 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1592 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1593 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1594 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1595 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1596 2, /* ports per cage */
1600 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1601 * cage, starting on cage 2.
1606 EFX_FAMILY_MEDFORD2,
1607 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1608 2, /* ports per cage */
1612 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1613 * connector, starting on cage 1.
1620 EFX_FAMILY_MEDFORD2,
1621 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1622 4, /* ports per cage */
1626 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1627 * connector, starting on cage 2.
1634 EFX_FAMILY_MEDFORD2,
1635 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1636 (1U << TLV_PORT_MODE_NA_1x2), /* mode 11 */
1637 4, /* ports per cage */
1642 static __checkReturn efx_rc_t
1643 ef10_external_port_mapping(
1644 __in efx_nic_t *enp,
1646 __out uint8_t *external_portp)
1650 uint32_t port_modes;
1653 int32_t count = 1; /* Default 1-1 mapping */
1654 int32_t offset = 1; /* Default starting external port number */
1656 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1659 * No current port mode information (i.e. Huntington)
1660 * - infer mapping from available modes
1662 if ((rc = efx_mcdi_get_port_modes(enp,
1663 &port_modes, NULL, NULL)) != 0) {
1665 * No port mode information available
1666 * - use default mapping
1671 /* Only need to scan the current mode */
1672 port_modes = 1 << current;
1676 * Infer the internal port -> external number mapping from
1677 * the possible port modes for this NIC.
1679 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1680 struct ef10_external_port_map_s *eepmp =
1681 &__ef10_external_port_mappings[i];
1682 if (eepmp->family != enp->en_family)
1684 matches = (eepmp->modes_mask & port_modes);
1687 * Some modes match. For some Huntington boards
1688 * there will be multiple matches. The mapping on the
1689 * last match is used.
1691 count = eepmp->count;
1692 offset = eepmp->offset;
1693 port_modes &= ~matches;
1697 if (port_modes != 0) {
1698 /* Some advertised modes are not supported */
1705 * Scale as required by last matched mode and then convert to
1706 * correctly offset numbering
1708 *external_portp = (uint8_t)((port / count) + offset);
1712 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1717 static __checkReturn efx_rc_t
1719 __in efx_nic_t *enp)
1721 const efx_nic_ops_t *enop = enp->en_enop;
1722 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1723 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1724 ef10_link_state_t els;
1725 efx_port_t *epp = &(enp->en_port);
1726 uint32_t board_type = 0;
1727 uint32_t base, nvec;
1732 uint8_t mac_addr[6] = { 0 };
1735 /* Get the (zero-based) MCDI port number */
1736 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1739 /* EFX MCDI interface uses one-based port numbers */
1740 emip->emi_port = port + 1;
1742 if ((rc = ef10_external_port_mapping(enp, port,
1743 &encp->enc_external_port)) != 0)
1747 * Get PCIe function number from firmware (used for
1748 * per-function privilege and dynamic config info).
1749 * - PCIe PF: pf = PF number, vf = 0xffff.
1750 * - PCIe VF: pf = parent PF, vf = VF number.
1752 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1758 /* MAC address for this function */
1759 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1760 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1761 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1763 * Disable static config checking, ONLY for manufacturing test
1764 * and setup at the factory, to allow the static config to be
1767 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1768 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1770 * If the static config does not include a global MAC
1771 * address pool then the board may return a locally
1772 * administered MAC address (this should only happen on
1773 * incorrectly programmed boards).
1777 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1779 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1784 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1786 /* Board configuration (legacy) */
1787 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1789 /* Unprivileged functions may not be able to read board cfg */
1796 encp->enc_board_type = board_type;
1797 encp->enc_clk_mult = 1; /* not used for EF10 */
1799 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1800 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1804 * Firmware with support for *_FEC capability bits does not
1805 * report that the corresponding *_FEC_REQUESTED bits are supported.
1806 * Add them here so that drivers understand that they are supported.
1808 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
1809 epp->ep_phy_cap_mask |=
1810 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
1811 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
1812 epp->ep_phy_cap_mask |=
1813 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
1814 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
1815 epp->ep_phy_cap_mask |=
1816 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
1818 /* Obtain the default PHY advertised capabilities */
1819 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1821 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
1822 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
1824 /* Check capabilities of running datapath firmware */
1825 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1828 /* Alignment for WPTR updates */
1829 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1831 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
1832 /* No boundary crossing limits */
1833 encp->enc_tx_dma_desc_boundary = 0;
1836 * Maximum number of bytes into the frame the TCP header can start for
1837 * firmware assisted TSO to work.
1839 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1842 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1843 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1844 * resources (allocated to this PCIe function), which is zero until
1845 * after we have allocated VIs.
1847 encp->enc_evq_limit = 1024;
1848 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1849 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1851 encp->enc_buftbl_limit = 0xFFFFFFFF;
1853 /* Get interrupt vector limits */
1854 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1855 if (EFX_PCI_FUNCTION_IS_PF(encp))
1858 /* Ignore error (cannot query vector limits from a VF). */
1862 encp->enc_intr_vec_base = base;
1863 encp->enc_intr_limit = nvec;
1866 * Get the current privilege mask. Note that this may be modified
1867 * dynamically, so this value is informational only. DO NOT use
1868 * the privilege mask to check for sufficient privileges, as that
1869 * can result in time-of-check/time-of-use bugs.
1871 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1873 encp->enc_privilege_mask = mask;
1875 /* Get remaining controller-specific board config */
1876 if ((rc = enop->eno_board_cfg(enp)) != 0)
1883 EFSYS_PROBE(fail11);
1885 EFSYS_PROBE(fail10);
1903 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1908 __checkReturn efx_rc_t
1910 __in efx_nic_t *enp)
1912 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1913 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1916 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1917 enp->en_family == EFX_FAMILY_MEDFORD ||
1918 enp->en_family == EFX_FAMILY_MEDFORD2);
1920 /* Read and clear any assertion state */
1921 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1924 /* Exit the assertion handler */
1925 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1929 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1932 if ((rc = ef10_nic_board_cfg(enp)) != 0)
1936 * Set default driver config limits (based on board config).
1938 * FIXME: For now allocate a fixed number of VIs which is likely to be
1939 * sufficient and small enough to allow multiple functions on the same
1942 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1943 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1945 /* The client driver must configure and enable PIO buffer support */
1946 edcp->edc_max_piobuf_count = 0;
1947 edcp->edc_pio_alloc_size = 0;
1949 #if EFSYS_OPT_MAC_STATS
1950 /* Wipe the MAC statistics */
1951 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1955 #if EFSYS_OPT_LOOPBACK
1956 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1960 #if EFSYS_OPT_MON_STATS
1961 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1962 /* Unprivileged functions do not have access to sensors */
1968 encp->enc_features = enp->en_features;
1972 #if EFSYS_OPT_MON_STATS
1976 #if EFSYS_OPT_LOOPBACK
1980 #if EFSYS_OPT_MAC_STATS
1991 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1996 __checkReturn efx_rc_t
1997 ef10_nic_set_drv_limits(
1998 __inout efx_nic_t *enp,
1999 __in efx_drv_limits_t *edlp)
2001 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2002 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2003 uint32_t min_evq_count, max_evq_count;
2004 uint32_t min_rxq_count, max_rxq_count;
2005 uint32_t min_txq_count, max_txq_count;
2013 /* Get minimum required and maximum usable VI limits */
2014 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2015 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2016 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2018 edcp->edc_min_vi_count =
2019 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2021 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2022 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2023 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2025 edcp->edc_max_vi_count =
2026 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2029 * Check limits for sub-allocated piobuf blocks.
2030 * PIO is optional, so don't fail if the limits are incorrect.
2032 if ((encp->enc_piobuf_size == 0) ||
2033 (encp->enc_piobuf_limit == 0) ||
2034 (edlp->edl_min_pio_alloc_size == 0) ||
2035 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2037 edcp->edc_max_piobuf_count = 0;
2038 edcp->edc_pio_alloc_size = 0;
2040 uint32_t blk_size, blk_count, blks_per_piobuf;
2043 MAX(edlp->edl_min_pio_alloc_size,
2044 encp->enc_piobuf_min_alloc_size);
2046 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2047 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2049 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2051 /* A zero max pio alloc count means unlimited */
2052 if ((edlp->edl_max_pio_alloc_count > 0) &&
2053 (edlp->edl_max_pio_alloc_count < blk_count)) {
2054 blk_count = edlp->edl_max_pio_alloc_count;
2057 edcp->edc_pio_alloc_size = blk_size;
2058 edcp->edc_max_piobuf_count =
2059 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2065 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2071 __checkReturn efx_rc_t
2073 __in efx_nic_t *enp)
2076 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
2077 MC_CMD_ENTITY_RESET_OUT_LEN);
2080 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2081 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2083 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2086 req.emr_cmd = MC_CMD_ENTITY_RESET;
2087 req.emr_in_buf = payload;
2088 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
2089 req.emr_out_buf = payload;
2090 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
2092 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
2093 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
2095 efx_mcdi_execute(enp, &req);
2097 if (req.emr_rc != 0) {
2102 /* Clear RX/TX DMA queue errors */
2103 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2112 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2117 __checkReturn efx_rc_t
2119 __in efx_nic_t *enp)
2121 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2122 uint32_t min_vi_count, max_vi_count;
2123 uint32_t vi_count, vi_base, vi_shift;
2127 uint32_t vi_window_size;
2130 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2131 enp->en_family == EFX_FAMILY_MEDFORD ||
2132 enp->en_family == EFX_FAMILY_MEDFORD2);
2134 /* Enable reporting of some events (e.g. link change) */
2135 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2138 /* Allocate (optional) on-chip PIO buffers */
2139 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2142 * For best performance, PIO writes should use a write-combined
2143 * (WC) memory mapping. Using a separate WC mapping for the PIO
2144 * aperture of each VI would be a burden to drivers (and not
2145 * possible if the host page size is >4Kbyte).
2147 * To avoid this we use a single uncached (UC) mapping for VI
2148 * register access, and a single WC mapping for extra VIs used
2151 * Each piobuf must be linked to a VI in the WC mapping, and to
2152 * each VI that is using a sub-allocated block from the piobuf.
2154 min_vi_count = edcp->edc_min_vi_count;
2156 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2158 /* Ensure that the previously attached driver's VIs are freed */
2159 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2163 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2164 * fails then retrying the request for fewer VI resources may succeed.
2167 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2168 &vi_base, &vi_count, &vi_shift)) != 0)
2171 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2173 if (vi_count < min_vi_count) {
2178 enp->en_arch.ef10.ena_vi_base = vi_base;
2179 enp->en_arch.ef10.ena_vi_count = vi_count;
2180 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2182 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2183 /* Not enough extra VIs to map piobufs */
2184 ef10_nic_free_piobufs(enp);
2187 enp->en_arch.ef10.ena_pio_write_vi_base =
2188 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2190 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2191 EFX_VI_WINDOW_SHIFT_INVALID);
2192 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2193 EFX_VI_WINDOW_SHIFT_64K);
2194 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2196 /* Save UC memory mapping details */
2197 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2198 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2199 enp->en_arch.ef10.ena_uc_mem_map_size =
2201 enp->en_arch.ef10.ena_pio_write_vi_base);
2203 enp->en_arch.ef10.ena_uc_mem_map_size =
2205 enp->en_arch.ef10.ena_vi_count);
2208 /* Save WC memory mapping details */
2209 enp->en_arch.ef10.ena_wc_mem_map_offset =
2210 enp->en_arch.ef10.ena_uc_mem_map_offset +
2211 enp->en_arch.ef10.ena_uc_mem_map_size;
2213 enp->en_arch.ef10.ena_wc_mem_map_size =
2215 enp->en_arch.ef10.ena_piobuf_count);
2217 /* Link piobufs to extra VIs in WC mapping */
2218 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2219 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2220 rc = efx_mcdi_link_piobuf(enp,
2221 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2222 enp->en_arch.ef10.ena_piobuf_handle[i]);
2229 * Allocate a vAdaptor attached to our upstream vPort/pPort.
2231 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2232 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2233 * retry the request several times after waiting a while. The wait time
2234 * between retries starts small (10ms) and exponentially increases.
2235 * Total wait time is a little over two seconds. Retry logic in the
2236 * client driver may mean this whole loop is repeated if it continues to
2241 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2242 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2245 * Do not retry alloc for PF, or for other errors on
2251 /* VF startup before PF is ready. Retry allocation. */
2253 /* Too many attempts */
2257 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2258 EFSYS_SLEEP(delay_us);
2260 if (delay_us < 500000)
2264 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2265 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2280 ef10_nic_free_piobufs(enp);
2283 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2288 __checkReturn efx_rc_t
2289 ef10_nic_get_vi_pool(
2290 __in efx_nic_t *enp,
2291 __out uint32_t *vi_countp)
2293 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2294 enp->en_family == EFX_FAMILY_MEDFORD ||
2295 enp->en_family == EFX_FAMILY_MEDFORD2);
2298 * Report VIs that the client driver can use.
2299 * Do not include VIs used for PIO buffer writes.
2301 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2306 __checkReturn efx_rc_t
2307 ef10_nic_get_bar_region(
2308 __in efx_nic_t *enp,
2309 __in efx_nic_region_t region,
2310 __out uint32_t *offsetp,
2311 __out size_t *sizep)
2315 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
2316 enp->en_family == EFX_FAMILY_MEDFORD ||
2317 enp->en_family == EFX_FAMILY_MEDFORD2);
2320 * TODO: Specify host memory mapping alignment and granularity
2321 * in efx_drv_limits_t so that they can be taken into account
2322 * when allocating extra VIs for PIO writes.
2326 /* UC mapped memory BAR region for VI registers */
2327 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2328 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2331 case EFX_REGION_PIO_WRITE_VI:
2332 /* WC mapped memory BAR region for piobuf writes */
2333 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2334 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2345 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2350 __checkReturn boolean_t
2351 ef10_nic_hw_unavailable(
2352 __in efx_nic_t *enp)
2356 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
2359 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE);
2360 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
2366 ef10_nic_set_hw_unavailable(enp);
2372 ef10_nic_set_hw_unavailable(
2373 __in efx_nic_t *enp)
2375 EFSYS_PROBE(hw_unavail);
2376 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
2382 __in efx_nic_t *enp)
2387 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2388 enp->en_vport_id = 0;
2390 /* Unlink piobufs from extra VIs in WC mapping */
2391 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2392 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2393 rc = efx_mcdi_unlink_piobuf(enp,
2394 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2400 ef10_nic_free_piobufs(enp);
2402 (void) efx_mcdi_free_vis(enp);
2403 enp->en_arch.ef10.ena_vi_count = 0;
2408 __in efx_nic_t *enp)
2410 #if EFSYS_OPT_MON_STATS
2411 mcdi_mon_cfg_free(enp);
2412 #endif /* EFSYS_OPT_MON_STATS */
2413 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2418 __checkReturn efx_rc_t
2419 ef10_nic_register_test(
2420 __in efx_nic_t *enp)
2425 _NOTE(ARGUNUSED(enp))
2426 _NOTE(CONSTANTCONDITION)
2436 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2441 #endif /* EFSYS_OPT_DIAG */
2443 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2445 __checkReturn efx_rc_t
2446 efx_mcdi_get_nic_global(
2447 __in efx_nic_t *enp,
2449 __out uint32_t *valuep)
2452 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2453 MC_CMD_GET_NIC_GLOBAL_OUT_LEN);
2456 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2457 req.emr_in_buf = payload;
2458 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2459 req.emr_out_buf = payload;
2460 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2462 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2464 efx_mcdi_execute(enp, &req);
2466 if (req.emr_rc != 0) {
2471 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2476 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2483 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2488 __checkReturn efx_rc_t
2489 efx_mcdi_set_nic_global(
2490 __in efx_nic_t *enp,
2492 __in uint32_t value)
2495 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0);
2498 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2499 req.emr_in_buf = payload;
2500 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2501 req.emr_out_buf = NULL;
2502 req.emr_out_length = 0;
2504 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2505 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2507 efx_mcdi_execute(enp, &req);
2509 if (req.emr_rc != 0) {
2517 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2522 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2524 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */