1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
27 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
28 enp->en_family == EFX_FAMILY_MEDFORD ||
29 enp->en_family == EFX_FAMILY_MEDFORD2);
31 (void) memset(payload, 0, sizeof (payload));
32 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
33 req.emr_in_buf = payload;
34 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
35 req.emr_out_buf = payload;
36 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
38 efx_mcdi_execute(enp, &req);
40 if (req.emr_rc != 0) {
45 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
50 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
57 EFSYS_PROBE1(fail1, efx_rc_t, rc);
62 __checkReturn efx_rc_t
63 efx_mcdi_get_port_modes(
65 __out uint32_t *modesp,
66 __out_opt uint32_t *current_modep)
69 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
70 MC_CMD_GET_PORT_MODES_OUT_LEN)];
73 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
74 enp->en_family == EFX_FAMILY_MEDFORD ||
75 enp->en_family == EFX_FAMILY_MEDFORD2);
77 (void) memset(payload, 0, sizeof (payload));
78 req.emr_cmd = MC_CMD_GET_PORT_MODES;
79 req.emr_in_buf = payload;
80 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
81 req.emr_out_buf = payload;
82 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
84 efx_mcdi_execute(enp, &req);
86 if (req.emr_rc != 0) {
92 * Require only Modes and DefaultMode fields, unless the current mode
93 * was requested (CurrentMode field was added for Medford).
95 if (req.emr_out_length_used <
96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
100 if ((current_modep != NULL) && (req.emr_out_length_used <
101 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
106 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
108 if (current_modep != NULL) {
109 *current_modep = MCDI_OUT_DWORD(req,
110 GET_PORT_MODES_OUT_CURRENT_MODE);
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
125 __checkReturn efx_rc_t
126 ef10_nic_get_port_mode_bandwidth(
127 __in uint32_t port_mode,
128 __out uint32_t *bandwidth_mbpsp)
134 case TLV_PORT_MODE_10G:
137 case TLV_PORT_MODE_10G_10G:
138 bandwidth = 10000 * 2;
140 case TLV_PORT_MODE_10G_10G_10G_10G:
141 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
142 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
143 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
144 bandwidth = 10000 * 4;
146 case TLV_PORT_MODE_40G:
149 case TLV_PORT_MODE_40G_40G:
150 bandwidth = 40000 * 2;
152 case TLV_PORT_MODE_40G_10G_10G:
153 case TLV_PORT_MODE_10G_10G_40G:
154 bandwidth = 40000 + (10000 * 2);
161 *bandwidth_mbpsp = bandwidth;
166 EFSYS_PROBE1(fail1, efx_rc_t, rc);
171 static __checkReturn efx_rc_t
172 efx_mcdi_vadaptor_alloc(
174 __in uint32_t port_id)
177 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
178 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
181 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
183 (void) memset(payload, 0, sizeof (payload));
184 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
185 req.emr_in_buf = payload;
186 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
187 req.emr_out_buf = payload;
188 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
190 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
191 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
192 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
193 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
195 efx_mcdi_execute(enp, &req);
197 if (req.emr_rc != 0) {
205 EFSYS_PROBE1(fail1, efx_rc_t, rc);
210 static __checkReturn efx_rc_t
211 efx_mcdi_vadaptor_free(
213 __in uint32_t port_id)
216 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
217 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
220 (void) memset(payload, 0, sizeof (payload));
221 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
222 req.emr_in_buf = payload;
223 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
224 req.emr_out_buf = payload;
225 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
227 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
229 efx_mcdi_execute(enp, &req);
231 if (req.emr_rc != 0) {
239 EFSYS_PROBE1(fail1, efx_rc_t, rc);
244 __checkReturn efx_rc_t
245 efx_mcdi_get_mac_address_pf(
247 __out_ecount_opt(6) uint8_t mac_addrp[6])
250 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
251 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
254 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
255 enp->en_family == EFX_FAMILY_MEDFORD ||
256 enp->en_family == EFX_FAMILY_MEDFORD2);
258 (void) memset(payload, 0, sizeof (payload));
259 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
260 req.emr_in_buf = payload;
261 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
262 req.emr_out_buf = payload;
263 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
265 efx_mcdi_execute(enp, &req);
267 if (req.emr_rc != 0) {
272 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
277 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
282 if (mac_addrp != NULL) {
285 addrp = MCDI_OUT2(req, uint8_t,
286 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
288 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
298 EFSYS_PROBE1(fail1, efx_rc_t, rc);
303 __checkReturn efx_rc_t
304 efx_mcdi_get_mac_address_vf(
306 __out_ecount_opt(6) uint8_t mac_addrp[6])
309 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
310 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
313 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
314 enp->en_family == EFX_FAMILY_MEDFORD ||
315 enp->en_family == EFX_FAMILY_MEDFORD2);
317 (void) memset(payload, 0, sizeof (payload));
318 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
319 req.emr_in_buf = payload;
320 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
321 req.emr_out_buf = payload;
322 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
324 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
325 EVB_PORT_ID_ASSIGNED);
327 efx_mcdi_execute(enp, &req);
329 if (req.emr_rc != 0) {
334 if (req.emr_out_length_used <
335 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
340 if (MCDI_OUT_DWORD(req,
341 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
346 if (mac_addrp != NULL) {
349 addrp = MCDI_OUT2(req, uint8_t,
350 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
352 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
362 EFSYS_PROBE1(fail1, efx_rc_t, rc);
367 __checkReturn efx_rc_t
370 __out uint32_t *sys_freqp,
371 __out uint32_t *dpcpu_freqp)
374 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
375 MC_CMD_GET_CLOCK_OUT_LEN)];
378 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
379 enp->en_family == EFX_FAMILY_MEDFORD ||
380 enp->en_family == EFX_FAMILY_MEDFORD2);
382 (void) memset(payload, 0, sizeof (payload));
383 req.emr_cmd = MC_CMD_GET_CLOCK;
384 req.emr_in_buf = payload;
385 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
386 req.emr_out_buf = payload;
387 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
389 efx_mcdi_execute(enp, &req);
391 if (req.emr_rc != 0) {
396 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
401 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
402 if (*sys_freqp == 0) {
406 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
407 if (*dpcpu_freqp == 0) {
421 EFSYS_PROBE1(fail1, efx_rc_t, rc);
426 __checkReturn efx_rc_t
427 efx_mcdi_get_vector_cfg(
429 __out_opt uint32_t *vec_basep,
430 __out_opt uint32_t *pf_nvecp,
431 __out_opt uint32_t *vf_nvecp)
434 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
435 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
438 (void) memset(payload, 0, sizeof (payload));
439 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
440 req.emr_in_buf = payload;
441 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
442 req.emr_out_buf = payload;
443 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
445 efx_mcdi_execute(enp, &req);
447 if (req.emr_rc != 0) {
452 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
457 if (vec_basep != NULL)
458 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
459 if (pf_nvecp != NULL)
460 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
461 if (vf_nvecp != NULL)
462 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
469 EFSYS_PROBE1(fail1, efx_rc_t, rc);
474 static __checkReturn efx_rc_t
477 __in uint32_t min_vi_count,
478 __in uint32_t max_vi_count,
479 __out uint32_t *vi_basep,
480 __out uint32_t *vi_countp,
481 __out uint32_t *vi_shiftp)
484 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
485 MC_CMD_ALLOC_VIS_EXT_OUT_LEN)];
488 if (vi_countp == NULL) {
493 (void) memset(payload, 0, sizeof (payload));
494 req.emr_cmd = MC_CMD_ALLOC_VIS;
495 req.emr_in_buf = payload;
496 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
497 req.emr_out_buf = payload;
498 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
500 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
501 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
503 efx_mcdi_execute(enp, &req);
505 if (req.emr_rc != 0) {
510 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
515 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
516 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
518 /* Report VI_SHIFT if available (always zero for Huntington) */
519 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
522 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
531 EFSYS_PROBE1(fail1, efx_rc_t, rc);
537 static __checkReturn efx_rc_t
544 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
545 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
547 req.emr_cmd = MC_CMD_FREE_VIS;
548 req.emr_in_buf = NULL;
549 req.emr_in_length = 0;
550 req.emr_out_buf = NULL;
551 req.emr_out_length = 0;
553 efx_mcdi_execute_quiet(enp, &req);
555 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
556 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
564 EFSYS_PROBE1(fail1, efx_rc_t, rc);
570 static __checkReturn efx_rc_t
571 efx_mcdi_alloc_piobuf(
573 __out efx_piobuf_handle_t *handlep)
576 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
577 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
580 if (handlep == NULL) {
585 (void) memset(payload, 0, sizeof (payload));
586 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
587 req.emr_in_buf = payload;
588 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
589 req.emr_out_buf = payload;
590 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
592 efx_mcdi_execute_quiet(enp, &req);
594 if (req.emr_rc != 0) {
599 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
604 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
613 EFSYS_PROBE1(fail1, efx_rc_t, rc);
618 static __checkReturn efx_rc_t
619 efx_mcdi_free_piobuf(
621 __in efx_piobuf_handle_t handle)
624 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
625 MC_CMD_FREE_PIOBUF_OUT_LEN)];
628 (void) memset(payload, 0, sizeof (payload));
629 req.emr_cmd = MC_CMD_FREE_PIOBUF;
630 req.emr_in_buf = payload;
631 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
632 req.emr_out_buf = payload;
633 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
635 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
637 efx_mcdi_execute_quiet(enp, &req);
639 if (req.emr_rc != 0) {
647 EFSYS_PROBE1(fail1, efx_rc_t, rc);
652 static __checkReturn efx_rc_t
653 efx_mcdi_link_piobuf(
655 __in uint32_t vi_index,
656 __in efx_piobuf_handle_t handle)
659 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
660 MC_CMD_LINK_PIOBUF_OUT_LEN)];
663 (void) memset(payload, 0, sizeof (payload));
664 req.emr_cmd = MC_CMD_LINK_PIOBUF;
665 req.emr_in_buf = payload;
666 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
667 req.emr_out_buf = payload;
668 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
670 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
671 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
673 efx_mcdi_execute(enp, &req);
675 if (req.emr_rc != 0) {
683 EFSYS_PROBE1(fail1, efx_rc_t, rc);
688 static __checkReturn efx_rc_t
689 efx_mcdi_unlink_piobuf(
691 __in uint32_t vi_index)
694 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
695 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
698 (void) memset(payload, 0, sizeof (payload));
699 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
700 req.emr_in_buf = payload;
701 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
702 req.emr_out_buf = payload;
703 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
705 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
707 efx_mcdi_execute_quiet(enp, &req);
709 if (req.emr_rc != 0) {
717 EFSYS_PROBE1(fail1, efx_rc_t, rc);
723 ef10_nic_alloc_piobufs(
725 __in uint32_t max_piobuf_count)
727 efx_piobuf_handle_t *handlep;
730 EFSYS_ASSERT3U(max_piobuf_count, <=,
731 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
733 enp->en_arch.ef10.ena_piobuf_count = 0;
735 for (i = 0; i < max_piobuf_count; i++) {
736 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
738 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
741 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
742 enp->en_arch.ef10.ena_piobuf_count++;
748 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
749 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
751 efx_mcdi_free_piobuf(enp, *handlep);
752 *handlep = EFX_PIOBUF_HANDLE_INVALID;
754 enp->en_arch.ef10.ena_piobuf_count = 0;
759 ef10_nic_free_piobufs(
762 efx_piobuf_handle_t *handlep;
765 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
766 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
768 efx_mcdi_free_piobuf(enp, *handlep);
769 *handlep = EFX_PIOBUF_HANDLE_INVALID;
771 enp->en_arch.ef10.ena_piobuf_count = 0;
774 /* Sub-allocate a block from a piobuf */
775 __checkReturn efx_rc_t
777 __inout efx_nic_t *enp,
778 __out uint32_t *bufnump,
779 __out efx_piobuf_handle_t *handlep,
780 __out uint32_t *blknump,
781 __out uint32_t *offsetp,
784 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
785 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
786 uint32_t blk_per_buf;
790 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
791 enp->en_family == EFX_FAMILY_MEDFORD ||
792 enp->en_family == EFX_FAMILY_MEDFORD2);
793 EFSYS_ASSERT(bufnump);
794 EFSYS_ASSERT(handlep);
795 EFSYS_ASSERT(blknump);
796 EFSYS_ASSERT(offsetp);
799 if ((edcp->edc_pio_alloc_size == 0) ||
800 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
804 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
806 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
807 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
812 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
813 for (blk = 0; blk < blk_per_buf; blk++) {
814 if ((*map & (1u << blk)) == 0) {
824 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
827 *sizep = edcp->edc_pio_alloc_size;
828 *offsetp = blk * (*sizep);
835 EFSYS_PROBE1(fail1, efx_rc_t, rc);
840 /* Free a piobuf sub-allocated block */
841 __checkReturn efx_rc_t
843 __inout efx_nic_t *enp,
844 __in uint32_t bufnum,
845 __in uint32_t blknum)
850 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
851 (blknum >= (8 * sizeof (*map)))) {
856 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
857 if ((*map & (1u << blknum)) == 0) {
861 *map &= ~(1u << blknum);
868 EFSYS_PROBE1(fail1, efx_rc_t, rc);
873 __checkReturn efx_rc_t
875 __inout efx_nic_t *enp,
876 __in uint32_t vi_index,
877 __in efx_piobuf_handle_t handle)
879 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
882 __checkReturn efx_rc_t
884 __inout efx_nic_t *enp,
885 __in uint32_t vi_index)
887 return (efx_mcdi_unlink_piobuf(enp, vi_index));
890 static __checkReturn efx_rc_t
891 ef10_mcdi_get_pf_count(
893 __out uint32_t *pf_countp)
896 uint8_t payload[MAX(MC_CMD_GET_PF_COUNT_IN_LEN,
897 MC_CMD_GET_PF_COUNT_OUT_LEN)];
900 (void) memset(payload, 0, sizeof (payload));
901 req.emr_cmd = MC_CMD_GET_PF_COUNT;
902 req.emr_in_buf = payload;
903 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
904 req.emr_out_buf = payload;
905 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
907 efx_mcdi_execute(enp, &req);
909 if (req.emr_rc != 0) {
914 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
919 *pf_countp = *MCDI_OUT(req, uint8_t,
920 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
922 EFSYS_ASSERT(*pf_countp != 0);
929 EFSYS_PROBE1(fail1, efx_rc_t, rc);
934 __checkReturn efx_rc_t
935 ef10_get_datapath_caps(
938 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
944 if ((rc = efx_mcdi_get_capabilities(enp, &flags, NULL, NULL,
945 &flags2, &tso2nc)) != 0)
948 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
951 #define CAP_FLAG(flags1, field) \
952 ((flags1) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
954 #define CAP_FLAG2(flags2, field) \
955 ((flags2) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
958 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
959 * We only support the 14 byte prefix here.
961 if (CAP_FLAG(flags, RX_PREFIX_LEN_14) == 0) {
965 encp->enc_rx_prefix_size = 14;
967 /* Check if the firmware supports TSO */
968 encp->enc_fw_assisted_tso_enabled =
969 CAP_FLAG(flags, TX_TSO) ? B_TRUE : B_FALSE;
971 /* Check if the firmware supports FATSOv2 */
972 encp->enc_fw_assisted_tso_v2_enabled =
973 CAP_FLAG2(flags2, TX_TSO_V2) ? B_TRUE : B_FALSE;
975 /* Get the number of TSO contexts (FATSOv2) */
976 encp->enc_fw_assisted_tso_v2_n_contexts =
977 CAP_FLAG2(flags2, TX_TSO_V2) ? tso2nc : 0;
979 /* Check if the firmware has vadapter/vport/vswitch support */
980 encp->enc_datapath_cap_evb =
981 CAP_FLAG(flags, EVB) ? B_TRUE : B_FALSE;
983 /* Check if the firmware supports VLAN insertion */
984 encp->enc_hw_tx_insert_vlan_enabled =
985 CAP_FLAG(flags, TX_VLAN_INSERTION) ? B_TRUE : B_FALSE;
987 /* Check if the firmware supports RX event batching */
988 encp->enc_rx_batching_enabled =
989 CAP_FLAG(flags, RX_BATCHING) ? B_TRUE : B_FALSE;
992 * Even if batching isn't reported as supported, we may still get
993 * batched events (see bug61153).
995 encp->enc_rx_batch_max = 16;
997 /* Check if the firmware supports disabling scatter on RXQs */
998 encp->enc_rx_disable_scatter_supported =
999 CAP_FLAG(flags, RX_DISABLE_SCATTER) ? B_TRUE : B_FALSE;
1001 /* Check if the firmware supports packed stream mode */
1002 encp->enc_rx_packed_stream_supported =
1003 CAP_FLAG(flags, RX_PACKED_STREAM) ? B_TRUE : B_FALSE;
1006 * Check if the firmware supports configurable buffer sizes
1007 * for packed stream mode (otherwise buffer size is 1Mbyte)
1009 encp->enc_rx_var_packed_stream_supported =
1010 CAP_FLAG(flags, RX_PACKED_STREAM_VAR_BUFFERS) ? B_TRUE : B_FALSE;
1012 /* Check if the firmware supports set mac with running filters */
1013 encp->enc_allow_set_mac_with_installed_filters =
1014 CAP_FLAG(flags, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED) ?
1018 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1019 * specifying which parameters to configure.
1021 encp->enc_enhanced_set_mac_supported =
1022 CAP_FLAG(flags, SET_MAC_ENHANCED) ? B_TRUE : B_FALSE;
1025 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1026 * us to let the firmware choose the settings to use on an EVQ.
1028 encp->enc_init_evq_v2_supported =
1029 CAP_FLAG2(flags2, INIT_EVQ_V2) ? B_TRUE : B_FALSE;
1032 * Check if firmware-verified NVRAM updates must be used.
1034 * The firmware trusted installer requires all NVRAM updates to use
1035 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1036 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1037 * partition and report the result).
1039 encp->enc_nvram_update_verify_result_supported =
1040 CAP_FLAG2(flags2, NVRAM_UPDATE_REPORT_VERIFY_RESULT) ?
1044 * Check if firmware provides packet memory and Rx datapath
1047 encp->enc_pm_and_rxdp_counters =
1048 CAP_FLAG(flags, PM_AND_RXDP_COUNTERS) ? B_TRUE : B_FALSE;
1051 * Check if the 40G MAC hardware is capable of reporting
1052 * statistics for Tx size bins.
1054 encp->enc_mac_stats_40g_tx_size_bins =
1055 CAP_FLAG2(flags2, MAC_STATS_40G_TX_SIZE_BINS) ? B_TRUE : B_FALSE;
1058 * Check if firmware supports VXLAN and NVGRE tunnels.
1059 * The capability indicates Geneve protocol support as well.
1061 if (CAP_FLAG(flags, VXLAN_NVGRE)) {
1062 encp->enc_tunnel_encapsulations_supported =
1063 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1064 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1065 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1067 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1068 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1069 encp->enc_tunnel_config_udp_entries_max =
1070 EFX_TUNNEL_MAXNENTRIES;
1072 encp->enc_tunnel_config_udp_entries_max = 0;
1083 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1089 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1090 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1091 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1092 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1093 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1094 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1095 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1096 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1097 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1098 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1099 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1100 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1102 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1105 __checkReturn efx_rc_t
1106 ef10_get_privilege_mask(
1107 __in efx_nic_t *enp,
1108 __out uint32_t *maskp)
1110 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1114 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1119 /* Fallback for old firmware without privilege mask support */
1120 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1121 /* Assume PF has admin privilege */
1122 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1124 /* VF is always unprivileged by default */
1125 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1134 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1141 * Table of mapping schemes from port number to the number of the external
1142 * connector on the board. The external numbering does not distinguish
1143 * off-board separated outputs such as from multi-headed cables.
1145 * The count of adjacent port numbers that map to each external port
1146 * and the offset in the numbering, is determined by the chip family and
1147 * current port mode.
1149 * For the Huntington family, the current port mode cannot be discovered,
1150 * so the mapping used is instead the last match in the table to the full
1151 * set of port modes to which the NIC can be configured. Therefore the
1152 * ordering of entries in the mapping table is significant.
1155 efx_family_t family;
1156 uint32_t modes_mask;
1159 } __ef10_external_port_mappings[] = {
1160 /* Supported modes with 1 output per external port */
1162 EFX_FAMILY_HUNTINGTON,
1163 (1 << TLV_PORT_MODE_10G) |
1164 (1 << TLV_PORT_MODE_10G_10G) |
1165 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1171 (1 << TLV_PORT_MODE_10G) |
1172 (1 << TLV_PORT_MODE_10G_10G),
1176 /* Supported modes with 2 outputs per external port */
1178 EFX_FAMILY_HUNTINGTON,
1179 (1 << TLV_PORT_MODE_40G) |
1180 (1 << TLV_PORT_MODE_40G_40G) |
1181 (1 << TLV_PORT_MODE_40G_10G_10G) |
1182 (1 << TLV_PORT_MODE_10G_10G_40G),
1188 (1 << TLV_PORT_MODE_40G) |
1189 (1 << TLV_PORT_MODE_40G_40G) |
1190 (1 << TLV_PORT_MODE_40G_10G_10G) |
1191 (1 << TLV_PORT_MODE_10G_10G_40G) |
1192 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
1196 /* Supported modes with 4 outputs per external port */
1199 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1200 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
1206 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1212 __checkReturn efx_rc_t
1213 ef10_external_port_mapping(
1214 __in efx_nic_t *enp,
1216 __out uint8_t *external_portp)
1220 uint32_t port_modes;
1223 int32_t count = 1; /* Default 1-1 mapping */
1224 int32_t offset = 1; /* Default starting external port number */
1226 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t)) != 0) {
1228 * No current port mode information
1229 * - infer mapping from available modes
1231 if ((rc = efx_mcdi_get_port_modes(enp,
1232 &port_modes, NULL)) != 0) {
1234 * No port mode information available
1235 * - use default mapping
1240 /* Only need to scan the current mode */
1241 port_modes = 1 << current;
1245 * Infer the internal port -> external port mapping from
1246 * the possible port modes for this NIC.
1248 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1249 if (__ef10_external_port_mappings[i].family !=
1252 matches = (__ef10_external_port_mappings[i].modes_mask &
1255 count = __ef10_external_port_mappings[i].count;
1256 offset = __ef10_external_port_mappings[i].offset;
1257 port_modes &= ~matches;
1261 if (port_modes != 0) {
1262 /* Some advertised modes are not supported */
1269 * Scale as required by last matched mode and then convert to
1270 * correctly offset numbering
1272 *external_portp = (uint8_t)((port / count) + offset);
1276 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1282 __checkReturn efx_rc_t
1284 __in efx_nic_t *enp)
1286 const efx_nic_ops_t *enop = enp->en_enop;
1287 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1288 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1291 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1292 enp->en_family == EFX_FAMILY_MEDFORD ||
1293 enp->en_family == EFX_FAMILY_MEDFORD2);
1295 /* Read and clear any assertion state */
1296 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1299 /* Exit the assertion handler */
1300 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1304 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1307 if ((rc = enop->eno_board_cfg(enp)) != 0)
1312 * Set default driver config limits (based on board config).
1314 * FIXME: For now allocate a fixed number of VIs which is likely to be
1315 * sufficient and small enough to allow multiple functions on the same
1318 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1319 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1321 /* The client driver must configure and enable PIO buffer support */
1322 edcp->edc_max_piobuf_count = 0;
1323 edcp->edc_pio_alloc_size = 0;
1325 #if EFSYS_OPT_MAC_STATS
1326 /* Wipe the MAC statistics */
1327 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1331 #if EFSYS_OPT_LOOPBACK
1332 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1336 #if EFSYS_OPT_MON_STATS
1337 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1338 /* Unprivileged functions do not have access to sensors */
1344 encp->enc_features = enp->en_features;
1348 #if EFSYS_OPT_MON_STATS
1352 #if EFSYS_OPT_LOOPBACK
1356 #if EFSYS_OPT_MAC_STATS
1367 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1372 __checkReturn efx_rc_t
1373 ef10_nic_set_drv_limits(
1374 __inout efx_nic_t *enp,
1375 __in efx_drv_limits_t *edlp)
1377 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1378 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1379 uint32_t min_evq_count, max_evq_count;
1380 uint32_t min_rxq_count, max_rxq_count;
1381 uint32_t min_txq_count, max_txq_count;
1389 /* Get minimum required and maximum usable VI limits */
1390 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1391 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1392 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1394 edcp->edc_min_vi_count =
1395 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1397 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1398 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1399 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1401 edcp->edc_max_vi_count =
1402 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1405 * Check limits for sub-allocated piobuf blocks.
1406 * PIO is optional, so don't fail if the limits are incorrect.
1408 if ((encp->enc_piobuf_size == 0) ||
1409 (encp->enc_piobuf_limit == 0) ||
1410 (edlp->edl_min_pio_alloc_size == 0) ||
1411 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1413 edcp->edc_max_piobuf_count = 0;
1414 edcp->edc_pio_alloc_size = 0;
1416 uint32_t blk_size, blk_count, blks_per_piobuf;
1419 MAX(edlp->edl_min_pio_alloc_size,
1420 encp->enc_piobuf_min_alloc_size);
1422 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1423 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1425 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1427 /* A zero max pio alloc count means unlimited */
1428 if ((edlp->edl_max_pio_alloc_count > 0) &&
1429 (edlp->edl_max_pio_alloc_count < blk_count)) {
1430 blk_count = edlp->edl_max_pio_alloc_count;
1433 edcp->edc_pio_alloc_size = blk_size;
1434 edcp->edc_max_piobuf_count =
1435 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1441 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1447 __checkReturn efx_rc_t
1449 __in efx_nic_t *enp)
1452 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1453 MC_CMD_ENTITY_RESET_OUT_LEN)];
1456 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1457 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1459 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1462 (void) memset(payload, 0, sizeof (payload));
1463 req.emr_cmd = MC_CMD_ENTITY_RESET;
1464 req.emr_in_buf = payload;
1465 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1466 req.emr_out_buf = payload;
1467 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1469 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1470 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1472 efx_mcdi_execute(enp, &req);
1474 if (req.emr_rc != 0) {
1479 /* Clear RX/TX DMA queue errors */
1480 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1489 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1494 __checkReturn efx_rc_t
1496 __in efx_nic_t *enp)
1498 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1499 uint32_t min_vi_count, max_vi_count;
1500 uint32_t vi_count, vi_base, vi_shift;
1506 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1507 enp->en_family == EFX_FAMILY_MEDFORD ||
1508 enp->en_family == EFX_FAMILY_MEDFORD2);
1510 /* Enable reporting of some events (e.g. link change) */
1511 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1514 /* Allocate (optional) on-chip PIO buffers */
1515 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1518 * For best performance, PIO writes should use a write-combined
1519 * (WC) memory mapping. Using a separate WC mapping for the PIO
1520 * aperture of each VI would be a burden to drivers (and not
1521 * possible if the host page size is >4Kbyte).
1523 * To avoid this we use a single uncached (UC) mapping for VI
1524 * register access, and a single WC mapping for extra VIs used
1527 * Each piobuf must be linked to a VI in the WC mapping, and to
1528 * each VI that is using a sub-allocated block from the piobuf.
1530 min_vi_count = edcp->edc_min_vi_count;
1532 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1534 /* Ensure that the previously attached driver's VIs are freed */
1535 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1539 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1540 * fails then retrying the request for fewer VI resources may succeed.
1543 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1544 &vi_base, &vi_count, &vi_shift)) != 0)
1547 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1549 if (vi_count < min_vi_count) {
1554 enp->en_arch.ef10.ena_vi_base = vi_base;
1555 enp->en_arch.ef10.ena_vi_count = vi_count;
1556 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1558 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1559 /* Not enough extra VIs to map piobufs */
1560 ef10_nic_free_piobufs(enp);
1563 enp->en_arch.ef10.ena_pio_write_vi_base =
1564 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1566 /* Save UC memory mapping details */
1567 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1568 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1569 enp->en_arch.ef10.ena_uc_mem_map_size =
1570 (ER_DZ_TX_PIOBUF_STEP *
1571 enp->en_arch.ef10.ena_pio_write_vi_base);
1573 enp->en_arch.ef10.ena_uc_mem_map_size =
1574 (ER_DZ_TX_PIOBUF_STEP *
1575 enp->en_arch.ef10.ena_vi_count);
1578 /* Save WC memory mapping details */
1579 enp->en_arch.ef10.ena_wc_mem_map_offset =
1580 enp->en_arch.ef10.ena_uc_mem_map_offset +
1581 enp->en_arch.ef10.ena_uc_mem_map_size;
1583 enp->en_arch.ef10.ena_wc_mem_map_size =
1584 (ER_DZ_TX_PIOBUF_STEP *
1585 enp->en_arch.ef10.ena_piobuf_count);
1587 /* Link piobufs to extra VIs in WC mapping */
1588 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1589 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1590 rc = efx_mcdi_link_piobuf(enp,
1591 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1592 enp->en_arch.ef10.ena_piobuf_handle[i]);
1599 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1601 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1602 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1603 * retry the request several times after waiting a while. The wait time
1604 * between retries starts small (10ms) and exponentially increases.
1605 * Total wait time is a little over two seconds. Retry logic in the
1606 * client driver may mean this whole loop is repeated if it continues to
1611 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1612 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1615 * Do not retry alloc for PF, or for other errors on
1621 /* VF startup before PF is ready. Retry allocation. */
1623 /* Too many attempts */
1627 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1628 EFSYS_SLEEP(delay_us);
1630 if (delay_us < 500000)
1634 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1635 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1650 ef10_nic_free_piobufs(enp);
1653 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1658 __checkReturn efx_rc_t
1659 ef10_nic_get_vi_pool(
1660 __in efx_nic_t *enp,
1661 __out uint32_t *vi_countp)
1663 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1664 enp->en_family == EFX_FAMILY_MEDFORD ||
1665 enp->en_family == EFX_FAMILY_MEDFORD2);
1668 * Report VIs that the client driver can use.
1669 * Do not include VIs used for PIO buffer writes.
1671 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1676 __checkReturn efx_rc_t
1677 ef10_nic_get_bar_region(
1678 __in efx_nic_t *enp,
1679 __in efx_nic_region_t region,
1680 __out uint32_t *offsetp,
1681 __out size_t *sizep)
1685 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1686 enp->en_family == EFX_FAMILY_MEDFORD ||
1687 enp->en_family == EFX_FAMILY_MEDFORD2);
1690 * TODO: Specify host memory mapping alignment and granularity
1691 * in efx_drv_limits_t so that they can be taken into account
1692 * when allocating extra VIs for PIO writes.
1696 /* UC mapped memory BAR region for VI registers */
1697 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1698 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1701 case EFX_REGION_PIO_WRITE_VI:
1702 /* WC mapped memory BAR region for piobuf writes */
1703 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1704 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1715 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1722 __in efx_nic_t *enp)
1727 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1728 enp->en_vport_id = 0;
1730 /* Unlink piobufs from extra VIs in WC mapping */
1731 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1732 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1733 rc = efx_mcdi_unlink_piobuf(enp,
1734 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1740 ef10_nic_free_piobufs(enp);
1742 (void) efx_mcdi_free_vis(enp);
1743 enp->en_arch.ef10.ena_vi_count = 0;
1748 __in efx_nic_t *enp)
1750 #if EFSYS_OPT_MON_STATS
1751 mcdi_mon_cfg_free(enp);
1752 #endif /* EFSYS_OPT_MON_STATS */
1753 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1758 __checkReturn efx_rc_t
1759 ef10_nic_register_test(
1760 __in efx_nic_t *enp)
1765 _NOTE(ARGUNUSED(enp))
1766 _NOTE(CONSTANTCONDITION)
1776 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1781 #endif /* EFSYS_OPT_DIAG */
1784 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */