drivers/net/sfc/base/ef10_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2012-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
  12
  13
  14 static  __checkReturn   efx_rc_t
  15 efx_mcdi_init_rxq(
  16         __in            efx_nic_t *enp,
  17         __in            uint32_t ndescs,
  18         __in            efx_evq_t *eep,
  19         __in            uint32_t label,
  20         __in            uint32_t instance,
  21         __in            efsys_mem_t *esmp,
  22         __in            boolean_t disable_scatter,
  23         __in            boolean_t want_inner_classes,
  24         __in            uint32_t ps_bufsize,
  25         __in            uint32_t es_bufs_per_desc,
  26         __in            uint32_t es_max_dma_len,
  27         __in            uint32_t es_buf_stride,
  28         __in            uint32_t hol_block_timeout)
  29 {
  30         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
  31         efx_mcdi_req_t req;
  32         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V3_IN_LEN,
  33                 MC_CMD_INIT_RXQ_V3_OUT_LEN);
  34         int npages = efx_rxq_nbufs(enp, ndescs);
  35         int i;
  36         efx_qword_t *dma_addr;
  37         uint64_t addr;
  38         efx_rc_t rc;
  39         uint32_t dma_mode;
  40         boolean_t want_outer_classes;
  41         boolean_t no_cont_ev;
  42
  43         EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs);
  44
  45         if ((esmp == NULL) ||
  46             (EFSYS_MEM_SIZE(esmp) < efx_rxq_size(enp, ndescs))) {
  47                 rc = EINVAL;
  48                 goto fail1;
  49         }
  50
  51         no_cont_ev = (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV);
  52         if ((no_cont_ev == B_TRUE) && (disable_scatter == B_FALSE)) {
  53                 /* TODO: Support scatter in NO_CONT_EV mode */
  54                 rc = EINVAL;
  55                 goto fail2;
  56         }
  57
  58         if (ps_bufsize > 0)
  59                 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM;
  60         else if (es_bufs_per_desc > 0)
  61                 dma_mode = MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER;
  62         else
  63                 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET;
  64
  65         if (encp->enc_tunnel_encapsulations_supported != 0 &&
  66             !want_inner_classes) {
  67                 /*
  68                  * WANT_OUTER_CLASSES can only be specified on hardware which
  69                  * supports tunnel encapsulation offloads, even though it is
  70                  * effectively the behaviour the hardware gives.
  71                  *
  72                  * Also, on hardware which does support such offloads, older
  73                  * firmware rejects the flag if the offloads are not supported
  74                  * by the current firmware variant, which means this may fail if
  75                  * the capabilities are not updated when the firmware variant
  76                  * changes. This is not an issue on newer firmware, as it was
  77                  * changed in bug 69842 (v6.4.2.1007) to permit this flag to be
  78                  * specified on all firmware variants.
  79                  */
  80                 want_outer_classes = B_TRUE;
  81         } else {
  82                 want_outer_classes = B_FALSE;
  83         }
  84
  85         req.emr_cmd = MC_CMD_INIT_RXQ;
  86         req.emr_in_buf = payload;
  87         req.emr_in_length = MC_CMD_INIT_RXQ_V3_IN_LEN;
  88         req.emr_out_buf = payload;
  89         req.emr_out_length = MC_CMD_INIT_RXQ_V3_OUT_LEN;
  90
  91         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs);
  92         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, eep->ee_index);
  93         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label);
  94         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance);
  95         MCDI_IN_POPULATE_DWORD_10(req, INIT_RXQ_EXT_IN_FLAGS,
  96             INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0,
  97             INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0,
  98             INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0,
  99             INIT_RXQ_EXT_IN_CRC_MODE, 0,
 100             INIT_RXQ_EXT_IN_FLAG_PREFIX, 1,
 101             INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER, disable_scatter,
 102             INIT_RXQ_EXT_IN_DMA_MODE,
 103             dma_mode,
 104             INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, ps_bufsize,
 105             INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes,
 106             INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV, no_cont_ev);
 107         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0);
 108         MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
 109
 110         if (es_bufs_per_desc > 0) {
 111                 MCDI_IN_SET_DWORD(req,
 112                     INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET,
 113                     es_bufs_per_desc);
 114                 MCDI_IN_SET_DWORD(req,
 115                     INIT_RXQ_V3_IN_ES_MAX_DMA_LEN, es_max_dma_len);
 116                 MCDI_IN_SET_DWORD(req,
 117                     INIT_RXQ_V3_IN_ES_PACKET_STRIDE, es_buf_stride);
 118                 MCDI_IN_SET_DWORD(req,
 119                     INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT,
 120                     hol_block_timeout);
 121         }
 122
 123         dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR);
 124         addr = EFSYS_MEM_ADDR(esmp);
 125
 126         for (i = 0; i < npages; i++) {
 127                 EFX_POPULATE_QWORD_2(*dma_addr,
 128                     EFX_DWORD_1, (uint32_t)(addr >> 32),
 129                     EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
 130
 131                 dma_addr++;
 132                 addr += EFX_BUF_SIZE;
 133         }
 134
 135         efx_mcdi_execute(enp, &req);
 136
 137         if (req.emr_rc != 0) {
 138                 rc = req.emr_rc;
 139                 goto fail3;
 140         }
 141
 142         return (0);
 143
 144 fail3:
 145         EFSYS_PROBE(fail3);
 146 fail2:
 147         EFSYS_PROBE(fail2);
 148 fail1:
 149         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 150
 151         return (rc);
 152 }
 153
 154 static  __checkReturn   efx_rc_t
 155 efx_mcdi_fini_rxq(
 156         __in            efx_nic_t *enp,
 157         __in            uint32_t instance)
 158 {
 159         efx_mcdi_req_t req;
 160         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_RXQ_IN_LEN,
 161                 MC_CMD_FINI_RXQ_OUT_LEN);
 162         efx_rc_t rc;
 163
 164         req.emr_cmd = MC_CMD_FINI_RXQ;
 165         req.emr_in_buf = payload;
 166         req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN;
 167         req.emr_out_buf = payload;
 168         req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN;
 169
 170         MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance);
 171
 172         efx_mcdi_execute_quiet(enp, &req);
 173
 174         if (req.emr_rc != 0) {
 175                 rc = req.emr_rc;
 176                 goto fail1;
 177         }
 178
 179         return (0);
 180
 181 fail1:
 182         /*
 183          * EALREADY is not an error, but indicates that the MC has rebooted and
 184          * that the RXQ has already been destroyed.
 185          */
 186         if (rc != EALREADY)
 187                 EFSYS_PROBE1(fail1, efx_rc_t, rc);
 188
 189         return (rc);
 190 }
 191
 192 #if EFSYS_OPT_RX_SCALE
 193 static  __checkReturn   efx_rc_t
 194 efx_mcdi_rss_context_alloc(
 195         __in            efx_nic_t *enp,
 196         __in            efx_rx_scale_context_type_t type,
 197         __in            uint32_t num_queues,
 198         __out           uint32_t *rss_contextp)
 199 {
 200         efx_mcdi_req_t req;
 201         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN,
 202                 MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
 203         uint32_t rss_context;
 204         uint32_t context_type;
 205         efx_rc_t rc;
 206
 207         if (num_queues > EFX_MAXRSS) {
 208                 rc = EINVAL;
 209                 goto fail1;
 210         }
 211
 212         switch (type) {
 213         case EFX_RX_SCALE_EXCLUSIVE:
 214                 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE;
 215                 break;
 216         case EFX_RX_SCALE_SHARED:
 217                 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
 218                 break;
 219         default:
 220                 rc = EINVAL;
 221                 goto fail2;
 222         }
 223
 224         req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC;
 225         req.emr_in_buf = payload;
 226         req.emr_in_length = MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN;
 227         req.emr_out_buf = payload;
 228         req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN;
 229
 230         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
 231             EVB_PORT_ID_ASSIGNED);
 232         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
 233
 234         /*
 235          * For exclusive contexts, NUM_QUEUES is only used to validate
 236          * indirection table offsets.
 237          * For shared contexts, the provided context will spread traffic over
 238          * NUM_QUEUES many queues.
 239          */
 240         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
 241
 242         efx_mcdi_execute(enp, &req);
 243
 244         if (req.emr_rc != 0) {
 245                 rc = req.emr_rc;
 246                 goto fail3;
 247         }
 248
 249         if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) {
 250                 rc = EMSGSIZE;
 251                 goto fail4;
 252         }
 253
 254         rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
 255         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 256                 rc = ENOENT;
 257                 goto fail5;
 258         }
 259
 260         *rss_contextp = rss_context;
 261
 262         return (0);
 263
 264 fail5:
 265         EFSYS_PROBE(fail5);
 266 fail4:
 267         EFSYS_PROBE(fail4);
 268 fail3:
 269         EFSYS_PROBE(fail3);
 270 fail2:
 271         EFSYS_PROBE(fail2);
 272 fail1:
 273         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 274
 275         return (rc);
 276 }
 277 #endif /* EFSYS_OPT_RX_SCALE */
 278
 279 #if EFSYS_OPT_RX_SCALE
 280 static                  efx_rc_t
 281 efx_mcdi_rss_context_free(
 282         __in            efx_nic_t *enp,
 283         __in            uint32_t rss_context)
 284 {
 285         efx_mcdi_req_t req;
 286         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_FREE_IN_LEN,
 287                 MC_CMD_RSS_CONTEXT_FREE_OUT_LEN);
 288         efx_rc_t rc;
 289
 290         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 291                 rc = EINVAL;
 292                 goto fail1;
 293         }
 294
 295         req.emr_cmd = MC_CMD_RSS_CONTEXT_FREE;
 296         req.emr_in_buf = payload;
 297         req.emr_in_length = MC_CMD_RSS_CONTEXT_FREE_IN_LEN;
 298         req.emr_out_buf = payload;
 299         req.emr_out_length = MC_CMD_RSS_CONTEXT_FREE_OUT_LEN;
 300
 301         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, rss_context);
 302
 303         efx_mcdi_execute_quiet(enp, &req);
 304
 305         if (req.emr_rc != 0) {
 306                 rc = req.emr_rc;
 307                 goto fail2;
 308         }
 309
 310         return (0);
 311
 312 fail2:
 313         EFSYS_PROBE(fail2);
 314 fail1:
 315         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 316
 317         return (rc);
 318 }
 319 #endif /* EFSYS_OPT_RX_SCALE */
 320
 321 #if EFSYS_OPT_RX_SCALE
 322 static                  efx_rc_t
 323 efx_mcdi_rss_context_set_flags(
 324         __in            efx_nic_t *enp,
 325         __in            uint32_t rss_context,
 326         __in            efx_rx_hash_type_t type)
 327 {
 328         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 329         efx_mcdi_req_t req;
 330         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN,
 331                 MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN);
 332         efx_rc_t rc;
 333
 334         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN ==
 335                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN);
 336         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH ==
 337                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH);
 338         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN ==
 339                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN);
 340         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH ==
 341                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH);
 342         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN ==
 343                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN);
 344         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH ==
 345                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH);
 346         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN ==
 347                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN);
 348         EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH ==
 349                     MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH);
 350
 351         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 352                 rc = EINVAL;
 353                 goto fail1;
 354         }
 355
 356         req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_FLAGS;
 357         req.emr_in_buf = payload;
 358         req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN;
 359         req.emr_out_buf = payload;
 360         req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN;
 361
 362         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
 363             rss_context);
 364
 365         /*
 366          * If the firmware lacks support for additional modes, RSS_MODE
 367          * fields must contain zeros, otherwise the operation will fail.
 368          */
 369         if (encp->enc_rx_scale_additional_modes_supported == B_FALSE)
 370                 type &= EFX_RX_HASH_LEGACY_MASK;
 371
 372         MCDI_IN_POPULATE_DWORD_10(req, RSS_CONTEXT_SET_FLAGS_IN_FLAGS,
 373             RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN,
 374             (type & EFX_RX_HASH_IPV4) ? 1 : 0,
 375             RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN,
 376             (type & EFX_RX_HASH_TCPIPV4) ? 1 : 0,
 377             RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN,
 378             (type & EFX_RX_HASH_IPV6) ? 1 : 0,
 379             RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN,
 380             (type & EFX_RX_HASH_TCPIPV6) ? 1 : 0,
 381             RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE,
 382             (type >> EFX_RX_CLASS_IPV4_TCP_LBN) &
 383             EFX_MASK32(EFX_RX_CLASS_IPV4_TCP),
 384             RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE,
 385             (type >> EFX_RX_CLASS_IPV4_UDP_LBN) &
 386             EFX_MASK32(EFX_RX_CLASS_IPV4_UDP),
 387             RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE,
 388             (type >> EFX_RX_CLASS_IPV4_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV4),
 389             RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE,
 390             (type >> EFX_RX_CLASS_IPV6_TCP_LBN) &
 391             EFX_MASK32(EFX_RX_CLASS_IPV6_TCP),
 392             RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE,
 393             (type >> EFX_RX_CLASS_IPV6_UDP_LBN) &
 394             EFX_MASK32(EFX_RX_CLASS_IPV6_UDP),
 395             RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE,
 396             (type >> EFX_RX_CLASS_IPV6_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV6));
 397
 398         efx_mcdi_execute(enp, &req);
 399
 400         if (req.emr_rc != 0) {
 401                 rc = req.emr_rc;
 402                 goto fail2;
 403         }
 404
 405         return (0);
 406
 407 fail2:
 408         EFSYS_PROBE(fail2);
 409 fail1:
 410         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 411
 412         return (rc);
 413 }
 414 #endif /* EFSYS_OPT_RX_SCALE */
 415
 416 #if EFSYS_OPT_RX_SCALE
 417 static                  efx_rc_t
 418 efx_mcdi_rss_context_set_key(
 419         __in            efx_nic_t *enp,
 420         __in            uint32_t rss_context,
 421         __in_ecount(n)  uint8_t *key,
 422         __in            size_t n)
 423 {
 424         efx_mcdi_req_t req;
 425         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN,
 426                 MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN);
 427         efx_rc_t rc;
 428
 429         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 430                 rc = EINVAL;
 431                 goto fail1;
 432         }
 433
 434         req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_KEY;
 435         req.emr_in_buf = payload;
 436         req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN;
 437         req.emr_out_buf = payload;
 438         req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN;
 439
 440         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
 441             rss_context);
 442
 443         EFSYS_ASSERT3U(n, ==, MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
 444         if (n != MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN) {
 445                 rc = EINVAL;
 446                 goto fail2;
 447         }
 448
 449         memcpy(MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY),
 450             key, n);
 451
 452         efx_mcdi_execute(enp, &req);
 453
 454         if (req.emr_rc != 0) {
 455                 rc = req.emr_rc;
 456                 goto fail3;
 457         }
 458
 459         return (0);
 460
 461 fail3:
 462         EFSYS_PROBE(fail3);
 463 fail2:
 464         EFSYS_PROBE(fail2);
 465 fail1:
 466         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 467
 468         return (rc);
 469 }
 470 #endif /* EFSYS_OPT_RX_SCALE */
 471
 472 #if EFSYS_OPT_RX_SCALE
 473 static                  efx_rc_t
 474 efx_mcdi_rss_context_set_table(
 475         __in            efx_nic_t *enp,
 476         __in            uint32_t rss_context,
 477         __in_ecount(n)  unsigned int *table,
 478         __in            size_t n)
 479 {
 480         efx_mcdi_req_t req;
 481         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN,
 482                 MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN);
 483         uint8_t *req_table;
 484         int i, rc;
 485
 486         if (rss_context == EF10_RSS_CONTEXT_INVALID) {
 487                 rc = EINVAL;
 488                 goto fail1;
 489         }
 490
 491         req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_TABLE;
 492         req.emr_in_buf = payload;
 493         req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN;
 494         req.emr_out_buf = payload;
 495         req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN;
 496
 497         MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
 498             rss_context);
 499
 500         req_table =
 501             MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE);
 502
 503         for (i = 0;
 504             i < MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN;
 505             i++) {
 506                 req_table[i] = (n > 0) ? (uint8_t)table[i % n] : 0;
 507         }
 508
 509         efx_mcdi_execute(enp, &req);
 510
 511         if (req.emr_rc != 0) {
 512                 rc = req.emr_rc;
 513                 goto fail2;
 514         }
 515
 516         return (0);
 517
 518 fail2:
 519         EFSYS_PROBE(fail2);
 520 fail1:
 521         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 522
 523         return (rc);
 524 }
 525 #endif /* EFSYS_OPT_RX_SCALE */
 526
 527
 528         __checkReturn   efx_rc_t
 529 ef10_rx_init(
 530         __in            efx_nic_t *enp)
 531 {
 532 #if EFSYS_OPT_RX_SCALE
 533
 534         if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS,
 535                 &enp->en_rss_context) == 0) {
 536                 /*
 537                  * Allocated an exclusive RSS context, which allows both the
 538                  * indirection table and key to be modified.
 539                  */
 540                 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
 541                 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
 542         } else {
 543                 /*
 544                  * Failed to allocate an exclusive RSS context. Continue
 545                  * operation without support for RSS. The pseudo-header in
 546                  * received packets will not contain a Toeplitz hash value.
 547                  */
 548                 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
 549                 enp->en_hash_support = EFX_RX_HASH_UNAVAILABLE;
 550         }
 551
 552 #endif /* EFSYS_OPT_RX_SCALE */
 553
 554         return (0);
 555 }
 556
 557 #if EFSYS_OPT_RX_SCATTER
 558         __checkReturn   efx_rc_t
 559 ef10_rx_scatter_enable(
 560         __in            efx_nic_t *enp,
 561         __in            unsigned int buf_size)
 562 {
 563         _NOTE(ARGUNUSED(enp, buf_size))
 564         return (0);
 565 }
 566 #endif  /* EFSYS_OPT_RX_SCATTER */
 567
 568 #if EFSYS_OPT_RX_SCALE
 569         __checkReturn   efx_rc_t
 570 ef10_rx_scale_context_alloc(
 571         __in            efx_nic_t *enp,
 572         __in            efx_rx_scale_context_type_t type,
 573         __in            uint32_t num_queues,
 574         __out           uint32_t *rss_contextp)
 575 {
 576         efx_rc_t rc;
 577
 578         rc = efx_mcdi_rss_context_alloc(enp, type, num_queues, rss_contextp);
 579         if (rc != 0)
 580                 goto fail1;
 581
 582         return (0);
 583
 584 fail1:
 585         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 586         return (rc);
 587 }
 588 #endif /* EFSYS_OPT_RX_SCALE */
 589
 590 #if EFSYS_OPT_RX_SCALE
 591         __checkReturn   efx_rc_t
 592 ef10_rx_scale_context_free(
 593         __in            efx_nic_t *enp,
 594         __in            uint32_t rss_context)
 595 {
 596         efx_rc_t rc;
 597
 598         rc = efx_mcdi_rss_context_free(enp, rss_context);
 599         if (rc != 0)
 600                 goto fail1;
 601
 602         return (0);
 603
 604 fail1:
 605         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 606         return (rc);
 607 }
 608 #endif /* EFSYS_OPT_RX_SCALE */
 609
 610 #if EFSYS_OPT_RX_SCALE
 611         __checkReturn   efx_rc_t
 612 ef10_rx_scale_mode_set(
 613         __in            efx_nic_t *enp,
 614         __in            uint32_t rss_context,
 615         __in            efx_rx_hash_alg_t alg,
 616         __in            efx_rx_hash_type_t type,
 617         __in            boolean_t insert)
 618 {
 619         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 620         efx_rc_t rc;
 621
 622         EFSYS_ASSERT3U(insert, ==, B_TRUE);
 623
 624         if ((encp->enc_rx_scale_hash_alg_mask & (1U << alg)) == 0 ||
 625             insert == B_FALSE) {
 626                 rc = EINVAL;
 627                 goto fail1;
 628         }
 629
 630         if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
 631                 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
 632                         rc = ENOTSUP;
 633                         goto fail2;
 634                 }
 635                 rss_context = enp->en_rss_context;
 636         }
 637
 638         if ((rc = efx_mcdi_rss_context_set_flags(enp,
 639                     rss_context, type)) != 0)
 640                 goto fail3;
 641
 642         return (0);
 643
 644 fail3:
 645         EFSYS_PROBE(fail3);
 646 fail2:
 647         EFSYS_PROBE(fail2);
 648 fail1:
 649         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 650
 651         return (rc);
 652 }
 653 #endif /* EFSYS_OPT_RX_SCALE */
 654
 655 #if EFSYS_OPT_RX_SCALE
 656         __checkReturn   efx_rc_t
 657 ef10_rx_scale_key_set(
 658         __in            efx_nic_t *enp,
 659         __in            uint32_t rss_context,
 660         __in_ecount(n)  uint8_t *key,
 661         __in            size_t n)
 662 {
 663         efx_rc_t rc;
 664
 665         EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
 666             MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
 667
 668         if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
 669                 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
 670                         rc = ENOTSUP;
 671                         goto fail1;
 672                 }
 673                 rss_context = enp->en_rss_context;
 674         }
 675
 676         if ((rc = efx_mcdi_rss_context_set_key(enp, rss_context, key, n)) != 0)
 677                 goto fail2;
 678
 679         return (0);
 680
 681 fail2:
 682         EFSYS_PROBE(fail2);
 683 fail1:
 684         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 685
 686         return (rc);
 687 }
 688 #endif /* EFSYS_OPT_RX_SCALE */
 689
 690 #if EFSYS_OPT_RX_SCALE
 691         __checkReturn   efx_rc_t
 692 ef10_rx_scale_tbl_set(
 693         __in            efx_nic_t *enp,
 694         __in            uint32_t rss_context,
 695         __in_ecount(n)  unsigned int *table,
 696         __in            size_t n)
 697 {
 698         efx_rc_t rc;
 699
 700
 701         if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
 702                 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
 703                         rc = ENOTSUP;
 704                         goto fail1;
 705                 }
 706                 rss_context = enp->en_rss_context;
 707         }
 708
 709         if ((rc = efx_mcdi_rss_context_set_table(enp,
 710                     rss_context, table, n)) != 0)
 711                 goto fail2;
 712
 713         return (0);
 714
 715 fail2:
 716         EFSYS_PROBE(fail2);
 717 fail1:
 718         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 719
 720         return (rc);
 721 }
 722 #endif /* EFSYS_OPT_RX_SCALE */
 723
 724
 725 /*
 726  * EF10 RX pseudo-header
 727  * ---------------------
 728  *
 729  * Receive packets are prefixed by an (optional) 14 byte pseudo-header:
 730  *
 731  *  +00: Toeplitz hash value.
 732  *       (32bit little-endian)
 733  *  +04: Outer VLAN tag. Zero if the packet did not have an outer VLAN tag.
 734  *       (16bit big-endian)
 735  *  +06: Inner VLAN tag. Zero if the packet did not have an inner VLAN tag.
 736  *       (16bit big-endian)
 737  *  +08: Packet Length. Zero if the RX datapath was in cut-through mode.
 738  *       (16bit little-endian)
 739  *  +10: MAC timestamp. Zero if timestamping is not enabled.
 740  *       (32bit little-endian)
 741  *
 742  * See "The RX Pseudo-header" in SF-109306-TC.
 743  */
 744
 745         __checkReturn   efx_rc_t
 746 ef10_rx_prefix_pktlen(
 747         __in            efx_nic_t *enp,
 748         __in            uint8_t *buffer,
 749         __out           uint16_t *lengthp)
 750 {
 751         _NOTE(ARGUNUSED(enp))
 752
 753         /*
 754          * The RX pseudo-header contains the packet length, excluding the
 755          * pseudo-header. If the hardware receive datapath was operating in
 756          * cut-through mode then the length in the RX pseudo-header will be
 757          * zero, and the packet length must be obtained from the DMA length
 758          * reported in the RX event.
 759          */
 760         *lengthp = buffer[8] | (buffer[9] << 8);
 761         return (0);
 762 }
 763
 764 #if EFSYS_OPT_RX_SCALE
 765         __checkReturn   uint32_t
 766 ef10_rx_prefix_hash(
 767         __in            efx_nic_t *enp,
 768         __in            efx_rx_hash_alg_t func,
 769         __in            uint8_t *buffer)
 770 {
 771         _NOTE(ARGUNUSED(enp))
 772
 773         switch (func) {
 774         case EFX_RX_HASHALG_PACKED_STREAM:
 775         case EFX_RX_HASHALG_TOEPLITZ:
 776                 return (buffer[0] |
 777                     (buffer[1] << 8) |
 778                     (buffer[2] << 16) |
 779                     (buffer[3] << 24));
 780
 781         default:
 782                 EFSYS_ASSERT(0);
 783                 return (0);
 784         }
 785 }
 786 #endif /* EFSYS_OPT_RX_SCALE */
 787
 788 #if EFSYS_OPT_RX_PACKED_STREAM
 789 /*
 790  * Fake length for RXQ descriptors in packed stream mode
 791  * to make hardware happy
 792  */
 793 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
 794 #endif
 795
 796                                 void
 797 ef10_rx_qpost(
 798         __in                    efx_rxq_t *erp,
 799         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
 800         __in                    size_t size,
 801         __in                    unsigned int ndescs,
 802         __in                    unsigned int completed,
 803         __in                    unsigned int added)
 804 {
 805         efx_qword_t qword;
 806         unsigned int i;
 807         unsigned int offset;
 808         unsigned int id;
 809
 810         _NOTE(ARGUNUSED(completed))
 811
 812 #if EFSYS_OPT_RX_PACKED_STREAM
 813         /*
 814          * Real size of the buffer does not fit into ESF_DZ_RX_KER_BYTE_CNT
 815          * and equal to 0 after applying mask. Hardware does not like it.
 816          */
 817         if (erp->er_ev_qstate->eers_rx_packed_stream)
 818                 size = EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE;
 819 #endif
 820
 821         /* The client driver must not overfill the queue */
 822         EFSYS_ASSERT3U(added - completed + ndescs, <=,
 823             EFX_RXQ_LIMIT(erp->er_mask + 1));
 824
 825         id = added & (erp->er_mask);
 826         for (i = 0; i < ndescs; i++) {
 827                 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
 828                     unsigned int, id, efsys_dma_addr_t, addrp[i],
 829                     size_t, size);
 830
 831                 EFX_POPULATE_QWORD_3(qword,
 832                     ESF_DZ_RX_KER_BYTE_CNT, (uint32_t)(size),
 833                     ESF_DZ_RX_KER_BUF_ADDR_DW0,
 834                     (uint32_t)(addrp[i] & 0xffffffff),
 835                     ESF_DZ_RX_KER_BUF_ADDR_DW1,
 836                     (uint32_t)(addrp[i] >> 32));
 837
 838                 offset = id * sizeof (efx_qword_t);
 839                 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
 840
 841                 id = (id + 1) & (erp->er_mask);
 842         }
 843 }
 844
 845                         void
 846 ef10_rx_qpush(
 847         __in    efx_rxq_t *erp,
 848         __in    unsigned int added,
 849         __inout unsigned int *pushedp)
 850 {
 851         efx_nic_t *enp = erp->er_enp;
 852         unsigned int pushed = *pushedp;
 853         uint32_t wptr;
 854         efx_dword_t dword;
 855
 856         /* Hardware has alignment restriction for WPTR */
 857         wptr = P2ALIGN(added, EF10_RX_WPTR_ALIGN);
 858         if (pushed == wptr)
 859                 return;
 860
 861         *pushedp = wptr;
 862
 863         /* Push the populated descriptors out */
 864         wptr &= erp->er_mask;
 865
 866         EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, wptr);
 867
 868         /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
 869         EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
 870             wptr, pushed & erp->er_mask);
 871         EFSYS_PIO_WRITE_BARRIER();
 872         EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
 873             erp->er_index, &dword, B_FALSE);
 874 }
 875
 876 #if EFSYS_OPT_RX_PACKED_STREAM
 877
 878                         void
 879 ef10_rx_qpush_ps_credits(
 880         __in            efx_rxq_t *erp)
 881 {
 882         efx_nic_t *enp = erp->er_enp;
 883         efx_dword_t dword;
 884         efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
 885         uint32_t credits;
 886
 887         EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
 888
 889         if (rxq_state->eers_rx_packed_stream_credits == 0)
 890                 return;
 891
 892         /*
 893          * It is a bug if we think that FW has utilized more
 894          * credits than it is allowed to have (maximum). However,
 895          * make sure that we do not credit more than maximum anyway.
 896          */
 897         credits = MIN(rxq_state->eers_rx_packed_stream_credits,
 898             EFX_RX_PACKED_STREAM_MAX_CREDITS);
 899         EFX_POPULATE_DWORD_3(dword,
 900             ERF_DZ_RX_DESC_MAGIC_DOORBELL, 1,
 901             ERF_DZ_RX_DESC_MAGIC_CMD,
 902             ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS,
 903             ERF_DZ_RX_DESC_MAGIC_DATA, credits);
 904         EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
 905             erp->er_index, &dword, B_FALSE);
 906
 907         rxq_state->eers_rx_packed_stream_credits = 0;
 908 }
 909
 910 /*
 911  * In accordance with SF-112241-TC the received data has the following layout:
 912  *  - 8 byte pseudo-header which consist of:
 913  *    - 4 byte little-endian timestamp
 914  *    - 2 byte little-endian captured length in bytes
 915  *    - 2 byte little-endian original packet length in bytes
 916  *  - captured packet bytes
 917  *  - optional padding to align to 64 bytes boundary
 918  *  - 64 bytes scratch space for the host software
 919  */
 920         __checkReturn   uint8_t *
 921 ef10_rx_qps_packet_info(
 922         __in            efx_rxq_t *erp,
 923         __in            uint8_t *buffer,
 924         __in            uint32_t buffer_length,
 925         __in            uint32_t current_offset,
 926         __out           uint16_t *lengthp,
 927         __out           uint32_t *next_offsetp,
 928         __out           uint32_t *timestamp)
 929 {
 930         uint16_t buf_len;
 931         uint8_t *pkt_start;
 932         efx_qword_t *qwordp;
 933         efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
 934
 935         EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
 936
 937         buffer += current_offset;
 938         pkt_start = buffer + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE;
 939
 940         qwordp = (efx_qword_t *)buffer;
 941         *timestamp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_TSTAMP);
 942         *lengthp   = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_ORIG_LEN);
 943         buf_len    = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_CAP_LEN);
 944
 945         buf_len = P2ROUNDUP(buf_len + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE,
 946                             EFX_RX_PACKED_STREAM_ALIGNMENT);
 947         *next_offsetp =
 948             current_offset + buf_len + EFX_RX_PACKED_STREAM_ALIGNMENT;
 949
 950         EFSYS_ASSERT3U(*next_offsetp, <=, buffer_length);
 951         EFSYS_ASSERT3U(current_offset + *lengthp, <, *next_offsetp);
 952
 953         if ((*next_offsetp ^ current_offset) &
 954             EFX_RX_PACKED_STREAM_MEM_PER_CREDIT)
 955                 rxq_state->eers_rx_packed_stream_credits++;
 956
 957         return (pkt_start);
 958 }
 959
 960
 961 #endif
 962
 963         __checkReturn   efx_rc_t
 964 ef10_rx_qflush(
 965         __in    efx_rxq_t *erp)
 966 {
 967         efx_nic_t *enp = erp->er_enp;
 968         efx_rc_t rc;
 969
 970         if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0)
 971                 goto fail1;
 972
 973         return (0);
 974
 975 fail1:
 976         /*
 977          * EALREADY is not an error, but indicates that the MC has rebooted and
 978          * that the RXQ has already been destroyed. Callers need to know that
 979          * the RXQ flush has completed to avoid waiting until timeout for a
 980          * flush done event that will not be delivered.
 981          */
 982         if (rc != EALREADY)
 983                 EFSYS_PROBE1(fail1, efx_rc_t, rc);
 984
 985         return (rc);
 986 }
 987
 988                 void
 989 ef10_rx_qenable(
 990         __in    efx_rxq_t *erp)
 991 {
 992         /* FIXME */
 993         _NOTE(ARGUNUSED(erp))
 994         /* FIXME */
 995 }
 996
 997         __checkReturn   efx_rc_t
 998 ef10_rx_qcreate(
 999         __in            efx_nic_t *enp,
1000         __in            unsigned int index,
1001         __in            unsigned int label,
1002         __in            efx_rxq_type_t type,
1003         __in_opt        const efx_rxq_type_data_t *type_data,
1004         __in            efsys_mem_t *esmp,
1005         __in            size_t ndescs,
1006         __in            uint32_t id,
1007         __in            unsigned int flags,
1008         __in            efx_evq_t *eep,
1009         __in            efx_rxq_t *erp)
1010 {
1011         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1012         efx_rc_t rc;
1013         boolean_t disable_scatter;
1014         boolean_t want_inner_classes;
1015         unsigned int ps_buf_size;
1016         uint32_t es_bufs_per_desc = 0;
1017         uint32_t es_max_dma_len = 0;
1018         uint32_t es_buf_stride = 0;
1019         uint32_t hol_block_timeout = 0;
1020
1021         _NOTE(ARGUNUSED(id, erp, type_data))
1022
1023         EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
1024         EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1025         EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1026
1027         if (index >= encp->enc_rxq_limit) {
1028                 rc = EINVAL;
1029                 goto fail1;
1030         }
1031
1032         switch (type) {
1033         case EFX_RXQ_TYPE_DEFAULT:
1034                 ps_buf_size = 0;
1035                 break;
1036 #if EFSYS_OPT_RX_PACKED_STREAM
1037         case EFX_RXQ_TYPE_PACKED_STREAM:
1038                 if (type_data == NULL) {
1039                         rc = EINVAL;
1040                         goto fail2;
1041                 }
1042                 switch (type_data->ertd_packed_stream.eps_buf_size) {
1043                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M:
1044                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
1045                         break;
1046                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K:
1047                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
1048                         break;
1049                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K:
1050                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
1051                         break;
1052                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K:
1053                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
1054                         break;
1055                 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K:
1056                         ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
1057                         break;
1058                 default:
1059                         rc = ENOTSUP;
1060                         goto fail3;
1061                 }
1062                 break;
1063 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1064 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1065         case EFX_RXQ_TYPE_ES_SUPER_BUFFER:
1066                 if (type_data == NULL) {
1067                         rc = EINVAL;
1068                         goto fail4;
1069                 }
1070                 ps_buf_size = 0;
1071                 es_bufs_per_desc =
1072                     type_data->ertd_es_super_buffer.eessb_bufs_per_desc;
1073                 es_max_dma_len =
1074                     type_data->ertd_es_super_buffer.eessb_max_dma_len;
1075                 es_buf_stride =
1076                     type_data->ertd_es_super_buffer.eessb_buf_stride;
1077                 hol_block_timeout =
1078                     type_data->ertd_es_super_buffer.eessb_hol_block_timeout;
1079                 break;
1080 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1081         default:
1082                 rc = ENOTSUP;
1083                 goto fail5;
1084         }
1085
1086 #if EFSYS_OPT_RX_PACKED_STREAM
1087         if (ps_buf_size != 0) {
1088                 /* Check if datapath firmware supports packed stream mode */
1089                 if (encp->enc_rx_packed_stream_supported == B_FALSE) {
1090                         rc = ENOTSUP;
1091                         goto fail6;
1092                 }
1093                 /* Check if packed stream allows configurable buffer sizes */
1094                 if ((ps_buf_size != MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M) &&
1095                     (encp->enc_rx_var_packed_stream_supported == B_FALSE)) {
1096                         rc = ENOTSUP;
1097                         goto fail7;
1098                 }
1099         }
1100 #else /* EFSYS_OPT_RX_PACKED_STREAM */
1101         EFSYS_ASSERT(ps_buf_size == 0);
1102 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1103
1104 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1105         if (es_bufs_per_desc > 0) {
1106                 if (encp->enc_rx_es_super_buffer_supported == B_FALSE) {
1107                         rc = ENOTSUP;
1108                         goto fail8;
1109                 }
1110                 if (!IS_P2ALIGNED(es_max_dma_len,
1111                             EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1112                         rc = EINVAL;
1113                         goto fail9;
1114                 }
1115                 if (!IS_P2ALIGNED(es_buf_stride,
1116                             EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1117                         rc = EINVAL;
1118                         goto fail10;
1119                 }
1120         }
1121 #else /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1122         EFSYS_ASSERT(es_bufs_per_desc == 0);
1123 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1124
1125         /* Scatter can only be disabled if the firmware supports doing so */
1126         if (flags & EFX_RXQ_FLAG_SCATTER)
1127                 disable_scatter = B_FALSE;
1128         else
1129                 disable_scatter = encp->enc_rx_disable_scatter_supported;
1130
1131         if (flags & EFX_RXQ_FLAG_INNER_CLASSES)
1132                 want_inner_classes = B_TRUE;
1133         else
1134                 want_inner_classes = B_FALSE;
1135
1136         if ((rc = efx_mcdi_init_rxq(enp, ndescs, eep, label, index,
1137                     esmp, disable_scatter, want_inner_classes,
1138                     ps_buf_size, es_bufs_per_desc, es_max_dma_len,
1139                     es_buf_stride, hol_block_timeout)) != 0)
1140                 goto fail11;
1141
1142         erp->er_eep = eep;
1143         erp->er_label = label;
1144
1145         ef10_ev_rxlabel_init(eep, erp, label, type);
1146
1147         erp->er_ev_qstate = &erp->er_eep->ee_rxq_state[label];
1148
1149         return (0);
1150
1151 fail11:
1152         EFSYS_PROBE(fail11);
1153 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1154 fail10:
1155         EFSYS_PROBE(fail10);
1156 fail9:
1157         EFSYS_PROBE(fail9);
1158 fail8:
1159         EFSYS_PROBE(fail8);
1160 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1161 #if EFSYS_OPT_RX_PACKED_STREAM
1162 fail7:
1163         EFSYS_PROBE(fail7);
1164 fail6:
1165         EFSYS_PROBE(fail6);
1166 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1167 fail5:
1168         EFSYS_PROBE(fail5);
1169 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1170 fail4:
1171         EFSYS_PROBE(fail4);
1172 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1173 #if EFSYS_OPT_RX_PACKED_STREAM
1174 fail3:
1175         EFSYS_PROBE(fail3);
1176 fail2:
1177         EFSYS_PROBE(fail2);
1178 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1179 fail1:
1180         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1181
1182         return (rc);
1183 }
1184
1185                 void
1186 ef10_rx_qdestroy(
1187         __in    efx_rxq_t *erp)
1188 {
1189         efx_nic_t *enp = erp->er_enp;
1190         efx_evq_t *eep = erp->er_eep;
1191         unsigned int label = erp->er_label;
1192
1193         ef10_ev_rxlabel_fini(eep, label);
1194
1195         EFSYS_ASSERT(enp->en_rx_qcount != 0);
1196         --enp->en_rx_qcount;
1197
1198         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1199 }
1200
1201                 void
1202 ef10_rx_fini(
1203         __in    efx_nic_t *enp)
1204 {
1205 #if EFSYS_OPT_RX_SCALE
1206         if (enp->en_rss_context_type != EFX_RX_SCALE_UNAVAILABLE)
1207                 (void) efx_mcdi_rss_context_free(enp, enp->en_rss_context);
1208         enp->en_rss_context = 0;
1209         enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
1210 #else
1211         _NOTE(ARGUNUSED(enp))
1212 #endif /* EFSYS_OPT_RX_SCALE */
1213 }
1214
1215 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */