drivers/net/sfc/base/efx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2006-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_H
   8 #define _SYS_EFX_H
   9
  10 #include "efsys.h"
  11 #include "efx_check.h"
  12 #include "efx_phy_ids.h"
  13
  14 #ifdef  __cplusplus
  15 extern "C" {
  16 #endif
  17
  18 #define EFX_STATIC_ASSERT(_cond)                \
  19         ((void)sizeof (char[(_cond) ? 1 : -1]))
  20
  21 #define EFX_ARRAY_SIZE(_array)                  \
  22         (sizeof (_array) / sizeof ((_array)[0]))
  23
  24 #define EFX_FIELD_OFFSET(_type, _field)         \
  25         ((size_t)&(((_type *)0)->_field))
  26
  27 /* The macro expands divider twice */
  28 #define EFX_DIV_ROUND_UP(_n, _d)                (((_n) + (_d) - 1) / (_d))
  29
  30 /* Return codes */
  31
  32 typedef __success(return == 0) int efx_rc_t;
  33
  34
  35 /* Chip families */
  36
  37 typedef enum efx_family_e {
  38         EFX_FAMILY_INVALID,
  39         EFX_FAMILY_FALCON,      /* Obsolete and not supported */
  40         EFX_FAMILY_SIENA,
  41         EFX_FAMILY_HUNTINGTON,
  42         EFX_FAMILY_MEDFORD,
  43         EFX_FAMILY_MEDFORD2,
  44         EFX_FAMILY_NTYPES
  45 } efx_family_t;
  46
  47 extern  __checkReturn   efx_rc_t
  48 efx_family(
  49         __in            uint16_t venid,
  50         __in            uint16_t devid,
  51         __out           efx_family_t *efp,
  52         __out           unsigned int *membarp);
  53
  54
  55 #define EFX_PCI_VENID_SFC                       0x1924
  56
  57 #define EFX_PCI_DEVID_FALCON                    0x0710  /* SFC4000 */
  58
  59 #define EFX_PCI_DEVID_BETHPAGE                  0x0803  /* SFC9020 */
  60 #define EFX_PCI_DEVID_SIENA                     0x0813  /* SFL9021 */
  61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT           0x0810
  62
  63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT      0x0901
  64 #define EFX_PCI_DEVID_FARMINGDALE               0x0903  /* SFC9120 PF */
  65 #define EFX_PCI_DEVID_GREENPORT                 0x0923  /* SFC9140 PF */
  66
  67 #define EFX_PCI_DEVID_FARMINGDALE_VF            0x1903  /* SFC9120 VF */
  68 #define EFX_PCI_DEVID_GREENPORT_VF              0x1923  /* SFC9140 VF */
  69
  70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT         0x0913
  71 #define EFX_PCI_DEVID_MEDFORD                   0x0A03  /* SFC9240 PF */
  72 #define EFX_PCI_DEVID_MEDFORD_VF                0x1A03  /* SFC9240 VF */
  73
  74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT        0x0B13
  75 #define EFX_PCI_DEVID_MEDFORD2                  0x0B03  /* SFC9250 PF */
  76 #define EFX_PCI_DEVID_MEDFORD2_VF               0x1B03  /* SFC9250 VF */
  77
  78
  79 #define EFX_MEM_BAR_SIENA                       2
  80
  81 #define EFX_MEM_BAR_HUNTINGTON_PF               2
  82 #define EFX_MEM_BAR_HUNTINGTON_VF               0
  83
  84 #define EFX_MEM_BAR_MEDFORD_PF                  2
  85 #define EFX_MEM_BAR_MEDFORD_VF                  0
  86
  87 #define EFX_MEM_BAR_MEDFORD2                    0
  88
  89
  90 /* Error codes */
  91
  92 enum {
  93         EFX_ERR_INVALID,
  94         EFX_ERR_SRAM_OOB,
  95         EFX_ERR_BUFID_DC_OOB,
  96         EFX_ERR_MEM_PERR,
  97         EFX_ERR_RBUF_OWN,
  98         EFX_ERR_TBUF_OWN,
  99         EFX_ERR_RDESQ_OWN,
 100         EFX_ERR_TDESQ_OWN,
 101         EFX_ERR_EVQ_OWN,
 102         EFX_ERR_EVFF_OFLO,
 103         EFX_ERR_ILL_ADDR,
 104         EFX_ERR_SRAM_PERR,
 105         EFX_ERR_NCODES
 106 };
 107
 108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
 109 extern  __checkReturn           uint32_t
 110 efx_crc32_calculate(
 111         __in                    uint32_t crc_init,
 112         __in_ecount(length)     uint8_t const *input,
 113         __in                    int length);
 114
 115
 116 /* Type prototypes */
 117
 118 typedef struct efx_rxq_s        efx_rxq_t;
 119
 120 /* NIC */
 121
 122 typedef struct efx_nic_s        efx_nic_t;
 123
 124 extern  __checkReturn   efx_rc_t
 125 efx_nic_create(
 126         __in            efx_family_t family,
 127         __in            efsys_identifier_t *esip,
 128         __in            efsys_bar_t *esbp,
 129         __in            efsys_lock_t *eslp,
 130         __deref_out     efx_nic_t **enpp);
 131
 132 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
 133 typedef enum efx_fw_variant_e {
 134         EFX_FW_VARIANT_FULL_FEATURED,
 135         EFX_FW_VARIANT_LOW_LATENCY,
 136         EFX_FW_VARIANT_PACKED_STREAM,
 137         EFX_FW_VARIANT_HIGH_TX_RATE,
 138         EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
 139         EFX_FW_VARIANT_RULES_ENGINE,
 140         EFX_FW_VARIANT_DPDK,
 141         EFX_FW_VARIANT_DONT_CARE = 0xffffffff
 142 } efx_fw_variant_t;
 143
 144 extern  __checkReturn   efx_rc_t
 145 efx_nic_probe(
 146         __in            efx_nic_t *enp,
 147         __in            efx_fw_variant_t efv);
 148
 149 extern  __checkReturn   efx_rc_t
 150 efx_nic_init(
 151         __in            efx_nic_t *enp);
 152
 153 extern  __checkReturn   efx_rc_t
 154 efx_nic_reset(
 155         __in            efx_nic_t *enp);
 156
 157 #if EFSYS_OPT_DIAG
 158
 159 extern  __checkReturn   efx_rc_t
 160 efx_nic_register_test(
 161         __in            efx_nic_t *enp);
 162
 163 #endif  /* EFSYS_OPT_DIAG */
 164
 165 extern          void
 166 efx_nic_fini(
 167         __in            efx_nic_t *enp);
 168
 169 extern          void
 170 efx_nic_unprobe(
 171         __in            efx_nic_t *enp);
 172
 173 extern          void
 174 efx_nic_destroy(
 175         __in    efx_nic_t *enp);
 176
 177 #define EFX_PCIE_LINK_SPEED_GEN1                1
 178 #define EFX_PCIE_LINK_SPEED_GEN2                2
 179 #define EFX_PCIE_LINK_SPEED_GEN3                3
 180
 181 typedef enum efx_pcie_link_performance_e {
 182         EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
 183         EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
 184         EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
 185         EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
 186 } efx_pcie_link_performance_t;
 187
 188 extern  __checkReturn   efx_rc_t
 189 efx_nic_calculate_pcie_link_bandwidth(
 190         __in            uint32_t pcie_link_width,
 191         __in            uint32_t pcie_link_gen,
 192         __out           uint32_t *bandwidth_mbpsp);
 193
 194 extern  __checkReturn   efx_rc_t
 195 efx_nic_check_pcie_link_speed(
 196         __in            efx_nic_t *enp,
 197         __in            uint32_t pcie_link_width,
 198         __in            uint32_t pcie_link_gen,
 199         __out           efx_pcie_link_performance_t *resultp);
 200
 201 #if EFSYS_OPT_MCDI
 202
 203 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 204 /* Huntington and Medford require MCDIv2 commands */
 205 #define WITH_MCDI_V2 1
 206 #endif
 207
 208 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
 209
 210 typedef enum efx_mcdi_exception_e {
 211         EFX_MCDI_EXCEPTION_MC_REBOOT,
 212         EFX_MCDI_EXCEPTION_MC_BADASSERT,
 213 } efx_mcdi_exception_t;
 214
 215 #if EFSYS_OPT_MCDI_LOGGING
 216 typedef enum efx_log_msg_e {
 217         EFX_LOG_INVALID,
 218         EFX_LOG_MCDI_REQUEST,
 219         EFX_LOG_MCDI_RESPONSE,
 220 } efx_log_msg_t;
 221 #endif /* EFSYS_OPT_MCDI_LOGGING */
 222
 223 typedef struct efx_mcdi_transport_s {
 224         void            *emt_context;
 225         efsys_mem_t     *emt_dma_mem;
 226         void            (*emt_execute)(void *, efx_mcdi_req_t *);
 227         void            (*emt_ev_cpl)(void *);
 228         void            (*emt_exception)(void *, efx_mcdi_exception_t);
 229 #if EFSYS_OPT_MCDI_LOGGING
 230         void            (*emt_logger)(void *, efx_log_msg_t,
 231                                         void *, size_t, void *, size_t);
 232 #endif /* EFSYS_OPT_MCDI_LOGGING */
 233 #if EFSYS_OPT_MCDI_PROXY_AUTH
 234         void            (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
 235 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
 236 } efx_mcdi_transport_t;
 237
 238 extern  __checkReturn   efx_rc_t
 239 efx_mcdi_init(
 240         __in            efx_nic_t *enp,
 241         __in            const efx_mcdi_transport_t *mtp);
 242
 243 extern  __checkReturn   efx_rc_t
 244 efx_mcdi_reboot(
 245         __in            efx_nic_t *enp);
 246
 247                         void
 248 efx_mcdi_new_epoch(
 249         __in            efx_nic_t *enp);
 250
 251 extern                  void
 252 efx_mcdi_get_timeout(
 253         __in            efx_nic_t *enp,
 254         __in            efx_mcdi_req_t *emrp,
 255         __out           uint32_t *usec_timeoutp);
 256
 257 extern                  void
 258 efx_mcdi_request_start(
 259         __in            efx_nic_t *enp,
 260         __in            efx_mcdi_req_t *emrp,
 261         __in            boolean_t ev_cpl);
 262
 263 extern  __checkReturn   boolean_t
 264 efx_mcdi_request_poll(
 265         __in            efx_nic_t *enp);
 266
 267 extern  __checkReturn   boolean_t
 268 efx_mcdi_request_abort(
 269         __in            efx_nic_t *enp);
 270
 271 extern                  void
 272 efx_mcdi_fini(
 273         __in            efx_nic_t *enp);
 274
 275 #endif  /* EFSYS_OPT_MCDI */
 276
 277 /* INTR */
 278
 279 #define EFX_NINTR_SIENA 1024
 280
 281 typedef enum efx_intr_type_e {
 282         EFX_INTR_INVALID = 0,
 283         EFX_INTR_LINE,
 284         EFX_INTR_MESSAGE,
 285         EFX_INTR_NTYPES
 286 } efx_intr_type_t;
 287
 288 #define EFX_INTR_SIZE   (sizeof (efx_oword_t))
 289
 290 extern  __checkReturn   efx_rc_t
 291 efx_intr_init(
 292         __in            efx_nic_t *enp,
 293         __in            efx_intr_type_t type,
 294         __in            efsys_mem_t *esmp);
 295
 296 extern                  void
 297 efx_intr_enable(
 298         __in            efx_nic_t *enp);
 299
 300 extern                  void
 301 efx_intr_disable(
 302         __in            efx_nic_t *enp);
 303
 304 extern                  void
 305 efx_intr_disable_unlocked(
 306         __in            efx_nic_t *enp);
 307
 308 #define EFX_INTR_NEVQS  32
 309
 310 extern  __checkReturn   efx_rc_t
 311 efx_intr_trigger(
 312         __in            efx_nic_t *enp,
 313         __in            unsigned int level);
 314
 315 extern                  void
 316 efx_intr_status_line(
 317         __in            efx_nic_t *enp,
 318         __out           boolean_t *fatalp,
 319         __out           uint32_t *maskp);
 320
 321 extern                  void
 322 efx_intr_status_message(
 323         __in            efx_nic_t *enp,
 324         __in            unsigned int message,
 325         __out           boolean_t *fatalp);
 326
 327 extern                  void
 328 efx_intr_fatal(
 329         __in            efx_nic_t *enp);
 330
 331 extern                  void
 332 efx_intr_fini(
 333         __in            efx_nic_t *enp);
 334
 335 /* MAC */
 336
 337 #if EFSYS_OPT_MAC_STATS
 338
 339 /* START MKCONFIG GENERATED EfxHeaderMacBlock 7d59c0d68431a5d1 */
 340 typedef enum efx_mac_stat_e {
 341         EFX_MAC_RX_OCTETS,
 342         EFX_MAC_RX_PKTS,
 343         EFX_MAC_RX_UNICST_PKTS,
 344         EFX_MAC_RX_MULTICST_PKTS,
 345         EFX_MAC_RX_BRDCST_PKTS,
 346         EFX_MAC_RX_PAUSE_PKTS,
 347         EFX_MAC_RX_LE_64_PKTS,
 348         EFX_MAC_RX_65_TO_127_PKTS,
 349         EFX_MAC_RX_128_TO_255_PKTS,
 350         EFX_MAC_RX_256_TO_511_PKTS,
 351         EFX_MAC_RX_512_TO_1023_PKTS,
 352         EFX_MAC_RX_1024_TO_15XX_PKTS,
 353         EFX_MAC_RX_GE_15XX_PKTS,
 354         EFX_MAC_RX_ERRORS,
 355         EFX_MAC_RX_FCS_ERRORS,
 356         EFX_MAC_RX_DROP_EVENTS,
 357         EFX_MAC_RX_FALSE_CARRIER_ERRORS,
 358         EFX_MAC_RX_SYMBOL_ERRORS,
 359         EFX_MAC_RX_ALIGN_ERRORS,
 360         EFX_MAC_RX_INTERNAL_ERRORS,
 361         EFX_MAC_RX_JABBER_PKTS,
 362         EFX_MAC_RX_LANE0_CHAR_ERR,
 363         EFX_MAC_RX_LANE1_CHAR_ERR,
 364         EFX_MAC_RX_LANE2_CHAR_ERR,
 365         EFX_MAC_RX_LANE3_CHAR_ERR,
 366         EFX_MAC_RX_LANE0_DISP_ERR,
 367         EFX_MAC_RX_LANE1_DISP_ERR,
 368         EFX_MAC_RX_LANE2_DISP_ERR,
 369         EFX_MAC_RX_LANE3_DISP_ERR,
 370         EFX_MAC_RX_MATCH_FAULT,
 371         EFX_MAC_RX_NODESC_DROP_CNT,
 372         EFX_MAC_TX_OCTETS,
 373         EFX_MAC_TX_PKTS,
 374         EFX_MAC_TX_UNICST_PKTS,
 375         EFX_MAC_TX_MULTICST_PKTS,
 376         EFX_MAC_TX_BRDCST_PKTS,
 377         EFX_MAC_TX_PAUSE_PKTS,
 378         EFX_MAC_TX_LE_64_PKTS,
 379         EFX_MAC_TX_65_TO_127_PKTS,
 380         EFX_MAC_TX_128_TO_255_PKTS,
 381         EFX_MAC_TX_256_TO_511_PKTS,
 382         EFX_MAC_TX_512_TO_1023_PKTS,
 383         EFX_MAC_TX_1024_TO_15XX_PKTS,
 384         EFX_MAC_TX_GE_15XX_PKTS,
 385         EFX_MAC_TX_ERRORS,
 386         EFX_MAC_TX_SGL_COL_PKTS,
 387         EFX_MAC_TX_MULT_COL_PKTS,
 388         EFX_MAC_TX_EX_COL_PKTS,
 389         EFX_MAC_TX_LATE_COL_PKTS,
 390         EFX_MAC_TX_DEF_PKTS,
 391         EFX_MAC_TX_EX_DEF_PKTS,
 392         EFX_MAC_PM_TRUNC_BB_OVERFLOW,
 393         EFX_MAC_PM_DISCARD_BB_OVERFLOW,
 394         EFX_MAC_PM_TRUNC_VFIFO_FULL,
 395         EFX_MAC_PM_DISCARD_VFIFO_FULL,
 396         EFX_MAC_PM_TRUNC_QBB,
 397         EFX_MAC_PM_DISCARD_QBB,
 398         EFX_MAC_PM_DISCARD_MAPPING,
 399         EFX_MAC_RXDP_Q_DISABLED_PKTS,
 400         EFX_MAC_RXDP_DI_DROPPED_PKTS,
 401         EFX_MAC_RXDP_STREAMING_PKTS,
 402         EFX_MAC_RXDP_HLB_FETCH,
 403         EFX_MAC_RXDP_HLB_WAIT,
 404         EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
 405         EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
 406         EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
 407         EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
 408         EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
 409         EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
 410         EFX_MAC_VADAPTER_RX_BAD_PACKETS,
 411         EFX_MAC_VADAPTER_RX_BAD_BYTES,
 412         EFX_MAC_VADAPTER_RX_OVERFLOW,
 413         EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
 414         EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
 415         EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
 416         EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
 417         EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
 418         EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
 419         EFX_MAC_VADAPTER_TX_BAD_PACKETS,
 420         EFX_MAC_VADAPTER_TX_BAD_BYTES,
 421         EFX_MAC_VADAPTER_TX_OVERFLOW,
 422         EFX_MAC_FEC_UNCORRECTED_ERRORS,
 423         EFX_MAC_FEC_CORRECTED_ERRORS,
 424         EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
 425         EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
 426         EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
 427         EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
 428         EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
 429         EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
 430         EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
 431         EFX_MAC_CTPIO_OVERFLOW_FAIL,
 432         EFX_MAC_CTPIO_UNDERFLOW_FAIL,
 433         EFX_MAC_CTPIO_TIMEOUT_FAIL,
 434         EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
 435         EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
 436         EFX_MAC_CTPIO_INVALID_WR_FAIL,
 437         EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
 438         EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
 439         EFX_MAC_CTPIO_RUNT_FALLBACK,
 440         EFX_MAC_CTPIO_SUCCESS,
 441         EFX_MAC_CTPIO_FALLBACK,
 442         EFX_MAC_CTPIO_POISON,
 443         EFX_MAC_CTPIO_ERASE,
 444         EFX_MAC_NSTATS
 445 } efx_mac_stat_t;
 446
 447 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
 448
 449 #endif  /* EFSYS_OPT_MAC_STATS */
 450
 451 typedef enum efx_link_mode_e {
 452         EFX_LINK_UNKNOWN = 0,
 453         EFX_LINK_DOWN,
 454         EFX_LINK_10HDX,
 455         EFX_LINK_10FDX,
 456         EFX_LINK_100HDX,
 457         EFX_LINK_100FDX,
 458         EFX_LINK_1000HDX,
 459         EFX_LINK_1000FDX,
 460         EFX_LINK_10000FDX,
 461         EFX_LINK_40000FDX,
 462         EFX_LINK_25000FDX,
 463         EFX_LINK_50000FDX,
 464         EFX_LINK_100000FDX,
 465         EFX_LINK_NMODES
 466 } efx_link_mode_t;
 467
 468 #define EFX_MAC_ADDR_LEN 6
 469
 470 #define EFX_VNI_OR_VSID_LEN 3
 471
 472 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
 473
 474 #define EFX_MAC_MULTICAST_LIST_MAX      256
 475
 476 #define EFX_MAC_SDU_MAX 9202
 477
 478 #define EFX_MAC_PDU_ADJUSTMENT                                  \
 479         (/* EtherII */ 14                                       \
 480             + /* VLAN */ 4                                      \
 481             + /* CRC */ 4                                       \
 482             + /* bug16011 */ 16)                                \
 483
 484 #define EFX_MAC_PDU(_sdu)                                       \
 485         P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
 486
 487 /*
 488  * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
 489  * the SDU rounded up slightly.
 490  */
 491 #define EFX_MAC_SDU_FROM_PDU(_pdu)      ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
 492
 493 #define EFX_MAC_PDU_MIN 60
 494 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
 495
 496 extern  __checkReturn   efx_rc_t
 497 efx_mac_pdu_get(
 498         __in            efx_nic_t *enp,
 499         __out           size_t *pdu);
 500
 501 extern  __checkReturn   efx_rc_t
 502 efx_mac_pdu_set(
 503         __in            efx_nic_t *enp,
 504         __in            size_t pdu);
 505
 506 extern  __checkReturn   efx_rc_t
 507 efx_mac_addr_set(
 508         __in            efx_nic_t *enp,
 509         __in            uint8_t *addr);
 510
 511 extern  __checkReturn                   efx_rc_t
 512 efx_mac_filter_set(
 513         __in                            efx_nic_t *enp,
 514         __in                            boolean_t all_unicst,
 515         __in                            boolean_t mulcst,
 516         __in                            boolean_t all_mulcst,
 517         __in                            boolean_t brdcst);
 518
 519 extern  __checkReturn   efx_rc_t
 520 efx_mac_multicast_list_set(
 521         __in                            efx_nic_t *enp,
 522         __in_ecount(6*count)            uint8_t const *addrs,
 523         __in                            int count);
 524
 525 extern  __checkReturn   efx_rc_t
 526 efx_mac_filter_default_rxq_set(
 527         __in            efx_nic_t *enp,
 528         __in            efx_rxq_t *erp,
 529         __in            boolean_t using_rss);
 530
 531 extern                  void
 532 efx_mac_filter_default_rxq_clear(
 533         __in            efx_nic_t *enp);
 534
 535 extern  __checkReturn   efx_rc_t
 536 efx_mac_drain(
 537         __in            efx_nic_t *enp,
 538         __in            boolean_t enabled);
 539
 540 extern  __checkReturn   efx_rc_t
 541 efx_mac_up(
 542         __in            efx_nic_t *enp,
 543         __out           boolean_t *mac_upp);
 544
 545 #define EFX_FCNTL_RESPOND       0x00000001
 546 #define EFX_FCNTL_GENERATE      0x00000002
 547
 548 extern  __checkReturn   efx_rc_t
 549 efx_mac_fcntl_set(
 550         __in            efx_nic_t *enp,
 551         __in            unsigned int fcntl,
 552         __in            boolean_t autoneg);
 553
 554 extern                  void
 555 efx_mac_fcntl_get(
 556         __in            efx_nic_t *enp,
 557         __out           unsigned int *fcntl_wantedp,
 558         __out           unsigned int *fcntl_linkp);
 559
 560
 561 #if EFSYS_OPT_MAC_STATS
 562
 563 #if EFSYS_OPT_NAMES
 564
 565 extern  __checkReturn                   const char *
 566 efx_mac_stat_name(
 567         __in                            efx_nic_t *enp,
 568         __in                            unsigned int id);
 569
 570 #endif  /* EFSYS_OPT_NAMES */
 571
 572 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE        (8 * sizeof (uint32_t))
 573
 574 #define EFX_MAC_STATS_MASK_NPAGES       \
 575         (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
 576             EFX_MAC_STATS_MASK_BITS_PER_PAGE)
 577
 578 /*
 579  * Get mask of MAC statistics supported by the hardware.
 580  *
 581  * If mask_size is insufficient to return the mask, EINVAL error is
 582  * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
 583  * (which is sizeof (uint32_t)) is sufficient.
 584  */
 585 extern  __checkReturn                   efx_rc_t
 586 efx_mac_stats_get_mask(
 587         __in                            efx_nic_t *enp,
 588         __out_bcount(mask_size)         uint32_t *maskp,
 589         __in                            size_t mask_size);
 590
 591 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat)    \
 592         ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] &  \
 593             (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
 594
 595
 596 extern  __checkReturn                   efx_rc_t
 597 efx_mac_stats_clear(
 598         __in                            efx_nic_t *enp);
 599
 600 /*
 601  * Upload mac statistics supported by the hardware into the given buffer.
 602  *
 603  * The DMA buffer must be 4Kbyte aligned and sized to hold at least
 604  * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
 605  *
 606  * The hardware will only DMA statistics that it understands (of course).
 607  * Drivers should not make any assumptions about which statistics are
 608  * supported, especially when the statistics are generated by firmware.
 609  *
 610  * Thus, drivers should zero this buffer before use, so that not-understood
 611  * statistics read back as zero.
 612  */
 613 extern  __checkReturn                   efx_rc_t
 614 efx_mac_stats_upload(
 615         __in                            efx_nic_t *enp,
 616         __in                            efsys_mem_t *esmp);
 617
 618 extern  __checkReturn                   efx_rc_t
 619 efx_mac_stats_periodic(
 620         __in                            efx_nic_t *enp,
 621         __in                            efsys_mem_t *esmp,
 622         __in                            uint16_t period_ms,
 623         __in                            boolean_t events);
 624
 625 extern  __checkReturn                   efx_rc_t
 626 efx_mac_stats_update(
 627         __in                            efx_nic_t *enp,
 628         __in                            efsys_mem_t *esmp,
 629         __inout_ecount(EFX_MAC_NSTATS)  efsys_stat_t *stat,
 630         __inout_opt                     uint32_t *generationp);
 631
 632 #endif  /* EFSYS_OPT_MAC_STATS */
 633
 634 /* MON */
 635
 636 typedef enum efx_mon_type_e {
 637         EFX_MON_INVALID = 0,
 638         EFX_MON_SFC90X0,
 639         EFX_MON_SFC91X0,
 640         EFX_MON_SFC92X0,
 641         EFX_MON_NTYPES
 642 } efx_mon_type_t;
 643
 644 #if EFSYS_OPT_NAMES
 645
 646 extern          const char *
 647 efx_mon_name(
 648         __in    efx_nic_t *enp);
 649
 650 #endif  /* EFSYS_OPT_NAMES */
 651
 652 extern  __checkReturn   efx_rc_t
 653 efx_mon_init(
 654         __in            efx_nic_t *enp);
 655
 656 #if EFSYS_OPT_MON_STATS
 657
 658 #define EFX_MON_STATS_PAGE_SIZE 0x100
 659 #define EFX_MON_MASK_ELEMENT_SIZE 32
 660
 661 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
 662 typedef enum efx_mon_stat_e {
 663         EFX_MON_STAT_2_5V,
 664         EFX_MON_STAT_VCCP1,
 665         EFX_MON_STAT_VCC,
 666         EFX_MON_STAT_5V,
 667         EFX_MON_STAT_12V,
 668         EFX_MON_STAT_VCCP2,
 669         EFX_MON_STAT_EXT_TEMP,
 670         EFX_MON_STAT_INT_TEMP,
 671         EFX_MON_STAT_AIN1,
 672         EFX_MON_STAT_AIN2,
 673         EFX_MON_STAT_INT_COOLING,
 674         EFX_MON_STAT_EXT_COOLING,
 675         EFX_MON_STAT_1V,
 676         EFX_MON_STAT_1_2V,
 677         EFX_MON_STAT_1_8V,
 678         EFX_MON_STAT_3_3V,
 679         EFX_MON_STAT_1_2VA,
 680         EFX_MON_STAT_VREF,
 681         EFX_MON_STAT_VAOE,
 682         EFX_MON_STAT_AOE_TEMP,
 683         EFX_MON_STAT_PSU_AOE_TEMP,
 684         EFX_MON_STAT_PSU_TEMP,
 685         EFX_MON_STAT_FAN0,
 686         EFX_MON_STAT_FAN1,
 687         EFX_MON_STAT_FAN2,
 688         EFX_MON_STAT_FAN3,
 689         EFX_MON_STAT_FAN4,
 690         EFX_MON_STAT_VAOE_IN,
 691         EFX_MON_STAT_IAOE,
 692         EFX_MON_STAT_IAOE_IN,
 693         EFX_MON_STAT_NIC_POWER,
 694         EFX_MON_STAT_0_9V,
 695         EFX_MON_STAT_I0_9V,
 696         EFX_MON_STAT_I1_2V,
 697         EFX_MON_STAT_0_9V_ADC,
 698         EFX_MON_STAT_INT_TEMP2,
 699         EFX_MON_STAT_VREG_TEMP,
 700         EFX_MON_STAT_VREG_0_9V_TEMP,
 701         EFX_MON_STAT_VREG_1_2V_TEMP,
 702         EFX_MON_STAT_INT_VPTAT,
 703         EFX_MON_STAT_INT_ADC_TEMP,
 704         EFX_MON_STAT_EXT_VPTAT,
 705         EFX_MON_STAT_EXT_ADC_TEMP,
 706         EFX_MON_STAT_AMBIENT_TEMP,
 707         EFX_MON_STAT_AIRFLOW,
 708         EFX_MON_STAT_VDD08D_VSS08D_CSR,
 709         EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
 710         EFX_MON_STAT_HOTPOINT_TEMP,
 711         EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
 712         EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
 713         EFX_MON_STAT_MUM_VCC,
 714         EFX_MON_STAT_0V9_A,
 715         EFX_MON_STAT_I0V9_A,
 716         EFX_MON_STAT_0V9_A_TEMP,
 717         EFX_MON_STAT_0V9_B,
 718         EFX_MON_STAT_I0V9_B,
 719         EFX_MON_STAT_0V9_B_TEMP,
 720         EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
 721         EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
 722         EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
 723         EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
 724         EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
 725         EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
 726         EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
 727         EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
 728         EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
 729         EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
 730         EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
 731         EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
 732         EFX_MON_STAT_SODIMM_VOUT,
 733         EFX_MON_STAT_SODIMM_0_TEMP,
 734         EFX_MON_STAT_SODIMM_1_TEMP,
 735         EFX_MON_STAT_PHY0_VCC,
 736         EFX_MON_STAT_PHY1_VCC,
 737         EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
 738         EFX_MON_STAT_BOARD_FRONT_TEMP,
 739         EFX_MON_STAT_BOARD_BACK_TEMP,
 740         EFX_MON_STAT_I1V8,
 741         EFX_MON_STAT_I2V5,
 742         EFX_MON_STAT_I3V3,
 743         EFX_MON_STAT_I12V0,
 744         EFX_MON_STAT_1_3V,
 745         EFX_MON_STAT_I1V3,
 746         EFX_MON_NSTATS
 747 } efx_mon_stat_t;
 748
 749 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
 750
 751 typedef enum efx_mon_stat_state_e {
 752         EFX_MON_STAT_STATE_OK = 0,
 753         EFX_MON_STAT_STATE_WARNING = 1,
 754         EFX_MON_STAT_STATE_FATAL = 2,
 755         EFX_MON_STAT_STATE_BROKEN = 3,
 756         EFX_MON_STAT_STATE_NO_READING = 4,
 757 } efx_mon_stat_state_t;
 758
 759 typedef struct efx_mon_stat_value_s {
 760         uint16_t        emsv_value;
 761         uint16_t        emsv_state;
 762 } efx_mon_stat_value_t;
 763
 764 #if EFSYS_OPT_NAMES
 765
 766 extern                                  const char *
 767 efx_mon_stat_name(
 768         __in                            efx_nic_t *enp,
 769         __in                            efx_mon_stat_t id);
 770
 771 #endif  /* EFSYS_OPT_NAMES */
 772
 773 extern  __checkReturn                   efx_rc_t
 774 efx_mon_stats_update(
 775         __in                            efx_nic_t *enp,
 776         __in                            efsys_mem_t *esmp,
 777         __inout_ecount(EFX_MON_NSTATS)  efx_mon_stat_value_t *values);
 778
 779 #endif  /* EFSYS_OPT_MON_STATS */
 780
 781 extern          void
 782 efx_mon_fini(
 783         __in    efx_nic_t *enp);
 784
 785 /* PHY */
 786
 787 extern  __checkReturn   efx_rc_t
 788 efx_phy_verify(
 789         __in            efx_nic_t *enp);
 790
 791 #if EFSYS_OPT_PHY_LED_CONTROL
 792
 793 typedef enum efx_phy_led_mode_e {
 794         EFX_PHY_LED_DEFAULT = 0,
 795         EFX_PHY_LED_OFF,
 796         EFX_PHY_LED_ON,
 797         EFX_PHY_LED_FLASH,
 798         EFX_PHY_LED_NMODES
 799 } efx_phy_led_mode_t;
 800
 801 extern  __checkReturn   efx_rc_t
 802 efx_phy_led_set(
 803         __in    efx_nic_t *enp,
 804         __in    efx_phy_led_mode_t mode);
 805
 806 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 807
 808 extern  __checkReturn   efx_rc_t
 809 efx_port_init(
 810         __in            efx_nic_t *enp);
 811
 812 #if EFSYS_OPT_LOOPBACK
 813
 814 typedef enum efx_loopback_type_e {
 815         EFX_LOOPBACK_OFF = 0,
 816         EFX_LOOPBACK_DATA = 1,
 817         EFX_LOOPBACK_GMAC = 2,
 818         EFX_LOOPBACK_XGMII = 3,
 819         EFX_LOOPBACK_XGXS = 4,
 820         EFX_LOOPBACK_XAUI = 5,
 821         EFX_LOOPBACK_GMII = 6,
 822         EFX_LOOPBACK_SGMII = 7,
 823         EFX_LOOPBACK_XGBR = 8,
 824         EFX_LOOPBACK_XFI = 9,
 825         EFX_LOOPBACK_XAUI_FAR = 10,
 826         EFX_LOOPBACK_GMII_FAR = 11,
 827         EFX_LOOPBACK_SGMII_FAR = 12,
 828         EFX_LOOPBACK_XFI_FAR = 13,
 829         EFX_LOOPBACK_GPHY = 14,
 830         EFX_LOOPBACK_PHY_XS = 15,
 831         EFX_LOOPBACK_PCS = 16,
 832         EFX_LOOPBACK_PMA_PMD = 17,
 833         EFX_LOOPBACK_XPORT = 18,
 834         EFX_LOOPBACK_XGMII_WS = 19,
 835         EFX_LOOPBACK_XAUI_WS = 20,
 836         EFX_LOOPBACK_XAUI_WS_FAR = 21,
 837         EFX_LOOPBACK_XAUI_WS_NEAR = 22,
 838         EFX_LOOPBACK_GMII_WS = 23,
 839         EFX_LOOPBACK_XFI_WS = 24,
 840         EFX_LOOPBACK_XFI_WS_FAR = 25,
 841         EFX_LOOPBACK_PHYXS_WS = 26,
 842         EFX_LOOPBACK_PMA_INT = 27,
 843         EFX_LOOPBACK_SD_NEAR = 28,
 844         EFX_LOOPBACK_SD_FAR = 29,
 845         EFX_LOOPBACK_PMA_INT_WS = 30,
 846         EFX_LOOPBACK_SD_FEP2_WS = 31,
 847         EFX_LOOPBACK_SD_FEP1_5_WS = 32,
 848         EFX_LOOPBACK_SD_FEP_WS = 33,
 849         EFX_LOOPBACK_SD_FES_WS = 34,
 850         EFX_LOOPBACK_AOE_INT_NEAR = 35,
 851         EFX_LOOPBACK_DATA_WS = 36,
 852         EFX_LOOPBACK_FORCE_EXT_LINK = 37,
 853         EFX_LOOPBACK_NTYPES
 854 } efx_loopback_type_t;
 855
 856 typedef enum efx_loopback_kind_e {
 857         EFX_LOOPBACK_KIND_OFF = 0,
 858         EFX_LOOPBACK_KIND_ALL,
 859         EFX_LOOPBACK_KIND_MAC,
 860         EFX_LOOPBACK_KIND_PHY,
 861         EFX_LOOPBACK_NKINDS
 862 } efx_loopback_kind_t;
 863
 864 extern                  void
 865 efx_loopback_mask(
 866         __in    efx_loopback_kind_t loopback_kind,
 867         __out   efx_qword_t *maskp);
 868
 869 extern  __checkReturn   efx_rc_t
 870 efx_port_loopback_set(
 871         __in    efx_nic_t *enp,
 872         __in    efx_link_mode_t link_mode,
 873         __in    efx_loopback_type_t type);
 874
 875 #if EFSYS_OPT_NAMES
 876
 877 extern  __checkReturn   const char *
 878 efx_loopback_type_name(
 879         __in            efx_nic_t *enp,
 880         __in            efx_loopback_type_t type);
 881
 882 #endif  /* EFSYS_OPT_NAMES */
 883
 884 #endif  /* EFSYS_OPT_LOOPBACK */
 885
 886 extern  __checkReturn   efx_rc_t
 887 efx_port_poll(
 888         __in            efx_nic_t *enp,
 889         __out_opt       efx_link_mode_t *link_modep);
 890
 891 extern          void
 892 efx_port_fini(
 893         __in    efx_nic_t *enp);
 894
 895 typedef enum efx_phy_cap_type_e {
 896         EFX_PHY_CAP_INVALID = 0,
 897         EFX_PHY_CAP_10HDX,
 898         EFX_PHY_CAP_10FDX,
 899         EFX_PHY_CAP_100HDX,
 900         EFX_PHY_CAP_100FDX,
 901         EFX_PHY_CAP_1000HDX,
 902         EFX_PHY_CAP_1000FDX,
 903         EFX_PHY_CAP_10000FDX,
 904         EFX_PHY_CAP_PAUSE,
 905         EFX_PHY_CAP_ASYM,
 906         EFX_PHY_CAP_AN,
 907         EFX_PHY_CAP_40000FDX,
 908         EFX_PHY_CAP_DDM,
 909         EFX_PHY_CAP_100000FDX,
 910         EFX_PHY_CAP_25000FDX,
 911         EFX_PHY_CAP_50000FDX,
 912         EFX_PHY_CAP_BASER_FEC,
 913         EFX_PHY_CAP_BASER_FEC_REQUESTED,
 914         EFX_PHY_CAP_RS_FEC,
 915         EFX_PHY_CAP_RS_FEC_REQUESTED,
 916         EFX_PHY_CAP_25G_BASER_FEC,
 917         EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
 918         EFX_PHY_CAP_NTYPES
 919 } efx_phy_cap_type_t;
 920
 921
 922 #define EFX_PHY_CAP_CURRENT     0x00000000
 923 #define EFX_PHY_CAP_DEFAULT     0x00000001
 924 #define EFX_PHY_CAP_PERM        0x00000002
 925
 926 extern          void
 927 efx_phy_adv_cap_get(
 928         __in            efx_nic_t *enp,
 929         __in            uint32_t flag,
 930         __out           uint32_t *maskp);
 931
 932 extern  __checkReturn   efx_rc_t
 933 efx_phy_adv_cap_set(
 934         __in            efx_nic_t *enp,
 935         __in            uint32_t mask);
 936
 937 extern                  void
 938 efx_phy_lp_cap_get(
 939         __in            efx_nic_t *enp,
 940         __out           uint32_t *maskp);
 941
 942 extern  __checkReturn   efx_rc_t
 943 efx_phy_oui_get(
 944         __in            efx_nic_t *enp,
 945         __out           uint32_t *ouip);
 946
 947 typedef enum efx_phy_media_type_e {
 948         EFX_PHY_MEDIA_INVALID = 0,
 949         EFX_PHY_MEDIA_XAUI,
 950         EFX_PHY_MEDIA_CX4,
 951         EFX_PHY_MEDIA_KX4,
 952         EFX_PHY_MEDIA_XFP,
 953         EFX_PHY_MEDIA_SFP_PLUS,
 954         EFX_PHY_MEDIA_BASE_T,
 955         EFX_PHY_MEDIA_QSFP_PLUS,
 956         EFX_PHY_MEDIA_NTYPES
 957 } efx_phy_media_type_t;
 958
 959 /*
 960  * Get the type of medium currently used.  If the board has ports for
 961  * modules, a module is present, and we recognise the media type of
 962  * the module, then this will be the media type of the module.
 963  * Otherwise it will be the media type of the port.
 964  */
 965 extern                  void
 966 efx_phy_media_type_get(
 967         __in            efx_nic_t *enp,
 968         __out           efx_phy_media_type_t *typep);
 969
 970 extern  __checkReturn           efx_rc_t
 971 efx_phy_module_get_info(
 972         __in                    efx_nic_t *enp,
 973         __in                    uint8_t dev_addr,
 974         __in                    uint8_t offset,
 975         __in                    uint8_t len,
 976         __out_bcount(len)       uint8_t *data);
 977
 978 #if EFSYS_OPT_PHY_STATS
 979
 980 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
 981 typedef enum efx_phy_stat_e {
 982         EFX_PHY_STAT_OUI,
 983         EFX_PHY_STAT_PMA_PMD_LINK_UP,
 984         EFX_PHY_STAT_PMA_PMD_RX_FAULT,
 985         EFX_PHY_STAT_PMA_PMD_TX_FAULT,
 986         EFX_PHY_STAT_PMA_PMD_REV_A,
 987         EFX_PHY_STAT_PMA_PMD_REV_B,
 988         EFX_PHY_STAT_PMA_PMD_REV_C,
 989         EFX_PHY_STAT_PMA_PMD_REV_D,
 990         EFX_PHY_STAT_PCS_LINK_UP,
 991         EFX_PHY_STAT_PCS_RX_FAULT,
 992         EFX_PHY_STAT_PCS_TX_FAULT,
 993         EFX_PHY_STAT_PCS_BER,
 994         EFX_PHY_STAT_PCS_BLOCK_ERRORS,
 995         EFX_PHY_STAT_PHY_XS_LINK_UP,
 996         EFX_PHY_STAT_PHY_XS_RX_FAULT,
 997         EFX_PHY_STAT_PHY_XS_TX_FAULT,
 998         EFX_PHY_STAT_PHY_XS_ALIGN,
 999         EFX_PHY_STAT_PHY_XS_SYNC_A,
1000         EFX_PHY_STAT_PHY_XS_SYNC_B,
1001         EFX_PHY_STAT_PHY_XS_SYNC_C,
1002         EFX_PHY_STAT_PHY_XS_SYNC_D,
1003         EFX_PHY_STAT_AN_LINK_UP,
1004         EFX_PHY_STAT_AN_MASTER,
1005         EFX_PHY_STAT_AN_LOCAL_RX_OK,
1006         EFX_PHY_STAT_AN_REMOTE_RX_OK,
1007         EFX_PHY_STAT_CL22EXT_LINK_UP,
1008         EFX_PHY_STAT_SNR_A,
1009         EFX_PHY_STAT_SNR_B,
1010         EFX_PHY_STAT_SNR_C,
1011         EFX_PHY_STAT_SNR_D,
1012         EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1013         EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1014         EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1015         EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1016         EFX_PHY_STAT_AN_COMPLETE,
1017         EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1018         EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1019         EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1020         EFX_PHY_STAT_PCS_FW_VERSION_0,
1021         EFX_PHY_STAT_PCS_FW_VERSION_1,
1022         EFX_PHY_STAT_PCS_FW_VERSION_2,
1023         EFX_PHY_STAT_PCS_FW_VERSION_3,
1024         EFX_PHY_STAT_PCS_FW_BUILD_YY,
1025         EFX_PHY_STAT_PCS_FW_BUILD_MM,
1026         EFX_PHY_STAT_PCS_FW_BUILD_DD,
1027         EFX_PHY_STAT_PCS_OP_MODE,
1028         EFX_PHY_NSTATS
1029 } efx_phy_stat_t;
1030
1031 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1032
1033 #if EFSYS_OPT_NAMES
1034
1035 extern                                  const char *
1036 efx_phy_stat_name(
1037         __in                            efx_nic_t *enp,
1038         __in                            efx_phy_stat_t stat);
1039
1040 #endif  /* EFSYS_OPT_NAMES */
1041
1042 #define EFX_PHY_STATS_SIZE 0x100
1043
1044 extern  __checkReturn                   efx_rc_t
1045 efx_phy_stats_update(
1046         __in                            efx_nic_t *enp,
1047         __in                            efsys_mem_t *esmp,
1048         __inout_ecount(EFX_PHY_NSTATS)  uint32_t *stat);
1049
1050 #endif  /* EFSYS_OPT_PHY_STATS */
1051
1052
1053 #if EFSYS_OPT_BIST
1054
1055 typedef enum efx_bist_type_e {
1056         EFX_BIST_TYPE_UNKNOWN,
1057         EFX_BIST_TYPE_PHY_NORMAL,
1058         EFX_BIST_TYPE_PHY_CABLE_SHORT,
1059         EFX_BIST_TYPE_PHY_CABLE_LONG,
1060         EFX_BIST_TYPE_MC_MEM,   /* Test the MC DMEM and IMEM */
1061         EFX_BIST_TYPE_SAT_MEM,  /* Test the DMEM and IMEM of satellite cpus */
1062         EFX_BIST_TYPE_REG,      /* Test the register memories */
1063         EFX_BIST_TYPE_NTYPES,
1064 } efx_bist_type_t;
1065
1066 typedef enum efx_bist_result_e {
1067         EFX_BIST_RESULT_UNKNOWN,
1068         EFX_BIST_RESULT_RUNNING,
1069         EFX_BIST_RESULT_PASSED,
1070         EFX_BIST_RESULT_FAILED,
1071 } efx_bist_result_t;
1072
1073 typedef enum efx_phy_cable_status_e {
1074         EFX_PHY_CABLE_STATUS_OK,
1075         EFX_PHY_CABLE_STATUS_INVALID,
1076         EFX_PHY_CABLE_STATUS_OPEN,
1077         EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1078         EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1079         EFX_PHY_CABLE_STATUS_BUSY,
1080 } efx_phy_cable_status_t;
1081
1082 typedef enum efx_bist_value_e {
1083         EFX_BIST_PHY_CABLE_LENGTH_A,
1084         EFX_BIST_PHY_CABLE_LENGTH_B,
1085         EFX_BIST_PHY_CABLE_LENGTH_C,
1086         EFX_BIST_PHY_CABLE_LENGTH_D,
1087         EFX_BIST_PHY_CABLE_STATUS_A,
1088         EFX_BIST_PHY_CABLE_STATUS_B,
1089         EFX_BIST_PHY_CABLE_STATUS_C,
1090         EFX_BIST_PHY_CABLE_STATUS_D,
1091         EFX_BIST_FAULT_CODE,
1092         /*
1093          * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1094          * response.
1095          */
1096         EFX_BIST_MEM_TEST,
1097         EFX_BIST_MEM_ADDR,
1098         EFX_BIST_MEM_BUS,
1099         EFX_BIST_MEM_EXPECT,
1100         EFX_BIST_MEM_ACTUAL,
1101         EFX_BIST_MEM_ECC,
1102         EFX_BIST_MEM_ECC_PARITY,
1103         EFX_BIST_MEM_ECC_FATAL,
1104         EFX_BIST_NVALUES,
1105 } efx_bist_value_t;
1106
1107 extern  __checkReturn           efx_rc_t
1108 efx_bist_enable_offline(
1109         __in                    efx_nic_t *enp);
1110
1111 extern  __checkReturn           efx_rc_t
1112 efx_bist_start(
1113         __in                    efx_nic_t *enp,
1114         __in                    efx_bist_type_t type);
1115
1116 extern  __checkReturn           efx_rc_t
1117 efx_bist_poll(
1118         __in                    efx_nic_t *enp,
1119         __in                    efx_bist_type_t type,
1120         __out                   efx_bist_result_t *resultp,
1121         __out_opt               uint32_t *value_maskp,
1122         __out_ecount_opt(count) unsigned long *valuesp,
1123         __in                    size_t count);
1124
1125 extern                          void
1126 efx_bist_stop(
1127         __in                    efx_nic_t *enp,
1128         __in                    efx_bist_type_t type);
1129
1130 #endif  /* EFSYS_OPT_BIST */
1131
1132 #define EFX_FEATURE_IPV6                0x00000001
1133 #define EFX_FEATURE_LFSR_HASH_INSERT    0x00000002
1134 #define EFX_FEATURE_LINK_EVENTS         0x00000004
1135 #define EFX_FEATURE_PERIODIC_MAC_STATS  0x00000008
1136 #define EFX_FEATURE_MCDI                0x00000020
1137 #define EFX_FEATURE_LOOKAHEAD_SPLIT     0x00000040
1138 #define EFX_FEATURE_MAC_HEADER_FILTERS  0x00000080
1139 #define EFX_FEATURE_TURBO               0x00000100
1140 #define EFX_FEATURE_MCDI_DMA            0x00000200
1141 #define EFX_FEATURE_TX_SRC_FILTERS      0x00000400
1142 #define EFX_FEATURE_PIO_BUFFERS         0x00000800
1143 #define EFX_FEATURE_FW_ASSISTED_TSO     0x00001000
1144 #define EFX_FEATURE_FW_ASSISTED_TSO_V2  0x00002000
1145 #define EFX_FEATURE_PACKED_STREAM       0x00004000
1146
1147 typedef enum efx_tunnel_protocol_e {
1148         EFX_TUNNEL_PROTOCOL_NONE = 0,
1149         EFX_TUNNEL_PROTOCOL_VXLAN,
1150         EFX_TUNNEL_PROTOCOL_GENEVE,
1151         EFX_TUNNEL_PROTOCOL_NVGRE,
1152         EFX_TUNNEL_NPROTOS
1153 } efx_tunnel_protocol_t;
1154
1155 typedef enum efx_vi_window_shift_e {
1156         EFX_VI_WINDOW_SHIFT_INVALID = 0,
1157         EFX_VI_WINDOW_SHIFT_8K = 13,
1158         EFX_VI_WINDOW_SHIFT_16K = 14,
1159         EFX_VI_WINDOW_SHIFT_64K = 16,
1160 } efx_vi_window_shift_t;
1161
1162 typedef struct efx_nic_cfg_s {
1163         uint32_t                enc_board_type;
1164         uint32_t                enc_phy_type;
1165 #if EFSYS_OPT_NAMES
1166         char                    enc_phy_name[21];
1167 #endif
1168         char                    enc_phy_revision[21];
1169         efx_mon_type_t          enc_mon_type;
1170 #if EFSYS_OPT_MON_STATS
1171         uint32_t                enc_mon_stat_dma_buf_size;
1172         uint32_t                enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1173 #endif
1174         unsigned int            enc_features;
1175         efx_vi_window_shift_t   enc_vi_window_shift;
1176         uint8_t                 enc_mac_addr[6];
1177         uint8_t                 enc_port;       /* PHY port number */
1178         uint32_t                enc_intr_vec_base;
1179         uint32_t                enc_intr_limit;
1180         uint32_t                enc_evq_limit;
1181         uint32_t                enc_txq_limit;
1182         uint32_t                enc_rxq_limit;
1183         uint32_t                enc_txq_max_ndescs;
1184         uint32_t                enc_buftbl_limit;
1185         uint32_t                enc_piobuf_limit;
1186         uint32_t                enc_piobuf_size;
1187         uint32_t                enc_piobuf_min_alloc_size;
1188         uint32_t                enc_evq_timer_quantum_ns;
1189         uint32_t                enc_evq_timer_max_us;
1190         uint32_t                enc_clk_mult;
1191         uint32_t                enc_rx_prefix_size;
1192         uint32_t                enc_rx_buf_align_start;
1193         uint32_t                enc_rx_buf_align_end;
1194         uint32_t                enc_rx_scale_max_exclusive_contexts;
1195         boolean_t               enc_rx_scale_additional_modes_supported;
1196 #if EFSYS_OPT_LOOPBACK
1197         efx_qword_t             enc_loopback_types[EFX_LINK_NMODES];
1198 #endif  /* EFSYS_OPT_LOOPBACK */
1199 #if EFSYS_OPT_PHY_FLAGS
1200         uint32_t                enc_phy_flags_mask;
1201 #endif  /* EFSYS_OPT_PHY_FLAGS */
1202 #if EFSYS_OPT_PHY_LED_CONTROL
1203         uint32_t                enc_led_mask;
1204 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
1205 #if EFSYS_OPT_PHY_STATS
1206         uint64_t                enc_phy_stat_mask;
1207 #endif  /* EFSYS_OPT_PHY_STATS */
1208 #if EFSYS_OPT_MCDI
1209         uint8_t                 enc_mcdi_mdio_channel;
1210 #if EFSYS_OPT_PHY_STATS
1211         uint32_t                enc_mcdi_phy_stat_mask;
1212 #endif  /* EFSYS_OPT_PHY_STATS */
1213 #if EFSYS_OPT_MON_STATS
1214         uint32_t                *enc_mcdi_sensor_maskp;
1215         uint32_t                enc_mcdi_sensor_mask_size;
1216 #endif  /* EFSYS_OPT_MON_STATS */
1217 #endif  /* EFSYS_OPT_MCDI */
1218 #if EFSYS_OPT_BIST
1219         uint32_t                enc_bist_mask;
1220 #endif  /* EFSYS_OPT_BIST */
1221 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1222         uint32_t                enc_pf;
1223         uint32_t                enc_vf;
1224         uint32_t                enc_privilege_mask;
1225 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1226         boolean_t               enc_bug26807_workaround;
1227         boolean_t               enc_bug35388_workaround;
1228         boolean_t               enc_bug41750_workaround;
1229         boolean_t               enc_bug61265_workaround;
1230         boolean_t               enc_rx_batching_enabled;
1231         /* Maximum number of descriptors completed in an rx event. */
1232         uint32_t                enc_rx_batch_max;
1233         /* Number of rx descriptors the hardware requires for a push. */
1234         uint32_t                enc_rx_push_align;
1235         /* Maximum amount of data in DMA descriptor */
1236         uint32_t                enc_tx_dma_desc_size_max;
1237         /*
1238          * Boundary which DMA descriptor data must not cross or 0 if no
1239          * limitation.
1240          */
1241         uint32_t                enc_tx_dma_desc_boundary;
1242         /*
1243          * Maximum number of bytes into the packet the TCP header can start for
1244          * the hardware to apply TSO packet edits.
1245          */
1246         uint32_t                enc_tx_tso_tcp_header_offset_limit;
1247         boolean_t               enc_fw_assisted_tso_enabled;
1248         boolean_t               enc_fw_assisted_tso_v2_enabled;
1249         boolean_t               enc_fw_assisted_tso_v2_encap_enabled;
1250         /* Number of TSO contexts on the NIC (FATSOv2) */
1251         uint32_t                enc_fw_assisted_tso_v2_n_contexts;
1252         boolean_t               enc_hw_tx_insert_vlan_enabled;
1253         /* Number of PFs on the NIC */
1254         uint32_t                enc_hw_pf_count;
1255         /* Datapath firmware vadapter/vport/vswitch support */
1256         boolean_t               enc_datapath_cap_evb;
1257         boolean_t               enc_rx_disable_scatter_supported;
1258         boolean_t               enc_allow_set_mac_with_installed_filters;
1259         boolean_t               enc_enhanced_set_mac_supported;
1260         boolean_t               enc_init_evq_v2_supported;
1261         boolean_t               enc_rx_packed_stream_supported;
1262         boolean_t               enc_rx_var_packed_stream_supported;
1263         boolean_t               enc_fw_subvariant_no_tx_csum_supported;
1264         boolean_t               enc_pm_and_rxdp_counters;
1265         boolean_t               enc_mac_stats_40g_tx_size_bins;
1266         uint32_t                enc_tunnel_encapsulations_supported;
1267         /*
1268          * NIC global maximum for unique UDP tunnel ports shared by all
1269          * functions.
1270          */
1271         uint32_t                enc_tunnel_config_udp_entries_max;
1272         /* External port identifier */
1273         uint8_t                 enc_external_port;
1274         uint32_t                enc_mcdi_max_payload_length;
1275         /* VPD may be per-PF or global */
1276         boolean_t               enc_vpd_is_global;
1277         /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1278         uint32_t                enc_required_pcie_bandwidth_mbps;
1279         uint32_t                enc_max_pcie_link_gen;
1280         /* Firmware verifies integrity of NVRAM updates */
1281         uint32_t                enc_nvram_update_verify_result_supported;
1282         /* Firmware support for extended MAC_STATS buffer */
1283         uint32_t                enc_mac_stats_nstats;
1284         boolean_t               enc_fec_counters;
1285 } efx_nic_cfg_t;
1286
1287 #define EFX_PCI_FUNCTION_IS_PF(_encp)   ((_encp)->enc_vf == 0xffff)
1288 #define EFX_PCI_FUNCTION_IS_VF(_encp)   ((_encp)->enc_vf != 0xffff)
1289
1290 #define EFX_PCI_FUNCTION(_encp) \
1291         (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1292
1293 #define EFX_PCI_VF_PARENT(_encp)        ((_encp)->enc_pf)
1294
1295 extern                  const efx_nic_cfg_t *
1296 efx_nic_cfg_get(
1297         __in            efx_nic_t *enp);
1298
1299 /* RxDPCPU firmware id values by which FW variant can be identified */
1300 #define EFX_RXDP_FULL_FEATURED_FW_ID    0x0
1301 #define EFX_RXDP_LOW_LATENCY_FW_ID      0x1
1302 #define EFX_RXDP_PACKED_STREAM_FW_ID    0x2
1303 #define EFX_RXDP_RULES_ENGINE_FW_ID     0x5
1304 #define EFX_RXDP_DPDK_FW_ID             0x6
1305
1306 typedef struct efx_nic_fw_info_s {
1307         /* Basic FW version information */
1308         uint16_t        enfi_mc_fw_version[4];
1309         /*
1310          * If datapath capabilities can be detected,
1311          * additional FW information is to be shown
1312          */
1313         boolean_t       enfi_dpcpu_fw_ids_valid;
1314         /* Rx and Tx datapath CPU FW IDs */
1315         uint16_t        enfi_rx_dpcpu_fw_id;
1316         uint16_t        enfi_tx_dpcpu_fw_id;
1317 } efx_nic_fw_info_t;
1318
1319 extern  __checkReturn           efx_rc_t
1320 efx_nic_get_fw_version(
1321         __in                    efx_nic_t *enp,
1322         __out                   efx_nic_fw_info_t *enfip);
1323
1324 /* Driver resource limits (minimum required/maximum usable). */
1325 typedef struct efx_drv_limits_s {
1326         uint32_t        edl_min_evq_count;
1327         uint32_t        edl_max_evq_count;
1328
1329         uint32_t        edl_min_rxq_count;
1330         uint32_t        edl_max_rxq_count;
1331
1332         uint32_t        edl_min_txq_count;
1333         uint32_t        edl_max_txq_count;
1334
1335         /* PIO blocks (sub-allocated from piobuf) */
1336         uint32_t        edl_min_pio_alloc_size;
1337         uint32_t        edl_max_pio_alloc_count;
1338 } efx_drv_limits_t;
1339
1340 extern  __checkReturn   efx_rc_t
1341 efx_nic_set_drv_limits(
1342         __inout         efx_nic_t *enp,
1343         __in            efx_drv_limits_t *edlp);
1344
1345 typedef enum efx_nic_region_e {
1346         EFX_REGION_VI,                  /* Memory BAR UC mapping */
1347         EFX_REGION_PIO_WRITE_VI,        /* Memory BAR WC mapping */
1348 } efx_nic_region_t;
1349
1350 extern  __checkReturn   efx_rc_t
1351 efx_nic_get_bar_region(
1352         __in            efx_nic_t *enp,
1353         __in            efx_nic_region_t region,
1354         __out           uint32_t *offsetp,
1355         __out           size_t *sizep);
1356
1357 extern  __checkReturn   efx_rc_t
1358 efx_nic_get_vi_pool(
1359         __in            efx_nic_t *enp,
1360         __out           uint32_t *evq_countp,
1361         __out           uint32_t *rxq_countp,
1362         __out           uint32_t *txq_countp);
1363
1364
1365 #if EFSYS_OPT_VPD
1366
1367 typedef enum efx_vpd_tag_e {
1368         EFX_VPD_ID = 0x02,
1369         EFX_VPD_END = 0x0f,
1370         EFX_VPD_RO = 0x10,
1371         EFX_VPD_RW = 0x11,
1372 } efx_vpd_tag_t;
1373
1374 typedef uint16_t efx_vpd_keyword_t;
1375
1376 typedef struct efx_vpd_value_s {
1377         efx_vpd_tag_t           evv_tag;
1378         efx_vpd_keyword_t       evv_keyword;
1379         uint8_t                 evv_length;
1380         uint8_t                 evv_value[0x100];
1381 } efx_vpd_value_t;
1382
1383
1384 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1385
1386 extern  __checkReturn           efx_rc_t
1387 efx_vpd_init(
1388         __in                    efx_nic_t *enp);
1389
1390 extern  __checkReturn           efx_rc_t
1391 efx_vpd_size(
1392         __in                    efx_nic_t *enp,
1393         __out                   size_t *sizep);
1394
1395 extern  __checkReturn           efx_rc_t
1396 efx_vpd_read(
1397         __in                    efx_nic_t *enp,
1398         __out_bcount(size)      caddr_t data,
1399         __in                    size_t size);
1400
1401 extern  __checkReturn           efx_rc_t
1402 efx_vpd_verify(
1403         __in                    efx_nic_t *enp,
1404         __in_bcount(size)       caddr_t data,
1405         __in                    size_t size);
1406
1407 extern  __checkReturn           efx_rc_t
1408 efx_vpd_reinit(
1409         __in                    efx_nic_t *enp,
1410         __in_bcount(size)       caddr_t data,
1411         __in                    size_t size);
1412
1413 extern  __checkReturn           efx_rc_t
1414 efx_vpd_get(
1415         __in                    efx_nic_t *enp,
1416         __in_bcount(size)       caddr_t data,
1417         __in                    size_t size,
1418         __inout                 efx_vpd_value_t *evvp);
1419
1420 extern  __checkReturn           efx_rc_t
1421 efx_vpd_set(
1422         __in                    efx_nic_t *enp,
1423         __inout_bcount(size)    caddr_t data,
1424         __in                    size_t size,
1425         __in                    efx_vpd_value_t *evvp);
1426
1427 extern  __checkReturn           efx_rc_t
1428 efx_vpd_next(
1429         __in                    efx_nic_t *enp,
1430         __inout_bcount(size)    caddr_t data,
1431         __in                    size_t size,
1432         __out                   efx_vpd_value_t *evvp,
1433         __inout                 unsigned int *contp);
1434
1435 extern  __checkReturn           efx_rc_t
1436 efx_vpd_write(
1437         __in                    efx_nic_t *enp,
1438         __in_bcount(size)       caddr_t data,
1439         __in                    size_t size);
1440
1441 extern                          void
1442 efx_vpd_fini(
1443         __in                    efx_nic_t *enp);
1444
1445 #endif  /* EFSYS_OPT_VPD */
1446
1447 /* NVRAM */
1448
1449 #if EFSYS_OPT_NVRAM
1450
1451 typedef enum efx_nvram_type_e {
1452         EFX_NVRAM_INVALID = 0,
1453         EFX_NVRAM_BOOTROM,
1454         EFX_NVRAM_BOOTROM_CFG,
1455         EFX_NVRAM_MC_FIRMWARE,
1456         EFX_NVRAM_MC_GOLDEN,
1457         EFX_NVRAM_PHY,
1458         EFX_NVRAM_NULLPHY,
1459         EFX_NVRAM_FPGA,
1460         EFX_NVRAM_FCFW,
1461         EFX_NVRAM_CPLD,
1462         EFX_NVRAM_FPGA_BACKUP,
1463         EFX_NVRAM_DYNAMIC_CFG,
1464         EFX_NVRAM_LICENSE,
1465         EFX_NVRAM_UEFIROM,
1466         EFX_NVRAM_MUM_FIRMWARE,
1467         EFX_NVRAM_NTYPES,
1468 } efx_nvram_type_t;
1469
1470 extern  __checkReturn           efx_rc_t
1471 efx_nvram_init(
1472         __in                    efx_nic_t *enp);
1473
1474 #if EFSYS_OPT_DIAG
1475
1476 extern  __checkReturn           efx_rc_t
1477 efx_nvram_test(
1478         __in                    efx_nic_t *enp);
1479
1480 #endif  /* EFSYS_OPT_DIAG */
1481
1482 extern  __checkReturn           efx_rc_t
1483 efx_nvram_size(
1484         __in                    efx_nic_t *enp,
1485         __in                    efx_nvram_type_t type,
1486         __out                   size_t *sizep);
1487
1488 extern  __checkReturn           efx_rc_t
1489 efx_nvram_rw_start(
1490         __in                    efx_nic_t *enp,
1491         __in                    efx_nvram_type_t type,
1492         __out_opt               size_t *pref_chunkp);
1493
1494 extern  __checkReturn           efx_rc_t
1495 efx_nvram_rw_finish(
1496         __in                    efx_nic_t *enp,
1497         __in                    efx_nvram_type_t type,
1498         __out_opt               uint32_t *verify_resultp);
1499
1500 extern  __checkReturn           efx_rc_t
1501 efx_nvram_get_version(
1502         __in                    efx_nic_t *enp,
1503         __in                    efx_nvram_type_t type,
1504         __out                   uint32_t *subtypep,
1505         __out_ecount(4)         uint16_t version[4]);
1506
1507 extern  __checkReturn           efx_rc_t
1508 efx_nvram_read_chunk(
1509         __in                    efx_nic_t *enp,
1510         __in                    efx_nvram_type_t type,
1511         __in                    unsigned int offset,
1512         __out_bcount(size)      caddr_t data,
1513         __in                    size_t size);
1514
1515 extern  __checkReturn           efx_rc_t
1516 efx_nvram_read_backup(
1517         __in                    efx_nic_t *enp,
1518         __in                    efx_nvram_type_t type,
1519         __in                    unsigned int offset,
1520         __out_bcount(size)      caddr_t data,
1521         __in                    size_t size);
1522
1523 extern  __checkReturn           efx_rc_t
1524 efx_nvram_set_version(
1525         __in                    efx_nic_t *enp,
1526         __in                    efx_nvram_type_t type,
1527         __in_ecount(4)          uint16_t version[4]);
1528
1529 extern  __checkReturn           efx_rc_t
1530 efx_nvram_validate(
1531         __in                    efx_nic_t *enp,
1532         __in                    efx_nvram_type_t type,
1533         __in_bcount(partn_size) caddr_t partn_data,
1534         __in                    size_t partn_size);
1535
1536 extern   __checkReturn          efx_rc_t
1537 efx_nvram_erase(
1538         __in                    efx_nic_t *enp,
1539         __in                    efx_nvram_type_t type);
1540
1541 extern  __checkReturn           efx_rc_t
1542 efx_nvram_write_chunk(
1543         __in                    efx_nic_t *enp,
1544         __in                    efx_nvram_type_t type,
1545         __in                    unsigned int offset,
1546         __in_bcount(size)       caddr_t data,
1547         __in                    size_t size);
1548
1549 extern                          void
1550 efx_nvram_fini(
1551         __in                    efx_nic_t *enp);
1552
1553 #endif  /* EFSYS_OPT_NVRAM */
1554
1555 #if EFSYS_OPT_BOOTCFG
1556
1557 /* Report size and offset of bootcfg sector in NVRAM partition. */
1558 extern  __checkReturn           efx_rc_t
1559 efx_bootcfg_sector_info(
1560         __in                    efx_nic_t *enp,
1561         __in                    uint32_t pf,
1562         __out_opt               uint32_t *sector_countp,
1563         __out                   size_t *offsetp,
1564         __out                   size_t *max_sizep);
1565
1566 /*
1567  * Copy bootcfg sector data to a target buffer which may differ in size.
1568  * Optionally corrects format errors in source buffer.
1569  */
1570 extern                          efx_rc_t
1571 efx_bootcfg_copy_sector(
1572         __in                    efx_nic_t *enp,
1573         __inout_bcount(sector_length)
1574                                 uint8_t *sector,
1575         __in                    size_t sector_length,
1576         __out_bcount(data_size) uint8_t *data,
1577         __in                    size_t data_size,
1578         __in                    boolean_t handle_format_errors);
1579
1580 extern                          efx_rc_t
1581 efx_bootcfg_read(
1582         __in                    efx_nic_t *enp,
1583         __out_bcount(size)      uint8_t *data,
1584         __in                    size_t size);
1585
1586 extern                          efx_rc_t
1587 efx_bootcfg_write(
1588         __in                    efx_nic_t *enp,
1589         __in_bcount(size)       uint8_t *data,
1590         __in                    size_t size);
1591
1592 #endif  /* EFSYS_OPT_BOOTCFG */
1593
1594 #if EFSYS_OPT_IMAGE_LAYOUT
1595
1596 #include "ef10_signed_image_layout.h"
1597
1598 /*
1599  * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1600  *
1601  * NOTE:
1602  * The image header format is extensible. However, older drivers require an
1603  * exact match of image header version and header length when validating and
1604  * writing firmware images.
1605  *
1606  * To avoid breaking backward compatibility, we use the upper bits of the
1607  * controller version fields to contain an extra version number used for
1608  * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1609  * version). See bug39254 and SF-102785-PS for details.
1610  */
1611 typedef struct efx_image_header_s {
1612         uint32_t        eih_magic;
1613         uint32_t        eih_version;
1614         uint32_t        eih_type;
1615         uint32_t        eih_subtype;
1616         uint32_t        eih_code_size;
1617         uint32_t        eih_size;
1618         union {
1619                 uint32_t        eih_controller_version_min;
1620                 struct {
1621                         uint16_t        eih_controller_version_min_short;
1622                         uint8_t         eih_extra_version_a;
1623                         uint8_t         eih_extra_version_b;
1624                 };
1625         };
1626         union {
1627                 uint32_t        eih_controller_version_max;
1628                 struct {
1629                         uint16_t        eih_controller_version_max_short;
1630                         uint8_t         eih_extra_version_c;
1631                         uint8_t         eih_extra_version_d;
1632                 };
1633         };
1634         uint16_t        eih_code_version_a;
1635         uint16_t        eih_code_version_b;
1636         uint16_t        eih_code_version_c;
1637         uint16_t        eih_code_version_d;
1638 } efx_image_header_t;
1639
1640 #define EFX_IMAGE_HEADER_SIZE           (40)
1641 #define EFX_IMAGE_HEADER_VERSION        (4)
1642 #define EFX_IMAGE_HEADER_MAGIC          (0x106F1A5)
1643
1644
1645 typedef struct efx_image_trailer_s {
1646         uint32_t        eit_crc;
1647 } efx_image_trailer_t;
1648
1649 #define EFX_IMAGE_TRAILER_SIZE          (4)
1650
1651 typedef enum efx_image_format_e {
1652         EFX_IMAGE_FORMAT_NO_IMAGE,
1653         EFX_IMAGE_FORMAT_INVALID,
1654         EFX_IMAGE_FORMAT_UNSIGNED,
1655         EFX_IMAGE_FORMAT_SIGNED,
1656 } efx_image_format_t;
1657
1658 typedef struct efx_image_info_s {
1659         efx_image_format_t      eii_format;
1660         uint8_t *               eii_imagep;
1661         size_t                  eii_image_size;
1662         efx_image_header_t *    eii_headerp;
1663 } efx_image_info_t;
1664
1665 extern  __checkReturn   efx_rc_t
1666 efx_check_reflash_image(
1667         __in            void                    *bufferp,
1668         __in            uint32_t                buffer_size,
1669         __out           efx_image_info_t        *infop);
1670
1671 extern  __checkReturn   efx_rc_t
1672 efx_build_signed_image_write_buffer(
1673         __out           uint8_t                 *bufferp,
1674         __in            uint32_t                buffer_size,
1675         __in            efx_image_info_t        *infop,
1676         __out           efx_image_header_t      **headerpp);
1677
1678 #endif  /* EFSYS_OPT_IMAGE_LAYOUT */
1679
1680 #if EFSYS_OPT_DIAG
1681
1682 typedef enum efx_pattern_type_t {
1683         EFX_PATTERN_BYTE_INCREMENT = 0,
1684         EFX_PATTERN_ALL_THE_SAME,
1685         EFX_PATTERN_BIT_ALTERNATE,
1686         EFX_PATTERN_BYTE_ALTERNATE,
1687         EFX_PATTERN_BYTE_CHANGING,
1688         EFX_PATTERN_BIT_SWEEP,
1689         EFX_PATTERN_NTYPES
1690 } efx_pattern_type_t;
1691
1692 typedef                 void
1693 (*efx_sram_pattern_fn_t)(
1694         __in            size_t row,
1695         __in            boolean_t negate,
1696         __out           efx_qword_t *eqp);
1697
1698 extern  __checkReturn   efx_rc_t
1699 efx_sram_test(
1700         __in            efx_nic_t *enp,
1701         __in            efx_pattern_type_t type);
1702
1703 #endif  /* EFSYS_OPT_DIAG */
1704
1705 extern  __checkReturn   efx_rc_t
1706 efx_sram_buf_tbl_set(
1707         __in            efx_nic_t *enp,
1708         __in            uint32_t id,
1709         __in            efsys_mem_t *esmp,
1710         __in            size_t n);
1711
1712 extern          void
1713 efx_sram_buf_tbl_clear(
1714         __in    efx_nic_t *enp,
1715         __in    uint32_t id,
1716         __in    size_t n);
1717
1718 #define EFX_BUF_TBL_SIZE        0x20000
1719
1720 #define EFX_BUF_SIZE            4096
1721
1722 /* EV */
1723
1724 typedef struct efx_evq_s        efx_evq_t;
1725
1726 #if EFSYS_OPT_QSTATS
1727
1728 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1729 typedef enum efx_ev_qstat_e {
1730         EV_ALL,
1731         EV_RX,
1732         EV_RX_OK,
1733         EV_RX_FRM_TRUNC,
1734         EV_RX_TOBE_DISC,
1735         EV_RX_PAUSE_FRM_ERR,
1736         EV_RX_BUF_OWNER_ID_ERR,
1737         EV_RX_IPV4_HDR_CHKSUM_ERR,
1738         EV_RX_TCP_UDP_CHKSUM_ERR,
1739         EV_RX_ETH_CRC_ERR,
1740         EV_RX_IP_FRAG_ERR,
1741         EV_RX_MCAST_PKT,
1742         EV_RX_MCAST_HASH_MATCH,
1743         EV_RX_TCP_IPV4,
1744         EV_RX_TCP_IPV6,
1745         EV_RX_UDP_IPV4,
1746         EV_RX_UDP_IPV6,
1747         EV_RX_OTHER_IPV4,
1748         EV_RX_OTHER_IPV6,
1749         EV_RX_NON_IP,
1750         EV_RX_BATCH,
1751         EV_TX,
1752         EV_TX_WQ_FF_FULL,
1753         EV_TX_PKT_ERR,
1754         EV_TX_PKT_TOO_BIG,
1755         EV_TX_UNEXPECTED,
1756         EV_GLOBAL,
1757         EV_GLOBAL_MNT,
1758         EV_DRIVER,
1759         EV_DRIVER_SRM_UPD_DONE,
1760         EV_DRIVER_TX_DESCQ_FLS_DONE,
1761         EV_DRIVER_RX_DESCQ_FLS_DONE,
1762         EV_DRIVER_RX_DESCQ_FLS_FAILED,
1763         EV_DRIVER_RX_DSC_ERROR,
1764         EV_DRIVER_TX_DSC_ERROR,
1765         EV_DRV_GEN,
1766         EV_MCDI_RESPONSE,
1767         EV_NQSTATS
1768 } efx_ev_qstat_t;
1769
1770 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1771
1772 #endif  /* EFSYS_OPT_QSTATS */
1773
1774 extern  __checkReturn   efx_rc_t
1775 efx_ev_init(
1776         __in            efx_nic_t *enp);
1777
1778 extern          void
1779 efx_ev_fini(
1780         __in            efx_nic_t *enp);
1781
1782 #define EFX_EVQ_MAXNEVS         32768
1783 #define EFX_EVQ_MINNEVS         512
1784
1785 #define EFX_EVQ_SIZE(_nevs)     ((_nevs) * sizeof (efx_qword_t))
1786 #define EFX_EVQ_NBUFS(_nevs)    (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1787
1788 #define EFX_EVQ_FLAGS_TYPE_MASK         (0x3)
1789 #define EFX_EVQ_FLAGS_TYPE_AUTO         (0x0)
1790 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT   (0x1)
1791 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY  (0x2)
1792
1793 #define EFX_EVQ_FLAGS_NOTIFY_MASK       (0xC)
1794 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT  (0x0)   /* Interrupting (default) */
1795 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED   (0x4)   /* Non-interrupting */
1796
1797 extern  __checkReturn   efx_rc_t
1798 efx_ev_qcreate(
1799         __in            efx_nic_t *enp,
1800         __in            unsigned int index,
1801         __in            efsys_mem_t *esmp,
1802         __in            size_t ndescs,
1803         __in            uint32_t id,
1804         __in            uint32_t us,
1805         __in            uint32_t flags,
1806         __deref_out     efx_evq_t **eepp);
1807
1808 extern          void
1809 efx_ev_qpost(
1810         __in            efx_evq_t *eep,
1811         __in            uint16_t data);
1812
1813 typedef __checkReturn   boolean_t
1814 (*efx_initialized_ev_t)(
1815         __in_opt        void *arg);
1816
1817 #define EFX_PKT_UNICAST         0x0004
1818 #define EFX_PKT_START           0x0008
1819
1820 #define EFX_PKT_VLAN_TAGGED     0x0010
1821 #define EFX_CKSUM_TCPUDP        0x0020
1822 #define EFX_CKSUM_IPV4          0x0040
1823 #define EFX_PKT_CONT            0x0080
1824
1825 #define EFX_CHECK_VLAN          0x0100
1826 #define EFX_PKT_TCP             0x0200
1827 #define EFX_PKT_UDP             0x0400
1828 #define EFX_PKT_IPV4            0x0800
1829
1830 #define EFX_PKT_IPV6            0x1000
1831 #define EFX_PKT_PREFIX_LEN      0x2000
1832 #define EFX_ADDR_MISMATCH       0x4000
1833 #define EFX_DISCARD             0x8000
1834
1835 /*
1836  * The following flags are used only for packed stream
1837  * mode. The values for the flags are reused to fit into 16 bit,
1838  * since EFX_PKT_START and EFX_PKT_CONT are never used in
1839  * packed stream mode
1840  */
1841 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER        EFX_PKT_START
1842 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE  EFX_PKT_CONT
1843
1844
1845 #define EFX_EV_RX_NLABELS       32
1846 #define EFX_EV_TX_NLABELS       32
1847
1848 typedef __checkReturn   boolean_t
1849 (*efx_rx_ev_t)(
1850         __in_opt        void *arg,
1851         __in            uint32_t label,
1852         __in            uint32_t id,
1853         __in            uint32_t size,
1854         __in            uint16_t flags);
1855
1856 #if EFSYS_OPT_RX_PACKED_STREAM
1857
1858 /*
1859  * Packed stream mode is documented in SF-112241-TC.
1860  * The general idea is that, instead of putting each incoming
1861  * packet into a separate buffer which is specified in a RX
1862  * descriptor, a large buffer is provided to the hardware and
1863  * packets are put there in a continuous stream.
1864  * The main advantage of such an approach is that RX queue refilling
1865  * happens much less frequently.
1866  */
1867
1868 typedef __checkReturn   boolean_t
1869 (*efx_rx_ps_ev_t)(
1870         __in_opt        void *arg,
1871         __in            uint32_t label,
1872         __in            uint32_t id,
1873         __in            uint32_t pkt_count,
1874         __in            uint16_t flags);
1875
1876 #endif
1877
1878 typedef __checkReturn   boolean_t
1879 (*efx_tx_ev_t)(
1880         __in_opt        void *arg,
1881         __in            uint32_t label,
1882         __in            uint32_t id);
1883
1884 #define EFX_EXCEPTION_RX_RECOVERY       0x00000001
1885 #define EFX_EXCEPTION_RX_DSC_ERROR      0x00000002
1886 #define EFX_EXCEPTION_TX_DSC_ERROR      0x00000003
1887 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1888 #define EFX_EXCEPTION_FWALERT_SRAM      0x00000005
1889 #define EFX_EXCEPTION_UNKNOWN_FWALERT   0x00000006
1890 #define EFX_EXCEPTION_RX_ERROR          0x00000007
1891 #define EFX_EXCEPTION_TX_ERROR          0x00000008
1892 #define EFX_EXCEPTION_EV_ERROR          0x00000009
1893
1894 typedef __checkReturn   boolean_t
1895 (*efx_exception_ev_t)(
1896         __in_opt        void *arg,
1897         __in            uint32_t label,
1898         __in            uint32_t data);
1899
1900 typedef __checkReturn   boolean_t
1901 (*efx_rxq_flush_done_ev_t)(
1902         __in_opt        void *arg,
1903         __in            uint32_t rxq_index);
1904
1905 typedef __checkReturn   boolean_t
1906 (*efx_rxq_flush_failed_ev_t)(
1907         __in_opt        void *arg,
1908         __in            uint32_t rxq_index);
1909
1910 typedef __checkReturn   boolean_t
1911 (*efx_txq_flush_done_ev_t)(
1912         __in_opt        void *arg,
1913         __in            uint32_t txq_index);
1914
1915 typedef __checkReturn   boolean_t
1916 (*efx_software_ev_t)(
1917         __in_opt        void *arg,
1918         __in            uint16_t magic);
1919
1920 typedef __checkReturn   boolean_t
1921 (*efx_sram_ev_t)(
1922         __in_opt        void *arg,
1923         __in            uint32_t code);
1924
1925 #define EFX_SRAM_CLEAR          0
1926 #define EFX_SRAM_UPDATE         1
1927 #define EFX_SRAM_ILLEGAL_CLEAR  2
1928
1929 typedef __checkReturn   boolean_t
1930 (*efx_wake_up_ev_t)(
1931         __in_opt        void *arg,
1932         __in            uint32_t label);
1933
1934 typedef __checkReturn   boolean_t
1935 (*efx_timer_ev_t)(
1936         __in_opt        void *arg,
1937         __in            uint32_t label);
1938
1939 typedef __checkReturn   boolean_t
1940 (*efx_link_change_ev_t)(
1941         __in_opt        void *arg,
1942         __in            efx_link_mode_t link_mode);
1943
1944 #if EFSYS_OPT_MON_STATS
1945
1946 typedef __checkReturn   boolean_t
1947 (*efx_monitor_ev_t)(
1948         __in_opt        void *arg,
1949         __in            efx_mon_stat_t id,
1950         __in            efx_mon_stat_value_t value);
1951
1952 #endif  /* EFSYS_OPT_MON_STATS */
1953
1954 #if EFSYS_OPT_MAC_STATS
1955
1956 typedef __checkReturn   boolean_t
1957 (*efx_mac_stats_ev_t)(
1958         __in_opt        void *arg,
1959         __in            uint32_t generation);
1960
1961 #endif  /* EFSYS_OPT_MAC_STATS */
1962
1963 typedef struct efx_ev_callbacks_s {
1964         efx_initialized_ev_t            eec_initialized;
1965         efx_rx_ev_t                     eec_rx;
1966 #if EFSYS_OPT_RX_PACKED_STREAM
1967         efx_rx_ps_ev_t                  eec_rx_ps;
1968 #endif
1969         efx_tx_ev_t                     eec_tx;
1970         efx_exception_ev_t              eec_exception;
1971         efx_rxq_flush_done_ev_t         eec_rxq_flush_done;
1972         efx_rxq_flush_failed_ev_t       eec_rxq_flush_failed;
1973         efx_txq_flush_done_ev_t         eec_txq_flush_done;
1974         efx_software_ev_t               eec_software;
1975         efx_sram_ev_t                   eec_sram;
1976         efx_wake_up_ev_t                eec_wake_up;
1977         efx_timer_ev_t                  eec_timer;
1978         efx_link_change_ev_t            eec_link_change;
1979 #if EFSYS_OPT_MON_STATS
1980         efx_monitor_ev_t                eec_monitor;
1981 #endif  /* EFSYS_OPT_MON_STATS */
1982 #if EFSYS_OPT_MAC_STATS
1983         efx_mac_stats_ev_t              eec_mac_stats;
1984 #endif  /* EFSYS_OPT_MAC_STATS */
1985 } efx_ev_callbacks_t;
1986
1987 extern  __checkReturn   boolean_t
1988 efx_ev_qpending(
1989         __in            efx_evq_t *eep,
1990         __in            unsigned int count);
1991
1992 #if EFSYS_OPT_EV_PREFETCH
1993
1994 extern                  void
1995 efx_ev_qprefetch(
1996         __in            efx_evq_t *eep,
1997         __in            unsigned int count);
1998
1999 #endif  /* EFSYS_OPT_EV_PREFETCH */
2000
2001 extern                  void
2002 efx_ev_qpoll(
2003         __in            efx_evq_t *eep,
2004         __inout         unsigned int *countp,
2005         __in            const efx_ev_callbacks_t *eecp,
2006         __in_opt        void *arg);
2007
2008 extern  __checkReturn   efx_rc_t
2009 efx_ev_usecs_to_ticks(
2010         __in            efx_nic_t *enp,
2011         __in            unsigned int usecs,
2012         __out           unsigned int *ticksp);
2013
2014 extern  __checkReturn   efx_rc_t
2015 efx_ev_qmoderate(
2016         __in            efx_evq_t *eep,
2017         __in            unsigned int us);
2018
2019 extern  __checkReturn   efx_rc_t
2020 efx_ev_qprime(
2021         __in            efx_evq_t *eep,
2022         __in            unsigned int count);
2023
2024 #if EFSYS_OPT_QSTATS
2025
2026 #if EFSYS_OPT_NAMES
2027
2028 extern          const char *
2029 efx_ev_qstat_name(
2030         __in    efx_nic_t *enp,
2031         __in    unsigned int id);
2032
2033 #endif  /* EFSYS_OPT_NAMES */
2034
2035 extern                                  void
2036 efx_ev_qstats_update(
2037         __in                            efx_evq_t *eep,
2038         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
2039
2040 #endif  /* EFSYS_OPT_QSTATS */
2041
2042 extern          void
2043 efx_ev_qdestroy(
2044         __in    efx_evq_t *eep);
2045
2046 /* RX */
2047
2048 extern  __checkReturn   efx_rc_t
2049 efx_rx_init(
2050         __inout         efx_nic_t *enp);
2051
2052 extern          void
2053 efx_rx_fini(
2054         __in            efx_nic_t *enp);
2055
2056 #if EFSYS_OPT_RX_SCATTER
2057         __checkReturn   efx_rc_t
2058 efx_rx_scatter_enable(
2059         __in            efx_nic_t *enp,
2060         __in            unsigned int buf_size);
2061 #endif  /* EFSYS_OPT_RX_SCATTER */
2062
2063 /* Handle to represent use of the default RSS context. */
2064 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2065
2066 #if EFSYS_OPT_RX_SCALE
2067
2068 typedef enum efx_rx_hash_alg_e {
2069         EFX_RX_HASHALG_LFSR = 0,
2070         EFX_RX_HASHALG_TOEPLITZ
2071 } efx_rx_hash_alg_t;
2072
2073 /*
2074  * Legacy hash type flags.
2075  *
2076  * They represent standard tuples for distinct traffic classes.
2077  */
2078 #define EFX_RX_HASH_IPV4        (1U << 0)
2079 #define EFX_RX_HASH_TCPIPV4     (1U << 1)
2080 #define EFX_RX_HASH_IPV6        (1U << 2)
2081 #define EFX_RX_HASH_TCPIPV6     (1U << 3)
2082
2083 #define EFX_RX_HASH_LEGACY_MASK         \
2084         (EFX_RX_HASH_IPV4       |       \
2085         EFX_RX_HASH_TCPIPV4     |       \
2086         EFX_RX_HASH_IPV6        |       \
2087         EFX_RX_HASH_TCPIPV6)
2088
2089 /*
2090  * The type of the argument used by efx_rx_scale_mode_set() to
2091  * provide a means for the client drivers to configure hashing.
2092  *
2093  * A properly constructed value can either be:
2094  *  - a combination of legacy flags
2095  *  - a combination of EFX_RX_HASH() flags
2096  */
2097 typedef unsigned int efx_rx_hash_type_t;
2098
2099 typedef enum efx_rx_hash_support_e {
2100         EFX_RX_HASH_UNAVAILABLE = 0,    /* Hardware hash not inserted */
2101         EFX_RX_HASH_AVAILABLE           /* Insert hash with/without RSS */
2102 } efx_rx_hash_support_t;
2103
2104 #define EFX_RSS_KEY_SIZE        40      /* RSS key size (bytes) */
2105 #define EFX_RSS_TBL_SIZE        128     /* Rows in RX indirection table */
2106 #define EFX_MAXRSS              64      /* RX indirection entry range */
2107 #define EFX_MAXRSS_LEGACY       16      /* See bug16611 and bug17213 */
2108
2109 typedef enum efx_rx_scale_context_type_e {
2110         EFX_RX_SCALE_UNAVAILABLE = 0,   /* No RX scale context */
2111         EFX_RX_SCALE_EXCLUSIVE,         /* Writable key/indirection table */
2112         EFX_RX_SCALE_SHARED             /* Read-only key/indirection table */
2113 } efx_rx_scale_context_type_t;
2114
2115 /*
2116  * Traffic classes eligible for hash computation.
2117  *
2118  * Select packet headers used in computing the receive hash.
2119  * This uses the same encoding as the RSS_MODES field of
2120  * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2121  */
2122 #define EFX_RX_CLASS_IPV4_TCP_LBN       8
2123 #define EFX_RX_CLASS_IPV4_TCP_WIDTH     4
2124 #define EFX_RX_CLASS_IPV4_UDP_LBN       12
2125 #define EFX_RX_CLASS_IPV4_UDP_WIDTH     4
2126 #define EFX_RX_CLASS_IPV4_LBN           16
2127 #define EFX_RX_CLASS_IPV4_WIDTH         4
2128 #define EFX_RX_CLASS_IPV6_TCP_LBN       20
2129 #define EFX_RX_CLASS_IPV6_TCP_WIDTH     4
2130 #define EFX_RX_CLASS_IPV6_UDP_LBN       24
2131 #define EFX_RX_CLASS_IPV6_UDP_WIDTH     4
2132 #define EFX_RX_CLASS_IPV6_LBN           28
2133 #define EFX_RX_CLASS_IPV6_WIDTH         4
2134
2135 #define EFX_RX_NCLASSES                 6
2136
2137 /*
2138  * Ancillary flags used to construct generic hash tuples.
2139  * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2140  */
2141 #define EFX_RX_CLASS_HASH_SRC_ADDR      (1U << 0)
2142 #define EFX_RX_CLASS_HASH_DST_ADDR      (1U << 1)
2143 #define EFX_RX_CLASS_HASH_SRC_PORT      (1U << 2)
2144 #define EFX_RX_CLASS_HASH_DST_PORT      (1U << 3)
2145
2146 /*
2147  * Generic hash tuples.
2148  *
2149  * They express combinations of packet fields
2150  * which can contribute to the hash value for
2151  * a particular traffic class.
2152  */
2153 #define EFX_RX_CLASS_HASH_DISABLE       0
2154
2155 #define EFX_RX_CLASS_HASH_1TUPLE_SRC    EFX_RX_CLASS_HASH_SRC_ADDR
2156 #define EFX_RX_CLASS_HASH_1TUPLE_DST    EFX_RX_CLASS_HASH_DST_ADDR
2157
2158 #define EFX_RX_CLASS_HASH_2TUPLE                \
2159         (EFX_RX_CLASS_HASH_SRC_ADDR     |       \
2160         EFX_RX_CLASS_HASH_DST_ADDR)
2161
2162 #define EFX_RX_CLASS_HASH_2TUPLE_SRC            \
2163         (EFX_RX_CLASS_HASH_SRC_ADDR     |       \
2164         EFX_RX_CLASS_HASH_SRC_PORT)
2165
2166 #define EFX_RX_CLASS_HASH_2TUPLE_DST            \
2167         (EFX_RX_CLASS_HASH_DST_ADDR     |       \
2168         EFX_RX_CLASS_HASH_DST_PORT)
2169
2170 #define EFX_RX_CLASS_HASH_4TUPLE                \
2171         (EFX_RX_CLASS_HASH_SRC_ADDR     |       \
2172         EFX_RX_CLASS_HASH_DST_ADDR      |       \
2173         EFX_RX_CLASS_HASH_SRC_PORT      |       \
2174         EFX_RX_CLASS_HASH_DST_PORT)
2175
2176 #define EFX_RX_CLASS_HASH_NTUPLES       7
2177
2178 /*
2179  * Hash flag constructor.
2180  *
2181  * Resulting flags encode hash tuples for specific traffic classes.
2182  * The client drivers are encouraged to use these flags to form
2183  * a hash type value.
2184  */
2185 #define EFX_RX_HASH(_class, _tuple)                             \
2186         EFX_INSERT_FIELD_NATIVE32(0, 31,                        \
2187         EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2188
2189 /*
2190  * The maximum number of EFX_RX_HASH() flags.
2191  */
2192 #define EFX_RX_HASH_NFLAGS      (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2193
2194 extern  __checkReturn                           efx_rc_t
2195 efx_rx_scale_hash_flags_get(
2196         __in                                    efx_nic_t *enp,
2197         __in                                    efx_rx_hash_alg_t hash_alg,
2198         __inout_ecount(EFX_RX_HASH_NFLAGS)      unsigned int *flags,
2199         __out                                   unsigned int *nflagsp);
2200
2201 extern  __checkReturn   efx_rc_t
2202 efx_rx_hash_default_support_get(
2203         __in            efx_nic_t *enp,
2204         __out           efx_rx_hash_support_t *supportp);
2205
2206
2207 extern  __checkReturn   efx_rc_t
2208 efx_rx_scale_default_support_get(
2209         __in            efx_nic_t *enp,
2210         __out           efx_rx_scale_context_type_t *typep);
2211
2212 extern  __checkReturn   efx_rc_t
2213 efx_rx_scale_context_alloc(
2214         __in            efx_nic_t *enp,
2215         __in            efx_rx_scale_context_type_t type,
2216         __in            uint32_t num_queues,
2217         __out           uint32_t *rss_contextp);
2218
2219 extern  __checkReturn   efx_rc_t
2220 efx_rx_scale_context_free(
2221         __in            efx_nic_t *enp,
2222         __in            uint32_t rss_context);
2223
2224 extern  __checkReturn   efx_rc_t
2225 efx_rx_scale_mode_set(
2226         __in    efx_nic_t *enp,
2227         __in    uint32_t rss_context,
2228         __in    efx_rx_hash_alg_t alg,
2229         __in    efx_rx_hash_type_t type,
2230         __in    boolean_t insert);
2231
2232 extern  __checkReturn   efx_rc_t
2233 efx_rx_scale_tbl_set(
2234         __in            efx_nic_t *enp,
2235         __in            uint32_t rss_context,
2236         __in_ecount(n)  unsigned int *table,
2237         __in            size_t n);
2238
2239 extern  __checkReturn   efx_rc_t
2240 efx_rx_scale_key_set(
2241         __in            efx_nic_t *enp,
2242         __in            uint32_t rss_context,
2243         __in_ecount(n)  uint8_t *key,
2244         __in            size_t n);
2245
2246 extern  __checkReturn   uint32_t
2247 efx_pseudo_hdr_hash_get(
2248         __in            efx_rxq_t *erp,
2249         __in            efx_rx_hash_alg_t func,
2250         __in            uint8_t *buffer);
2251
2252 #endif  /* EFSYS_OPT_RX_SCALE */
2253
2254 extern  __checkReturn   efx_rc_t
2255 efx_pseudo_hdr_pkt_length_get(
2256         __in            efx_rxq_t *erp,
2257         __in            uint8_t *buffer,
2258         __out           uint16_t *pkt_lengthp);
2259
2260 #define EFX_RXQ_MAXNDESCS               4096
2261 #define EFX_RXQ_MINNDESCS               512
2262
2263 #define EFX_RXQ_SIZE(_ndescs)           ((_ndescs) * sizeof (efx_qword_t))
2264 #define EFX_RXQ_NBUFS(_ndescs)          (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2265 #define EFX_RXQ_LIMIT(_ndescs)          ((_ndescs) - 16)
2266 #define EFX_RXQ_DC_NDESCS(_dcsize)      (8 << _dcsize)
2267
2268 typedef enum efx_rxq_type_e {
2269         EFX_RXQ_TYPE_DEFAULT,
2270         EFX_RXQ_TYPE_PACKED_STREAM,
2271         EFX_RXQ_NTYPES
2272 } efx_rxq_type_t;
2273
2274 /*
2275  * Dummy flag to be used instead of 0 to make it clear that the argument
2276  * is receive queue flags.
2277  */
2278 #define EFX_RXQ_FLAG_NONE               0x0
2279 #define EFX_RXQ_FLAG_SCATTER            0x1
2280 /*
2281  * If tunnels are supported and Rx event can provide information about
2282  * either outer or inner packet classes (e.g. SFN8xxx adapters with
2283  * full-feature firmware variant running), outer classes are requested by
2284  * default. However, if the driver supports tunnels, the flag allows to
2285  * request inner classes which are required to be able to interpret inner
2286  * Rx checksum offload results.
2287  */
2288 #define EFX_RXQ_FLAG_INNER_CLASSES      0x2
2289
2290 extern  __checkReturn   efx_rc_t
2291 efx_rx_qcreate(
2292         __in            efx_nic_t *enp,
2293         __in            unsigned int index,
2294         __in            unsigned int label,
2295         __in            efx_rxq_type_t type,
2296         __in            efsys_mem_t *esmp,
2297         __in            size_t ndescs,
2298         __in            uint32_t id,
2299         __in            unsigned int flags,
2300         __in            efx_evq_t *eep,
2301         __deref_out     efx_rxq_t **erpp);
2302
2303 #if EFSYS_OPT_RX_PACKED_STREAM
2304
2305 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M       (1U * 1024 * 1024)
2306 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K     (512U * 1024)
2307 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K     (256U * 1024)
2308 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K     (128U * 1024)
2309 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K      (64U * 1024)
2310
2311 extern  __checkReturn   efx_rc_t
2312 efx_rx_qcreate_packed_stream(
2313         __in            efx_nic_t *enp,
2314         __in            unsigned int index,
2315         __in            unsigned int label,
2316         __in            uint32_t ps_buf_size,
2317         __in            efsys_mem_t *esmp,
2318         __in            size_t ndescs,
2319         __in            efx_evq_t *eep,
2320         __deref_out     efx_rxq_t **erpp);
2321
2322 #endif
2323
2324 typedef struct efx_buffer_s {
2325         efsys_dma_addr_t        eb_addr;
2326         size_t                  eb_size;
2327         boolean_t               eb_eop;
2328 } efx_buffer_t;
2329
2330 typedef struct efx_desc_s {
2331         efx_qword_t ed_eq;
2332 } efx_desc_t;
2333
2334 extern                          void
2335 efx_rx_qpost(
2336         __in                    efx_rxq_t *erp,
2337         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
2338         __in                    size_t size,
2339         __in                    unsigned int ndescs,
2340         __in                    unsigned int completed,
2341         __in                    unsigned int added);
2342
2343 extern          void
2344 efx_rx_qpush(
2345         __in    efx_rxq_t *erp,
2346         __in    unsigned int added,
2347         __inout unsigned int *pushedp);
2348
2349 #if EFSYS_OPT_RX_PACKED_STREAM
2350
2351 extern                  void
2352 efx_rx_qpush_ps_credits(
2353         __in            efx_rxq_t *erp);
2354
2355 extern  __checkReturn   uint8_t *
2356 efx_rx_qps_packet_info(
2357         __in            efx_rxq_t *erp,
2358         __in            uint8_t *buffer,
2359         __in            uint32_t buffer_length,
2360         __in            uint32_t current_offset,
2361         __out           uint16_t *lengthp,
2362         __out           uint32_t *next_offsetp,
2363         __out           uint32_t *timestamp);
2364 #endif
2365
2366 extern  __checkReturn   efx_rc_t
2367 efx_rx_qflush(
2368         __in    efx_rxq_t *erp);
2369
2370 extern          void
2371 efx_rx_qenable(
2372         __in    efx_rxq_t *erp);
2373
2374 extern          void
2375 efx_rx_qdestroy(
2376         __in    efx_rxq_t *erp);
2377
2378 /* TX */
2379
2380 typedef struct efx_txq_s        efx_txq_t;
2381
2382 #if EFSYS_OPT_QSTATS
2383
2384 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2385 typedef enum efx_tx_qstat_e {
2386         TX_POST,
2387         TX_POST_PIO,
2388         TX_NQSTATS
2389 } efx_tx_qstat_t;
2390
2391 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2392
2393 #endif  /* EFSYS_OPT_QSTATS */
2394
2395 extern  __checkReturn   efx_rc_t
2396 efx_tx_init(
2397         __in            efx_nic_t *enp);
2398
2399 extern          void
2400 efx_tx_fini(
2401         __in    efx_nic_t *enp);
2402
2403 #define EFX_TXQ_MINNDESCS               512
2404
2405 #define EFX_TXQ_SIZE(_ndescs)           ((_ndescs) * sizeof (efx_qword_t))
2406 #define EFX_TXQ_NBUFS(_ndescs)          (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2407 #define EFX_TXQ_LIMIT(_ndescs)          ((_ndescs) - 16)
2408
2409 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2410
2411 #define EFX_TXQ_CKSUM_IPV4              0x0001
2412 #define EFX_TXQ_CKSUM_TCPUDP            0x0002
2413 #define EFX_TXQ_FATSOV2                 0x0004
2414 #define EFX_TXQ_CKSUM_INNER_IPV4        0x0008
2415 #define EFX_TXQ_CKSUM_INNER_TCPUDP      0x0010
2416
2417 extern  __checkReturn   efx_rc_t
2418 efx_tx_qcreate(
2419         __in            efx_nic_t *enp,
2420         __in            unsigned int index,
2421         __in            unsigned int label,
2422         __in            efsys_mem_t *esmp,
2423         __in            size_t n,
2424         __in            uint32_t id,
2425         __in            uint16_t flags,
2426         __in            efx_evq_t *eep,
2427         __deref_out     efx_txq_t **etpp,
2428         __out           unsigned int *addedp);
2429
2430 extern  __checkReturn           efx_rc_t
2431 efx_tx_qpost(
2432         __in                    efx_txq_t *etp,
2433         __in_ecount(ndescs)     efx_buffer_t *eb,
2434         __in                    unsigned int ndescs,
2435         __in                    unsigned int completed,
2436         __inout                 unsigned int *addedp);
2437
2438 extern  __checkReturn   efx_rc_t
2439 efx_tx_qpace(
2440         __in            efx_txq_t *etp,
2441         __in            unsigned int ns);
2442
2443 extern                  void
2444 efx_tx_qpush(
2445         __in            efx_txq_t *etp,
2446         __in            unsigned int added,
2447         __in            unsigned int pushed);
2448
2449 extern  __checkReturn   efx_rc_t
2450 efx_tx_qflush(
2451         __in            efx_txq_t *etp);
2452
2453 extern                  void
2454 efx_tx_qenable(
2455         __in            efx_txq_t *etp);
2456
2457 extern  __checkReturn   efx_rc_t
2458 efx_tx_qpio_enable(
2459         __in            efx_txq_t *etp);
2460
2461 extern                  void
2462 efx_tx_qpio_disable(
2463         __in            efx_txq_t *etp);
2464
2465 extern  __checkReturn   efx_rc_t
2466 efx_tx_qpio_write(
2467         __in                    efx_txq_t *etp,
2468         __in_ecount(buf_length) uint8_t *buffer,
2469         __in                    size_t buf_length,
2470         __in                    size_t pio_buf_offset);
2471
2472 extern  __checkReturn   efx_rc_t
2473 efx_tx_qpio_post(
2474         __in                    efx_txq_t *etp,
2475         __in                    size_t pkt_length,
2476         __in                    unsigned int completed,
2477         __inout                 unsigned int *addedp);
2478
2479 extern  __checkReturn   efx_rc_t
2480 efx_tx_qdesc_post(
2481         __in            efx_txq_t *etp,
2482         __in_ecount(n)  efx_desc_t *ed,
2483         __in            unsigned int n,
2484         __in            unsigned int completed,
2485         __inout         unsigned int *addedp);
2486
2487 extern  void
2488 efx_tx_qdesc_dma_create(
2489         __in    efx_txq_t *etp,
2490         __in    efsys_dma_addr_t addr,
2491         __in    size_t size,
2492         __in    boolean_t eop,
2493         __out   efx_desc_t *edp);
2494
2495 extern  void
2496 efx_tx_qdesc_tso_create(
2497         __in    efx_txq_t *etp,
2498         __in    uint16_t ipv4_id,
2499         __in    uint32_t tcp_seq,
2500         __in    uint8_t  tcp_flags,
2501         __out   efx_desc_t *edp);
2502
2503 /* Number of FATSOv2 option descriptors */
2504 #define EFX_TX_FATSOV2_OPT_NDESCS               2
2505
2506 /* Maximum number of DMA segments per TSO packet (not superframe) */
2507 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX     24
2508
2509 extern  void
2510 efx_tx_qdesc_tso2_create(
2511         __in                    efx_txq_t *etp,
2512         __in                    uint16_t ipv4_id,
2513         __in                    uint16_t outer_ipv4_id,
2514         __in                    uint32_t tcp_seq,
2515         __in                    uint16_t tcp_mss,
2516         __out_ecount(count)     efx_desc_t *edp,
2517         __in                    int count);
2518
2519 extern  void
2520 efx_tx_qdesc_vlantci_create(
2521         __in    efx_txq_t *etp,
2522         __in    uint16_t tci,
2523         __out   efx_desc_t *edp);
2524
2525 extern  void
2526 efx_tx_qdesc_checksum_create(
2527         __in    efx_txq_t *etp,
2528         __in    uint16_t flags,
2529         __out   efx_desc_t *edp);
2530
2531 #if EFSYS_OPT_QSTATS
2532
2533 #if EFSYS_OPT_NAMES
2534
2535 extern          const char *
2536 efx_tx_qstat_name(
2537         __in    efx_nic_t *etp,
2538         __in    unsigned int id);
2539
2540 #endif  /* EFSYS_OPT_NAMES */
2541
2542 extern                                  void
2543 efx_tx_qstats_update(
2544         __in                            efx_txq_t *etp,
2545         __inout_ecount(TX_NQSTATS)      efsys_stat_t *stat);
2546
2547 #endif  /* EFSYS_OPT_QSTATS */
2548
2549 extern          void
2550 efx_tx_qdestroy(
2551         __in    efx_txq_t *etp);
2552
2553
2554 /* FILTER */
2555
2556 #if EFSYS_OPT_FILTER
2557
2558 #define EFX_ETHER_TYPE_IPV4 0x0800
2559 #define EFX_ETHER_TYPE_IPV6 0x86DD
2560
2561 #define EFX_IPPROTO_TCP 6
2562 #define EFX_IPPROTO_UDP 17
2563 #define EFX_IPPROTO_GRE 47
2564
2565 /* Use RSS to spread across multiple queues */
2566 #define EFX_FILTER_FLAG_RX_RSS          0x01
2567 /* Enable RX scatter */
2568 #define EFX_FILTER_FLAG_RX_SCATTER      0x02
2569 /*
2570  * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2571  * May only be set by the filter implementation for each type.
2572  * A removal request will restore the automatic filter in its place.
2573  */
2574 #define EFX_FILTER_FLAG_RX_OVER_AUTO    0x04
2575 /* Filter is for RX */
2576 #define EFX_FILTER_FLAG_RX              0x08
2577 /* Filter is for TX */
2578 #define EFX_FILTER_FLAG_TX              0x10
2579
2580 typedef uint8_t efx_filter_flags_t;
2581
2582 /*
2583  * Flags which specify the fields to match on. The values are the same as in the
2584  * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2585  */
2586
2587 /* Match by remote IP host address */
2588 #define EFX_FILTER_MATCH_REM_HOST               0x00000001
2589 /* Match by local IP host address */
2590 #define EFX_FILTER_MATCH_LOC_HOST               0x00000002
2591 /* Match by remote MAC address */
2592 #define EFX_FILTER_MATCH_REM_MAC                0x00000004
2593 /* Match by remote TCP/UDP port */
2594 #define EFX_FILTER_MATCH_REM_PORT               0x00000008
2595 /* Match by remote TCP/UDP port */
2596 #define EFX_FILTER_MATCH_LOC_MAC                0x00000010
2597 /* Match by local TCP/UDP port */
2598 #define EFX_FILTER_MATCH_LOC_PORT               0x00000020
2599 /* Match by Ether-type */
2600 #define EFX_FILTER_MATCH_ETHER_TYPE             0x00000040
2601 /* Match by inner VLAN ID */
2602 #define EFX_FILTER_MATCH_INNER_VID              0x00000080
2603 /* Match by outer VLAN ID */
2604 #define EFX_FILTER_MATCH_OUTER_VID              0x00000100
2605 /* Match by IP transport protocol */
2606 #define EFX_FILTER_MATCH_IP_PROTO               0x00000200
2607 /* Match by VNI or VSID */
2608 #define EFX_FILTER_MATCH_VNI_OR_VSID            0x00000800
2609 /* For encapsulated packets, match by inner frame local MAC address */
2610 #define EFX_FILTER_MATCH_IFRM_LOC_MAC           0x00010000
2611 /* For encapsulated packets, match all multicast inner frames */
2612 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2613 /* For encapsulated packets, match all unicast inner frames */
2614 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2615 /*
2616  * Match by encap type, this flag does not correspond to
2617  * the MCDI match flags and any unoccupied value may be used
2618  */
2619 #define EFX_FILTER_MATCH_ENCAP_TYPE             0x20000000
2620 /* Match otherwise-unmatched multicast and broadcast packets */
2621 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST      0x40000000
2622 /* Match otherwise-unmatched unicast packets */
2623 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST      0x80000000
2624
2625 typedef uint32_t efx_filter_match_flags_t;
2626
2627 typedef enum efx_filter_priority_s {
2628         EFX_FILTER_PRI_HINT = 0,        /* Performance hint */
2629         EFX_FILTER_PRI_AUTO,            /* Automatic filter based on device
2630                                          * address list or hardware
2631                                          * requirements. This may only be used
2632                                          * by the filter implementation for
2633                                          * each NIC type. */
2634         EFX_FILTER_PRI_MANUAL,          /* Manually configured filter */
2635         EFX_FILTER_PRI_REQUIRED,        /* Required for correct behaviour of the
2636                                          * client (e.g. SR-IOV, HyperV VMQ etc.)
2637                                          */
2638 } efx_filter_priority_t;
2639
2640 /*
2641  * FIXME: All these fields are assumed to be in little-endian byte order.
2642  * It may be better for some to be big-endian. See bug42804.
2643  */
2644
2645 typedef struct efx_filter_spec_s {
2646         efx_filter_match_flags_t        efs_match_flags;
2647         uint8_t                         efs_priority;
2648         efx_filter_flags_t              efs_flags;
2649         uint16_t                        efs_dmaq_id;
2650         uint32_t                        efs_rss_context;
2651         uint16_t                        efs_outer_vid;
2652         uint16_t                        efs_inner_vid;
2653         uint8_t                         efs_loc_mac[EFX_MAC_ADDR_LEN];
2654         uint8_t                         efs_rem_mac[EFX_MAC_ADDR_LEN];
2655         uint16_t                        efs_ether_type;
2656         uint8_t                         efs_ip_proto;
2657         efx_tunnel_protocol_t           efs_encap_type;
2658         uint16_t                        efs_loc_port;
2659         uint16_t                        efs_rem_port;
2660         efx_oword_t                     efs_rem_host;
2661         efx_oword_t                     efs_loc_host;
2662         uint8_t                         efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2663         uint8_t                         efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2664 } efx_filter_spec_t;
2665
2666
2667 /* Default values for use in filter specifications */
2668 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP         0xfff
2669 #define EFX_FILTER_SPEC_VID_UNSPEC              0xffff
2670
2671 extern  __checkReturn   efx_rc_t
2672 efx_filter_init(
2673         __in            efx_nic_t *enp);
2674
2675 extern                  void
2676 efx_filter_fini(
2677         __in            efx_nic_t *enp);
2678
2679 extern  __checkReturn   efx_rc_t
2680 efx_filter_insert(
2681         __in            efx_nic_t *enp,
2682         __inout         efx_filter_spec_t *spec);
2683
2684 extern  __checkReturn   efx_rc_t
2685 efx_filter_remove(
2686         __in            efx_nic_t *enp,
2687         __inout         efx_filter_spec_t *spec);
2688
2689 extern  __checkReturn   efx_rc_t
2690 efx_filter_restore(
2691         __in            efx_nic_t *enp);
2692
2693 extern  __checkReturn   efx_rc_t
2694 efx_filter_supported_filters(
2695         __in                            efx_nic_t *enp,
2696         __out_ecount(buffer_length)     uint32_t *buffer,
2697         __in                            size_t buffer_length,
2698         __out                           size_t *list_lengthp);
2699
2700 extern                  void
2701 efx_filter_spec_init_rx(
2702         __out           efx_filter_spec_t *spec,
2703         __in            efx_filter_priority_t priority,
2704         __in            efx_filter_flags_t flags,
2705         __in            efx_rxq_t *erp);
2706
2707 extern                  void
2708 efx_filter_spec_init_tx(
2709         __out           efx_filter_spec_t *spec,
2710         __in            efx_txq_t *etp);
2711
2712 extern  __checkReturn   efx_rc_t
2713 efx_filter_spec_set_ipv4_local(
2714         __inout         efx_filter_spec_t *spec,
2715         __in            uint8_t proto,
2716         __in            uint32_t host,
2717         __in            uint16_t port);
2718
2719 extern  __checkReturn   efx_rc_t
2720 efx_filter_spec_set_ipv4_full(
2721         __inout         efx_filter_spec_t *spec,
2722         __in            uint8_t proto,
2723         __in            uint32_t lhost,
2724         __in            uint16_t lport,
2725         __in            uint32_t rhost,
2726         __in            uint16_t rport);
2727
2728 extern  __checkReturn   efx_rc_t
2729 efx_filter_spec_set_eth_local(
2730         __inout         efx_filter_spec_t *spec,
2731         __in            uint16_t vid,
2732         __in            const uint8_t *addr);
2733
2734 extern                  void
2735 efx_filter_spec_set_ether_type(
2736         __inout         efx_filter_spec_t *spec,
2737         __in            uint16_t ether_type);
2738
2739 extern  __checkReturn   efx_rc_t
2740 efx_filter_spec_set_uc_def(
2741         __inout         efx_filter_spec_t *spec);
2742
2743 extern  __checkReturn   efx_rc_t
2744 efx_filter_spec_set_mc_def(
2745         __inout         efx_filter_spec_t *spec);
2746
2747 typedef enum efx_filter_inner_frame_match_e {
2748         EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2749         EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2750         EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2751 } efx_filter_inner_frame_match_t;
2752
2753 extern  __checkReturn   efx_rc_t
2754 efx_filter_spec_set_encap_type(
2755         __inout         efx_filter_spec_t *spec,
2756         __in            efx_tunnel_protocol_t encap_type,
2757         __in            efx_filter_inner_frame_match_t inner_frame_match);
2758
2759 extern  __checkReturn   efx_rc_t
2760 efx_filter_spec_set_vxlan_full(
2761         __inout         efx_filter_spec_t *spec,
2762         __in            const uint8_t *vxlan_id,
2763         __in            const uint8_t *inner_addr,
2764         __in            const uint8_t *outer_addr);
2765
2766 #if EFSYS_OPT_RX_SCALE
2767 extern  __checkReturn   efx_rc_t
2768 efx_filter_spec_set_rss_context(
2769         __inout         efx_filter_spec_t *spec,
2770         __in            uint32_t rss_context);
2771 #endif
2772 #endif  /* EFSYS_OPT_FILTER */
2773
2774 /* HASH */
2775
2776 extern  __checkReturn           uint32_t
2777 efx_hash_dwords(
2778         __in_ecount(count)      uint32_t const *input,
2779         __in                    size_t count,
2780         __in                    uint32_t init);
2781
2782 extern  __checkReturn           uint32_t
2783 efx_hash_bytes(
2784         __in_ecount(length)     uint8_t const *input,
2785         __in                    size_t length,
2786         __in                    uint32_t init);
2787
2788 #if EFSYS_OPT_LICENSING
2789
2790 /* LICENSING */
2791
2792 typedef struct efx_key_stats_s {
2793         uint32_t        eks_valid;
2794         uint32_t        eks_invalid;
2795         uint32_t        eks_blacklisted;
2796         uint32_t        eks_unverifiable;
2797         uint32_t        eks_wrong_node;
2798         uint32_t        eks_licensed_apps_lo;
2799         uint32_t        eks_licensed_apps_hi;
2800         uint32_t        eks_licensed_features_lo;
2801         uint32_t        eks_licensed_features_hi;
2802 } efx_key_stats_t;
2803
2804 extern  __checkReturn           efx_rc_t
2805 efx_lic_init(
2806         __in                    efx_nic_t *enp);
2807
2808 extern                          void
2809 efx_lic_fini(
2810         __in                    efx_nic_t *enp);
2811
2812 extern  __checkReturn   boolean_t
2813 efx_lic_check_support(
2814         __in                    efx_nic_t *enp);
2815
2816 extern  __checkReturn   efx_rc_t
2817 efx_lic_update_licenses(
2818         __in            efx_nic_t *enp);
2819
2820 extern  __checkReturn   efx_rc_t
2821 efx_lic_get_key_stats(
2822         __in            efx_nic_t *enp,
2823         __out           efx_key_stats_t *ksp);
2824
2825 extern  __checkReturn   efx_rc_t
2826 efx_lic_app_state(
2827         __in            efx_nic_t *enp,
2828         __in            uint64_t app_id,
2829         __out           boolean_t *licensedp);
2830
2831 extern  __checkReturn   efx_rc_t
2832 efx_lic_get_id(
2833         __in            efx_nic_t *enp,
2834         __in            size_t buffer_size,
2835         __out           uint32_t *typep,
2836         __out           size_t *lengthp,
2837         __out_opt       uint8_t *bufferp);
2838
2839
2840 extern  __checkReturn           efx_rc_t
2841 efx_lic_find_start(
2842         __in                    efx_nic_t *enp,
2843         __in_bcount(buffer_size)
2844                                 caddr_t bufferp,
2845         __in                    size_t buffer_size,
2846         __out                   uint32_t *startp);
2847
2848 extern  __checkReturn           efx_rc_t
2849 efx_lic_find_end(
2850         __in                    efx_nic_t *enp,
2851         __in_bcount(buffer_size)
2852                                 caddr_t bufferp,
2853         __in                    size_t buffer_size,
2854         __in                    uint32_t offset,
2855         __out                   uint32_t *endp);
2856
2857 extern  __checkReturn   __success(return != B_FALSE)    boolean_t
2858 efx_lic_find_key(
2859         __in                    efx_nic_t *enp,
2860         __in_bcount(buffer_size)
2861                                 caddr_t bufferp,
2862         __in                    size_t buffer_size,
2863         __in                    uint32_t offset,
2864         __out                   uint32_t *startp,
2865         __out                   uint32_t *lengthp);
2866
2867 extern  __checkReturn   __success(return != B_FALSE)    boolean_t
2868 efx_lic_validate_key(
2869         __in                    efx_nic_t *enp,
2870         __in_bcount(length)     caddr_t keyp,
2871         __in                    uint32_t length);
2872
2873 extern  __checkReturn           efx_rc_t
2874 efx_lic_read_key(
2875         __in                    efx_nic_t *enp,
2876         __in_bcount(buffer_size)
2877                                 caddr_t bufferp,
2878         __in                    size_t buffer_size,
2879         __in                    uint32_t offset,
2880         __in                    uint32_t length,
2881         __out_bcount_part(key_max_size, *lengthp)
2882                                 caddr_t keyp,
2883         __in                    size_t key_max_size,
2884         __out                   uint32_t *lengthp);
2885
2886 extern  __checkReturn           efx_rc_t
2887 efx_lic_write_key(
2888         __in                    efx_nic_t *enp,
2889         __in_bcount(buffer_size)
2890                                 caddr_t bufferp,
2891         __in                    size_t buffer_size,
2892         __in                    uint32_t offset,
2893         __in_bcount(length)     caddr_t keyp,
2894         __in                    uint32_t length,
2895         __out                   uint32_t *lengthp);
2896
2897         __checkReturn           efx_rc_t
2898 efx_lic_delete_key(
2899         __in                    efx_nic_t *enp,
2900         __in_bcount(buffer_size)
2901                                 caddr_t bufferp,
2902         __in                    size_t buffer_size,
2903         __in                    uint32_t offset,
2904         __in                    uint32_t length,
2905         __in                    uint32_t end,
2906         __out                   uint32_t *deltap);
2907
2908 extern  __checkReturn           efx_rc_t
2909 efx_lic_create_partition(
2910         __in                    efx_nic_t *enp,
2911         __in_bcount(buffer_size)
2912                                 caddr_t bufferp,
2913         __in                    size_t buffer_size);
2914
2915 extern  __checkReturn           efx_rc_t
2916 efx_lic_finish_partition(
2917         __in                    efx_nic_t *enp,
2918         __in_bcount(buffer_size)
2919                                 caddr_t bufferp,
2920         __in                    size_t buffer_size);
2921
2922 #endif  /* EFSYS_OPT_LICENSING */
2923
2924 /* TUNNEL */
2925
2926 #if EFSYS_OPT_TUNNEL
2927
2928 extern  __checkReturn   efx_rc_t
2929 efx_tunnel_init(
2930         __in            efx_nic_t *enp);
2931
2932 extern                  void
2933 efx_tunnel_fini(
2934         __in            efx_nic_t *enp);
2935
2936 /*
2937  * For overlay network encapsulation using UDP, the firmware needs to know
2938  * the configured UDP port for the overlay so it can decode encapsulated
2939  * frames correctly.
2940  * The UDP port/protocol list is global.
2941  */
2942
2943 extern  __checkReturn   efx_rc_t
2944 efx_tunnel_config_udp_add(
2945         __in            efx_nic_t *enp,
2946         __in            uint16_t port /* host/cpu-endian */,
2947         __in            efx_tunnel_protocol_t protocol);
2948
2949 extern  __checkReturn   efx_rc_t
2950 efx_tunnel_config_udp_remove(
2951         __in            efx_nic_t *enp,
2952         __in            uint16_t port /* host/cpu-endian */,
2953         __in            efx_tunnel_protocol_t protocol);
2954
2955 extern                  void
2956 efx_tunnel_config_clear(
2957         __in            efx_nic_t *enp);
2958
2959 /**
2960  * Apply tunnel UDP ports configuration to hardware.
2961  *
2962  * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2963  * reboot).
2964  */
2965 extern  __checkReturn   efx_rc_t
2966 efx_tunnel_reconfigure(
2967         __in            efx_nic_t *enp);
2968
2969 #endif /* EFSYS_OPT_TUNNEL */
2970
2971 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2972
2973 /**
2974  * Firmware subvariant choice options.
2975  *
2976  * It may be switched to no Tx checksum if attached drivers are either
2977  * preboot or firmware subvariant aware and no VIS are allocated.
2978  * If may be always switched to default explicitly using set request or
2979  * implicitly if unaware driver is attaching. If switching is done when
2980  * a driver is attached, it gets MC_REBOOT event and should recreate its
2981  * datapath.
2982  *
2983  * See SF-119419-TC DPDK Firmware Driver Interface and
2984  * SF-109306-TC EF10 for Driver Writers for details.
2985  */
2986 typedef enum efx_nic_fw_subvariant_e {
2987         EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
2988         EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
2989         EFX_NIC_FW_SUBVARIANT_NTYPES
2990 } efx_nic_fw_subvariant_t;
2991
2992 extern  __checkReturn   efx_rc_t
2993 efx_nic_get_fw_subvariant(
2994         __in            efx_nic_t *enp,
2995         __out           efx_nic_fw_subvariant_t *subvariantp);
2996
2997 extern  __checkReturn   efx_rc_t
2998 efx_nic_set_fw_subvariant(
2999         __in            efx_nic_t *enp,
3000         __in            efx_nic_fw_subvariant_t subvariant);
3001
3002 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3003
3004 #ifdef  __cplusplus
3005 }
3006 #endif
3007
3008 #endif  /* _SYS_EFX_H */